drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62 #include "bnx2x.h"
  63 #include "bnx2x_init.h"
  64 #include "bnx2x_init_ops.h"
  65 #include "bnx2x_cmn.h"
  66 #include "bnx2x_vfpf.h"
  67 #include "bnx2x_dcb.h"
  68 #include "bnx2x_sp.h"
  69 #include <linux/firmware.h>
  70 #include "bnx2x_fw_file_hdr.h"
  71 /* FW files */
  72 /*(DEBLOBBED)*/
  73 #define FW_FILE_NAME_E1         "/*(DEBLOBBED)*/"
  74 #define FW_FILE_NAME_E1H        "/*(DEBLOBBED)*/"
  75 #define FW_FILE_NAME_E2         "/*(DEBLOBBED)*/"
  76 #define bnx2x_init_block(bp, start, end) \
  77   return (printk(KERN_ERR "%s: Missing Free firmware\n", bp->dev->name),\
  78           -EINVAL)
  79
  80 /* Time in jiffies before concluding the transmitter is hung */
  81 #define TX_TIMEOUT              (5*HZ)
  82
  83 static char version[] =
  84         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  86
  87 MODULE_AUTHOR("Eliezer Tamir");
  88 MODULE_DESCRIPTION("QLogic "
  89                    "BCM57710/57711/57711E/"
  90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  91                    "57840/57840_MF Driver");
  92 MODULE_LICENSE("GPL");
  93 MODULE_VERSION(DRV_MODULE_VERSION);
  94 /*(DEBLOBBED)*/
  95
  96 int bnx2x_num_queues;
  97 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  98 MODULE_PARM_DESC(num_queues,
  99                  " Set number of queues (default is as a number of CPUs)");
 100
 101 static int disable_tpa;
 102 module_param(disable_tpa, int, S_IRUGO);
 103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 104
 105 static int int_mode;
 106 module_param(int_mode, int, S_IRUGO);
 107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 108                                 "(1 INT#x; 2 MSI)");
 109
 110 static int dropless_fc;
 111 module_param(dropless_fc, int, S_IRUGO);
 112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 113
 114 static int mrrs = -1;
 115 module_param(mrrs, int, S_IRUGO);
 116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 117
 118 static int debug;
 119 module_param(debug, int, S_IRUGO);
 120 MODULE_PARM_DESC(debug, " Default debug msglevel");
 121
 122 static struct workqueue_struct *bnx2x_wq;
 123 struct workqueue_struct *bnx2x_iov_wq;
 124
 125 struct bnx2x_mac_vals {
 126         u32 xmac_addr;
 127         u32 xmac_val;
 128         u32 emac_addr;
 129         u32 emac_val;
 130         u32 umac_addr[2];
 131         u32 umac_val[2];
 132         u32 bmac_addr;
 133         u32 bmac_val[2];
 134 };
 135
 136 enum bnx2x_board_type {
 137         BCM57710 = 0,
 138         BCM57711,
 139         BCM57711E,
 140         BCM57712,
 141         BCM57712_MF,
 142         BCM57712_VF,
 143         BCM57800,
 144         BCM57800_MF,
 145         BCM57800_VF,
 146         BCM57810,
 147         BCM57810_MF,
 148         BCM57810_VF,
 149         BCM57840_4_10,
 150         BCM57840_2_20,
 151         BCM57840_MF,
 152         BCM57840_VF,
 153         BCM57811,
 154         BCM57811_MF,
 155         BCM57840_O,
 156         BCM57840_MFO,
 157         BCM57811_VF
 158 };
 159
 160 /* indexed by board_type, above */
 161 static struct {
 162         char *name;
 163 } board_info[] = {
 164         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 165         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 166         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 167         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 168         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 169         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 170         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 171         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 172         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 173         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 174         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 175         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 177         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 178         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 179         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 180         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 181         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 182         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 183         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 184         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 185 };
 186
 187 #ifndef PCI_DEVICE_ID_NX2_57710
 188 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 189 #endif
 190 #ifndef PCI_DEVICE_ID_NX2_57711
 191 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 192 #endif
 193 #ifndef PCI_DEVICE_ID_NX2_57711E
 194 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57712
 197 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 200 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 203 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57800
 206 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 209 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 212 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57810
 215 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 218 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57840_O
 221 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 224 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 227 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 230 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 233 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 236 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 239 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57811
 242 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 245 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 248 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 249 #endif
 250
 251 static const struct pci_device_id bnx2x_pci_tbl[] = {
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 265         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 270         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 272         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 276         { 0 }
 277 };
 278
 279 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 280
 281 /* Global resources for unloading a previously loaded device */
 282 #define BNX2X_PREV_WAIT_NEEDED 1
 283 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 284 static LIST_HEAD(bnx2x_prev_list);
 285
 286 /* Forward declaration */
 287 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 288 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 289 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 290
 291 /****************************************************************************
 292 * General service functions
 293 ****************************************************************************/
 294
 295 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 296
 297 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 298                                        u32 addr, dma_addr_t mapping)
 299 {
 300         REG_WR(bp,  addr, U64_LO(mapping));
 301         REG_WR(bp,  addr + 4, U64_HI(mapping));
 302 }
 303
 304 static void storm_memset_spq_addr(struct bnx2x *bp,
 305                                   dma_addr_t mapping, u16 abs_fid)
 306 {
 307         u32 addr = XSEM_REG_FAST_MEMORY +
 308                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 309
 310         __storm_memset_dma_mapping(bp, addr, mapping);
 311 }
 312
 313 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 314                                   u16 pf_id)
 315 {
 316         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 317                 pf_id);
 318         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 319                 pf_id);
 320         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 321                 pf_id);
 322         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 323                 pf_id);
 324 }
 325
 326 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 327                                  u8 enable)
 328 {
 329         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 330                 enable);
 331         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 332                 enable);
 333         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 334                 enable);
 335         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 336                 enable);
 337 }
 338
 339 static void storm_memset_eq_data(struct bnx2x *bp,
 340                                  struct event_ring_data *eq_data,
 341                                 u16 pfid)
 342 {
 343         size_t size = sizeof(struct event_ring_data);
 344
 345         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 346
 347         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 348 }
 349
 350 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 351                                  u16 pfid)
 352 {
 353         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 354         REG_WR16(bp, addr, eq_prod);
 355 }
 356
 357 /* used only at init
 358  * locking is done by mcp
 359  */
 360 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 361 {
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 364         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 365                                PCICFG_VENDOR_ID_OFFSET);
 366 }
 367
 368 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 369 {
 370         u32 val;
 371
 372         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 373         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 374         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 375                                PCICFG_VENDOR_ID_OFFSET);
 376
 377         return val;
 378 }
 379
 380 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 381 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 382 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 383 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 384 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 385
 386 static void bnx2x_dp_dmae(struct bnx2x *bp,
 387                           struct dmae_command *dmae, int msglvl)
 388 {
 389         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 390         int i;
 391
 392         switch (dmae->opcode & DMAE_COMMAND_DST) {
 393         case DMAE_CMD_DST_PCI:
 394                 if (src_type == DMAE_CMD_SRC_PCI)
 395                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 396                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 397                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 398                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 399                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 400                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 401                            dmae->comp_val);
 402                 else
 403                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 404                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 405                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 406                            dmae->opcode, dmae->src_addr_lo >> 2,
 407                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 408                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 409                            dmae->comp_val);
 410                 break;
 411         case DMAE_CMD_DST_GRC:
 412                 if (src_type == DMAE_CMD_SRC_PCI)
 413                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 414                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 415                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 416                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 417                            dmae->len, dmae->dst_addr_lo >> 2,
 418                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 419                            dmae->comp_val);
 420                 else
 421                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 422                            "src [%08x], len [%d*4], dst [%08x]\n"
 423                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 424                            dmae->opcode, dmae->src_addr_lo >> 2,
 425                            dmae->len, dmae->dst_addr_lo >> 2,
 426                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 427                            dmae->comp_val);
 428                 break;
 429         default:
 430                 if (src_type == DMAE_CMD_SRC_PCI)
 431                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 432                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 433                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 434                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 435                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 436                            dmae->comp_val);
 437                 else
 438                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 439                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 440                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 441                            dmae->opcode, dmae->src_addr_lo >> 2,
 442                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 443                            dmae->comp_val);
 444                 break;
 445         }
 446
 447         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 448                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 449                    i, *(((u32 *)dmae) + i));
 450 }
 451
 452 /* copy command into DMAE command memory and set DMAE command go */
 453 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 454 {
 455         u32 cmd_offset;
 456         int i;
 457
 458         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 459         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 460                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 461         }
 462         REG_WR(bp, dmae_reg_go_c[idx], 1);
 463 }
 464
 465 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 466 {
 467         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 468                            DMAE_CMD_C_ENABLE);
 469 }
 470
 471 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 472 {
 473         return opcode & ~DMAE_CMD_SRC_RESET;
 474 }
 475
 476 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 477                              bool with_comp, u8 comp_type)
 478 {
 479         u32 opcode = 0;
 480
 481         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 482                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 483
 484         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 485
 486         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 487         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 488                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 489         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 490
 491 #ifdef __BIG_ENDIAN
 492         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 493 #else
 494         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 495 #endif
 496         if (with_comp)
 497                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 498         return opcode;
 499 }
 500
 501 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 502                                       struct dmae_command *dmae,
 503                                       u8 src_type, u8 dst_type)
 504 {
 505         memset(dmae, 0, sizeof(struct dmae_command));
 506
 507         /* set the opcode */
 508         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 509                                          true, DMAE_COMP_PCI);
 510
 511         /* fill in the completion parameters */
 512         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 513         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 514         dmae->comp_val = DMAE_COMP_VAL;
 515 }
 516
 517 /* issue a dmae command over the init-channel and wait for completion */
 518 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 519                                u32 *comp)
 520 {
 521         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 522         int rc = 0;
 523
 524         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 525
 526         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 527          * as long as this code is called both from syscall context and
 528          * from ndo_set_rx_mode() flow that may be called from BH.
 529          */
 530
 531         spin_lock_bh(&bp->dmae_lock);
 532
 533         /* reset completion */
 534         *comp = 0;
 535
 536         /* post the command on the channel used for initializations */
 537         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 538
 539         /* wait for completion */
 540         udelay(5);
 541         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 542
 543                 if (!cnt ||
 544                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 545                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 546                         BNX2X_ERR("DMAE timeout!\n");
 547                         rc = DMAE_TIMEOUT;
 548                         goto unlock;
 549                 }
 550                 cnt--;
 551                 udelay(50);
 552         }
 553         if (*comp & DMAE_PCI_ERR_FLAG) {
 554                 BNX2X_ERR("DMAE PCI error!\n");
 555                 rc = DMAE_PCI_ERROR;
 556         }
 557
 558 unlock:
 559
 560         spin_unlock_bh(&bp->dmae_lock);
 561
 562         return rc;
 563 }
 564
 565 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 566                       u32 len32)
 567 {
 568         int rc;
 569         struct dmae_command dmae;
 570
 571         if (!bp->dmae_ready) {
 572                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 573
 574                 if (CHIP_IS_E1(bp))
 575                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 576                 else
 577                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 578                 return;
 579         }
 580
 581         /* set opcode and fixed command fields */
 582         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 583
 584         /* fill in addresses and len */
 585         dmae.src_addr_lo = U64_LO(dma_addr);
 586         dmae.src_addr_hi = U64_HI(dma_addr);
 587         dmae.dst_addr_lo = dst_addr >> 2;
 588         dmae.dst_addr_hi = 0;
 589         dmae.len = len32;
 590
 591         /* issue the command and wait for completion */
 592         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 593         if (rc) {
 594                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 595 #ifdef BNX2X_STOP_ON_ERROR
 596                 bnx2x_panic();
 597 #endif
 598         }
 599 }
 600
 601 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 602 {
 603         int rc;
 604         struct dmae_command dmae;
 605
 606         if (!bp->dmae_ready) {
 607                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 608                 int i;
 609
 610                 if (CHIP_IS_E1(bp))
 611                         for (i = 0; i < len32; i++)
 612                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 613                 else
 614                         for (i = 0; i < len32; i++)
 615                                 data[i] = REG_RD(bp, src_addr + i*4);
 616
 617                 return;
 618         }
 619
 620         /* set opcode and fixed command fields */
 621         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 622
 623         /* fill in addresses and len */
 624         dmae.src_addr_lo = src_addr >> 2;
 625         dmae.src_addr_hi = 0;
 626         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 627         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 628         dmae.len = len32;
 629
 630         /* issue the command and wait for completion */
 631         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 632         if (rc) {
 633                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 634 #ifdef BNX2X_STOP_ON_ERROR
 635                 bnx2x_panic();
 636 #endif
 637         }
 638 }
 639
 640 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 641                                       u32 addr, u32 len)
 642 {
 643         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 644         int offset = 0;
 645
 646         while (len > dmae_wr_max) {
 647                 bnx2x_write_dmae(bp, phys_addr + offset,
 648                                  addr + offset, dmae_wr_max);
 649                 offset += dmae_wr_max * 4;
 650                 len -= dmae_wr_max;
 651         }
 652
 653         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 654 }
 655
 656 enum storms {
 657            XSTORM,
 658            TSTORM,
 659            CSTORM,
 660            USTORM,
 661            MAX_STORMS
 662 };
 663
 664 #define STORMS_NUM 4
 665 #define REGS_IN_ENTRY 4
 666
 667 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 668                                               enum storms storm,
 669                                               int entry)
 670 {
 671         switch (storm) {
 672         case XSTORM:
 673                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 674         case TSTORM:
 675                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 676         case CSTORM:
 677                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 678         case USTORM:
 679                 return USTORM_ASSERT_LIST_OFFSET(entry);
 680         case MAX_STORMS:
 681         default:
 682                 BNX2X_ERR("unknown storm\n");
 683         }
 684         return -EINVAL;
 685 }
 686
 687 static int bnx2x_mc_assert(struct bnx2x *bp)
 688 {
 689         char last_idx;
 690         int i, j, rc = 0;
 691         enum storms storm;
 692         u32 regs[REGS_IN_ENTRY];
 693         u32 bar_storm_intmem[STORMS_NUM] = {
 694                 BAR_XSTRORM_INTMEM,
 695                 BAR_TSTRORM_INTMEM,
 696                 BAR_CSTRORM_INTMEM,
 697                 BAR_USTRORM_INTMEM
 698         };
 699         u32 storm_assert_list_index[STORMS_NUM] = {
 700                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 703                 USTORM_ASSERT_LIST_INDEX_OFFSET
 704         };
 705         char *storms_string[STORMS_NUM] = {
 706                 "XSTORM",
 707                 "TSTORM",
 708                 "CSTORM",
 709                 "USTORM"
 710         };
 711
 712         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 713                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 714                                    storm_assert_list_index[storm]);
 715                 if (last_idx)
 716                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 717                                   storms_string[storm], last_idx);
 718
 719                 /* print the asserts */
 720                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 721                         /* read a single assert entry */
 722                         for (j = 0; j < REGS_IN_ENTRY; j++)
 723                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 724                                           bnx2x_get_assert_list_entry(bp,
 725                                                                       storm,
 726                                                                       i) +
 727                                           sizeof(u32) * j);
 728
 729                         /* log entry if it contains a valid assert */
 730                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 731                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 732                                           storms_string[storm], i, regs[3],
 733                                           regs[2], regs[1], regs[0]);
 734                                 rc++;
 735                         } else {
 736                                 break;
 737                         }
 738                 }
 739         }
 740
 741         BNX2X_ERR("Chip Revision: %s, /*(DEBLOBBED)*/\n",
 742                   CHIP_IS_E1(bp) ? "everest1" :
 743                   CHIP_IS_E1H(bp) ? "everest1h" :
 744                   CHIP_IS_E2(bp) ? "everest2" : "everest3"/*(DEBLOBBED)*/);
 745
 746         return rc;
 747 }
 748
 749 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 750 #define SCRATCH_BUFFER_SIZE(bp) \
 751         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 752
 753 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 754 {
 755         u32 addr, val;
 756         u32 mark, offset;
 757         __be32 data[9];
 758         int word;
 759         u32 trace_shmem_base;
 760         if (BP_NOMCP(bp)) {
 761                 BNX2X_ERR("NO MCP - can not dump\n");
 762                 return;
 763         }
 764         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 765                 (bp->common.bc_ver & 0xff0000) >> 16,
 766                 (bp->common.bc_ver & 0xff00) >> 8,
 767                 (bp->common.bc_ver & 0xff));
 768
 769         if (pci_channel_offline(bp->pdev)) {
 770                 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
 771                 return;
 772         }
 773
 774         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 775         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 776                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 777
 778         if (BP_PATH(bp) == 0)
 779                 trace_shmem_base = bp->common.shmem_base;
 780         else
 781                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 782
 783         /* sanity */
 784         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 785             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 786                                 SCRATCH_BUFFER_SIZE(bp)) {
 787                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 788                           trace_shmem_base);
 789                 return;
 790         }
 791
 792         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 793
 794         /* validate TRCB signature */
 795         mark = REG_RD(bp, addr);
 796         if (mark != MFW_TRACE_SIGNATURE) {
 797                 BNX2X_ERR("Trace buffer signature is missing.");
 798                 return ;
 799         }
 800
 801         /* read cyclic buffer pointer */
 802         addr += 4;
 803         mark = REG_RD(bp, addr);
 804         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 805         if (mark >= trace_shmem_base || mark < addr + 4) {
 806                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 807                 return;
 808         }
 809         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 810
 811         printk("%s", lvl);
 812
 813         /* dump buffer after the mark */
 814         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 815                 for (word = 0; word < 8; word++)
 816                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 817                 data[8] = 0x0;
 818                 pr_cont("%s", (char *)data);
 819         }
 820
 821         /* dump buffer before the mark */
 822         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 823                 for (word = 0; word < 8; word++)
 824                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 825                 data[8] = 0x0;
 826                 pr_cont("%s", (char *)data);
 827         }
 828         printk("%s" "end of fw dump\n", lvl);
 829 }
 830
 831 static void bnx2x_fw_dump(struct bnx2x *bp)
 832 {
 833         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 834 }
 835
 836 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 837 {
 838         int port = BP_PORT(bp);
 839         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 840         u32 val = REG_RD(bp, addr);
 841
 842         /* in E1 we must use only PCI configuration space to disable
 843          * MSI/MSIX capability
 844          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 845          */
 846         if (CHIP_IS_E1(bp)) {
 847                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 848                  * Use mask register to prevent from HC sending interrupts
 849                  * after we exit the function
 850                  */
 851                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 852
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 855                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 856         } else
 857                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 858                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 859                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 860                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 861
 862         DP(NETIF_MSG_IFDOWN,
 863            "write %x to HC %d (addr 0x%x)\n",
 864            val, port, addr);
 865
 866         /* flush all outstanding writes */
 867         mmiowb();
 868
 869         REG_WR(bp, addr, val);
 870         if (REG_RD(bp, addr) != val)
 871                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 872 }
 873
 874 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 875 {
 876         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 877
 878         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 879                  IGU_PF_CONF_INT_LINE_EN |
 880                  IGU_PF_CONF_ATTN_BIT_EN);
 881
 882         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 883
 884         /* flush all outstanding writes */
 885         mmiowb();
 886
 887         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 888         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 889                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 890 }
 891
 892 static void bnx2x_int_disable(struct bnx2x *bp)
 893 {
 894         if (bp->common.int_block == INT_BLOCK_HC)
 895                 bnx2x_hc_int_disable(bp);
 896         else
 897                 bnx2x_igu_int_disable(bp);
 898 }
 899
 900 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 901 {
 902         int i;
 903         u16 j;
 904         struct hc_sp_status_block_data sp_sb_data;
 905         int func = BP_FUNC(bp);
 906 #ifdef BNX2X_STOP_ON_ERROR
 907         u16 start = 0, end = 0;
 908         u8 cos;
 909 #endif
 910         if (IS_PF(bp) && disable_int)
 911                 bnx2x_int_disable(bp);
 912
 913         bp->stats_state = STATS_STATE_DISABLED;
 914         bp->eth_stats.unrecoverable_error++;
 915         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 916
 917         BNX2X_ERR("begin crash dump -----------------\n");
 918
 919         /* Indices */
 920         /* Common */
 921         if (IS_PF(bp)) {
 922                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 923                 int data_size, cstorm_offset;
 924
 925                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 926                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 927                           bp->spq_prod_idx, bp->stats_counter);
 928                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 929                           def_sb->atten_status_block.attn_bits,
 930                           def_sb->atten_status_block.attn_bits_ack,
 931                           def_sb->atten_status_block.status_block_id,
 932                           def_sb->atten_status_block.attn_bits_index);
 933                 BNX2X_ERR("     def (");
 934                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 935                         pr_cont("0x%x%s",
 936                                 def_sb->sp_sb.index_values[i],
 937                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 938
 939                 data_size = sizeof(struct hc_sp_status_block_data) /
 940                             sizeof(u32);
 941                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 942                 for (i = 0; i < data_size; i++)
 943                         *((u32 *)&sp_sb_data + i) =
 944                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 945                                            i * sizeof(u32));
 946
 947                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 948                         sp_sb_data.igu_sb_id,
 949                         sp_sb_data.igu_seg_id,
 950                         sp_sb_data.p_func.pf_id,
 951                         sp_sb_data.p_func.vnic_id,
 952                         sp_sb_data.p_func.vf_id,
 953                         sp_sb_data.p_func.vf_valid,
 954                         sp_sb_data.state);
 955         }
 956
 957         for_each_eth_queue(bp, i) {
 958                 struct bnx2x_fastpath *fp = &bp->fp[i];
 959                 int loop;
 960                 struct hc_status_block_data_e2 sb_data_e2;
 961                 struct hc_status_block_data_e1x sb_data_e1x;
 962                 struct hc_status_block_sm  *hc_sm_p =
 963                         CHIP_IS_E1x(bp) ?
 964                         sb_data_e1x.common.state_machine :
 965                         sb_data_e2.common.state_machine;
 966                 struct hc_index_data *hc_index_p =
 967                         CHIP_IS_E1x(bp) ?
 968                         sb_data_e1x.index_data :
 969                         sb_data_e2.index_data;
 970                 u8 data_size, cos;
 971                 u32 *sb_data_p;
 972                 struct bnx2x_fp_txdata txdata;
 973
 974                 if (!bp->fp)
 975                         break;
 976
 977                 if (!fp->rx_cons_sb)
 978                         continue;
 979
 980                 /* Rx */
 981                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 982                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 983                           fp->rx_comp_prod,
 984                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 985                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 986                           fp->rx_sge_prod, fp->last_max_sge,
 987                           le16_to_cpu(fp->fp_hc_idx));
 988
 989                 /* Tx */
 990                 for_each_cos_in_tx_queue(fp, cos)
 991                 {
 992                         if (!fp->txdata_ptr[cos])
 993                                 break;
 994
 995                         txdata = *fp->txdata_ptr[cos];
 996
 997                         if (!txdata.tx_cons_sb)
 998                                 continue;
 999
1000                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1001                                   i, txdata.tx_pkt_prod,
1002                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1003                                   txdata.tx_bd_cons,
1004                                   le16_to_cpu(*txdata.tx_cons_sb));
1005                 }
1006
1007                 loop = CHIP_IS_E1x(bp) ?
1008                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1009
1010                 /* host sb data */
1011
1012                 if (IS_FCOE_FP(fp))
1013                         continue;
1014
1015                 BNX2X_ERR("     run indexes (");
1016                 for (j = 0; j < HC_SB_MAX_SM; j++)
1017                         pr_cont("0x%x%s",
1018                                fp->sb_running_index[j],
1019                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1020
1021                 BNX2X_ERR("     indexes (");
1022                 for (j = 0; j < loop; j++)
1023                         pr_cont("0x%x%s",
1024                                fp->sb_index_values[j],
1025                                (j == loop - 1) ? ")" : " ");
1026
1027                 /* VF cannot access FW refelection for status block */
1028                 if (IS_VF(bp))
1029                         continue;
1030
1031                 /* fw sb data */
1032                 data_size = CHIP_IS_E1x(bp) ?
1033                         sizeof(struct hc_status_block_data_e1x) :
1034                         sizeof(struct hc_status_block_data_e2);
1035                 data_size /= sizeof(u32);
1036                 sb_data_p = CHIP_IS_E1x(bp) ?
1037                         (u32 *)&sb_data_e1x :
1038                         (u32 *)&sb_data_e2;
1039                 /* copy sb data in here */
1040                 for (j = 0; j < data_size; j++)
1041                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1042                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1043                                 j * sizeof(u32));
1044
1045                 if (!CHIP_IS_E1x(bp)) {
1046                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1047                                 sb_data_e2.common.p_func.pf_id,
1048                                 sb_data_e2.common.p_func.vf_id,
1049                                 sb_data_e2.common.p_func.vf_valid,
1050                                 sb_data_e2.common.p_func.vnic_id,
1051                                 sb_data_e2.common.same_igu_sb_1b,
1052                                 sb_data_e2.common.state);
1053                 } else {
1054                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1055                                 sb_data_e1x.common.p_func.pf_id,
1056                                 sb_data_e1x.common.p_func.vf_id,
1057                                 sb_data_e1x.common.p_func.vf_valid,
1058                                 sb_data_e1x.common.p_func.vnic_id,
1059                                 sb_data_e1x.common.same_igu_sb_1b,
1060                                 sb_data_e1x.common.state);
1061                 }
1062
1063                 /* SB_SMs data */
1064                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1065                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1066                                 j, hc_sm_p[j].__flags,
1067                                 hc_sm_p[j].igu_sb_id,
1068                                 hc_sm_p[j].igu_seg_id,
1069                                 hc_sm_p[j].time_to_expire,
1070                                 hc_sm_p[j].timer_value);
1071                 }
1072
1073                 /* Indices data */
1074                 for (j = 0; j < loop; j++) {
1075                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1076                                hc_index_p[j].flags,
1077                                hc_index_p[j].timeout);
1078                 }
1079         }
1080
1081 #ifdef BNX2X_STOP_ON_ERROR
1082         if (IS_PF(bp)) {
1083                 /* event queue */
1084                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1085                 for (i = 0; i < NUM_EQ_DESC; i++) {
1086                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1087
1088                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1089                                   i, bp->eq_ring[i].message.opcode,
1090                                   bp->eq_ring[i].message.error);
1091                         BNX2X_ERR("data: %x %x %x\n",
1092                                   data[0], data[1], data[2]);
1093                 }
1094         }
1095
1096         /* Rings */
1097         /* Rx */
1098         for_each_valid_rx_queue(bp, i) {
1099                 struct bnx2x_fastpath *fp = &bp->fp[i];
1100
1101                 if (!bp->fp)
1102                         break;
1103
1104                 if (!fp->rx_cons_sb)
1105                         continue;
1106
1107                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1108                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1109                 for (j = start; j != end; j = RX_BD(j + 1)) {
1110                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1111                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1112
1113                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1114                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1115                 }
1116
1117                 start = RX_SGE(fp->rx_sge_prod);
1118                 end = RX_SGE(fp->last_max_sge);
1119                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1120                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1121                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1122
1123                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1124                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1125                 }
1126
1127                 start = RCQ_BD(fp->rx_comp_cons - 10);
1128                 end = RCQ_BD(fp->rx_comp_cons + 503);
1129                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1130                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1131
1132                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1133                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1134                 }
1135         }
1136
1137         /* Tx */
1138         for_each_valid_tx_queue(bp, i) {
1139                 struct bnx2x_fastpath *fp = &bp->fp[i];
1140
1141                 if (!bp->fp)
1142                         break;
1143
1144                 for_each_cos_in_tx_queue(fp, cos) {
1145                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1146
1147                         if (!fp->txdata_ptr[cos])
1148                                 break;
1149
1150                         if (!txdata->tx_cons_sb)
1151                                 continue;
1152
1153                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1154                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1155                         for (j = start; j != end; j = TX_BD(j + 1)) {
1156                                 struct sw_tx_bd *sw_bd =
1157                                         &txdata->tx_buf_ring[j];
1158
1159                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1160                                           i, cos, j, sw_bd->skb,
1161                                           sw_bd->first_bd);
1162                         }
1163
1164                         start = TX_BD(txdata->tx_bd_cons - 10);
1165                         end = TX_BD(txdata->tx_bd_cons + 254);
1166                         for (j = start; j != end; j = TX_BD(j + 1)) {
1167                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1168
1169                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1170                                           i, cos, j, tx_bd[0], tx_bd[1],
1171                                           tx_bd[2], tx_bd[3]);
1172                         }
1173                 }
1174         }
1175 #endif
1176         if (IS_PF(bp)) {
1177                 bnx2x_fw_dump(bp);
1178                 bnx2x_mc_assert(bp);
1179         }
1180         BNX2X_ERR("end crash dump -----------------\n");
1181 }
1182
1183 /*
1184  * FLR Support for E2
1185  *
1186  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1187  * initialization.
1188  */
1189 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1190 #define FLR_WAIT_INTERVAL       50      /* usec */
1191 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1192
1193 struct pbf_pN_buf_regs {
1194         int pN;
1195         u32 init_crd;
1196         u32 crd;
1197         u32 crd_freed;
1198 };
1199
1200 struct pbf_pN_cmd_regs {
1201         int pN;
1202         u32 lines_occup;
1203         u32 lines_freed;
1204 };
1205
1206 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1207                                      struct pbf_pN_buf_regs *regs,
1208                                      u32 poll_count)
1209 {
1210         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1211         u32 cur_cnt = poll_count;
1212
1213         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1214         crd = crd_start = REG_RD(bp, regs->crd);
1215         init_crd = REG_RD(bp, regs->init_crd);
1216
1217         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1218         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1219         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1220
1221         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1222                (init_crd - crd_start))) {
1223                 if (cur_cnt--) {
1224                         udelay(FLR_WAIT_INTERVAL);
1225                         crd = REG_RD(bp, regs->crd);
1226                         crd_freed = REG_RD(bp, regs->crd_freed);
1227                 } else {
1228                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1229                            regs->pN);
1230                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1231                            regs->pN, crd);
1232                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1233                            regs->pN, crd_freed);
1234                         break;
1235                 }
1236         }
1237         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1238            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1239 }
1240
1241 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1242                                      struct pbf_pN_cmd_regs *regs,
1243                                      u32 poll_count)
1244 {
1245         u32 occup, to_free, freed, freed_start;
1246         u32 cur_cnt = poll_count;
1247
1248         occup = to_free = REG_RD(bp, regs->lines_occup);
1249         freed = freed_start = REG_RD(bp, regs->lines_freed);
1250
1251         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1252         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1253
1254         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1255                 if (cur_cnt--) {
1256                         udelay(FLR_WAIT_INTERVAL);
1257                         occup = REG_RD(bp, regs->lines_occup);
1258                         freed = REG_RD(bp, regs->lines_freed);
1259                 } else {
1260                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1261                            regs->pN);
1262                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1263                            regs->pN, occup);
1264                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1265                            regs->pN, freed);
1266                         break;
1267                 }
1268         }
1269         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1270            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1271 }
1272
1273 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1274                                     u32 expected, u32 poll_count)
1275 {
1276         u32 cur_cnt = poll_count;
1277         u32 val;
1278
1279         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1280                 udelay(FLR_WAIT_INTERVAL);
1281
1282         return val;
1283 }
1284
1285 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1286                                     char *msg, u32 poll_cnt)
1287 {
1288         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1289         if (val != 0) {
1290                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1291                 return 1;
1292         }
1293         return 0;
1294 }
1295
1296 /* Common routines with VF FLR cleanup */
1297 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1298 {
1299         /* adjust polling timeout */
1300         if (CHIP_REV_IS_EMUL(bp))
1301                 return FLR_POLL_CNT * 2000;
1302
1303         if (CHIP_REV_IS_FPGA(bp))
1304                 return FLR_POLL_CNT * 120;
1305
1306         return FLR_POLL_CNT;
1307 }
1308
1309 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1310 {
1311         struct pbf_pN_cmd_regs cmd_regs[] = {
1312                 {0, (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_OCCUPANCY_Q0 :
1314                         PBF_REG_P0_TQ_OCCUPANCY,
1315                     (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1317                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1318                 {1, (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_OCCUPANCY_Q1 :
1320                         PBF_REG_P1_TQ_OCCUPANCY,
1321                     (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1323                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1324                 {4, (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1326                         PBF_REG_P4_TQ_OCCUPANCY,
1327                     (CHIP_IS_E3B0(bp)) ?
1328                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1329                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1330         };
1331
1332         struct pbf_pN_buf_regs buf_regs[] = {
1333                 {0, (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_INIT_CRD_Q0 :
1335                         PBF_REG_P0_INIT_CRD ,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_CREDIT_Q0 :
1338                         PBF_REG_P0_CREDIT,
1339                     (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1341                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1342                 {1, (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_INIT_CRD_Q1 :
1344                         PBF_REG_P1_INIT_CRD,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_CREDIT_Q1 :
1347                         PBF_REG_P1_CREDIT,
1348                     (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1350                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1351                 {4, (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_INIT_CRD_LB_Q :
1353                         PBF_REG_P4_INIT_CRD,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_CREDIT_LB_Q :
1356                         PBF_REG_P4_CREDIT,
1357                     (CHIP_IS_E3B0(bp)) ?
1358                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1359                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1360         };
1361
1362         int i;
1363
1364         /* Verify the command queues are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1366                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1367
1368         /* Verify the transmission buffers are flushed P0, P1, P4 */
1369         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1370                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1371 }
1372
1373 #define OP_GEN_PARAM(param) \
1374         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1375
1376 #define OP_GEN_TYPE(type) \
1377         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1378
1379 #define OP_GEN_AGG_VECT(index) \
1380         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1381
1382 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1383 {
1384         u32 op_gen_command = 0;
1385         u32 comp_addr = BAR_CSTRORM_INTMEM +
1386                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1387         int ret = 0;
1388
1389         if (REG_RD(bp, comp_addr)) {
1390                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1391                 return 1;
1392         }
1393
1394         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1395         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1396         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1397         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1398
1399         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1400         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1401
1402         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1403                 BNX2X_ERR("FW final cleanup did not succeed\n");
1404                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1405                    (REG_RD(bp, comp_addr)));
1406                 bnx2x_panic();
1407                 return 1;
1408         }
1409         /* Zero completion for next FLR */
1410         REG_WR(bp, comp_addr, 0);
1411
1412         return ret;
1413 }
1414
1415 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1416 {
1417         u16 status;
1418
1419         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1420         return status & PCI_EXP_DEVSTA_TRPND;
1421 }
1422
1423 /* PF FLR specific routines
1424 */
1425 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1426 {
1427         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1428         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1429                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1430                         "CFC PF usage counter timed out",
1431                         poll_cnt))
1432                 return 1;
1433
1434         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1435         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1436                         DORQ_REG_PF_USAGE_CNT,
1437                         "DQ PF usage counter timed out",
1438                         poll_cnt))
1439                 return 1;
1440
1441         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1442         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1443                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1444                         "QM PF usage counter timed out",
1445                         poll_cnt))
1446                 return 1;
1447
1448         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1449         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1450                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1451                         "Timers VNIC usage counter timed out",
1452                         poll_cnt))
1453                 return 1;
1454         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1455                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1456                         "Timers NUM_SCANS usage counter timed out",
1457                         poll_cnt))
1458                 return 1;
1459
1460         /* Wait DMAE PF usage counter to zero */
1461         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1462                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1463                         "DMAE command register timed out",
1464                         poll_cnt))
1465                 return 1;
1466
1467         return 0;
1468 }
1469
1470 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1471 {
1472         u32 val;
1473
1474         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1475         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1476
1477         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1478         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1479
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1482
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1485
1486         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1487         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1488
1489         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1491
1492         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1494
1495         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1496         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1497            val);
1498 }
1499
1500 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1501 {
1502         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1503
1504         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1505
1506         /* Re-enable PF target read access */
1507         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1508
1509         /* Poll HW usage counters */
1510         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1511         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1512                 return -EBUSY;
1513
1514         /* Zero the igu 'trailing edge' and 'leading edge' */
1515
1516         /* Send the FW cleanup command */
1517         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1518                 return -EBUSY;
1519
1520         /* ATC cleanup */
1521
1522         /* Verify TX hw is flushed */
1523         bnx2x_tx_hw_flushed(bp, poll_cnt);
1524
1525         /* Wait 100ms (not adjusted according to platform) */
1526         msleep(100);
1527
1528         /* Verify no pending pci transactions */
1529         if (bnx2x_is_pcie_pending(bp->pdev))
1530                 BNX2X_ERR("PCIE Transactions still pending\n");
1531
1532         /* Debug */
1533         bnx2x_hw_enable_status(bp);
1534
1535         /*
1536          * Master enable - Due to WB DMAE writes performed before this
1537          * register is re-initialized as part of the regular function init
1538          */
1539         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1540
1541         return 0;
1542 }
1543
1544 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1545 {
1546         int port = BP_PORT(bp);
1547         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1548         u32 val = REG_RD(bp, addr);
1549         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1550         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1551         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1552
1553         if (msix) {
1554                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1555                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1556                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1557                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1558                 if (single_msix)
1559                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1560         } else if (msi) {
1561                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1565         } else {
1566                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1567                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1568                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1569                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1570
1571                 if (!CHIP_IS_E1(bp)) {
1572                         DP(NETIF_MSG_IFUP,
1573                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1574
1575                         REG_WR(bp, addr, val);
1576
1577                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1578                 }
1579         }
1580
1581         if (CHIP_IS_E1(bp))
1582                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1583
1584         DP(NETIF_MSG_IFUP,
1585            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1586            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1587
1588         REG_WR(bp, addr, val);
1589         /*
1590          * Ensure that HC_CONFIG is written before leading/trailing edge config
1591          */
1592         mmiowb();
1593         barrier();
1594
1595         if (!CHIP_IS_E1(bp)) {
1596                 /* init leading/trailing edge */
1597                 if (IS_MF(bp)) {
1598                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1599                         if (bp->port.pmf)
1600                                 /* enable nig and gpio3 attention */
1601                                 val |= 0x1100;
1602                 } else
1603                         val = 0xffff;
1604
1605                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1606                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1607         }
1608
1609         /* Make sure that interrupts are indeed enabled from here on */
1610         mmiowb();
1611 }
1612
1613 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1614 {
1615         u32 val;
1616         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1617         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1618         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1619
1620         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1621
1622         if (msix) {
1623                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1624                          IGU_PF_CONF_SINGLE_ISR_EN);
1625                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1626                         IGU_PF_CONF_ATTN_BIT_EN);
1627
1628                 if (single_msix)
1629                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1630         } else if (msi) {
1631                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1632                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1633                         IGU_PF_CONF_ATTN_BIT_EN |
1634                         IGU_PF_CONF_SINGLE_ISR_EN);
1635         } else {
1636                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1637                 val |= (IGU_PF_CONF_INT_LINE_EN |
1638                         IGU_PF_CONF_ATTN_BIT_EN |
1639                         IGU_PF_CONF_SINGLE_ISR_EN);
1640         }
1641
1642         /* Clean previous status - need to configure igu prior to ack*/
1643         if ((!msix) || single_msix) {
1644                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1645                 bnx2x_ack_int(bp);
1646         }
1647
1648         val |= IGU_PF_CONF_FUNC_EN;
1649
1650         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1651            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1652
1653         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1654
1655         if (val & IGU_PF_CONF_INT_LINE_EN)
1656                 pci_intx(bp->pdev, true);
1657
1658         barrier();
1659
1660         /* init leading/trailing edge */
1661         if (IS_MF(bp)) {
1662                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1663                 if (bp->port.pmf)
1664                         /* enable nig and gpio3 attention */
1665                         val |= 0x1100;
1666         } else
1667                 val = 0xffff;
1668
1669         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1670         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1671
1672         /* Make sure that interrupts are indeed enabled from here on */
1673         mmiowb();
1674 }
1675
1676 void bnx2x_int_enable(struct bnx2x *bp)
1677 {
1678         if (bp->common.int_block == INT_BLOCK_HC)
1679                 bnx2x_hc_int_enable(bp);
1680         else
1681                 bnx2x_igu_int_enable(bp);
1682 }
1683
1684 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1685 {
1686         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1687         int i, offset;
1688
1689         if (disable_hw)
1690                 /* prevent the HW from sending interrupts */
1691                 bnx2x_int_disable(bp);
1692
1693         /* make sure all ISRs are done */
1694         if (msix) {
1695                 synchronize_irq(bp->msix_table[0].vector);
1696                 offset = 1;
1697                 if (CNIC_SUPPORT(bp))
1698                         offset++;
1699                 for_each_eth_queue(bp, i)
1700                         synchronize_irq(bp->msix_table[offset++].vector);
1701         } else
1702                 synchronize_irq(bp->pdev->irq);
1703
1704         /* make sure sp_task is not running */
1705         cancel_delayed_work(&bp->sp_task);
1706         cancel_delayed_work(&bp->period_task);
1707         flush_workqueue(bnx2x_wq);
1708 }
1709
1710 /* fast path */
1711
1712 /*
1713  * General service functions
1714  */
1715
1716 /* Return true if succeeded to acquire the lock */
1717 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1718 {
1719         u32 lock_status;
1720         u32 resource_bit = (1 << resource);
1721         int func = BP_FUNC(bp);
1722         u32 hw_lock_control_reg;
1723
1724         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1725            "Trying to take a lock on resource %d\n", resource);
1726
1727         /* Validating that the resource is within range */
1728         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1729                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1730                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1731                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1732                 return false;
1733         }
1734
1735         if (func <= 5)
1736                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1737         else
1738                 hw_lock_control_reg =
1739                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1740
1741         /* Try to acquire the lock */
1742         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1743         lock_status = REG_RD(bp, hw_lock_control_reg);
1744         if (lock_status & resource_bit)
1745                 return true;
1746
1747         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1748            "Failed to get a lock on resource %d\n", resource);
1749         return false;
1750 }
1751
1752 /**
1753  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1754  *
1755  * @bp: driver handle
1756  *
1757  * Returns the recovery leader resource id according to the engine this function
1758  * belongs to. Currently only only 2 engines is supported.
1759  */
1760 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1761 {
1762         if (BP_PATH(bp))
1763                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1764         else
1765                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1766 }
1767
1768 /**
1769  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1770  *
1771  * @bp: driver handle
1772  *
1773  * Tries to acquire a leader lock for current engine.
1774  */
1775 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1776 {
1777         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1778 }
1779
1780 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1781
1782 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1783 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1784 {
1785         /* Set the interrupt occurred bit for the sp-task to recognize it
1786          * must ack the interrupt and transition according to the IGU
1787          * state machine.
1788          */
1789         atomic_set(&bp->interrupt_occurred, 1);
1790
1791         /* The sp_task must execute only after this bit
1792          * is set, otherwise we will get out of sync and miss all
1793          * further interrupts. Hence, the barrier.
1794          */
1795         smp_wmb();
1796
1797         /* schedule sp_task to workqueue */
1798         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1799 }
1800
1801 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1802 {
1803         struct bnx2x *bp = fp->bp;
1804         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1805         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1806         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1807         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1808
1809         DP(BNX2X_MSG_SP,
1810            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1811            fp->index, cid, command, bp->state,
1812            rr_cqe->ramrod_cqe.ramrod_type);
1813
1814         /* If cid is within VF range, replace the slowpath object with the
1815          * one corresponding to this VF
1816          */
1817         if (cid >= BNX2X_FIRST_VF_CID  &&
1818             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1819                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1820
1821         switch (command) {
1822         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1823                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1824                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1825                 break;
1826
1827         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1828                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1829                 drv_cmd = BNX2X_Q_CMD_SETUP;
1830                 break;
1831
1832         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1833                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1834                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1835                 break;
1836
1837         case (RAMROD_CMD_ID_ETH_HALT):
1838                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1839                 drv_cmd = BNX2X_Q_CMD_HALT;
1840                 break;
1841
1842         case (RAMROD_CMD_ID_ETH_TERMINATE):
1843                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1844                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1845                 break;
1846
1847         case (RAMROD_CMD_ID_ETH_EMPTY):
1848                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1849                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1850                 break;
1851
1852         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1853                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1854                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1855                 break;
1856
1857         default:
1858                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1859                           command, fp->index);
1860                 return;
1861         }
1862
1863         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1864             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1865                 /* q_obj->complete_cmd() failure means that this was
1866                  * an unexpected completion.
1867                  *
1868                  * In this case we don't want to increase the bp->spq_left
1869                  * because apparently we haven't sent this command the first
1870                  * place.
1871                  */
1872 #ifdef BNX2X_STOP_ON_ERROR
1873                 bnx2x_panic();
1874 #else
1875                 return;
1876 #endif
1877
1878         smp_mb__before_atomic();
1879         atomic_inc(&bp->cq_spq_left);
1880         /* push the change in bp->spq_left and towards the memory */
1881         smp_mb__after_atomic();
1882
1883         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1884
1885         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1886             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1887                 /* if Q update ramrod is completed for last Q in AFEX vif set
1888                  * flow, then ACK MCP at the end
1889                  *
1890                  * mark pending ACK to MCP bit.
1891                  * prevent case that both bits are cleared.
1892                  * At the end of load/unload driver checks that
1893                  * sp_state is cleared, and this order prevents
1894                  * races
1895                  */
1896                 smp_mb__before_atomic();
1897                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1898                 wmb();
1899                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1900                 smp_mb__after_atomic();
1901
1902                 /* schedule the sp task as mcp ack is required */
1903                 bnx2x_schedule_sp_task(bp);
1904         }
1905
1906         return;
1907 }
1908
1909 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1910 {
1911         struct bnx2x *bp = netdev_priv(dev_instance);
1912         u16 status = bnx2x_ack_int(bp);
1913         u16 mask;
1914         int i;
1915         u8 cos;
1916
1917         /* Return here if interrupt is shared and it's not for us */
1918         if (unlikely(status == 0)) {
1919                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1920                 return IRQ_NONE;
1921         }
1922         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1923
1924 #ifdef BNX2X_STOP_ON_ERROR
1925         if (unlikely(bp->panic))
1926                 return IRQ_HANDLED;
1927 #endif
1928
1929         for_each_eth_queue(bp, i) {
1930                 struct bnx2x_fastpath *fp = &bp->fp[i];
1931
1932                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1933                 if (status & mask) {
1934                         /* Handle Rx or Tx according to SB id */
1935                         for_each_cos_in_tx_queue(fp, cos)
1936                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1937                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1938                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1939                         status &= ~mask;
1940                 }
1941         }
1942
1943         if (CNIC_SUPPORT(bp)) {
1944                 mask = 0x2;
1945                 if (status & (mask | 0x1)) {
1946                         struct cnic_ops *c_ops = NULL;
1947
1948                         rcu_read_lock();
1949                         c_ops = rcu_dereference(bp->cnic_ops);
1950                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1951                                       CNIC_DRV_STATE_HANDLES_IRQ))
1952                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1953                         rcu_read_unlock();
1954
1955                         status &= ~mask;
1956                 }
1957         }
1958
1959         if (unlikely(status & 0x1)) {
1960
1961                 /* schedule sp task to perform default status block work, ack
1962                  * attentions and enable interrupts.
1963                  */
1964                 bnx2x_schedule_sp_task(bp);
1965
1966                 status &= ~0x1;
1967                 if (!status)
1968                         return IRQ_HANDLED;
1969         }
1970
1971         if (unlikely(status))
1972                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1973                    status);
1974
1975         return IRQ_HANDLED;
1976 }
1977
1978 /* Link */
1979
1980 /*
1981  * General service functions
1982  */
1983
1984 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1985 {
1986         u32 lock_status;
1987         u32 resource_bit = (1 << resource);
1988         int func = BP_FUNC(bp);
1989         u32 hw_lock_control_reg;
1990         int cnt;
1991
1992         /* Validating that the resource is within range */
1993         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1994                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1995                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1996                 return -EINVAL;
1997         }
1998
1999         if (func <= 5) {
2000                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2001         } else {
2002                 hw_lock_control_reg =
2003                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2004         }
2005
2006         /* Validating that the resource is not already taken */
2007         lock_status = REG_RD(bp, hw_lock_control_reg);
2008         if (lock_status & resource_bit) {
2009                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2010                    lock_status, resource_bit);
2011                 return -EEXIST;
2012         }
2013
2014         /* Try for 5 second every 5ms */
2015         for (cnt = 0; cnt < 1000; cnt++) {
2016                 /* Try to acquire the lock */
2017                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2018                 lock_status = REG_RD(bp, hw_lock_control_reg);
2019                 if (lock_status & resource_bit)
2020                         return 0;
2021
2022                 usleep_range(5000, 10000);
2023         }
2024         BNX2X_ERR("Timeout\n");
2025         return -EAGAIN;
2026 }
2027
2028 int bnx2x_release_leader_lock(struct bnx2x *bp)
2029 {
2030         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2031 }
2032
2033 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2034 {
2035         u32 lock_status;
2036         u32 resource_bit = (1 << resource);
2037         int func = BP_FUNC(bp);
2038         u32 hw_lock_control_reg;
2039
2040         /* Validating that the resource is within range */
2041         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2042                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2043                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2044                 return -EINVAL;
2045         }
2046
2047         if (func <= 5) {
2048                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2049         } else {
2050                 hw_lock_control_reg =
2051                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2052         }
2053
2054         /* Validating that the resource is currently taken */
2055         lock_status = REG_RD(bp, hw_lock_control_reg);
2056         if (!(lock_status & resource_bit)) {
2057                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2058                           lock_status, resource_bit);
2059                 return -EFAULT;
2060         }
2061
2062         REG_WR(bp, hw_lock_control_reg, resource_bit);
2063         return 0;
2064 }
2065
2066 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2067 {
2068         /* The GPIO should be swapped if swap register is set and active */
2069         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2070                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2071         int gpio_shift = gpio_num +
2072                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2073         u32 gpio_mask = (1 << gpio_shift);
2074         u32 gpio_reg;
2075         int value;
2076
2077         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2078                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2079                 return -EINVAL;
2080         }
2081
2082         /* read GPIO value */
2083         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2084
2085         /* get the requested pin value */
2086         if ((gpio_reg & gpio_mask) == gpio_mask)
2087                 value = 1;
2088         else
2089                 value = 0;
2090
2091         return value;
2092 }
2093
2094 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2095 {
2096         /* The GPIO should be swapped if swap register is set and active */
2097         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2098                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2099         int gpio_shift = gpio_num +
2100                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2101         u32 gpio_mask = (1 << gpio_shift);
2102         u32 gpio_reg;
2103
2104         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2105                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2106                 return -EINVAL;
2107         }
2108
2109         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2110         /* read GPIO and mask except the float bits */
2111         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2112
2113         switch (mode) {
2114         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2115                 DP(NETIF_MSG_LINK,
2116                    "Set GPIO %d (shift %d) -> output low\n",
2117                    gpio_num, gpio_shift);
2118                 /* clear FLOAT and set CLR */
2119                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2120                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2121                 break;
2122
2123         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2124                 DP(NETIF_MSG_LINK,
2125                    "Set GPIO %d (shift %d) -> output high\n",
2126                    gpio_num, gpio_shift);
2127                 /* clear FLOAT and set SET */
2128                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2129                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2130                 break;
2131
2132         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2133                 DP(NETIF_MSG_LINK,
2134                    "Set GPIO %d (shift %d) -> input\n",
2135                    gpio_num, gpio_shift);
2136                 /* set FLOAT */
2137                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2138                 break;
2139
2140         default:
2141                 break;
2142         }
2143
2144         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2145         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2146
2147         return 0;
2148 }
2149
2150 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2151 {
2152         u32 gpio_reg = 0;
2153         int rc = 0;
2154
2155         /* Any port swapping should be handled by caller. */
2156
2157         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2158         /* read GPIO and mask except the float bits */
2159         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2160         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2161         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2162         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2163
2164         switch (mode) {
2165         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2166                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2167                 /* set CLR */
2168                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2169                 break;
2170
2171         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2172                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2173                 /* set SET */
2174                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2175                 break;
2176
2177         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2178                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2179                 /* set FLOAT */
2180                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2181                 break;
2182
2183         default:
2184                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2185                 rc = -EINVAL;
2186                 break;
2187         }
2188
2189         if (rc == 0)
2190                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2191
2192         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2193
2194         return rc;
2195 }
2196
2197 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2198 {
2199         /* The GPIO should be swapped if swap register is set and active */
2200         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2201                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2202         int gpio_shift = gpio_num +
2203                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2204         u32 gpio_mask = (1 << gpio_shift);
2205         u32 gpio_reg;
2206
2207         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2208                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2209                 return -EINVAL;
2210         }
2211
2212         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2213         /* read GPIO int */
2214         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2215
2216         switch (mode) {
2217         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2218                 DP(NETIF_MSG_LINK,
2219                    "Clear GPIO INT %d (shift %d) -> output low\n",
2220                    gpio_num, gpio_shift);
2221                 /* clear SET and set CLR */
2222                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2223                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2224                 break;
2225
2226         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2227                 DP(NETIF_MSG_LINK,
2228                    "Set GPIO INT %d (shift %d) -> output high\n",
2229                    gpio_num, gpio_shift);
2230                 /* clear CLR and set SET */
2231                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2232                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2233                 break;
2234
2235         default:
2236                 break;
2237         }
2238
2239         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2240         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2241
2242         return 0;
2243 }
2244
2245 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2246 {
2247         u32 spio_reg;
2248
2249         /* Only 2 SPIOs are configurable */
2250         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2251                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2252                 return -EINVAL;
2253         }
2254
2255         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2256         /* read SPIO and mask except the float bits */
2257         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2258
2259         switch (mode) {
2260         case MISC_SPIO_OUTPUT_LOW:
2261                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2262                 /* clear FLOAT and set CLR */
2263                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2264                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2265                 break;
2266
2267         case MISC_SPIO_OUTPUT_HIGH:
2268                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2269                 /* clear FLOAT and set SET */
2270                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2271                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2272                 break;
2273
2274         case MISC_SPIO_INPUT_HI_Z:
2275                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2276                 /* set FLOAT */
2277                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2278                 break;
2279
2280         default:
2281                 break;
2282         }
2283
2284         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2285         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2286
2287         return 0;
2288 }
2289
2290 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2291 {
2292         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2293
2294         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2295                                            ADVERTISED_Pause);
2296         switch (bp->link_vars.ieee_fc &
2297                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2298         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2299                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2300                                                   ADVERTISED_Pause);
2301                 break;
2302
2303         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2304                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2305                 break;
2306
2307         default:
2308                 break;
2309         }
2310 }
2311
2312 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2313 {
2314         /* Initialize link parameters structure variables
2315          * It is recommended to turn off RX FC for jumbo frames
2316          *  for better performance
2317          */
2318         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320         else
2321                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2322 }
2323
2324 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325 {
2326         u32 pause_enabled = 0;
2327
2328         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2330                         pause_enabled = 1;
2331
2332                 REG_WR(bp, BAR_USTRORM_INTMEM +
2333                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334                        pause_enabled);
2335         }
2336
2337         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338            pause_enabled ? "enabled" : "disabled");
2339 }
2340
2341 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342 {
2343         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345
2346         if (!BP_NOMCP(bp)) {
2347                 bnx2x_set_requested_fc(bp);
2348                 bnx2x_acquire_phy_lock(bp);
2349
2350                 if (load_mode == LOAD_DIAG) {
2351                         struct link_params *lp = &bp->link_params;
2352                         lp->loopback_mode = LOOPBACK_XGXS;
2353                         /* Prefer doing PHY loopback at highest speed */
2354                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2355                                 if (lp->speed_cap_mask[cfx_idx] &
2356                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2357                                         lp->req_line_speed[cfx_idx] =
2358                                         SPEED_20000;
2359                                 else if (lp->speed_cap_mask[cfx_idx] &
2360                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2361                                                 lp->req_line_speed[cfx_idx] =
2362                                                 SPEED_10000;
2363                                 else
2364                                         lp->req_line_speed[cfx_idx] =
2365                                         SPEED_1000;
2366                         }
2367                 }
2368
2369                 if (load_mode == LOAD_LOOPBACK_EXT) {
2370                         struct link_params *lp = &bp->link_params;
2371                         lp->loopback_mode = LOOPBACK_EXT;
2372                 }
2373
2374                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2375
2376                 bnx2x_release_phy_lock(bp);
2377
2378                 bnx2x_init_dropless_fc(bp);
2379
2380                 bnx2x_calc_fc_adv(bp);
2381
2382                 if (bp->link_vars.link_up) {
2383                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2384                         bnx2x_link_report(bp);
2385                 }
2386                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2387                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2388                 return rc;
2389         }
2390         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2391         return -EINVAL;
2392 }
2393
2394 void bnx2x_link_set(struct bnx2x *bp)
2395 {
2396         if (!BP_NOMCP(bp)) {
2397                 bnx2x_acquire_phy_lock(bp);
2398                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2399                 bnx2x_release_phy_lock(bp);
2400
2401                 bnx2x_init_dropless_fc(bp);
2402
2403                 bnx2x_calc_fc_adv(bp);
2404         } else
2405                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2406 }
2407
2408 static void bnx2x__link_reset(struct bnx2x *bp)
2409 {
2410         if (!BP_NOMCP(bp)) {
2411                 bnx2x_acquire_phy_lock(bp);
2412                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2413                 bnx2x_release_phy_lock(bp);
2414         } else
2415                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2416 }
2417
2418 void bnx2x_force_link_reset(struct bnx2x *bp)
2419 {
2420         bnx2x_acquire_phy_lock(bp);
2421         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2422         bnx2x_release_phy_lock(bp);
2423 }
2424
2425 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2426 {
2427         u8 rc = 0;
2428
2429         if (!BP_NOMCP(bp)) {
2430                 bnx2x_acquire_phy_lock(bp);
2431                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2432                                      is_serdes);
2433                 bnx2x_release_phy_lock(bp);
2434         } else
2435                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2436
2437         return rc;
2438 }
2439
2440 /* Calculates the sum of vn_min_rates.
2441    It's needed for further normalizing of the min_rates.
2442    Returns:
2443      sum of vn_min_rates.
2444        or
2445      0 - if all the min_rates are 0.
2446      In the later case fairness algorithm should be deactivated.
2447      If not all min_rates are zero then those that are zeroes will be set to 1.
2448  */
2449 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2450                                       struct cmng_init_input *input)
2451 {
2452         int all_zero = 1;
2453         int vn;
2454
2455         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2456                 u32 vn_cfg = bp->mf_config[vn];
2457                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2458                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2459
2460                 /* Skip hidden vns */
2461                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2462                         vn_min_rate = 0;
2463                 /* If min rate is zero - set it to 1 */
2464                 else if (!vn_min_rate)
2465                         vn_min_rate = DEF_MIN_RATE;
2466                 else
2467                         all_zero = 0;
2468
2469                 input->vnic_min_rate[vn] = vn_min_rate;
2470         }
2471
2472         /* if ETS or all min rates are zeros - disable fairness */
2473         if (BNX2X_IS_ETS_ENABLED(bp)) {
2474                 input->flags.cmng_enables &=
2475                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2477         } else if (all_zero) {
2478                 input->flags.cmng_enables &=
2479                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2480                 DP(NETIF_MSG_IFUP,
2481                    "All MIN values are zeroes fairness will be disabled\n");
2482         } else
2483                 input->flags.cmng_enables |=
2484                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2485 }
2486
2487 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2488                                     struct cmng_init_input *input)
2489 {
2490         u16 vn_max_rate;
2491         u32 vn_cfg = bp->mf_config[vn];
2492
2493         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2494                 vn_max_rate = 0;
2495         else {
2496                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2497
2498                 if (IS_MF_PERCENT_BW(bp)) {
2499                         /* maxCfg in percents of linkspeed */
2500                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2501                 } else /* SD modes */
2502                         /* maxCfg is absolute in 100Mb units */
2503                         vn_max_rate = maxCfg * 100;
2504         }
2505
2506         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2507
2508         input->vnic_max_rate[vn] = vn_max_rate;
2509 }
2510
2511 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2512 {
2513         if (CHIP_REV_IS_SLOW(bp))
2514                 return CMNG_FNS_NONE;
2515         if (IS_MF(bp))
2516                 return CMNG_FNS_MINMAX;
2517
2518         return CMNG_FNS_NONE;
2519 }
2520
2521 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2522 {
2523         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2524
2525         if (BP_NOMCP(bp))
2526                 return; /* what should be the default value in this case */
2527
2528         /* For 2 port configuration the absolute function number formula
2529          * is:
2530          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2531          *
2532          *      and there are 4 functions per port
2533          *
2534          * For 4 port configuration it is
2535          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2536          *
2537          *      and there are 2 functions per port
2538          */
2539         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2540                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2541
2542                 if (func >= E1H_FUNC_MAX)
2543                         break;
2544
2545                 bp->mf_config[vn] =
2546                         MF_CFG_RD(bp, func_mf_config[func].config);
2547         }
2548         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2549                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2550                 bp->flags |= MF_FUNC_DIS;
2551         } else {
2552                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2553                 bp->flags &= ~MF_FUNC_DIS;
2554         }
2555 }
2556
2557 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2558 {
2559         struct cmng_init_input input;
2560         memset(&input, 0, sizeof(struct cmng_init_input));
2561
2562         input.port_rate = bp->link_vars.line_speed;
2563
2564         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2565                 int vn;
2566
2567                 /* read mf conf from shmem */
2568                 if (read_cfg)
2569                         bnx2x_read_mf_cfg(bp);
2570
2571                 /* vn_weight_sum and enable fairness if not 0 */
2572                 bnx2x_calc_vn_min(bp, &input);
2573
2574                 /* calculate and set min-max rate for each vn */
2575                 if (bp->port.pmf)
2576                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2577                                 bnx2x_calc_vn_max(bp, vn, &input);
2578
2579                 /* always enable rate shaping and fairness */
2580                 input.flags.cmng_enables |=
2581                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2582
2583                 bnx2x_init_cmng(&input, &bp->cmng);
2584                 return;
2585         }
2586
2587         /* rate shaping and fairness are disabled */
2588         DP(NETIF_MSG_IFUP,
2589            "rate shaping and fairness are disabled\n");
2590 }
2591
2592 static void storm_memset_cmng(struct bnx2x *bp,
2593                               struct cmng_init *cmng,
2594                               u8 port)
2595 {
2596         int vn;
2597         size_t size = sizeof(struct cmng_struct_per_port);
2598
2599         u32 addr = BAR_XSTRORM_INTMEM +
2600                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2601
2602         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2603
2604         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2605                 int func = func_by_vn(bp, vn);
2606
2607                 addr = BAR_XSTRORM_INTMEM +
2608                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2609                 size = sizeof(struct rate_shaping_vars_per_vn);
2610                 __storm_memset_struct(bp, addr, size,
2611                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2612
2613                 addr = BAR_XSTRORM_INTMEM +
2614                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2615                 size = sizeof(struct fairness_vars_per_vn);
2616                 __storm_memset_struct(bp, addr, size,
2617                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2618         }
2619 }
2620
2621 /* init cmng mode in HW according to local configuration */
2622 void bnx2x_set_local_cmng(struct bnx2x *bp)
2623 {
2624         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2625
2626         if (cmng_fns != CMNG_FNS_NONE) {
2627                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2628                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2629         } else {
2630                 /* rate shaping and fairness are disabled */
2631                 DP(NETIF_MSG_IFUP,
2632                    "single function mode without fairness\n");
2633         }
2634 }
2635
2636 /* This function is called upon link interrupt */
2637 static void bnx2x_link_attn(struct bnx2x *bp)
2638 {
2639         /* Make sure that we are synced with the current statistics */
2640         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2641
2642         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2643
2644         bnx2x_init_dropless_fc(bp);
2645
2646         if (bp->link_vars.link_up) {
2647
2648                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2649                         struct host_port_stats *pstats;
2650
2651                         pstats = bnx2x_sp(bp, port_stats);
2652                         /* reset old mac stats */
2653                         memset(&(pstats->mac_stx[0]), 0,
2654                                sizeof(struct mac_stx));
2655                 }
2656                 if (bp->state == BNX2X_STATE_OPEN)
2657                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2658         }
2659
2660         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2661                 bnx2x_set_local_cmng(bp);
2662
2663         __bnx2x_link_report(bp);
2664
2665         if (IS_MF(bp))
2666                 bnx2x_link_sync_notify(bp);
2667 }
2668
2669 void bnx2x__link_status_update(struct bnx2x *bp)
2670 {
2671         if (bp->state != BNX2X_STATE_OPEN)
2672                 return;
2673
2674         /* read updated dcb configuration */
2675         if (IS_PF(bp)) {
2676                 bnx2x_dcbx_pmf_update(bp);
2677                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2678                 if (bp->link_vars.link_up)
2679                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2680                 else
2681                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2682                         /* indicate link status */
2683                 bnx2x_link_report(bp);
2684
2685         } else { /* VF */
2686                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2687                                           SUPPORTED_10baseT_Full |
2688                                           SUPPORTED_100baseT_Half |
2689                                           SUPPORTED_100baseT_Full |
2690                                           SUPPORTED_1000baseT_Full |
2691                                           SUPPORTED_2500baseX_Full |
2692                                           SUPPORTED_10000baseT_Full |
2693                                           SUPPORTED_TP |
2694                                           SUPPORTED_FIBRE |
2695                                           SUPPORTED_Autoneg |
2696                                           SUPPORTED_Pause |
2697                                           SUPPORTED_Asym_Pause);
2698                 bp->port.advertising[0] = bp->port.supported[0];
2699
2700                 bp->link_params.bp = bp;
2701                 bp->link_params.port = BP_PORT(bp);
2702                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2703                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2704                 bp->link_params.req_line_speed[0] = SPEED_10000;
2705                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2706                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2707                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2708                 bp->link_vars.line_speed = SPEED_10000;
2709                 bp->link_vars.link_status =
2710                         (LINK_STATUS_LINK_UP |
2711                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2712                 bp->link_vars.link_up = 1;
2713                 bp->link_vars.duplex = DUPLEX_FULL;
2714                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2715                 __bnx2x_link_report(bp);
2716
2717                 bnx2x_sample_bulletin(bp);
2718
2719                 /* if bulletin board did not have an update for link status
2720                  * __bnx2x_link_report will report current status
2721                  * but it will NOT duplicate report in case of already reported
2722                  * during sampling bulletin board.
2723                  */
2724                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2725         }
2726 }
2727
2728 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2729                                   u16 vlan_val, u8 allowed_prio)
2730 {
2731         struct bnx2x_func_state_params func_params = {NULL};
2732         struct bnx2x_func_afex_update_params *f_update_params =
2733                 &func_params.params.afex_update;
2734
2735         func_params.f_obj = &bp->func_obj;
2736         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2737
2738         /* no need to wait for RAMROD completion, so don't
2739          * set RAMROD_COMP_WAIT flag
2740          */
2741
2742         f_update_params->vif_id = vifid;
2743         f_update_params->afex_default_vlan = vlan_val;
2744         f_update_params->allowed_priorities = allowed_prio;
2745
2746         /* if ramrod can not be sent, response to MCP immediately */
2747         if (bnx2x_func_state_change(bp, &func_params) < 0)
2748                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2749
2750         return 0;
2751 }
2752
2753 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2754                                           u16 vif_index, u8 func_bit_map)
2755 {
2756         struct bnx2x_func_state_params func_params = {NULL};
2757         struct bnx2x_func_afex_viflists_params *update_params =
2758                 &func_params.params.afex_viflists;
2759         int rc;
2760         u32 drv_msg_code;
2761
2762         /* validate only LIST_SET and LIST_GET are received from switch */
2763         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2764                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2765                           cmd_type);
2766
2767         func_params.f_obj = &bp->func_obj;
2768         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2769
2770         /* set parameters according to cmd_type */
2771         update_params->afex_vif_list_command = cmd_type;
2772         update_params->vif_list_index = vif_index;
2773         update_params->func_bit_map =
2774                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2775         update_params->func_to_clear = 0;
2776         drv_msg_code =
2777                 (cmd_type == VIF_LIST_RULE_GET) ?
2778                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2779                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2780
2781         /* if ramrod can not be sent, respond to MCP immediately for
2782          * SET and GET requests (other are not triggered from MCP)
2783          */
2784         rc = bnx2x_func_state_change(bp, &func_params);
2785         if (rc < 0)
2786                 bnx2x_fw_command(bp, drv_msg_code, 0);
2787
2788         return 0;
2789 }
2790
2791 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2792 {
2793         struct afex_stats afex_stats;
2794         u32 func = BP_ABS_FUNC(bp);
2795         u32 mf_config;
2796         u16 vlan_val;
2797         u32 vlan_prio;
2798         u16 vif_id;
2799         u8 allowed_prio;
2800         u8 vlan_mode;
2801         u32 addr_to_write, vifid, addrs, stats_type, i;
2802
2803         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2804                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2805                 DP(BNX2X_MSG_MCP,
2806                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2807                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2808         }
2809
2810         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2811                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2812                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2813                 DP(BNX2X_MSG_MCP,
2814                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2815                    vifid, addrs);
2816                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2817                                                addrs);
2818         }
2819
2820         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2821                 addr_to_write = SHMEM2_RD(bp,
2822                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2823                 stats_type = SHMEM2_RD(bp,
2824                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2825
2826                 DP(BNX2X_MSG_MCP,
2827                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2828                    addr_to_write);
2829
2830                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2831
2832                 /* write response to scratchpad, for MCP */
2833                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2834                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2835                                *(((u32 *)(&afex_stats))+i));
2836
2837                 /* send ack message to MCP */
2838                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2839         }
2840
2841         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2842                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2843                 bp->mf_config[BP_VN(bp)] = mf_config;
2844                 DP(BNX2X_MSG_MCP,
2845                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2846                    mf_config);
2847
2848                 /* if VIF_SET is "enabled" */
2849                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2850                         /* set rate limit directly to internal RAM */
2851                         struct cmng_init_input cmng_input;
2852                         struct rate_shaping_vars_per_vn m_rs_vn;
2853                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2854                         u32 addr = BAR_XSTRORM_INTMEM +
2855                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2856
2857                         bp->mf_config[BP_VN(bp)] = mf_config;
2858
2859                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2860                         m_rs_vn.vn_counter.rate =
2861                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2862                         m_rs_vn.vn_counter.quota =
2863                                 (m_rs_vn.vn_counter.rate *
2864                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2865
2866                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2867
2868                         /* read relevant values from mf_cfg struct in shmem */
2869                         vif_id =
2870                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2872                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2873                         vlan_val =
2874                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2875                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2876                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2877                         vlan_prio = (mf_config &
2878                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2879                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2880                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2881                         vlan_mode =
2882                                 (MF_CFG_RD(bp,
2883                                            func_mf_config[func].afex_config) &
2884                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2885                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2886                         allowed_prio =
2887                                 (MF_CFG_RD(bp,
2888                                            func_mf_config[func].afex_config) &
2889                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2890                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2891
2892                         /* send ramrod to FW, return in case of failure */
2893                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2894                                                    allowed_prio))
2895                                 return;
2896
2897                         bp->afex_def_vlan_tag = vlan_val;
2898                         bp->afex_vlan_mode = vlan_mode;
2899                 } else {
2900                         /* notify link down because BP->flags is disabled */
2901                         bnx2x_link_report(bp);
2902
2903                         /* send INVALID VIF ramrod to FW */
2904                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2905
2906                         /* Reset the default afex VLAN */
2907                         bp->afex_def_vlan_tag = -1;
2908                 }
2909         }
2910 }
2911
2912 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2913 {
2914         struct bnx2x_func_switch_update_params *switch_update_params;
2915         struct bnx2x_func_state_params func_params;
2916
2917         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2918         switch_update_params = &func_params.params.switch_update;
2919         func_params.f_obj = &bp->func_obj;
2920         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2921
2922         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2923                 int func = BP_ABS_FUNC(bp);
2924                 u32 val;
2925
2926                 /* Re-learn the S-tag from shmem */
2927                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2928                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2929                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2930                         bp->mf_ov = val;
2931                 } else {
2932                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2933                         goto fail;
2934                 }
2935
2936                 /* Configure new S-tag in LLH */
2937                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2938                        bp->mf_ov);
2939
2940                 /* Send Ramrod to update FW of change */
2941                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2942                           &switch_update_params->changes);
2943                 switch_update_params->vlan = bp->mf_ov;
2944
2945                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2946                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2947                                   bp->mf_ov);
2948                         goto fail;
2949                 } else {
2950                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2951                            bp->mf_ov);
2952                 }
2953         } else {
2954                 goto fail;
2955         }
2956
2957         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2958         return;
2959 fail:
2960         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2961 }
2962
2963 static void bnx2x_pmf_update(struct bnx2x *bp)
2964 {
2965         int port = BP_PORT(bp);
2966         u32 val;
2967
2968         bp->port.pmf = 1;
2969         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2970
2971         /*
2972          * We need the mb() to ensure the ordering between the writing to
2973          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2974          */
2975         smp_mb();
2976
2977         /* queue a periodic task */
2978         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2979
2980         bnx2x_dcbx_pmf_update(bp);
2981
2982         /* enable nig attention */
2983         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2984         if (bp->common.int_block == INT_BLOCK_HC) {
2985                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2986                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2987         } else if (!CHIP_IS_E1x(bp)) {
2988                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2989                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2990         }
2991
2992         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2993 }
2994
2995 /* end of Link */
2996
2997 /* slow path */
2998
2999 /*
3000  * General service functions
3001  */
3002
3003 /* send the MCP a request, block until there is a reply */
3004 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3005 {
3006         int mb_idx = BP_FW_MB_IDX(bp);
3007         u32 seq;
3008         u32 rc = 0;
3009         u32 cnt = 1;
3010         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3011
3012         mutex_lock(&bp->fw_mb_mutex);
3013         seq = ++bp->fw_seq;
3014         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3015         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3016
3017         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3018                         (command | seq), param);
3019
3020         do {
3021                 /* let the FW do it's magic ... */
3022                 msleep(delay);
3023
3024                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3025
3026                 /* Give the FW up to 5 second (500*10ms) */
3027         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3028
3029         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3030            cnt*delay, rc, seq);
3031
3032         /* is this a reply to our command? */
3033         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3034                 rc &= FW_MSG_CODE_MASK;
3035         else {
3036                 /* FW BUG! */
3037                 BNX2X_ERR("FW failed to respond!\n");
3038                 bnx2x_fw_dump(bp);
3039                 rc = 0;
3040         }
3041         mutex_unlock(&bp->fw_mb_mutex);
3042
3043         return rc;
3044 }
3045
3046 static void storm_memset_func_cfg(struct bnx2x *bp,
3047                                  struct tstorm_eth_function_common_config *tcfg,
3048                                  u16 abs_fid)
3049 {
3050         size_t size = sizeof(struct tstorm_eth_function_common_config);
3051
3052         u32 addr = BAR_TSTRORM_INTMEM +
3053                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3054
3055         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3056 }
3057
3058 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3059 {
3060         if (CHIP_IS_E1x(bp)) {
3061                 struct tstorm_eth_function_common_config tcfg = {0};
3062
3063                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3064         }
3065
3066         /* Enable the function in the FW */
3067         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3068         storm_memset_func_en(bp, p->func_id, 1);
3069
3070         /* spq */
3071         if (p->spq_active) {
3072                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3073                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3074                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3075         }
3076 }
3077
3078 /**
3079  * bnx2x_get_common_flags - Return common flags
3080  *
3081  * @bp          device handle
3082  * @fp          queue handle
3083  * @zero_stats  TRUE if statistics zeroing is needed
3084  *
3085  * Return the flags that are common for the Tx-only and not normal connections.
3086  */
3087 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3088                                             struct bnx2x_fastpath *fp,
3089                                             bool zero_stats)
3090 {
3091         unsigned long flags = 0;
3092
3093         /* PF driver will always initialize the Queue to an ACTIVE state */
3094         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3095
3096         /* tx only connections collect statistics (on the same index as the
3097          * parent connection). The statistics are zeroed when the parent
3098          * connection is initialized.
3099          */
3100
3101         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3102         if (zero_stats)
3103                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3104
3105         if (bp->flags & TX_SWITCHING)
3106                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3107
3108         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3109         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3110
3111 #ifdef BNX2X_STOP_ON_ERROR
3112         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3113 #endif
3114
3115         return flags;
3116 }
3117
3118 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3119                                        struct bnx2x_fastpath *fp,
3120                                        bool leading)
3121 {
3122         unsigned long flags = 0;
3123
3124         /* calculate other queue flags */
3125         if (IS_MF_SD(bp))
3126                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3127
3128         if (IS_FCOE_FP(fp)) {
3129                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3130                 /* For FCoE - force usage of default priority (for afex) */
3131                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3132         }
3133
3134         if (fp->mode != TPA_MODE_DISABLED) {
3135                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3136                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3137                 if (fp->mode == TPA_MODE_GRO)
3138                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3139         }
3140
3141         if (leading) {
3142                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3143                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3144         }
3145
3146         /* Always set HW VLAN stripping */
3147         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3148
3149         /* configure silent vlan removal */
3150         if (IS_MF_AFEX(bp))
3151                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3152
3153         return flags | bnx2x_get_common_flags(bp, fp, true);
3154 }
3155
3156 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3157         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3158         u8 cos)
3159 {
3160         gen_init->stat_id = bnx2x_stats_id(fp);
3161         gen_init->spcl_id = fp->cl_id;
3162
3163         /* Always use mini-jumbo MTU for FCoE L2 ring */
3164         if (IS_FCOE_FP(fp))
3165                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3166         else
3167                 gen_init->mtu = bp->dev->mtu;
3168
3169         gen_init->cos = cos;
3170
3171         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3172 }
3173
3174 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3175         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3176         struct bnx2x_rxq_setup_params *rxq_init)
3177 {
3178         u8 max_sge = 0;
3179         u16 sge_sz = 0;
3180         u16 tpa_agg_size = 0;
3181
3182         if (fp->mode != TPA_MODE_DISABLED) {
3183                 pause->sge_th_lo = SGE_TH_LO(bp);
3184                 pause->sge_th_hi = SGE_TH_HI(bp);
3185
3186                 /* validate SGE ring has enough to cross high threshold */
3187                 WARN_ON(bp->dropless_fc &&
3188                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3189                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3190
3191                 tpa_agg_size = TPA_AGG_SIZE;
3192                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3193                         SGE_PAGE_SHIFT;
3194                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3195                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3196                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3197         }
3198
3199         /* pause - not for e1 */
3200         if (!CHIP_IS_E1(bp)) {
3201                 pause->bd_th_lo = BD_TH_LO(bp);
3202                 pause->bd_th_hi = BD_TH_HI(bp);
3203
3204                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3205                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3206                 /*
3207                  * validate that rings have enough entries to cross
3208                  * high thresholds
3209                  */
3210                 WARN_ON(bp->dropless_fc &&
3211                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3212                                 bp->rx_ring_size);
3213                 WARN_ON(bp->dropless_fc &&
3214                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3215                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3216
3217                 pause->pri_map = 1;
3218         }
3219
3220         /* rxq setup */
3221         rxq_init->dscr_map = fp->rx_desc_mapping;
3222         rxq_init->sge_map = fp->rx_sge_mapping;
3223         rxq_init->rcq_map = fp->rx_comp_mapping;
3224         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3225
3226         /* This should be a maximum number of data bytes that may be
3227          * placed on the BD (not including paddings).
3228          */
3229         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3230                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3231
3232         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3233         rxq_init->tpa_agg_sz = tpa_agg_size;
3234         rxq_init->sge_buf_sz = sge_sz;
3235         rxq_init->max_sges_pkt = max_sge;
3236         rxq_init->rss_engine_id = BP_FUNC(bp);
3237         rxq_init->mcast_engine_id = BP_FUNC(bp);
3238
3239         /* Maximum number or simultaneous TPA aggregation for this Queue.
3240          *
3241          * For PF Clients it should be the maximum available number.
3242          * VF driver(s) may want to define it to a smaller value.
3243          */
3244         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3245
3246         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3247         rxq_init->fw_sb_id = fp->fw_sb_id;
3248
3249         if (IS_FCOE_FP(fp))
3250                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3251         else
3252                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3253         /* configure silent vlan removal
3254          * if multi function mode is afex, then mask default vlan
3255          */
3256         if (IS_MF_AFEX(bp)) {
3257                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3258                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3259         }
3260 }
3261
3262 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3263         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3264         u8 cos)
3265 {
3266         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3267         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3268         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3269         txq_init->fw_sb_id = fp->fw_sb_id;
3270
3271         /*
3272          * set the tss leading client id for TX classification ==
3273          * leading RSS client id
3274          */
3275         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3276
3277         if (IS_FCOE_FP(fp)) {
3278                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3279                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3280         }
3281 }
3282
3283 static void bnx2x_pf_init(struct bnx2x *bp)
3284 {
3285         struct bnx2x_func_init_params func_init = {0};
3286         struct event_ring_data eq_data = { {0} };
3287
3288         if (!CHIP_IS_E1x(bp)) {
3289                 /* reset IGU PF statistics: MSIX + ATTN */
3290                 /* PF */
3291                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3292                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3293                            (CHIP_MODE_IS_4_PORT(bp) ?
3294                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3295                 /* ATTN */
3296                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3297                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3298                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3299                            (CHIP_MODE_IS_4_PORT(bp) ?
3300                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3301         }
3302
3303         func_init.spq_active = true;
3304         func_init.pf_id = BP_FUNC(bp);
3305         func_init.func_id = BP_FUNC(bp);
3306         func_init.spq_map = bp->spq_mapping;
3307         func_init.spq_prod = bp->spq_prod_idx;
3308
3309         bnx2x_func_init(bp, &func_init);
3310
3311         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3312
3313         /*
3314          * Congestion management values depend on the link rate
3315          * There is no active link so initial link rate is set to 10 Gbps.
3316          * When the link comes up The congestion management values are
3317          * re-calculated according to the actual link rate.
3318          */
3319         bp->link_vars.line_speed = SPEED_10000;
3320         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3321
3322         /* Only the PMF sets the HW */
3323         if (bp->port.pmf)
3324                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3325
3326         /* init Event Queue - PCI bus guarantees correct endianity*/
3327         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3328         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3329         eq_data.producer = bp->eq_prod;
3330         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3331         eq_data.sb_id = DEF_SB_ID;
3332         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3333 }
3334
3335 static void bnx2x_e1h_disable(struct bnx2x *bp)
3336 {
3337         int port = BP_PORT(bp);
3338
3339         bnx2x_tx_disable(bp);
3340
3341         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3342 }
3343
3344 static void bnx2x_e1h_enable(struct bnx2x *bp)
3345 {
3346         int port = BP_PORT(bp);
3347
3348         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3349                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3350
3351         /* Tx queue should be only re-enabled */
3352         netif_tx_wake_all_queues(bp->dev);
3353
3354         /*
3355          * Should not call netif_carrier_on since it will be called if the link
3356          * is up when checking for link state
3357          */
3358 }
3359
3360 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3361
3362 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3363 {
3364         struct eth_stats_info *ether_stat =
3365                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3366         struct bnx2x_vlan_mac_obj *mac_obj =
3367                 &bp->sp_objs->mac_obj;
3368         int i;
3369
3370         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3371                 ETH_STAT_INFO_VERSION_LEN);
3372
3373         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3374          * mac_local field in ether_stat struct. The base address is offset by 2
3375          * bytes to account for the field being 8 bytes but a mac address is
3376          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3377          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3378          * allocated by the ether_stat struct, so the macs will land in their
3379          * proper positions.
3380          */
3381         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3382                 memset(ether_stat->mac_local + i, 0,
3383                        sizeof(ether_stat->mac_local[0]));
3384         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3385                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3386                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3387                                 ETH_ALEN);
3388         ether_stat->mtu_size = bp->dev->mtu;
3389         if (bp->dev->features & NETIF_F_RXCSUM)
3390                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3391         if (bp->dev->features & NETIF_F_TSO)
3392                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3393         ether_stat->feature_flags |= bp->common.boot_mode;
3394
3395         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3396
3397         ether_stat->txq_size = bp->tx_ring_size;
3398         ether_stat->rxq_size = bp->rx_ring_size;
3399
3400 #ifdef CONFIG_BNX2X_SRIOV
3401         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3402 #endif
3403 }
3404
3405 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3406 {
3407         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3408         struct fcoe_stats_info *fcoe_stat =
3409                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3410
3411         if (!CNIC_LOADED(bp))
3412                 return;
3413
3414         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3415
3416         fcoe_stat->qos_priority =
3417                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3418
3419         /* insert FCoE stats from ramrod response */
3420         if (!NO_FCOE(bp)) {
3421                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3422                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3423                         tstorm_queue_statistics;
3424
3425                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3426                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3427                         xstorm_queue_statistics;
3428
3429                 struct fcoe_statistics_params *fw_fcoe_stat =
3430                         &bp->fw_stats_data->fcoe;
3431
3432                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3433                           fcoe_stat->rx_bytes_lo,
3434                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3435
3436                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3437                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3438                           fcoe_stat->rx_bytes_lo,
3439                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3440
3441                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3442                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3443                           fcoe_stat->rx_bytes_lo,
3444                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3445
3446                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3447                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3448                           fcoe_stat->rx_bytes_lo,
3449                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3450
3451                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3452                           fcoe_stat->rx_frames_lo,
3453                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3454
3455                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456                           fcoe_stat->rx_frames_lo,
3457                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3458
3459                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460                           fcoe_stat->rx_frames_lo,
3461                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3462
3463                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464                           fcoe_stat->rx_frames_lo,
3465                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3466
3467                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3468                           fcoe_stat->tx_bytes_lo,
3469                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3470
3471                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3472                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3473                           fcoe_stat->tx_bytes_lo,
3474                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3475
3476                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3477                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3478                           fcoe_stat->tx_bytes_lo,
3479                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3480
3481                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3482                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3483                           fcoe_stat->tx_bytes_lo,
3484                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3485
3486                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3487                           fcoe_stat->tx_frames_lo,
3488                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3489
3490                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491                           fcoe_stat->tx_frames_lo,
3492                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3493
3494                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495                           fcoe_stat->tx_frames_lo,
3496                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3497
3498                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499                           fcoe_stat->tx_frames_lo,
3500                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3501         }
3502
3503         /* ask L5 driver to add data to the struct */
3504         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3505 }
3506
3507 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3508 {
3509         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3510         struct iscsi_stats_info *iscsi_stat =
3511                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3512
3513         if (!CNIC_LOADED(bp))
3514                 return;
3515
3516         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3517                ETH_ALEN);
3518
3519         iscsi_stat->qos_priority =
3520                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3521
3522         /* ask L5 driver to add data to the struct */
3523         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3524 }
3525
3526 /* called due to MCP event (on pmf):
3527  *      reread new bandwidth configuration
3528  *      configure FW
3529  *      notify others function about the change
3530  */
3531 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3532 {
3533         if (bp->link_vars.link_up) {
3534                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3535                 bnx2x_link_sync_notify(bp);
3536         }
3537         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3538 }
3539
3540 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3541 {
3542         bnx2x_config_mf_bw(bp);
3543         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3544 }
3545
3546 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3547 {
3548         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3549         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3550 }
3551
3552 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3553 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3554
3555 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3556 {
3557         enum drv_info_opcode op_code;
3558         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3559         bool release = false;
3560         int wait;
3561
3562         /* if drv_info version supported by MFW doesn't match - send NACK */
3563         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3564                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3565                 return;
3566         }
3567
3568         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3569                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3570
3571         /* Must prevent other flows from accessing drv_info_to_mcp */
3572         mutex_lock(&bp->drv_info_mutex);
3573
3574         memset(&bp->slowpath->drv_info_to_mcp, 0,
3575                sizeof(union drv_info_to_mcp));
3576
3577         switch (op_code) {
3578         case ETH_STATS_OPCODE:
3579                 bnx2x_drv_info_ether_stat(bp);
3580                 break;
3581         case FCOE_STATS_OPCODE:
3582                 bnx2x_drv_info_fcoe_stat(bp);
3583                 break;
3584         case ISCSI_STATS_OPCODE:
3585                 bnx2x_drv_info_iscsi_stat(bp);
3586                 break;
3587         default:
3588                 /* if op code isn't supported - send NACK */
3589                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3590                 goto out;
3591         }
3592
3593         /* if we got drv_info attn from MFW then these fields are defined in
3594          * shmem2 for sure
3595          */
3596         SHMEM2_WR(bp, drv_info_host_addr_lo,
3597                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3598         SHMEM2_WR(bp, drv_info_host_addr_hi,
3599                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600
3601         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3602
3603         /* Since possible management wants both this and get_driver_version
3604          * need to wait until management notifies us it finished utilizing
3605          * the buffer.
3606          */
3607         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3608                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3609         } else if (!bp->drv_info_mng_owner) {
3610                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3611
3612                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3613                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3614
3615                         /* Management is done; need to clear indication */
3616                         if (indication & bit) {
3617                                 SHMEM2_WR(bp, mfw_drv_indication,
3618                                           indication & ~bit);
3619                                 release = true;
3620                                 break;
3621                         }
3622
3623                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3624                 }
3625         }
3626         if (!release) {
3627                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3628                 bp->drv_info_mng_owner = true;
3629         }
3630
3631 out:
3632         mutex_unlock(&bp->drv_info_mutex);
3633 }
3634
3635 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3636 {
3637         u8 vals[4];
3638         int i = 0;
3639
3640         if (bnx2x_format) {
3641                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3642                            &vals[0], &vals[1], &vals[2], &vals[3]);
3643                 if (i > 0)
3644                         vals[0] -= '0';
3645         } else {
3646                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3647                            &vals[0], &vals[1], &vals[2], &vals[3]);
3648         }
3649
3650         while (i < 4)
3651                 vals[i++] = 0;
3652
3653         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3654 }
3655
3656 void bnx2x_update_mng_version(struct bnx2x *bp)
3657 {
3658         u32 iscsiver = DRV_VER_NOT_LOADED;
3659         u32 fcoever = DRV_VER_NOT_LOADED;
3660         u32 ethver = DRV_VER_NOT_LOADED;
3661         int idx = BP_FW_MB_IDX(bp);
3662         u8 *version;
3663
3664         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3665                 return;
3666
3667         mutex_lock(&bp->drv_info_mutex);
3668         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3669         if (bp->drv_info_mng_owner)
3670                 goto out;
3671
3672         if (bp->state != BNX2X_STATE_OPEN)
3673                 goto out;
3674
3675         /* Parse ethernet driver version */
3676         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3677         if (!CNIC_LOADED(bp))
3678                 goto out;
3679
3680         /* Try getting storage driver version via cnic */
3681         memset(&bp->slowpath->drv_info_to_mcp, 0,
3682                sizeof(union drv_info_to_mcp));
3683         bnx2x_drv_info_iscsi_stat(bp);
3684         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3685         iscsiver = bnx2x_update_mng_version_utility(version, false);
3686
3687         memset(&bp->slowpath->drv_info_to_mcp, 0,
3688                sizeof(union drv_info_to_mcp));
3689         bnx2x_drv_info_fcoe_stat(bp);
3690         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3691         fcoever = bnx2x_update_mng_version_utility(version, false);
3692
3693 out:
3694         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3695         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3696         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3697
3698         mutex_unlock(&bp->drv_info_mutex);
3699
3700         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3701            ethver, iscsiver, fcoever);
3702 }
3703
3704 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3705 {
3706         u32 drv_ver;
3707         u32 valid_dump;
3708
3709         if (!SHMEM2_HAS(bp, drv_info))
3710                 return;
3711
3712         /* Update Driver load time, possibly broken in y2038 */
3713         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3714
3715         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3716         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3717
3718         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3719
3720         /* Check & notify On-Chip dump. */
3721         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3722
3723         if (valid_dump & FIRST_DUMP_VALID)
3724                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3725
3726         if (valid_dump & SECOND_DUMP_VALID)
3727                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3728 }
3729
3730 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3731 {
3732         u32 cmd_ok, cmd_fail;
3733
3734         /* sanity */
3735         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3736             event & DRV_STATUS_OEM_EVENT_MASK) {
3737                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3738                 return;
3739         }
3740
3741         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3742                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3743                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3744         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3745                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3746                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3747         }
3748
3749         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3750
3751         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3752                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3753                 /* This is the only place besides the function initialization
3754                  * where the bp->flags can change so it is done without any
3755                  * locks
3756                  */
3757                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3758                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3759                         bp->flags |= MF_FUNC_DIS;
3760
3761                         bnx2x_e1h_disable(bp);
3762                 } else {
3763                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3764                         bp->flags &= ~MF_FUNC_DIS;
3765
3766                         bnx2x_e1h_enable(bp);
3767                 }
3768                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3769                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3770         }
3771
3772         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3773                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3774                 bnx2x_config_mf_bw(bp);
3775                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3776                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3777         }
3778
3779         /* Report results to MCP */
3780         if (event)
3781                 bnx2x_fw_command(bp, cmd_fail, 0);
3782         else
3783                 bnx2x_fw_command(bp, cmd_ok, 0);
3784 }
3785
3786 /* must be called under the spq lock */
3787 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3788 {
3789         struct eth_spe *next_spe = bp->spq_prod_bd;
3790
3791         if (bp->spq_prod_bd == bp->spq_last_bd) {
3792                 bp->spq_prod_bd = bp->spq;
3793                 bp->spq_prod_idx = 0;
3794                 DP(BNX2X_MSG_SP, "end of spq\n");
3795         } else {
3796                 bp->spq_prod_bd++;
3797                 bp->spq_prod_idx++;
3798         }
3799         return next_spe;
3800 }
3801
3802 /* must be called under the spq lock */
3803 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3804 {
3805         int func = BP_FUNC(bp);
3806
3807         /*
3808          * Make sure that BD data is updated before writing the producer:
3809          * BD data is written to the memory, the producer is read from the
3810          * memory, thus we need a full memory barrier to ensure the ordering.
3811          */
3812         mb();
3813
3814         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3815                  bp->spq_prod_idx);
3816         mmiowb();
3817 }
3818
3819 /**
3820  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3821  *
3822  * @cmd:        command to check
3823  * @cmd_type:   command type
3824  */
3825 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3826 {
3827         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3828             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3829             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3830             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3831             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3832             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3833             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3834                 return true;
3835         else
3836                 return false;
3837 }
3838
3839 /**
3840  * bnx2x_sp_post - place a single command on an SP ring
3841  *
3842  * @bp:         driver handle
3843  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3844  * @cid:        SW CID the command is related to
3845  * @data_hi:    command private data address (high 32 bits)
3846  * @data_lo:    command private data address (low 32 bits)
3847  * @cmd_type:   command type (e.g. NONE, ETH)
3848  *
3849  * SP data is handled as if it's always an address pair, thus data fields are
3850  * not swapped to little endian in upper functions. Instead this function swaps
3851  * data as if it's two u32 fields.
3852  */
3853 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3854                   u32 data_hi, u32 data_lo, int cmd_type)
3855 {
3856         struct eth_spe *spe;
3857         u16 type;
3858         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3859
3860 #ifdef BNX2X_STOP_ON_ERROR
3861         if (unlikely(bp->panic)) {
3862                 BNX2X_ERR("Can't post SP when there is panic\n");
3863                 return -EIO;
3864         }
3865 #endif
3866
3867         spin_lock_bh(&bp->spq_lock);
3868
3869         if (common) {
3870                 if (!atomic_read(&bp->eq_spq_left)) {
3871                         BNX2X_ERR("BUG! EQ ring full!\n");
3872                         spin_unlock_bh(&bp->spq_lock);
3873                         bnx2x_panic();
3874                         return -EBUSY;
3875                 }
3876         } else if (!atomic_read(&bp->cq_spq_left)) {
3877                         BNX2X_ERR("BUG! SPQ ring full!\n");
3878                         spin_unlock_bh(&bp->spq_lock);
3879                         bnx2x_panic();
3880                         return -EBUSY;
3881         }
3882
3883         spe = bnx2x_sp_get_next(bp);
3884
3885         /* CID needs port number to be encoded int it */
3886         spe->hdr.conn_and_cmd_data =
3887                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3888                                     HW_CID(bp, cid));
3889
3890         /* In some cases, type may already contain the func-id
3891          * mainly in SRIOV related use cases, so we add it here only
3892          * if it's not already set.
3893          */
3894         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3895                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3896                         SPE_HDR_CONN_TYPE;
3897                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3898                          SPE_HDR_FUNCTION_ID);
3899         } else {
3900                 type = cmd_type;
3901         }
3902
3903         spe->hdr.type = cpu_to_le16(type);
3904
3905         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3906         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3907
3908         /*
3909          * It's ok if the actual decrement is issued towards the memory
3910          * somewhere between the spin_lock and spin_unlock. Thus no
3911          * more explicit memory barrier is needed.
3912          */
3913         if (common)
3914                 atomic_dec(&bp->eq_spq_left);
3915         else
3916                 atomic_dec(&bp->cq_spq_left);
3917
3918         DP(BNX2X_MSG_SP,
3919            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3920            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3921            (u32)(U64_LO(bp->spq_mapping) +
3922            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3923            HW_CID(bp, cid), data_hi, data_lo, type,
3924            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3925
3926         bnx2x_sp_prod_update(bp);
3927         spin_unlock_bh(&bp->spq_lock);
3928         return 0;
3929 }
3930
3931 /* acquire split MCP access lock register */
3932 static int bnx2x_acquire_alr(struct bnx2x *bp)
3933 {
3934         u32 j, val;
3935         int rc = 0;
3936
3937         might_sleep();
3938         for (j = 0; j < 1000; j++) {
3939                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3940                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3941                 if (val & MCPR_ACCESS_LOCK_LOCK)
3942                         break;
3943
3944                 usleep_range(5000, 10000);
3945         }
3946         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3947                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3948                 rc = -EBUSY;
3949         }
3950
3951         return rc;
3952 }
3953
3954 /* release split MCP access lock register */
3955 static void bnx2x_release_alr(struct bnx2x *bp)
3956 {
3957         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3958 }
3959
3960 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3961 #define BNX2X_DEF_SB_IDX        0x0002
3962
3963 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3964 {
3965         struct host_sp_status_block *def_sb = bp->def_status_blk;
3966         u16 rc = 0;
3967
3968         barrier(); /* status block is written to by the chip */
3969         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3970                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3971                 rc |= BNX2X_DEF_SB_ATT_IDX;
3972         }
3973
3974         if (bp->def_idx != def_sb->sp_sb.running_index) {
3975                 bp->def_idx = def_sb->sp_sb.running_index;
3976                 rc |= BNX2X_DEF_SB_IDX;
3977         }
3978
3979         /* Do not reorder: indices reading should complete before handling */
3980         barrier();
3981         return rc;
3982 }
3983
3984 /*
3985  * slow path service functions
3986  */
3987
3988 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3989 {
3990         int port = BP_PORT(bp);
3991         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3992                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3993         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3994                                        NIG_REG_MASK_INTERRUPT_PORT0;
3995         u32 aeu_mask;
3996         u32 nig_mask = 0;
3997         u32 reg_addr;
3998
3999         if (bp->attn_state & asserted)
4000                 BNX2X_ERR("IGU ERROR\n");
4001
4002         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4003         aeu_mask = REG_RD(bp, aeu_addr);
4004
4005         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4006            aeu_mask, asserted);
4007         aeu_mask &= ~(asserted & 0x3ff);
4008         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4009
4010         REG_WR(bp, aeu_addr, aeu_mask);
4011         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4012
4013         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4014         bp->attn_state |= asserted;
4015         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4016
4017         if (asserted & ATTN_HARD_WIRED_MASK) {
4018                 if (asserted & ATTN_NIG_FOR_FUNC) {
4019
4020                         bnx2x_acquire_phy_lock(bp);
4021
4022                         /* save nig interrupt mask */
4023                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4024
4025                         /* If nig_mask is not set, no need to call the update
4026                          * function.
4027                          */
4028                         if (nig_mask) {
4029                                 REG_WR(bp, nig_int_mask_addr, 0);
4030
4031                                 bnx2x_link_attn(bp);
4032                         }
4033
4034                         /* handle unicore attn? */
4035                 }
4036                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4037                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4038
4039                 if (asserted & GPIO_2_FUNC)
4040                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4041
4042                 if (asserted & GPIO_3_FUNC)
4043                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4044
4045                 if (asserted & GPIO_4_FUNC)
4046                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4047
4048                 if (port == 0) {
4049                         if (asserted & ATTN_GENERAL_ATTN_1) {
4050                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4051                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4052                         }
4053                         if (asserted & ATTN_GENERAL_ATTN_2) {
4054                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4055                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4056                         }
4057                         if (asserted & ATTN_GENERAL_ATTN_3) {
4058                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4059                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4060                         }
4061                 } else {
4062                         if (asserted & ATTN_GENERAL_ATTN_4) {
4063                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4064                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4065                         }
4066                         if (asserted & ATTN_GENERAL_ATTN_5) {
4067                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4068                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4069                         }
4070                         if (asserted & ATTN_GENERAL_ATTN_6) {
4071                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4072                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4073                         }
4074                 }
4075
4076         } /* if hardwired */
4077
4078         if (bp->common.int_block == INT_BLOCK_HC)
4079                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4080                             COMMAND_REG_ATTN_BITS_SET);
4081         else
4082                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4083
4084         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4085            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4086         REG_WR(bp, reg_addr, asserted);
4087
4088         /* now set back the mask */
4089         if (asserted & ATTN_NIG_FOR_FUNC) {
4090                 /* Verify that IGU ack through BAR was written before restoring
4091                  * NIG mask. This loop should exit after 2-3 iterations max.
4092                  */
4093                 if (bp->common.int_block != INT_BLOCK_HC) {
4094                         u32 cnt = 0, igu_acked;
4095                         do {
4096                                 igu_acked = REG_RD(bp,
4097                                                    IGU_REG_ATTENTION_ACK_BITS);
4098                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4099                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4100                         if (!igu_acked)
4101                                 DP(NETIF_MSG_HW,
4102                                    "Failed to verify IGU ack on time\n");
4103                         barrier();
4104                 }
4105                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4106                 bnx2x_release_phy_lock(bp);
4107         }
4108 }
4109
4110 static void bnx2x_fan_failure(struct bnx2x *bp)
4111 {
4112         int port = BP_PORT(bp);
4113         u32 ext_phy_config;
4114         /* mark the failure */
4115         ext_phy_config =
4116                 SHMEM_RD(bp,
4117                          dev_info.port_hw_config[port].external_phy_config);
4118
4119         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4120         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4121         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4122                  ext_phy_config);
4123
4124         /* log the failure */
4125         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4126                             "Please contact OEM Support for assistance\n");
4127
4128         /* Schedule device reset (unload)
4129          * This is due to some boards consuming sufficient power when driver is
4130          * up to overheat if fan fails.
4131          */
4132         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4133 }
4134
4135 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4136 {
4137         int port = BP_PORT(bp);
4138         int reg_offset;
4139         u32 val;
4140
4141         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4142                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4143
4144         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4145
4146                 val = REG_RD(bp, reg_offset);
4147                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4148                 REG_WR(bp, reg_offset, val);
4149
4150                 BNX2X_ERR("SPIO5 hw attention\n");
4151
4152                 /* Fan failure attention */
4153                 bnx2x_hw_reset_phy(&bp->link_params);
4154                 bnx2x_fan_failure(bp);
4155         }
4156
4157         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4158                 bnx2x_acquire_phy_lock(bp);
4159                 bnx2x_handle_module_detect_int(&bp->link_params);
4160                 bnx2x_release_phy_lock(bp);
4161         }
4162
4163         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4164
4165                 val = REG_RD(bp, reg_offset);
4166                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4167                 REG_WR(bp, reg_offset, val);
4168
4169                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4170                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4171                 bnx2x_panic();
4172         }
4173 }
4174
4175 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4176 {
4177         u32 val;
4178
4179         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4180
4181                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4182                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4183                 /* DORQ discard attention */
4184                 if (val & 0x2)
4185                         BNX2X_ERR("FATAL error from DORQ\n");
4186         }
4187
4188         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4189
4190                 int port = BP_PORT(bp);
4191                 int reg_offset;
4192
4193                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4194                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4195
4196                 val = REG_RD(bp, reg_offset);
4197                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4198                 REG_WR(bp, reg_offset, val);
4199
4200                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4201                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4202                 bnx2x_panic();
4203         }
4204 }
4205
4206 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4207 {
4208         u32 val;
4209
4210         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4211
4212                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4213                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4214                 /* CFC error attention */
4215                 if (val & 0x2)
4216                         BNX2X_ERR("FATAL error from CFC\n");
4217         }
4218
4219         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4220                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4221                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4222                 /* RQ_USDMDP_FIFO_OVERFLOW */
4223                 if (val & 0x18000)
4224                         BNX2X_ERR("FATAL error from PXP\n");
4225
4226                 if (!CHIP_IS_E1x(bp)) {
4227                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4228                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4229                 }
4230         }
4231
4232         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4233
4234                 int port = BP_PORT(bp);
4235                 int reg_offset;
4236
4237                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4238                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4239
4240                 val = REG_RD(bp, reg_offset);
4241                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4242                 REG_WR(bp, reg_offset, val);
4243
4244                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4245                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4246                 bnx2x_panic();
4247         }
4248 }
4249
4250 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4251 {
4252         u32 val;
4253
4254         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4255
4256                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4257                         int func = BP_FUNC(bp);
4258
4259                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4260                         bnx2x_read_mf_cfg(bp);
4261                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4262                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4263                         val = SHMEM_RD(bp,
4264                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4265
4266                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4267                                    DRV_STATUS_OEM_EVENT_MASK))
4268                                 bnx2x_oem_event(bp,
4269                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4270                                                 DRV_STATUS_OEM_EVENT_MASK)));
4271
4272                         if (val & DRV_STATUS_SET_MF_BW)
4273                                 bnx2x_set_mf_bw(bp);
4274
4275                         if (val & DRV_STATUS_DRV_INFO_REQ)
4276                                 bnx2x_handle_drv_info_req(bp);
4277
4278                         if (val & DRV_STATUS_VF_DISABLED)
4279                                 bnx2x_schedule_iov_task(bp,
4280                                                         BNX2X_IOV_HANDLE_FLR);
4281
4282                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4283                                 bnx2x_pmf_update(bp);
4284
4285                         if (bp->port.pmf &&
4286                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4287                                 bp->dcbx_enabled > 0)
4288                                 /* start dcbx state machine */
4289                                 bnx2x_dcbx_set_params(bp,
4290                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4291                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4292                                 bnx2x_handle_afex_cmd(bp,
4293                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4294                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4295                                 bnx2x_handle_eee_event(bp);
4296
4297                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4298                                 bnx2x_handle_update_svid_cmd(bp);
4299
4300                         if (bp->link_vars.periodic_flags &
4301                             PERIODIC_FLAGS_LINK_EVENT) {
4302                                 /*  sync with link */
4303                                 bnx2x_acquire_phy_lock(bp);
4304                                 bp->link_vars.periodic_flags &=
4305                                         ~PERIODIC_FLAGS_LINK_EVENT;
4306                                 bnx2x_release_phy_lock(bp);
4307                                 if (IS_MF(bp))
4308                                         bnx2x_link_sync_notify(bp);
4309                                 bnx2x_link_report(bp);
4310                         }
4311                         /* Always call it here: bnx2x_link_report() will
4312                          * prevent the link indication duplication.
4313                          */
4314                         bnx2x__link_status_update(bp);
4315                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4316
4317                         BNX2X_ERR("MC assert!\n");
4318                         bnx2x_mc_assert(bp);
4319                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4320                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4321                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4322                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4323                         bnx2x_panic();
4324
4325                 } else if (attn & BNX2X_MCP_ASSERT) {
4326
4327                         BNX2X_ERR("MCP assert!\n");
4328                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4329                         bnx2x_fw_dump(bp);
4330
4331                 } else
4332                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4333         }
4334
4335         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4336                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4337                 if (attn & BNX2X_GRC_TIMEOUT) {
4338                         val = CHIP_IS_E1(bp) ? 0 :
4339                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4340                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4341                 }
4342                 if (attn & BNX2X_GRC_RSV) {
4343                         val = CHIP_IS_E1(bp) ? 0 :
4344                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4345                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4346                 }
4347                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4348         }
4349 }
4350
4351 /*
4352  * Bits map:
4353  * 0-7   - Engine0 load counter.
4354  * 8-15  - Engine1 load counter.
4355  * 16    - Engine0 RESET_IN_PROGRESS bit.
4356  * 17    - Engine1 RESET_IN_PROGRESS bit.
4357  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4358  *         on the engine
4359  * 19    - Engine1 ONE_IS_LOADED.
4360  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4361  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4362  *         just the one belonging to its engine).
4363  *
4364  */
4365 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4366
4367 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4368 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4369 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4370 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4371 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4372 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4373 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4374
4375 /*
4376  * Set the GLOBAL_RESET bit.
4377  *
4378  * Should be run under rtnl lock
4379  */
4380 void bnx2x_set_reset_global(struct bnx2x *bp)
4381 {
4382         u32 val;
4383         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4384         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4385         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4386         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4387 }
4388
4389 /*
4390  * Clear the GLOBAL_RESET bit.
4391  *
4392  * Should be run under rtnl lock
4393  */
4394 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4395 {
4396         u32 val;
4397         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4398         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4399         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4400         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4401 }
4402
4403 /*
4404  * Checks the GLOBAL_RESET bit.
4405  *
4406  * should be run under rtnl lock
4407  */
4408 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4409 {
4410         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4411
4412         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4413         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4414 }
4415
4416 /*
4417  * Clear RESET_IN_PROGRESS bit for the current engine.
4418  *
4419  * Should be run under rtnl lock
4420  */
4421 static void bnx2x_set_reset_done(struct bnx2x *bp)
4422 {
4423         u32 val;
4424         u32 bit = BP_PATH(bp) ?
4425                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4426         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4427         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4428
4429         /* Clear the bit */
4430         val &= ~bit;
4431         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4432
4433         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4434 }
4435
4436 /*
4437  * Set RESET_IN_PROGRESS for the current engine.
4438  *
4439  * should be run under rtnl lock
4440  */
4441 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4442 {
4443         u32 val;
4444         u32 bit = BP_PATH(bp) ?
4445                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4446         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4447         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4448
4449         /* Set the bit */
4450         val |= bit;
4451         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4452         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4453 }
4454
4455 /*
4456  * Checks the RESET_IN_PROGRESS bit for the given engine.
4457  * should be run under rtnl lock
4458  */
4459 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4460 {
4461         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4462         u32 bit = engine ?
4463                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4464
4465         /* return false if bit is set */
4466         return (val & bit) ? false : true;
4467 }
4468
4469 /*
4470  * set pf load for the current pf.
4471  *
4472  * should be run under rtnl lock
4473  */
4474 void bnx2x_set_pf_load(struct bnx2x *bp)
4475 {
4476         u32 val1, val;
4477         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4478                              BNX2X_PATH0_LOAD_CNT_MASK;
4479         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4480                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4481
4482         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4483         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4484
4485         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4486
4487         /* get the current counter value */
4488         val1 = (val & mask) >> shift;
4489
4490         /* set bit of that PF */
4491         val1 |= (1 << bp->pf_num);
4492
4493         /* clear the old value */
4494         val &= ~mask;
4495
4496         /* set the new one */
4497         val |= ((val1 << shift) & mask);
4498
4499         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4500         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4501 }
4502
4503 /**
4504  * bnx2x_clear_pf_load - clear pf load mark
4505  *
4506  * @bp:         driver handle
4507  *
4508  * Should be run under rtnl lock.
4509  * Decrements the load counter for the current engine. Returns
4510  * whether other functions are still loaded
4511  */
4512 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4513 {
4514         u32 val1, val;
4515         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4516                              BNX2X_PATH0_LOAD_CNT_MASK;
4517         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4518                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4519
4520         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4521         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4522         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4523
4524         /* get the current counter value */
4525         val1 = (val & mask) >> shift;
4526
4527         /* clear bit of that PF */
4528         val1 &= ~(1 << bp->pf_num);
4529
4530         /* clear the old value */
4531         val &= ~mask;
4532
4533         /* set the new one */
4534         val |= ((val1 << shift) & mask);
4535
4536         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4537         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4538         return val1 != 0;
4539 }
4540
4541 /*
4542  * Read the load status for the current engine.
4543  *
4544  * should be run under rtnl lock
4545  */
4546 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4547 {
4548         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4549                              BNX2X_PATH0_LOAD_CNT_MASK);
4550         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4551                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4552         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4553
4554         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4555
4556         val = (val & mask) >> shift;
4557
4558         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4559            engine, val);
4560
4561         return val != 0;
4562 }
4563
4564 static void _print_parity(struct bnx2x *bp, u32 reg)
4565 {
4566         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4567 }
4568
4569 static void _print_next_block(int idx, const char *blk)
4570 {
4571         pr_cont("%s%s", idx ? ", " : "", blk);
4572 }
4573
4574 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4575                                             int *par_num, bool print)
4576 {
4577         u32 cur_bit;
4578         bool res;
4579         int i;
4580
4581         res = false;
4582
4583         for (i = 0; sig; i++) {
4584                 cur_bit = (0x1UL << i);
4585                 if (sig & cur_bit) {
4586                         res |= true; /* Each bit is real error! */
4587
4588                         if (print) {
4589                                 switch (cur_bit) {
4590                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4591                                         _print_next_block((*par_num)++, "BRB");
4592                                         _print_parity(bp,
4593                                                       BRB1_REG_BRB1_PRTY_STS);
4594                                         break;
4595                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4596                                         _print_next_block((*par_num)++,
4597                                                           "PARSER");
4598                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4599                                         break;
4600                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4601                                         _print_next_block((*par_num)++, "TSDM");
4602                                         _print_parity(bp,
4603                                                       TSDM_REG_TSDM_PRTY_STS);
4604                                         break;
4605                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4606                                         _print_next_block((*par_num)++,
4607                                                           "SEARCHER");
4608                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4609                                         break;
4610                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4611                                         _print_next_block((*par_num)++, "TCM");
4612                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4613                                         break;
4614                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4615                                         _print_next_block((*par_num)++,
4616                                                           "TSEMI");
4617                                         _print_parity(bp,
4618                                                       TSEM_REG_TSEM_PRTY_STS_0);
4619                                         _print_parity(bp,
4620                                                       TSEM_REG_TSEM_PRTY_STS_1);
4621                                         break;
4622                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4623                                         _print_next_block((*par_num)++, "XPB");
4624                                         _print_parity(bp, GRCBASE_XPB +
4625                                                           PB_REG_PB_PRTY_STS);
4626                                         break;
4627                                 }
4628                         }
4629
4630                         /* Clear the bit */
4631                         sig &= ~cur_bit;
4632                 }
4633         }
4634
4635         return res;
4636 }
4637
4638 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4639                                             int *par_num, bool *global,
4640                                             bool print)
4641 {
4642         u32 cur_bit;
4643         bool res;
4644         int i;
4645
4646         res = false;
4647
4648         for (i = 0; sig; i++) {
4649                 cur_bit = (0x1UL << i);
4650                 if (sig & cur_bit) {
4651                         res |= true; /* Each bit is real error! */
4652                         switch (cur_bit) {
4653                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4654                                 if (print) {
4655                                         _print_next_block((*par_num)++, "PBF");
4656                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4657                                 }
4658                                 break;
4659                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4660                                 if (print) {
4661                                         _print_next_block((*par_num)++, "QM");
4662                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4663                                 }
4664                                 break;
4665                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4666                                 if (print) {
4667                                         _print_next_block((*par_num)++, "TM");
4668                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4669                                 }
4670                                 break;
4671                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4672                                 if (print) {
4673                                         _print_next_block((*par_num)++, "XSDM");
4674                                         _print_parity(bp,
4675                                                       XSDM_REG_XSDM_PRTY_STS);
4676                                 }
4677                                 break;
4678                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4679                                 if (print) {
4680                                         _print_next_block((*par_num)++, "XCM");
4681                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4682                                 }
4683                                 break;
4684                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4685                                 if (print) {
4686                                         _print_next_block((*par_num)++,
4687                                                           "XSEMI");
4688                                         _print_parity(bp,
4689                                                       XSEM_REG_XSEM_PRTY_STS_0);
4690                                         _print_parity(bp,
4691                                                       XSEM_REG_XSEM_PRTY_STS_1);
4692                                 }
4693                                 break;
4694                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4695                                 if (print) {
4696                                         _print_next_block((*par_num)++,
4697                                                           "DOORBELLQ");
4698                                         _print_parity(bp,
4699                                                       DORQ_REG_DORQ_PRTY_STS);
4700                                 }
4701                                 break;
4702                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4703                                 if (print) {
4704                                         _print_next_block((*par_num)++, "NIG");
4705                                         if (CHIP_IS_E1x(bp)) {
4706                                                 _print_parity(bp,
4707                                                         NIG_REG_NIG_PRTY_STS);
4708                                         } else {
4709                                                 _print_parity(bp,
4710                                                         NIG_REG_NIG_PRTY_STS_0);
4711                                                 _print_parity(bp,
4712                                                         NIG_REG_NIG_PRTY_STS_1);
4713                                         }
4714                                 }
4715                                 break;
4716                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4717                                 if (print)
4718                                         _print_next_block((*par_num)++,
4719                                                           "VAUX PCI CORE");
4720                                 *global = true;
4721                                 break;
4722                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4723                                 if (print) {
4724                                         _print_next_block((*par_num)++,
4725                                                           "DEBUG");
4726                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4727                                 }
4728                                 break;
4729                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4730                                 if (print) {
4731                                         _print_next_block((*par_num)++, "USDM");
4732                                         _print_parity(bp,
4733                                                       USDM_REG_USDM_PRTY_STS);
4734                                 }
4735                                 break;
4736                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4737                                 if (print) {
4738                                         _print_next_block((*par_num)++, "UCM");
4739                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4740                                 }
4741                                 break;
4742                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4743                                 if (print) {
4744                                         _print_next_block((*par_num)++,
4745                                                           "USEMI");
4746                                         _print_parity(bp,
4747                                                       USEM_REG_USEM_PRTY_STS_0);
4748                                         _print_parity(bp,
4749                                                       USEM_REG_USEM_PRTY_STS_1);
4750                                 }
4751                                 break;
4752                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4753                                 if (print) {
4754                                         _print_next_block((*par_num)++, "UPB");
4755                                         _print_parity(bp, GRCBASE_UPB +
4756                                                           PB_REG_PB_PRTY_STS);
4757                                 }
4758                                 break;
4759                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4760                                 if (print) {
4761                                         _print_next_block((*par_num)++, "CSDM");
4762                                         _print_parity(bp,
4763                                                       CSDM_REG_CSDM_PRTY_STS);
4764                                 }
4765                                 break;
4766                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4767                                 if (print) {
4768                                         _print_next_block((*par_num)++, "CCM");
4769                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4770                                 }
4771                                 break;
4772                         }
4773
4774                         /* Clear the bit */
4775                         sig &= ~cur_bit;
4776                 }
4777         }
4778
4779         return res;
4780 }
4781
4782 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4783                                             int *par_num, bool print)
4784 {
4785         u32 cur_bit;
4786         bool res;
4787         int i;
4788
4789         res = false;
4790
4791         for (i = 0; sig; i++) {
4792                 cur_bit = (0x1UL << i);
4793                 if (sig & cur_bit) {
4794                         res = true; /* Each bit is real error! */
4795                         if (print) {
4796                                 switch (cur_bit) {
4797                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4798                                         _print_next_block((*par_num)++,
4799                                                           "CSEMI");
4800                                         _print_parity(bp,
4801                                                       CSEM_REG_CSEM_PRTY_STS_0);
4802                                         _print_parity(bp,
4803                                                       CSEM_REG_CSEM_PRTY_STS_1);
4804                                         break;
4805                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4806                                         _print_next_block((*par_num)++, "PXP");
4807                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4808                                         _print_parity(bp,
4809                                                       PXP2_REG_PXP2_PRTY_STS_0);
4810                                         _print_parity(bp,
4811                                                       PXP2_REG_PXP2_PRTY_STS_1);
4812                                         break;
4813                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4814                                         _print_next_block((*par_num)++,
4815                                                           "PXPPCICLOCKCLIENT");
4816                                         break;
4817                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4818                                         _print_next_block((*par_num)++, "CFC");
4819                                         _print_parity(bp,
4820                                                       CFC_REG_CFC_PRTY_STS);
4821                                         break;
4822                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4823                                         _print_next_block((*par_num)++, "CDU");
4824                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4825                                         break;
4826                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4827                                         _print_next_block((*par_num)++, "DMAE");
4828                                         _print_parity(bp,
4829                                                       DMAE_REG_DMAE_PRTY_STS);
4830                                         break;
4831                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4832                                         _print_next_block((*par_num)++, "IGU");
4833                                         if (CHIP_IS_E1x(bp))
4834                                                 _print_parity(bp,
4835                                                         HC_REG_HC_PRTY_STS);
4836                                         else
4837                                                 _print_parity(bp,
4838                                                         IGU_REG_IGU_PRTY_STS);
4839                                         break;
4840                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4841                                         _print_next_block((*par_num)++, "MISC");
4842                                         _print_parity(bp,
4843                                                       MISC_REG_MISC_PRTY_STS);
4844                                         break;
4845                                 }
4846                         }
4847
4848                         /* Clear the bit */
4849                         sig &= ~cur_bit;
4850                 }
4851         }
4852
4853         return res;
4854 }
4855
4856 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4857                                             int *par_num, bool *global,
4858                                             bool print)
4859 {
4860         bool res = false;
4861         u32 cur_bit;
4862         int i;
4863
4864         for (i = 0; sig; i++) {
4865                 cur_bit = (0x1UL << i);
4866                 if (sig & cur_bit) {
4867                         switch (cur_bit) {
4868                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4869                                 if (print)
4870                                         _print_next_block((*par_num)++,
4871                                                           "MCP ROM");
4872                                 *global = true;
4873                                 res = true;
4874                                 break;
4875                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4876                                 if (print)
4877                                         _print_next_block((*par_num)++,
4878                                                           "MCP UMP RX");
4879                                 *global = true;
4880                                 res = true;
4881                                 break;
4882                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4883                                 if (print)
4884                                         _print_next_block((*par_num)++,
4885                                                           "MCP UMP TX");
4886                                 *global = true;
4887                                 res = true;
4888                                 break;
4889                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4890                                 (*par_num)++;
4891                                 /* clear latched SCPAD PATIRY from MCP */
4892                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4893                                        1UL << 10);
4894                                 break;
4895                         }
4896
4897                         /* Clear the bit */
4898                         sig &= ~cur_bit;
4899                 }
4900         }
4901
4902         return res;
4903 }
4904
4905 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4906                                             int *par_num, bool print)
4907 {
4908         u32 cur_bit;
4909         bool res;
4910         int i;
4911
4912         res = false;
4913
4914         for (i = 0; sig; i++) {
4915                 cur_bit = (0x1UL << i);
4916                 if (sig & cur_bit) {
4917                         res = true; /* Each bit is real error! */
4918                         if (print) {
4919                                 switch (cur_bit) {
4920                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4921                                         _print_next_block((*par_num)++,
4922                                                           "PGLUE_B");
4923                                         _print_parity(bp,
4924                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4925                                         break;
4926                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4927                                         _print_next_block((*par_num)++, "ATC");
4928                                         _print_parity(bp,
4929                                                       ATC_REG_ATC_PRTY_STS);
4930                                         break;
4931                                 }
4932                         }
4933                         /* Clear the bit */
4934                         sig &= ~cur_bit;
4935                 }
4936         }
4937
4938         return res;
4939 }
4940
4941 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4942                               u32 *sig)
4943 {
4944         bool res = false;
4945
4946         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4947             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4948             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4949             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4950             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4951                 int par_num = 0;
4952
4953                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4954                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4955                           sig[0] & HW_PRTY_ASSERT_SET_0,
4956                           sig[1] & HW_PRTY_ASSERT_SET_1,
4957                           sig[2] & HW_PRTY_ASSERT_SET_2,
4958                           sig[3] & HW_PRTY_ASSERT_SET_3,
4959                           sig[4] & HW_PRTY_ASSERT_SET_4);
4960                 if (print) {
4961                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4962                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4963                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4964                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4965                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4966                                 netdev_err(bp->dev,
4967                                            "Parity errors detected in blocks: ");
4968                         } else {
4969                                 print = false;
4970                         }
4971                 }
4972                 res |= bnx2x_check_blocks_with_parity0(bp,
4973                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4974                 res |= bnx2x_check_blocks_with_parity1(bp,
4975                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4976                 res |= bnx2x_check_blocks_with_parity2(bp,
4977                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4978                 res |= bnx2x_check_blocks_with_parity3(bp,
4979                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4980                 res |= bnx2x_check_blocks_with_parity4(bp,
4981                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4982
4983                 if (print)
4984                         pr_cont("\n");
4985         }
4986
4987         return res;
4988 }
4989
4990 /**
4991  * bnx2x_chk_parity_attn - checks for parity attentions.
4992  *
4993  * @bp:         driver handle
4994  * @global:     true if there was a global attention
4995  * @print:      show parity attention in syslog
4996  */
4997 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4998 {
4999         struct attn_route attn = { {0} };
5000         int port = BP_PORT(bp);
5001
5002         attn.sig[0] = REG_RD(bp,
5003                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5004                              port*4);
5005         attn.sig[1] = REG_RD(bp,
5006                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5007                              port*4);
5008         attn.sig[2] = REG_RD(bp,
5009                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5010                              port*4);
5011         attn.sig[3] = REG_RD(bp,
5012                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5013                              port*4);
5014         /* Since MCP attentions can't be disabled inside the block, we need to
5015          * read AEU registers to see whether they're currently disabled
5016          */
5017         attn.sig[3] &= ((REG_RD(bp,
5018                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5019                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5020                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5021                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5022
5023         if (!CHIP_IS_E1x(bp))
5024                 attn.sig[4] = REG_RD(bp,
5025                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5026                                      port*4);
5027
5028         return bnx2x_parity_attn(bp, global, print, attn.sig);
5029 }
5030
5031 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5032 {
5033         u32 val;
5034         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5035
5036                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5037                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5038                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5039                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5040                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5041                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5042                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5043                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5044                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5045                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5046                 if (val &
5047                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5048                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5049                 if (val &
5050                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5051                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5052                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5053                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5054                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5055                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5056                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5057                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5058         }
5059         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5060                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5061                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5062                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5063                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5064                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5065                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5066                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5067                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5068                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5069                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5070                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5071                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5072                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5073                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5074         }
5075
5076         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5077                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5078                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5079                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5080                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5081         }
5082 }
5083
5084 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5085 {
5086         struct attn_route attn, *group_mask;
5087         int port = BP_PORT(bp);
5088         int index;
5089         u32 reg_addr;
5090         u32 val;
5091         u32 aeu_mask;
5092         bool global = false;
5093
5094         /* need to take HW lock because MCP or other port might also
5095            try to handle this event */
5096         bnx2x_acquire_alr(bp);
5097
5098         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5099 #ifndef BNX2X_STOP_ON_ERROR
5100                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5101                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5102                 /* Disable HW interrupts */
5103                 bnx2x_int_disable(bp);
5104                 /* In case of parity errors don't handle attentions so that
5105                  * other function would "see" parity errors.
5106                  */
5107 #else
5108                 bnx2x_panic();
5109 #endif
5110                 bnx2x_release_alr(bp);
5111                 return;
5112         }
5113
5114         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5115         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5116         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5117         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5118         if (!CHIP_IS_E1x(bp))
5119                 attn.sig[4] =
5120                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5121         else
5122                 attn.sig[4] = 0;
5123
5124         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5125            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5126
5127         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5128                 if (deasserted & (1 << index)) {
5129                         group_mask = &bp->attn_group[index];
5130
5131                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5132                            index,
5133                            group_mask->sig[0], group_mask->sig[1],
5134                            group_mask->sig[2], group_mask->sig[3],
5135                            group_mask->sig[4]);
5136
5137                         bnx2x_attn_int_deasserted4(bp,
5138                                         attn.sig[4] & group_mask->sig[4]);
5139                         bnx2x_attn_int_deasserted3(bp,
5140                                         attn.sig[3] & group_mask->sig[3]);
5141                         bnx2x_attn_int_deasserted1(bp,
5142                                         attn.sig[1] & group_mask->sig[1]);
5143                         bnx2x_attn_int_deasserted2(bp,
5144                                         attn.sig[2] & group_mask->sig[2]);
5145                         bnx2x_attn_int_deasserted0(bp,
5146                                         attn.sig[0] & group_mask->sig[0]);
5147                 }
5148         }
5149
5150         bnx2x_release_alr(bp);
5151
5152         if (bp->common.int_block == INT_BLOCK_HC)
5153                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5154                             COMMAND_REG_ATTN_BITS_CLR);
5155         else
5156                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5157
5158         val = ~deasserted;
5159         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5160            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5161         REG_WR(bp, reg_addr, val);
5162
5163         if (~bp->attn_state & deasserted)
5164                 BNX2X_ERR("IGU ERROR\n");
5165
5166         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5167                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5168
5169         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5170         aeu_mask = REG_RD(bp, reg_addr);
5171
5172         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5173            aeu_mask, deasserted);
5174         aeu_mask |= (deasserted & 0x3ff);
5175         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5176
5177         REG_WR(bp, reg_addr, aeu_mask);
5178         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5179
5180         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5181         bp->attn_state &= ~deasserted;
5182         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5183 }
5184
5185 static void bnx2x_attn_int(struct bnx2x *bp)
5186 {
5187         /* read local copy of bits */
5188         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5189                                                                 attn_bits);
5190         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5191                                                                 attn_bits_ack);
5192         u32 attn_state = bp->attn_state;
5193
5194         /* look for changed bits */
5195         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5196         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5197
5198         DP(NETIF_MSG_HW,
5199            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5200            attn_bits, attn_ack, asserted, deasserted);
5201
5202         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5203                 BNX2X_ERR("BAD attention state\n");
5204
5205         /* handle bits that were raised */
5206         if (asserted)
5207                 bnx2x_attn_int_asserted(bp, asserted);
5208
5209         if (deasserted)
5210                 bnx2x_attn_int_deasserted(bp, deasserted);
5211 }
5212
5213 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5214                       u16 index, u8 op, u8 update)
5215 {
5216         u32 igu_addr = bp->igu_base_addr;
5217         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5218         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5219                              igu_addr);
5220 }
5221
5222 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5223 {
5224         /* No memory barriers */
5225         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5226         mmiowb(); /* keep prod updates ordered */
5227 }
5228
5229 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5230                                       union event_ring_elem *elem)
5231 {
5232         u8 err = elem->message.error;
5233
5234         if (!bp->cnic_eth_dev.starting_cid  ||
5235             (cid < bp->cnic_eth_dev.starting_cid &&
5236             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5237                 return 1;
5238
5239         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5240
5241         if (unlikely(err)) {
5242
5243                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5244                           cid);
5245                 bnx2x_panic_dump(bp, false);
5246         }
5247         bnx2x_cnic_cfc_comp(bp, cid, err);
5248         return 0;
5249 }
5250
5251 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5252 {
5253         struct bnx2x_mcast_ramrod_params rparam;
5254         int rc;
5255
5256         memset(&rparam, 0, sizeof(rparam));
5257
5258         rparam.mcast_obj = &bp->mcast_obj;
5259
5260         netif_addr_lock_bh(bp->dev);
5261
5262         /* Clear pending state for the last command */
5263         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5264
5265         /* If there are pending mcast commands - send them */
5266         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5267                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5268                 if (rc < 0)
5269                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5270                                   rc);
5271         }
5272
5273         netif_addr_unlock_bh(bp->dev);
5274 }
5275
5276 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5277                                             union event_ring_elem *elem)
5278 {
5279         unsigned long ramrod_flags = 0;
5280         int rc = 0;
5281         u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5282         u32 cid = echo & BNX2X_SWCID_MASK;
5283         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5284
5285         /* Always push next commands out, don't wait here */
5286         __set_bit(RAMROD_CONT, &ramrod_flags);
5287
5288         switch (echo >> BNX2X_SWCID_SHIFT) {
5289         case BNX2X_FILTER_MAC_PENDING:
5290                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5291                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5292                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5293                 else
5294                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5295
5296                 break;
5297         case BNX2X_FILTER_VLAN_PENDING:
5298                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5299                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5300                 break;
5301         case BNX2X_FILTER_MCAST_PENDING:
5302                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5303                 /* This is only relevant for 57710 where multicast MACs are
5304                  * configured as unicast MACs using the same ramrod.
5305                  */
5306                 bnx2x_handle_mcast_eqe(bp);
5307                 return;
5308         default:
5309                 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
5310                 return;
5311         }
5312
5313         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5314
5315         if (rc < 0)
5316                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5317         else if (rc > 0)
5318                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5319 }
5320
5321 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5322
5323 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5324 {
5325         netif_addr_lock_bh(bp->dev);
5326
5327         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5328
5329         /* Send rx_mode command again if was requested */
5330         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5331                 bnx2x_set_storm_rx_mode(bp);
5332         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5333                                     &bp->sp_state))
5334                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5335         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5336                                     &bp->sp_state))
5337                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5338
5339         netif_addr_unlock_bh(bp->dev);
5340 }
5341
5342 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5343                                               union event_ring_elem *elem)
5344 {
5345         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5346                 DP(BNX2X_MSG_SP,
5347                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5348                    elem->message.data.vif_list_event.func_bit_map);
5349                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5350                         elem->message.data.vif_list_event.func_bit_map);
5351         } else if (elem->message.data.vif_list_event.echo ==
5352                    VIF_LIST_RULE_SET) {
5353                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5354                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5355         }
5356 }
5357
5358 /* called with rtnl_lock */
5359 static void bnx2x_after_function_update(struct bnx2x *bp)
5360 {
5361         int q, rc;
5362         struct bnx2x_fastpath *fp;
5363         struct bnx2x_queue_state_params queue_params = {NULL};
5364         struct bnx2x_queue_update_params *q_update_params =
5365                 &queue_params.params.update;
5366
5367         /* Send Q update command with afex vlan removal values for all Qs */
5368         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5369
5370         /* set silent vlan removal values according to vlan mode */
5371         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5372                   &q_update_params->update_flags);
5373         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5374                   &q_update_params->update_flags);
5375         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5376
5377         /* in access mode mark mask and value are 0 to strip all vlans */
5378         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5379                 q_update_params->silent_removal_value = 0;
5380                 q_update_params->silent_removal_mask = 0;
5381         } else {
5382                 q_update_params->silent_removal_value =
5383                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5384                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5385         }
5386
5387         for_each_eth_queue(bp, q) {
5388                 /* Set the appropriate Queue object */
5389                 fp = &bp->fp[q];
5390                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5391
5392                 /* send the ramrod */
5393                 rc = bnx2x_queue_state_change(bp, &queue_params);
5394                 if (rc < 0)
5395                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5396                                   q);
5397         }
5398
5399         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5400                 fp = &bp->fp[FCOE_IDX(bp)];
5401                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5402
5403                 /* clear pending completion bit */
5404                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5405
5406                 /* mark latest Q bit */
5407                 smp_mb__before_atomic();
5408                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5409                 smp_mb__after_atomic();
5410
5411                 /* send Q update ramrod for FCoE Q */
5412                 rc = bnx2x_queue_state_change(bp, &queue_params);
5413                 if (rc < 0)
5414                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5415                                   q);
5416         } else {
5417                 /* If no FCoE ring - ACK MCP now */
5418                 bnx2x_link_report(bp);
5419                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5420         }
5421 }
5422
5423 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5424         struct bnx2x *bp, u32 cid)
5425 {
5426         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5427
5428         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5429                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5430         else
5431                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5432 }
5433
5434 static void bnx2x_eq_int(struct bnx2x *bp)
5435 {
5436         u16 hw_cons, sw_cons, sw_prod;
5437         union event_ring_elem *elem;
5438         u8 echo;
5439         u32 cid;
5440         u8 opcode;
5441         int rc, spqe_cnt = 0;
5442         struct bnx2x_queue_sp_obj *q_obj;
5443         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5444         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5445
5446         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5447
5448         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5449          * when we get the next-page we need to adjust so the loop
5450          * condition below will be met. The next element is the size of a
5451          * regular element and hence incrementing by 1
5452          */
5453         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5454                 hw_cons++;
5455
5456         /* This function may never run in parallel with itself for a
5457          * specific bp, thus there is no need in "paired" read memory
5458          * barrier here.
5459          */
5460         sw_cons = bp->eq_cons;
5461         sw_prod = bp->eq_prod;
5462
5463         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5464                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5465
5466         for (; sw_cons != hw_cons;
5467               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5468
5469                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5470
5471                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5472                 if (!rc) {
5473                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5474                            rc);
5475                         goto next_spqe;
5476                 }
5477
5478                 opcode = elem->message.opcode;
5479
5480                 /* handle eq element */
5481                 switch (opcode) {
5482                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5483                         bnx2x_vf_mbx_schedule(bp,
5484                                               &elem->message.data.vf_pf_event);
5485                         continue;
5486
5487                 case EVENT_RING_OPCODE_STAT_QUERY:
5488                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5489                                "got statistics comp event %d\n",
5490                                bp->stats_comp++);
5491                         /* nothing to do with stats comp */
5492                         goto next_spqe;
5493
5494                 case EVENT_RING_OPCODE_CFC_DEL:
5495                         /* handle according to cid range */
5496                         /*
5497                          * we may want to verify here that the bp state is
5498                          * HALTING
5499                          */
5500
5501                         /* elem CID originates from FW; actually LE */
5502                         cid = SW_CID(elem->message.data.cfc_del_event.cid);
5503
5504                         DP(BNX2X_MSG_SP,
5505                            "got delete ramrod for MULTI[%d]\n", cid);
5506
5507                         if (CNIC_LOADED(bp) &&
5508                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5509                                 goto next_spqe;
5510
5511                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5512
5513                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5514                                 break;
5515
5516                         goto next_spqe;
5517
5518                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5519                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5520                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5521                         if (f_obj->complete_cmd(bp, f_obj,
5522                                                 BNX2X_F_CMD_TX_STOP))
5523                                 break;
5524                         goto next_spqe;
5525
5526                 case EVENT_RING_OPCODE_START_TRAFFIC:
5527                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5528                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5529                         if (f_obj->complete_cmd(bp, f_obj,
5530                                                 BNX2X_F_CMD_TX_START))
5531                                 break;
5532                         goto next_spqe;
5533
5534                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5535                         echo = elem->message.data.function_update_event.echo;
5536                         if (echo == SWITCH_UPDATE) {
5537                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5538                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5539                                 if (f_obj->complete_cmd(
5540                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5541                                         break;
5542
5543                         } else {
5544                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5545
5546                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5547                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5548                                 f_obj->complete_cmd(bp, f_obj,
5549                                                     BNX2X_F_CMD_AFEX_UPDATE);
5550
5551                                 /* We will perform the Queues update from
5552                                  * sp_rtnl task as all Queue SP operations
5553                                  * should run under rtnl_lock.
5554                                  */
5555                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5556                         }
5557
5558                         goto next_spqe;
5559
5560                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5561                         f_obj->complete_cmd(bp, f_obj,
5562                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5563                         bnx2x_after_afex_vif_lists(bp, elem);
5564                         goto next_spqe;
5565                 case EVENT_RING_OPCODE_FUNCTION_START:
5566                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5567                            "got FUNC_START ramrod\n");
5568                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5569                                 break;
5570
5571                         goto next_spqe;
5572
5573                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5574                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5575                            "got FUNC_STOP ramrod\n");
5576                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5577                                 break;
5578
5579                         goto next_spqe;
5580
5581                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5582                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5583                            "got set_timesync ramrod completion\n");
5584                         if (f_obj->complete_cmd(bp, f_obj,
5585                                                 BNX2X_F_CMD_SET_TIMESYNC))
5586                                 break;
5587                         goto next_spqe;
5588                 }
5589
5590                 switch (opcode | bp->state) {
5591                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5592                       BNX2X_STATE_OPEN):
5593                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5594                       BNX2X_STATE_OPENING_WAIT4_PORT):
5595                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5596                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5597                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5598                            SW_CID(elem->message.data.eth_event.echo));
5599                         rss_raw->clear_pending(rss_raw);
5600                         break;
5601
5602                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5603                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5604                 case (EVENT_RING_OPCODE_SET_MAC |
5605                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5606                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5607                       BNX2X_STATE_OPEN):
5608                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5609                       BNX2X_STATE_DIAG):
5610                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5611                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5612                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5613                         bnx2x_handle_classification_eqe(bp, elem);
5614                         break;
5615
5616                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5617                       BNX2X_STATE_OPEN):
5618                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5619                       BNX2X_STATE_DIAG):
5620                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5621                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5622                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5623                         bnx2x_handle_mcast_eqe(bp);
5624                         break;
5625
5626                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5627                       BNX2X_STATE_OPEN):
5628                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5629                       BNX2X_STATE_DIAG):
5630                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5631                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5632                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5633                         bnx2x_handle_rx_mode_eqe(bp);
5634                         break;
5635                 default:
5636                         /* unknown event log error and continue */
5637                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5638                                   elem->message.opcode, bp->state);
5639                 }
5640 next_spqe:
5641                 spqe_cnt++;
5642         } /* for */
5643
5644         smp_mb__before_atomic();
5645         atomic_add(spqe_cnt, &bp->eq_spq_left);
5646
5647         bp->eq_cons = sw_cons;
5648         bp->eq_prod = sw_prod;
5649         /* Make sure that above mem writes were issued towards the memory */
5650         smp_wmb();
5651
5652         /* update producer */
5653         bnx2x_update_eq_prod(bp, bp->eq_prod);
5654 }
5655
5656 static void bnx2x_sp_task(struct work_struct *work)
5657 {
5658         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5659
5660         DP(BNX2X_MSG_SP, "sp task invoked\n");
5661
5662         /* make sure the atomic interrupt_occurred has been written */
5663         smp_rmb();
5664         if (atomic_read(&bp->interrupt_occurred)) {
5665
5666                 /* what work needs to be performed? */
5667                 u16 status = bnx2x_update_dsb_idx(bp);
5668
5669                 DP(BNX2X_MSG_SP, "status %x\n", status);
5670                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5671                 atomic_set(&bp->interrupt_occurred, 0);
5672
5673                 /* HW attentions */
5674                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5675                         bnx2x_attn_int(bp);
5676                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5677                 }
5678
5679                 /* SP events: STAT_QUERY and others */
5680                 if (status & BNX2X_DEF_SB_IDX) {
5681                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5682
5683                         if (FCOE_INIT(bp) &&
5684                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5685                                 /* Prevent local bottom-halves from running as
5686                                  * we are going to change the local NAPI list.
5687                                  */
5688                                 local_bh_disable();
5689                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5690                                 local_bh_enable();
5691                         }
5692
5693                         /* Handle EQ completions */
5694                         bnx2x_eq_int(bp);
5695                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5696                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5697
5698                         status &= ~BNX2X_DEF_SB_IDX;
5699                 }
5700
5701                 /* if status is non zero then perhaps something went wrong */
5702                 if (unlikely(status))
5703                         DP(BNX2X_MSG_SP,
5704                            "got an unknown interrupt! (status 0x%x)\n", status);
5705
5706                 /* ack status block only if something was actually handled */
5707                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5708                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5709         }
5710
5711         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5712         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5713                                &bp->sp_state)) {
5714                 bnx2x_link_report(bp);
5715                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5716         }
5717 }
5718
5719 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5720 {
5721         struct net_device *dev = dev_instance;
5722         struct bnx2x *bp = netdev_priv(dev);
5723
5724         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5725                      IGU_INT_DISABLE, 0);
5726
5727 #ifdef BNX2X_STOP_ON_ERROR
5728         if (unlikely(bp->panic))
5729                 return IRQ_HANDLED;
5730 #endif
5731
5732         if (CNIC_LOADED(bp)) {
5733                 struct cnic_ops *c_ops;
5734
5735                 rcu_read_lock();
5736                 c_ops = rcu_dereference(bp->cnic_ops);
5737                 if (c_ops)
5738                         c_ops->cnic_handler(bp->cnic_data, NULL);
5739                 rcu_read_unlock();
5740         }
5741
5742         /* schedule sp task to perform default status block work, ack
5743          * attentions and enable interrupts.
5744          */
5745         bnx2x_schedule_sp_task(bp);
5746
5747         return IRQ_HANDLED;
5748 }
5749
5750 /* end of slow path */
5751
5752 void bnx2x_drv_pulse(struct bnx2x *bp)
5753 {
5754         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5755                  bp->fw_drv_pulse_wr_seq);
5756 }
5757
5758 static void bnx2x_timer(unsigned long data)
5759 {
5760         struct bnx2x *bp = (struct bnx2x *) data;
5761
5762         if (!netif_running(bp->dev))
5763                 return;
5764
5765         if (IS_PF(bp) &&
5766             !BP_NOMCP(bp)) {
5767                 int mb_idx = BP_FW_MB_IDX(bp);
5768                 u16 drv_pulse;
5769                 u16 mcp_pulse;
5770
5771                 ++bp->fw_drv_pulse_wr_seq;
5772                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5773                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5774                 bnx2x_drv_pulse(bp);
5775
5776                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5777                              MCP_PULSE_SEQ_MASK);
5778                 /* The delta between driver pulse and mcp response
5779                  * should not get too big. If the MFW is more than 5 pulses
5780                  * behind, we should worry about it enough to generate an error
5781                  * log.
5782                  */
5783                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5784                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5785                                   drv_pulse, mcp_pulse);
5786         }
5787
5788         if (bp->state == BNX2X_STATE_OPEN)
5789                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5790
5791         /* sample pf vf bulletin board for new posts from pf */
5792         if (IS_VF(bp))
5793                 bnx2x_timer_sriov(bp);
5794
5795         mod_timer(&bp->timer, jiffies + bp->current_interval);
5796 }
5797
5798 /* end of Statistics */
5799
5800 /* nic init */
5801
5802 /*
5803  * nic init service functions
5804  */
5805
5806 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5807 {
5808         u32 i;
5809         if (!(len%4) && !(addr%4))
5810                 for (i = 0; i < len; i += 4)
5811                         REG_WR(bp, addr + i, fill);
5812         else
5813                 for (i = 0; i < len; i++)
5814                         REG_WR8(bp, addr + i, fill);
5815 }
5816
5817 /* helper: writes FP SP data to FW - data_size in dwords */
5818 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5819                                 int fw_sb_id,
5820                                 u32 *sb_data_p,
5821                                 u32 data_size)
5822 {
5823         int index;
5824         for (index = 0; index < data_size; index++)
5825                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5826                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5827                         sizeof(u32)*index,
5828                         *(sb_data_p + index));
5829 }
5830
5831 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5832 {
5833         u32 *sb_data_p;
5834         u32 data_size = 0;
5835         struct hc_status_block_data_e2 sb_data_e2;
5836         struct hc_status_block_data_e1x sb_data_e1x;
5837
5838         /* disable the function first */
5839         if (!CHIP_IS_E1x(bp)) {
5840                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5841                 sb_data_e2.common.state = SB_DISABLED;
5842                 sb_data_e2.common.p_func.vf_valid = false;
5843                 sb_data_p = (u32 *)&sb_data_e2;
5844                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5845         } else {
5846                 memset(&sb_data_e1x, 0,
5847                        sizeof(struct hc_status_block_data_e1x));
5848                 sb_data_e1x.common.state = SB_DISABLED;
5849                 sb_data_e1x.common.p_func.vf_valid = false;
5850                 sb_data_p = (u32 *)&sb_data_e1x;
5851                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5852         }
5853         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5854
5855         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5856                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5857                         CSTORM_STATUS_BLOCK_SIZE);
5858         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5859                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5860                         CSTORM_SYNC_BLOCK_SIZE);
5861 }
5862
5863 /* helper:  writes SP SB data to FW */
5864 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5865                 struct hc_sp_status_block_data *sp_sb_data)
5866 {
5867         int func = BP_FUNC(bp);
5868         int i;
5869         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5870                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5871                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5872                         i*sizeof(u32),
5873                         *((u32 *)sp_sb_data + i));
5874 }
5875
5876 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5877 {
5878         int func = BP_FUNC(bp);
5879         struct hc_sp_status_block_data sp_sb_data;
5880         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5881
5882         sp_sb_data.state = SB_DISABLED;
5883         sp_sb_data.p_func.vf_valid = false;
5884
5885         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5886
5887         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5888                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5889                         CSTORM_SP_STATUS_BLOCK_SIZE);
5890         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5891                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5892                         CSTORM_SP_SYNC_BLOCK_SIZE);
5893 }
5894
5895 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5896                                            int igu_sb_id, int igu_seg_id)
5897 {
5898         hc_sm->igu_sb_id = igu_sb_id;
5899         hc_sm->igu_seg_id = igu_seg_id;
5900         hc_sm->timer_value = 0xFF;
5901         hc_sm->time_to_expire = 0xFFFFFFFF;
5902 }
5903
5904 /* allocates state machine ids. */
5905 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5906 {
5907         /* zero out state machine indices */
5908         /* rx indices */
5909         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5910
5911         /* tx indices */
5912         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5913         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5914         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5915         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5916
5917         /* map indices */
5918         /* rx indices */
5919         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5920                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5921
5922         /* tx indices */
5923         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5924                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5925         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5926                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5927         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5928                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5930                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931 }
5932
5933 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5934                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5935 {
5936         int igu_seg_id;
5937
5938         struct hc_status_block_data_e2 sb_data_e2;
5939         struct hc_status_block_data_e1x sb_data_e1x;
5940         struct hc_status_block_sm  *hc_sm_p;
5941         int data_size;
5942         u32 *sb_data_p;
5943
5944         if (CHIP_INT_MODE_IS_BC(bp))
5945                 igu_seg_id = HC_SEG_ACCESS_NORM;
5946         else
5947                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5948
5949         bnx2x_zero_fp_sb(bp, fw_sb_id);
5950
5951         if (!CHIP_IS_E1x(bp)) {
5952                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5953                 sb_data_e2.common.state = SB_ENABLED;
5954                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5955                 sb_data_e2.common.p_func.vf_id = vfid;
5956                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5957                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5958                 sb_data_e2.common.same_igu_sb_1b = true;
5959                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5960                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5961                 hc_sm_p = sb_data_e2.common.state_machine;
5962                 sb_data_p = (u32 *)&sb_data_e2;
5963                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5964                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5965         } else {
5966                 memset(&sb_data_e1x, 0,
5967                        sizeof(struct hc_status_block_data_e1x));
5968                 sb_data_e1x.common.state = SB_ENABLED;
5969                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5970                 sb_data_e1x.common.p_func.vf_id = 0xff;
5971                 sb_data_e1x.common.p_func.vf_valid = false;
5972                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5973                 sb_data_e1x.common.same_igu_sb_1b = true;
5974                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5975                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5976                 hc_sm_p = sb_data_e1x.common.state_machine;
5977                 sb_data_p = (u32 *)&sb_data_e1x;
5978                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5979                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5980         }
5981
5982         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5983                                        igu_sb_id, igu_seg_id);
5984         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5985                                        igu_sb_id, igu_seg_id);
5986
5987         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5988
5989         /* write indices to HW - PCI guarantees endianity of regpairs */
5990         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5991 }
5992
5993 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5994                                      u16 tx_usec, u16 rx_usec)
5995 {
5996         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5997                                     false, rx_usec);
5998         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5999                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6000                                        tx_usec);
6001         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6002                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6003                                        tx_usec);
6004         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6005                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6006                                        tx_usec);
6007 }
6008
6009 static void bnx2x_init_def_sb(struct bnx2x *bp)
6010 {
6011         struct host_sp_status_block *def_sb = bp->def_status_blk;
6012         dma_addr_t mapping = bp->def_status_blk_mapping;
6013         int igu_sp_sb_index;
6014         int igu_seg_id;
6015         int port = BP_PORT(bp);
6016         int func = BP_FUNC(bp);
6017         int reg_offset, reg_offset_en5;
6018         u64 section;
6019         int index;
6020         struct hc_sp_status_block_data sp_sb_data;
6021         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6022
6023         if (CHIP_INT_MODE_IS_BC(bp)) {
6024                 igu_sp_sb_index = DEF_SB_IGU_ID;
6025                 igu_seg_id = HC_SEG_ACCESS_DEF;
6026         } else {
6027                 igu_sp_sb_index = bp->igu_dsb_id;
6028                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6029         }
6030
6031         /* ATTN */
6032         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6033                                             atten_status_block);
6034         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6035
6036         bp->attn_state = 0;
6037
6038         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6039                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6040         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6041                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6042         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6043                 int sindex;
6044                 /* take care of sig[0]..sig[4] */
6045                 for (sindex = 0; sindex < 4; sindex++)
6046                         bp->attn_group[index].sig[sindex] =
6047                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6048
6049                 if (!CHIP_IS_E1x(bp))
6050                         /*
6051                          * enable5 is separate from the rest of the registers,
6052                          * and therefore the address skip is 4
6053                          * and not 16 between the different groups
6054                          */
6055                         bp->attn_group[index].sig[4] = REG_RD(bp,
6056                                         reg_offset_en5 + 0x4*index);
6057                 else
6058                         bp->attn_group[index].sig[4] = 0;
6059         }
6060
6061         if (bp->common.int_block == INT_BLOCK_HC) {
6062                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6063                                      HC_REG_ATTN_MSG0_ADDR_L);
6064
6065                 REG_WR(bp, reg_offset, U64_LO(section));
6066                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6067         } else if (!CHIP_IS_E1x(bp)) {
6068                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6069                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6070         }
6071
6072         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6073                                             sp_sb);
6074
6075         bnx2x_zero_sp_sb(bp);
6076
6077         /* PCI guarantees endianity of regpairs */
6078         sp_sb_data.state                = SB_ENABLED;
6079         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6080         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6081         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6082         sp_sb_data.igu_seg_id           = igu_seg_id;
6083         sp_sb_data.p_func.pf_id         = func;
6084         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6085         sp_sb_data.p_func.vf_id         = 0xff;
6086
6087         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6088
6089         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6090 }
6091
6092 void bnx2x_update_coalesce(struct bnx2x *bp)
6093 {
6094         int i;
6095
6096         for_each_eth_queue(bp, i)
6097                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6098                                          bp->tx_ticks, bp->rx_ticks);
6099 }
6100
6101 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6102 {
6103         spin_lock_init(&bp->spq_lock);
6104         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6105
6106         bp->spq_prod_idx = 0;
6107         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6108         bp->spq_prod_bd = bp->spq;
6109         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6110 }
6111
6112 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6113 {
6114         int i;
6115         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6116                 union event_ring_elem *elem =
6117                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6118
6119                 elem->next_page.addr.hi =
6120                         cpu_to_le32(U64_HI(bp->eq_mapping +
6121                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6122                 elem->next_page.addr.lo =
6123                         cpu_to_le32(U64_LO(bp->eq_mapping +
6124                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6125         }
6126         bp->eq_cons = 0;
6127         bp->eq_prod = NUM_EQ_DESC;
6128         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6129         /* we want a warning message before it gets wrought... */
6130         atomic_set(&bp->eq_spq_left,
6131                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6132 }
6133
6134 /* called with netif_addr_lock_bh() */
6135 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6136                                unsigned long rx_mode_flags,
6137                                unsigned long rx_accept_flags,
6138                                unsigned long tx_accept_flags,
6139                                unsigned long ramrod_flags)
6140 {
6141         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6142         int rc;
6143
6144         memset(&ramrod_param, 0, sizeof(ramrod_param));
6145
6146         /* Prepare ramrod parameters */
6147         ramrod_param.cid = 0;
6148         ramrod_param.cl_id = cl_id;
6149         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6150         ramrod_param.func_id = BP_FUNC(bp);
6151
6152         ramrod_param.pstate = &bp->sp_state;
6153         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6154
6155         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6156         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6157
6158         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6159
6160         ramrod_param.ramrod_flags = ramrod_flags;
6161         ramrod_param.rx_mode_flags = rx_mode_flags;
6162
6163         ramrod_param.rx_accept_flags = rx_accept_flags;
6164         ramrod_param.tx_accept_flags = tx_accept_flags;
6165
6166         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6167         if (rc < 0) {
6168                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6169                 return rc;
6170         }
6171
6172         return 0;
6173 }
6174
6175 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6176                                    unsigned long *rx_accept_flags,
6177                                    unsigned long *tx_accept_flags)
6178 {
6179         /* Clear the flags first */
6180         *rx_accept_flags = 0;
6181         *tx_accept_flags = 0;
6182
6183         switch (rx_mode) {
6184         case BNX2X_RX_MODE_NONE:
6185                 /*
6186                  * 'drop all' supersedes any accept flags that may have been
6187                  * passed to the function.
6188                  */
6189                 break;
6190         case BNX2X_RX_MODE_NORMAL:
6191                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6192                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6193                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6194
6195                 /* internal switching mode */
6196                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6197                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6198                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6199
6200                 if (bp->accept_any_vlan) {
6201                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6202                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6203                 }
6204
6205                 break;
6206         case BNX2X_RX_MODE_ALLMULTI:
6207                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6208                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6209                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6210
6211                 /* internal switching mode */
6212                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6213                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6214                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6215
6216                 if (bp->accept_any_vlan) {
6217                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6218                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6219                 }
6220
6221                 break;
6222         case BNX2X_RX_MODE_PROMISC:
6223                 /* According to definition of SI mode, iface in promisc mode
6224                  * should receive matched and unmatched (in resolution of port)
6225                  * unicast packets.
6226                  */
6227                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6228                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6229                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6230                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6231
6232                 /* internal switching mode */
6233                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6234                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6235
6236                 if (IS_MF_SI(bp))
6237                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6238                 else
6239                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6240
6241                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6242                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6243
6244                 break;
6245         default:
6246                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6247                 return -EINVAL;
6248         }
6249
6250         return 0;
6251 }
6252
6253 /* called with netif_addr_lock_bh() */
6254 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6255 {
6256         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6257         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6258         int rc;
6259
6260         if (!NO_FCOE(bp))
6261                 /* Configure rx_mode of FCoE Queue */
6262                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6263
6264         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6265                                      &tx_accept_flags);
6266         if (rc)
6267                 return rc;
6268
6269         __set_bit(RAMROD_RX, &ramrod_flags);
6270         __set_bit(RAMROD_TX, &ramrod_flags);
6271
6272         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6273                                    rx_accept_flags, tx_accept_flags,
6274                                    ramrod_flags);
6275 }
6276
6277 static void bnx2x_init_internal_common(struct bnx2x *bp)
6278 {
6279         int i;
6280
6281         /* Zero this manually as its initialization is
6282            currently missing in the initTool */
6283         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6284                 REG_WR(bp, BAR_USTRORM_INTMEM +
6285                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6286         if (!CHIP_IS_E1x(bp)) {
6287                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6288                         CHIP_INT_MODE_IS_BC(bp) ?
6289                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6290         }
6291 }
6292
6293 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6294 {
6295         switch (load_code) {
6296         case FW_MSG_CODE_DRV_LOAD_COMMON:
6297         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6298                 bnx2x_init_internal_common(bp);
6299                 /* no break */
6300
6301         case FW_MSG_CODE_DRV_LOAD_PORT:
6302                 /* nothing to do */
6303                 /* no break */
6304
6305         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6306                 /* internal memory per function is
6307                    initialized inside bnx2x_pf_init */
6308                 break;
6309
6310         default:
6311                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6312                 break;
6313         }
6314 }
6315
6316 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6317 {
6318         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6319 }
6320
6321 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6322 {
6323         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6324 }
6325
6326 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6327 {
6328         if (CHIP_IS_E1x(fp->bp))
6329                 return BP_L_ID(fp->bp) + fp->index;
6330         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6331                 return bnx2x_fp_igu_sb_id(fp);
6332 }
6333
6334 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6335 {
6336         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6337         u8 cos;
6338         unsigned long q_type = 0;
6339         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6340         fp->rx_queue = fp_idx;
6341         fp->cid = fp_idx;
6342         fp->cl_id = bnx2x_fp_cl_id(fp);
6343         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6344         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6345         /* qZone id equals to FW (per path) client id */
6346         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6347
6348         /* init shortcut */
6349         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6350
6351         /* Setup SB indices */
6352         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6353
6354         /* Configure Queue State object */
6355         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6356         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6357
6358         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6359
6360         /* init tx data */
6361         for_each_cos_in_tx_queue(fp, cos) {
6362                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6363                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6364                                   FP_COS_TO_TXQ(fp, cos, bp),
6365                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6366                 cids[cos] = fp->txdata_ptr[cos]->cid;
6367         }
6368
6369         /* nothing more for vf to do here */
6370         if (IS_VF(bp))
6371                 return;
6372
6373         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6374                       fp->fw_sb_id, fp->igu_sb_id);
6375         bnx2x_update_fpsb_idx(fp);
6376         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6377                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6378                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6379
6380         /**
6381          * Configure classification DBs: Always enable Tx switching
6382          */
6383         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6384
6385         DP(NETIF_MSG_IFUP,
6386            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6387            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6388            fp->igu_sb_id);
6389 }
6390
6391 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6392 {
6393         int i;
6394
6395         for (i = 1; i <= NUM_TX_RINGS; i++) {
6396                 struct eth_tx_next_bd *tx_next_bd =
6397                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6398
6399                 tx_next_bd->addr_hi =
6400                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6401                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6402                 tx_next_bd->addr_lo =
6403                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6404                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6405         }
6406
6407         *txdata->tx_cons_sb = cpu_to_le16(0);
6408
6409         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6410         txdata->tx_db.data.zero_fill1 = 0;
6411         txdata->tx_db.data.prod = 0;
6412
6413         txdata->tx_pkt_prod = 0;
6414         txdata->tx_pkt_cons = 0;
6415         txdata->tx_bd_prod = 0;
6416         txdata->tx_bd_cons = 0;
6417         txdata->tx_pkt = 0;
6418 }
6419
6420 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6421 {
6422         int i;
6423
6424         for_each_tx_queue_cnic(bp, i)
6425                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6426 }
6427
6428 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6429 {
6430         int i;
6431         u8 cos;
6432
6433         for_each_eth_queue(bp, i)
6434                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6435                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6436 }
6437
6438 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6439 {
6440         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6441         unsigned long q_type = 0;
6442
6443         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6444         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6445                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6446         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6447         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6448         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6449         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6450         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6451                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6452                           fp);
6453
6454         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6455
6456         /* qZone id equals to FW (per path) client id */
6457         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6458         /* init shortcut */
6459         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6460                 bnx2x_rx_ustorm_prods_offset(fp);
6461
6462         /* Configure Queue State object */
6463         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6464         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6465
6466         /* No multi-CoS for FCoE L2 client */
6467         BUG_ON(fp->max_cos != 1);
6468
6469         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6470                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6471                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6472
6473         DP(NETIF_MSG_IFUP,
6474            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6475            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6476            fp->igu_sb_id);
6477 }
6478
6479 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6480 {
6481         if (!NO_FCOE(bp))
6482                 bnx2x_init_fcoe_fp(bp);
6483
6484         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6485                       BNX2X_VF_ID_INVALID, false,
6486                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6487
6488         /* ensure status block indices were read */
6489         rmb();
6490         bnx2x_init_rx_rings_cnic(bp);
6491         bnx2x_init_tx_rings_cnic(bp);
6492
6493         /* flush all */
6494         mb();
6495         mmiowb();
6496 }
6497
6498 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6499 {
6500         int i;
6501
6502         /* Setup NIC internals and enable interrupts */
6503         for_each_eth_queue(bp, i)
6504                 bnx2x_init_eth_fp(bp, i);
6505
6506         /* ensure status block indices were read */
6507         rmb();
6508         bnx2x_init_rx_rings(bp);
6509         bnx2x_init_tx_rings(bp);
6510
6511         if (IS_PF(bp)) {
6512                 /* Initialize MOD_ABS interrupts */
6513                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6514                                        bp->common.shmem_base,
6515                                        bp->common.shmem2_base, BP_PORT(bp));
6516
6517                 /* initialize the default status block and sp ring */
6518                 bnx2x_init_def_sb(bp);
6519                 bnx2x_update_dsb_idx(bp);
6520                 bnx2x_init_sp_ring(bp);
6521         } else {
6522                 bnx2x_memset_stats(bp);
6523         }
6524 }
6525
6526 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6527 {
6528         bnx2x_init_eq_ring(bp);
6529         bnx2x_init_internal(bp, load_code);
6530         bnx2x_pf_init(bp);
6531         bnx2x_stats_init(bp);
6532
6533         /* flush all before enabling interrupts */
6534         mb();
6535         mmiowb();
6536
6537         bnx2x_int_enable(bp);
6538
6539         /* Check for SPIO5 */
6540         bnx2x_attn_int_deasserted0(bp,
6541                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6542                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6543 }
6544
6545 /* gzip service functions */
6546 static int bnx2x_gunzip_init(struct bnx2x *bp)
6547 {
6548         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6549                                             &bp->gunzip_mapping, GFP_KERNEL);
6550         if (bp->gunzip_buf  == NULL)
6551                 goto gunzip_nomem1;
6552
6553         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6554         if (bp->strm  == NULL)
6555                 goto gunzip_nomem2;
6556
6557         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6558         if (bp->strm->workspace == NULL)
6559                 goto gunzip_nomem3;
6560
6561         return 0;
6562
6563 gunzip_nomem3:
6564         kfree(bp->strm);
6565         bp->strm = NULL;
6566
6567 gunzip_nomem2:
6568         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6569                           bp->gunzip_mapping);
6570         bp->gunzip_buf = NULL;
6571
6572 gunzip_nomem1:
6573         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6574         return -ENOMEM;
6575 }
6576
6577 static void bnx2x_gunzip_end(struct bnx2x *bp)
6578 {
6579         if (bp->strm) {
6580                 vfree(bp->strm->workspace);
6581                 kfree(bp->strm);
6582                 bp->strm = NULL;
6583         }
6584
6585         if (bp->gunzip_buf) {
6586                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6587                                   bp->gunzip_mapping);
6588                 bp->gunzip_buf = NULL;
6589         }
6590 }
6591
6592 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6593 {
6594         int n, rc;
6595
6596         /* check gzip header */
6597         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6598                 BNX2X_ERR("Bad gzip header\n");
6599                 return -EINVAL;
6600         }
6601
6602         n = 10;
6603
6604 #define FNAME                           0x8
6605
6606         if (zbuf[3] & FNAME)
6607                 while ((zbuf[n++] != 0) && (n < len));
6608
6609         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6610         bp->strm->avail_in = len - n;
6611         bp->strm->next_out = bp->gunzip_buf;
6612         bp->strm->avail_out = FW_BUF_SIZE;
6613
6614         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6615         if (rc != Z_OK)
6616                 return rc;
6617
6618         rc = zlib_inflate(bp->strm, Z_FINISH);
6619         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6620                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6621                            bp->strm->msg);
6622
6623         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6624         if (bp->gunzip_outlen & 0x3)
6625                 netdev_err(bp->dev,
6626                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6627                                 bp->gunzip_outlen);
6628         bp->gunzip_outlen >>= 2;
6629
6630         zlib_inflateEnd(bp->strm);
6631
6632         if (rc == Z_STREAM_END)
6633                 return 0;
6634
6635         return rc;
6636 }
6637
6638 /* nic load/unload */
6639
6640 /*
6641  * General service functions
6642  */
6643
6644 /* send a NIG loopback debug packet */
6645 static void bnx2x_lb_pckt(struct bnx2x *bp)
6646 {
6647         u32 wb_write[3];
6648
6649         /* Ethernet source and destination addresses */
6650         wb_write[0] = 0x55555555;
6651         wb_write[1] = 0x55555555;
6652         wb_write[2] = 0x20;             /* SOP */
6653         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6654
6655         /* NON-IP protocol */
6656         wb_write[0] = 0x09000000;
6657         wb_write[1] = 0x55555555;
6658         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6659         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6660 }
6661
6662 /* some of the internal memories
6663  * are not directly readable from the driver
6664  * to test them we send debug packets
6665  */
6666 static int bnx2x_int_mem_test(struct bnx2x *bp)
6667 {
6668         int factor;
6669         int count, i;
6670         u32 val = 0;
6671
6672         if (CHIP_REV_IS_FPGA(bp))
6673                 factor = 120;
6674         else if (CHIP_REV_IS_EMUL(bp))
6675                 factor = 200;
6676         else
6677                 factor = 1;
6678
6679         /* Disable inputs of parser neighbor blocks */
6680         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6681         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6682         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6683         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6684
6685         /*  Write 0 to parser credits for CFC search request */
6686         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6687
6688         /* send Ethernet packet */
6689         bnx2x_lb_pckt(bp);
6690
6691         /* TODO do i reset NIG statistic? */
6692         /* Wait until NIG register shows 1 packet of size 0x10 */
6693         count = 1000 * factor;
6694         while (count) {
6695
6696                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6697                 val = *bnx2x_sp(bp, wb_data[0]);
6698                 if (val == 0x10)
6699                         break;
6700
6701                 usleep_range(10000, 20000);
6702                 count--;
6703         }
6704         if (val != 0x10) {
6705                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6706                 return -1;
6707         }
6708
6709         /* Wait until PRS register shows 1 packet */
6710         count = 1000 * factor;
6711         while (count) {
6712                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6713                 if (val == 1)
6714                         break;
6715
6716                 usleep_range(10000, 20000);
6717                 count--;
6718         }
6719         if (val != 0x1) {
6720                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6721                 return -2;
6722         }
6723
6724         /* Reset and init BRB, PRS */
6725         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6726         msleep(50);
6727         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6728         msleep(50);
6729         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6730         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6731
6732         DP(NETIF_MSG_HW, "part2\n");
6733
6734         /* Disable inputs of parser neighbor blocks */
6735         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6736         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6737         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6738         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6739
6740         /* Write 0 to parser credits for CFC search request */
6741         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6742
6743         /* send 10 Ethernet packets */
6744         for (i = 0; i < 10; i++)
6745                 bnx2x_lb_pckt(bp);
6746
6747         /* Wait until NIG register shows 10 + 1
6748            packets of size 11*0x10 = 0xb0 */
6749         count = 1000 * factor;
6750         while (count) {
6751
6752                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6753                 val = *bnx2x_sp(bp, wb_data[0]);
6754                 if (val == 0xb0)
6755                         break;
6756
6757                 usleep_range(10000, 20000);
6758                 count--;
6759         }
6760         if (val != 0xb0) {
6761                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6762                 return -3;
6763         }
6764
6765         /* Wait until PRS register shows 2 packets */
6766         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6767         if (val != 2)
6768                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6769
6770         /* Write 1 to parser credits for CFC search request */
6771         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6772
6773         /* Wait until PRS register shows 3 packets */
6774         msleep(10 * factor);
6775         /* Wait until NIG register shows 1 packet of size 0x10 */
6776         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6777         if (val != 3)
6778                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6779
6780         /* clear NIG EOP FIFO */
6781         for (i = 0; i < 11; i++)
6782                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6783         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6784         if (val != 1) {
6785                 BNX2X_ERR("clear of NIG failed\n");
6786                 return -4;
6787         }
6788
6789         /* Reset and init BRB, PRS, NIG */
6790         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6791         msleep(50);
6792         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6793         msleep(50);
6794         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6795         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6796         if (!CNIC_SUPPORT(bp))
6797                 /* set NIC mode */
6798                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6799
6800         /* Enable inputs of parser neighbor blocks */
6801         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6802         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6803         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6804         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6805
6806         DP(NETIF_MSG_HW, "done\n");
6807
6808         return 0; /* OK */
6809 }
6810
6811 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6812 {
6813         u32 val;
6814
6815         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6816         if (!CHIP_IS_E1x(bp))
6817                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6818         else
6819                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6820         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6821         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6822         /*
6823          * mask read length error interrupts in brb for parser
6824          * (parsing unit and 'checksum and crc' unit)
6825          * these errors are legal (PU reads fixed length and CAC can cause
6826          * read length error on truncated packets)
6827          */
6828         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6829         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6830         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6831         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6832         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6833         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6834 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6835 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6836         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6837         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6838         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6839 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6840 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6841         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6842         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6843         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6844         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6845 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6846 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6847
6848         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6849                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6850                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6851         if (!CHIP_IS_E1x(bp))
6852                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6853                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6854         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6855
6856         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6857         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6858         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6859 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6860
6861         if (!CHIP_IS_E1x(bp))
6862                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6863                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6864
6865         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6866         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6867 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6868         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6869 }
6870
6871 static void bnx2x_reset_common(struct bnx2x *bp)
6872 {
6873         u32 val = 0x1400;
6874
6875         /* reset_common */
6876         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6877                0xd3ffff7f);
6878
6879         if (CHIP_IS_E3(bp)) {
6880                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6881                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6882         }
6883
6884         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6885 }
6886
6887 static void bnx2x_setup_dmae(struct bnx2x *bp)
6888 {
6889         bp->dmae_ready = 0;
6890         spin_lock_init(&bp->dmae_lock);
6891 }
6892
6893 static void bnx2x_init_pxp(struct bnx2x *bp)
6894 {
6895         u16 devctl;
6896         int r_order, w_order;
6897
6898         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6899         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6900         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6901         if (bp->mrrs == -1)
6902                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6903         else {
6904                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6905                 r_order = bp->mrrs;
6906         }
6907
6908         bnx2x_init_pxp_arb(bp, r_order, w_order);
6909 }
6910
6911 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6912 {
6913         int is_required;
6914         u32 val;
6915         int port;
6916
6917         if (BP_NOMCP(bp))
6918                 return;
6919
6920         is_required = 0;
6921         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6922               SHARED_HW_CFG_FAN_FAILURE_MASK;
6923
6924         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6925                 is_required = 1;
6926
6927         /*
6928          * The fan failure mechanism is usually related to the PHY type since
6929          * the power consumption of the board is affected by the PHY. Currently,
6930          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6931          */
6932         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6933                 for (port = PORT_0; port < PORT_MAX; port++) {
6934                         is_required |=
6935                                 bnx2x_fan_failure_det_req(
6936                                         bp,
6937                                         bp->common.shmem_base,
6938                                         bp->common.shmem2_base,
6939                                         port);
6940                 }
6941
6942         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6943
6944         if (is_required == 0)
6945                 return;
6946
6947         /* Fan failure is indicated by SPIO 5 */
6948         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6949
6950         /* set to active low mode */
6951         val = REG_RD(bp, MISC_REG_SPIO_INT);
6952         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6953         REG_WR(bp, MISC_REG_SPIO_INT, val);
6954
6955         /* enable interrupt to signal the IGU */
6956         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6957         val |= MISC_SPIO_SPIO5;
6958         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6959 }
6960
6961 void bnx2x_pf_disable(struct bnx2x *bp)
6962 {
6963         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6964         val &= ~IGU_PF_CONF_FUNC_EN;
6965
6966         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6967         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6968         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6969 }
6970
6971 static void bnx2x__common_init_phy(struct bnx2x *bp)
6972 {
6973         u32 shmem_base[2], shmem2_base[2];
6974         /* Avoid common init in case MFW supports LFA */
6975         if (SHMEM2_RD(bp, size) >
6976             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6977                 return;
6978         shmem_base[0] =  bp->common.shmem_base;
6979         shmem2_base[0] = bp->common.shmem2_base;
6980         if (!CHIP_IS_E1x(bp)) {
6981                 shmem_base[1] =
6982                         SHMEM2_RD(bp, other_shmem_base_addr);
6983                 shmem2_base[1] =
6984                         SHMEM2_RD(bp, other_shmem2_base_addr);
6985         }
6986         bnx2x_acquire_phy_lock(bp);
6987         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6988                               bp->common.chip_id);
6989         bnx2x_release_phy_lock(bp);
6990 }
6991
6992 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6993 {
6994         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6995         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6996         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6997         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6998         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6999
7000         /* make sure this value is 0 */
7001         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7002
7003         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7004         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7005         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7006         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7007 }
7008
7009 static void bnx2x_set_endianity(struct bnx2x *bp)
7010 {
7011 #ifdef __BIG_ENDIAN
7012         bnx2x_config_endianity(bp, 1);
7013 #else
7014         bnx2x_config_endianity(bp, 0);
7015 #endif
7016 }
7017
7018 static void bnx2x_reset_endianity(struct bnx2x *bp)
7019 {
7020         bnx2x_config_endianity(bp, 0);
7021 }
7022
7023 /**
7024  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7025  *
7026  * @bp:         driver handle
7027  */
7028 static int bnx2x_init_hw_common(struct bnx2x *bp)
7029 {
7030         u32 val;
7031
7032         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7033
7034         /*
7035          * take the RESET lock to protect undi_unload flow from accessing
7036          * registers while we're resetting the chip
7037          */
7038         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7039
7040         bnx2x_reset_common(bp);
7041         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7042
7043         val = 0xfffc;
7044         if (CHIP_IS_E3(bp)) {
7045                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7046                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7047         }
7048         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7049
7050         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7051
7052         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7053
7054         if (!CHIP_IS_E1x(bp)) {
7055                 u8 abs_func_id;
7056
7057                 /**
7058                  * 4-port mode or 2-port mode we need to turn of master-enable
7059                  * for everyone, after that, turn it back on for self.
7060                  * so, we disregard multi-function or not, and always disable
7061                  * for all functions on the given path, this means 0,2,4,6 for
7062                  * path 0 and 1,3,5,7 for path 1
7063                  */
7064                 for (abs_func_id = BP_PATH(bp);
7065                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7066                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7067                                 REG_WR(bp,
7068                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7069                                     1);
7070                                 continue;
7071                         }
7072
7073                         bnx2x_pretend_func(bp, abs_func_id);
7074                         /* clear pf enable */
7075                         bnx2x_pf_disable(bp);
7076                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7077                 }
7078         }
7079
7080         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7081         if (CHIP_IS_E1(bp)) {
7082                 /* enable HW interrupt from PXP on USDM overflow
7083                    bit 16 on INT_MASK_0 */
7084                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7085         }
7086
7087         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7088         bnx2x_init_pxp(bp);
7089         bnx2x_set_endianity(bp);
7090         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7091
7092         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7093                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7094
7095         /* let the HW do it's magic ... */
7096         msleep(100);
7097         /* finish PXP init */
7098         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7099         if (val != 1) {
7100                 BNX2X_ERR("PXP2 CFG failed\n");
7101                 return -EBUSY;
7102         }
7103         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7104         if (val != 1) {
7105                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7106                 return -EBUSY;
7107         }
7108
7109         /* Timers bug workaround E2 only. We need to set the entire ILT to
7110          * have entries with value "0" and valid bit on.
7111          * This needs to be done by the first PF that is loaded in a path
7112          * (i.e. common phase)
7113          */
7114         if (!CHIP_IS_E1x(bp)) {
7115 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7116  * (i.e. vnic3) to start even if it is marked as "scan-off".
7117  * This occurs when a different function (func2,3) is being marked
7118  * as "scan-off". Real-life scenario for example: if a driver is being
7119  * load-unloaded while func6,7 are down. This will cause the timer to access
7120  * the ilt, translate to a logical address and send a request to read/write.
7121  * Since the ilt for the function that is down is not valid, this will cause
7122  * a translation error which is unrecoverable.
7123  * The Workaround is intended to make sure that when this happens nothing fatal
7124  * will occur. The workaround:
7125  *      1.  First PF driver which loads on a path will:
7126  *              a.  After taking the chip out of reset, by using pretend,
7127  *                  it will write "0" to the following registers of
7128  *                  the other vnics.
7129  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7130  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7131  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7132  *                  And for itself it will write '1' to
7133  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7134  *                  dmae-operations (writing to pram for example.)
7135  *                  note: can be done for only function 6,7 but cleaner this
7136  *                        way.
7137  *              b.  Write zero+valid to the entire ILT.
7138  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7139  *                  VNIC3 (of that port). The range allocated will be the
7140  *                  entire ILT. This is needed to prevent  ILT range error.
7141  *      2.  Any PF driver load flow:
7142  *              a.  ILT update with the physical addresses of the allocated
7143  *                  logical pages.
7144  *              b.  Wait 20msec. - note that this timeout is needed to make
7145  *                  sure there are no requests in one of the PXP internal
7146  *                  queues with "old" ILT addresses.
7147  *              c.  PF enable in the PGLC.
7148  *              d.  Clear the was_error of the PF in the PGLC. (could have
7149  *                  occurred while driver was down)
7150  *              e.  PF enable in the CFC (WEAK + STRONG)
7151  *              f.  Timers scan enable
7152  *      3.  PF driver unload flow:
7153  *              a.  Clear the Timers scan_en.
7154  *              b.  Polling for scan_on=0 for that PF.
7155  *              c.  Clear the PF enable bit in the PXP.
7156  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7157  *              e.  Write zero+valid to all ILT entries (The valid bit must
7158  *                  stay set)
7159  *              f.  If this is VNIC 3 of a port then also init
7160  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7161  *                  to the last entry in the ILT.
7162  *
7163  *      Notes:
7164  *      Currently the PF error in the PGLC is non recoverable.
7165  *      In the future the there will be a recovery routine for this error.
7166  *      Currently attention is masked.
7167  *      Having an MCP lock on the load/unload process does not guarantee that
7168  *      there is no Timer disable during Func6/7 enable. This is because the
7169  *      Timers scan is currently being cleared by the MCP on FLR.
7170  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7171  *      there is error before clearing it. But the flow above is simpler and
7172  *      more general.
7173  *      All ILT entries are written by zero+valid and not just PF6/7
7174  *      ILT entries since in the future the ILT entries allocation for
7175  *      PF-s might be dynamic.
7176  */
7177                 struct ilt_client_info ilt_cli;
7178                 struct bnx2x_ilt ilt;
7179                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7180                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7181
7182                 /* initialize dummy TM client */
7183                 ilt_cli.start = 0;
7184                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7185                 ilt_cli.client_num = ILT_CLIENT_TM;
7186
7187                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7188                  * Step 2: set the timers first/last ilt entry to point
7189                  * to the entire range to prevent ILT range error for 3rd/4th
7190                  * vnic (this code assumes existence of the vnic)
7191                  *
7192                  * both steps performed by call to bnx2x_ilt_client_init_op()
7193                  * with dummy TM client
7194                  *
7195                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7196                  * and his brother are split registers
7197                  */
7198                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7199                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7200                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7201
7202                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7203                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7204                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7205         }
7206
7207         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7208         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7209
7210         if (!CHIP_IS_E1x(bp)) {
7211                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7212                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7213                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7214
7215                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7216
7217                 /* let the HW do it's magic ... */
7218                 do {
7219                         msleep(200);
7220                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7221                 } while (factor-- && (val != 1));
7222
7223                 if (val != 1) {
7224                         BNX2X_ERR("ATC_INIT failed\n");
7225                         return -EBUSY;
7226                 }
7227         }
7228
7229         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7230
7231         bnx2x_iov_init_dmae(bp);
7232
7233         /* clean the DMAE memory */
7234         bp->dmae_ready = 1;
7235         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7236
7237         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7238
7239         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7240
7241         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7242
7243         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7244
7245         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7246         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7247         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7248         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7249
7250         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7251
7252         /* QM queues pointers table */
7253         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7254
7255         /* soft reset pulse */
7256         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7257         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7258
7259         if (CNIC_SUPPORT(bp))
7260                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7261
7262         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7263
7264         if (!CHIP_REV_IS_SLOW(bp))
7265                 /* enable hw interrupt from doorbell Q */
7266                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7267
7268         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7269
7270         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7271         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7272
7273         if (!CHIP_IS_E1(bp))
7274                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7275
7276         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7277                 if (IS_MF_AFEX(bp)) {
7278                         /* configure that VNTag and VLAN headers must be
7279                          * received in afex mode
7280                          */
7281                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7282                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7283                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7284                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7285                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7286                 } else {
7287                         /* Bit-map indicating which L2 hdrs may appear
7288                          * after the basic Ethernet header
7289                          */
7290                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7291                                bp->path_has_ovlan ? 7 : 6);
7292                 }
7293         }
7294
7295         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7296         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7297         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7298         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7299
7300         if (!CHIP_IS_E1x(bp)) {
7301                 /* reset VFC memories */
7302                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7303                            VFC_MEMORIES_RST_REG_CAM_RST |
7304                            VFC_MEMORIES_RST_REG_RAM_RST);
7305                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7306                            VFC_MEMORIES_RST_REG_CAM_RST |
7307                            VFC_MEMORIES_RST_REG_RAM_RST);
7308
7309                 msleep(20);
7310         }
7311
7312         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7313         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7314         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7315         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7316
7317         /* sync semi rtc */
7318         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7319                0x80000000);
7320         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7321                0x80000000);
7322
7323         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7324         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7325         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7326
7327         if (!CHIP_IS_E1x(bp)) {
7328                 if (IS_MF_AFEX(bp)) {
7329                         /* configure that VNTag and VLAN headers must be
7330                          * sent in afex mode
7331                          */
7332                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7333                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7334                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7335                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7336                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7337                 } else {
7338                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7339                                bp->path_has_ovlan ? 7 : 6);
7340                 }
7341         }
7342
7343         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7344
7345         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7346
7347         if (CNIC_SUPPORT(bp)) {
7348                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7349                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7350                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7351                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7352                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7353                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7354                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7355                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7356                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7357                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7358         }
7359         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7360
7361         if (sizeof(union cdu_context) != 1024)
7362                 /* we currently assume that a context is 1024 bytes */
7363                 dev_alert(&bp->pdev->dev,
7364                           "please adjust the size of cdu_context(%ld)\n",
7365                           (long)sizeof(union cdu_context));
7366
7367         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7368         val = (4 << 24) + (0 << 12) + 1024;
7369         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7370
7371         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7372         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7373         /* enable context validation interrupt from CFC */
7374         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7375
7376         /* set the thresholds to prevent CFC/CDU race */
7377         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7378
7379         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7380
7381         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7382                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7383
7384         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7385         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7386
7387         /* Reset PCIE errors for debug */
7388         REG_WR(bp, 0x2814, 0xffffffff);
7389         REG_WR(bp, 0x3820, 0xffffffff);
7390
7391         if (!CHIP_IS_E1x(bp)) {
7392                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7393                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7394                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7395                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7396                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7397                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7398                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7399                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7400                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7401                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7402                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7403         }
7404
7405         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7406         if (!CHIP_IS_E1(bp)) {
7407                 /* in E3 this done in per-port section */
7408                 if (!CHIP_IS_E3(bp))
7409                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7410         }
7411         if (CHIP_IS_E1H(bp))
7412                 /* not applicable for E2 (and above ...) */
7413                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7414
7415         if (CHIP_REV_IS_SLOW(bp))
7416                 msleep(200);
7417
7418         /* finish CFC init */
7419         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7420         if (val != 1) {
7421                 BNX2X_ERR("CFC LL_INIT failed\n");
7422                 return -EBUSY;
7423         }
7424         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7425         if (val != 1) {
7426                 BNX2X_ERR("CFC AC_INIT failed\n");
7427                 return -EBUSY;
7428         }
7429         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7430         if (val != 1) {
7431                 BNX2X_ERR("CFC CAM_INIT failed\n");
7432                 return -EBUSY;
7433         }
7434         REG_WR(bp, CFC_REG_DEBUG0, 0);
7435
7436         if (CHIP_IS_E1(bp)) {
7437                 /* read NIG statistic
7438                    to see if this is our first up since powerup */
7439                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7440                 val = *bnx2x_sp(bp, wb_data[0]);
7441
7442                 /* do internal memory self test */
7443                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7444                         BNX2X_ERR("internal mem self test failed\n");
7445                         return -EBUSY;
7446                 }
7447         }
7448
7449         bnx2x_setup_fan_failure_detection(bp);
7450
7451         /* clear PXP2 attentions */
7452         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7453
7454         bnx2x_enable_blocks_attention(bp);
7455         bnx2x_enable_blocks_parity(bp);
7456
7457         if (!BP_NOMCP(bp)) {
7458                 if (CHIP_IS_E1x(bp))
7459                         bnx2x__common_init_phy(bp);
7460         } else
7461                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7462
7463         if (SHMEM2_HAS(bp, netproc_fw_ver))
7464                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7465
7466         return 0;
7467 }
7468
7469 /**
7470  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7471  *
7472  * @bp:         driver handle
7473  */
7474 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7475 {
7476         int rc = bnx2x_init_hw_common(bp);
7477
7478         if (rc)
7479                 return rc;
7480
7481         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7482         if (!BP_NOMCP(bp))
7483                 bnx2x__common_init_phy(bp);
7484
7485         return 0;
7486 }
7487
7488 static int bnx2x_init_hw_port(struct bnx2x *bp)
7489 {
7490         int port = BP_PORT(bp);
7491         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7492         u32 low, high;
7493         u32 val, reg;
7494
7495         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7496
7497         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7498
7499         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7500         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7501         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7502
7503         /* Timers bug workaround: disables the pf_master bit in pglue at
7504          * common phase, we need to enable it here before any dmae access are
7505          * attempted. Therefore we manually added the enable-master to the
7506          * port phase (it also happens in the function phase)
7507          */
7508         if (!CHIP_IS_E1x(bp))
7509                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7510
7511         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7512         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7513         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7514         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7515
7516         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7517         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7518         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7519         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7520
7521         /* QM cid (connection) count */
7522         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7523
7524         if (CNIC_SUPPORT(bp)) {
7525                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7526                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7527                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7528         }
7529
7530         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7531
7532         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7533
7534         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7535
7536                 if (IS_MF(bp))
7537                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7538                 else if (bp->dev->mtu > 4096) {
7539                         if (bp->flags & ONE_PORT_FLAG)
7540                                 low = 160;
7541                         else {
7542                                 val = bp->dev->mtu;
7543                                 /* (24*1024 + val*4)/256 */
7544                                 low = 96 + (val/64) +
7545                                                 ((val % 64) ? 1 : 0);
7546                         }
7547                 } else
7548                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7549                 high = low + 56;        /* 14*1024/256 */
7550                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7551                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7552         }
7553
7554         if (CHIP_MODE_IS_4_PORT(bp))
7555                 REG_WR(bp, (BP_PORT(bp) ?
7556                             BRB1_REG_MAC_GUARANTIED_1 :
7557                             BRB1_REG_MAC_GUARANTIED_0), 40);
7558
7559         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7560         if (CHIP_IS_E3B0(bp)) {
7561                 if (IS_MF_AFEX(bp)) {
7562                         /* configure headers for AFEX mode */
7563                         REG_WR(bp, BP_PORT(bp) ?
7564                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7565                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7566                         REG_WR(bp, BP_PORT(bp) ?
7567                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7568                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7569                         REG_WR(bp, BP_PORT(bp) ?
7570                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7571                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7572                 } else {
7573                         /* Ovlan exists only if we are in multi-function +
7574                          * switch-dependent mode, in switch-independent there
7575                          * is no ovlan headers
7576                          */
7577                         REG_WR(bp, BP_PORT(bp) ?
7578                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7579                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7580                                (bp->path_has_ovlan ? 7 : 6));
7581                 }
7582         }
7583
7584         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7585         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7586         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7587         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7588
7589         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7590         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7591         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7592         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7593
7594         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7595         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7596
7597         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7598
7599         if (CHIP_IS_E1x(bp)) {
7600                 /* configure PBF to work without PAUSE mtu 9000 */
7601                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7602
7603                 /* update threshold */
7604                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7605                 /* update init credit */
7606                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7607
7608                 /* probe changes */
7609                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7610                 udelay(50);
7611                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7612         }
7613
7614         if (CNIC_SUPPORT(bp))
7615                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7616
7617         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7618         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7619
7620         if (CHIP_IS_E1(bp)) {
7621                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7622                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7623         }
7624         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7625
7626         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7627
7628         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7629         /* init aeu_mask_attn_func_0/1:
7630          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7631          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7632          *             bits 4-7 are used for "per vn group attention" */
7633         val = IS_MF(bp) ? 0xF7 : 0x7;
7634         /* Enable DCBX attention for all but E1 */
7635         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7636         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7637
7638         /* SCPAD_PARITY should NOT trigger close the gates */
7639         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7640         REG_WR(bp, reg,
7641                REG_RD(bp, reg) &
7642                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7643
7644         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7645         REG_WR(bp, reg,
7646                REG_RD(bp, reg) &
7647                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7648
7649         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7650
7651         if (!CHIP_IS_E1x(bp)) {
7652                 /* Bit-map indicating which L2 hdrs may appear after the
7653                  * basic Ethernet header
7654                  */
7655                 if (IS_MF_AFEX(bp))
7656                         REG_WR(bp, BP_PORT(bp) ?
7657                                NIG_REG_P1_HDRS_AFTER_BASIC :
7658                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7659                 else
7660                         REG_WR(bp, BP_PORT(bp) ?
7661                                NIG_REG_P1_HDRS_AFTER_BASIC :
7662                                NIG_REG_P0_HDRS_AFTER_BASIC,
7663                                IS_MF_SD(bp) ? 7 : 6);
7664
7665                 if (CHIP_IS_E3(bp))
7666                         REG_WR(bp, BP_PORT(bp) ?
7667                                    NIG_REG_LLH1_MF_MODE :
7668                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7669         }
7670         if (!CHIP_IS_E3(bp))
7671                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7672
7673         if (!CHIP_IS_E1(bp)) {
7674                 /* 0x2 disable mf_ov, 0x1 enable */
7675                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7676                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7677
7678                 if (!CHIP_IS_E1x(bp)) {
7679                         val = 0;
7680                         switch (bp->mf_mode) {
7681                         case MULTI_FUNCTION_SD:
7682                                 val = 1;
7683                                 break;
7684                         case MULTI_FUNCTION_SI:
7685                         case MULTI_FUNCTION_AFEX:
7686                                 val = 2;
7687                                 break;
7688                         }
7689
7690                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7691                                                   NIG_REG_LLH0_CLS_TYPE), val);
7692                 }
7693                 {
7694                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7695                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7696                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7697                 }
7698         }
7699
7700         /* If SPIO5 is set to generate interrupts, enable it for this port */
7701         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7702         if (val & MISC_SPIO_SPIO5) {
7703                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7704                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7705                 val = REG_RD(bp, reg_addr);
7706                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7707                 REG_WR(bp, reg_addr, val);
7708         }
7709
7710         return 0;
7711 }
7712
7713 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7714 {
7715         int reg;
7716         u32 wb_write[2];
7717
7718         if (CHIP_IS_E1(bp))
7719                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7720         else
7721                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7722
7723         wb_write[0] = ONCHIP_ADDR1(addr);
7724         wb_write[1] = ONCHIP_ADDR2(addr);
7725         REG_WR_DMAE(bp, reg, wb_write, 2);
7726 }
7727
7728 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7729 {
7730         u32 data, ctl, cnt = 100;
7731         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7732         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7733         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7734         u32 sb_bit =  1 << (idu_sb_id%32);
7735         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7736         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7737
7738         /* Not supported in BC mode */
7739         if (CHIP_INT_MODE_IS_BC(bp))
7740                 return;
7741
7742         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7743                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7744                 IGU_REGULAR_CLEANUP_SET                         |
7745                 IGU_REGULAR_BCLEANUP;
7746
7747         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7748               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7749               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7750
7751         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7752                          data, igu_addr_data);
7753         REG_WR(bp, igu_addr_data, data);
7754         mmiowb();
7755         barrier();
7756         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7757                           ctl, igu_addr_ctl);
7758         REG_WR(bp, igu_addr_ctl, ctl);
7759         mmiowb();
7760         barrier();
7761
7762         /* wait for clean up to finish */
7763         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7764                 msleep(20);
7765
7766         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7767                 DP(NETIF_MSG_HW,
7768                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7769                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7770         }
7771 }
7772
7773 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7774 {
7775         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7776 }
7777
7778 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7779 {
7780         u32 i, base = FUNC_ILT_BASE(func);
7781         for (i = base; i < base + ILT_PER_FUNC; i++)
7782                 bnx2x_ilt_wr(bp, i, 0);
7783 }
7784
7785 static void bnx2x_init_searcher(struct bnx2x *bp)
7786 {
7787         int port = BP_PORT(bp);
7788         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7789         /* T1 hash bits value determines the T1 number of entries */
7790         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7791 }
7792
7793 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7794 {
7795         int rc;
7796         struct bnx2x_func_state_params func_params = {NULL};
7797         struct bnx2x_func_switch_update_params *switch_update_params =
7798                 &func_params.params.switch_update;
7799
7800         /* Prepare parameters for function state transitions */
7801         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7802         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7803
7804         func_params.f_obj = &bp->func_obj;
7805         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7806
7807         /* Function parameters */
7808         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7809                   &switch_update_params->changes);
7810         if (suspend)
7811                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7812                           &switch_update_params->changes);
7813
7814         rc = bnx2x_func_state_change(bp, &func_params);
7815
7816         return rc;
7817 }
7818
7819 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7820 {
7821         int rc, i, port = BP_PORT(bp);
7822         int vlan_en = 0, mac_en[NUM_MACS];
7823
7824         /* Close input from network */
7825         if (bp->mf_mode == SINGLE_FUNCTION) {
7826                 bnx2x_set_rx_filter(&bp->link_params, 0);
7827         } else {
7828                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7829                                    NIG_REG_LLH0_FUNC_EN);
7830                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7831                           NIG_REG_LLH0_FUNC_EN, 0);
7832                 for (i = 0; i < NUM_MACS; i++) {
7833                         mac_en[i] = REG_RD(bp, port ?
7834                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7835                                               4 * i) :
7836                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7837                                               4 * i));
7838                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7839                                               4 * i) :
7840                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7841                 }
7842         }
7843
7844         /* Close BMC to host */
7845         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7846                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7847
7848         /* Suspend Tx switching to the PF. Completion of this ramrod
7849          * further guarantees that all the packets of that PF / child
7850          * VFs in BRB were processed by the Parser, so it is safe to
7851          * change the NIC_MODE register.
7852          */
7853         rc = bnx2x_func_switch_update(bp, 1);
7854         if (rc) {
7855                 BNX2X_ERR("Can't suspend tx-switching!\n");
7856                 return rc;
7857         }
7858
7859         /* Change NIC_MODE register */
7860         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7861
7862         /* Open input from network */
7863         if (bp->mf_mode == SINGLE_FUNCTION) {
7864                 bnx2x_set_rx_filter(&bp->link_params, 1);
7865         } else {
7866                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7867                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7868                 for (i = 0; i < NUM_MACS; i++) {
7869                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7870                                               4 * i) :
7871                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7872                                   mac_en[i]);
7873                 }
7874         }
7875
7876         /* Enable BMC to host */
7877         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7878                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7879
7880         /* Resume Tx switching to the PF */
7881         rc = bnx2x_func_switch_update(bp, 0);
7882         if (rc) {
7883                 BNX2X_ERR("Can't resume tx-switching!\n");
7884                 return rc;
7885         }
7886
7887         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7888         return 0;
7889 }
7890
7891 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7892 {
7893         int rc;
7894
7895         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7896
7897         if (CONFIGURE_NIC_MODE(bp)) {
7898                 /* Configure searcher as part of function hw init */
7899                 bnx2x_init_searcher(bp);
7900
7901                 /* Reset NIC mode */
7902                 rc = bnx2x_reset_nic_mode(bp);
7903                 if (rc)
7904                         BNX2X_ERR("Can't change NIC mode!\n");
7905                 return rc;
7906         }
7907
7908         return 0;
7909 }
7910
7911 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7912  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7913  * the addresses of the transaction, resulting in was-error bit set in the pci
7914  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7915  * to clear the interrupt which detected this from the pglueb and the was done
7916  * bit
7917  */
7918 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7919 {
7920         if (!CHIP_IS_E1x(bp))
7921                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7922                        1 << BP_ABS_FUNC(bp));
7923 }
7924
7925 static int bnx2x_init_hw_func(struct bnx2x *bp)
7926 {
7927         int port = BP_PORT(bp);
7928         int func = BP_FUNC(bp);
7929         int init_phase = PHASE_PF0 + func;
7930         struct bnx2x_ilt *ilt = BP_ILT(bp);
7931         u16 cdu_ilt_start;
7932         u32 addr, val;
7933         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7934         int i, main_mem_width, rc;
7935
7936         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7937
7938         /* FLR cleanup - hmmm */
7939         if (!CHIP_IS_E1x(bp)) {
7940                 rc = bnx2x_pf_flr_clnup(bp);
7941                 if (rc) {
7942                         bnx2x_fw_dump(bp);
7943                         return rc;
7944                 }
7945         }
7946
7947         /* set MSI reconfigure capability */
7948         if (bp->common.int_block == INT_BLOCK_HC) {
7949                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7950                 val = REG_RD(bp, addr);
7951                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7952                 REG_WR(bp, addr, val);
7953         }
7954
7955         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7956         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7957
7958         ilt = BP_ILT(bp);
7959         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7960
7961         if (IS_SRIOV(bp))
7962                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7963         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7964
7965         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7966          * those of the VFs, so start line should be reset
7967          */
7968         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7969         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7970                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7971                 ilt->lines[cdu_ilt_start + i].page_mapping =
7972                         bp->context[i].cxt_mapping;
7973                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7974         }
7975
7976         bnx2x_ilt_init_op(bp, INITOP_SET);
7977
7978         if (!CONFIGURE_NIC_MODE(bp)) {
7979                 bnx2x_init_searcher(bp);
7980                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7981                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7982         } else {
7983                 /* Set NIC mode */
7984                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7985                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7986         }
7987
7988         if (!CHIP_IS_E1x(bp)) {
7989                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7990
7991                 /* Turn on a single ISR mode in IGU if driver is going to use
7992                  * INT#x or MSI
7993                  */
7994                 if (!(bp->flags & USING_MSIX_FLAG))
7995                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7996                 /*
7997                  * Timers workaround bug: function init part.
7998                  * Need to wait 20msec after initializing ILT,
7999                  * needed to make sure there are no requests in
8000                  * one of the PXP internal queues with "old" ILT addresses
8001                  */
8002                 msleep(20);
8003                 /*
8004                  * Master enable - Due to WB DMAE writes performed before this
8005                  * register is re-initialized as part of the regular function
8006                  * init
8007                  */
8008                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8009                 /* Enable the function in IGU */
8010                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8011         }
8012
8013         bp->dmae_ready = 1;
8014
8015         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8016
8017         bnx2x_clean_pglue_errors(bp);
8018
8019         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8020         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8021         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8022         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8023         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8024         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8025         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8026         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8027         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8028         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8029         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8030         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8031         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8032
8033         if (!CHIP_IS_E1x(bp))
8034                 REG_WR(bp, QM_REG_PF_EN, 1);
8035
8036         if (!CHIP_IS_E1x(bp)) {
8037                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8038                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8039                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8040                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8041         }
8042         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8043
8044         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8045         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8046         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8047
8048         bnx2x_iov_init_dq(bp);
8049
8050         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8051         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8052         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8053         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8054         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8055         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8056         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8057         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8058         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8059         if (!CHIP_IS_E1x(bp))
8060                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8061
8062         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8063
8064         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8065
8066         if (!CHIP_IS_E1x(bp))
8067                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8068
8069         if (IS_MF(bp)) {
8070                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8071                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8072                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8073                                bp->mf_ov);
8074                 }
8075         }
8076
8077         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8078
8079         /* HC init per function */
8080         if (bp->common.int_block == INT_BLOCK_HC) {
8081                 if (CHIP_IS_E1H(bp)) {
8082                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8083
8084                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8085                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8086                 }
8087                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8088
8089         } else {
8090                 int num_segs, sb_idx, prod_offset;
8091
8092                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8093
8094                 if (!CHIP_IS_E1x(bp)) {
8095                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8096                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8097                 }
8098
8099                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8100
8101                 if (!CHIP_IS_E1x(bp)) {
8102                         int dsb_idx = 0;
8103                         /**
8104                          * Producer memory:
8105                          * E2 mode: address 0-135 match to the mapping memory;
8106                          * 136 - PF0 default prod; 137 - PF1 default prod;
8107                          * 138 - PF2 default prod; 139 - PF3 default prod;
8108                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8109                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8110                          * 144-147 reserved.
8111                          *
8112                          * E1.5 mode - In backward compatible mode;
8113                          * for non default SB; each even line in the memory
8114                          * holds the U producer and each odd line hold
8115                          * the C producer. The first 128 producers are for
8116                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8117                          * producers are for the DSB for each PF.
8118                          * Each PF has five segments: (the order inside each
8119                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8120                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8121                          * 144-147 attn prods;
8122                          */
8123                         /* non-default-status-blocks */
8124                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8125                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8126                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8127                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8128                                         num_segs;
8129
8130                                 for (i = 0; i < num_segs; i++) {
8131                                         addr = IGU_REG_PROD_CONS_MEMORY +
8132                                                         (prod_offset + i) * 4;
8133                                         REG_WR(bp, addr, 0);
8134                                 }
8135                                 /* send consumer update with value 0 */
8136                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8137                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8138                                 bnx2x_igu_clear_sb(bp,
8139                                                    bp->igu_base_sb + sb_idx);
8140                         }
8141
8142                         /* default-status-blocks */
8143                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8144                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8145
8146                         if (CHIP_MODE_IS_4_PORT(bp))
8147                                 dsb_idx = BP_FUNC(bp);
8148                         else
8149                                 dsb_idx = BP_VN(bp);
8150
8151                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8152                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8153                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8154
8155                         /*
8156                          * igu prods come in chunks of E1HVN_MAX (4) -
8157                          * does not matters what is the current chip mode
8158                          */
8159                         for (i = 0; i < (num_segs * E1HVN_MAX);
8160                              i += E1HVN_MAX) {
8161                                 addr = IGU_REG_PROD_CONS_MEMORY +
8162                                                         (prod_offset + i)*4;
8163                                 REG_WR(bp, addr, 0);
8164                         }
8165                         /* send consumer update with 0 */
8166                         if (CHIP_INT_MODE_IS_BC(bp)) {
8167                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8168                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8169                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8170                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8171                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8172                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8173                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8174                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8175                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8176                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8177                         } else {
8178                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8179                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8180                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8181                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8182                         }
8183                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8184
8185                         /* !!! These should become driver const once
8186                            rf-tool supports split-68 const */
8187                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8188                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8189                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8190                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8191                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8192                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8193                 }
8194         }
8195
8196         /* Reset PCIE errors for debug */
8197         REG_WR(bp, 0x2114, 0xffffffff);
8198         REG_WR(bp, 0x2120, 0xffffffff);
8199
8200         if (CHIP_IS_E1x(bp)) {
8201                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8202                 main_mem_base = HC_REG_MAIN_MEMORY +
8203                                 BP_PORT(bp) * (main_mem_size * 4);
8204                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8205                 main_mem_width = 8;
8206
8207                 val = REG_RD(bp, main_mem_prty_clr);
8208                 if (val)
8209                         DP(NETIF_MSG_HW,
8210                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8211                            val);
8212
8213                 /* Clear "false" parity errors in MSI-X table */
8214                 for (i = main_mem_base;
8215                      i < main_mem_base + main_mem_size * 4;
8216                      i += main_mem_width) {
8217                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8218                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8219                                          i, main_mem_width / 4);
8220                 }
8221                 /* Clear HC parity attention */
8222                 REG_RD(bp, main_mem_prty_clr);
8223         }
8224
8225 #ifdef BNX2X_STOP_ON_ERROR
8226         /* Enable STORMs SP logging */
8227         REG_WR8(bp, BAR_USTRORM_INTMEM +
8228                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8229         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8230                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8231         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8232                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8233         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8234                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8235 #endif
8236
8237         bnx2x_phy_probe(&bp->link_params);
8238
8239         return 0;
8240 }
8241
8242 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8243 {
8244         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8245
8246         if (!CHIP_IS_E1x(bp))
8247                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8248                                sizeof(struct host_hc_status_block_e2));
8249         else
8250                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8251                                sizeof(struct host_hc_status_block_e1x));
8252
8253         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8254 }
8255
8256 void bnx2x_free_mem(struct bnx2x *bp)
8257 {
8258         int i;
8259
8260         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8261                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8262
8263         if (IS_VF(bp))
8264                 return;
8265
8266         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8267                        sizeof(struct host_sp_status_block));
8268
8269         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8270                        sizeof(struct bnx2x_slowpath));
8271
8272         for (i = 0; i < L2_ILT_LINES(bp); i++)
8273                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8274                                bp->context[i].size);
8275         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8276
8277         BNX2X_FREE(bp->ilt->lines);
8278
8279         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8280
8281         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8282                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8283
8284         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8285
8286         bnx2x_iov_free_mem(bp);
8287 }
8288
8289 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8290 {
8291         if (!CHIP_IS_E1x(bp)) {
8292                 /* size = the status block + ramrod buffers */
8293                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8294                                                     sizeof(struct host_hc_status_block_e2));
8295                 if (!bp->cnic_sb.e2_sb)
8296                         goto alloc_mem_err;
8297         } else {
8298                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8299                                                      sizeof(struct host_hc_status_block_e1x));
8300                 if (!bp->cnic_sb.e1x_sb)
8301                         goto alloc_mem_err;
8302         }
8303
8304         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8305                 /* allocate searcher T2 table, as it wasn't allocated before */
8306                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8307                 if (!bp->t2)
8308                         goto alloc_mem_err;
8309         }
8310
8311         /* write address to which L5 should insert its values */
8312         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8313                 &bp->slowpath->drv_info_to_mcp;
8314
8315         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8316                 goto alloc_mem_err;
8317
8318         return 0;
8319
8320 alloc_mem_err:
8321         bnx2x_free_mem_cnic(bp);
8322         BNX2X_ERR("Can't allocate memory\n");
8323         return -ENOMEM;
8324 }
8325
8326 int bnx2x_alloc_mem(struct bnx2x *bp)
8327 {
8328         int i, allocated, context_size;
8329
8330         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8331                 /* allocate searcher T2 table */
8332                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8333                 if (!bp->t2)
8334                         goto alloc_mem_err;
8335         }
8336
8337         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8338                                              sizeof(struct host_sp_status_block));
8339         if (!bp->def_status_blk)
8340                 goto alloc_mem_err;
8341
8342         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8343                                        sizeof(struct bnx2x_slowpath));
8344         if (!bp->slowpath)
8345                 goto alloc_mem_err;
8346
8347         /* Allocate memory for CDU context:
8348          * This memory is allocated separately and not in the generic ILT
8349          * functions because CDU differs in few aspects:
8350          * 1. There are multiple entities allocating memory for context -
8351          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8352          * its own ILT lines.
8353          * 2. Since CDU page-size is not a single 4KB page (which is the case
8354          * for the other ILT clients), to be efficient we want to support
8355          * allocation of sub-page-size in the last entry.
8356          * 3. Context pointers are used by the driver to pass to FW / update
8357          * the context (for the other ILT clients the pointers are used just to
8358          * free the memory during unload).
8359          */
8360         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8361
8362         for (i = 0, allocated = 0; allocated < context_size; i++) {
8363                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8364                                           (context_size - allocated));
8365                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8366                                                       bp->context[i].size);
8367                 if (!bp->context[i].vcxt)
8368                         goto alloc_mem_err;
8369                 allocated += bp->context[i].size;
8370         }
8371         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8372                                  GFP_KERNEL);
8373         if (!bp->ilt->lines)
8374                 goto alloc_mem_err;
8375
8376         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8377                 goto alloc_mem_err;
8378
8379         if (bnx2x_iov_alloc_mem(bp))
8380                 goto alloc_mem_err;
8381
8382         /* Slow path ring */
8383         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8384         if (!bp->spq)
8385                 goto alloc_mem_err;
8386
8387         /* EQ */
8388         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8389                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8390         if (!bp->eq_ring)
8391                 goto alloc_mem_err;
8392
8393         return 0;
8394
8395 alloc_mem_err:
8396         bnx2x_free_mem(bp);
8397         BNX2X_ERR("Can't allocate memory\n");
8398         return -ENOMEM;
8399 }
8400
8401 /*
8402  * Init service functions
8403  */
8404
8405 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8406                       struct bnx2x_vlan_mac_obj *obj, bool set,
8407                       int mac_type, unsigned long *ramrod_flags)
8408 {
8409         int rc;
8410         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8411
8412         memset(&ramrod_param, 0, sizeof(ramrod_param));
8413
8414         /* Fill general parameters */
8415         ramrod_param.vlan_mac_obj = obj;
8416         ramrod_param.ramrod_flags = *ramrod_flags;
8417
8418         /* Fill a user request section if needed */
8419         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8420                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8421
8422                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8423
8424                 /* Set the command: ADD or DEL */
8425                 if (set)
8426                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8427                 else
8428                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8429         }
8430
8431         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8432
8433         if (rc == -EEXIST) {
8434                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8435                 /* do not treat adding same MAC as error */
8436                 rc = 0;
8437         } else if (rc < 0)
8438                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8439
8440         return rc;
8441 }
8442
8443 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8444                        struct bnx2x_vlan_mac_obj *obj, bool set,
8445                        unsigned long *ramrod_flags)
8446 {
8447         int rc;
8448         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8449
8450         memset(&ramrod_param, 0, sizeof(ramrod_param));
8451
8452         /* Fill general parameters */
8453         ramrod_param.vlan_mac_obj = obj;
8454         ramrod_param.ramrod_flags = *ramrod_flags;
8455
8456         /* Fill a user request section if needed */
8457         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8458                 ramrod_param.user_req.u.vlan.vlan = vlan;
8459                 /* Set the command: ADD or DEL */
8460                 if (set)
8461                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8462                 else
8463                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8464         }
8465
8466         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8467
8468         if (rc == -EEXIST) {
8469                 /* Do not treat adding same vlan as error. */
8470                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8471                 rc = 0;
8472         } else if (rc < 0) {
8473                 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8474         }
8475
8476         return rc;
8477 }
8478
8479 int bnx2x_del_all_macs(struct bnx2x *bp,
8480                        struct bnx2x_vlan_mac_obj *mac_obj,
8481                        int mac_type, bool wait_for_comp)
8482 {
8483         int rc;
8484         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8485
8486         /* Wait for completion of requested */
8487         if (wait_for_comp)
8488                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8489
8490         /* Set the mac type of addresses we want to clear */
8491         __set_bit(mac_type, &vlan_mac_flags);
8492
8493         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8494         if (rc < 0)
8495                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8496
8497         return rc;
8498 }
8499
8500 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8501 {
8502         if (IS_PF(bp)) {
8503                 unsigned long ramrod_flags = 0;
8504
8505                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8506                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8507                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8508                                          &bp->sp_objs->mac_obj, set,
8509                                          BNX2X_ETH_MAC, &ramrod_flags);
8510         } else { /* vf */
8511                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8512                                              bp->fp->index, set);
8513         }
8514 }
8515
8516 int bnx2x_setup_leading(struct bnx2x *bp)
8517 {
8518         if (IS_PF(bp))
8519                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8520         else /* VF */
8521                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8522 }
8523
8524 /**
8525  * bnx2x_set_int_mode - configure interrupt mode
8526  *
8527  * @bp:         driver handle
8528  *
8529  * In case of MSI-X it will also try to enable MSI-X.
8530  */
8531 int bnx2x_set_int_mode(struct bnx2x *bp)
8532 {
8533         int rc = 0;
8534
8535         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8536                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8537                 return -EINVAL;
8538         }
8539
8540         switch (int_mode) {
8541         case BNX2X_INT_MODE_MSIX:
8542                 /* attempt to enable msix */
8543                 rc = bnx2x_enable_msix(bp);
8544
8545                 /* msix attained */
8546                 if (!rc)
8547                         return 0;
8548
8549                 /* vfs use only msix */
8550                 if (rc && IS_VF(bp))
8551                         return rc;
8552
8553                 /* failed to enable multiple MSI-X */
8554                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8555                                bp->num_queues,
8556                                1 + bp->num_cnic_queues);
8557
8558                 /* falling through... */
8559         case BNX2X_INT_MODE_MSI:
8560                 bnx2x_enable_msi(bp);
8561
8562                 /* falling through... */
8563         case BNX2X_INT_MODE_INTX:
8564                 bp->num_ethernet_queues = 1;
8565                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8566                 BNX2X_DEV_INFO("set number of queues to 1\n");
8567                 break;
8568         default:
8569                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8570                 return -EINVAL;
8571         }
8572         return 0;
8573 }
8574
8575 /* must be called prior to any HW initializations */
8576 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8577 {
8578         if (IS_SRIOV(bp))
8579                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8580         return L2_ILT_LINES(bp);
8581 }
8582
8583 void bnx2x_ilt_set_info(struct bnx2x *bp)
8584 {
8585         struct ilt_client_info *ilt_client;
8586         struct bnx2x_ilt *ilt = BP_ILT(bp);
8587         u16 line = 0;
8588
8589         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8590         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8591
8592         /* CDU */
8593         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8594         ilt_client->client_num = ILT_CLIENT_CDU;
8595         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8596         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8597         ilt_client->start = line;
8598         line += bnx2x_cid_ilt_lines(bp);
8599
8600         if (CNIC_SUPPORT(bp))
8601                 line += CNIC_ILT_LINES;
8602         ilt_client->end = line - 1;
8603
8604         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8605            ilt_client->start,
8606            ilt_client->end,
8607            ilt_client->page_size,
8608            ilt_client->flags,
8609            ilog2(ilt_client->page_size >> 12));
8610
8611         /* QM */
8612         if (QM_INIT(bp->qm_cid_count)) {
8613                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8614                 ilt_client->client_num = ILT_CLIENT_QM;
8615                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8616                 ilt_client->flags = 0;
8617                 ilt_client->start = line;
8618
8619                 /* 4 bytes for each cid */
8620                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8621                                                          QM_ILT_PAGE_SZ);
8622
8623                 ilt_client->end = line - 1;
8624
8625                 DP(NETIF_MSG_IFUP,
8626                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8627                    ilt_client->start,
8628                    ilt_client->end,
8629                    ilt_client->page_size,
8630                    ilt_client->flags,
8631                    ilog2(ilt_client->page_size >> 12));
8632         }
8633
8634         if (CNIC_SUPPORT(bp)) {
8635                 /* SRC */
8636                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8637                 ilt_client->client_num = ILT_CLIENT_SRC;
8638                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8639                 ilt_client->flags = 0;
8640                 ilt_client->start = line;
8641                 line += SRC_ILT_LINES;
8642                 ilt_client->end = line - 1;
8643
8644                 DP(NETIF_MSG_IFUP,
8645                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8646                    ilt_client->start,
8647                    ilt_client->end,
8648                    ilt_client->page_size,
8649                    ilt_client->flags,
8650                    ilog2(ilt_client->page_size >> 12));
8651
8652                 /* TM */
8653                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8654                 ilt_client->client_num = ILT_CLIENT_TM;
8655                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8656                 ilt_client->flags = 0;
8657                 ilt_client->start = line;
8658                 line += TM_ILT_LINES;
8659                 ilt_client->end = line - 1;
8660
8661                 DP(NETIF_MSG_IFUP,
8662                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8663                    ilt_client->start,
8664                    ilt_client->end,
8665                    ilt_client->page_size,
8666                    ilt_client->flags,
8667                    ilog2(ilt_client->page_size >> 12));
8668         }
8669
8670         BUG_ON(line > ILT_MAX_LINES);
8671 }
8672
8673 /**
8674  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8675  *
8676  * @bp:                 driver handle
8677  * @fp:                 pointer to fastpath
8678  * @init_params:        pointer to parameters structure
8679  *
8680  * parameters configured:
8681  *      - HC configuration
8682  *      - Queue's CDU context
8683  */
8684 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8685         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8686 {
8687         u8 cos;
8688         int cxt_index, cxt_offset;
8689
8690         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8691         if (!IS_FCOE_FP(fp)) {
8692                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8693                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8694
8695                 /* If HC is supported, enable host coalescing in the transition
8696                  * to INIT state.
8697                  */
8698                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8699                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8700
8701                 /* HC rate */
8702                 init_params->rx.hc_rate = bp->rx_ticks ?
8703                         (1000000 / bp->rx_ticks) : 0;
8704                 init_params->tx.hc_rate = bp->tx_ticks ?
8705                         (1000000 / bp->tx_ticks) : 0;
8706
8707                 /* FW SB ID */
8708                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8709                         fp->fw_sb_id;
8710
8711                 /*
8712                  * CQ index among the SB indices: FCoE clients uses the default
8713                  * SB, therefore it's different.
8714                  */
8715                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8716                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8717         }
8718
8719         /* set maximum number of COSs supported by this queue */
8720         init_params->max_cos = fp->max_cos;
8721
8722         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8723             fp->index, init_params->max_cos);
8724
8725         /* set the context pointers queue object */
8726         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8727                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8728                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8729                                 ILT_PAGE_CIDS);
8730                 init_params->cxts[cos] =
8731                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8732         }
8733 }
8734
8735 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8736                         struct bnx2x_queue_state_params *q_params,
8737                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8738                         int tx_index, bool leading)
8739 {
8740         memset(tx_only_params, 0, sizeof(*tx_only_params));
8741
8742         /* Set the command */
8743         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8744
8745         /* Set tx-only QUEUE flags: don't zero statistics */
8746         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8747
8748         /* choose the index of the cid to send the slow path on */
8749         tx_only_params->cid_index = tx_index;
8750
8751         /* Set general TX_ONLY_SETUP parameters */
8752         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8753
8754         /* Set Tx TX_ONLY_SETUP parameters */
8755         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8756
8757         DP(NETIF_MSG_IFUP,
8758            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8759            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8760            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8761            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8762
8763         /* send the ramrod */
8764         return bnx2x_queue_state_change(bp, q_params);
8765 }
8766
8767 /**
8768  * bnx2x_setup_queue - setup queue
8769  *
8770  * @bp:         driver handle
8771  * @fp:         pointer to fastpath
8772  * @leading:    is leading
8773  *
8774  * This function performs 2 steps in a Queue state machine
8775  *      actually: 1) RESET->INIT 2) INIT->SETUP
8776  */
8777
8778 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8779                        bool leading)
8780 {
8781         struct bnx2x_queue_state_params q_params = {NULL};
8782         struct bnx2x_queue_setup_params *setup_params =
8783                                                 &q_params.params.setup;
8784         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8785                                                 &q_params.params.tx_only;
8786         int rc;
8787         u8 tx_index;
8788
8789         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8790
8791         /* reset IGU state skip FCoE L2 queue */
8792         if (!IS_FCOE_FP(fp))
8793                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8794                              IGU_INT_ENABLE, 0);
8795
8796         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8797         /* We want to wait for completion in this context */
8798         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8799
8800         /* Prepare the INIT parameters */
8801         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8802
8803         /* Set the command */
8804         q_params.cmd = BNX2X_Q_CMD_INIT;
8805
8806         /* Change the state to INIT */
8807         rc = bnx2x_queue_state_change(bp, &q_params);
8808         if (rc) {
8809                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8810                 return rc;
8811         }
8812
8813         DP(NETIF_MSG_IFUP, "init complete\n");
8814
8815         /* Now move the Queue to the SETUP state... */
8816         memset(setup_params, 0, sizeof(*setup_params));
8817
8818         /* Set QUEUE flags */
8819         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8820
8821         /* Set general SETUP parameters */
8822         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8823                                 FIRST_TX_COS_INDEX);
8824
8825         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8826                             &setup_params->rxq_params);
8827
8828         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8829                            FIRST_TX_COS_INDEX);
8830
8831         /* Set the command */
8832         q_params.cmd = BNX2X_Q_CMD_SETUP;
8833
8834         if (IS_FCOE_FP(fp))
8835                 bp->fcoe_init = true;
8836
8837         /* Change the state to SETUP */
8838         rc = bnx2x_queue_state_change(bp, &q_params);
8839         if (rc) {
8840                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8841                 return rc;
8842         }
8843
8844         /* loop through the relevant tx-only indices */
8845         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8846               tx_index < fp->max_cos;
8847               tx_index++) {
8848
8849                 /* prepare and send tx-only ramrod*/
8850                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8851                                           tx_only_params, tx_index, leading);
8852                 if (rc) {
8853                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8854                                   fp->index, tx_index);
8855                         return rc;
8856                 }
8857         }
8858
8859         return rc;
8860 }
8861
8862 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8863 {
8864         struct bnx2x_fastpath *fp = &bp->fp[index];
8865         struct bnx2x_fp_txdata *txdata;
8866         struct bnx2x_queue_state_params q_params = {NULL};
8867         int rc, tx_index;
8868
8869         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8870
8871         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8872         /* We want to wait for completion in this context */
8873         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8874
8875         /* close tx-only connections */
8876         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8877              tx_index < fp->max_cos;
8878              tx_index++){
8879
8880                 /* ascertain this is a normal queue*/
8881                 txdata = fp->txdata_ptr[tx_index];
8882
8883                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8884                                                         txdata->txq_index);
8885
8886                 /* send halt terminate on tx-only connection */
8887                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8888                 memset(&q_params.params.terminate, 0,
8889                        sizeof(q_params.params.terminate));
8890                 q_params.params.terminate.cid_index = tx_index;
8891
8892                 rc = bnx2x_queue_state_change(bp, &q_params);
8893                 if (rc)
8894                         return rc;
8895
8896                 /* send halt terminate on tx-only connection */
8897                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8898                 memset(&q_params.params.cfc_del, 0,
8899                        sizeof(q_params.params.cfc_del));
8900                 q_params.params.cfc_del.cid_index = tx_index;
8901                 rc = bnx2x_queue_state_change(bp, &q_params);
8902                 if (rc)
8903                         return rc;
8904         }
8905         /* Stop the primary connection: */
8906         /* ...halt the connection */
8907         q_params.cmd = BNX2X_Q_CMD_HALT;
8908         rc = bnx2x_queue_state_change(bp, &q_params);
8909         if (rc)
8910                 return rc;
8911
8912         /* ...terminate the connection */
8913         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8914         memset(&q_params.params.terminate, 0,
8915                sizeof(q_params.params.terminate));
8916         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8917         rc = bnx2x_queue_state_change(bp, &q_params);
8918         if (rc)
8919                 return rc;
8920         /* ...delete cfc entry */
8921         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8922         memset(&q_params.params.cfc_del, 0,
8923                sizeof(q_params.params.cfc_del));
8924         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8925         return bnx2x_queue_state_change(bp, &q_params);
8926 }
8927
8928 static void bnx2x_reset_func(struct bnx2x *bp)
8929 {
8930         int port = BP_PORT(bp);
8931         int func = BP_FUNC(bp);
8932         int i;
8933
8934         /* Disable the function in the FW */
8935         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8936         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8937         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8938         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8939
8940         /* FP SBs */
8941         for_each_eth_queue(bp, i) {
8942                 struct bnx2x_fastpath *fp = &bp->fp[i];
8943                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8944                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8945                            SB_DISABLED);
8946         }
8947
8948         if (CNIC_LOADED(bp))
8949                 /* CNIC SB */
8950                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8951                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8952                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8953
8954         /* SP SB */
8955         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8956                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8957                 SB_DISABLED);
8958
8959         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8960                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8961                        0);
8962
8963         /* Configure IGU */
8964         if (bp->common.int_block == INT_BLOCK_HC) {
8965                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8966                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8967         } else {
8968                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8969                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8970         }
8971
8972         if (CNIC_LOADED(bp)) {
8973                 /* Disable Timer scan */
8974                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8975                 /*
8976                  * Wait for at least 10ms and up to 2 second for the timers
8977                  * scan to complete
8978                  */
8979                 for (i = 0; i < 200; i++) {
8980                         usleep_range(10000, 20000);
8981                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8982                                 break;
8983                 }
8984         }
8985         /* Clear ILT */
8986         bnx2x_clear_func_ilt(bp, func);
8987
8988         /* Timers workaround bug for E2: if this is vnic-3,
8989          * we need to set the entire ilt range for this timers.
8990          */
8991         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8992                 struct ilt_client_info ilt_cli;
8993                 /* use dummy TM client */
8994                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8995                 ilt_cli.start = 0;
8996                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8997                 ilt_cli.client_num = ILT_CLIENT_TM;
8998
8999                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9000         }
9001
9002         /* this assumes that reset_port() called before reset_func()*/
9003         if (!CHIP_IS_E1x(bp))
9004                 bnx2x_pf_disable(bp);
9005
9006         bp->dmae_ready = 0;
9007 }
9008
9009 static void bnx2x_reset_port(struct bnx2x *bp)
9010 {
9011         int port = BP_PORT(bp);
9012         u32 val;
9013
9014         /* Reset physical Link */
9015         bnx2x__link_reset(bp);
9016
9017         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9018
9019         /* Do not rcv packets to BRB */
9020         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9021         /* Do not direct rcv packets that are not for MCP to the BRB */
9022         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9023                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9024
9025         /* Configure AEU */
9026         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9027
9028         msleep(100);
9029         /* Check for BRB port occupancy */
9030         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9031         if (val)
9032                 DP(NETIF_MSG_IFDOWN,
9033                    "BRB1 is not empty  %d blocks are occupied\n", val);
9034
9035         /* TODO: Close Doorbell port? */
9036 }
9037
9038 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9039 {
9040         struct bnx2x_func_state_params func_params = {NULL};
9041
9042         /* Prepare parameters for function state transitions */
9043         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9044
9045         func_params.f_obj = &bp->func_obj;
9046         func_params.cmd = BNX2X_F_CMD_HW_RESET;
9047
9048         func_params.params.hw_init.load_phase = load_code;
9049
9050         return bnx2x_func_state_change(bp, &func_params);
9051 }
9052
9053 static int bnx2x_func_stop(struct bnx2x *bp)
9054 {
9055         struct bnx2x_func_state_params func_params = {NULL};
9056         int rc;
9057
9058         /* Prepare parameters for function state transitions */
9059         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9060         func_params.f_obj = &bp->func_obj;
9061         func_params.cmd = BNX2X_F_CMD_STOP;
9062
9063         /*
9064          * Try to stop the function the 'good way'. If fails (in case
9065          * of a parity error during bnx2x_chip_cleanup()) and we are
9066          * not in a debug mode, perform a state transaction in order to
9067          * enable further HW_RESET transaction.
9068          */
9069         rc = bnx2x_func_state_change(bp, &func_params);
9070         if (rc) {
9071 #ifdef BNX2X_STOP_ON_ERROR
9072                 return rc;
9073 #else
9074                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9075                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9076                 return bnx2x_func_state_change(bp, &func_params);
9077 #endif
9078         }
9079
9080         return 0;
9081 }
9082
9083 /**
9084  * bnx2x_send_unload_req - request unload mode from the MCP.
9085  *
9086  * @bp:                 driver handle
9087  * @unload_mode:        requested function's unload mode
9088  *
9089  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9090  */
9091 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9092 {
9093         u32 reset_code = 0;
9094         int port = BP_PORT(bp);
9095
9096         /* Select the UNLOAD request mode */
9097         if (unload_mode == UNLOAD_NORMAL)
9098                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9099
9100         else if (bp->flags & NO_WOL_FLAG)
9101                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9102
9103         else if (bp->wol) {
9104                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9105                 u8 *mac_addr = bp->dev->dev_addr;
9106                 struct pci_dev *pdev = bp->pdev;
9107                 u32 val;
9108                 u16 pmc;
9109
9110                 /* The mac address is written to entries 1-4 to
9111                  * preserve entry 0 which is used by the PMF
9112                  */
9113                 u8 entry = (BP_VN(bp) + 1)*8;
9114
9115                 val = (mac_addr[0] << 8) | mac_addr[1];
9116                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9117
9118                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9119                       (mac_addr[4] << 8) | mac_addr[5];
9120                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9121
9122                 /* Enable the PME and clear the status */
9123                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9124                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9125                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9126
9127                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9128
9129         } else
9130                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9131
9132         /* Send the request to the MCP */
9133         if (!BP_NOMCP(bp))
9134                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9135         else {
9136                 int path = BP_PATH(bp);
9137
9138                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9139                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9140                    bnx2x_load_count[path][2]);
9141                 bnx2x_load_count[path][0]--;
9142                 bnx2x_load_count[path][1 + port]--;
9143                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9144                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9145                    bnx2x_load_count[path][2]);
9146                 if (bnx2x_load_count[path][0] == 0)
9147                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9148                 else if (bnx2x_load_count[path][1 + port] == 0)
9149                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9150                 else
9151                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9152         }
9153
9154         return reset_code;
9155 }
9156
9157 /**
9158  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9159  *
9160  * @bp:         driver handle
9161  * @keep_link:          true iff link should be kept up
9162  */
9163 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9164 {
9165         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9166
9167         /* Report UNLOAD_DONE to MCP */
9168         if (!BP_NOMCP(bp))
9169                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9170 }
9171
9172 static int bnx2x_func_wait_started(struct bnx2x *bp)
9173 {
9174         int tout = 50;
9175         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9176
9177         if (!bp->port.pmf)
9178                 return 0;
9179
9180         /*
9181          * (assumption: No Attention from MCP at this stage)
9182          * PMF probably in the middle of TX disable/enable transaction
9183          * 1. Sync IRS for default SB
9184          * 2. Sync SP queue - this guarantees us that attention handling started
9185          * 3. Wait, that TX disable/enable transaction completes
9186          *
9187          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9188          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9189          * received completion for the transaction the state is TX_STOPPED.
9190          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9191          * transaction.
9192          */
9193
9194         /* make sure default SB ISR is done */
9195         if (msix)
9196                 synchronize_irq(bp->msix_table[0].vector);
9197         else
9198                 synchronize_irq(bp->pdev->irq);
9199
9200         flush_workqueue(bnx2x_wq);
9201         flush_workqueue(bnx2x_iov_wq);
9202
9203         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9204                                 BNX2X_F_STATE_STARTED && tout--)
9205                 msleep(20);
9206
9207         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9208                                                 BNX2X_F_STATE_STARTED) {
9209 #ifdef BNX2X_STOP_ON_ERROR
9210                 BNX2X_ERR("Wrong function state\n");
9211                 return -EBUSY;
9212 #else
9213                 /*
9214                  * Failed to complete the transaction in a "good way"
9215                  * Force both transactions with CLR bit
9216                  */
9217                 struct bnx2x_func_state_params func_params = {NULL};
9218
9219                 DP(NETIF_MSG_IFDOWN,
9220                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9221
9222                 func_params.f_obj = &bp->func_obj;
9223                 __set_bit(RAMROD_DRV_CLR_ONLY,
9224                                         &func_params.ramrod_flags);
9225
9226                 /* STARTED-->TX_ST0PPED */
9227                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9228                 bnx2x_func_state_change(bp, &func_params);
9229
9230                 /* TX_ST0PPED-->STARTED */
9231                 func_params.cmd = BNX2X_F_CMD_TX_START;
9232                 return bnx2x_func_state_change(bp, &func_params);
9233 #endif
9234         }
9235
9236         return 0;
9237 }
9238
9239 static void bnx2x_disable_ptp(struct bnx2x *bp)
9240 {
9241         int port = BP_PORT(bp);
9242
9243         /* Disable sending PTP packets to host */
9244         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9245                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9246
9247         /* Reset PTP event detection rules */
9248         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9249                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9250         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9251                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9252         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9253                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9254         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9255                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9256
9257         /* Disable the PTP feature */
9258         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9259                NIG_REG_P0_PTP_EN, 0x0);
9260 }
9261
9262 /* Called during unload, to stop PTP-related stuff */
9263 static void bnx2x_stop_ptp(struct bnx2x *bp)
9264 {
9265         /* Cancel PTP work queue. Should be done after the Tx queues are
9266          * drained to prevent additional scheduling.
9267          */
9268         cancel_work_sync(&bp->ptp_task);
9269
9270         if (bp->ptp_tx_skb) {
9271                 dev_kfree_skb_any(bp->ptp_tx_skb);
9272                 bp->ptp_tx_skb = NULL;
9273         }
9274
9275         /* Disable PTP in HW */
9276         bnx2x_disable_ptp(bp);
9277
9278         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9279 }
9280
9281 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9282 {
9283         int port = BP_PORT(bp);
9284         int i, rc = 0;
9285         u8 cos;
9286         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9287         u32 reset_code;
9288
9289         /* Wait until tx fastpath tasks complete */
9290         for_each_tx_queue(bp, i) {
9291                 struct bnx2x_fastpath *fp = &bp->fp[i];
9292
9293                 for_each_cos_in_tx_queue(fp, cos)
9294                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9295 #ifdef BNX2X_STOP_ON_ERROR
9296                 if (rc)
9297                         return;
9298 #endif
9299         }
9300
9301         /* Give HW time to discard old tx messages */
9302         usleep_range(1000, 2000);
9303
9304         /* Clean all ETH MACs */
9305         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9306                                 false);
9307         if (rc < 0)
9308                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9309
9310         /* Clean up UC list  */
9311         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9312                                 true);
9313         if (rc < 0)
9314                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9315                           rc);
9316
9317         /* Disable LLH */
9318         if (!CHIP_IS_E1(bp))
9319                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9320
9321         /* Set "drop all" (stop Rx).
9322          * We need to take a netif_addr_lock() here in order to prevent
9323          * a race between the completion code and this code.
9324          */
9325         netif_addr_lock_bh(bp->dev);
9326         /* Schedule the rx_mode command */
9327         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9328                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9329         else
9330                 bnx2x_set_storm_rx_mode(bp);
9331
9332         /* Cleanup multicast configuration */
9333         rparam.mcast_obj = &bp->mcast_obj;
9334         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9335         if (rc < 0)
9336                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9337
9338         netif_addr_unlock_bh(bp->dev);
9339
9340         bnx2x_iov_chip_cleanup(bp);
9341
9342         /*
9343          * Send the UNLOAD_REQUEST to the MCP. This will return if
9344          * this function should perform FUNC, PORT or COMMON HW
9345          * reset.
9346          */
9347         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9348
9349         /*
9350          * (assumption: No Attention from MCP at this stage)
9351          * PMF probably in the middle of TX disable/enable transaction
9352          */
9353         rc = bnx2x_func_wait_started(bp);
9354         if (rc) {
9355                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9356 #ifdef BNX2X_STOP_ON_ERROR
9357                 return;
9358 #endif
9359         }
9360
9361         /* Close multi and leading connections
9362          * Completions for ramrods are collected in a synchronous way
9363          */
9364         for_each_eth_queue(bp, i)
9365                 if (bnx2x_stop_queue(bp, i))
9366 #ifdef BNX2X_STOP_ON_ERROR
9367                         return;
9368 #else
9369                         goto unload_error;
9370 #endif
9371
9372         if (CNIC_LOADED(bp)) {
9373                 for_each_cnic_queue(bp, i)
9374                         if (bnx2x_stop_queue(bp, i))
9375 #ifdef BNX2X_STOP_ON_ERROR
9376                                 return;
9377 #else
9378                                 goto unload_error;
9379 #endif
9380         }
9381
9382         /* If SP settings didn't get completed so far - something
9383          * very wrong has happen.
9384          */
9385         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9386                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9387
9388 #ifndef BNX2X_STOP_ON_ERROR
9389 unload_error:
9390 #endif
9391         rc = bnx2x_func_stop(bp);
9392         if (rc) {
9393                 BNX2X_ERR("Function stop failed!\n");
9394 #ifdef BNX2X_STOP_ON_ERROR
9395                 return;
9396 #endif
9397         }
9398
9399         /* stop_ptp should be after the Tx queues are drained to prevent
9400          * scheduling to the cancelled PTP work queue. It should also be after
9401          * function stop ramrod is sent, since as part of this ramrod FW access
9402          * PTP registers.
9403          */
9404         if (bp->flags & PTP_SUPPORTED)
9405                 bnx2x_stop_ptp(bp);
9406
9407         /* Disable HW interrupts, NAPI */
9408         bnx2x_netif_stop(bp, 1);
9409         /* Delete all NAPI objects */
9410         bnx2x_del_all_napi(bp);
9411         if (CNIC_LOADED(bp))
9412                 bnx2x_del_all_napi_cnic(bp);
9413
9414         /* Release IRQs */
9415         bnx2x_free_irq(bp);
9416
9417         /* Reset the chip, unless PCI function is offline. If we reach this
9418          * point following a PCI error handling, it means device is really
9419          * in a bad state and we're about to remove it, so reset the chip
9420          * is not a good idea.
9421          */
9422         if (!pci_channel_offline(bp->pdev)) {
9423                 rc = bnx2x_reset_hw(bp, reset_code);
9424                 if (rc)
9425                         BNX2X_ERR("HW_RESET failed\n");
9426         }
9427
9428         /* Report UNLOAD_DONE to MCP */
9429         bnx2x_send_unload_done(bp, keep_link);
9430 }
9431
9432 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9433 {
9434         u32 val;
9435
9436         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9437
9438         if (CHIP_IS_E1(bp)) {
9439                 int port = BP_PORT(bp);
9440                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9441                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9442
9443                 val = REG_RD(bp, addr);
9444                 val &= ~(0x300);
9445                 REG_WR(bp, addr, val);
9446         } else {
9447                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9448                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9449                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9450                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9451         }
9452 }
9453
9454 /* Close gates #2, #3 and #4: */
9455 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9456 {
9457         u32 val;
9458
9459         /* Gates #2 and #4a are closed/opened for "not E1" only */
9460         if (!CHIP_IS_E1(bp)) {
9461                 /* #4 */
9462                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9463                 /* #2 */
9464                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9465         }
9466
9467         /* #3 */
9468         if (CHIP_IS_E1x(bp)) {
9469                 /* Prevent interrupts from HC on both ports */
9470                 val = REG_RD(bp, HC_REG_CONFIG_1);
9471                 REG_WR(bp, HC_REG_CONFIG_1,
9472                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9473                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9474
9475                 val = REG_RD(bp, HC_REG_CONFIG_0);
9476                 REG_WR(bp, HC_REG_CONFIG_0,
9477                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9478                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9479         } else {
9480                 /* Prevent incoming interrupts in IGU */
9481                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9482
9483                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9484                        (!close) ?
9485                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9486                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9487         }
9488
9489         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9490                 close ? "closing" : "opening");
9491         mmiowb();
9492 }
9493
9494 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9495
9496 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9497 {
9498         /* Do some magic... */
9499         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9500         *magic_val = val & SHARED_MF_CLP_MAGIC;
9501         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9502 }
9503
9504 /**
9505  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9506  *
9507  * @bp:         driver handle
9508  * @magic_val:  old value of the `magic' bit.
9509  */
9510 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9511 {
9512         /* Restore the `magic' bit value... */
9513         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9514         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9515                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9516 }
9517
9518 /**
9519  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9520  *
9521  * @bp:         driver handle
9522  * @magic_val:  old value of 'magic' bit.
9523  *
9524  * Takes care of CLP configurations.
9525  */
9526 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9527 {
9528         u32 shmem;
9529         u32 validity_offset;
9530
9531         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9532
9533         /* Set `magic' bit in order to save MF config */
9534         if (!CHIP_IS_E1(bp))
9535                 bnx2x_clp_reset_prep(bp, magic_val);
9536
9537         /* Get shmem offset */
9538         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9539         validity_offset =
9540                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9541
9542         /* Clear validity map flags */
9543         if (shmem > 0)
9544                 REG_WR(bp, shmem + validity_offset, 0);
9545 }
9546
9547 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9548 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9549
9550 /**
9551  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9552  *
9553  * @bp: driver handle
9554  */
9555 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9556 {
9557         /* special handling for emulation and FPGA,
9558            wait 10 times longer */
9559         if (CHIP_REV_IS_SLOW(bp))
9560                 msleep(MCP_ONE_TIMEOUT*10);
9561         else
9562                 msleep(MCP_ONE_TIMEOUT);
9563 }
9564
9565 /*
9566  * initializes bp->common.shmem_base and waits for validity signature to appear
9567  */
9568 static int bnx2x_init_shmem(struct bnx2x *bp)
9569 {
9570         int cnt = 0;
9571         u32 val = 0;
9572
9573         do {
9574                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9575                 if (bp->common.shmem_base) {
9576                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9577                         if (val & SHR_MEM_VALIDITY_MB)
9578                                 return 0;
9579                 }
9580
9581                 bnx2x_mcp_wait_one(bp);
9582
9583         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9584
9585         BNX2X_ERR("BAD MCP validity signature\n");
9586
9587         return -ENODEV;
9588 }
9589
9590 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9591 {
9592         int rc = bnx2x_init_shmem(bp);
9593
9594         /* Restore the `magic' bit value */
9595         if (!CHIP_IS_E1(bp))
9596                 bnx2x_clp_reset_done(bp, magic_val);
9597
9598         return rc;
9599 }
9600
9601 static void bnx2x_pxp_prep(struct bnx2x *bp)
9602 {
9603         if (!CHIP_IS_E1(bp)) {
9604                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9605                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9606                 mmiowb();
9607         }
9608 }
9609
9610 /*
9611  * Reset the whole chip except for:
9612  *      - PCIE core
9613  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9614  *              one reset bit)
9615  *      - IGU
9616  *      - MISC (including AEU)
9617  *      - GRC
9618  *      - RBCN, RBCP
9619  */
9620 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9621 {
9622         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9623         u32 global_bits2, stay_reset2;
9624
9625         /*
9626          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9627          * (per chip) blocks.
9628          */
9629         global_bits2 =
9630                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9631                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9632
9633         /* Don't reset the following blocks.
9634          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9635          *            reset, as in 4 port device they might still be owned
9636          *            by the MCP (there is only one leader per path).
9637          */
9638         not_reset_mask1 =
9639                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9640                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9641                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9642
9643         not_reset_mask2 =
9644                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9645                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9646                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9647                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9648                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9649                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9650                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9651                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9652                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9653                 MISC_REGISTERS_RESET_REG_2_PGLC |
9654                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9655                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9656                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9657                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9658                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9659                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9660
9661         /*
9662          * Keep the following blocks in reset:
9663          *  - all xxMACs are handled by the bnx2x_link code.
9664          */
9665         stay_reset2 =
9666                 MISC_REGISTERS_RESET_REG_2_XMAC |
9667                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9668
9669         /* Full reset masks according to the chip */
9670         reset_mask1 = 0xffffffff;
9671
9672         if (CHIP_IS_E1(bp))
9673                 reset_mask2 = 0xffff;
9674         else if (CHIP_IS_E1H(bp))
9675                 reset_mask2 = 0x1ffff;
9676         else if (CHIP_IS_E2(bp))
9677                 reset_mask2 = 0xfffff;
9678         else /* CHIP_IS_E3 */
9679                 reset_mask2 = 0x3ffffff;
9680
9681         /* Don't reset global blocks unless we need to */
9682         if (!global)
9683                 reset_mask2 &= ~global_bits2;
9684
9685         /*
9686          * In case of attention in the QM, we need to reset PXP
9687          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9688          * because otherwise QM reset would release 'close the gates' shortly
9689          * before resetting the PXP, then the PSWRQ would send a write
9690          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9691          * read the payload data from PSWWR, but PSWWR would not
9692          * respond. The write queue in PGLUE would stuck, dmae commands
9693          * would not return. Therefore it's important to reset the second
9694          * reset register (containing the
9695          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9696          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9697          * bit).
9698          */
9699         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9700                reset_mask2 & (~not_reset_mask2));
9701
9702         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9703                reset_mask1 & (~not_reset_mask1));
9704
9705         barrier();
9706         mmiowb();
9707
9708         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9709                reset_mask2 & (~stay_reset2));
9710
9711         barrier();
9712         mmiowb();
9713
9714         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9715         mmiowb();
9716 }
9717
9718 /**
9719  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9720  * It should get cleared in no more than 1s.
9721  *
9722  * @bp: driver handle
9723  *
9724  * It should get cleared in no more than 1s. Returns 0 if
9725  * pending writes bit gets cleared.
9726  */
9727 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9728 {
9729         u32 cnt = 1000;
9730         u32 pend_bits = 0;
9731
9732         do {
9733                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9734
9735                 if (pend_bits == 0)
9736                         break;
9737
9738                 usleep_range(1000, 2000);
9739         } while (cnt-- > 0);
9740
9741         if (cnt <= 0) {
9742                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9743                           pend_bits);
9744                 return -EBUSY;
9745         }
9746
9747         return 0;
9748 }
9749
9750 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9751 {
9752         int cnt = 1000;
9753         u32 val = 0;
9754         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9755         u32 tags_63_32 = 0;
9756
9757         /* Empty the Tetris buffer, wait for 1s */
9758         do {
9759                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9760                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9761                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9762                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9763                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9764                 if (CHIP_IS_E3(bp))
9765                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9766
9767                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9768                     ((port_is_idle_0 & 0x1) == 0x1) &&
9769                     ((port_is_idle_1 & 0x1) == 0x1) &&
9770                     (pgl_exp_rom2 == 0xffffffff) &&
9771                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9772                         break;
9773                 usleep_range(1000, 2000);
9774         } while (cnt-- > 0);
9775
9776         if (cnt <= 0) {
9777                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9778                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9779                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9780                           pgl_exp_rom2);
9781                 return -EAGAIN;
9782         }
9783
9784         barrier();
9785
9786         /* Close gates #2, #3 and #4 */
9787         bnx2x_set_234_gates(bp, true);
9788
9789         /* Poll for IGU VQs for 57712 and newer chips */
9790         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9791                 return -EAGAIN;
9792
9793         /* TBD: Indicate that "process kill" is in progress to MCP */
9794
9795         /* Clear "unprepared" bit */
9796         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9797         barrier();
9798
9799         /* Make sure all is written to the chip before the reset */
9800         mmiowb();
9801
9802         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9803          * PSWHST, GRC and PSWRD Tetris buffer.
9804          */
9805         usleep_range(1000, 2000);
9806
9807         /* Prepare to chip reset: */
9808         /* MCP */
9809         if (global)
9810                 bnx2x_reset_mcp_prep(bp, &val);
9811
9812         /* PXP */
9813         bnx2x_pxp_prep(bp);
9814         barrier();
9815
9816         /* reset the chip */
9817         bnx2x_process_kill_chip_reset(bp, global);
9818         barrier();
9819
9820         /* clear errors in PGB */
9821         if (!CHIP_IS_E1x(bp))
9822                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9823
9824         /* Recover after reset: */
9825         /* MCP */
9826         if (global && bnx2x_reset_mcp_comp(bp, val))
9827                 return -EAGAIN;
9828
9829         /* TBD: Add resetting the NO_MCP mode DB here */
9830
9831         /* Open the gates #2, #3 and #4 */
9832         bnx2x_set_234_gates(bp, false);
9833
9834         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9835          * reset state, re-enable attentions. */
9836
9837         return 0;
9838 }
9839
9840 static int bnx2x_leader_reset(struct bnx2x *bp)
9841 {
9842         int rc = 0;
9843         bool global = bnx2x_reset_is_global(bp);
9844         u32 load_code;
9845
9846         /* if not going to reset MCP - load "fake" driver to reset HW while
9847          * driver is owner of the HW
9848          */
9849         if (!global && !BP_NOMCP(bp)) {
9850                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9851                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9852                 if (!load_code) {
9853                         BNX2X_ERR("MCP response failure, aborting\n");
9854                         rc = -EAGAIN;
9855                         goto exit_leader_reset;
9856                 }
9857                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9858                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9859                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9860                         rc = -EAGAIN;
9861                         goto exit_leader_reset2;
9862                 }
9863                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9864                 if (!load_code) {
9865                         BNX2X_ERR("MCP response failure, aborting\n");
9866                         rc = -EAGAIN;
9867                         goto exit_leader_reset2;
9868                 }
9869         }
9870
9871         /* Try to recover after the failure */
9872         if (bnx2x_process_kill(bp, global)) {
9873                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9874                           BP_PATH(bp));
9875                 rc = -EAGAIN;
9876                 goto exit_leader_reset2;
9877         }
9878
9879         /*
9880          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9881          * state.
9882          */
9883         bnx2x_set_reset_done(bp);
9884         if (global)
9885                 bnx2x_clear_reset_global(bp);
9886
9887 exit_leader_reset2:
9888         /* unload "fake driver" if it was loaded */
9889         if (!global && !BP_NOMCP(bp)) {
9890                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9891                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9892         }
9893 exit_leader_reset:
9894         bp->is_leader = 0;
9895         bnx2x_release_leader_lock(bp);
9896         smp_mb();
9897         return rc;
9898 }
9899
9900 static void bnx2x_recovery_failed(struct bnx2x *bp)
9901 {
9902         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9903
9904         /* Disconnect this device */
9905         netif_device_detach(bp->dev);
9906
9907         /*
9908          * Block ifup for all function on this engine until "process kill"
9909          * or power cycle.
9910          */
9911         bnx2x_set_reset_in_progress(bp);
9912
9913         /* Shut down the power */
9914         bnx2x_set_power_state(bp, PCI_D3hot);
9915
9916         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9917
9918         smp_mb();
9919 }
9920
9921 /*
9922  * Assumption: runs under rtnl lock. This together with the fact
9923  * that it's called only from bnx2x_sp_rtnl() ensure that it
9924  * will never be called when netif_running(bp->dev) is false.
9925  */
9926 static void bnx2x_parity_recover(struct bnx2x *bp)
9927 {
9928         bool global = false;
9929         u32 error_recovered, error_unrecovered;
9930         bool is_parity;
9931
9932         DP(NETIF_MSG_HW, "Handling parity\n");
9933         while (1) {
9934                 switch (bp->recovery_state) {
9935                 case BNX2X_RECOVERY_INIT:
9936                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9937                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9938                         WARN_ON(!is_parity);
9939
9940                         /* Try to get a LEADER_LOCK HW lock */
9941                         if (bnx2x_trylock_leader_lock(bp)) {
9942                                 bnx2x_set_reset_in_progress(bp);
9943                                 /*
9944                                  * Check if there is a global attention and if
9945                                  * there was a global attention, set the global
9946                                  * reset bit.
9947                                  */
9948
9949                                 if (global)
9950                                         bnx2x_set_reset_global(bp);
9951
9952                                 bp->is_leader = 1;
9953                         }
9954
9955                         /* Stop the driver */
9956                         /* If interface has been removed - break */
9957                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9958                                 return;
9959
9960                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9961
9962                         /* Ensure "is_leader", MCP command sequence and
9963                          * "recovery_state" update values are seen on other
9964                          * CPUs.
9965                          */
9966                         smp_mb();
9967                         break;
9968
9969                 case BNX2X_RECOVERY_WAIT:
9970                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9971                         if (bp->is_leader) {
9972                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9973                                 bool other_load_status =
9974                                         bnx2x_get_load_status(bp, other_engine);
9975                                 bool load_status =
9976                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9977                                 global = bnx2x_reset_is_global(bp);
9978
9979                                 /*
9980                                  * In case of a parity in a global block, let
9981                                  * the first leader that performs a
9982                                  * leader_reset() reset the global blocks in
9983                                  * order to clear global attentions. Otherwise
9984                                  * the gates will remain closed for that
9985                                  * engine.
9986                                  */
9987                                 if (load_status ||
9988                                     (global && other_load_status)) {
9989                                         /* Wait until all other functions get
9990                                          * down.
9991                                          */
9992                                         schedule_delayed_work(&bp->sp_rtnl_task,
9993                                                                 HZ/10);
9994                                         return;
9995                                 } else {
9996                                         /* If all other functions got down -
9997                                          * try to bring the chip back to
9998                                          * normal. In any case it's an exit
9999                                          * point for a leader.
10000                                          */
10001                                         if (bnx2x_leader_reset(bp)) {
10002                                                 bnx2x_recovery_failed(bp);
10003                                                 return;
10004                                         }
10005
10006                                         /* If we are here, means that the
10007                                          * leader has succeeded and doesn't
10008                                          * want to be a leader any more. Try
10009                                          * to continue as a none-leader.
10010                                          */
10011                                         break;
10012                                 }
10013                         } else { /* non-leader */
10014                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10015                                         /* Try to get a LEADER_LOCK HW lock as
10016                                          * long as a former leader may have
10017                                          * been unloaded by the user or
10018                                          * released a leadership by another
10019                                          * reason.
10020                                          */
10021                                         if (bnx2x_trylock_leader_lock(bp)) {
10022                                                 /* I'm a leader now! Restart a
10023                                                  * switch case.
10024                                                  */
10025                                                 bp->is_leader = 1;
10026                                                 break;
10027                                         }
10028
10029                                         schedule_delayed_work(&bp->sp_rtnl_task,
10030                                                                 HZ/10);
10031                                         return;
10032
10033                                 } else {
10034                                         /*
10035                                          * If there was a global attention, wait
10036                                          * for it to be cleared.
10037                                          */
10038                                         if (bnx2x_reset_is_global(bp)) {
10039                                                 schedule_delayed_work(
10040                                                         &bp->sp_rtnl_task,
10041                                                         HZ/10);
10042                                                 return;
10043                                         }
10044
10045                                         error_recovered =
10046                                           bp->eth_stats.recoverable_error;
10047                                         error_unrecovered =
10048                                           bp->eth_stats.unrecoverable_error;
10049                                         bp->recovery_state =
10050                                                 BNX2X_RECOVERY_NIC_LOADING;
10051                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10052                                                 error_unrecovered++;
10053                                                 netdev_err(bp->dev,
10054                                                            "Recovery failed. Power cycle needed\n");
10055                                                 /* Disconnect this device */
10056                                                 netif_device_detach(bp->dev);
10057                                                 /* Shut down the power */
10058                                                 bnx2x_set_power_state(
10059                                                         bp, PCI_D3hot);
10060                                                 smp_mb();
10061                                         } else {
10062                                                 bp->recovery_state =
10063                                                         BNX2X_RECOVERY_DONE;
10064                                                 error_recovered++;
10065                                                 smp_mb();
10066                                         }
10067                                         bp->eth_stats.recoverable_error =
10068                                                 error_recovered;
10069                                         bp->eth_stats.unrecoverable_error =
10070                                                 error_unrecovered;
10071
10072                                         return;
10073                                 }
10074                         }
10075                 default:
10076                         return;
10077                 }
10078         }
10079 }
10080
10081 static int bnx2x_udp_port_update(struct bnx2x *bp)
10082 {
10083         struct bnx2x_func_switch_update_params *switch_update_params;
10084         struct bnx2x_func_state_params func_params = {NULL};
10085         struct bnx2x_udp_tunnel *udp_tunnel;
10086         u16 vxlan_port = 0, geneve_port = 0;
10087         int rc;
10088
10089         switch_update_params = &func_params.params.switch_update;
10090
10091         /* Prepare parameters for function state transitions */
10092         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10093         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10094
10095         func_params.f_obj = &bp->func_obj;
10096         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10097
10098         /* Function parameters */
10099         __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10100                   &switch_update_params->changes);
10101
10102         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10103                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10104                 geneve_port = udp_tunnel->dst_port;
10105                 switch_update_params->geneve_dst_port = geneve_port;
10106         }
10107
10108         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10109                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10110                 vxlan_port = udp_tunnel->dst_port;
10111                 switch_update_params->vxlan_dst_port = vxlan_port;
10112         }
10113
10114         /* Re-enable inner-rss for the offloaded UDP tunnels */
10115         __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10116                   &switch_update_params->changes);
10117
10118         rc = bnx2x_func_state_change(bp, &func_params);
10119         if (rc)
10120                 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10121                           vxlan_port, geneve_port, rc);
10122         else
10123                 DP(BNX2X_MSG_SP,
10124                    "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10125                    vxlan_port, geneve_port);
10126
10127         return rc;
10128 }
10129
10130 static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10131                                  enum bnx2x_udp_port_type type)
10132 {
10133         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10134
10135         if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp))
10136                 return;
10137
10138         if (udp_port->count && udp_port->dst_port == port) {
10139                 udp_port->count++;
10140                 return;
10141         }
10142
10143         if (udp_port->count) {
10144                 DP(BNX2X_MSG_SP,
10145                    "UDP tunnel [%d] -  destination port limit reached\n",
10146                    type);
10147                 return;
10148         }
10149
10150         udp_port->dst_port = port;
10151         udp_port->count = 1;
10152         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10153 }
10154
10155 static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10156                                  enum bnx2x_udp_port_type type)
10157 {
10158         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10159
10160         if (!IS_PF(bp) || CHIP_IS_E1x(bp))
10161                 return;
10162
10163         if (!udp_port->count || udp_port->dst_port != port) {
10164                 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10165                    type);
10166                 return;
10167         }
10168
10169         /* Remove reference, and make certain it's no longer in use */
10170         udp_port->count--;
10171         if (udp_port->count)
10172                 return;
10173         udp_port->dst_port = 0;
10174
10175         if (netif_running(bp->dev))
10176                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10177         else
10178                 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10179                    type, port);
10180 }
10181
10182 static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10183                                  struct udp_tunnel_info *ti)
10184 {
10185         struct bnx2x *bp = netdev_priv(netdev);
10186         u16 t_port = ntohs(ti->port);
10187
10188         switch (ti->type) {
10189         case UDP_TUNNEL_TYPE_VXLAN:
10190                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10191                 break;
10192         case UDP_TUNNEL_TYPE_GENEVE:
10193                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10194                 break;
10195         default:
10196                 break;
10197         }
10198 }
10199
10200 static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10201                                  struct udp_tunnel_info *ti)
10202 {
10203         struct bnx2x *bp = netdev_priv(netdev);
10204         u16 t_port = ntohs(ti->port);
10205
10206         switch (ti->type) {
10207         case UDP_TUNNEL_TYPE_VXLAN:
10208                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10209                 break;
10210         case UDP_TUNNEL_TYPE_GENEVE:
10211                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10212                 break;
10213         default:
10214                 break;
10215         }
10216 }
10217
10218 static int bnx2x_close(struct net_device *dev);
10219
10220 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10221  * scheduled on a general queue in order to prevent a dead lock.
10222  */
10223 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10224 {
10225         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10226
10227         rtnl_lock();
10228
10229         if (!netif_running(bp->dev)) {
10230                 rtnl_unlock();
10231                 return;
10232         }
10233
10234         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10235 #ifdef BNX2X_STOP_ON_ERROR
10236                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10237                           "you will need to reboot when done\n");
10238                 goto sp_rtnl_not_reset;
10239 #endif
10240                 /*
10241                  * Clear all pending SP commands as we are going to reset the
10242                  * function anyway.
10243                  */
10244                 bp->sp_rtnl_state = 0;
10245                 smp_mb();
10246
10247                 bnx2x_parity_recover(bp);
10248
10249                 rtnl_unlock();
10250                 return;
10251         }
10252
10253         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10254 #ifdef BNX2X_STOP_ON_ERROR
10255                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10256                           "you will need to reboot when done\n");
10257                 goto sp_rtnl_not_reset;
10258 #endif
10259
10260                 /*
10261                  * Clear all pending SP commands as we are going to reset the
10262                  * function anyway.
10263                  */
10264                 bp->sp_rtnl_state = 0;
10265                 smp_mb();
10266
10267                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10268                 bnx2x_nic_load(bp, LOAD_NORMAL);
10269
10270                 rtnl_unlock();
10271                 return;
10272         }
10273 #ifdef BNX2X_STOP_ON_ERROR
10274 sp_rtnl_not_reset:
10275 #endif
10276         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10277                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10278         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10279                 bnx2x_after_function_update(bp);
10280         /*
10281          * in case of fan failure we need to reset id if the "stop on error"
10282          * debug flag is set, since we trying to prevent permanent overheating
10283          * damage
10284          */
10285         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10286                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10287                 netif_device_detach(bp->dev);
10288                 bnx2x_close(bp->dev);
10289                 rtnl_unlock();
10290                 return;
10291         }
10292
10293         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10294                 DP(BNX2X_MSG_SP,
10295                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10296                 bnx2x_vfpf_set_mcast(bp->dev);
10297         }
10298         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10299                                &bp->sp_rtnl_state)){
10300                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10301                         bnx2x_tx_disable(bp);
10302                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10303                 }
10304         }
10305
10306         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10307                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10308                 bnx2x_set_rx_mode_inner(bp);
10309         }
10310
10311         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10312                                &bp->sp_rtnl_state))
10313                 bnx2x_pf_set_vfs_vlan(bp);
10314
10315         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10316                 bnx2x_dcbx_stop_hw_tx(bp);
10317                 bnx2x_dcbx_resume_hw_tx(bp);
10318         }
10319
10320         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10321                                &bp->sp_rtnl_state))
10322                 bnx2x_update_mng_version(bp);
10323
10324         if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
10325                                &bp->sp_rtnl_state)) {
10326                 if (bnx2x_udp_port_update(bp)) {
10327                         /* On error, forget configuration */
10328                         memset(bp->udp_tunnel_ports, 0,
10329                                sizeof(struct bnx2x_udp_tunnel) *
10330                                BNX2X_UDP_PORT_MAX);
10331                 } else {
10332                         /* Since we don't store additional port information,
10333                          * if no ports are configured for any feature ask for
10334                          * information about currently configured ports.
10335                          */
10336                         if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10337                             !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10338                                 udp_tunnel_get_rx_info(bp->dev);
10339                 }
10340         }
10341
10342         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10343          * can be called from other contexts as well)
10344          */
10345         rtnl_unlock();
10346
10347         /* enable SR-IOV if applicable */
10348         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10349                                                &bp->sp_rtnl_state)) {
10350                 bnx2x_disable_sriov(bp);
10351                 bnx2x_enable_sriov(bp);
10352         }
10353 }
10354
10355 static void bnx2x_period_task(struct work_struct *work)
10356 {
10357         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10358
10359         if (!netif_running(bp->dev))
10360                 goto period_task_exit;
10361
10362         if (CHIP_REV_IS_SLOW(bp)) {
10363                 BNX2X_ERR("period task called on emulation, ignoring\n");
10364                 goto period_task_exit;
10365         }
10366
10367         bnx2x_acquire_phy_lock(bp);
10368         /*
10369          * The barrier is needed to ensure the ordering between the writing to
10370          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10371          * the reading here.
10372          */
10373         smp_mb();
10374         if (bp->port.pmf) {
10375                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10376
10377                 /* Re-queue task in 1 sec */
10378                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10379         }
10380
10381         bnx2x_release_phy_lock(bp);
10382 period_task_exit:
10383         return;
10384 }
10385
10386 /*
10387  * Init service functions
10388  */
10389
10390 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10391 {
10392         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10393         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10394         return base + (BP_ABS_FUNC(bp)) * stride;
10395 }
10396
10397 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10398                                          u8 port, u32 reset_reg,
10399                                          struct bnx2x_mac_vals *vals)
10400 {
10401         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10402         u32 base_addr;
10403
10404         if (!(mask & reset_reg))
10405                 return false;
10406
10407         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10408         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10409         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10410         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10411         REG_WR(bp, vals->umac_addr[port], 0);
10412
10413         return true;
10414 }
10415
10416 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10417                                         struct bnx2x_mac_vals *vals)
10418 {
10419         u32 val, base_addr, offset, mask, reset_reg;
10420         bool mac_stopped = false;
10421         u8 port = BP_PORT(bp);
10422
10423         /* reset addresses as they also mark which values were changed */
10424         memset(vals, 0, sizeof(*vals));
10425
10426         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10427
10428         if (!CHIP_IS_E3(bp)) {
10429                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10430                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10431                 if ((mask & reset_reg) && val) {
10432                         u32 wb_data[2];
10433                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10434                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10435                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10436                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10437                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10438
10439                         /*
10440                          * use rd/wr since we cannot use dmae. This is safe
10441                          * since MCP won't access the bus due to the request
10442                          * to unload, and no function on the path can be
10443                          * loaded at this time.
10444                          */
10445                         wb_data[0] = REG_RD(bp, base_addr + offset);
10446                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10447                         vals->bmac_addr = base_addr + offset;
10448                         vals->bmac_val[0] = wb_data[0];
10449                         vals->bmac_val[1] = wb_data[1];
10450                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10451                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10452                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10453                 }
10454                 BNX2X_DEV_INFO("Disable emac Rx\n");
10455                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10456                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10457                 REG_WR(bp, vals->emac_addr, 0);
10458                 mac_stopped = true;
10459         } else {
10460                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10461                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10462                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10463                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10464                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10465                                val & ~(1 << 1));
10466                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10467                                val | (1 << 1));
10468                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10469                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10470                         REG_WR(bp, vals->xmac_addr, 0);
10471                         mac_stopped = true;
10472                 }
10473
10474                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10475                                                             reset_reg, vals);
10476                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10477                                                             reset_reg, vals);
10478         }
10479
10480         if (mac_stopped)
10481                 msleep(20);
10482 }
10483
10484 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10485 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10486                                         0x1848 + ((f) << 4))
10487 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10488 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10489 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10490
10491 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10492 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10493 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10494
10495 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10496 {
10497         /* UNDI marks its presence in DORQ -
10498          * it initializes CID offset for normal bell to 0x7
10499          */
10500         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10501             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10502                 return false;
10503
10504         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10505                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10506                 return true;
10507         }
10508
10509         return false;
10510 }
10511
10512 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10513 {
10514         u16 rcq, bd;
10515         u32 addr, tmp_reg;
10516
10517         if (BP_FUNC(bp) < 2)
10518                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10519         else
10520                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10521
10522         tmp_reg = REG_RD(bp, addr);
10523         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10524         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10525
10526         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10527         REG_WR(bp, addr, tmp_reg);
10528
10529         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10530                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10531 }
10532
10533 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10534 {
10535         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10536                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10537         if (!rc) {
10538                 BNX2X_ERR("MCP response failure, aborting\n");
10539                 return -EBUSY;
10540         }
10541
10542         return 0;
10543 }
10544
10545 static struct bnx2x_prev_path_list *
10546                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10547 {
10548         struct bnx2x_prev_path_list *tmp_list;
10549
10550         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10551                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10552                     bp->pdev->bus->number == tmp_list->bus &&
10553                     BP_PATH(bp) == tmp_list->path)
10554                         return tmp_list;
10555
10556         return NULL;
10557 }
10558
10559 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10560 {
10561         struct bnx2x_prev_path_list *tmp_list;
10562         int rc;
10563
10564         rc = down_interruptible(&bnx2x_prev_sem);
10565         if (rc) {
10566                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10567                 return rc;
10568         }
10569
10570         tmp_list = bnx2x_prev_path_get_entry(bp);
10571         if (tmp_list) {
10572                 tmp_list->aer = 1;
10573                 rc = 0;
10574         } else {
10575                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10576                           BP_PATH(bp));
10577         }
10578
10579         up(&bnx2x_prev_sem);
10580
10581         return rc;
10582 }
10583
10584 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10585 {
10586         struct bnx2x_prev_path_list *tmp_list;
10587         bool rc = false;
10588
10589         if (down_trylock(&bnx2x_prev_sem))
10590                 return false;
10591
10592         tmp_list = bnx2x_prev_path_get_entry(bp);
10593         if (tmp_list) {
10594                 if (tmp_list->aer) {
10595                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10596                            BP_PATH(bp));
10597                 } else {
10598                         rc = true;
10599                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10600                                        BP_PATH(bp));
10601                 }
10602         }
10603
10604         up(&bnx2x_prev_sem);
10605
10606         return rc;
10607 }
10608
10609 bool bnx2x_port_after_undi(struct bnx2x *bp)
10610 {
10611         struct bnx2x_prev_path_list *entry;
10612         bool val;
10613
10614         down(&bnx2x_prev_sem);
10615
10616         entry = bnx2x_prev_path_get_entry(bp);
10617         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10618
10619         up(&bnx2x_prev_sem);
10620
10621         return val;
10622 }
10623
10624 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10625 {
10626         struct bnx2x_prev_path_list *tmp_list;
10627         int rc;
10628
10629         rc = down_interruptible(&bnx2x_prev_sem);
10630         if (rc) {
10631                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10632                 return rc;
10633         }
10634
10635         /* Check whether the entry for this path already exists */
10636         tmp_list = bnx2x_prev_path_get_entry(bp);
10637         if (tmp_list) {
10638                 if (!tmp_list->aer) {
10639                         BNX2X_ERR("Re-Marking the path.\n");
10640                 } else {
10641                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10642                            BP_PATH(bp));
10643                         tmp_list->aer = 0;
10644                 }
10645                 up(&bnx2x_prev_sem);
10646                 return 0;
10647         }
10648         up(&bnx2x_prev_sem);
10649
10650         /* Create an entry for this path and add it */
10651         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10652         if (!tmp_list) {
10653                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10654                 return -ENOMEM;
10655         }
10656
10657         tmp_list->bus = bp->pdev->bus->number;
10658         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10659         tmp_list->path = BP_PATH(bp);
10660         tmp_list->aer = 0;
10661         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10662
10663         rc = down_interruptible(&bnx2x_prev_sem);
10664         if (rc) {
10665                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10666                 kfree(tmp_list);
10667         } else {
10668                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10669                    BP_PATH(bp));
10670                 list_add(&tmp_list->list, &bnx2x_prev_list);
10671                 up(&bnx2x_prev_sem);
10672         }
10673
10674         return rc;
10675 }
10676
10677 static int bnx2x_do_flr(struct bnx2x *bp)
10678 {
10679         struct pci_dev *dev = bp->pdev;
10680
10681         if (CHIP_IS_E1x(bp)) {
10682                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10683                 return -EINVAL;
10684         }
10685
10686         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10687         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10688                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10689                           bp->common.bc_ver);
10690                 return -EINVAL;
10691         }
10692
10693         if (!pci_wait_for_pending_transaction(dev))
10694                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10695
10696         BNX2X_DEV_INFO("Initiating FLR\n");
10697         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10698
10699         return 0;
10700 }
10701
10702 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10703 {
10704         int rc;
10705
10706         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10707
10708         /* Test if previous unload process was already finished for this path */
10709         if (bnx2x_prev_is_path_marked(bp))
10710                 return bnx2x_prev_mcp_done(bp);
10711
10712         BNX2X_DEV_INFO("Path is unmarked\n");
10713
10714         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10715         if (bnx2x_prev_is_after_undi(bp))
10716                 goto out;
10717
10718         /* If function has FLR capabilities, and existing FW version matches
10719          * the one required, then FLR will be sufficient to clean any residue
10720          * left by previous driver
10721          */
10722         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10723
10724         if (!rc) {
10725                 /* fw version is good */
10726                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10727                 rc = bnx2x_do_flr(bp);
10728         }
10729
10730         if (!rc) {
10731                 /* FLR was performed */
10732                 BNX2X_DEV_INFO("FLR successful\n");
10733                 return 0;
10734         }
10735
10736         BNX2X_DEV_INFO("Could not FLR\n");
10737
10738 out:
10739         /* Close the MCP request, return failure*/
10740         rc = bnx2x_prev_mcp_done(bp);
10741         if (!rc)
10742                 rc = BNX2X_PREV_WAIT_NEEDED;
10743
10744         return rc;
10745 }
10746
10747 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10748 {
10749         u32 reset_reg, tmp_reg = 0, rc;
10750         bool prev_undi = false;
10751         struct bnx2x_mac_vals mac_vals;
10752
10753         /* It is possible a previous function received 'common' answer,
10754          * but hasn't loaded yet, therefore creating a scenario of
10755          * multiple functions receiving 'common' on the same path.
10756          */
10757         BNX2X_DEV_INFO("Common unload Flow\n");
10758
10759         memset(&mac_vals, 0, sizeof(mac_vals));
10760
10761         if (bnx2x_prev_is_path_marked(bp))
10762                 return bnx2x_prev_mcp_done(bp);
10763
10764         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10765
10766         /* Reset should be performed after BRB is emptied */
10767         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10768                 u32 timer_count = 1000;
10769
10770                 /* Close the MAC Rx to prevent BRB from filling up */
10771                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10772
10773                 /* close LLH filters for both ports towards the BRB */
10774                 bnx2x_set_rx_filter(&bp->link_params, 0);
10775                 bp->link_params.port ^= 1;
10776                 bnx2x_set_rx_filter(&bp->link_params, 0);
10777                 bp->link_params.port ^= 1;
10778
10779                 /* Check if the UNDI driver was previously loaded */
10780                 if (bnx2x_prev_is_after_undi(bp)) {
10781                         prev_undi = true;
10782                         /* clear the UNDI indication */
10783                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10784                         /* clear possible idle check errors */
10785                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10786                 }
10787                 if (!CHIP_IS_E1x(bp))
10788                         /* block FW from writing to host */
10789                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10790
10791                 /* wait until BRB is empty */
10792                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10793                 while (timer_count) {
10794                         u32 prev_brb = tmp_reg;
10795
10796                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10797                         if (!tmp_reg)
10798                                 break;
10799
10800                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10801
10802                         /* reset timer as long as BRB actually gets emptied */
10803                         if (prev_brb > tmp_reg)
10804                                 timer_count = 1000;
10805                         else
10806                                 timer_count--;
10807
10808                         /* If UNDI resides in memory, manually increment it */
10809                         if (prev_undi)
10810                                 bnx2x_prev_unload_undi_inc(bp, 1);
10811
10812                         udelay(10);
10813                 }
10814
10815                 if (!timer_count)
10816                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10817         }
10818
10819         /* No packets are in the pipeline, path is ready for reset */
10820         bnx2x_reset_common(bp);
10821
10822         if (mac_vals.xmac_addr)
10823                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10824         if (mac_vals.umac_addr[0])
10825                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10826         if (mac_vals.umac_addr[1])
10827                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10828         if (mac_vals.emac_addr)
10829                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10830         if (mac_vals.bmac_addr) {
10831                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10832                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10833         }
10834
10835         rc = bnx2x_prev_mark_path(bp, prev_undi);
10836         if (rc) {
10837                 bnx2x_prev_mcp_done(bp);
10838                 return rc;
10839         }
10840
10841         return bnx2x_prev_mcp_done(bp);
10842 }
10843
10844 static int bnx2x_prev_unload(struct bnx2x *bp)
10845 {
10846         int time_counter = 10;
10847         u32 rc, fw, hw_lock_reg, hw_lock_val;
10848         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10849
10850         /* clear hw from errors which may have resulted from an interrupted
10851          * dmae transaction.
10852          */
10853         bnx2x_clean_pglue_errors(bp);
10854
10855         /* Release previously held locks */
10856         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10857                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10858                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10859
10860         hw_lock_val = REG_RD(bp, hw_lock_reg);
10861         if (hw_lock_val) {
10862                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10863                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10864                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10865                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10866                 }
10867
10868                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10869                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10870         } else
10871                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10872
10873         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10874                 BNX2X_DEV_INFO("Release previously held alr\n");
10875                 bnx2x_release_alr(bp);
10876         }
10877
10878         do {
10879                 int aer = 0;
10880                 /* Lock MCP using an unload request */
10881                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10882                 if (!fw) {
10883                         BNX2X_ERR("MCP response failure, aborting\n");
10884                         rc = -EBUSY;
10885                         break;
10886                 }
10887
10888                 rc = down_interruptible(&bnx2x_prev_sem);
10889                 if (rc) {
10890                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10891                                   rc);
10892                 } else {
10893                         /* If Path is marked by EEH, ignore unload status */
10894                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10895                                  bnx2x_prev_path_get_entry(bp)->aer);
10896                         up(&bnx2x_prev_sem);
10897                 }
10898
10899                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10900                         rc = bnx2x_prev_unload_common(bp);
10901                         break;
10902                 }
10903
10904                 /* non-common reply from MCP might require looping */
10905                 rc = bnx2x_prev_unload_uncommon(bp);
10906                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10907                         break;
10908
10909                 msleep(20);
10910         } while (--time_counter);
10911
10912         if (!time_counter || rc) {
10913                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10914                 rc = -EPROBE_DEFER;
10915         }
10916
10917         /* Mark function if its port was used to boot from SAN */
10918         if (bnx2x_port_after_undi(bp))
10919                 bp->link_params.feature_config_flags |=
10920                         FEATURE_CONFIG_BOOT_FROM_SAN;
10921
10922         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10923
10924         return rc;
10925 }
10926
10927 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10928 {
10929         u32 val, val2, val3, val4, id, boot_mode;
10930         u16 pmc;
10931
10932         /* Get the chip revision id and number. */
10933         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10934         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10935         id = ((val & 0xffff) << 16);
10936         val = REG_RD(bp, MISC_REG_CHIP_REV);
10937         id |= ((val & 0xf) << 12);
10938
10939         /* Metal is read from PCI regs, but we can't access >=0x400 from
10940          * the configuration space (so we need to reg_rd)
10941          */
10942         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10943         id |= (((val >> 24) & 0xf) << 4);
10944         val = REG_RD(bp, MISC_REG_BOND_ID);
10945         id |= (val & 0xf);
10946         bp->common.chip_id = id;
10947
10948         /* force 57811 according to MISC register */
10949         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10950                 if (CHIP_IS_57810(bp))
10951                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10952                                 (bp->common.chip_id & 0x0000FFFF);
10953                 else if (CHIP_IS_57810_MF(bp))
10954                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10955                                 (bp->common.chip_id & 0x0000FFFF);
10956                 bp->common.chip_id |= 0x1;
10957         }
10958
10959         /* Set doorbell size */
10960         bp->db_size = (1 << BNX2X_DB_SHIFT);
10961
10962         if (!CHIP_IS_E1x(bp)) {
10963                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10964                 if ((val & 1) == 0)
10965                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10966                 else
10967                         val = (val >> 1) & 1;
10968                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10969                                                        "2_PORT_MODE");
10970                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10971                                                  CHIP_2_PORT_MODE;
10972
10973                 if (CHIP_MODE_IS_4_PORT(bp))
10974                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10975                 else
10976                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10977         } else {
10978                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10979                 bp->pfid = bp->pf_num;                  /* 0..7 */
10980         }
10981
10982         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10983
10984         bp->link_params.chip_id = bp->common.chip_id;
10985         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10986
10987         val = (REG_RD(bp, 0x2874) & 0x55);
10988         if ((bp->common.chip_id & 0x1) ||
10989             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10990                 bp->flags |= ONE_PORT_FLAG;
10991                 BNX2X_DEV_INFO("single port device\n");
10992         }
10993
10994         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10995         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10996                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10997         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10998                        bp->common.flash_size, bp->common.flash_size);
10999
11000         bnx2x_init_shmem(bp);
11001
11002         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11003                                         MISC_REG_GENERIC_CR_1 :
11004                                         MISC_REG_GENERIC_CR_0));
11005
11006         bp->link_params.shmem_base = bp->common.shmem_base;
11007         bp->link_params.shmem2_base = bp->common.shmem2_base;
11008         if (SHMEM2_RD(bp, size) >
11009             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11010                 bp->link_params.lfa_base =
11011                 REG_RD(bp, bp->common.shmem2_base +
11012                        (u32)offsetof(struct shmem2_region,
11013                                      lfa_host_addr[BP_PORT(bp)]));
11014         else
11015                 bp->link_params.lfa_base = 0;
11016         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
11017                        bp->common.shmem_base, bp->common.shmem2_base);
11018
11019         if (!bp->common.shmem_base) {
11020                 BNX2X_DEV_INFO("MCP not active\n");
11021                 bp->flags |= NO_MCP_FLAG;
11022                 return;
11023         }
11024
11025         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
11026         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
11027
11028         bp->link_params.hw_led_mode = ((bp->common.hw_config &
11029                                         SHARED_HW_CFG_LED_MODE_MASK) >>
11030                                        SHARED_HW_CFG_LED_MODE_SHIFT);
11031
11032         bp->link_params.feature_config_flags = 0;
11033         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11034         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11035                 bp->link_params.feature_config_flags |=
11036                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11037         else
11038                 bp->link_params.feature_config_flags &=
11039                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11040
11041         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11042         bp->common.bc_ver = val;
11043         BNX2X_DEV_INFO("bc_ver %X\n", val);
11044         if (val < BNX2X_BC_VER) {
11045                 /* for now only warn
11046                  * later we might need to enforce this */
11047                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11048                           BNX2X_BC_VER, val);
11049         }
11050         bp->link_params.feature_config_flags |=
11051                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11052                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11053
11054         bp->link_params.feature_config_flags |=
11055                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11056                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11057         bp->link_params.feature_config_flags |=
11058                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11059                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11060         bp->link_params.feature_config_flags |=
11061                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11062                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11063
11064         bp->link_params.feature_config_flags |=
11065                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11066                 FEATURE_CONFIG_MT_SUPPORT : 0;
11067
11068         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11069                         BC_SUPPORTS_PFC_STATS : 0;
11070
11071         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11072                         BC_SUPPORTS_FCOE_FEATURES : 0;
11073
11074         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11075                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11076
11077         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11078                         BC_SUPPORTS_RMMOD_CMD : 0;
11079
11080         boot_mode = SHMEM_RD(bp,
11081                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11082                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11083         switch (boot_mode) {
11084         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11085                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11086                 break;
11087         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11088                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11089                 break;
11090         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11091                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11092                 break;
11093         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11094                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11095                 break;
11096         }
11097
11098         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11099         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11100
11101         BNX2X_DEV_INFO("%sWoL capable\n",
11102                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
11103
11104         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11105         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11106         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11107         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11108
11109         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11110                  val, val2, val3, val4);
11111 }
11112
11113 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11114 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11115
11116 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11117 {
11118         int pfid = BP_FUNC(bp);
11119         int igu_sb_id;
11120         u32 val;
11121         u8 fid, igu_sb_cnt = 0;
11122
11123         bp->igu_base_sb = 0xff;
11124         if (CHIP_INT_MODE_IS_BC(bp)) {
11125                 int vn = BP_VN(bp);
11126                 igu_sb_cnt = bp->igu_sb_cnt;
11127                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11128                         FP_SB_MAX_E1x;
11129
11130                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
11131                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11132
11133                 return 0;
11134         }
11135
11136         /* IGU in normal mode - read CAM */
11137         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11138              igu_sb_id++) {
11139                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11140                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11141                         continue;
11142                 fid = IGU_FID(val);
11143                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11144                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11145                                 continue;
11146                         if (IGU_VEC(val) == 0)
11147                                 /* default status block */
11148                                 bp->igu_dsb_id = igu_sb_id;
11149                         else {
11150                                 if (bp->igu_base_sb == 0xff)
11151                                         bp->igu_base_sb = igu_sb_id;
11152                                 igu_sb_cnt++;
11153                         }
11154                 }
11155         }
11156
11157 #ifdef CONFIG_PCI_MSI
11158         /* Due to new PF resource allocation by MFW T7.4 and above, it's
11159          * optional that number of CAM entries will not be equal to the value
11160          * advertised in PCI.
11161          * Driver should use the minimal value of both as the actual status
11162          * block count
11163          */
11164         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11165 #endif
11166
11167         if (igu_sb_cnt == 0) {
11168                 BNX2X_ERR("CAM configuration error\n");
11169                 return -EINVAL;
11170         }
11171
11172         return 0;
11173 }
11174
11175 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11176 {
11177         int cfg_size = 0, idx, port = BP_PORT(bp);
11178
11179         /* Aggregation of supported attributes of all external phys */
11180         bp->port.supported[0] = 0;
11181         bp->port.supported[1] = 0;
11182         switch (bp->link_params.num_phys) {
11183         case 1:
11184                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11185                 cfg_size = 1;
11186                 break;
11187         case 2:
11188                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11189                 cfg_size = 1;
11190                 break;
11191         case 3:
11192                 if (bp->link_params.multi_phy_config &
11193                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11194                         bp->port.supported[1] =
11195                                 bp->link_params.phy[EXT_PHY1].supported;
11196                         bp->port.supported[0] =
11197                                 bp->link_params.phy[EXT_PHY2].supported;
11198                 } else {
11199                         bp->port.supported[0] =
11200                                 bp->link_params.phy[EXT_PHY1].supported;
11201                         bp->port.supported[1] =
11202                                 bp->link_params.phy[EXT_PHY2].supported;
11203                 }
11204                 cfg_size = 2;
11205                 break;
11206         }
11207
11208         if (!(bp->port.supported[0] || bp->port.supported[1])) {
11209                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11210                            SHMEM_RD(bp,
11211                            dev_info.port_hw_config[port].external_phy_config),
11212                            SHMEM_RD(bp,
11213                            dev_info.port_hw_config[port].external_phy_config2));
11214                         return;
11215         }
11216
11217         if (CHIP_IS_E3(bp))
11218                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11219         else {
11220                 switch (switch_cfg) {
11221                 case SWITCH_CFG_1G:
11222                         bp->port.phy_addr = REG_RD(
11223                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11224                         break;
11225                 case SWITCH_CFG_10G:
11226                         bp->port.phy_addr = REG_RD(
11227                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11228                         break;
11229                 default:
11230                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11231                                   bp->port.link_config[0]);
11232                         return;
11233                 }
11234         }
11235         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11236         /* mask what we support according to speed_cap_mask per configuration */
11237         for (idx = 0; idx < cfg_size; idx++) {
11238                 if (!(bp->link_params.speed_cap_mask[idx] &
11239                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11240                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11241
11242                 if (!(bp->link_params.speed_cap_mask[idx] &
11243                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11244                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11245
11246                 if (!(bp->link_params.speed_cap_mask[idx] &
11247                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11248                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11249
11250                 if (!(bp->link_params.speed_cap_mask[idx] &
11251                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11252                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11253
11254                 if (!(bp->link_params.speed_cap_mask[idx] &
11255                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11256                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11257                                                      SUPPORTED_1000baseT_Full);
11258
11259                 if (!(bp->link_params.speed_cap_mask[idx] &
11260                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11261                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11262
11263                 if (!(bp->link_params.speed_cap_mask[idx] &
11264                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11265                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11266
11267                 if (!(bp->link_params.speed_cap_mask[idx] &
11268                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11269                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11270         }
11271
11272         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11273                        bp->port.supported[1]);
11274 }
11275
11276 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11277 {
11278         u32 link_config, idx, cfg_size = 0;
11279         bp->port.advertising[0] = 0;
11280         bp->port.advertising[1] = 0;
11281         switch (bp->link_params.num_phys) {
11282         case 1:
11283         case 2:
11284                 cfg_size = 1;
11285                 break;
11286         case 3:
11287                 cfg_size = 2;
11288                 break;
11289         }
11290         for (idx = 0; idx < cfg_size; idx++) {
11291                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11292                 link_config = bp->port.link_config[idx];
11293                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11294                 case PORT_FEATURE_LINK_SPEED_AUTO:
11295                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11296                                 bp->link_params.req_line_speed[idx] =
11297                                         SPEED_AUTO_NEG;
11298                                 bp->port.advertising[idx] |=
11299                                         bp->port.supported[idx];
11300                                 if (bp->link_params.phy[EXT_PHY1].type ==
11301                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11302                                         bp->port.advertising[idx] |=
11303                                         (SUPPORTED_100baseT_Half |
11304                                          SUPPORTED_100baseT_Full);
11305                         } else {
11306                                 /* force 10G, no AN */
11307                                 bp->link_params.req_line_speed[idx] =
11308                                         SPEED_10000;
11309                                 bp->port.advertising[idx] |=
11310                                         (ADVERTISED_10000baseT_Full |
11311                                          ADVERTISED_FIBRE);
11312                                 continue;
11313                         }
11314                         break;
11315
11316                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11317                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11318                                 bp->link_params.req_line_speed[idx] =
11319                                         SPEED_10;
11320                                 bp->port.advertising[idx] |=
11321                                         (ADVERTISED_10baseT_Full |
11322                                          ADVERTISED_TP);
11323                         } else {
11324                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11325                                             link_config,
11326                                     bp->link_params.speed_cap_mask[idx]);
11327                                 return;
11328                         }
11329                         break;
11330
11331                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11332                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11333                                 bp->link_params.req_line_speed[idx] =
11334                                         SPEED_10;
11335                                 bp->link_params.req_duplex[idx] =
11336                                         DUPLEX_HALF;
11337                                 bp->port.advertising[idx] |=
11338                                         (ADVERTISED_10baseT_Half |
11339                                          ADVERTISED_TP);
11340                         } else {
11341                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11342                                             link_config,
11343                                           bp->link_params.speed_cap_mask[idx]);
11344                                 return;
11345                         }
11346                         break;
11347
11348                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11349                         if (bp->port.supported[idx] &
11350                             SUPPORTED_100baseT_Full) {
11351                                 bp->link_params.req_line_speed[idx] =
11352                                         SPEED_100;
11353                                 bp->port.advertising[idx] |=
11354                                         (ADVERTISED_100baseT_Full |
11355                                          ADVERTISED_TP);
11356                         } else {
11357                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11358                                             link_config,
11359                                           bp->link_params.speed_cap_mask[idx]);
11360                                 return;
11361                         }
11362                         break;
11363
11364                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11365                         if (bp->port.supported[idx] &
11366                             SUPPORTED_100baseT_Half) {
11367                                 bp->link_params.req_line_speed[idx] =
11368                                                                 SPEED_100;
11369                                 bp->link_params.req_duplex[idx] =
11370                                                                 DUPLEX_HALF;
11371                                 bp->port.advertising[idx] |=
11372                                         (ADVERTISED_100baseT_Half |
11373                                          ADVERTISED_TP);
11374                         } else {
11375                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11376                                     link_config,
11377                                     bp->link_params.speed_cap_mask[idx]);
11378                                 return;
11379                         }
11380                         break;
11381
11382                 case PORT_FEATURE_LINK_SPEED_1G:
11383                         if (bp->port.supported[idx] &
11384                             SUPPORTED_1000baseT_Full) {
11385                                 bp->link_params.req_line_speed[idx] =
11386                                         SPEED_1000;
11387                                 bp->port.advertising[idx] |=
11388                                         (ADVERTISED_1000baseT_Full |
11389                                          ADVERTISED_TP);
11390                         } else if (bp->port.supported[idx] &
11391                                    SUPPORTED_1000baseKX_Full) {
11392                                 bp->link_params.req_line_speed[idx] =
11393                                         SPEED_1000;
11394                                 bp->port.advertising[idx] |=
11395                                         ADVERTISED_1000baseKX_Full;
11396                         } else {
11397                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11398                                     link_config,
11399                                     bp->link_params.speed_cap_mask[idx]);
11400                                 return;
11401                         }
11402                         break;
11403
11404                 case PORT_FEATURE_LINK_SPEED_2_5G:
11405                         if (bp->port.supported[idx] &
11406                             SUPPORTED_2500baseX_Full) {
11407                                 bp->link_params.req_line_speed[idx] =
11408                                         SPEED_2500;
11409                                 bp->port.advertising[idx] |=
11410                                         (ADVERTISED_2500baseX_Full |
11411                                                 ADVERTISED_TP);
11412                         } else {
11413                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11414                                     link_config,
11415                                     bp->link_params.speed_cap_mask[idx]);
11416                                 return;
11417                         }
11418                         break;
11419
11420                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11421                         if (bp->port.supported[idx] &
11422                             SUPPORTED_10000baseT_Full) {
11423                                 bp->link_params.req_line_speed[idx] =
11424                                         SPEED_10000;
11425                                 bp->port.advertising[idx] |=
11426                                         (ADVERTISED_10000baseT_Full |
11427                                                 ADVERTISED_FIBRE);
11428                         } else if (bp->port.supported[idx] &
11429                                    SUPPORTED_10000baseKR_Full) {
11430                                 bp->link_params.req_line_speed[idx] =
11431                                         SPEED_10000;
11432                                 bp->port.advertising[idx] |=
11433                                         (ADVERTISED_10000baseKR_Full |
11434                                                 ADVERTISED_FIBRE);
11435                         } else {
11436                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11437                                     link_config,
11438                                     bp->link_params.speed_cap_mask[idx]);
11439                                 return;
11440                         }
11441                         break;
11442                 case PORT_FEATURE_LINK_SPEED_20G:
11443                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11444
11445                         break;
11446                 default:
11447                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11448                                   link_config);
11449                                 bp->link_params.req_line_speed[idx] =
11450                                                         SPEED_AUTO_NEG;
11451                                 bp->port.advertising[idx] =
11452                                                 bp->port.supported[idx];
11453                         break;
11454                 }
11455
11456                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11457                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11458                 if (bp->link_params.req_flow_ctrl[idx] ==
11459                     BNX2X_FLOW_CTRL_AUTO) {
11460                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11461                                 bp->link_params.req_flow_ctrl[idx] =
11462                                                         BNX2X_FLOW_CTRL_NONE;
11463                         else
11464                                 bnx2x_set_requested_fc(bp);
11465                 }
11466
11467                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11468                                bp->link_params.req_line_speed[idx],
11469                                bp->link_params.req_duplex[idx],
11470                                bp->link_params.req_flow_ctrl[idx],
11471                                bp->port.advertising[idx]);
11472         }
11473 }
11474
11475 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11476 {
11477         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11478         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11479         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11480         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11481 }
11482
11483 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11484 {
11485         int port = BP_PORT(bp);
11486         u32 config;
11487         u32 ext_phy_type, ext_phy_config, eee_mode;
11488
11489         bp->link_params.bp = bp;
11490         bp->link_params.port = port;
11491
11492         bp->link_params.lane_config =
11493                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11494
11495         bp->link_params.speed_cap_mask[0] =
11496                 SHMEM_RD(bp,
11497                          dev_info.port_hw_config[port].speed_capability_mask) &
11498                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11499         bp->link_params.speed_cap_mask[1] =
11500                 SHMEM_RD(bp,
11501                          dev_info.port_hw_config[port].speed_capability_mask2) &
11502                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11503         bp->port.link_config[0] =
11504                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11505
11506         bp->port.link_config[1] =
11507                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11508
11509         bp->link_params.multi_phy_config =
11510                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11511         /* If the device is capable of WoL, set the default state according
11512          * to the HW
11513          */
11514         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11515         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11516                    (config & PORT_FEATURE_WOL_ENABLED));
11517
11518         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11519             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11520                 bp->flags |= NO_ISCSI_FLAG;
11521         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11522             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11523                 bp->flags |= NO_FCOE_FLAG;
11524
11525         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11526                        bp->link_params.lane_config,
11527                        bp->link_params.speed_cap_mask[0],
11528                        bp->port.link_config[0]);
11529
11530         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11531                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11532         bnx2x_phy_probe(&bp->link_params);
11533         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11534
11535         bnx2x_link_settings_requested(bp);
11536
11537         /*
11538          * If connected directly, work with the internal PHY, otherwise, work
11539          * with the external PHY
11540          */
11541         ext_phy_config =
11542                 SHMEM_RD(bp,
11543                          dev_info.port_hw_config[port].external_phy_config);
11544         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11545         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11546                 bp->mdio.prtad = bp->port.phy_addr;
11547
11548         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11549                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11550                 bp->mdio.prtad =
11551                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11552
11553         /* Configure link feature according to nvram value */
11554         eee_mode = (((SHMEM_RD(bp, dev_info.
11555                       port_feature_config[port].eee_power_mode)) &
11556                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11557                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11558         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11559                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11560                                            EEE_MODE_ENABLE_LPI |
11561                                            EEE_MODE_OUTPUT_TIME;
11562         } else {
11563                 bp->link_params.eee_mode = 0;
11564         }
11565 }
11566
11567 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11568 {
11569         u32 no_flags = NO_ISCSI_FLAG;
11570         int port = BP_PORT(bp);
11571         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11572                                 drv_lic_key[port].max_iscsi_conn);
11573
11574         if (!CNIC_SUPPORT(bp)) {
11575                 bp->flags |= no_flags;
11576                 return;
11577         }
11578
11579         /* Get the number of maximum allowed iSCSI connections */
11580         bp->cnic_eth_dev.max_iscsi_conn =
11581                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11582                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11583
11584         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11585                        bp->cnic_eth_dev.max_iscsi_conn);
11586
11587         /*
11588          * If maximum allowed number of connections is zero -
11589          * disable the feature.
11590          */
11591         if (!bp->cnic_eth_dev.max_iscsi_conn)
11592                 bp->flags |= no_flags;
11593 }
11594
11595 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11596 {
11597         /* Port info */
11598         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11599                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11600         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11601                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11602
11603         /* Node info */
11604         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11605                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11606         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11607                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11608 }
11609
11610 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11611 {
11612         u8 count = 0;
11613
11614         if (IS_MF(bp)) {
11615                 u8 fid;
11616
11617                 /* iterate over absolute function ids for this path: */
11618                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11619                         if (IS_MF_SD(bp)) {
11620                                 u32 cfg = MF_CFG_RD(bp,
11621                                                     func_mf_config[fid].config);
11622
11623                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11624                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11625                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11626                                         count++;
11627                         } else {
11628                                 u32 cfg = MF_CFG_RD(bp,
11629                                                     func_ext_config[fid].
11630                                                                       func_cfg);
11631
11632                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11633                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11634                                         count++;
11635                         }
11636                 }
11637         } else { /* SF */
11638                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11639
11640                 for (port = 0; port < port_cnt; port++) {
11641                         u32 lic = SHMEM_RD(bp,
11642                                            drv_lic_key[port].max_fcoe_conn) ^
11643                                   FW_ENCODE_32BIT_PATTERN;
11644                         if (lic)
11645                                 count++;
11646                 }
11647         }
11648
11649         return count;
11650 }
11651
11652 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11653 {
11654         int port = BP_PORT(bp);
11655         int func = BP_ABS_FUNC(bp);
11656         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11657                                 drv_lic_key[port].max_fcoe_conn);
11658         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11659
11660         if (!CNIC_SUPPORT(bp)) {
11661                 bp->flags |= NO_FCOE_FLAG;
11662                 return;
11663         }
11664
11665         /* Get the number of maximum allowed FCoE connections */
11666         bp->cnic_eth_dev.max_fcoe_conn =
11667                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11668                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11669
11670         /* Calculate the number of maximum allowed FCoE tasks */
11671         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11672
11673         /* check if FCoE resources must be shared between different functions */
11674         if (num_fcoe_func)
11675                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11676
11677         /* Read the WWN: */
11678         if (!IS_MF(bp)) {
11679                 /* Port info */
11680                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11681                         SHMEM_RD(bp,
11682                                  dev_info.port_hw_config[port].
11683                                  fcoe_wwn_port_name_upper);
11684                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11685                         SHMEM_RD(bp,
11686                                  dev_info.port_hw_config[port].
11687                                  fcoe_wwn_port_name_lower);
11688
11689                 /* Node info */
11690                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11691                         SHMEM_RD(bp,
11692                                  dev_info.port_hw_config[port].
11693                                  fcoe_wwn_node_name_upper);
11694                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11695                         SHMEM_RD(bp,
11696                                  dev_info.port_hw_config[port].
11697                                  fcoe_wwn_node_name_lower);
11698         } else if (!IS_MF_SD(bp)) {
11699                 /* Read the WWN info only if the FCoE feature is enabled for
11700                  * this function.
11701                  */
11702                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11703                         bnx2x_get_ext_wwn_info(bp, func);
11704         } else {
11705                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11706                         bnx2x_get_ext_wwn_info(bp, func);
11707         }
11708
11709         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11710
11711         /*
11712          * If maximum allowed number of connections is zero -
11713          * disable the feature.
11714          */
11715         if (!bp->cnic_eth_dev.max_fcoe_conn)
11716                 bp->flags |= NO_FCOE_FLAG;
11717 }
11718
11719 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11720 {
11721         /*
11722          * iSCSI may be dynamically disabled but reading
11723          * info here we will decrease memory usage by driver
11724          * if the feature is disabled for good
11725          */
11726         bnx2x_get_iscsi_info(bp);
11727         bnx2x_get_fcoe_info(bp);
11728 }
11729
11730 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11731 {
11732         u32 val, val2;
11733         int func = BP_ABS_FUNC(bp);
11734         int port = BP_PORT(bp);
11735         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11736         u8 *fip_mac = bp->fip_mac;
11737
11738         if (IS_MF(bp)) {
11739                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11740                  * FCoE MAC then the appropriate feature should be disabled.
11741                  * In non SD mode features configuration comes from struct
11742                  * func_ext_config.
11743                  */
11744                 if (!IS_MF_SD(bp)) {
11745                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11746                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11747                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11748                                                  iscsi_mac_addr_upper);
11749                                 val = MF_CFG_RD(bp, func_ext_config[func].
11750                                                 iscsi_mac_addr_lower);
11751                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11752                                 BNX2X_DEV_INFO
11753                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11754                         } else {
11755                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11756                         }
11757
11758                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11759                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11760                                                  fcoe_mac_addr_upper);
11761                                 val = MF_CFG_RD(bp, func_ext_config[func].
11762                                                 fcoe_mac_addr_lower);
11763                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11764                                 BNX2X_DEV_INFO
11765                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11766                         } else {
11767                                 bp->flags |= NO_FCOE_FLAG;
11768                         }
11769
11770                         bp->mf_ext_config = cfg;
11771
11772                 } else { /* SD MODE */
11773                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11774                                 /* use primary mac as iscsi mac */
11775                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11776
11777                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11778                                 BNX2X_DEV_INFO
11779                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11780                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11781                                 /* use primary mac as fip mac */
11782                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11783                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11784                                 BNX2X_DEV_INFO
11785                                         ("Read FIP MAC: %pM\n", fip_mac);
11786                         }
11787                 }
11788
11789                 /* If this is a storage-only interface, use SAN mac as
11790                  * primary MAC. Notice that for SD this is already the case,
11791                  * as the SAN mac was copied from the primary MAC.
11792                  */
11793                 if (IS_MF_FCOE_AFEX(bp))
11794                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11795         } else {
11796                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11797                                 iscsi_mac_upper);
11798                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11799                                iscsi_mac_lower);
11800                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11801
11802                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11803                                 fcoe_fip_mac_upper);
11804                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11805                                fcoe_fip_mac_lower);
11806                 bnx2x_set_mac_buf(fip_mac, val, val2);
11807         }
11808
11809         /* Disable iSCSI OOO if MAC configuration is invalid. */
11810         if (!is_valid_ether_addr(iscsi_mac)) {
11811                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11812                 eth_zero_addr(iscsi_mac);
11813         }
11814
11815         /* Disable FCoE if MAC configuration is invalid. */
11816         if (!is_valid_ether_addr(fip_mac)) {
11817                 bp->flags |= NO_FCOE_FLAG;
11818                 eth_zero_addr(bp->fip_mac);
11819         }
11820 }
11821
11822 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11823 {
11824         u32 val, val2;
11825         int func = BP_ABS_FUNC(bp);
11826         int port = BP_PORT(bp);
11827
11828         /* Zero primary MAC configuration */
11829         eth_zero_addr(bp->dev->dev_addr);
11830
11831         if (BP_NOMCP(bp)) {
11832                 BNX2X_ERROR("warning: random MAC workaround active\n");
11833                 eth_hw_addr_random(bp->dev);
11834         } else if (IS_MF(bp)) {
11835                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11836                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11837                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11838                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11839                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11840
11841                 if (CNIC_SUPPORT(bp))
11842                         bnx2x_get_cnic_mac_hwinfo(bp);
11843         } else {
11844                 /* in SF read MACs from port configuration */
11845                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11846                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11847                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11848
11849                 if (CNIC_SUPPORT(bp))
11850                         bnx2x_get_cnic_mac_hwinfo(bp);
11851         }
11852
11853         if (!BP_NOMCP(bp)) {
11854                 /* Read physical port identifier from shmem */
11855                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11856                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11857                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11858                 bp->flags |= HAS_PHYS_PORT_ID;
11859         }
11860
11861         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11862
11863         if (!is_valid_ether_addr(bp->dev->dev_addr))
11864                 dev_err(&bp->pdev->dev,
11865                         "bad Ethernet MAC address configuration: %pM\n"
11866                         "change it manually before bringing up the appropriate network interface\n",
11867                         bp->dev->dev_addr);
11868 }
11869
11870 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11871 {
11872         int tmp;
11873         u32 cfg;
11874
11875         if (IS_VF(bp))
11876                 return false;
11877
11878         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11879                 /* Take function: tmp = func */
11880                 tmp = BP_ABS_FUNC(bp);
11881                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11882                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11883         } else {
11884                 /* Take port: tmp = port */
11885                 tmp = BP_PORT(bp);
11886                 cfg = SHMEM_RD(bp,
11887                                dev_info.port_hw_config[tmp].generic_features);
11888                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11889         }
11890         return cfg;
11891 }
11892
11893 static void validate_set_si_mode(struct bnx2x *bp)
11894 {
11895         u8 func = BP_ABS_FUNC(bp);
11896         u32 val;
11897
11898         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11899
11900         /* check for legal mac (upper bytes) */
11901         if (val != 0xffff) {
11902                 bp->mf_mode = MULTI_FUNCTION_SI;
11903                 bp->mf_config[BP_VN(bp)] =
11904                         MF_CFG_RD(bp, func_mf_config[func].config);
11905         } else
11906                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11907 }
11908
11909 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11910 {
11911         int /*abs*/func = BP_ABS_FUNC(bp);
11912         int vn, mfw_vn;
11913         u32 val = 0, val2 = 0;
11914         int rc = 0;
11915
11916         /* Validate that chip access is feasible */
11917         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11918                 dev_err(&bp->pdev->dev,
11919                         "Chip read returns all Fs. Preventing probe from continuing\n");
11920                 return -EINVAL;
11921         }
11922
11923         bnx2x_get_common_hwinfo(bp);
11924
11925         /*
11926          * initialize IGU parameters
11927          */
11928         if (CHIP_IS_E1x(bp)) {
11929                 bp->common.int_block = INT_BLOCK_HC;
11930
11931                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11932                 bp->igu_base_sb = 0;
11933         } else {
11934                 bp->common.int_block = INT_BLOCK_IGU;
11935
11936                 /* do not allow device reset during IGU info processing */
11937                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11938
11939                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11940
11941                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11942                         int tout = 5000;
11943
11944                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11945
11946                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11947                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11948                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11949
11950                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11951                                 tout--;
11952                                 usleep_range(1000, 2000);
11953                         }
11954
11955                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11956                                 dev_err(&bp->pdev->dev,
11957                                         "FORCING Normal Mode failed!!!\n");
11958                                 bnx2x_release_hw_lock(bp,
11959                                                       HW_LOCK_RESOURCE_RESET);
11960                                 return -EPERM;
11961                         }
11962                 }
11963
11964                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11965                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11966                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11967                 } else
11968                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11969
11970                 rc = bnx2x_get_igu_cam_info(bp);
11971                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11972                 if (rc)
11973                         return rc;
11974         }
11975
11976         /*
11977          * set base FW non-default (fast path) status block id, this value is
11978          * used to initialize the fw_sb_id saved on the fp/queue structure to
11979          * determine the id used by the FW.
11980          */
11981         if (CHIP_IS_E1x(bp))
11982                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11983         else /*
11984               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11985               * the same queue are indicated on the same IGU SB). So we prefer
11986               * FW and IGU SBs to be the same value.
11987               */
11988                 bp->base_fw_ndsb = bp->igu_base_sb;
11989
11990         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11991                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11992                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11993
11994         /*
11995          * Initialize MF configuration
11996          */
11997
11998         bp->mf_ov = 0;
11999         bp->mf_mode = 0;
12000         bp->mf_sub_mode = 0;
12001         vn = BP_VN(bp);
12002         mfw_vn = BP_FW_MB_IDX(bp);
12003
12004         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
12005                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12006                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
12007                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12008
12009                 if (SHMEM2_HAS(bp, mf_cfg_addr))
12010                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12011                 else
12012                         bp->common.mf_cfg_base = bp->common.shmem_base +
12013                                 offsetof(struct shmem_region, func_mb) +
12014                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
12015                 /*
12016                  * get mf configuration:
12017                  * 1. Existence of MF configuration
12018                  * 2. MAC address must be legal (check only upper bytes)
12019                  *    for  Switch-Independent mode;
12020                  *    OVLAN must be legal for Switch-Dependent mode
12021                  * 3. SF_MODE configures specific MF mode
12022                  */
12023                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12024                         /* get mf configuration */
12025                         val = SHMEM_RD(bp,
12026                                        dev_info.shared_feature_config.config);
12027                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12028
12029                         switch (val) {
12030                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
12031                                 validate_set_si_mode(bp);
12032                                 break;
12033                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12034                                 if ((!CHIP_IS_E1x(bp)) &&
12035                                     (MF_CFG_RD(bp, func_mf_config[func].
12036                                                mac_upper) != 0xffff) &&
12037                                     (SHMEM2_HAS(bp,
12038                                                 afex_driver_support))) {
12039                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
12040                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12041                                                 func_mf_config[func].config);
12042                                 } else {
12043                                         BNX2X_DEV_INFO("can not configure afex mode\n");
12044                                 }
12045                                 break;
12046                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12047                                 /* get OV configuration */
12048                                 val = MF_CFG_RD(bp,
12049                                         func_mf_config[FUNC_0].e1hov_tag);
12050                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12051
12052                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12053                                         bp->mf_mode = MULTI_FUNCTION_SD;
12054                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12055                                                 func_mf_config[func].config);
12056                                 } else
12057                                         BNX2X_DEV_INFO("illegal OV for SD\n");
12058                                 break;
12059                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12060                                 bp->mf_mode = MULTI_FUNCTION_SD;
12061                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
12062                                 bp->mf_config[vn] =
12063                                         MF_CFG_RD(bp,
12064                                                   func_mf_config[func].config);
12065
12066                                 if (SHMEM2_HAS(bp, mtu_size)) {
12067                                         int mtu_idx = BP_FW_MB_IDX(bp);
12068                                         u16 mtu_size;
12069                                         u32 mtu;
12070
12071                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12072                                         mtu_size = (u16)mtu;
12073                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12074                                            mtu_size, mtu);
12075
12076                                         /* if valid: update device mtu */
12077                                         if (((mtu_size + ETH_HLEN) >=
12078                                              ETH_MIN_PACKET_SIZE) &&
12079                                             (mtu_size <=
12080                                              ETH_MAX_JUMBO_PACKET_SIZE))
12081                                                 bp->dev->mtu = mtu_size;
12082                                 }
12083                                 break;
12084                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12085                                 bp->mf_mode = MULTI_FUNCTION_SD;
12086                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12087                                 bp->mf_config[vn] =
12088                                         MF_CFG_RD(bp,
12089                                                   func_mf_config[func].config);
12090                                 break;
12091                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12092                                 bp->mf_config[vn] = 0;
12093                                 break;
12094                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12095                                 val2 = SHMEM_RD(bp,
12096                                         dev_info.shared_hw_config.config_3);
12097                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12098                                 switch (val2) {
12099                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12100                                         validate_set_si_mode(bp);
12101                                         bp->mf_sub_mode =
12102                                                         SUB_MF_MODE_NPAR1_DOT_5;
12103                                         break;
12104                                 default:
12105                                         /* Unknown configuration */
12106                                         bp->mf_config[vn] = 0;
12107                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12108                                                        val);
12109                                 }
12110                                 break;
12111                         default:
12112                                 /* Unknown configuration: reset mf_config */
12113                                 bp->mf_config[vn] = 0;
12114                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12115                         }
12116                 }
12117
12118                 BNX2X_DEV_INFO("%s function mode\n",
12119                                IS_MF(bp) ? "multi" : "single");
12120
12121                 switch (bp->mf_mode) {
12122                 case MULTI_FUNCTION_SD:
12123                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12124                               FUNC_MF_CFG_E1HOV_TAG_MASK;
12125                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12126                                 bp->mf_ov = val;
12127                                 bp->path_has_ovlan = true;
12128
12129                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12130                                                func, bp->mf_ov, bp->mf_ov);
12131                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12132                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12133                                 dev_err(&bp->pdev->dev,
12134                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12135                                         func);
12136                                 bp->path_has_ovlan = true;
12137                         } else {
12138                                 dev_err(&bp->pdev->dev,
12139                                         "No valid MF OV for func %d, aborting\n",
12140                                         func);
12141                                 return -EPERM;
12142                         }
12143                         break;
12144                 case MULTI_FUNCTION_AFEX:
12145                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12146                         break;
12147                 case MULTI_FUNCTION_SI:
12148                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12149                                        func);
12150                         break;
12151                 default:
12152                         if (vn) {
12153                                 dev_err(&bp->pdev->dev,
12154                                         "VN %d is in a single function mode, aborting\n",
12155                                         vn);
12156                                 return -EPERM;
12157                         }
12158                         break;
12159                 }
12160
12161                 /* check if other port on the path needs ovlan:
12162                  * Since MF configuration is shared between ports
12163                  * Possible mixed modes are only
12164                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12165                  */
12166                 if (CHIP_MODE_IS_4_PORT(bp) &&
12167                     !bp->path_has_ovlan &&
12168                     !IS_MF(bp) &&
12169                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12170                         u8 other_port = !BP_PORT(bp);
12171                         u8 other_func = BP_PATH(bp) + 2*other_port;
12172                         val = MF_CFG_RD(bp,
12173                                         func_mf_config[other_func].e1hov_tag);
12174                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12175                                 bp->path_has_ovlan = true;
12176                 }
12177         }
12178
12179         /* adjust igu_sb_cnt to MF for E1H */
12180         if (CHIP_IS_E1H(bp) && IS_MF(bp))
12181                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12182
12183         /* port info */
12184         bnx2x_get_port_hwinfo(bp);
12185
12186         /* Get MAC addresses */
12187         bnx2x_get_mac_hwinfo(bp);
12188
12189         bnx2x_get_cnic_info(bp);
12190
12191         return rc;
12192 }
12193
12194 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12195 {
12196         int cnt, i, block_end, rodi;
12197         char vpd_start[BNX2X_VPD_LEN+1];
12198         char str_id_reg[VENDOR_ID_LEN+1];
12199         char str_id_cap[VENDOR_ID_LEN+1];
12200         char *vpd_data;
12201         char *vpd_extended_data = NULL;
12202         u8 len;
12203
12204         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12205         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12206
12207         if (cnt < BNX2X_VPD_LEN)
12208                 goto out_not_found;
12209
12210         /* VPD RO tag should be first tag after identifier string, hence
12211          * we should be able to find it in first BNX2X_VPD_LEN chars
12212          */
12213         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12214                              PCI_VPD_LRDT_RO_DATA);
12215         if (i < 0)
12216                 goto out_not_found;
12217
12218         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12219                     pci_vpd_lrdt_size(&vpd_start[i]);
12220
12221         i += PCI_VPD_LRDT_TAG_SIZE;
12222
12223         if (block_end > BNX2X_VPD_LEN) {
12224                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12225                 if (vpd_extended_data  == NULL)
12226                         goto out_not_found;
12227
12228                 /* read rest of vpd image into vpd_extended_data */
12229                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12230                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12231                                    block_end - BNX2X_VPD_LEN,
12232                                    vpd_extended_data + BNX2X_VPD_LEN);
12233                 if (cnt < (block_end - BNX2X_VPD_LEN))
12234                         goto out_not_found;
12235                 vpd_data = vpd_extended_data;
12236         } else
12237                 vpd_data = vpd_start;
12238
12239         /* now vpd_data holds full vpd content in both cases */
12240
12241         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12242                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12243         if (rodi < 0)
12244                 goto out_not_found;
12245
12246         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12247
12248         if (len != VENDOR_ID_LEN)
12249                 goto out_not_found;
12250
12251         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12252
12253         /* vendor specific info */
12254         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12255         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12256         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12257             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12258
12259                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12260                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12261                 if (rodi >= 0) {
12262                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12263
12264                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12265
12266                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12267                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12268                                 bp->fw_ver[len] = ' ';
12269                         }
12270                 }
12271                 kfree(vpd_extended_data);
12272                 return;
12273         }
12274 out_not_found:
12275         kfree(vpd_extended_data);
12276         return;
12277 }
12278
12279 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12280 {
12281         u32 flags = 0;
12282
12283         if (CHIP_REV_IS_FPGA(bp))
12284                 SET_FLAGS(flags, MODE_FPGA);
12285         else if (CHIP_REV_IS_EMUL(bp))
12286                 SET_FLAGS(flags, MODE_EMUL);
12287         else
12288                 SET_FLAGS(flags, MODE_ASIC);
12289
12290         if (CHIP_MODE_IS_4_PORT(bp))
12291                 SET_FLAGS(flags, MODE_PORT4);
12292         else
12293                 SET_FLAGS(flags, MODE_PORT2);
12294
12295         if (CHIP_IS_E2(bp))
12296                 SET_FLAGS(flags, MODE_E2);
12297         else if (CHIP_IS_E3(bp)) {
12298                 SET_FLAGS(flags, MODE_E3);
12299                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12300                         SET_FLAGS(flags, MODE_E3_A0);
12301                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12302                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12303         }
12304
12305         if (IS_MF(bp)) {
12306                 SET_FLAGS(flags, MODE_MF);
12307                 switch (bp->mf_mode) {
12308                 case MULTI_FUNCTION_SD:
12309                         SET_FLAGS(flags, MODE_MF_SD);
12310                         break;
12311                 case MULTI_FUNCTION_SI:
12312                         SET_FLAGS(flags, MODE_MF_SI);
12313                         break;
12314                 case MULTI_FUNCTION_AFEX:
12315                         SET_FLAGS(flags, MODE_MF_AFEX);
12316                         break;
12317                 }
12318         } else
12319                 SET_FLAGS(flags, MODE_SF);
12320
12321 #if defined(__LITTLE_ENDIAN)
12322         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12323 #else /*(__BIG_ENDIAN)*/
12324         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12325 #endif
12326         INIT_MODE_FLAGS(bp) = flags;
12327 }
12328
12329 static int bnx2x_init_bp(struct bnx2x *bp)
12330 {
12331         int func;
12332         int rc;
12333
12334         mutex_init(&bp->port.phy_mutex);
12335         mutex_init(&bp->fw_mb_mutex);
12336         mutex_init(&bp->drv_info_mutex);
12337         sema_init(&bp->stats_lock, 1);
12338         bp->drv_info_mng_owner = false;
12339         INIT_LIST_HEAD(&bp->vlan_reg);
12340
12341         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12342         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12343         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12344         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12345         if (IS_PF(bp)) {
12346                 rc = bnx2x_get_hwinfo(bp);
12347                 if (rc)
12348                         return rc;
12349         } else {
12350                 eth_zero_addr(bp->dev->dev_addr);
12351         }
12352
12353         bnx2x_set_modes_bitmap(bp);
12354
12355         rc = bnx2x_alloc_mem_bp(bp);
12356         if (rc)
12357                 return rc;
12358
12359         bnx2x_read_fwinfo(bp);
12360
12361         func = BP_FUNC(bp);
12362
12363         /* need to reset chip if undi was active */
12364         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12365                 /* init fw_seq */
12366                 bp->fw_seq =
12367                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12368                                                         DRV_MSG_SEQ_NUMBER_MASK;
12369                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12370
12371                 rc = bnx2x_prev_unload(bp);
12372                 if (rc) {
12373                         bnx2x_free_mem_bp(bp);
12374                         return rc;
12375                 }
12376         }
12377
12378         if (CHIP_REV_IS_FPGA(bp))
12379                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12380
12381         if (BP_NOMCP(bp) && (func == 0))
12382                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12383
12384         bp->disable_tpa = disable_tpa;
12385         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12386         /* Reduce memory usage in kdump environment by disabling TPA */
12387         bp->disable_tpa |= is_kdump_kernel();
12388
12389         /* Set TPA flags */
12390         if (bp->disable_tpa) {
12391                 bp->dev->hw_features &= ~NETIF_F_LRO;
12392                 bp->dev->features &= ~NETIF_F_LRO;
12393         }
12394
12395         if (CHIP_IS_E1(bp))
12396                 bp->dropless_fc = 0;
12397         else
12398                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12399
12400         bp->mrrs = mrrs;
12401
12402         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12403         if (IS_VF(bp))
12404                 bp->rx_ring_size = MAX_RX_AVAIL;
12405
12406         /* make sure that the numbers are in the right granularity */
12407         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12408         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12409
12410         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12411
12412         init_timer(&bp->timer);
12413         bp->timer.expires = jiffies + bp->current_interval;
12414         bp->timer.data = (unsigned long) bp;
12415         bp->timer.function = bnx2x_timer;
12416
12417         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12418             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12419             SHMEM2_HAS(bp, dcbx_en) &&
12420             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12421             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12422             SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
12423                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12424                 bnx2x_dcbx_init_params(bp);
12425         } else {
12426                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12427         }
12428
12429         if (CHIP_IS_E1x(bp))
12430                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12431         else
12432                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12433
12434         /* multiple tx priority */
12435         if (IS_VF(bp))
12436                 bp->max_cos = 1;
12437         else if (CHIP_IS_E1x(bp))
12438                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12439         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12440                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12441         else if (CHIP_IS_E3B0(bp))
12442                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12443         else
12444                 BNX2X_ERR("unknown chip %x revision %x\n",
12445                           CHIP_NUM(bp), CHIP_REV(bp));
12446         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12447
12448         /* We need at least one default status block for slow-path events,
12449          * second status block for the L2 queue, and a third status block for
12450          * CNIC if supported.
12451          */
12452         if (IS_VF(bp))
12453                 bp->min_msix_vec_cnt = 1;
12454         else if (CNIC_SUPPORT(bp))
12455                 bp->min_msix_vec_cnt = 3;
12456         else /* PF w/o cnic */
12457                 bp->min_msix_vec_cnt = 2;
12458         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12459
12460         bp->dump_preset_idx = 1;
12461
12462         if (CHIP_IS_E3B0(bp))
12463                 bp->flags |= PTP_SUPPORTED;
12464
12465         return rc;
12466 }
12467
12468 /****************************************************************************
12469 * General service functions
12470 ****************************************************************************/
12471
12472 /*
12473  * net_device service functions
12474  */
12475
12476 /* called with rtnl_lock */
12477 static int bnx2x_open(struct net_device *dev)
12478 {
12479         struct bnx2x *bp = netdev_priv(dev);
12480         int rc;
12481
12482         bp->stats_init = true;
12483
12484         netif_carrier_off(dev);
12485
12486         bnx2x_set_power_state(bp, PCI_D0);
12487
12488         /* If parity had happen during the unload, then attentions
12489          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12490          * want the first function loaded on the current engine to
12491          * complete the recovery.
12492          * Parity recovery is only relevant for PF driver.
12493          */
12494         if (IS_PF(bp)) {
12495                 int other_engine = BP_PATH(bp) ? 0 : 1;
12496                 bool other_load_status, load_status;
12497                 bool global = false;
12498
12499                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12500                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12501                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12502                     bnx2x_chk_parity_attn(bp, &global, true)) {
12503                         do {
12504                                 /* If there are attentions and they are in a
12505                                  * global blocks, set the GLOBAL_RESET bit
12506                                  * regardless whether it will be this function
12507                                  * that will complete the recovery or not.
12508                                  */
12509                                 if (global)
12510                                         bnx2x_set_reset_global(bp);
12511
12512                                 /* Only the first function on the current
12513                                  * engine should try to recover in open. In case
12514                                  * of attentions in global blocks only the first
12515                                  * in the chip should try to recover.
12516                                  */
12517                                 if ((!load_status &&
12518                                      (!global || !other_load_status)) &&
12519                                       bnx2x_trylock_leader_lock(bp) &&
12520                                       !bnx2x_leader_reset(bp)) {
12521                                         netdev_info(bp->dev,
12522                                                     "Recovered in open\n");
12523                                         break;
12524                                 }
12525
12526                                 /* recovery has failed... */
12527                                 bnx2x_set_power_state(bp, PCI_D3hot);
12528                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12529
12530                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12531                                           "If you still see this message after a few retries then power cycle is required.\n");
12532
12533                                 return -EAGAIN;
12534                         } while (0);
12535                 }
12536         }
12537
12538         bp->recovery_state = BNX2X_RECOVERY_DONE;
12539         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12540         if (rc)
12541                 return rc;
12542
12543         if (IS_PF(bp))
12544                 udp_tunnel_get_rx_info(dev);
12545
12546         return 0;
12547 }
12548
12549 /* called with rtnl_lock */
12550 static int bnx2x_close(struct net_device *dev)
12551 {
12552         struct bnx2x *bp = netdev_priv(dev);
12553
12554         /* Unload the driver, release IRQs */
12555         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12556
12557         return 0;
12558 }
12559
12560 struct bnx2x_mcast_list_elem_group
12561 {
12562         struct list_head mcast_group_link;
12563         struct bnx2x_mcast_list_elem mcast_elems[];
12564 };
12565
12566 #define MCAST_ELEMS_PER_PG \
12567         ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12568         sizeof(struct bnx2x_mcast_list_elem))
12569
12570 static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list)
12571 {
12572         struct bnx2x_mcast_list_elem_group *current_mcast_group;
12573
12574         while (!list_empty(mcast_group_list)) {
12575                 current_mcast_group = list_first_entry(mcast_group_list,
12576                                       struct bnx2x_mcast_list_elem_group,
12577                                       mcast_group_link);
12578                 list_del(&current_mcast_group->mcast_group_link);
12579                 free_page((unsigned long)current_mcast_group);
12580         }
12581 }
12582
12583 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12584                                       struct bnx2x_mcast_ramrod_params *p,
12585                                       struct list_head *mcast_group_list)
12586 {
12587         struct bnx2x_mcast_list_elem *mc_mac;
12588         struct netdev_hw_addr *ha;
12589         struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL;
12590         int mc_count = netdev_mc_count(bp->dev);
12591         int offset = 0;
12592
12593         INIT_LIST_HEAD(&p->mcast_list);
12594         netdev_for_each_mc_addr(ha, bp->dev) {
12595                 if (!offset) {
12596                         current_mcast_group =
12597                                 (struct bnx2x_mcast_list_elem_group *)
12598                                 __get_free_page(GFP_ATOMIC);
12599                         if (!current_mcast_group) {
12600                                 bnx2x_free_mcast_macs_list(mcast_group_list);
12601                                 BNX2X_ERR("Failed to allocate mc MAC list\n");
12602                                 return -ENOMEM;
12603                         }
12604                         list_add(&current_mcast_group->mcast_group_link,
12605                                  mcast_group_list);
12606                 }
12607                 mc_mac = &current_mcast_group->mcast_elems[offset];
12608                 mc_mac->mac = bnx2x_mc_addr(ha);
12609                 list_add_tail(&mc_mac->link, &p->mcast_list);
12610                 offset++;
12611                 if (offset == MCAST_ELEMS_PER_PG)
12612                         offset = 0;
12613         }
12614         p->mcast_list_len = mc_count;
12615         return 0;
12616 }
12617
12618 /**
12619  * bnx2x_set_uc_list - configure a new unicast MACs list.
12620  *
12621  * @bp: driver handle
12622  *
12623  * We will use zero (0) as a MAC type for these MACs.
12624  */
12625 static int bnx2x_set_uc_list(struct bnx2x *bp)
12626 {
12627         int rc;
12628         struct net_device *dev = bp->dev;
12629         struct netdev_hw_addr *ha;
12630         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12631         unsigned long ramrod_flags = 0;
12632
12633         /* First schedule a cleanup up of old configuration */
12634         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12635         if (rc < 0) {
12636                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12637                 return rc;
12638         }
12639
12640         netdev_for_each_uc_addr(ha, dev) {
12641                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12642                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12643                 if (rc == -EEXIST) {
12644                         DP(BNX2X_MSG_SP,
12645                            "Failed to schedule ADD operations: %d\n", rc);
12646                         /* do not treat adding same MAC as error */
12647                         rc = 0;
12648
12649                 } else if (rc < 0) {
12650
12651                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12652                                   rc);
12653                         return rc;
12654                 }
12655         }
12656
12657         /* Execute the pending commands */
12658         __set_bit(RAMROD_CONT, &ramrod_flags);
12659         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12660                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12661 }
12662
12663 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
12664 {
12665         LIST_HEAD(mcast_group_list);
12666         struct net_device *dev = bp->dev;
12667         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12668         int rc = 0;
12669
12670         rparam.mcast_obj = &bp->mcast_obj;
12671
12672         /* first, clear all configured multicast MACs */
12673         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12674         if (rc < 0) {
12675                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12676                 return rc;
12677         }
12678
12679         /* then, configure a new MACs list */
12680         if (netdev_mc_count(dev)) {
12681                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12682                 if (rc)
12683                         return rc;
12684
12685                 /* Now add the new MACs */
12686                 rc = bnx2x_config_mcast(bp, &rparam,
12687                                         BNX2X_MCAST_CMD_ADD);
12688                 if (rc < 0)
12689                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12690                                   rc);
12691
12692                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12693         }
12694
12695         return rc;
12696 }
12697
12698 static int bnx2x_set_mc_list(struct bnx2x *bp)
12699 {
12700         LIST_HEAD(mcast_group_list);
12701         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12702         struct net_device *dev = bp->dev;
12703         int rc = 0;
12704
12705         /* On older adapters, we need to flush and re-add filters */
12706         if (CHIP_IS_E1x(bp))
12707                 return bnx2x_set_mc_list_e1x(bp);
12708
12709         rparam.mcast_obj = &bp->mcast_obj;
12710
12711         if (netdev_mc_count(dev)) {
12712                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12713                 if (rc)
12714                         return rc;
12715
12716                 /* Override the curently configured set of mc filters */
12717                 rc = bnx2x_config_mcast(bp, &rparam,
12718                                         BNX2X_MCAST_CMD_SET);
12719                 if (rc < 0)
12720                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12721                                   rc);
12722
12723                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12724         } else {
12725                 /* If no mc addresses are required, flush the configuration */
12726                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12727                 if (rc)
12728                         BNX2X_ERR("Failed to clear multicast configuration %d\n",
12729                                   rc);
12730         }
12731
12732         return rc;
12733 }
12734
12735 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12736 static void bnx2x_set_rx_mode(struct net_device *dev)
12737 {
12738         struct bnx2x *bp = netdev_priv(dev);
12739
12740         if (bp->state != BNX2X_STATE_OPEN) {
12741                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12742                 return;
12743         } else {
12744                 /* Schedule an SP task to handle rest of change */
12745                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12746                                        NETIF_MSG_IFUP);
12747         }
12748 }
12749
12750 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12751 {
12752         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12753
12754         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12755
12756         netif_addr_lock_bh(bp->dev);
12757
12758         if (bp->dev->flags & IFF_PROMISC) {
12759                 rx_mode = BNX2X_RX_MODE_PROMISC;
12760         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12761                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12762                     CHIP_IS_E1(bp))) {
12763                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12764         } else {
12765                 if (IS_PF(bp)) {
12766                         /* some multicasts */
12767                         if (bnx2x_set_mc_list(bp) < 0)
12768                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12769
12770                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12771                         netif_addr_unlock_bh(bp->dev);
12772                         if (bnx2x_set_uc_list(bp) < 0)
12773                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12774                         netif_addr_lock_bh(bp->dev);
12775                 } else {
12776                         /* configuring mcast to a vf involves sleeping (when we
12777                          * wait for the pf's response).
12778                          */
12779                         bnx2x_schedule_sp_rtnl(bp,
12780                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12781                 }
12782         }
12783
12784         bp->rx_mode = rx_mode;
12785         /* handle ISCSI SD mode */
12786         if (IS_MF_ISCSI_ONLY(bp))
12787                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12788
12789         /* Schedule the rx_mode command */
12790         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12791                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12792                 netif_addr_unlock_bh(bp->dev);
12793                 return;
12794         }
12795
12796         if (IS_PF(bp)) {
12797                 bnx2x_set_storm_rx_mode(bp);
12798                 netif_addr_unlock_bh(bp->dev);
12799         } else {
12800                 /* VF will need to request the PF to make this change, and so
12801                  * the VF needs to release the bottom-half lock prior to the
12802                  * request (as it will likely require sleep on the VF side)
12803                  */
12804                 netif_addr_unlock_bh(bp->dev);
12805                 bnx2x_vfpf_storm_rx_mode(bp);
12806         }
12807 }
12808
12809 /* called with rtnl_lock */
12810 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12811                            int devad, u16 addr)
12812 {
12813         struct bnx2x *bp = netdev_priv(netdev);
12814         u16 value;
12815         int rc;
12816
12817         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12818            prtad, devad, addr);
12819
12820         /* The HW expects different devad if CL22 is used */
12821         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12822
12823         bnx2x_acquire_phy_lock(bp);
12824         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12825         bnx2x_release_phy_lock(bp);
12826         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12827
12828         if (!rc)
12829                 rc = value;
12830         return rc;
12831 }
12832
12833 /* called with rtnl_lock */
12834 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12835                             u16 addr, u16 value)
12836 {
12837         struct bnx2x *bp = netdev_priv(netdev);
12838         int rc;
12839
12840         DP(NETIF_MSG_LINK,
12841            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12842            prtad, devad, addr, value);
12843
12844         /* The HW expects different devad if CL22 is used */
12845         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12846
12847         bnx2x_acquire_phy_lock(bp);
12848         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12849         bnx2x_release_phy_lock(bp);
12850         return rc;
12851 }
12852
12853 /* called with rtnl_lock */
12854 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12855 {
12856         struct bnx2x *bp = netdev_priv(dev);
12857         struct mii_ioctl_data *mdio = if_mii(ifr);
12858
12859         if (!netif_running(dev))
12860                 return -EAGAIN;
12861
12862         switch (cmd) {
12863         case SIOCSHWTSTAMP:
12864                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12865         default:
12866                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12867                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12868                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12869         }
12870 }
12871
12872 #ifdef CONFIG_NET_POLL_CONTROLLER
12873 static void poll_bnx2x(struct net_device *dev)
12874 {
12875         struct bnx2x *bp = netdev_priv(dev);
12876         int i;
12877
12878         for_each_eth_queue(bp, i) {
12879                 struct bnx2x_fastpath *fp = &bp->fp[i];
12880                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12881         }
12882 }
12883 #endif
12884
12885 static int bnx2x_validate_addr(struct net_device *dev)
12886 {
12887         struct bnx2x *bp = netdev_priv(dev);
12888
12889         /* query the bulletin board for mac address configured by the PF */
12890         if (IS_VF(bp))
12891                 bnx2x_sample_bulletin(bp);
12892
12893         if (!is_valid_ether_addr(dev->dev_addr)) {
12894                 BNX2X_ERR("Non-valid Ethernet address\n");
12895                 return -EADDRNOTAVAIL;
12896         }
12897         return 0;
12898 }
12899
12900 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12901                                   struct netdev_phys_item_id *ppid)
12902 {
12903         struct bnx2x *bp = netdev_priv(netdev);
12904
12905         if (!(bp->flags & HAS_PHYS_PORT_ID))
12906                 return -EOPNOTSUPP;
12907
12908         ppid->id_len = sizeof(bp->phys_port_id);
12909         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12910
12911         return 0;
12912 }
12913
12914 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12915                                               struct net_device *dev,
12916                                               netdev_features_t features)
12917 {
12918         features = vlan_features_check(skb, features);
12919         return vxlan_features_check(skb, features);
12920 }
12921
12922 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12923 {
12924         int rc;
12925
12926         if (IS_PF(bp)) {
12927                 unsigned long ramrod_flags = 0;
12928
12929                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12930                 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12931                                         add, &ramrod_flags);
12932         } else {
12933                 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12934         }
12935
12936         return rc;
12937 }
12938
12939 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
12940 {
12941         struct bnx2x_vlan_entry *vlan;
12942         int rc = 0;
12943
12944         /* Configure all non-configured entries */
12945         list_for_each_entry(vlan, &bp->vlan_reg, link) {
12946                 if (vlan->hw)
12947                         continue;
12948
12949                 if (bp->vlan_cnt >= bp->vlan_credit)
12950                         return -ENOBUFS;
12951
12952                 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12953                 if (rc) {
12954                         BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
12955                         return rc;
12956                 }
12957
12958                 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
12959                 vlan->hw = true;
12960                 bp->vlan_cnt++;
12961         }
12962
12963         return 0;
12964 }
12965
12966 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
12967 {
12968         bool need_accept_any_vlan;
12969
12970         need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
12971
12972         if (bp->accept_any_vlan != need_accept_any_vlan) {
12973                 bp->accept_any_vlan = need_accept_any_vlan;
12974                 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
12975                    bp->accept_any_vlan ? "raised" : "cleared");
12976                 if (set_rx_mode) {
12977                         if (IS_PF(bp))
12978                                 bnx2x_set_rx_mode_inner(bp);
12979                         else
12980                                 bnx2x_vfpf_storm_rx_mode(bp);
12981                 }
12982         }
12983 }
12984
12985 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12986 {
12987         struct bnx2x_vlan_entry *vlan;
12988
12989         /* The hw forgot all entries after reload */
12990         list_for_each_entry(vlan, &bp->vlan_reg, link)
12991                 vlan->hw = false;
12992         bp->vlan_cnt = 0;
12993
12994         /* Don't set rx mode here. Our caller will do it. */
12995         bnx2x_vlan_configure(bp, false);
12996
12997         return 0;
12998 }
12999
13000 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
13001 {
13002         struct bnx2x *bp = netdev_priv(dev);
13003         struct bnx2x_vlan_entry *vlan;
13004
13005         DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
13006
13007         vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
13008         if (!vlan)
13009                 return -ENOMEM;
13010
13011         vlan->vid = vid;
13012         vlan->hw = false;
13013         list_add_tail(&vlan->link, &bp->vlan_reg);
13014
13015         if (netif_running(dev))
13016                 bnx2x_vlan_configure(bp, true);
13017
13018         return 0;
13019 }
13020
13021 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
13022 {
13023         struct bnx2x *bp = netdev_priv(dev);
13024         struct bnx2x_vlan_entry *vlan;
13025         bool found = false;
13026         int rc = 0;
13027
13028         DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
13029
13030         list_for_each_entry(vlan, &bp->vlan_reg, link)
13031                 if (vlan->vid == vid) {
13032                         found = true;
13033                         break;
13034                 }
13035
13036         if (!found) {
13037                 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13038                 return -EINVAL;
13039         }
13040
13041         if (netif_running(dev) && vlan->hw) {
13042                 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
13043                 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13044                 bp->vlan_cnt--;
13045         }
13046
13047         list_del(&vlan->link);
13048         kfree(vlan);
13049
13050         if (netif_running(dev))
13051                 bnx2x_vlan_configure(bp, true);
13052
13053         DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13054
13055         return rc;
13056 }
13057
13058 static const struct net_device_ops bnx2x_netdev_ops = {
13059         .ndo_open               = bnx2x_open,
13060         .ndo_stop               = bnx2x_close,
13061         .ndo_start_xmit         = bnx2x_start_xmit,
13062         .ndo_select_queue       = bnx2x_select_queue,
13063         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
13064         .ndo_set_mac_address    = bnx2x_change_mac_addr,
13065         .ndo_validate_addr      = bnx2x_validate_addr,
13066         .ndo_do_ioctl           = bnx2x_ioctl,
13067         .ndo_change_mtu         = bnx2x_change_mtu,
13068         .ndo_fix_features       = bnx2x_fix_features,
13069         .ndo_set_features       = bnx2x_set_features,
13070         .ndo_tx_timeout         = bnx2x_tx_timeout,
13071         .ndo_vlan_rx_add_vid    = bnx2x_vlan_rx_add_vid,
13072         .ndo_vlan_rx_kill_vid   = bnx2x_vlan_rx_kill_vid,
13073 #ifdef CONFIG_NET_POLL_CONTROLLER
13074         .ndo_poll_controller    = poll_bnx2x,
13075 #endif
13076         .ndo_setup_tc           = __bnx2x_setup_tc,
13077 #ifdef CONFIG_BNX2X_SRIOV
13078         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
13079         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
13080         .ndo_get_vf_config      = bnx2x_get_vf_config,
13081 #endif
13082 #ifdef NETDEV_FCOE_WWNN
13083         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
13084 #endif
13085
13086         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
13087         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
13088         .ndo_features_check     = bnx2x_features_check,
13089         .ndo_udp_tunnel_add     = bnx2x_udp_tunnel_add,
13090         .ndo_udp_tunnel_del     = bnx2x_udp_tunnel_del,
13091 };
13092
13093 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13094 {
13095         struct device *dev = &bp->pdev->dev;
13096
13097         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13098             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13099                 dev_err(dev, "System does not support DMA, aborting\n");
13100                 return -EIO;
13101         }
13102
13103         return 0;
13104 }
13105
13106 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13107 {
13108         if (bp->flags & AER_ENABLED) {
13109                 pci_disable_pcie_error_reporting(bp->pdev);
13110                 bp->flags &= ~AER_ENABLED;
13111         }
13112 }
13113
13114 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13115                           struct net_device *dev, unsigned long board_type)
13116 {
13117         int rc;
13118         u32 pci_cfg_dword;
13119         bool chip_is_e1x = (board_type == BCM57710 ||
13120                             board_type == BCM57711 ||
13121                             board_type == BCM57711E);
13122
13123         SET_NETDEV_DEV(dev, &pdev->dev);
13124
13125         bp->dev = dev;
13126         bp->pdev = pdev;
13127
13128         rc = pci_enable_device(pdev);
13129         if (rc) {
13130                 dev_err(&bp->pdev->dev,
13131                         "Cannot enable PCI device, aborting\n");
13132                 goto err_out;
13133         }
13134
13135         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13136                 dev_err(&bp->pdev->dev,
13137                         "Cannot find PCI device base address, aborting\n");
13138                 rc = -ENODEV;
13139                 goto err_out_disable;
13140         }
13141
13142         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13143                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13144                 rc = -ENODEV;
13145                 goto err_out_disable;
13146         }
13147
13148         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13149         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13150             PCICFG_REVESION_ID_ERROR_VAL) {
13151                 pr_err("PCI device error, probably due to fan failure, aborting\n");
13152                 rc = -ENODEV;
13153                 goto err_out_disable;
13154         }
13155
13156         if (atomic_read(&pdev->enable_cnt) == 1) {
13157                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13158                 if (rc) {
13159                         dev_err(&bp->pdev->dev,
13160                                 "Cannot obtain PCI resources, aborting\n");
13161                         goto err_out_disable;
13162                 }
13163
13164                 pci_set_master(pdev);
13165                 pci_save_state(pdev);
13166         }
13167
13168         if (IS_PF(bp)) {
13169                 if (!pdev->pm_cap) {
13170                         dev_err(&bp->pdev->dev,
13171                                 "Cannot find power management capability, aborting\n");
13172                         rc = -EIO;
13173                         goto err_out_release;
13174                 }
13175         }
13176
13177         if (!pci_is_pcie(pdev)) {
13178                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13179                 rc = -EIO;
13180                 goto err_out_release;
13181         }
13182
13183         rc = bnx2x_set_coherency_mask(bp);
13184         if (rc)
13185                 goto err_out_release;
13186
13187         dev->mem_start = pci_resource_start(pdev, 0);
13188         dev->base_addr = dev->mem_start;
13189         dev->mem_end = pci_resource_end(pdev, 0);
13190
13191         dev->irq = pdev->irq;
13192
13193         bp->regview = pci_ioremap_bar(pdev, 0);
13194         if (!bp->regview) {
13195                 dev_err(&bp->pdev->dev,
13196                         "Cannot map register space, aborting\n");
13197                 rc = -ENOMEM;
13198                 goto err_out_release;
13199         }
13200
13201         /* In E1/E1H use pci device function given by kernel.
13202          * In E2/E3 read physical function from ME register since these chips
13203          * support Physical Device Assignment where kernel BDF maybe arbitrary
13204          * (depending on hypervisor).
13205          */
13206         if (chip_is_e1x) {
13207                 bp->pf_num = PCI_FUNC(pdev->devfn);
13208         } else {
13209                 /* chip is E2/3*/
13210                 pci_read_config_dword(bp->pdev,
13211                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
13212                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13213                                   ME_REG_ABS_PF_NUM_SHIFT);
13214         }
13215         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13216
13217         /* clean indirect addresses */
13218         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13219                                PCICFG_VENDOR_ID_OFFSET);
13220
13221         /* Set PCIe reset type to fundamental for EEH recovery */
13222         pdev->needs_freset = 1;
13223
13224         /* AER (Advanced Error reporting) configuration */
13225         rc = pci_enable_pcie_error_reporting(pdev);
13226         if (!rc)
13227                 bp->flags |= AER_ENABLED;
13228         else
13229                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13230
13231         /*
13232          * Clean the following indirect addresses for all functions since it
13233          * is not used by the driver.
13234          */
13235         if (IS_PF(bp)) {
13236                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13237                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13238                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13239                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13240
13241                 if (chip_is_e1x) {
13242                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13243                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13244                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13245                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13246                 }
13247
13248                 /* Enable internal target-read (in case we are probed after PF
13249                  * FLR). Must be done prior to any BAR read access. Only for
13250                  * 57712 and up
13251                  */
13252                 if (!chip_is_e1x)
13253                         REG_WR(bp,
13254                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13255         }
13256
13257         dev->watchdog_timeo = TX_TIMEOUT;
13258
13259         dev->netdev_ops = &bnx2x_netdev_ops;
13260         bnx2x_set_ethtool_ops(bp, dev);
13261
13262         dev->priv_flags |= IFF_UNICAST_FLT;
13263
13264         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13265                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13266                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13267                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13268         if (!chip_is_e1x) {
13269                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13270                                     NETIF_F_GSO_IPXIP4 |
13271                                     NETIF_F_GSO_UDP_TUNNEL |
13272                                     NETIF_F_GSO_UDP_TUNNEL_CSUM |
13273                                     NETIF_F_GSO_PARTIAL;
13274
13275                 dev->hw_enc_features =
13276                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13277                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13278                         NETIF_F_GSO_IPXIP4 |
13279                         NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13280                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13281                         NETIF_F_GSO_PARTIAL;
13282
13283                 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13284                                             NETIF_F_GSO_UDP_TUNNEL_CSUM;
13285         }
13286
13287         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13288                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13289
13290         /* VF with OLD Hypervisor or old PF do not support filtering */
13291         if (IS_PF(bp)) {
13292                 if (chip_is_e1x)
13293                         bp->accept_any_vlan = true;
13294                 else
13295                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13296 #ifdef CONFIG_BNX2X_SRIOV
13297         } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13298                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13299 #endif
13300         }
13301
13302         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13303         dev->features |= NETIF_F_HIGHDMA;
13304
13305         /* Add Loopback capability to the device */
13306         dev->hw_features |= NETIF_F_LOOPBACK;
13307
13308 #ifdef BCM_DCBNL
13309         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13310 #endif
13311
13312         /* get_port_hwinfo() will set prtad and mmds properly */
13313         bp->mdio.prtad = MDIO_PRTAD_NONE;
13314         bp->mdio.mmds = 0;
13315         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13316         bp->mdio.dev = dev;
13317         bp->mdio.mdio_read = bnx2x_mdio_read;
13318         bp->mdio.mdio_write = bnx2x_mdio_write;
13319
13320         return 0;
13321
13322 err_out_release:
13323         if (atomic_read(&pdev->enable_cnt) == 1)
13324                 pci_release_regions(pdev);
13325
13326 err_out_disable:
13327         pci_disable_device(pdev);
13328
13329 err_out:
13330         return rc;
13331 }
13332
13333 /*(DEBLOBBED)*/
13334
13335 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13336 {
13337         const __be32 *source = (const __be32 *)_source;
13338         u32 *target = (u32 *)_target;
13339         u32 i;
13340
13341         for (i = 0; i < n/4; i++)
13342                 target[i] = be32_to_cpu(source[i]);
13343 }
13344
13345 /*
13346    Ops array is stored in the following format:
13347    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13348  */
13349 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13350 {
13351         const __be32 *source = (const __be32 *)_source;
13352         struct raw_op *target = (struct raw_op *)_target;
13353         u32 i, j, tmp;
13354
13355         for (i = 0, j = 0; i < n/8; i++, j += 2) {
13356                 tmp = be32_to_cpu(source[j]);
13357                 target[i].op = (tmp >> 24) & 0xff;
13358                 target[i].offset = tmp & 0xffffff;
13359                 target[i].raw_data = be32_to_cpu(source[j + 1]);
13360         }
13361 }
13362
13363 /* IRO array is stored in the following format:
13364  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13365  */
13366 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13367 {
13368         const __be32 *source = (const __be32 *)_source;
13369         struct iro *target = (struct iro *)_target;
13370         u32 i, j, tmp;
13371
13372         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13373                 target[i].base = be32_to_cpu(source[j]);
13374                 j++;
13375                 tmp = be32_to_cpu(source[j]);
13376                 target[i].m1 = (tmp >> 16) & 0xffff;
13377                 target[i].m2 = tmp & 0xffff;
13378                 j++;
13379                 tmp = be32_to_cpu(source[j]);
13380                 target[i].m3 = (tmp >> 16) & 0xffff;
13381                 target[i].size = tmp & 0xffff;
13382                 j++;
13383         }
13384 }
13385
13386 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13387 {
13388         const __be16 *source = (const __be16 *)_source;
13389         u16 *target = (u16 *)_target;
13390         u32 i;
13391
13392         for (i = 0; i < n/2; i++)
13393                 target[i] = be16_to_cpu(source[i]);
13394 }
13395
13396 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13397 do {                                                                    \
13398         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13399         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13400         if (!bp->arr)                                                   \
13401                 goto lbl;                                               \
13402         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13403              (u8 *)bp->arr, len);                                       \
13404 } while (0)
13405
13406 static int bnx2x_init_firmware(struct bnx2x *bp)
13407 {
13408         const char *fw_file_name;
13409         struct bnx2x_fw_file_hdr *fw_hdr;
13410         int rc;
13411
13412         if (bp->firmware)
13413                 return 0;
13414
13415         if (CHIP_IS_E1(bp))
13416                 fw_file_name = FW_FILE_NAME_E1;
13417         else if (CHIP_IS_E1H(bp))
13418                 fw_file_name = FW_FILE_NAME_E1H;
13419         else if (!CHIP_IS_E1x(bp))
13420                 fw_file_name = FW_FILE_NAME_E2;
13421         else {
13422                 BNX2X_ERR("Unsupported chip revision\n");
13423                 return -EINVAL;
13424         }
13425         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13426
13427         rc = reject_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13428         if (rc) {
13429                 BNX2X_ERR("Can't load firmware file %s\n",
13430                           fw_file_name);
13431                 goto request_firmware_exit;
13432         }
13433
13434         /*(DEBLOBBED)*/
13435         if (rc) {
13436                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13437                 goto request_firmware_exit;
13438         }
13439
13440         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13441
13442         /* Initialize the pointers to the init arrays */
13443         /* Blob */
13444         rc = -ENOMEM;
13445         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13446
13447         /* Opcodes */
13448         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13449
13450         /* Offsets */
13451         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13452                             be16_to_cpu_n);
13453
13454         /* STORMs firmware */
13455         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13456                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13457         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13458                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13459         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13460                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13461         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13462                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13463         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13464                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13465         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13466                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13467         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13468                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13469         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13470                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13471         /* IRO */
13472         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13473
13474         return 0;
13475
13476 iro_alloc_err:
13477         kfree(bp->init_ops_offsets);
13478 init_offsets_alloc_err:
13479         kfree(bp->init_ops);
13480 init_ops_alloc_err:
13481         kfree(bp->init_data);
13482 request_firmware_exit:
13483         release_firmware(bp->firmware);
13484         bp->firmware = NULL;
13485
13486         return rc;
13487 }
13488
13489 static void bnx2x_release_firmware(struct bnx2x *bp)
13490 {
13491         kfree(bp->init_ops_offsets);
13492         kfree(bp->init_ops);
13493         kfree(bp->init_data);
13494         release_firmware(bp->firmware);
13495         bp->firmware = NULL;
13496 }
13497
13498 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13499         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13500         .init_hw_cmn      = bnx2x_init_hw_common,
13501         .init_hw_port     = bnx2x_init_hw_port,
13502         .init_hw_func     = bnx2x_init_hw_func,
13503
13504         .reset_hw_cmn     = bnx2x_reset_common,
13505         .reset_hw_port    = bnx2x_reset_port,
13506         .reset_hw_func    = bnx2x_reset_func,
13507
13508         .gunzip_init      = bnx2x_gunzip_init,
13509         .gunzip_end       = bnx2x_gunzip_end,
13510
13511         .init_fw          = bnx2x_init_firmware,
13512         .release_fw       = bnx2x_release_firmware,
13513 };
13514
13515 void bnx2x__init_func_obj(struct bnx2x *bp)
13516 {
13517         /* Prepare DMAE related driver resources */
13518         bnx2x_setup_dmae(bp);
13519
13520         bnx2x_init_func_obj(bp, &bp->func_obj,
13521                             bnx2x_sp(bp, func_rdata),
13522                             bnx2x_sp_mapping(bp, func_rdata),
13523                             bnx2x_sp(bp, func_afex_rdata),
13524                             bnx2x_sp_mapping(bp, func_afex_rdata),
13525                             &bnx2x_func_sp_drv);
13526 }
13527
13528 /* must be called after sriov-enable */
13529 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13530 {
13531         int cid_count = BNX2X_L2_MAX_CID(bp);
13532
13533         if (IS_SRIOV(bp))
13534                 cid_count += BNX2X_VF_CIDS;
13535
13536         if (CNIC_SUPPORT(bp))
13537                 cid_count += CNIC_CID_MAX;
13538
13539         return roundup(cid_count, QM_CID_ROUND);
13540 }
13541
13542 /**
13543  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13544  *
13545  * @dev:        pci device
13546  *
13547  */
13548 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13549 {
13550         int index;
13551         u16 control = 0;
13552
13553         /*
13554          * If MSI-X is not supported - return number of SBs needed to support
13555          * one fast path queue: one FP queue + SB for CNIC
13556          */
13557         if (!pdev->msix_cap) {
13558                 dev_info(&pdev->dev, "no msix capability found\n");
13559                 return 1 + cnic_cnt;
13560         }
13561         dev_info(&pdev->dev, "msix capability found\n");
13562
13563         /*
13564          * The value in the PCI configuration space is the index of the last
13565          * entry, namely one less than the actual size of the table, which is
13566          * exactly what we want to return from this function: number of all SBs
13567          * without the default SB.
13568          * For VFs there is no default SB, then we return (index+1).
13569          */
13570         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13571
13572         index = control & PCI_MSIX_FLAGS_QSIZE;
13573
13574         return index;
13575 }
13576
13577 static int set_max_cos_est(int chip_id)
13578 {
13579         switch (chip_id) {
13580         case BCM57710:
13581         case BCM57711:
13582         case BCM57711E:
13583                 return BNX2X_MULTI_TX_COS_E1X;
13584         case BCM57712:
13585         case BCM57712_MF:
13586                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13587         case BCM57800:
13588         case BCM57800_MF:
13589         case BCM57810:
13590         case BCM57810_MF:
13591         case BCM57840_4_10:
13592         case BCM57840_2_20:
13593         case BCM57840_O:
13594         case BCM57840_MFO:
13595         case BCM57840_MF:
13596         case BCM57811:
13597         case BCM57811_MF:
13598                 return BNX2X_MULTI_TX_COS_E3B0;
13599         case BCM57712_VF:
13600         case BCM57800_VF:
13601         case BCM57810_VF:
13602         case BCM57840_VF:
13603         case BCM57811_VF:
13604                 return 1;
13605         default:
13606                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13607                 return -ENODEV;
13608         }
13609 }
13610
13611 static int set_is_vf(int chip_id)
13612 {
13613         switch (chip_id) {
13614         case BCM57712_VF:
13615         case BCM57800_VF:
13616         case BCM57810_VF:
13617         case BCM57840_VF:
13618         case BCM57811_VF:
13619                 return true;
13620         default:
13621                 return false;
13622         }
13623 }
13624
13625 /* nig_tsgen registers relative address */
13626 #define tsgen_ctrl 0x0
13627 #define tsgen_freecount 0x10
13628 #define tsgen_synctime_t0 0x20
13629 #define tsgen_offset_t0 0x28
13630 #define tsgen_drift_t0 0x30
13631 #define tsgen_synctime_t1 0x58
13632 #define tsgen_offset_t1 0x60
13633 #define tsgen_drift_t1 0x68
13634
13635 /* FW workaround for setting drift */
13636 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13637                                           int best_val, int best_period)
13638 {
13639         struct bnx2x_func_state_params func_params = {NULL};
13640         struct bnx2x_func_set_timesync_params *set_timesync_params =
13641                 &func_params.params.set_timesync;
13642
13643         /* Prepare parameters for function state transitions */
13644         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13645         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13646
13647         func_params.f_obj = &bp->func_obj;
13648         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13649
13650         /* Function parameters */
13651         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13652         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13653         set_timesync_params->add_sub_drift_adjust_value =
13654                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13655         set_timesync_params->drift_adjust_value = best_val;
13656         set_timesync_params->drift_adjust_period = best_period;
13657
13658         return bnx2x_func_state_change(bp, &func_params);
13659 }
13660
13661 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13662 {
13663         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13664         int rc;
13665         int drift_dir = 1;
13666         int val, period, period1, period2, dif, dif1, dif2;
13667         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13668
13669         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13670
13671         if (!netif_running(bp->dev)) {
13672                 DP(BNX2X_MSG_PTP,
13673                    "PTP adjfreq called while the interface is down\n");
13674                 return -EFAULT;
13675         }
13676
13677         if (ppb < 0) {
13678                 ppb = -ppb;
13679                 drift_dir = 0;
13680         }
13681
13682         if (ppb == 0) {
13683                 best_val = 1;
13684                 best_period = 0x1FFFFFF;
13685         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13686                 best_val = 31;
13687                 best_period = 1;
13688         } else {
13689                 /* Changed not to allow val = 8, 16, 24 as these values
13690                  * are not supported in workaround.
13691                  */
13692                 for (val = 0; val <= 31; val++) {
13693                         if ((val & 0x7) == 0)
13694                                 continue;
13695                         period1 = val * 1000000 / ppb;
13696                         period2 = period1 + 1;
13697                         if (period1 != 0)
13698                                 dif1 = ppb - (val * 1000000 / period1);
13699                         else
13700                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13701                         if (dif1 < 0)
13702                                 dif1 = -dif1;
13703                         dif2 = ppb - (val * 1000000 / period2);
13704                         if (dif2 < 0)
13705                                 dif2 = -dif2;
13706                         dif = (dif1 < dif2) ? dif1 : dif2;
13707                         period = (dif1 < dif2) ? period1 : period2;
13708                         if (dif < best_dif) {
13709                                 best_dif = dif;
13710                                 best_val = val;
13711                                 best_period = period;
13712                         }
13713                 }
13714         }
13715
13716         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13717                                             best_period);
13718         if (rc) {
13719                 BNX2X_ERR("Failed to set drift\n");
13720                 return -EFAULT;
13721         }
13722
13723         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13724            best_period);
13725
13726         return 0;
13727 }
13728
13729 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13730 {
13731         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13732
13733         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13734
13735         timecounter_adjtime(&bp->timecounter, delta);
13736
13737         return 0;
13738 }
13739
13740 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13741 {
13742         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13743         u64 ns;
13744
13745         ns = timecounter_read(&bp->timecounter);
13746
13747         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13748
13749         *ts = ns_to_timespec64(ns);
13750
13751         return 0;
13752 }
13753
13754 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13755                              const struct timespec64 *ts)
13756 {
13757         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13758         u64 ns;
13759
13760         ns = timespec64_to_ns(ts);
13761
13762         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13763
13764         /* Re-init the timecounter */
13765         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13766
13767         return 0;
13768 }
13769
13770 /* Enable (or disable) ancillary features of the phc subsystem */
13771 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13772                             struct ptp_clock_request *rq, int on)
13773 {
13774         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13775
13776         BNX2X_ERR("PHC ancillary features are not supported\n");
13777         return -ENOTSUPP;
13778 }
13779
13780 static void bnx2x_register_phc(struct bnx2x *bp)
13781 {
13782         /* Fill the ptp_clock_info struct and register PTP clock*/
13783         bp->ptp_clock_info.owner = THIS_MODULE;
13784         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13785         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13786         bp->ptp_clock_info.n_alarm = 0;
13787         bp->ptp_clock_info.n_ext_ts = 0;
13788         bp->ptp_clock_info.n_per_out = 0;
13789         bp->ptp_clock_info.pps = 0;
13790         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13791         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13792         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13793         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13794         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13795
13796         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13797         if (IS_ERR(bp->ptp_clock)) {
13798                 bp->ptp_clock = NULL;
13799                 BNX2X_ERR("PTP clock registeration failed\n");
13800         }
13801 }
13802
13803 static int bnx2x_init_one(struct pci_dev *pdev,
13804                                     const struct pci_device_id *ent)
13805 {
13806         struct net_device *dev = NULL;
13807         struct bnx2x *bp;
13808         enum pcie_link_width pcie_width;
13809         enum pci_bus_speed pcie_speed;
13810         int rc, max_non_def_sbs;
13811         int rx_count, tx_count, rss_count, doorbell_size;
13812         int max_cos_est;
13813         bool is_vf;
13814         int cnic_cnt;
13815
13816         /* Management FW 'remembers' living interfaces. Allow it some time
13817          * to forget previously living interfaces, allowing a proper re-load.
13818          */
13819         if (is_kdump_kernel()) {
13820                 ktime_t now = ktime_get_boottime();
13821                 ktime_t fw_ready_time = ktime_set(5, 0);
13822
13823                 if (ktime_before(now, fw_ready_time))
13824                         msleep(ktime_ms_delta(fw_ready_time, now));
13825         }
13826
13827         /* An estimated maximum supported CoS number according to the chip
13828          * version.
13829          * We will try to roughly estimate the maximum number of CoSes this chip
13830          * may support in order to minimize the memory allocated for Tx
13831          * netdev_queue's. This number will be accurately calculated during the
13832          * initialization of bp->max_cos based on the chip versions AND chip
13833          * revision in the bnx2x_init_bp().
13834          */
13835         max_cos_est = set_max_cos_est(ent->driver_data);
13836         if (max_cos_est < 0)
13837                 return max_cos_est;
13838         is_vf = set_is_vf(ent->driver_data);
13839         cnic_cnt = is_vf ? 0 : 1;
13840
13841         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13842
13843         /* add another SB for VF as it has no default SB */
13844         max_non_def_sbs += is_vf ? 1 : 0;
13845
13846         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13847         rss_count = max_non_def_sbs - cnic_cnt;
13848
13849         if (rss_count < 1)
13850                 return -EINVAL;
13851
13852         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13853         rx_count = rss_count + cnic_cnt;
13854
13855         /* Maximum number of netdev Tx queues:
13856          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13857          */
13858         tx_count = rss_count * max_cos_est + cnic_cnt;
13859
13860         /* dev zeroed in init_etherdev */
13861         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13862         if (!dev)
13863                 return -ENOMEM;
13864
13865         bp = netdev_priv(dev);
13866
13867         bp->flags = 0;
13868         if (is_vf)
13869                 bp->flags |= IS_VF_FLAG;
13870
13871         bp->igu_sb_cnt = max_non_def_sbs;
13872         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13873         bp->msg_enable = debug;
13874         bp->cnic_support = cnic_cnt;
13875         bp->cnic_probe = bnx2x_cnic_probe;
13876
13877         pci_set_drvdata(pdev, dev);
13878
13879         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13880         if (rc < 0) {
13881                 free_netdev(dev);
13882                 return rc;
13883         }
13884
13885         BNX2X_DEV_INFO("This is a %s function\n",
13886                        IS_PF(bp) ? "physical" : "virtual");
13887         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13888         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13889         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13890                        tx_count, rx_count);
13891
13892         rc = bnx2x_init_bp(bp);
13893         if (rc)
13894                 goto init_one_exit;
13895
13896         /* Map doorbells here as we need the real value of bp->max_cos which
13897          * is initialized in bnx2x_init_bp() to determine the number of
13898          * l2 connections.
13899          */
13900         if (IS_VF(bp)) {
13901                 bp->doorbells = bnx2x_vf_doorbells(bp);
13902                 rc = bnx2x_vf_pci_alloc(bp);
13903                 if (rc)
13904                         goto init_one_freemem;
13905         } else {
13906                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13907                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13908                         dev_err(&bp->pdev->dev,
13909                                 "Cannot map doorbells, bar size too small, aborting\n");
13910                         rc = -ENOMEM;
13911                         goto init_one_freemem;
13912                 }
13913                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13914                                                 doorbell_size);
13915         }
13916         if (!bp->doorbells) {
13917                 dev_err(&bp->pdev->dev,
13918                         "Cannot map doorbell space, aborting\n");
13919                 rc = -ENOMEM;
13920                 goto init_one_freemem;
13921         }
13922
13923         if (IS_VF(bp)) {
13924                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13925                 if (rc)
13926                         goto init_one_freemem;
13927         }
13928
13929         /* Enable SRIOV if capability found in configuration space */
13930         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13931         if (rc)
13932                 goto init_one_freemem;
13933
13934         /* calc qm_cid_count */
13935         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13936         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13937
13938         /* disable FCOE L2 queue for E1x*/
13939         if (CHIP_IS_E1x(bp))
13940                 bp->flags |= NO_FCOE_FLAG;
13941
13942         /* Set bp->num_queues for MSI-X mode*/
13943         bnx2x_set_num_queues(bp);
13944
13945         /* Configure interrupt mode: try to enable MSI-X/MSI if
13946          * needed.
13947          */
13948         rc = bnx2x_set_int_mode(bp);
13949         if (rc) {
13950                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13951                 goto init_one_freemem;
13952         }
13953         BNX2X_DEV_INFO("set interrupts successfully\n");
13954
13955         /* register the net device */
13956         rc = register_netdev(dev);
13957         if (rc) {
13958                 dev_err(&pdev->dev, "Cannot register net device\n");
13959                 goto init_one_freemem;
13960         }
13961         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13962
13963         if (!NO_FCOE(bp)) {
13964                 /* Add storage MAC address */
13965                 rtnl_lock();
13966                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13967                 rtnl_unlock();
13968         }
13969         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13970             pcie_speed == PCI_SPEED_UNKNOWN ||
13971             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13972                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13973         else
13974                 BNX2X_DEV_INFO(
13975                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13976                        board_info[ent->driver_data].name,
13977                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13978                        pcie_width,
13979                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13980                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13981                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13982                        "Unknown",
13983                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13984
13985         bnx2x_register_phc(bp);
13986
13987         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13988                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13989
13990         return 0;
13991
13992 init_one_freemem:
13993         bnx2x_free_mem_bp(bp);
13994
13995 init_one_exit:
13996         bnx2x_disable_pcie_error_reporting(bp);
13997
13998         if (bp->regview)
13999                 iounmap(bp->regview);
14000
14001         if (IS_PF(bp) && bp->doorbells)
14002                 iounmap(bp->doorbells);
14003
14004         free_netdev(dev);
14005
14006         if (atomic_read(&pdev->enable_cnt) == 1)
14007                 pci_release_regions(pdev);
14008
14009         pci_disable_device(pdev);
14010
14011         return rc;
14012 }
14013
14014 static void __bnx2x_remove(struct pci_dev *pdev,
14015                            struct net_device *dev,
14016                            struct bnx2x *bp,
14017                            bool remove_netdev)
14018 {
14019         if (bp->ptp_clock) {
14020                 ptp_clock_unregister(bp->ptp_clock);
14021                 bp->ptp_clock = NULL;
14022         }
14023
14024         /* Delete storage MAC address */
14025         if (!NO_FCOE(bp)) {
14026                 rtnl_lock();
14027                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14028                 rtnl_unlock();
14029         }
14030
14031 #ifdef BCM_DCBNL
14032         /* Delete app tlvs from dcbnl */
14033         bnx2x_dcbnl_update_applist(bp, true);
14034 #endif
14035
14036         if (IS_PF(bp) &&
14037             !BP_NOMCP(bp) &&
14038             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14039                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14040
14041         /* Close the interface - either directly or implicitly */
14042         if (remove_netdev) {
14043                 unregister_netdev(dev);
14044         } else {
14045                 rtnl_lock();
14046                 dev_close(dev);
14047                 rtnl_unlock();
14048         }
14049
14050         bnx2x_iov_remove_one(bp);
14051
14052         /* Power on: we can't let PCI layer write to us while we are in D3 */
14053         if (IS_PF(bp)) {
14054                 bnx2x_set_power_state(bp, PCI_D0);
14055                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14056
14057                 /* Set endianity registers to reset values in case next driver
14058                  * boots in different endianty environment.
14059                  */
14060                 bnx2x_reset_endianity(bp);
14061         }
14062
14063         /* Disable MSI/MSI-X */
14064         bnx2x_disable_msi(bp);
14065
14066         /* Power off */
14067         if (IS_PF(bp))
14068                 bnx2x_set_power_state(bp, PCI_D3hot);
14069
14070         /* Make sure RESET task is not scheduled before continuing */
14071         cancel_delayed_work_sync(&bp->sp_rtnl_task);
14072
14073         /* send message via vfpf channel to release the resources of this vf */
14074         if (IS_VF(bp))
14075                 bnx2x_vfpf_release(bp);
14076
14077         /* Assumes no further PCIe PM changes will occur */
14078         if (system_state == SYSTEM_POWER_OFF) {
14079                 pci_wake_from_d3(pdev, bp->wol);
14080                 pci_set_power_state(pdev, PCI_D3hot);
14081         }
14082
14083         bnx2x_disable_pcie_error_reporting(bp);
14084         if (remove_netdev) {
14085                 if (bp->regview)
14086                         iounmap(bp->regview);
14087
14088                 /* For vfs, doorbells are part of the regview and were unmapped
14089                  * along with it. FW is only loaded by PF.
14090                  */
14091                 if (IS_PF(bp)) {
14092                         if (bp->doorbells)
14093                                 iounmap(bp->doorbells);
14094
14095                         bnx2x_release_firmware(bp);
14096                 } else {
14097                         bnx2x_vf_pci_dealloc(bp);
14098                 }
14099                 bnx2x_free_mem_bp(bp);
14100
14101                 free_netdev(dev);
14102
14103                 if (atomic_read(&pdev->enable_cnt) == 1)
14104                         pci_release_regions(pdev);
14105
14106                 pci_disable_device(pdev);
14107         }
14108 }
14109
14110 static void bnx2x_remove_one(struct pci_dev *pdev)
14111 {
14112         struct net_device *dev = pci_get_drvdata(pdev);
14113         struct bnx2x *bp;
14114
14115         if (!dev) {
14116                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14117                 return;
14118         }
14119         bp = netdev_priv(dev);
14120
14121         __bnx2x_remove(pdev, dev, bp, true);
14122 }
14123
14124 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14125 {
14126         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14127
14128         bp->rx_mode = BNX2X_RX_MODE_NONE;
14129
14130         if (CNIC_LOADED(bp))
14131                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14132
14133         /* Stop Tx */
14134         bnx2x_tx_disable(bp);
14135         /* Delete all NAPI objects */
14136         bnx2x_del_all_napi(bp);
14137         if (CNIC_LOADED(bp))
14138                 bnx2x_del_all_napi_cnic(bp);
14139         netdev_reset_tc(bp->dev);
14140
14141         del_timer_sync(&bp->timer);
14142         cancel_delayed_work_sync(&bp->sp_task);
14143         cancel_delayed_work_sync(&bp->period_task);
14144
14145         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14146                 bp->stats_state = STATS_STATE_DISABLED;
14147                 up(&bp->stats_lock);
14148         }
14149
14150         bnx2x_save_statistics(bp);
14151
14152         netif_carrier_off(bp->dev);
14153
14154         return 0;
14155 }
14156
14157 /**
14158  * bnx2x_io_error_detected - called when PCI error is detected
14159  * @pdev: Pointer to PCI device
14160  * @state: The current pci connection state
14161  *
14162  * This function is called after a PCI bus error affecting
14163  * this device has been detected.
14164  */
14165 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14166                                                 pci_channel_state_t state)
14167 {
14168         struct net_device *dev = pci_get_drvdata(pdev);
14169         struct bnx2x *bp = netdev_priv(dev);
14170
14171         rtnl_lock();
14172
14173         BNX2X_ERR("IO error detected\n");
14174
14175         netif_device_detach(dev);
14176
14177         if (state == pci_channel_io_perm_failure) {
14178                 rtnl_unlock();
14179                 return PCI_ERS_RESULT_DISCONNECT;
14180         }
14181
14182         if (netif_running(dev))
14183                 bnx2x_eeh_nic_unload(bp);
14184
14185         bnx2x_prev_path_mark_eeh(bp);
14186
14187         pci_disable_device(pdev);
14188
14189         rtnl_unlock();
14190
14191         /* Request a slot reset */
14192         return PCI_ERS_RESULT_NEED_RESET;
14193 }
14194
14195 /**
14196  * bnx2x_io_slot_reset - called after the PCI bus has been reset
14197  * @pdev: Pointer to PCI device
14198  *
14199  * Restart the card from scratch, as if from a cold-boot.
14200  */
14201 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14202 {
14203         struct net_device *dev = pci_get_drvdata(pdev);
14204         struct bnx2x *bp = netdev_priv(dev);
14205         int i;
14206
14207         rtnl_lock();
14208         BNX2X_ERR("IO slot reset initializing...\n");
14209         if (pci_enable_device(pdev)) {
14210                 dev_err(&pdev->dev,
14211                         "Cannot re-enable PCI device after reset\n");
14212                 rtnl_unlock();
14213                 return PCI_ERS_RESULT_DISCONNECT;
14214         }
14215
14216         pci_set_master(pdev);
14217         pci_restore_state(pdev);
14218         pci_save_state(pdev);
14219
14220         if (netif_running(dev))
14221                 bnx2x_set_power_state(bp, PCI_D0);
14222
14223         if (netif_running(dev)) {
14224                 BNX2X_ERR("IO slot reset --> driver unload\n");
14225
14226                 /* MCP should have been reset; Need to wait for validity */
14227                 bnx2x_init_shmem(bp);
14228
14229                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14230                         u32 v;
14231
14232                         v = SHMEM2_RD(bp,
14233                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14234                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14235                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14236                 }
14237                 bnx2x_drain_tx_queues(bp);
14238                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14239                 bnx2x_netif_stop(bp, 1);
14240                 bnx2x_free_irq(bp);
14241
14242                 /* Report UNLOAD_DONE to MCP */
14243                 bnx2x_send_unload_done(bp, true);
14244
14245                 bp->sp_state = 0;
14246                 bp->port.pmf = 0;
14247
14248                 bnx2x_prev_unload(bp);
14249
14250                 /* We should have reseted the engine, so It's fair to
14251                  * assume the FW will no longer write to the bnx2x driver.
14252                  */
14253                 bnx2x_squeeze_objects(bp);
14254                 bnx2x_free_skbs(bp);
14255                 for_each_rx_queue(bp, i)
14256                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14257                 bnx2x_free_fp_mem(bp);
14258                 bnx2x_free_mem(bp);
14259
14260                 bp->state = BNX2X_STATE_CLOSED;
14261         }
14262
14263         rtnl_unlock();
14264
14265         /* If AER, perform cleanup of the PCIe registers */
14266         if (bp->flags & AER_ENABLED) {
14267                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14268                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14269                 else
14270                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14271         }
14272
14273         return PCI_ERS_RESULT_RECOVERED;
14274 }
14275
14276 /**
14277  * bnx2x_io_resume - called when traffic can start flowing again
14278  * @pdev: Pointer to PCI device
14279  *
14280  * This callback is called when the error recovery driver tells us that
14281  * its OK to resume normal operation.
14282  */
14283 static void bnx2x_io_resume(struct pci_dev *pdev)
14284 {
14285         struct net_device *dev = pci_get_drvdata(pdev);
14286         struct bnx2x *bp = netdev_priv(dev);
14287
14288         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14289                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14290                 return;
14291         }
14292
14293         rtnl_lock();
14294
14295         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14296                                                         DRV_MSG_SEQ_NUMBER_MASK;
14297
14298         if (netif_running(dev))
14299                 bnx2x_nic_load(bp, LOAD_NORMAL);
14300
14301         netif_device_attach(dev);
14302
14303         rtnl_unlock();
14304 }
14305
14306 static const struct pci_error_handlers bnx2x_err_handler = {
14307         .error_detected = bnx2x_io_error_detected,
14308         .slot_reset     = bnx2x_io_slot_reset,
14309         .resume         = bnx2x_io_resume,
14310 };
14311
14312 static void bnx2x_shutdown(struct pci_dev *pdev)
14313 {
14314         struct net_device *dev = pci_get_drvdata(pdev);
14315         struct bnx2x *bp;
14316
14317         if (!dev)
14318                 return;
14319
14320         bp = netdev_priv(dev);
14321         if (!bp)
14322                 return;
14323
14324         rtnl_lock();
14325         netif_device_detach(dev);
14326         rtnl_unlock();
14327
14328         /* Don't remove the netdevice, as there are scenarios which will cause
14329          * the kernel to hang, e.g., when trying to remove bnx2i while the
14330          * rootfs is mounted from SAN.
14331          */
14332         __bnx2x_remove(pdev, dev, bp, false);
14333 }
14334
14335 static struct pci_driver bnx2x_pci_driver = {
14336         .name        = DRV_MODULE_NAME,
14337         .id_table    = bnx2x_pci_tbl,
14338         .probe       = bnx2x_init_one,
14339         .remove      = bnx2x_remove_one,
14340         .suspend     = bnx2x_suspend,
14341         .resume      = bnx2x_resume,
14342         .err_handler = &bnx2x_err_handler,
14343 #ifdef CONFIG_BNX2X_SRIOV
14344         .sriov_configure = bnx2x_sriov_configure,
14345 #endif
14346         .shutdown    = bnx2x_shutdown,
14347 };
14348
14349 static int __init bnx2x_init(void)
14350 {
14351         int ret;
14352
14353         pr_info("%s", version);
14354
14355         bnx2x_wq = create_singlethread_workqueue("bnx2x");
14356         if (bnx2x_wq == NULL) {
14357                 pr_err("Cannot create workqueue\n");
14358                 return -ENOMEM;
14359         }
14360         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14361         if (!bnx2x_iov_wq) {
14362                 pr_err("Cannot create iov workqueue\n");
14363                 destroy_workqueue(bnx2x_wq);
14364                 return -ENOMEM;
14365         }
14366
14367         ret = pci_register_driver(&bnx2x_pci_driver);
14368         if (ret) {
14369                 pr_err("Cannot register driver\n");
14370                 destroy_workqueue(bnx2x_wq);
14371                 destroy_workqueue(bnx2x_iov_wq);
14372         }
14373         return ret;
14374 }
14375
14376 static void __exit bnx2x_cleanup(void)
14377 {
14378         struct list_head *pos, *q;
14379
14380         pci_unregister_driver(&bnx2x_pci_driver);
14381
14382         destroy_workqueue(bnx2x_wq);
14383         destroy_workqueue(bnx2x_iov_wq);
14384
14385         /* Free globally allocated resources */
14386         list_for_each_safe(pos, q, &bnx2x_prev_list) {
14387                 struct bnx2x_prev_path_list *tmp =
14388                         list_entry(pos, struct bnx2x_prev_path_list, list);
14389                 list_del(pos);
14390                 kfree(tmp);
14391         }
14392 }
14393
14394 void bnx2x_notify_link_changed(struct bnx2x *bp)
14395 {
14396         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14397 }
14398
14399 module_init(bnx2x_init);
14400 module_exit(bnx2x_cleanup);
14401
14402 /**
14403  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14404  *
14405  * @bp:         driver handle
14406  * @set:        set or clear the CAM entry
14407  *
14408  * This function will wait until the ramrod completion returns.
14409  * Return 0 if success, -ENODEV if ramrod doesn't return.
14410  */
14411 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14412 {
14413         unsigned long ramrod_flags = 0;
14414
14415         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14416         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14417                                  &bp->iscsi_l2_mac_obj, true,
14418                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14419 }
14420
14421 /* count denotes the number of new completions we have seen */
14422 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14423 {
14424         struct eth_spe *spe;
14425         int cxt_index, cxt_offset;
14426
14427 #ifdef BNX2X_STOP_ON_ERROR
14428         if (unlikely(bp->panic))
14429                 return;
14430 #endif
14431
14432         spin_lock_bh(&bp->spq_lock);
14433         BUG_ON(bp->cnic_spq_pending < count);
14434         bp->cnic_spq_pending -= count;
14435
14436         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14437                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14438                                 & SPE_HDR_CONN_TYPE) >>
14439                                 SPE_HDR_CONN_TYPE_SHIFT;
14440                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14441                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14442
14443                 /* Set validation for iSCSI L2 client before sending SETUP
14444                  *  ramrod
14445                  */
14446                 if (type == ETH_CONNECTION_TYPE) {
14447                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14448                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14449                                         ILT_PAGE_CIDS;
14450                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14451                                         (cxt_index * ILT_PAGE_CIDS);
14452                                 bnx2x_set_ctx_validation(bp,
14453                                         &bp->context[cxt_index].
14454                                                          vcxt[cxt_offset].eth,
14455                                         BNX2X_ISCSI_ETH_CID(bp));
14456                         }
14457                 }
14458
14459                 /*
14460                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14461                  * and in the air. We also check that number of outstanding
14462                  * COMMON ramrods is not more than the EQ and SPQ can
14463                  * accommodate.
14464                  */
14465                 if (type == ETH_CONNECTION_TYPE) {
14466                         if (!atomic_read(&bp->cq_spq_left))
14467                                 break;
14468                         else
14469                                 atomic_dec(&bp->cq_spq_left);
14470                 } else if (type == NONE_CONNECTION_TYPE) {
14471                         if (!atomic_read(&bp->eq_spq_left))
14472                                 break;
14473                         else
14474                                 atomic_dec(&bp->eq_spq_left);
14475                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14476                            (type == FCOE_CONNECTION_TYPE)) {
14477                         if (bp->cnic_spq_pending >=
14478                             bp->cnic_eth_dev.max_kwqe_pending)
14479                                 break;
14480                         else
14481                                 bp->cnic_spq_pending++;
14482                 } else {
14483                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14484                         bnx2x_panic();
14485                         break;
14486                 }
14487
14488                 spe = bnx2x_sp_get_next(bp);
14489                 *spe = *bp->cnic_kwq_cons;
14490
14491                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14492                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14493
14494                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14495                         bp->cnic_kwq_cons = bp->cnic_kwq;
14496                 else
14497                         bp->cnic_kwq_cons++;
14498         }
14499         bnx2x_sp_prod_update(bp);
14500         spin_unlock_bh(&bp->spq_lock);
14501 }
14502
14503 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14504                                struct kwqe_16 *kwqes[], u32 count)
14505 {
14506         struct bnx2x *bp = netdev_priv(dev);
14507         int i;
14508
14509 #ifdef BNX2X_STOP_ON_ERROR
14510         if (unlikely(bp->panic)) {
14511                 BNX2X_ERR("Can't post to SP queue while panic\n");
14512                 return -EIO;
14513         }
14514 #endif
14515
14516         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14517             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14518                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14519                 return -EAGAIN;
14520         }
14521
14522         spin_lock_bh(&bp->spq_lock);
14523
14524         for (i = 0; i < count; i++) {
14525                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14526
14527                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14528                         break;
14529
14530                 *bp->cnic_kwq_prod = *spe;
14531
14532                 bp->cnic_kwq_pending++;
14533
14534                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14535                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14536                    spe->data.update_data_addr.hi,
14537                    spe->data.update_data_addr.lo,
14538                    bp->cnic_kwq_pending);
14539
14540                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14541                         bp->cnic_kwq_prod = bp->cnic_kwq;
14542                 else
14543                         bp->cnic_kwq_prod++;
14544         }
14545
14546         spin_unlock_bh(&bp->spq_lock);
14547
14548         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14549                 bnx2x_cnic_sp_post(bp, 0);
14550
14551         return i;
14552 }
14553
14554 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14555 {
14556         struct cnic_ops *c_ops;
14557         int rc = 0;
14558
14559         mutex_lock(&bp->cnic_mutex);
14560         c_ops = rcu_dereference_protected(bp->cnic_ops,
14561                                           lockdep_is_held(&bp->cnic_mutex));
14562         if (c_ops)
14563                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14564         mutex_unlock(&bp->cnic_mutex);
14565
14566         return rc;
14567 }
14568
14569 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14570 {
14571         struct cnic_ops *c_ops;
14572         int rc = 0;
14573
14574         rcu_read_lock();
14575         c_ops = rcu_dereference(bp->cnic_ops);
14576         if (c_ops)
14577                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14578         rcu_read_unlock();
14579
14580         return rc;
14581 }
14582
14583 /*
14584  * for commands that have no data
14585  */
14586 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14587 {
14588         struct cnic_ctl_info ctl = {0};
14589
14590         ctl.cmd = cmd;
14591
14592         return bnx2x_cnic_ctl_send(bp, &ctl);
14593 }
14594
14595 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14596 {
14597         struct cnic_ctl_info ctl = {0};
14598
14599         /* first we tell CNIC and only then we count this as a completion */
14600         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14601         ctl.data.comp.cid = cid;
14602         ctl.data.comp.error = err;
14603
14604         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14605         bnx2x_cnic_sp_post(bp, 0);
14606 }
14607
14608 /* Called with netif_addr_lock_bh() taken.
14609  * Sets an rx_mode config for an iSCSI ETH client.
14610  * Doesn't block.
14611  * Completion should be checked outside.
14612  */
14613 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14614 {
14615         unsigned long accept_flags = 0, ramrod_flags = 0;
14616         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14617         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14618
14619         if (start) {
14620                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14621                  * because it's the only way for UIO Queue to accept
14622                  * multicasts (in non-promiscuous mode only one Queue per
14623                  * function will receive multicast packets (leading in our
14624                  * case).
14625                  */
14626                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14627                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14628                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14629                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14630
14631                 /* Clear STOP_PENDING bit if START is requested */
14632                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14633
14634                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14635         } else
14636                 /* Clear START_PENDING bit if STOP is requested */
14637                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14638
14639         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14640                 set_bit(sched_state, &bp->sp_state);
14641         else {
14642                 __set_bit(RAMROD_RX, &ramrod_flags);
14643                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14644                                     ramrod_flags);
14645         }
14646 }
14647
14648 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14649 {
14650         struct bnx2x *bp = netdev_priv(dev);
14651         int rc = 0;
14652
14653         switch (ctl->cmd) {
14654         case DRV_CTL_CTXTBL_WR_CMD: {
14655                 u32 index = ctl->data.io.offset;
14656                 dma_addr_t addr = ctl->data.io.dma_addr;
14657
14658                 bnx2x_ilt_wr(bp, index, addr);
14659                 break;
14660         }
14661
14662         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14663                 int count = ctl->data.credit.credit_count;
14664
14665                 bnx2x_cnic_sp_post(bp, count);
14666                 break;
14667         }
14668
14669         /* rtnl_lock is held.  */
14670         case DRV_CTL_START_L2_CMD: {
14671                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14672                 unsigned long sp_bits = 0;
14673
14674                 /* Configure the iSCSI classification object */
14675                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14676                                    cp->iscsi_l2_client_id,
14677                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14678                                    bnx2x_sp(bp, mac_rdata),
14679                                    bnx2x_sp_mapping(bp, mac_rdata),
14680                                    BNX2X_FILTER_MAC_PENDING,
14681                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14682                                    &bp->macs_pool);
14683
14684                 /* Set iSCSI MAC address */
14685                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14686                 if (rc)
14687                         break;
14688
14689                 mmiowb();
14690                 barrier();
14691
14692                 /* Start accepting on iSCSI L2 ring */
14693
14694                 netif_addr_lock_bh(dev);
14695                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14696                 netif_addr_unlock_bh(dev);
14697
14698                 /* bits to wait on */
14699                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14700                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14701
14702                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14703                         BNX2X_ERR("rx_mode completion timed out!\n");
14704
14705                 break;
14706         }
14707
14708         /* rtnl_lock is held.  */
14709         case DRV_CTL_STOP_L2_CMD: {
14710                 unsigned long sp_bits = 0;
14711
14712                 /* Stop accepting on iSCSI L2 ring */
14713                 netif_addr_lock_bh(dev);
14714                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14715                 netif_addr_unlock_bh(dev);
14716
14717                 /* bits to wait on */
14718                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14719                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14720
14721                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14722                         BNX2X_ERR("rx_mode completion timed out!\n");
14723
14724                 mmiowb();
14725                 barrier();
14726
14727                 /* Unset iSCSI L2 MAC */
14728                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14729                                         BNX2X_ISCSI_ETH_MAC, true);
14730                 break;
14731         }
14732         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14733                 int count = ctl->data.credit.credit_count;
14734
14735                 smp_mb__before_atomic();
14736                 atomic_add(count, &bp->cq_spq_left);
14737                 smp_mb__after_atomic();
14738                 break;
14739         }
14740         case DRV_CTL_ULP_REGISTER_CMD: {
14741                 int ulp_type = ctl->data.register_data.ulp_type;
14742
14743                 if (CHIP_IS_E3(bp)) {
14744                         int idx = BP_FW_MB_IDX(bp);
14745                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14746                         int path = BP_PATH(bp);
14747                         int port = BP_PORT(bp);
14748                         int i;
14749                         u32 scratch_offset;
14750                         u32 *host_addr;
14751
14752                         /* first write capability to shmem2 */
14753                         if (ulp_type == CNIC_ULP_ISCSI)
14754                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14755                         else if (ulp_type == CNIC_ULP_FCOE)
14756                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14757                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14758
14759                         if ((ulp_type != CNIC_ULP_FCOE) ||
14760                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14761                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14762                                 break;
14763
14764                         /* if reached here - should write fcoe capabilities */
14765                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14766                         if (!scratch_offset)
14767                                 break;
14768                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14769                                                    fcoe_features[path][port]);
14770                         host_addr = (u32 *) &(ctl->data.register_data.
14771                                               fcoe_features);
14772                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14773                              i += 4)
14774                                 REG_WR(bp, scratch_offset + i,
14775                                        *(host_addr + i/4));
14776                 }
14777                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14778                 break;
14779         }
14780
14781         case DRV_CTL_ULP_UNREGISTER_CMD: {
14782                 int ulp_type = ctl->data.ulp_type;
14783
14784                 if (CHIP_IS_E3(bp)) {
14785                         int idx = BP_FW_MB_IDX(bp);
14786                         u32 cap;
14787
14788                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14789                         if (ulp_type == CNIC_ULP_ISCSI)
14790                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14791                         else if (ulp_type == CNIC_ULP_FCOE)
14792                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14793                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14794                 }
14795                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14796                 break;
14797         }
14798
14799         default:
14800                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14801                 rc = -EINVAL;
14802         }
14803
14804         /* For storage-only interfaces, change driver state */
14805         if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14806                 switch (ctl->drv_state) {
14807                 case DRV_NOP:
14808                         break;
14809                 case DRV_ACTIVE:
14810                         bnx2x_set_os_driver_state(bp,
14811                                                   OS_DRIVER_STATE_ACTIVE);
14812                         break;
14813                 case DRV_INACTIVE:
14814                         bnx2x_set_os_driver_state(bp,
14815                                                   OS_DRIVER_STATE_DISABLED);
14816                         break;
14817                 case DRV_UNLOADED:
14818                         bnx2x_set_os_driver_state(bp,
14819                                                   OS_DRIVER_STATE_NOT_LOADED);
14820                         break;
14821                 default:
14822                 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14823                 }
14824         }
14825
14826         return rc;
14827 }
14828
14829 static int bnx2x_get_fc_npiv(struct net_device *dev,
14830                              struct cnic_fc_npiv_tbl *cnic_tbl)
14831 {
14832         struct bnx2x *bp = netdev_priv(dev);
14833         struct bdn_fc_npiv_tbl *tbl = NULL;
14834         u32 offset, entries;
14835         int rc = -EINVAL;
14836         int i;
14837
14838         if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14839                 goto out;
14840
14841         DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14842
14843         tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14844         if (!tbl) {
14845                 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14846                 goto out;
14847         }
14848
14849         offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14850         if (!offset) {
14851                 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14852                 goto out;
14853         }
14854         DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14855
14856         /* Read the table contents from nvram */
14857         if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14858                 BNX2X_ERR("Failed to read FC-NPIV table\n");
14859                 goto out;
14860         }
14861
14862         /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14863          * the number of entries back to cpu endianness.
14864          */
14865         entries = tbl->fc_npiv_cfg.num_of_npiv;
14866         entries = (__force u32)be32_to_cpu((__force __be32)entries);
14867         tbl->fc_npiv_cfg.num_of_npiv = entries;
14868
14869         if (!tbl->fc_npiv_cfg.num_of_npiv) {
14870                 DP(BNX2X_MSG_MCP,
14871                    "No FC-NPIV table [valid, simply not present]\n");
14872                 goto out;
14873         } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14874                 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14875                           tbl->fc_npiv_cfg.num_of_npiv);
14876                 goto out;
14877         } else {
14878                 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14879                    tbl->fc_npiv_cfg.num_of_npiv);
14880         }
14881
14882         /* Copy the data into cnic-provided struct */
14883         cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14884         for (i = 0; i < cnic_tbl->count; i++) {
14885                 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14886                 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14887         }
14888
14889         rc = 0;
14890 out:
14891         kfree(tbl);
14892         return rc;
14893 }
14894
14895 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14896 {
14897         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14898
14899         if (bp->flags & USING_MSIX_FLAG) {
14900                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14901                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14902                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14903         } else {
14904                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14905                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14906         }
14907         if (!CHIP_IS_E1x(bp))
14908                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14909         else
14910                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14911
14912         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14913         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14914         cp->irq_arr[1].status_blk = bp->def_status_blk;
14915         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14916         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14917
14918         cp->num_irq = 2;
14919 }
14920
14921 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14922 {
14923         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14924
14925         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14926                              bnx2x_cid_ilt_lines(bp);
14927         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14928         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14929         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14930
14931         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14932            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14933            cp->iscsi_l2_cid);
14934
14935         if (NO_ISCSI_OOO(bp))
14936                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14937 }
14938
14939 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14940                                void *data)
14941 {
14942         struct bnx2x *bp = netdev_priv(dev);
14943         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14944         int rc;
14945
14946         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14947
14948         if (ops == NULL) {
14949                 BNX2X_ERR("NULL ops received\n");
14950                 return -EINVAL;
14951         }
14952
14953         if (!CNIC_SUPPORT(bp)) {
14954                 BNX2X_ERR("Can't register CNIC when not supported\n");
14955                 return -EOPNOTSUPP;
14956         }
14957
14958         if (!CNIC_LOADED(bp)) {
14959                 rc = bnx2x_load_cnic(bp);
14960                 if (rc) {
14961                         BNX2X_ERR("CNIC-related load failed\n");
14962                         return rc;
14963                 }
14964         }
14965
14966         bp->cnic_enabled = true;
14967
14968         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14969         if (!bp->cnic_kwq)
14970                 return -ENOMEM;
14971
14972         bp->cnic_kwq_cons = bp->cnic_kwq;
14973         bp->cnic_kwq_prod = bp->cnic_kwq;
14974         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14975
14976         bp->cnic_spq_pending = 0;
14977         bp->cnic_kwq_pending = 0;
14978
14979         bp->cnic_data = data;
14980
14981         cp->num_irq = 0;
14982         cp->drv_state |= CNIC_DRV_STATE_REGD;
14983         cp->iro_arr = bp->iro_arr;
14984
14985         bnx2x_setup_cnic_irq_info(bp);
14986
14987         rcu_assign_pointer(bp->cnic_ops, ops);
14988
14989         /* Schedule driver to read CNIC driver versions */
14990         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14991
14992         return 0;
14993 }
14994
14995 static int bnx2x_unregister_cnic(struct net_device *dev)
14996 {
14997         struct bnx2x *bp = netdev_priv(dev);
14998         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14999
15000         mutex_lock(&bp->cnic_mutex);
15001         cp->drv_state = 0;
15002         RCU_INIT_POINTER(bp->cnic_ops, NULL);
15003         mutex_unlock(&bp->cnic_mutex);
15004         synchronize_rcu();
15005         bp->cnic_enabled = false;
15006         kfree(bp->cnic_kwq);
15007         bp->cnic_kwq = NULL;
15008
15009         return 0;
15010 }
15011
15012 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
15013 {
15014         struct bnx2x *bp = netdev_priv(dev);
15015         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15016
15017         /* If both iSCSI and FCoE are disabled - return NULL in
15018          * order to indicate CNIC that it should not try to work
15019          * with this device.
15020          */
15021         if (NO_ISCSI(bp) && NO_FCOE(bp))
15022                 return NULL;
15023
15024         cp->drv_owner = THIS_MODULE;
15025         cp->chip_id = CHIP_ID(bp);
15026         cp->pdev = bp->pdev;
15027         cp->io_base = bp->regview;
15028         cp->io_base2 = bp->doorbells;
15029         cp->max_kwqe_pending = 8;
15030         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
15031         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15032                              bnx2x_cid_ilt_lines(bp);
15033         cp->ctx_tbl_len = CNIC_ILT_LINES;
15034         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15035         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15036         cp->drv_ctl = bnx2x_drv_ctl;
15037         cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15038         cp->drv_register_cnic = bnx2x_register_cnic;
15039         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15040         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15041         cp->iscsi_l2_client_id =
15042                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15043         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15044
15045         if (NO_ISCSI_OOO(bp))
15046                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15047
15048         if (NO_ISCSI(bp))
15049                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15050
15051         if (NO_FCOE(bp))
15052                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15053
15054         BNX2X_DEV_INFO(
15055                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15056            cp->ctx_blk_size,
15057            cp->ctx_tbl_offset,
15058            cp->ctx_tbl_len,
15059            cp->starting_cid);
15060         return cp;
15061 }
15062
15063 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15064 {
15065         struct bnx2x *bp = fp->bp;
15066         u32 offset = BAR_USTRORM_INTMEM;
15067
15068         if (IS_VF(bp))
15069                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15070         else if (!CHIP_IS_E1x(bp))
15071                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15072         else
15073                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15074
15075         return offset;
15076 }
15077
15078 /* called only on E1H or E2.
15079  * When pretending to be PF, the pretend value is the function number 0...7
15080  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15081  * combination
15082  */
15083 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15084 {
15085         u32 pretend_reg;
15086
15087         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15088                 return -1;
15089
15090         /* get my own pretend register */
15091         pretend_reg = bnx2x_get_pretend_reg(bp);
15092         REG_WR(bp, pretend_reg, pretend_func_val);
15093         REG_RD(bp, pretend_reg);
15094         return 0;
15095 }
15096
15097 static void bnx2x_ptp_task(struct work_struct *work)
15098 {
15099         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15100         int port = BP_PORT(bp);
15101         u32 val_seq;
15102         u64 timestamp, ns;
15103         struct skb_shared_hwtstamps shhwtstamps;
15104
15105         /* Read Tx timestamp registers */
15106         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15107                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15108         if (val_seq & 0x10000) {
15109                 /* There is a valid timestamp value */
15110                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15111                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15112                 timestamp <<= 32;
15113                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15114                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15115                 /* Reset timestamp register to allow new timestamp */
15116                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15117                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15118                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15119
15120                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15121                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15122                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15123                 dev_kfree_skb_any(bp->ptp_tx_skb);
15124                 bp->ptp_tx_skb = NULL;
15125
15126                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15127                    timestamp, ns);
15128         } else {
15129                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15130                 /* Reschedule to keep checking for a valid timestamp value */
15131                 schedule_work(&bp->ptp_task);
15132         }
15133 }
15134
15135 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15136 {
15137         int port = BP_PORT(bp);
15138         u64 timestamp, ns;
15139
15140         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15141                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15142         timestamp <<= 32;
15143         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15144                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15145
15146         /* Reset timestamp register to allow new timestamp */
15147         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15148                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15149
15150         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15151
15152         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15153
15154         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15155            timestamp, ns);
15156 }
15157
15158 /* Read the PHC */
15159 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15160 {
15161         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15162         int port = BP_PORT(bp);
15163         u32 wb_data[2];
15164         u64 phc_cycles;
15165
15166         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15167                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15168         phc_cycles = wb_data[1];
15169         phc_cycles = (phc_cycles << 32) + wb_data[0];
15170
15171         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15172
15173         return phc_cycles;
15174 }
15175
15176 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15177 {
15178         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15179         bp->cyclecounter.read = bnx2x_cyclecounter_read;
15180         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15181         bp->cyclecounter.shift = 0;
15182         bp->cyclecounter.mult = 1;
15183 }
15184
15185 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15186 {
15187         struct bnx2x_func_state_params func_params = {NULL};
15188         struct bnx2x_func_set_timesync_params *set_timesync_params =
15189                 &func_params.params.set_timesync;
15190
15191         /* Prepare parameters for function state transitions */
15192         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15193         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15194
15195         func_params.f_obj = &bp->func_obj;
15196         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15197
15198         /* Function parameters */
15199         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15200         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15201
15202         return bnx2x_func_state_change(bp, &func_params);
15203 }
15204
15205 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15206 {
15207         struct bnx2x_queue_state_params q_params;
15208         int rc, i;
15209
15210         /* send queue update ramrod to enable PTP packets */
15211         memset(&q_params, 0, sizeof(q_params));
15212         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15213         q_params.cmd = BNX2X_Q_CMD_UPDATE;
15214         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15215                   &q_params.params.update.update_flags);
15216         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15217                   &q_params.params.update.update_flags);
15218
15219         /* send the ramrod on all the queues of the PF */
15220         for_each_eth_queue(bp, i) {
15221                 struct bnx2x_fastpath *fp = &bp->fp[i];
15222
15223                 /* Set the appropriate Queue object */
15224                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15225
15226                 /* Update the Queue state */
15227                 rc = bnx2x_queue_state_change(bp, &q_params);
15228                 if (rc) {
15229                         BNX2X_ERR("Failed to enable PTP packets\n");
15230                         return rc;
15231                 }
15232         }
15233
15234         return 0;
15235 }
15236
15237 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15238 {
15239         int port = BP_PORT(bp);
15240         int rc;
15241
15242         if (!bp->hwtstamp_ioctl_called)
15243                 return 0;
15244
15245         switch (bp->tx_type) {
15246         case HWTSTAMP_TX_ON:
15247                 bp->flags |= TX_TIMESTAMPING_EN;
15248                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15249                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15250                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15251                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15252                 break;
15253         case HWTSTAMP_TX_ONESTEP_SYNC:
15254                 BNX2X_ERR("One-step timestamping is not supported\n");
15255                 return -ERANGE;
15256         }
15257
15258         switch (bp->rx_filter) {
15259         case HWTSTAMP_FILTER_NONE:
15260                 break;
15261         case HWTSTAMP_FILTER_ALL:
15262         case HWTSTAMP_FILTER_SOME:
15263                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15264                 break;
15265         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15266         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15267         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15268                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15269                 /* Initialize PTP detection for UDP/IPv4 events */
15270                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15271                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15272                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15273                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15274                 break;
15275         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15276         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15277         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15278                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15279                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15280                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15281                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15282                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15283                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15284                 break;
15285         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15286         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15287         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15288                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15289                 /* Initialize PTP detection L2 events */
15290                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15291                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15292                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15293                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15294
15295                 break;
15296         case HWTSTAMP_FILTER_PTP_V2_EVENT:
15297         case HWTSTAMP_FILTER_PTP_V2_SYNC:
15298         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15299                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15300                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15301                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15302                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15303                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15304                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15305                 break;
15306         }
15307
15308         /* Indicate to FW that this PF expects recorded PTP packets */
15309         rc = bnx2x_enable_ptp_packets(bp);
15310         if (rc)
15311                 return rc;
15312
15313         /* Enable sending PTP packets to host */
15314         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15315                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15316
15317         return 0;
15318 }
15319
15320 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15321 {
15322         struct hwtstamp_config config;
15323         int rc;
15324
15325         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15326
15327         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15328                 return -EFAULT;
15329
15330         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15331            config.tx_type, config.rx_filter);
15332
15333         if (config.flags) {
15334                 BNX2X_ERR("config.flags is reserved for future use\n");
15335                 return -EINVAL;
15336         }
15337
15338         bp->hwtstamp_ioctl_called = 1;
15339         bp->tx_type = config.tx_type;
15340         bp->rx_filter = config.rx_filter;
15341
15342         rc = bnx2x_configure_ptp_filters(bp);
15343         if (rc)
15344                 return rc;
15345
15346         config.rx_filter = bp->rx_filter;
15347
15348         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15349                 -EFAULT : 0;
15350 }
15351
15352 /* Configures HW for PTP */
15353 static int bnx2x_configure_ptp(struct bnx2x *bp)
15354 {
15355         int rc, port = BP_PORT(bp);
15356         u32 wb_data[2];
15357
15358         /* Reset PTP event detection rules - will be configured in the IOCTL */
15359         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15360                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15361         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15362                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15363         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15364                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15365         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15366                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15367
15368         /* Disable PTP packets to host - will be configured in the IOCTL*/
15369         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15370                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15371
15372         /* Enable the PTP feature */
15373         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15374                NIG_REG_P0_PTP_EN, 0x3F);
15375
15376         /* Enable the free-running counter */
15377         wb_data[0] = 0;
15378         wb_data[1] = 0;
15379         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15380
15381         /* Reset drift register (offset register is not reset) */
15382         rc = bnx2x_send_reset_timesync_ramrod(bp);
15383         if (rc) {
15384                 BNX2X_ERR("Failed to reset PHC drift register\n");
15385                 return -EFAULT;
15386         }
15387
15388         /* Reset possibly old timestamps */
15389         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15390                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15391         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15392                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15393
15394         return 0;
15395 }
15396
15397 /* Called during load, to initialize PTP-related stuff */
15398 void bnx2x_init_ptp(struct bnx2x *bp)
15399 {
15400         int rc;
15401
15402         /* Configure PTP in HW */
15403         rc = bnx2x_configure_ptp(bp);
15404         if (rc) {
15405                 BNX2X_ERR("Stopping PTP initialization\n");
15406                 return;
15407         }
15408
15409         /* Init work queue for Tx timestamping */
15410         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15411
15412         /* Init cyclecounter and timecounter. This is done only in the first
15413          * load. If done in every load, PTP application will fail when doing
15414          * unload / load (e.g. MTU change) while it is running.
15415          */
15416         if (!bp->timecounter_init_done) {
15417                 bnx2x_init_cyclecounter(bp);
15418                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15419                                  ktime_to_ns(ktime_get_real()));
15420                 bp->timecounter_init_done = 1;
15421         }
15422
15423         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15424 }