drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62
  63 #include "bnx2x.h"
  64 #include "bnx2x_init.h"
  65 #include "bnx2x_init_ops.h"
  66 #include "bnx2x_cmn.h"
  67 #include "bnx2x_vfpf.h"
  68 #include "bnx2x_dcb.h"
  69 #include "bnx2x_sp.h"
  70 #include <linux/firmware.h>
  71 #include "bnx2x_fw_file_hdr.h"
  72 /* FW files */
  73 /*(DEBLOBBED)*/
  74 #define FW_FILE_NAME_E1         "/*(DEBLOBBED)*/"
  75 #define FW_FILE_NAME_E1H        "/*(DEBLOBBED)*/"
  76 #define FW_FILE_NAME_E2         "/*(DEBLOBBED)*/"
  77 #define bnx2x_init_block(bp, start, end) \
  78   return (printk(KERN_ERR "%s: Missing Free firmware\n", bp->dev->name),\
  79           -EINVAL)
  80
  81 /* Time in jiffies before concluding the transmitter is hung */
  82 #define TX_TIMEOUT              (5*HZ)
  83
  84 static char version[] =
  85         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  86         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  87
  88 MODULE_AUTHOR("Eliezer Tamir");
  89 MODULE_DESCRIPTION("QLogic "
  90                    "BCM57710/57711/57711E/"
  91                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  92                    "57840/57840_MF Driver");
  93 MODULE_LICENSE("GPL");
  94 MODULE_VERSION(DRV_MODULE_VERSION);
  95 /*(DEBLOBBED)*/
  96
  97 int bnx2x_num_queues;
  98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, S_IRUGO);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 static int int_mode;
 107 module_param(int_mode, int, S_IRUGO);
 108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 109                                 "(1 INT#x; 2 MSI)");
 110
 111 static int dropless_fc;
 112 module_param(dropless_fc, int, S_IRUGO);
 113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 114
 115 static int mrrs = -1;
 116 module_param(mrrs, int, S_IRUGO);
 117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 118
 119 static int debug;
 120 module_param(debug, int, S_IRUGO);
 121 MODULE_PARM_DESC(debug, " Default debug msglevel");
 122
 123 static struct workqueue_struct *bnx2x_wq;
 124 struct workqueue_struct *bnx2x_iov_wq;
 125
 126 struct bnx2x_mac_vals {
 127         u32 xmac_addr;
 128         u32 xmac_val;
 129         u32 emac_addr;
 130         u32 emac_val;
 131         u32 umac_addr[2];
 132         u32 umac_val[2];
 133         u32 bmac_addr;
 134         u32 bmac_val[2];
 135 };
 136
 137 enum bnx2x_board_type {
 138         BCM57710 = 0,
 139         BCM57711,
 140         BCM57711E,
 141         BCM57712,
 142         BCM57712_MF,
 143         BCM57712_VF,
 144         BCM57800,
 145         BCM57800_MF,
 146         BCM57800_VF,
 147         BCM57810,
 148         BCM57810_MF,
 149         BCM57810_VF,
 150         BCM57840_4_10,
 151         BCM57840_2_20,
 152         BCM57840_MF,
 153         BCM57840_VF,
 154         BCM57811,
 155         BCM57811_MF,
 156         BCM57840_O,
 157         BCM57840_MFO,
 158         BCM57811_VF
 159 };
 160
 161 /* indexed by board_type, above */
 162 static struct {
 163         char *name;
 164 } board_info[] = {
 165         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 166         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 167         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 168         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 169         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 170         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 171         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 172         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 173         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 175         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 176         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 178         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 179         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 180         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 181         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 182         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 183         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 184         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 185         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 186 };
 187
 188 #ifndef PCI_DEVICE_ID_NX2_57710
 189 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 190 #endif
 191 #ifndef PCI_DEVICE_ID_NX2_57711
 192 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711E
 195 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57712
 198 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 201 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 204 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57800
 207 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 210 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 213 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57810
 216 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 219 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57840_O
 222 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 225 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 228 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 231 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 234 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 237 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 240 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57811
 243 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 246 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 249 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 250 #endif
 251
 252 static const struct pci_device_id bnx2x_pci_tbl[] = {
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 266         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 273         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 277         { 0 }
 278 };
 279
 280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 281
 282 /* Global resources for unloading a previously loaded device */
 283 #define BNX2X_PREV_WAIT_NEEDED 1
 284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 285 static LIST_HEAD(bnx2x_prev_list);
 286
 287 /* Forward declaration */
 288 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 289 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 290 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 291
 292 /****************************************************************************
 293 * General service functions
 294 ****************************************************************************/
 295
 296 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 297
 298 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 299                                        u32 addr, dma_addr_t mapping)
 300 {
 301         REG_WR(bp,  addr, U64_LO(mapping));
 302         REG_WR(bp,  addr + 4, U64_HI(mapping));
 303 }
 304
 305 static void storm_memset_spq_addr(struct bnx2x *bp,
 306                                   dma_addr_t mapping, u16 abs_fid)
 307 {
 308         u32 addr = XSEM_REG_FAST_MEMORY +
 309                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 310
 311         __storm_memset_dma_mapping(bp, addr, mapping);
 312 }
 313
 314 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 315                                   u16 pf_id)
 316 {
 317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 324                 pf_id);
 325 }
 326
 327 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 328                                  u8 enable)
 329 {
 330         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 337                 enable);
 338 }
 339
 340 static void storm_memset_eq_data(struct bnx2x *bp,
 341                                  struct event_ring_data *eq_data,
 342                                 u16 pfid)
 343 {
 344         size_t size = sizeof(struct event_ring_data);
 345
 346         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 347
 348         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 349 }
 350
 351 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 352                                  u16 pfid)
 353 {
 354         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 355         REG_WR16(bp, addr, eq_prod);
 356 }
 357
 358 /* used only at init
 359  * locking is done by mcp
 360  */
 361 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 362 {
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 364         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 366                                PCICFG_VENDOR_ID_OFFSET);
 367 }
 368
 369 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 370 {
 371         u32 val;
 372
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 374         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 375         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 376                                PCICFG_VENDOR_ID_OFFSET);
 377
 378         return val;
 379 }
 380
 381 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 382 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 383 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 384 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 385 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 386
 387 static void bnx2x_dp_dmae(struct bnx2x *bp,
 388                           struct dmae_command *dmae, int msglvl)
 389 {
 390         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 391         int i;
 392
 393         switch (dmae->opcode & DMAE_COMMAND_DST) {
 394         case DMAE_CMD_DST_PCI:
 395                 if (src_type == DMAE_CMD_SRC_PCI)
 396                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 397                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 398                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 399                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 400                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 401                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 402                            dmae->comp_val);
 403                 else
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_lo >> 2,
 408                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 break;
 412         case DMAE_CMD_DST_GRC:
 413                 if (src_type == DMAE_CMD_SRC_PCI)
 414                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 415                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 416                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 417                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 418                            dmae->len, dmae->dst_addr_lo >> 2,
 419                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 420                            dmae->comp_val);
 421                 else
 422                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 423                            "src [%08x], len [%d*4], dst [%08x]\n"
 424                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 425                            dmae->opcode, dmae->src_addr_lo >> 2,
 426                            dmae->len, dmae->dst_addr_lo >> 2,
 427                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 428                            dmae->comp_val);
 429                 break;
 430         default:
 431                 if (src_type == DMAE_CMD_SRC_PCI)
 432                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 433                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 434                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 435                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 436                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 437                            dmae->comp_val);
 438                 else
 439                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 440                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 441                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 442                            dmae->opcode, dmae->src_addr_lo >> 2,
 443                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 444                            dmae->comp_val);
 445                 break;
 446         }
 447
 448         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 449                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 450                    i, *(((u32 *)dmae) + i));
 451 }
 452
 453 /* copy command into DMAE command memory and set DMAE command go */
 454 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 455 {
 456         u32 cmd_offset;
 457         int i;
 458
 459         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 460         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 461                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 462         }
 463         REG_WR(bp, dmae_reg_go_c[idx], 1);
 464 }
 465
 466 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 467 {
 468         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 469                            DMAE_CMD_C_ENABLE);
 470 }
 471
 472 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 473 {
 474         return opcode & ~DMAE_CMD_SRC_RESET;
 475 }
 476
 477 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 478                              bool with_comp, u8 comp_type)
 479 {
 480         u32 opcode = 0;
 481
 482         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 483                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 484
 485         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 486
 487         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 488         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 489                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 490         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 491
 492 #ifdef __BIG_ENDIAN
 493         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 494 #else
 495         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 496 #endif
 497         if (with_comp)
 498                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 499         return opcode;
 500 }
 501
 502 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 503                                       struct dmae_command *dmae,
 504                                       u8 src_type, u8 dst_type)
 505 {
 506         memset(dmae, 0, sizeof(struct dmae_command));
 507
 508         /* set the opcode */
 509         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 510                                          true, DMAE_COMP_PCI);
 511
 512         /* fill in the completion parameters */
 513         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 514         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 515         dmae->comp_val = DMAE_COMP_VAL;
 516 }
 517
 518 /* issue a dmae command over the init-channel and wait for completion */
 519 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 520                                u32 *comp)
 521 {
 522         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 523         int rc = 0;
 524
 525         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 526
 527         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 528          * as long as this code is called both from syscall context and
 529          * from ndo_set_rx_mode() flow that may be called from BH.
 530          */
 531
 532         spin_lock_bh(&bp->dmae_lock);
 533
 534         /* reset completion */
 535         *comp = 0;
 536
 537         /* post the command on the channel used for initializations */
 538         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 539
 540         /* wait for completion */
 541         udelay(5);
 542         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 543
 544                 if (!cnt ||
 545                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 546                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 547                         BNX2X_ERR("DMAE timeout!\n");
 548                         rc = DMAE_TIMEOUT;
 549                         goto unlock;
 550                 }
 551                 cnt--;
 552                 udelay(50);
 553         }
 554         if (*comp & DMAE_PCI_ERR_FLAG) {
 555                 BNX2X_ERR("DMAE PCI error!\n");
 556                 rc = DMAE_PCI_ERROR;
 557         }
 558
 559 unlock:
 560
 561         spin_unlock_bh(&bp->dmae_lock);
 562
 563         return rc;
 564 }
 565
 566 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 567                       u32 len32)
 568 {
 569         int rc;
 570         struct dmae_command dmae;
 571
 572         if (!bp->dmae_ready) {
 573                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 574
 575                 if (CHIP_IS_E1(bp))
 576                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 577                 else
 578                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 579                 return;
 580         }
 581
 582         /* set opcode and fixed command fields */
 583         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 584
 585         /* fill in addresses and len */
 586         dmae.src_addr_lo = U64_LO(dma_addr);
 587         dmae.src_addr_hi = U64_HI(dma_addr);
 588         dmae.dst_addr_lo = dst_addr >> 2;
 589         dmae.dst_addr_hi = 0;
 590         dmae.len = len32;
 591
 592         /* issue the command and wait for completion */
 593         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 594         if (rc) {
 595                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 596 #ifdef BNX2X_STOP_ON_ERROR
 597                 bnx2x_panic();
 598 #endif
 599         }
 600 }
 601
 602 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 603 {
 604         int rc;
 605         struct dmae_command dmae;
 606
 607         if (!bp->dmae_ready) {
 608                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 609                 int i;
 610
 611                 if (CHIP_IS_E1(bp))
 612                         for (i = 0; i < len32; i++)
 613                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 614                 else
 615                         for (i = 0; i < len32; i++)
 616                                 data[i] = REG_RD(bp, src_addr + i*4);
 617
 618                 return;
 619         }
 620
 621         /* set opcode and fixed command fields */
 622         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 623
 624         /* fill in addresses and len */
 625         dmae.src_addr_lo = src_addr >> 2;
 626         dmae.src_addr_hi = 0;
 627         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 628         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 629         dmae.len = len32;
 630
 631         /* issue the command and wait for completion */
 632         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 633         if (rc) {
 634                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 635 #ifdef BNX2X_STOP_ON_ERROR
 636                 bnx2x_panic();
 637 #endif
 638         }
 639 }
 640
 641 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 642                                       u32 addr, u32 len)
 643 {
 644         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 645         int offset = 0;
 646
 647         while (len > dmae_wr_max) {
 648                 bnx2x_write_dmae(bp, phys_addr + offset,
 649                                  addr + offset, dmae_wr_max);
 650                 offset += dmae_wr_max * 4;
 651                 len -= dmae_wr_max;
 652         }
 653
 654         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 655 }
 656
 657 enum storms {
 658            XSTORM,
 659            TSTORM,
 660            CSTORM,
 661            USTORM,
 662            MAX_STORMS
 663 };
 664
 665 #define STORMS_NUM 4
 666 #define REGS_IN_ENTRY 4
 667
 668 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 669                                               enum storms storm,
 670                                               int entry)
 671 {
 672         switch (storm) {
 673         case XSTORM:
 674                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 675         case TSTORM:
 676                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 677         case CSTORM:
 678                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 679         case USTORM:
 680                 return USTORM_ASSERT_LIST_OFFSET(entry);
 681         case MAX_STORMS:
 682         default:
 683                 BNX2X_ERR("unknown storm\n");
 684         }
 685         return -EINVAL;
 686 }
 687
 688 static int bnx2x_mc_assert(struct bnx2x *bp)
 689 {
 690         char last_idx;
 691         int i, j, rc = 0;
 692         enum storms storm;
 693         u32 regs[REGS_IN_ENTRY];
 694         u32 bar_storm_intmem[STORMS_NUM] = {
 695                 BAR_XSTRORM_INTMEM,
 696                 BAR_TSTRORM_INTMEM,
 697                 BAR_CSTRORM_INTMEM,
 698                 BAR_USTRORM_INTMEM
 699         };
 700         u32 storm_assert_list_index[STORMS_NUM] = {
 701                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 703                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 704                 USTORM_ASSERT_LIST_INDEX_OFFSET
 705         };
 706         char *storms_string[STORMS_NUM] = {
 707                 "XSTORM",
 708                 "TSTORM",
 709                 "CSTORM",
 710                 "USTORM"
 711         };
 712
 713         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 714                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 715                                    storm_assert_list_index[storm]);
 716                 if (last_idx)
 717                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 718                                   storms_string[storm], last_idx);
 719
 720                 /* print the asserts */
 721                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 722                         /* read a single assert entry */
 723                         for (j = 0; j < REGS_IN_ENTRY; j++)
 724                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 725                                           bnx2x_get_assert_list_entry(bp,
 726                                                                       storm,
 727                                                                       i) +
 728                                           sizeof(u32) * j);
 729
 730                         /* log entry if it contains a valid assert */
 731                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 732                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 733                                           storms_string[storm], i, regs[3],
 734                                           regs[2], regs[1], regs[0]);
 735                                 rc++;
 736                         } else {
 737                                 break;
 738                         }
 739                 }
 740         }
 741
 742         BNX2X_ERR("Chip Revision: %s, /*(DEBLOBBED)*/\n",
 743                   CHIP_IS_E1(bp) ? "everest1" :
 744                   CHIP_IS_E1H(bp) ? "everest1h" :
 745                   CHIP_IS_E2(bp) ? "everest2" : "everest3"/*(DEBLOBBED)*/);
 746
 747         return rc;
 748 }
 749
 750 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 751 #define SCRATCH_BUFFER_SIZE(bp) \
 752         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 753
 754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 755 {
 756         u32 addr, val;
 757         u32 mark, offset;
 758         __be32 data[9];
 759         int word;
 760         u32 trace_shmem_base;
 761         if (BP_NOMCP(bp)) {
 762                 BNX2X_ERR("NO MCP - can not dump\n");
 763                 return;
 764         }
 765         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 766                 (bp->common.bc_ver & 0xff0000) >> 16,
 767                 (bp->common.bc_ver & 0xff00) >> 8,
 768                 (bp->common.bc_ver & 0xff));
 769
 770         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 771         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 772                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 773
 774         if (BP_PATH(bp) == 0)
 775                 trace_shmem_base = bp->common.shmem_base;
 776         else
 777                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 778
 779         /* sanity */
 780         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 781             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 782                                 SCRATCH_BUFFER_SIZE(bp)) {
 783                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 784                           trace_shmem_base);
 785                 return;
 786         }
 787
 788         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 789
 790         /* validate TRCB signature */
 791         mark = REG_RD(bp, addr);
 792         if (mark != MFW_TRACE_SIGNATURE) {
 793                 BNX2X_ERR("Trace buffer signature is missing.");
 794                 return ;
 795         }
 796
 797         /* read cyclic buffer pointer */
 798         addr += 4;
 799         mark = REG_RD(bp, addr);
 800         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 801         if (mark >= trace_shmem_base || mark < addr + 4) {
 802                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 803                 return;
 804         }
 805         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 806
 807         printk("%s", lvl);
 808
 809         /* dump buffer after the mark */
 810         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 811                 for (word = 0; word < 8; word++)
 812                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 813                 data[8] = 0x0;
 814                 pr_cont("%s", (char *)data);
 815         }
 816
 817         /* dump buffer before the mark */
 818         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 819                 for (word = 0; word < 8; word++)
 820                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 821                 data[8] = 0x0;
 822                 pr_cont("%s", (char *)data);
 823         }
 824         printk("%s" "end of fw dump\n", lvl);
 825 }
 826
 827 static void bnx2x_fw_dump(struct bnx2x *bp)
 828 {
 829         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 830 }
 831
 832 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 833 {
 834         int port = BP_PORT(bp);
 835         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 836         u32 val = REG_RD(bp, addr);
 837
 838         /* in E1 we must use only PCI configuration space to disable
 839          * MSI/MSIX capability
 840          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 841          */
 842         if (CHIP_IS_E1(bp)) {
 843                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 844                  * Use mask register to prevent from HC sending interrupts
 845                  * after we exit the function
 846                  */
 847                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 848
 849                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 850                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 851                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 852         } else
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 855                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 856                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 857
 858         DP(NETIF_MSG_IFDOWN,
 859            "write %x to HC %d (addr 0x%x)\n",
 860            val, port, addr);
 861
 862         /* flush all outstanding writes */
 863         mmiowb();
 864
 865         REG_WR(bp, addr, val);
 866         if (REG_RD(bp, addr) != val)
 867                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 868 }
 869
 870 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 871 {
 872         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 873
 874         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 875                  IGU_PF_CONF_INT_LINE_EN |
 876                  IGU_PF_CONF_ATTN_BIT_EN);
 877
 878         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 879
 880         /* flush all outstanding writes */
 881         mmiowb();
 882
 883         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 884         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 885                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 886 }
 887
 888 static void bnx2x_int_disable(struct bnx2x *bp)
 889 {
 890         if (bp->common.int_block == INT_BLOCK_HC)
 891                 bnx2x_hc_int_disable(bp);
 892         else
 893                 bnx2x_igu_int_disable(bp);
 894 }
 895
 896 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 897 {
 898         int i;
 899         u16 j;
 900         struct hc_sp_status_block_data sp_sb_data;
 901         int func = BP_FUNC(bp);
 902 #ifdef BNX2X_STOP_ON_ERROR
 903         u16 start = 0, end = 0;
 904         u8 cos;
 905 #endif
 906         if (IS_PF(bp) && disable_int)
 907                 bnx2x_int_disable(bp);
 908
 909         bp->stats_state = STATS_STATE_DISABLED;
 910         bp->eth_stats.unrecoverable_error++;
 911         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 912
 913         BNX2X_ERR("begin crash dump -----------------\n");
 914
 915         /* Indices */
 916         /* Common */
 917         if (IS_PF(bp)) {
 918                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 919                 int data_size, cstorm_offset;
 920
 921                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 922                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 923                           bp->spq_prod_idx, bp->stats_counter);
 924                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 925                           def_sb->atten_status_block.attn_bits,
 926                           def_sb->atten_status_block.attn_bits_ack,
 927                           def_sb->atten_status_block.status_block_id,
 928                           def_sb->atten_status_block.attn_bits_index);
 929                 BNX2X_ERR("     def (");
 930                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 931                         pr_cont("0x%x%s",
 932                                 def_sb->sp_sb.index_values[i],
 933                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 934
 935                 data_size = sizeof(struct hc_sp_status_block_data) /
 936                             sizeof(u32);
 937                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 938                 for (i = 0; i < data_size; i++)
 939                         *((u32 *)&sp_sb_data + i) =
 940                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 941                                            i * sizeof(u32));
 942
 943                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 944                         sp_sb_data.igu_sb_id,
 945                         sp_sb_data.igu_seg_id,
 946                         sp_sb_data.p_func.pf_id,
 947                         sp_sb_data.p_func.vnic_id,
 948                         sp_sb_data.p_func.vf_id,
 949                         sp_sb_data.p_func.vf_valid,
 950                         sp_sb_data.state);
 951         }
 952
 953         for_each_eth_queue(bp, i) {
 954                 struct bnx2x_fastpath *fp = &bp->fp[i];
 955                 int loop;
 956                 struct hc_status_block_data_e2 sb_data_e2;
 957                 struct hc_status_block_data_e1x sb_data_e1x;
 958                 struct hc_status_block_sm  *hc_sm_p =
 959                         CHIP_IS_E1x(bp) ?
 960                         sb_data_e1x.common.state_machine :
 961                         sb_data_e2.common.state_machine;
 962                 struct hc_index_data *hc_index_p =
 963                         CHIP_IS_E1x(bp) ?
 964                         sb_data_e1x.index_data :
 965                         sb_data_e2.index_data;
 966                 u8 data_size, cos;
 967                 u32 *sb_data_p;
 968                 struct bnx2x_fp_txdata txdata;
 969
 970                 if (!bp->fp)
 971                         break;
 972
 973                 if (!fp->rx_cons_sb)
 974                         continue;
 975
 976                 /* Rx */
 977                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 978                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 979                           fp->rx_comp_prod,
 980                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 981                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 982                           fp->rx_sge_prod, fp->last_max_sge,
 983                           le16_to_cpu(fp->fp_hc_idx));
 984
 985                 /* Tx */
 986                 for_each_cos_in_tx_queue(fp, cos)
 987                 {
 988                         if (!fp->txdata_ptr[cos])
 989                                 break;
 990
 991                         txdata = *fp->txdata_ptr[cos];
 992
 993                         if (!txdata.tx_cons_sb)
 994                                 continue;
 995
 996                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 997                                   i, txdata.tx_pkt_prod,
 998                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 999                                   txdata.tx_bd_cons,
1000                                   le16_to_cpu(*txdata.tx_cons_sb));
1001                 }
1002
1003                 loop = CHIP_IS_E1x(bp) ?
1004                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1005
1006                 /* host sb data */
1007
1008                 if (IS_FCOE_FP(fp))
1009                         continue;
1010
1011                 BNX2X_ERR("     run indexes (");
1012                 for (j = 0; j < HC_SB_MAX_SM; j++)
1013                         pr_cont("0x%x%s",
1014                                fp->sb_running_index[j],
1015                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1016
1017                 BNX2X_ERR("     indexes (");
1018                 for (j = 0; j < loop; j++)
1019                         pr_cont("0x%x%s",
1020                                fp->sb_index_values[j],
1021                                (j == loop - 1) ? ")" : " ");
1022
1023                 /* VF cannot access FW refelection for status block */
1024                 if (IS_VF(bp))
1025                         continue;
1026
1027                 /* fw sb data */
1028                 data_size = CHIP_IS_E1x(bp) ?
1029                         sizeof(struct hc_status_block_data_e1x) :
1030                         sizeof(struct hc_status_block_data_e2);
1031                 data_size /= sizeof(u32);
1032                 sb_data_p = CHIP_IS_E1x(bp) ?
1033                         (u32 *)&sb_data_e1x :
1034                         (u32 *)&sb_data_e2;
1035                 /* copy sb data in here */
1036                 for (j = 0; j < data_size; j++)
1037                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1038                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1039                                 j * sizeof(u32));
1040
1041                 if (!CHIP_IS_E1x(bp)) {
1042                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1043                                 sb_data_e2.common.p_func.pf_id,
1044                                 sb_data_e2.common.p_func.vf_id,
1045                                 sb_data_e2.common.p_func.vf_valid,
1046                                 sb_data_e2.common.p_func.vnic_id,
1047                                 sb_data_e2.common.same_igu_sb_1b,
1048                                 sb_data_e2.common.state);
1049                 } else {
1050                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1051                                 sb_data_e1x.common.p_func.pf_id,
1052                                 sb_data_e1x.common.p_func.vf_id,
1053                                 sb_data_e1x.common.p_func.vf_valid,
1054                                 sb_data_e1x.common.p_func.vnic_id,
1055                                 sb_data_e1x.common.same_igu_sb_1b,
1056                                 sb_data_e1x.common.state);
1057                 }
1058
1059                 /* SB_SMs data */
1060                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1061                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1062                                 j, hc_sm_p[j].__flags,
1063                                 hc_sm_p[j].igu_sb_id,
1064                                 hc_sm_p[j].igu_seg_id,
1065                                 hc_sm_p[j].time_to_expire,
1066                                 hc_sm_p[j].timer_value);
1067                 }
1068
1069                 /* Indices data */
1070                 for (j = 0; j < loop; j++) {
1071                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1072                                hc_index_p[j].flags,
1073                                hc_index_p[j].timeout);
1074                 }
1075         }
1076
1077 #ifdef BNX2X_STOP_ON_ERROR
1078         if (IS_PF(bp)) {
1079                 /* event queue */
1080                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1081                 for (i = 0; i < NUM_EQ_DESC; i++) {
1082                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1083
1084                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1085                                   i, bp->eq_ring[i].message.opcode,
1086                                   bp->eq_ring[i].message.error);
1087                         BNX2X_ERR("data: %x %x %x\n",
1088                                   data[0], data[1], data[2]);
1089                 }
1090         }
1091
1092         /* Rings */
1093         /* Rx */
1094         for_each_valid_rx_queue(bp, i) {
1095                 struct bnx2x_fastpath *fp = &bp->fp[i];
1096
1097                 if (!bp->fp)
1098                         break;
1099
1100                 if (!fp->rx_cons_sb)
1101                         continue;
1102
1103                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1104                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1105                 for (j = start; j != end; j = RX_BD(j + 1)) {
1106                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1107                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1108
1109                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1110                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1111                 }
1112
1113                 start = RX_SGE(fp->rx_sge_prod);
1114                 end = RX_SGE(fp->last_max_sge);
1115                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1116                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1117                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1118
1119                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1120                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1121                 }
1122
1123                 start = RCQ_BD(fp->rx_comp_cons - 10);
1124                 end = RCQ_BD(fp->rx_comp_cons + 503);
1125                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1126                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1127
1128                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1129                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1130                 }
1131         }
1132
1133         /* Tx */
1134         for_each_valid_tx_queue(bp, i) {
1135                 struct bnx2x_fastpath *fp = &bp->fp[i];
1136
1137                 if (!bp->fp)
1138                         break;
1139
1140                 for_each_cos_in_tx_queue(fp, cos) {
1141                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1142
1143                         if (!fp->txdata_ptr[cos])
1144                                 break;
1145
1146                         if (!txdata->tx_cons_sb)
1147                                 continue;
1148
1149                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1150                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1151                         for (j = start; j != end; j = TX_BD(j + 1)) {
1152                                 struct sw_tx_bd *sw_bd =
1153                                         &txdata->tx_buf_ring[j];
1154
1155                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1156                                           i, cos, j, sw_bd->skb,
1157                                           sw_bd->first_bd);
1158                         }
1159
1160                         start = TX_BD(txdata->tx_bd_cons - 10);
1161                         end = TX_BD(txdata->tx_bd_cons + 254);
1162                         for (j = start; j != end; j = TX_BD(j + 1)) {
1163                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1164
1165                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1166                                           i, cos, j, tx_bd[0], tx_bd[1],
1167                                           tx_bd[2], tx_bd[3]);
1168                         }
1169                 }
1170         }
1171 #endif
1172         if (IS_PF(bp)) {
1173                 bnx2x_fw_dump(bp);
1174                 bnx2x_mc_assert(bp);
1175         }
1176         BNX2X_ERR("end crash dump -----------------\n");
1177 }
1178
1179 /*
1180  * FLR Support for E2
1181  *
1182  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1183  * initialization.
1184  */
1185 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1186 #define FLR_WAIT_INTERVAL       50      /* usec */
1187 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1188
1189 struct pbf_pN_buf_regs {
1190         int pN;
1191         u32 init_crd;
1192         u32 crd;
1193         u32 crd_freed;
1194 };
1195
1196 struct pbf_pN_cmd_regs {
1197         int pN;
1198         u32 lines_occup;
1199         u32 lines_freed;
1200 };
1201
1202 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1203                                      struct pbf_pN_buf_regs *regs,
1204                                      u32 poll_count)
1205 {
1206         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1207         u32 cur_cnt = poll_count;
1208
1209         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1210         crd = crd_start = REG_RD(bp, regs->crd);
1211         init_crd = REG_RD(bp, regs->init_crd);
1212
1213         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1214         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1215         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1216
1217         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1218                (init_crd - crd_start))) {
1219                 if (cur_cnt--) {
1220                         udelay(FLR_WAIT_INTERVAL);
1221                         crd = REG_RD(bp, regs->crd);
1222                         crd_freed = REG_RD(bp, regs->crd_freed);
1223                 } else {
1224                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1225                            regs->pN);
1226                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1227                            regs->pN, crd);
1228                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1229                            regs->pN, crd_freed);
1230                         break;
1231                 }
1232         }
1233         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1234            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1235 }
1236
1237 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1238                                      struct pbf_pN_cmd_regs *regs,
1239                                      u32 poll_count)
1240 {
1241         u32 occup, to_free, freed, freed_start;
1242         u32 cur_cnt = poll_count;
1243
1244         occup = to_free = REG_RD(bp, regs->lines_occup);
1245         freed = freed_start = REG_RD(bp, regs->lines_freed);
1246
1247         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1248         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1249
1250         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1251                 if (cur_cnt--) {
1252                         udelay(FLR_WAIT_INTERVAL);
1253                         occup = REG_RD(bp, regs->lines_occup);
1254                         freed = REG_RD(bp, regs->lines_freed);
1255                 } else {
1256                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1257                            regs->pN);
1258                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1259                            regs->pN, occup);
1260                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1261                            regs->pN, freed);
1262                         break;
1263                 }
1264         }
1265         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1266            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1267 }
1268
1269 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1270                                     u32 expected, u32 poll_count)
1271 {
1272         u32 cur_cnt = poll_count;
1273         u32 val;
1274
1275         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1276                 udelay(FLR_WAIT_INTERVAL);
1277
1278         return val;
1279 }
1280
1281 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1282                                     char *msg, u32 poll_cnt)
1283 {
1284         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1285         if (val != 0) {
1286                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1287                 return 1;
1288         }
1289         return 0;
1290 }
1291
1292 /* Common routines with VF FLR cleanup */
1293 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1294 {
1295         /* adjust polling timeout */
1296         if (CHIP_REV_IS_EMUL(bp))
1297                 return FLR_POLL_CNT * 2000;
1298
1299         if (CHIP_REV_IS_FPGA(bp))
1300                 return FLR_POLL_CNT * 120;
1301
1302         return FLR_POLL_CNT;
1303 }
1304
1305 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1306 {
1307         struct pbf_pN_cmd_regs cmd_regs[] = {
1308                 {0, (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_TQ_OCCUPANCY_Q0 :
1310                         PBF_REG_P0_TQ_OCCUPANCY,
1311                     (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1313                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1314                 {1, (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_OCCUPANCY_Q1 :
1316                         PBF_REG_P1_TQ_OCCUPANCY,
1317                     (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1319                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1320                 {4, (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1322                         PBF_REG_P4_TQ_OCCUPANCY,
1323                     (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1325                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1326         };
1327
1328         struct pbf_pN_buf_regs buf_regs[] = {
1329                 {0, (CHIP_IS_E3B0(bp)) ?
1330                         PBF_REG_INIT_CRD_Q0 :
1331                         PBF_REG_P0_INIT_CRD ,
1332                     (CHIP_IS_E3B0(bp)) ?
1333                         PBF_REG_CREDIT_Q0 :
1334                         PBF_REG_P0_CREDIT,
1335                     (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1337                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1338                 {1, (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_INIT_CRD_Q1 :
1340                         PBF_REG_P1_INIT_CRD,
1341                     (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_CREDIT_Q1 :
1343                         PBF_REG_P1_CREDIT,
1344                     (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1346                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1347                 {4, (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_INIT_CRD_LB_Q :
1349                         PBF_REG_P4_INIT_CRD,
1350                     (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_CREDIT_LB_Q :
1352                         PBF_REG_P4_CREDIT,
1353                     (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1355                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1356         };
1357
1358         int i;
1359
1360         /* Verify the command queues are flushed P0, P1, P4 */
1361         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1362                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1363
1364         /* Verify the transmission buffers are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1366                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1367 }
1368
1369 #define OP_GEN_PARAM(param) \
1370         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1371
1372 #define OP_GEN_TYPE(type) \
1373         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1374
1375 #define OP_GEN_AGG_VECT(index) \
1376         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1377
1378 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1379 {
1380         u32 op_gen_command = 0;
1381         u32 comp_addr = BAR_CSTRORM_INTMEM +
1382                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1383         int ret = 0;
1384
1385         if (REG_RD(bp, comp_addr)) {
1386                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1387                 return 1;
1388         }
1389
1390         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1391         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1392         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1393         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1394
1395         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1396         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1397
1398         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1399                 BNX2X_ERR("FW final cleanup did not succeed\n");
1400                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1401                    (REG_RD(bp, comp_addr)));
1402                 bnx2x_panic();
1403                 return 1;
1404         }
1405         /* Zero completion for next FLR */
1406         REG_WR(bp, comp_addr, 0);
1407
1408         return ret;
1409 }
1410
1411 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1412 {
1413         u16 status;
1414
1415         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1416         return status & PCI_EXP_DEVSTA_TRPND;
1417 }
1418
1419 /* PF FLR specific routines
1420 */
1421 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1422 {
1423         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1424         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1426                         "CFC PF usage counter timed out",
1427                         poll_cnt))
1428                 return 1;
1429
1430         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1431         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432                         DORQ_REG_PF_USAGE_CNT,
1433                         "DQ PF usage counter timed out",
1434                         poll_cnt))
1435                 return 1;
1436
1437         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1438         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1439                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1440                         "QM PF usage counter timed out",
1441                         poll_cnt))
1442                 return 1;
1443
1444         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1445         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1447                         "Timers VNIC usage counter timed out",
1448                         poll_cnt))
1449                 return 1;
1450         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1451                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1452                         "Timers NUM_SCANS usage counter timed out",
1453                         poll_cnt))
1454                 return 1;
1455
1456         /* Wait DMAE PF usage counter to zero */
1457         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1458                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1459                         "DMAE command register timed out",
1460                         poll_cnt))
1461                 return 1;
1462
1463         return 0;
1464 }
1465
1466 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1467 {
1468         u32 val;
1469
1470         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1471         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1472
1473         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1474         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1475
1476         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1477         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1478
1479         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1480         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1481
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1484
1485         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1486         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1487
1488         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1489         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1490
1491         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1493            val);
1494 }
1495
1496 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1497 {
1498         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1499
1500         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1501
1502         /* Re-enable PF target read access */
1503         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1504
1505         /* Poll HW usage counters */
1506         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1507         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1508                 return -EBUSY;
1509
1510         /* Zero the igu 'trailing edge' and 'leading edge' */
1511
1512         /* Send the FW cleanup command */
1513         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1514                 return -EBUSY;
1515
1516         /* ATC cleanup */
1517
1518         /* Verify TX hw is flushed */
1519         bnx2x_tx_hw_flushed(bp, poll_cnt);
1520
1521         /* Wait 100ms (not adjusted according to platform) */
1522         msleep(100);
1523
1524         /* Verify no pending pci transactions */
1525         if (bnx2x_is_pcie_pending(bp->pdev))
1526                 BNX2X_ERR("PCIE Transactions still pending\n");
1527
1528         /* Debug */
1529         bnx2x_hw_enable_status(bp);
1530
1531         /*
1532          * Master enable - Due to WB DMAE writes performed before this
1533          * register is re-initialized as part of the regular function init
1534          */
1535         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1536
1537         return 0;
1538 }
1539
1540 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1541 {
1542         int port = BP_PORT(bp);
1543         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1544         u32 val = REG_RD(bp, addr);
1545         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1546         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1547         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1548
1549         if (msix) {
1550                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1551                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1552                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1553                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1554                 if (single_msix)
1555                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1556         } else if (msi) {
1557                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1558                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1560                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561         } else {
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1565                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1566
1567                 if (!CHIP_IS_E1(bp)) {
1568                         DP(NETIF_MSG_IFUP,
1569                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1570
1571                         REG_WR(bp, addr, val);
1572
1573                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1574                 }
1575         }
1576
1577         if (CHIP_IS_E1(bp))
1578                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1579
1580         DP(NETIF_MSG_IFUP,
1581            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1582            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1583
1584         REG_WR(bp, addr, val);
1585         /*
1586          * Ensure that HC_CONFIG is written before leading/trailing edge config
1587          */
1588         mmiowb();
1589         barrier();
1590
1591         if (!CHIP_IS_E1(bp)) {
1592                 /* init leading/trailing edge */
1593                 if (IS_MF(bp)) {
1594                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1595                         if (bp->port.pmf)
1596                                 /* enable nig and gpio3 attention */
1597                                 val |= 0x1100;
1598                 } else
1599                         val = 0xffff;
1600
1601                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1602                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1603         }
1604
1605         /* Make sure that interrupts are indeed enabled from here on */
1606         mmiowb();
1607 }
1608
1609 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610 {
1611         u32 val;
1612         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1615
1616         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617
1618         if (msix) {
1619                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620                          IGU_PF_CONF_SINGLE_ISR_EN);
1621                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1622                         IGU_PF_CONF_ATTN_BIT_EN);
1623
1624                 if (single_msix)
1625                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1626         } else if (msi) {
1627                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1628                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1629                         IGU_PF_CONF_ATTN_BIT_EN |
1630                         IGU_PF_CONF_SINGLE_ISR_EN);
1631         } else {
1632                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1633                 val |= (IGU_PF_CONF_INT_LINE_EN |
1634                         IGU_PF_CONF_ATTN_BIT_EN |
1635                         IGU_PF_CONF_SINGLE_ISR_EN);
1636         }
1637
1638         /* Clean previous status - need to configure igu prior to ack*/
1639         if ((!msix) || single_msix) {
1640                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641                 bnx2x_ack_int(bp);
1642         }
1643
1644         val |= IGU_PF_CONF_FUNC_EN;
1645
1646         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1647            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648
1649         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650
1651         if (val & IGU_PF_CONF_INT_LINE_EN)
1652                 pci_intx(bp->pdev, true);
1653
1654         barrier();
1655
1656         /* init leading/trailing edge */
1657         if (IS_MF(bp)) {
1658                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1659                 if (bp->port.pmf)
1660                         /* enable nig and gpio3 attention */
1661                         val |= 0x1100;
1662         } else
1663                 val = 0xffff;
1664
1665         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667
1668         /* Make sure that interrupts are indeed enabled from here on */
1669         mmiowb();
1670 }
1671
1672 void bnx2x_int_enable(struct bnx2x *bp)
1673 {
1674         if (bp->common.int_block == INT_BLOCK_HC)
1675                 bnx2x_hc_int_enable(bp);
1676         else
1677                 bnx2x_igu_int_enable(bp);
1678 }
1679
1680 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1681 {
1682         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1683         int i, offset;
1684
1685         if (disable_hw)
1686                 /* prevent the HW from sending interrupts */
1687                 bnx2x_int_disable(bp);
1688
1689         /* make sure all ISRs are done */
1690         if (msix) {
1691                 synchronize_irq(bp->msix_table[0].vector);
1692                 offset = 1;
1693                 if (CNIC_SUPPORT(bp))
1694                         offset++;
1695                 for_each_eth_queue(bp, i)
1696                         synchronize_irq(bp->msix_table[offset++].vector);
1697         } else
1698                 synchronize_irq(bp->pdev->irq);
1699
1700         /* make sure sp_task is not running */
1701         cancel_delayed_work(&bp->sp_task);
1702         cancel_delayed_work(&bp->period_task);
1703         flush_workqueue(bnx2x_wq);
1704 }
1705
1706 /* fast path */
1707
1708 /*
1709  * General service functions
1710  */
1711
1712 /* Return true if succeeded to acquire the lock */
1713 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1714 {
1715         u32 lock_status;
1716         u32 resource_bit = (1 << resource);
1717         int func = BP_FUNC(bp);
1718         u32 hw_lock_control_reg;
1719
1720         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721            "Trying to take a lock on resource %d\n", resource);
1722
1723         /* Validating that the resource is within range */
1724         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1725                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1726                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1727                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1728                 return false;
1729         }
1730
1731         if (func <= 5)
1732                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1733         else
1734                 hw_lock_control_reg =
1735                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1736
1737         /* Try to acquire the lock */
1738         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1739         lock_status = REG_RD(bp, hw_lock_control_reg);
1740         if (lock_status & resource_bit)
1741                 return true;
1742
1743         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744            "Failed to get a lock on resource %d\n", resource);
1745         return false;
1746 }
1747
1748 /**
1749  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1750  *
1751  * @bp: driver handle
1752  *
1753  * Returns the recovery leader resource id according to the engine this function
1754  * belongs to. Currently only only 2 engines is supported.
1755  */
1756 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1757 {
1758         if (BP_PATH(bp))
1759                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1760         else
1761                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1762 }
1763
1764 /**
1765  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1766  *
1767  * @bp: driver handle
1768  *
1769  * Tries to acquire a leader lock for current engine.
1770  */
1771 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1772 {
1773         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1774 }
1775
1776 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1777
1778 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1779 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1780 {
1781         /* Set the interrupt occurred bit for the sp-task to recognize it
1782          * must ack the interrupt and transition according to the IGU
1783          * state machine.
1784          */
1785         atomic_set(&bp->interrupt_occurred, 1);
1786
1787         /* The sp_task must execute only after this bit
1788          * is set, otherwise we will get out of sync and miss all
1789          * further interrupts. Hence, the barrier.
1790          */
1791         smp_wmb();
1792
1793         /* schedule sp_task to workqueue */
1794         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795 }
1796
1797 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1798 {
1799         struct bnx2x *bp = fp->bp;
1800         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1803         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1804
1805         DP(BNX2X_MSG_SP,
1806            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1807            fp->index, cid, command, bp->state,
1808            rr_cqe->ramrod_cqe.ramrod_type);
1809
1810         /* If cid is within VF range, replace the slowpath object with the
1811          * one corresponding to this VF
1812          */
1813         if (cid >= BNX2X_FIRST_VF_CID  &&
1814             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1815                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1816
1817         switch (command) {
1818         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1819                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1820                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1821                 break;
1822
1823         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1824                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1825                 drv_cmd = BNX2X_Q_CMD_SETUP;
1826                 break;
1827
1828         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1829                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1831                 break;
1832
1833         case (RAMROD_CMD_ID_ETH_HALT):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_HALT;
1836                 break;
1837
1838         case (RAMROD_CMD_ID_ETH_TERMINATE):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1841                 break;
1842
1843         case (RAMROD_CMD_ID_ETH_EMPTY):
1844                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1846                 break;
1847
1848         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1849                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1850                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1851                 break;
1852
1853         default:
1854                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1855                           command, fp->index);
1856                 return;
1857         }
1858
1859         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1860             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1861                 /* q_obj->complete_cmd() failure means that this was
1862                  * an unexpected completion.
1863                  *
1864                  * In this case we don't want to increase the bp->spq_left
1865                  * because apparently we haven't sent this command the first
1866                  * place.
1867                  */
1868 #ifdef BNX2X_STOP_ON_ERROR
1869                 bnx2x_panic();
1870 #else
1871                 return;
1872 #endif
1873
1874         smp_mb__before_atomic();
1875         atomic_inc(&bp->cq_spq_left);
1876         /* push the change in bp->spq_left and towards the memory */
1877         smp_mb__after_atomic();
1878
1879         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1880
1881         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1882             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1883                 /* if Q update ramrod is completed for last Q in AFEX vif set
1884                  * flow, then ACK MCP at the end
1885                  *
1886                  * mark pending ACK to MCP bit.
1887                  * prevent case that both bits are cleared.
1888                  * At the end of load/unload driver checks that
1889                  * sp_state is cleared, and this order prevents
1890                  * races
1891                  */
1892                 smp_mb__before_atomic();
1893                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1894                 wmb();
1895                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1896                 smp_mb__after_atomic();
1897
1898                 /* schedule the sp task as mcp ack is required */
1899                 bnx2x_schedule_sp_task(bp);
1900         }
1901
1902         return;
1903 }
1904
1905 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1906 {
1907         struct bnx2x *bp = netdev_priv(dev_instance);
1908         u16 status = bnx2x_ack_int(bp);
1909         u16 mask;
1910         int i;
1911         u8 cos;
1912
1913         /* Return here if interrupt is shared and it's not for us */
1914         if (unlikely(status == 0)) {
1915                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1916                 return IRQ_NONE;
1917         }
1918         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1919
1920 #ifdef BNX2X_STOP_ON_ERROR
1921         if (unlikely(bp->panic))
1922                 return IRQ_HANDLED;
1923 #endif
1924
1925         for_each_eth_queue(bp, i) {
1926                 struct bnx2x_fastpath *fp = &bp->fp[i];
1927
1928                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1929                 if (status & mask) {
1930                         /* Handle Rx or Tx according to SB id */
1931                         for_each_cos_in_tx_queue(fp, cos)
1932                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1933                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1934                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1935                         status &= ~mask;
1936                 }
1937         }
1938
1939         if (CNIC_SUPPORT(bp)) {
1940                 mask = 0x2;
1941                 if (status & (mask | 0x1)) {
1942                         struct cnic_ops *c_ops = NULL;
1943
1944                         rcu_read_lock();
1945                         c_ops = rcu_dereference(bp->cnic_ops);
1946                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1947                                       CNIC_DRV_STATE_HANDLES_IRQ))
1948                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1949                         rcu_read_unlock();
1950
1951                         status &= ~mask;
1952                 }
1953         }
1954
1955         if (unlikely(status & 0x1)) {
1956
1957                 /* schedule sp task to perform default status block work, ack
1958                  * attentions and enable interrupts.
1959                  */
1960                 bnx2x_schedule_sp_task(bp);
1961
1962                 status &= ~0x1;
1963                 if (!status)
1964                         return IRQ_HANDLED;
1965         }
1966
1967         if (unlikely(status))
1968                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1969                    status);
1970
1971         return IRQ_HANDLED;
1972 }
1973
1974 /* Link */
1975
1976 /*
1977  * General service functions
1978  */
1979
1980 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1981 {
1982         u32 lock_status;
1983         u32 resource_bit = (1 << resource);
1984         int func = BP_FUNC(bp);
1985         u32 hw_lock_control_reg;
1986         int cnt;
1987
1988         /* Validating that the resource is within range */
1989         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1990                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1991                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992                 return -EINVAL;
1993         }
1994
1995         if (func <= 5) {
1996                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997         } else {
1998                 hw_lock_control_reg =
1999                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000         }
2001
2002         /* Validating that the resource is not already taken */
2003         lock_status = REG_RD(bp, hw_lock_control_reg);
2004         if (lock_status & resource_bit) {
2005                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2006                    lock_status, resource_bit);
2007                 return -EEXIST;
2008         }
2009
2010         /* Try for 5 second every 5ms */
2011         for (cnt = 0; cnt < 1000; cnt++) {
2012                 /* Try to acquire the lock */
2013                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2014                 lock_status = REG_RD(bp, hw_lock_control_reg);
2015                 if (lock_status & resource_bit)
2016                         return 0;
2017
2018                 usleep_range(5000, 10000);
2019         }
2020         BNX2X_ERR("Timeout\n");
2021         return -EAGAIN;
2022 }
2023
2024 int bnx2x_release_leader_lock(struct bnx2x *bp)
2025 {
2026         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2027 }
2028
2029 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2030 {
2031         u32 lock_status;
2032         u32 resource_bit = (1 << resource);
2033         int func = BP_FUNC(bp);
2034         u32 hw_lock_control_reg;
2035
2036         /* Validating that the resource is within range */
2037         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2038                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2039                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2040                 return -EINVAL;
2041         }
2042
2043         if (func <= 5) {
2044                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2045         } else {
2046                 hw_lock_control_reg =
2047                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2048         }
2049
2050         /* Validating that the resource is currently taken */
2051         lock_status = REG_RD(bp, hw_lock_control_reg);
2052         if (!(lock_status & resource_bit)) {
2053                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2054                           lock_status, resource_bit);
2055                 return -EFAULT;
2056         }
2057
2058         REG_WR(bp, hw_lock_control_reg, resource_bit);
2059         return 0;
2060 }
2061
2062 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2063 {
2064         /* The GPIO should be swapped if swap register is set and active */
2065         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2066                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2067         int gpio_shift = gpio_num +
2068                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2069         u32 gpio_mask = (1 << gpio_shift);
2070         u32 gpio_reg;
2071         int value;
2072
2073         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2074                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2075                 return -EINVAL;
2076         }
2077
2078         /* read GPIO value */
2079         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080
2081         /* get the requested pin value */
2082         if ((gpio_reg & gpio_mask) == gpio_mask)
2083                 value = 1;
2084         else
2085                 value = 0;
2086
2087         return value;
2088 }
2089
2090 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2091 {
2092         /* The GPIO should be swapped if swap register is set and active */
2093         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2094                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2095         int gpio_shift = gpio_num +
2096                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2097         u32 gpio_mask = (1 << gpio_shift);
2098         u32 gpio_reg;
2099
2100         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2101                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2102                 return -EINVAL;
2103         }
2104
2105         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2106         /* read GPIO and mask except the float bits */
2107         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2108
2109         switch (mode) {
2110         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2111                 DP(NETIF_MSG_LINK,
2112                    "Set GPIO %d (shift %d) -> output low\n",
2113                    gpio_num, gpio_shift);
2114                 /* clear FLOAT and set CLR */
2115                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2116                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2117                 break;
2118
2119         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2120                 DP(NETIF_MSG_LINK,
2121                    "Set GPIO %d (shift %d) -> output high\n",
2122                    gpio_num, gpio_shift);
2123                 /* clear FLOAT and set SET */
2124                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2125                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2126                 break;
2127
2128         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2129                 DP(NETIF_MSG_LINK,
2130                    "Set GPIO %d (shift %d) -> input\n",
2131                    gpio_num, gpio_shift);
2132                 /* set FLOAT */
2133                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134                 break;
2135
2136         default:
2137                 break;
2138         }
2139
2140         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2141         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2142
2143         return 0;
2144 }
2145
2146 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2147 {
2148         u32 gpio_reg = 0;
2149         int rc = 0;
2150
2151         /* Any port swapping should be handled by caller. */
2152
2153         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154         /* read GPIO and mask except the float bits */
2155         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2156         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2159
2160         switch (mode) {
2161         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2162                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2163                 /* set CLR */
2164                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2165                 break;
2166
2167         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2168                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2169                 /* set SET */
2170                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2171                 break;
2172
2173         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2174                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2175                 /* set FLOAT */
2176                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177                 break;
2178
2179         default:
2180                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2181                 rc = -EINVAL;
2182                 break;
2183         }
2184
2185         if (rc == 0)
2186                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2187
2188         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2189
2190         return rc;
2191 }
2192
2193 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2194 {
2195         /* The GPIO should be swapped if swap register is set and active */
2196         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2197                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2198         int gpio_shift = gpio_num +
2199                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2200         u32 gpio_mask = (1 << gpio_shift);
2201         u32 gpio_reg;
2202
2203         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2204                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2205                 return -EINVAL;
2206         }
2207
2208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209         /* read GPIO int */
2210         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2211
2212         switch (mode) {
2213         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2214                 DP(NETIF_MSG_LINK,
2215                    "Clear GPIO INT %d (shift %d) -> output low\n",
2216                    gpio_num, gpio_shift);
2217                 /* clear SET and set CLR */
2218                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2220                 break;
2221
2222         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2223                 DP(NETIF_MSG_LINK,
2224                    "Set GPIO INT %d (shift %d) -> output high\n",
2225                    gpio_num, gpio_shift);
2226                 /* clear CLR and set SET */
2227                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229                 break;
2230
2231         default:
2232                 break;
2233         }
2234
2235         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2236         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2237
2238         return 0;
2239 }
2240
2241 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2242 {
2243         u32 spio_reg;
2244
2245         /* Only 2 SPIOs are configurable */
2246         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2247                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2248                 return -EINVAL;
2249         }
2250
2251         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2252         /* read SPIO and mask except the float bits */
2253         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2254
2255         switch (mode) {
2256         case MISC_SPIO_OUTPUT_LOW:
2257                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2258                 /* clear FLOAT and set CLR */
2259                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2261                 break;
2262
2263         case MISC_SPIO_OUTPUT_HIGH:
2264                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2265                 /* clear FLOAT and set SET */
2266                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2267                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2268                 break;
2269
2270         case MISC_SPIO_INPUT_HI_Z:
2271                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2272                 /* set FLOAT */
2273                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2274                 break;
2275
2276         default:
2277                 break;
2278         }
2279
2280         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2281         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2282
2283         return 0;
2284 }
2285
2286 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2287 {
2288         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2289
2290         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2291                                            ADVERTISED_Pause);
2292         switch (bp->link_vars.ieee_fc &
2293                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2294         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2295                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2296                                                   ADVERTISED_Pause);
2297                 break;
2298
2299         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2300                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2301                 break;
2302
2303         default:
2304                 break;
2305         }
2306 }
2307
2308 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2309 {
2310         /* Initialize link parameters structure variables
2311          * It is recommended to turn off RX FC for jumbo frames
2312          *  for better performance
2313          */
2314         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2315                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2316         else
2317                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2318 }
2319
2320 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2321 {
2322         u32 pause_enabled = 0;
2323
2324         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2325                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2326                         pause_enabled = 1;
2327
2328                 REG_WR(bp, BAR_USTRORM_INTMEM +
2329                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2330                        pause_enabled);
2331         }
2332
2333         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2334            pause_enabled ? "enabled" : "disabled");
2335 }
2336
2337 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2338 {
2339         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2340         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2341
2342         if (!BP_NOMCP(bp)) {
2343                 bnx2x_set_requested_fc(bp);
2344                 bnx2x_acquire_phy_lock(bp);
2345
2346                 if (load_mode == LOAD_DIAG) {
2347                         struct link_params *lp = &bp->link_params;
2348                         lp->loopback_mode = LOOPBACK_XGXS;
2349                         /* Prefer doing PHY loopback at highest speed */
2350                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2351                                 if (lp->speed_cap_mask[cfx_idx] &
2352                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2353                                         lp->req_line_speed[cfx_idx] =
2354                                         SPEED_20000;
2355                                 else if (lp->speed_cap_mask[cfx_idx] &
2356                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2357                                                 lp->req_line_speed[cfx_idx] =
2358                                                 SPEED_10000;
2359                                 else
2360                                         lp->req_line_speed[cfx_idx] =
2361                                         SPEED_1000;
2362                         }
2363                 }
2364
2365                 if (load_mode == LOAD_LOOPBACK_EXT) {
2366                         struct link_params *lp = &bp->link_params;
2367                         lp->loopback_mode = LOOPBACK_EXT;
2368                 }
2369
2370                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2371
2372                 bnx2x_release_phy_lock(bp);
2373
2374                 bnx2x_init_dropless_fc(bp);
2375
2376                 bnx2x_calc_fc_adv(bp);
2377
2378                 if (bp->link_vars.link_up) {
2379                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2380                         bnx2x_link_report(bp);
2381                 }
2382                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2383                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2384                 return rc;
2385         }
2386         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2387         return -EINVAL;
2388 }
2389
2390 void bnx2x_link_set(struct bnx2x *bp)
2391 {
2392         if (!BP_NOMCP(bp)) {
2393                 bnx2x_acquire_phy_lock(bp);
2394                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2395                 bnx2x_release_phy_lock(bp);
2396
2397                 bnx2x_init_dropless_fc(bp);
2398
2399                 bnx2x_calc_fc_adv(bp);
2400         } else
2401                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2402 }
2403
2404 static void bnx2x__link_reset(struct bnx2x *bp)
2405 {
2406         if (!BP_NOMCP(bp)) {
2407                 bnx2x_acquire_phy_lock(bp);
2408                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2409                 bnx2x_release_phy_lock(bp);
2410         } else
2411                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2412 }
2413
2414 void bnx2x_force_link_reset(struct bnx2x *bp)
2415 {
2416         bnx2x_acquire_phy_lock(bp);
2417         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2418         bnx2x_release_phy_lock(bp);
2419 }
2420
2421 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2422 {
2423         u8 rc = 0;
2424
2425         if (!BP_NOMCP(bp)) {
2426                 bnx2x_acquire_phy_lock(bp);
2427                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2428                                      is_serdes);
2429                 bnx2x_release_phy_lock(bp);
2430         } else
2431                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2432
2433         return rc;
2434 }
2435
2436 /* Calculates the sum of vn_min_rates.
2437    It's needed for further normalizing of the min_rates.
2438    Returns:
2439      sum of vn_min_rates.
2440        or
2441      0 - if all the min_rates are 0.
2442      In the later case fairness algorithm should be deactivated.
2443      If not all min_rates are zero then those that are zeroes will be set to 1.
2444  */
2445 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2446                                       struct cmng_init_input *input)
2447 {
2448         int all_zero = 1;
2449         int vn;
2450
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 u32 vn_cfg = bp->mf_config[vn];
2453                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2454                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2455
2456                 /* Skip hidden vns */
2457                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2458                         vn_min_rate = 0;
2459                 /* If min rate is zero - set it to 1 */
2460                 else if (!vn_min_rate)
2461                         vn_min_rate = DEF_MIN_RATE;
2462                 else
2463                         all_zero = 0;
2464
2465                 input->vnic_min_rate[vn] = vn_min_rate;
2466         }
2467
2468         /* if ETS or all min rates are zeros - disable fairness */
2469         if (BNX2X_IS_ETS_ENABLED(bp)) {
2470                 input->flags.cmng_enables &=
2471                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2472                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2473         } else if (all_zero) {
2474                 input->flags.cmng_enables &=
2475                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476                 DP(NETIF_MSG_IFUP,
2477                    "All MIN values are zeroes fairness will be disabled\n");
2478         } else
2479                 input->flags.cmng_enables |=
2480                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2481 }
2482
2483 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2484                                     struct cmng_init_input *input)
2485 {
2486         u16 vn_max_rate;
2487         u32 vn_cfg = bp->mf_config[vn];
2488
2489         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2490                 vn_max_rate = 0;
2491         else {
2492                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2493
2494                 if (IS_MF_PERCENT_BW(bp)) {
2495                         /* maxCfg in percents of linkspeed */
2496                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2497                 } else /* SD modes */
2498                         /* maxCfg is absolute in 100Mb units */
2499                         vn_max_rate = maxCfg * 100;
2500         }
2501
2502         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2503
2504         input->vnic_max_rate[vn] = vn_max_rate;
2505 }
2506
2507 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2508 {
2509         if (CHIP_REV_IS_SLOW(bp))
2510                 return CMNG_FNS_NONE;
2511         if (IS_MF(bp))
2512                 return CMNG_FNS_MINMAX;
2513
2514         return CMNG_FNS_NONE;
2515 }
2516
2517 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2518 {
2519         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2520
2521         if (BP_NOMCP(bp))
2522                 return; /* what should be the default value in this case */
2523
2524         /* For 2 port configuration the absolute function number formula
2525          * is:
2526          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2527          *
2528          *      and there are 4 functions per port
2529          *
2530          * For 4 port configuration it is
2531          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2532          *
2533          *      and there are 2 functions per port
2534          */
2535         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2536                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2537
2538                 if (func >= E1H_FUNC_MAX)
2539                         break;
2540
2541                 bp->mf_config[vn] =
2542                         MF_CFG_RD(bp, func_mf_config[func].config);
2543         }
2544         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2545                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2546                 bp->flags |= MF_FUNC_DIS;
2547         } else {
2548                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2549                 bp->flags &= ~MF_FUNC_DIS;
2550         }
2551 }
2552
2553 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2554 {
2555         struct cmng_init_input input;
2556         memset(&input, 0, sizeof(struct cmng_init_input));
2557
2558         input.port_rate = bp->link_vars.line_speed;
2559
2560         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2561                 int vn;
2562
2563                 /* read mf conf from shmem */
2564                 if (read_cfg)
2565                         bnx2x_read_mf_cfg(bp);
2566
2567                 /* vn_weight_sum and enable fairness if not 0 */
2568                 bnx2x_calc_vn_min(bp, &input);
2569
2570                 /* calculate and set min-max rate for each vn */
2571                 if (bp->port.pmf)
2572                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2573                                 bnx2x_calc_vn_max(bp, vn, &input);
2574
2575                 /* always enable rate shaping and fairness */
2576                 input.flags.cmng_enables |=
2577                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2578
2579                 bnx2x_init_cmng(&input, &bp->cmng);
2580                 return;
2581         }
2582
2583         /* rate shaping and fairness are disabled */
2584         DP(NETIF_MSG_IFUP,
2585            "rate shaping and fairness are disabled\n");
2586 }
2587
2588 static void storm_memset_cmng(struct bnx2x *bp,
2589                               struct cmng_init *cmng,
2590                               u8 port)
2591 {
2592         int vn;
2593         size_t size = sizeof(struct cmng_struct_per_port);
2594
2595         u32 addr = BAR_XSTRORM_INTMEM +
2596                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2597
2598         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2599
2600         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2601                 int func = func_by_vn(bp, vn);
2602
2603                 addr = BAR_XSTRORM_INTMEM +
2604                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2605                 size = sizeof(struct rate_shaping_vars_per_vn);
2606                 __storm_memset_struct(bp, addr, size,
2607                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2608
2609                 addr = BAR_XSTRORM_INTMEM +
2610                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2611                 size = sizeof(struct fairness_vars_per_vn);
2612                 __storm_memset_struct(bp, addr, size,
2613                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614         }
2615 }
2616
2617 /* init cmng mode in HW according to local configuration */
2618 void bnx2x_set_local_cmng(struct bnx2x *bp)
2619 {
2620         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2621
2622         if (cmng_fns != CMNG_FNS_NONE) {
2623                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2624                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2625         } else {
2626                 /* rate shaping and fairness are disabled */
2627                 DP(NETIF_MSG_IFUP,
2628                    "single function mode without fairness\n");
2629         }
2630 }
2631
2632 /* This function is called upon link interrupt */
2633 static void bnx2x_link_attn(struct bnx2x *bp)
2634 {
2635         /* Make sure that we are synced with the current statistics */
2636         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2637
2638         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2639
2640         bnx2x_init_dropless_fc(bp);
2641
2642         if (bp->link_vars.link_up) {
2643
2644                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2645                         struct host_port_stats *pstats;
2646
2647                         pstats = bnx2x_sp(bp, port_stats);
2648                         /* reset old mac stats */
2649                         memset(&(pstats->mac_stx[0]), 0,
2650                                sizeof(struct mac_stx));
2651                 }
2652                 if (bp->state == BNX2X_STATE_OPEN)
2653                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2654         }
2655
2656         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2657                 bnx2x_set_local_cmng(bp);
2658
2659         __bnx2x_link_report(bp);
2660
2661         if (IS_MF(bp))
2662                 bnx2x_link_sync_notify(bp);
2663 }
2664
2665 void bnx2x__link_status_update(struct bnx2x *bp)
2666 {
2667         if (bp->state != BNX2X_STATE_OPEN)
2668                 return;
2669
2670         /* read updated dcb configuration */
2671         if (IS_PF(bp)) {
2672                 bnx2x_dcbx_pmf_update(bp);
2673                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2674                 if (bp->link_vars.link_up)
2675                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2676                 else
2677                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2678                         /* indicate link status */
2679                 bnx2x_link_report(bp);
2680
2681         } else { /* VF */
2682                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2683                                           SUPPORTED_10baseT_Full |
2684                                           SUPPORTED_100baseT_Half |
2685                                           SUPPORTED_100baseT_Full |
2686                                           SUPPORTED_1000baseT_Full |
2687                                           SUPPORTED_2500baseX_Full |
2688                                           SUPPORTED_10000baseT_Full |
2689                                           SUPPORTED_TP |
2690                                           SUPPORTED_FIBRE |
2691                                           SUPPORTED_Autoneg |
2692                                           SUPPORTED_Pause |
2693                                           SUPPORTED_Asym_Pause);
2694                 bp->port.advertising[0] = bp->port.supported[0];
2695
2696                 bp->link_params.bp = bp;
2697                 bp->link_params.port = BP_PORT(bp);
2698                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2699                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2700                 bp->link_params.req_line_speed[0] = SPEED_10000;
2701                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2702                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2703                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2704                 bp->link_vars.line_speed = SPEED_10000;
2705                 bp->link_vars.link_status =
2706                         (LINK_STATUS_LINK_UP |
2707                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2708                 bp->link_vars.link_up = 1;
2709                 bp->link_vars.duplex = DUPLEX_FULL;
2710                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2711                 __bnx2x_link_report(bp);
2712
2713                 bnx2x_sample_bulletin(bp);
2714
2715                 /* if bulletin board did not have an update for link status
2716                  * __bnx2x_link_report will report current status
2717                  * but it will NOT duplicate report in case of already reported
2718                  * during sampling bulletin board.
2719                  */
2720                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2721         }
2722 }
2723
2724 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2725                                   u16 vlan_val, u8 allowed_prio)
2726 {
2727         struct bnx2x_func_state_params func_params = {NULL};
2728         struct bnx2x_func_afex_update_params *f_update_params =
2729                 &func_params.params.afex_update;
2730
2731         func_params.f_obj = &bp->func_obj;
2732         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2733
2734         /* no need to wait for RAMROD completion, so don't
2735          * set RAMROD_COMP_WAIT flag
2736          */
2737
2738         f_update_params->vif_id = vifid;
2739         f_update_params->afex_default_vlan = vlan_val;
2740         f_update_params->allowed_priorities = allowed_prio;
2741
2742         /* if ramrod can not be sent, response to MCP immediately */
2743         if (bnx2x_func_state_change(bp, &func_params) < 0)
2744                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2745
2746         return 0;
2747 }
2748
2749 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2750                                           u16 vif_index, u8 func_bit_map)
2751 {
2752         struct bnx2x_func_state_params func_params = {NULL};
2753         struct bnx2x_func_afex_viflists_params *update_params =
2754                 &func_params.params.afex_viflists;
2755         int rc;
2756         u32 drv_msg_code;
2757
2758         /* validate only LIST_SET and LIST_GET are received from switch */
2759         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2760                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2761                           cmd_type);
2762
2763         func_params.f_obj = &bp->func_obj;
2764         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2765
2766         /* set parameters according to cmd_type */
2767         update_params->afex_vif_list_command = cmd_type;
2768         update_params->vif_list_index = vif_index;
2769         update_params->func_bit_map =
2770                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2771         update_params->func_to_clear = 0;
2772         drv_msg_code =
2773                 (cmd_type == VIF_LIST_RULE_GET) ?
2774                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2775                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2776
2777         /* if ramrod can not be sent, respond to MCP immediately for
2778          * SET and GET requests (other are not triggered from MCP)
2779          */
2780         rc = bnx2x_func_state_change(bp, &func_params);
2781         if (rc < 0)
2782                 bnx2x_fw_command(bp, drv_msg_code, 0);
2783
2784         return 0;
2785 }
2786
2787 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2788 {
2789         struct afex_stats afex_stats;
2790         u32 func = BP_ABS_FUNC(bp);
2791         u32 mf_config;
2792         u16 vlan_val;
2793         u32 vlan_prio;
2794         u16 vif_id;
2795         u8 allowed_prio;
2796         u8 vlan_mode;
2797         u32 addr_to_write, vifid, addrs, stats_type, i;
2798
2799         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2800                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801                 DP(BNX2X_MSG_MCP,
2802                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2803                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2804         }
2805
2806         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2807                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2809                 DP(BNX2X_MSG_MCP,
2810                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2811                    vifid, addrs);
2812                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813                                                addrs);
2814         }
2815
2816         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2817                 addr_to_write = SHMEM2_RD(bp,
2818                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2819                 stats_type = SHMEM2_RD(bp,
2820                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821
2822                 DP(BNX2X_MSG_MCP,
2823                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2824                    addr_to_write);
2825
2826                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2827
2828                 /* write response to scratchpad, for MCP */
2829                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2830                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2831                                *(((u32 *)(&afex_stats))+i));
2832
2833                 /* send ack message to MCP */
2834                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2835         }
2836
2837         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2838                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2839                 bp->mf_config[BP_VN(bp)] = mf_config;
2840                 DP(BNX2X_MSG_MCP,
2841                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2842                    mf_config);
2843
2844                 /* if VIF_SET is "enabled" */
2845                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2846                         /* set rate limit directly to internal RAM */
2847                         struct cmng_init_input cmng_input;
2848                         struct rate_shaping_vars_per_vn m_rs_vn;
2849                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2850                         u32 addr = BAR_XSTRORM_INTMEM +
2851                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2852
2853                         bp->mf_config[BP_VN(bp)] = mf_config;
2854
2855                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2856                         m_rs_vn.vn_counter.rate =
2857                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2858                         m_rs_vn.vn_counter.quota =
2859                                 (m_rs_vn.vn_counter.rate *
2860                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2861
2862                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2863
2864                         /* read relevant values from mf_cfg struct in shmem */
2865                         vif_id =
2866                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2867                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2868                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2869                         vlan_val =
2870                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2872                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2873                         vlan_prio = (mf_config &
2874                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2875                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2876                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2877                         vlan_mode =
2878                                 (MF_CFG_RD(bp,
2879                                            func_mf_config[func].afex_config) &
2880                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2881                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2882                         allowed_prio =
2883                                 (MF_CFG_RD(bp,
2884                                            func_mf_config[func].afex_config) &
2885                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2886                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2887
2888                         /* send ramrod to FW, return in case of failure */
2889                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890                                                    allowed_prio))
2891                                 return;
2892
2893                         bp->afex_def_vlan_tag = vlan_val;
2894                         bp->afex_vlan_mode = vlan_mode;
2895                 } else {
2896                         /* notify link down because BP->flags is disabled */
2897                         bnx2x_link_report(bp);
2898
2899                         /* send INVALID VIF ramrod to FW */
2900                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2901
2902                         /* Reset the default afex VLAN */
2903                         bp->afex_def_vlan_tag = -1;
2904                 }
2905         }
2906 }
2907
2908 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2909 {
2910         struct bnx2x_func_switch_update_params *switch_update_params;
2911         struct bnx2x_func_state_params func_params;
2912
2913         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2914         switch_update_params = &func_params.params.switch_update;
2915         func_params.f_obj = &bp->func_obj;
2916         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2917
2918         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2919                 int func = BP_ABS_FUNC(bp);
2920                 u32 val;
2921
2922                 /* Re-learn the S-tag from shmem */
2923                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2924                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2925                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2926                         bp->mf_ov = val;
2927                 } else {
2928                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2929                         goto fail;
2930                 }
2931
2932                 /* Configure new S-tag in LLH */
2933                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2934                        bp->mf_ov);
2935
2936                 /* Send Ramrod to update FW of change */
2937                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2938                           &switch_update_params->changes);
2939                 switch_update_params->vlan = bp->mf_ov;
2940
2941                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2942                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2943                                   bp->mf_ov);
2944                         goto fail;
2945                 } else {
2946                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2947                            bp->mf_ov);
2948                 }
2949         } else {
2950                 goto fail;
2951         }
2952
2953         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2954         return;
2955 fail:
2956         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2957 }
2958
2959 static void bnx2x_pmf_update(struct bnx2x *bp)
2960 {
2961         int port = BP_PORT(bp);
2962         u32 val;
2963
2964         bp->port.pmf = 1;
2965         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2966
2967         /*
2968          * We need the mb() to ensure the ordering between the writing to
2969          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2970          */
2971         smp_mb();
2972
2973         /* queue a periodic task */
2974         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2975
2976         bnx2x_dcbx_pmf_update(bp);
2977
2978         /* enable nig attention */
2979         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2980         if (bp->common.int_block == INT_BLOCK_HC) {
2981                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2982                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2983         } else if (!CHIP_IS_E1x(bp)) {
2984                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2985                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2986         }
2987
2988         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2989 }
2990
2991 /* end of Link */
2992
2993 /* slow path */
2994
2995 /*
2996  * General service functions
2997  */
2998
2999 /* send the MCP a request, block until there is a reply */
3000 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3001 {
3002         int mb_idx = BP_FW_MB_IDX(bp);
3003         u32 seq;
3004         u32 rc = 0;
3005         u32 cnt = 1;
3006         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3007
3008         mutex_lock(&bp->fw_mb_mutex);
3009         seq = ++bp->fw_seq;
3010         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3012
3013         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3014                         (command | seq), param);
3015
3016         do {
3017                 /* let the FW do it's magic ... */
3018                 msleep(delay);
3019
3020                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3021
3022                 /* Give the FW up to 5 second (500*10ms) */
3023         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3024
3025         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3026            cnt*delay, rc, seq);
3027
3028         /* is this a reply to our command? */
3029         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3030                 rc &= FW_MSG_CODE_MASK;
3031         else {
3032                 /* FW BUG! */
3033                 BNX2X_ERR("FW failed to respond!\n");
3034                 bnx2x_fw_dump(bp);
3035                 rc = 0;
3036         }
3037         mutex_unlock(&bp->fw_mb_mutex);
3038
3039         return rc;
3040 }
3041
3042 static void storm_memset_func_cfg(struct bnx2x *bp,
3043                                  struct tstorm_eth_function_common_config *tcfg,
3044                                  u16 abs_fid)
3045 {
3046         size_t size = sizeof(struct tstorm_eth_function_common_config);
3047
3048         u32 addr = BAR_TSTRORM_INTMEM +
3049                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3050
3051         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3052 }
3053
3054 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3055 {
3056         if (CHIP_IS_E1x(bp)) {
3057                 struct tstorm_eth_function_common_config tcfg = {0};
3058
3059                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3060         }
3061
3062         /* Enable the function in the FW */
3063         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3064         storm_memset_func_en(bp, p->func_id, 1);
3065
3066         /* spq */
3067         if (p->spq_active) {
3068                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3069                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3070                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3071         }
3072 }
3073
3074 /**
3075  * bnx2x_get_common_flags - Return common flags
3076  *
3077  * @bp          device handle
3078  * @fp          queue handle
3079  * @zero_stats  TRUE if statistics zeroing is needed
3080  *
3081  * Return the flags that are common for the Tx-only and not normal connections.
3082  */
3083 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3084                                             struct bnx2x_fastpath *fp,
3085                                             bool zero_stats)
3086 {
3087         unsigned long flags = 0;
3088
3089         /* PF driver will always initialize the Queue to an ACTIVE state */
3090         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3091
3092         /* tx only connections collect statistics (on the same index as the
3093          * parent connection). The statistics are zeroed when the parent
3094          * connection is initialized.
3095          */
3096
3097         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3098         if (zero_stats)
3099                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3100
3101         if (bp->flags & TX_SWITCHING)
3102                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3103
3104         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3105         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3106
3107 #ifdef BNX2X_STOP_ON_ERROR
3108         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3109 #endif
3110
3111         return flags;
3112 }
3113
3114 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3115                                        struct bnx2x_fastpath *fp,
3116                                        bool leading)
3117 {
3118         unsigned long flags = 0;
3119
3120         /* calculate other queue flags */
3121         if (IS_MF_SD(bp))
3122                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3123
3124         if (IS_FCOE_FP(fp)) {
3125                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3126                 /* For FCoE - force usage of default priority (for afex) */
3127                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3128         }
3129
3130         if (fp->mode != TPA_MODE_DISABLED) {
3131                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3132                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3133                 if (fp->mode == TPA_MODE_GRO)
3134                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3135         }
3136
3137         if (leading) {
3138                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3139                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3140         }
3141
3142         /* Always set HW VLAN stripping */
3143         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3144
3145         /* configure silent vlan removal */
3146         if (IS_MF_AFEX(bp))
3147                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3148
3149         return flags | bnx2x_get_common_flags(bp, fp, true);
3150 }
3151
3152 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3153         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3154         u8 cos)
3155 {
3156         gen_init->stat_id = bnx2x_stats_id(fp);
3157         gen_init->spcl_id = fp->cl_id;
3158
3159         /* Always use mini-jumbo MTU for FCoE L2 ring */
3160         if (IS_FCOE_FP(fp))
3161                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3162         else
3163                 gen_init->mtu = bp->dev->mtu;
3164
3165         gen_init->cos = cos;
3166
3167         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3168 }
3169
3170 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3171         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3172         struct bnx2x_rxq_setup_params *rxq_init)
3173 {
3174         u8 max_sge = 0;
3175         u16 sge_sz = 0;
3176         u16 tpa_agg_size = 0;
3177
3178         if (fp->mode != TPA_MODE_DISABLED) {
3179                 pause->sge_th_lo = SGE_TH_LO(bp);
3180                 pause->sge_th_hi = SGE_TH_HI(bp);
3181
3182                 /* validate SGE ring has enough to cross high threshold */
3183                 WARN_ON(bp->dropless_fc &&
3184                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3185                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3186
3187                 tpa_agg_size = TPA_AGG_SIZE;
3188                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3189                         SGE_PAGE_SHIFT;
3190                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3191                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3192                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3193         }
3194
3195         /* pause - not for e1 */
3196         if (!CHIP_IS_E1(bp)) {
3197                 pause->bd_th_lo = BD_TH_LO(bp);
3198                 pause->bd_th_hi = BD_TH_HI(bp);
3199
3200                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3201                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3202                 /*
3203                  * validate that rings have enough entries to cross
3204                  * high thresholds
3205                  */
3206                 WARN_ON(bp->dropless_fc &&
3207                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3208                                 bp->rx_ring_size);
3209                 WARN_ON(bp->dropless_fc &&
3210                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3211                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3212
3213                 pause->pri_map = 1;
3214         }
3215
3216         /* rxq setup */
3217         rxq_init->dscr_map = fp->rx_desc_mapping;
3218         rxq_init->sge_map = fp->rx_sge_mapping;
3219         rxq_init->rcq_map = fp->rx_comp_mapping;
3220         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3221
3222         /* This should be a maximum number of data bytes that may be
3223          * placed on the BD (not including paddings).
3224          */
3225         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3226                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3227
3228         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3229         rxq_init->tpa_agg_sz = tpa_agg_size;
3230         rxq_init->sge_buf_sz = sge_sz;
3231         rxq_init->max_sges_pkt = max_sge;
3232         rxq_init->rss_engine_id = BP_FUNC(bp);
3233         rxq_init->mcast_engine_id = BP_FUNC(bp);
3234
3235         /* Maximum number or simultaneous TPA aggregation for this Queue.
3236          *
3237          * For PF Clients it should be the maximum available number.
3238          * VF driver(s) may want to define it to a smaller value.
3239          */
3240         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3241
3242         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3243         rxq_init->fw_sb_id = fp->fw_sb_id;
3244
3245         if (IS_FCOE_FP(fp))
3246                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3247         else
3248                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3249         /* configure silent vlan removal
3250          * if multi function mode is afex, then mask default vlan
3251          */
3252         if (IS_MF_AFEX(bp)) {
3253                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3254                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3255         }
3256 }
3257
3258 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3259         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3260         u8 cos)
3261 {
3262         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3263         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3264         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3265         txq_init->fw_sb_id = fp->fw_sb_id;
3266
3267         /*
3268          * set the tss leading client id for TX classification ==
3269          * leading RSS client id
3270          */
3271         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3272
3273         if (IS_FCOE_FP(fp)) {
3274                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3275                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3276         }
3277 }
3278
3279 static void bnx2x_pf_init(struct bnx2x *bp)
3280 {
3281         struct bnx2x_func_init_params func_init = {0};
3282         struct event_ring_data eq_data = { {0} };
3283
3284         if (!CHIP_IS_E1x(bp)) {
3285                 /* reset IGU PF statistics: MSIX + ATTN */
3286                 /* PF */
3287                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3288                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3289                            (CHIP_MODE_IS_4_PORT(bp) ?
3290                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3291                 /* ATTN */
3292                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3293                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3294                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3295                            (CHIP_MODE_IS_4_PORT(bp) ?
3296                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3297         }
3298
3299         func_init.spq_active = true;
3300         func_init.pf_id = BP_FUNC(bp);
3301         func_init.func_id = BP_FUNC(bp);
3302         func_init.spq_map = bp->spq_mapping;
3303         func_init.spq_prod = bp->spq_prod_idx;
3304
3305         bnx2x_func_init(bp, &func_init);
3306
3307         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3308
3309         /*
3310          * Congestion management values depend on the link rate
3311          * There is no active link so initial link rate is set to 10 Gbps.
3312          * When the link comes up The congestion management values are
3313          * re-calculated according to the actual link rate.
3314          */
3315         bp->link_vars.line_speed = SPEED_10000;
3316         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3317
3318         /* Only the PMF sets the HW */
3319         if (bp->port.pmf)
3320                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3321
3322         /* init Event Queue - PCI bus guarantees correct endianity*/
3323         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3324         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3325         eq_data.producer = bp->eq_prod;
3326         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3327         eq_data.sb_id = DEF_SB_ID;
3328         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3329 }
3330
3331 static void bnx2x_e1h_disable(struct bnx2x *bp)
3332 {
3333         int port = BP_PORT(bp);
3334
3335         bnx2x_tx_disable(bp);
3336
3337         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3338 }
3339
3340 static void bnx2x_e1h_enable(struct bnx2x *bp)
3341 {
3342         int port = BP_PORT(bp);
3343
3344         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3345                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3346
3347         /* Tx queue should be only re-enabled */
3348         netif_tx_wake_all_queues(bp->dev);
3349
3350         /*
3351          * Should not call netif_carrier_on since it will be called if the link
3352          * is up when checking for link state
3353          */
3354 }
3355
3356 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3357
3358 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3359 {
3360         struct eth_stats_info *ether_stat =
3361                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3362         struct bnx2x_vlan_mac_obj *mac_obj =
3363                 &bp->sp_objs->mac_obj;
3364         int i;
3365
3366         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3367                 ETH_STAT_INFO_VERSION_LEN);
3368
3369         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3370          * mac_local field in ether_stat struct. The base address is offset by 2
3371          * bytes to account for the field being 8 bytes but a mac address is
3372          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3373          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3374          * allocated by the ether_stat struct, so the macs will land in their
3375          * proper positions.
3376          */
3377         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3378                 memset(ether_stat->mac_local + i, 0,
3379                        sizeof(ether_stat->mac_local[0]));
3380         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3381                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3382                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3383                                 ETH_ALEN);
3384         ether_stat->mtu_size = bp->dev->mtu;
3385         if (bp->dev->features & NETIF_F_RXCSUM)
3386                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3387         if (bp->dev->features & NETIF_F_TSO)
3388                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3389         ether_stat->feature_flags |= bp->common.boot_mode;
3390
3391         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3392
3393         ether_stat->txq_size = bp->tx_ring_size;
3394         ether_stat->rxq_size = bp->rx_ring_size;
3395
3396 #ifdef CONFIG_BNX2X_SRIOV
3397         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3398 #endif
3399 }
3400
3401 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3402 {
3403         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3404         struct fcoe_stats_info *fcoe_stat =
3405                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3406
3407         if (!CNIC_LOADED(bp))
3408                 return;
3409
3410         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3411
3412         fcoe_stat->qos_priority =
3413                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3414
3415         /* insert FCoE stats from ramrod response */
3416         if (!NO_FCOE(bp)) {
3417                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3418                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3419                         tstorm_queue_statistics;
3420
3421                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3422                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3423                         xstorm_queue_statistics;
3424
3425                 struct fcoe_statistics_params *fw_fcoe_stat =
3426                         &bp->fw_stats_data->fcoe;
3427
3428                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3429                           fcoe_stat->rx_bytes_lo,
3430                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3431
3432                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3433                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3434                           fcoe_stat->rx_bytes_lo,
3435                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3436
3437                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3438                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3439                           fcoe_stat->rx_bytes_lo,
3440                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3441
3442                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3444                           fcoe_stat->rx_bytes_lo,
3445                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3446
3447                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3448                           fcoe_stat->rx_frames_lo,
3449                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3450
3451                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3452                           fcoe_stat->rx_frames_lo,
3453                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3454
3455                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456                           fcoe_stat->rx_frames_lo,
3457                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3458
3459                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460                           fcoe_stat->rx_frames_lo,
3461                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3462
3463                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3464                           fcoe_stat->tx_bytes_lo,
3465                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3466
3467                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3468                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3469                           fcoe_stat->tx_bytes_lo,
3470                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3471
3472                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3473                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3474                           fcoe_stat->tx_bytes_lo,
3475                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3476
3477                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3479                           fcoe_stat->tx_bytes_lo,
3480                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3481
3482                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3483                           fcoe_stat->tx_frames_lo,
3484                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3485
3486                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3487                           fcoe_stat->tx_frames_lo,
3488                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3489
3490                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491                           fcoe_stat->tx_frames_lo,
3492                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3493
3494                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495                           fcoe_stat->tx_frames_lo,
3496                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3497         }
3498
3499         /* ask L5 driver to add data to the struct */
3500         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3501 }
3502
3503 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3504 {
3505         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3506         struct iscsi_stats_info *iscsi_stat =
3507                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3508
3509         if (!CNIC_LOADED(bp))
3510                 return;
3511
3512         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3513                ETH_ALEN);
3514
3515         iscsi_stat->qos_priority =
3516                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3517
3518         /* ask L5 driver to add data to the struct */
3519         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3520 }
3521
3522 /* called due to MCP event (on pmf):
3523  *      reread new bandwidth configuration
3524  *      configure FW
3525  *      notify others function about the change
3526  */
3527 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3528 {
3529         /* Workaround for MFW bug.
3530          * MFW is not supposed to generate BW attention in
3531          * single function mode.
3532          */
3533         if (!IS_MF(bp)) {
3534                 DP(BNX2X_MSG_MCP,
3535                    "Ignoring MF BW config in single function mode\n");
3536                 return;
3537         }
3538
3539         if (bp->link_vars.link_up) {
3540                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3541                 bnx2x_link_sync_notify(bp);
3542         }
3543         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3544 }
3545
3546 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3547 {
3548         bnx2x_config_mf_bw(bp);
3549         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3550 }
3551
3552 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3553 {
3554         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3555         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3556 }
3557
3558 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3559 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3560
3561 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3562 {
3563         enum drv_info_opcode op_code;
3564         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3565         bool release = false;
3566         int wait;
3567
3568         /* if drv_info version supported by MFW doesn't match - send NACK */
3569         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3570                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3571                 return;
3572         }
3573
3574         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3575                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3576
3577         /* Must prevent other flows from accessing drv_info_to_mcp */
3578         mutex_lock(&bp->drv_info_mutex);
3579
3580         memset(&bp->slowpath->drv_info_to_mcp, 0,
3581                sizeof(union drv_info_to_mcp));
3582
3583         switch (op_code) {
3584         case ETH_STATS_OPCODE:
3585                 bnx2x_drv_info_ether_stat(bp);
3586                 break;
3587         case FCOE_STATS_OPCODE:
3588                 bnx2x_drv_info_fcoe_stat(bp);
3589                 break;
3590         case ISCSI_STATS_OPCODE:
3591                 bnx2x_drv_info_iscsi_stat(bp);
3592                 break;
3593         default:
3594                 /* if op code isn't supported - send NACK */
3595                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596                 goto out;
3597         }
3598
3599         /* if we got drv_info attn from MFW then these fields are defined in
3600          * shmem2 for sure
3601          */
3602         SHMEM2_WR(bp, drv_info_host_addr_lo,
3603                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604         SHMEM2_WR(bp, drv_info_host_addr_hi,
3605                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606
3607         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3608
3609         /* Since possible management wants both this and get_driver_version
3610          * need to wait until management notifies us it finished utilizing
3611          * the buffer.
3612          */
3613         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3614                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3615         } else if (!bp->drv_info_mng_owner) {
3616                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3617
3618                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3619                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3620
3621                         /* Management is done; need to clear indication */
3622                         if (indication & bit) {
3623                                 SHMEM2_WR(bp, mfw_drv_indication,
3624                                           indication & ~bit);
3625                                 release = true;
3626                                 break;
3627                         }
3628
3629                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3630                 }
3631         }
3632         if (!release) {
3633                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3634                 bp->drv_info_mng_owner = true;
3635         }
3636
3637 out:
3638         mutex_unlock(&bp->drv_info_mutex);
3639 }
3640
3641 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3642 {
3643         u8 vals[4];
3644         int i = 0;
3645
3646         if (bnx2x_format) {
3647                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3648                            &vals[0], &vals[1], &vals[2], &vals[3]);
3649                 if (i > 0)
3650                         vals[0] -= '0';
3651         } else {
3652                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3653                            &vals[0], &vals[1], &vals[2], &vals[3]);
3654         }
3655
3656         while (i < 4)
3657                 vals[i++] = 0;
3658
3659         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3660 }
3661
3662 void bnx2x_update_mng_version(struct bnx2x *bp)
3663 {
3664         u32 iscsiver = DRV_VER_NOT_LOADED;
3665         u32 fcoever = DRV_VER_NOT_LOADED;
3666         u32 ethver = DRV_VER_NOT_LOADED;
3667         int idx = BP_FW_MB_IDX(bp);
3668         u8 *version;
3669
3670         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3671                 return;
3672
3673         mutex_lock(&bp->drv_info_mutex);
3674         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3675         if (bp->drv_info_mng_owner)
3676                 goto out;
3677
3678         if (bp->state != BNX2X_STATE_OPEN)
3679                 goto out;
3680
3681         /* Parse ethernet driver version */
3682         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3683         if (!CNIC_LOADED(bp))
3684                 goto out;
3685
3686         /* Try getting storage driver version via cnic */
3687         memset(&bp->slowpath->drv_info_to_mcp, 0,
3688                sizeof(union drv_info_to_mcp));
3689         bnx2x_drv_info_iscsi_stat(bp);
3690         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3691         iscsiver = bnx2x_update_mng_version_utility(version, false);
3692
3693         memset(&bp->slowpath->drv_info_to_mcp, 0,
3694                sizeof(union drv_info_to_mcp));
3695         bnx2x_drv_info_fcoe_stat(bp);
3696         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3697         fcoever = bnx2x_update_mng_version_utility(version, false);
3698
3699 out:
3700         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3701         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3702         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3703
3704         mutex_unlock(&bp->drv_info_mutex);
3705
3706         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3707            ethver, iscsiver, fcoever);
3708 }
3709
3710 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3711 {
3712         u32 drv_ver;
3713         u32 valid_dump;
3714
3715         if (!SHMEM2_HAS(bp, drv_info))
3716                 return;
3717
3718         /* Update Driver load time, possibly broken in y2038 */
3719         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3720
3721         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3722         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3723
3724         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3725
3726         /* Check & notify On-Chip dump. */
3727         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3728
3729         if (valid_dump & FIRST_DUMP_VALID)
3730                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3731
3732         if (valid_dump & SECOND_DUMP_VALID)
3733                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3734 }
3735
3736 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3737 {
3738         u32 cmd_ok, cmd_fail;
3739
3740         /* sanity */
3741         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3742             event & DRV_STATUS_OEM_EVENT_MASK) {
3743                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3744                 return;
3745         }
3746
3747         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3748                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3749                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3750         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3751                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3752                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3753         }
3754
3755         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3756
3757         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3758                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3759                 /* This is the only place besides the function initialization
3760                  * where the bp->flags can change so it is done without any
3761                  * locks
3762                  */
3763                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3764                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3765                         bp->flags |= MF_FUNC_DIS;
3766
3767                         bnx2x_e1h_disable(bp);
3768                 } else {
3769                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3770                         bp->flags &= ~MF_FUNC_DIS;
3771
3772                         bnx2x_e1h_enable(bp);
3773                 }
3774                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3775                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3776         }
3777
3778         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3779                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3780                 bnx2x_config_mf_bw(bp);
3781                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3782                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3783         }
3784
3785         /* Report results to MCP */
3786         if (event)
3787                 bnx2x_fw_command(bp, cmd_fail, 0);
3788         else
3789                 bnx2x_fw_command(bp, cmd_ok, 0);
3790 }
3791
3792 /* must be called under the spq lock */
3793 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3794 {
3795         struct eth_spe *next_spe = bp->spq_prod_bd;
3796
3797         if (bp->spq_prod_bd == bp->spq_last_bd) {
3798                 bp->spq_prod_bd = bp->spq;
3799                 bp->spq_prod_idx = 0;
3800                 DP(BNX2X_MSG_SP, "end of spq\n");
3801         } else {
3802                 bp->spq_prod_bd++;
3803                 bp->spq_prod_idx++;
3804         }
3805         return next_spe;
3806 }
3807
3808 /* must be called under the spq lock */
3809 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3810 {
3811         int func = BP_FUNC(bp);
3812
3813         /*
3814          * Make sure that BD data is updated before writing the producer:
3815          * BD data is written to the memory, the producer is read from the
3816          * memory, thus we need a full memory barrier to ensure the ordering.
3817          */
3818         mb();
3819
3820         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3821                  bp->spq_prod_idx);
3822         mmiowb();
3823 }
3824
3825 /**
3826  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3827  *
3828  * @cmd:        command to check
3829  * @cmd_type:   command type
3830  */
3831 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3832 {
3833         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3834             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3835             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3836             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3837             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3838             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3839             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3840                 return true;
3841         else
3842                 return false;
3843 }
3844
3845 /**
3846  * bnx2x_sp_post - place a single command on an SP ring
3847  *
3848  * @bp:         driver handle
3849  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3850  * @cid:        SW CID the command is related to
3851  * @data_hi:    command private data address (high 32 bits)
3852  * @data_lo:    command private data address (low 32 bits)
3853  * @cmd_type:   command type (e.g. NONE, ETH)
3854  *
3855  * SP data is handled as if it's always an address pair, thus data fields are
3856  * not swapped to little endian in upper functions. Instead this function swaps
3857  * data as if it's two u32 fields.
3858  */
3859 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3860                   u32 data_hi, u32 data_lo, int cmd_type)
3861 {
3862         struct eth_spe *spe;
3863         u16 type;
3864         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3865
3866 #ifdef BNX2X_STOP_ON_ERROR
3867         if (unlikely(bp->panic)) {
3868                 BNX2X_ERR("Can't post SP when there is panic\n");
3869                 return -EIO;
3870         }
3871 #endif
3872
3873         spin_lock_bh(&bp->spq_lock);
3874
3875         if (common) {
3876                 if (!atomic_read(&bp->eq_spq_left)) {
3877                         BNX2X_ERR("BUG! EQ ring full!\n");
3878                         spin_unlock_bh(&bp->spq_lock);
3879                         bnx2x_panic();
3880                         return -EBUSY;
3881                 }
3882         } else if (!atomic_read(&bp->cq_spq_left)) {
3883                         BNX2X_ERR("BUG! SPQ ring full!\n");
3884                         spin_unlock_bh(&bp->spq_lock);
3885                         bnx2x_panic();
3886                         return -EBUSY;
3887         }
3888
3889         spe = bnx2x_sp_get_next(bp);
3890
3891         /* CID needs port number to be encoded int it */
3892         spe->hdr.conn_and_cmd_data =
3893                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3894                                     HW_CID(bp, cid));
3895
3896         /* In some cases, type may already contain the func-id
3897          * mainly in SRIOV related use cases, so we add it here only
3898          * if it's not already set.
3899          */
3900         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3901                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3902                         SPE_HDR_CONN_TYPE;
3903                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3904                          SPE_HDR_FUNCTION_ID);
3905         } else {
3906                 type = cmd_type;
3907         }
3908
3909         spe->hdr.type = cpu_to_le16(type);
3910
3911         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3912         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3913
3914         /*
3915          * It's ok if the actual decrement is issued towards the memory
3916          * somewhere between the spin_lock and spin_unlock. Thus no
3917          * more explicit memory barrier is needed.
3918          */
3919         if (common)
3920                 atomic_dec(&bp->eq_spq_left);
3921         else
3922                 atomic_dec(&bp->cq_spq_left);
3923
3924         DP(BNX2X_MSG_SP,
3925            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3926            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3927            (u32)(U64_LO(bp->spq_mapping) +
3928            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3929            HW_CID(bp, cid), data_hi, data_lo, type,
3930            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3931
3932         bnx2x_sp_prod_update(bp);
3933         spin_unlock_bh(&bp->spq_lock);
3934         return 0;
3935 }
3936
3937 /* acquire split MCP access lock register */
3938 static int bnx2x_acquire_alr(struct bnx2x *bp)
3939 {
3940         u32 j, val;
3941         int rc = 0;
3942
3943         might_sleep();
3944         for (j = 0; j < 1000; j++) {
3945                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3946                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3947                 if (val & MCPR_ACCESS_LOCK_LOCK)
3948                         break;
3949
3950                 usleep_range(5000, 10000);
3951         }
3952         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3953                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3954                 rc = -EBUSY;
3955         }
3956
3957         return rc;
3958 }
3959
3960 /* release split MCP access lock register */
3961 static void bnx2x_release_alr(struct bnx2x *bp)
3962 {
3963         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3964 }
3965
3966 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3967 #define BNX2X_DEF_SB_IDX        0x0002
3968
3969 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3970 {
3971         struct host_sp_status_block *def_sb = bp->def_status_blk;
3972         u16 rc = 0;
3973
3974         barrier(); /* status block is written to by the chip */
3975         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3976                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3977                 rc |= BNX2X_DEF_SB_ATT_IDX;
3978         }
3979
3980         if (bp->def_idx != def_sb->sp_sb.running_index) {
3981                 bp->def_idx = def_sb->sp_sb.running_index;
3982                 rc |= BNX2X_DEF_SB_IDX;
3983         }
3984
3985         /* Do not reorder: indices reading should complete before handling */
3986         barrier();
3987         return rc;
3988 }
3989
3990 /*
3991  * slow path service functions
3992  */
3993
3994 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3995 {
3996         int port = BP_PORT(bp);
3997         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3998                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3999         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4000                                        NIG_REG_MASK_INTERRUPT_PORT0;
4001         u32 aeu_mask;
4002         u32 nig_mask = 0;
4003         u32 reg_addr;
4004
4005         if (bp->attn_state & asserted)
4006                 BNX2X_ERR("IGU ERROR\n");
4007
4008         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4009         aeu_mask = REG_RD(bp, aeu_addr);
4010
4011         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4012            aeu_mask, asserted);
4013         aeu_mask &= ~(asserted & 0x3ff);
4014         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4015
4016         REG_WR(bp, aeu_addr, aeu_mask);
4017         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4018
4019         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4020         bp->attn_state |= asserted;
4021         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4022
4023         if (asserted & ATTN_HARD_WIRED_MASK) {
4024                 if (asserted & ATTN_NIG_FOR_FUNC) {
4025
4026                         bnx2x_acquire_phy_lock(bp);
4027
4028                         /* save nig interrupt mask */
4029                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4030
4031                         /* If nig_mask is not set, no need to call the update
4032                          * function.
4033                          */
4034                         if (nig_mask) {
4035                                 REG_WR(bp, nig_int_mask_addr, 0);
4036
4037                                 bnx2x_link_attn(bp);
4038                         }
4039
4040                         /* handle unicore attn? */
4041                 }
4042                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4043                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4044
4045                 if (asserted & GPIO_2_FUNC)
4046                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4047
4048                 if (asserted & GPIO_3_FUNC)
4049                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4050
4051                 if (asserted & GPIO_4_FUNC)
4052                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4053
4054                 if (port == 0) {
4055                         if (asserted & ATTN_GENERAL_ATTN_1) {
4056                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4057                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4058                         }
4059                         if (asserted & ATTN_GENERAL_ATTN_2) {
4060                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4061                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4062                         }
4063                         if (asserted & ATTN_GENERAL_ATTN_3) {
4064                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4065                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4066                         }
4067                 } else {
4068                         if (asserted & ATTN_GENERAL_ATTN_4) {
4069                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4070                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4071                         }
4072                         if (asserted & ATTN_GENERAL_ATTN_5) {
4073                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4074                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4075                         }
4076                         if (asserted & ATTN_GENERAL_ATTN_6) {
4077                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4078                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4079                         }
4080                 }
4081
4082         } /* if hardwired */
4083
4084         if (bp->common.int_block == INT_BLOCK_HC)
4085                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4086                             COMMAND_REG_ATTN_BITS_SET);
4087         else
4088                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4089
4090         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4091            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4092         REG_WR(bp, reg_addr, asserted);
4093
4094         /* now set back the mask */
4095         if (asserted & ATTN_NIG_FOR_FUNC) {
4096                 /* Verify that IGU ack through BAR was written before restoring
4097                  * NIG mask. This loop should exit after 2-3 iterations max.
4098                  */
4099                 if (bp->common.int_block != INT_BLOCK_HC) {
4100                         u32 cnt = 0, igu_acked;
4101                         do {
4102                                 igu_acked = REG_RD(bp,
4103                                                    IGU_REG_ATTENTION_ACK_BITS);
4104                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4105                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4106                         if (!igu_acked)
4107                                 DP(NETIF_MSG_HW,
4108                                    "Failed to verify IGU ack on time\n");
4109                         barrier();
4110                 }
4111                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4112                 bnx2x_release_phy_lock(bp);
4113         }
4114 }
4115
4116 static void bnx2x_fan_failure(struct bnx2x *bp)
4117 {
4118         int port = BP_PORT(bp);
4119         u32 ext_phy_config;
4120         /* mark the failure */
4121         ext_phy_config =
4122                 SHMEM_RD(bp,
4123                          dev_info.port_hw_config[port].external_phy_config);
4124
4125         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4126         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4127         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4128                  ext_phy_config);
4129
4130         /* log the failure */
4131         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4132                             "Please contact OEM Support for assistance\n");
4133
4134         /* Schedule device reset (unload)
4135          * This is due to some boards consuming sufficient power when driver is
4136          * up to overheat if fan fails.
4137          */
4138         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4139 }
4140
4141 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4142 {
4143         int port = BP_PORT(bp);
4144         int reg_offset;
4145         u32 val;
4146
4147         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4148                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4149
4150         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4151
4152                 val = REG_RD(bp, reg_offset);
4153                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4154                 REG_WR(bp, reg_offset, val);
4155
4156                 BNX2X_ERR("SPIO5 hw attention\n");
4157
4158                 /* Fan failure attention */
4159                 bnx2x_hw_reset_phy(&bp->link_params);
4160                 bnx2x_fan_failure(bp);
4161         }
4162
4163         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4164                 bnx2x_acquire_phy_lock(bp);
4165                 bnx2x_handle_module_detect_int(&bp->link_params);
4166                 bnx2x_release_phy_lock(bp);
4167         }
4168
4169         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4170
4171                 val = REG_RD(bp, reg_offset);
4172                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4173                 REG_WR(bp, reg_offset, val);
4174
4175                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4176                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4177                 bnx2x_panic();
4178         }
4179 }
4180
4181 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4182 {
4183         u32 val;
4184
4185         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4186
4187                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4188                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4189                 /* DORQ discard attention */
4190                 if (val & 0x2)
4191                         BNX2X_ERR("FATAL error from DORQ\n");
4192         }
4193
4194         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4195
4196                 int port = BP_PORT(bp);
4197                 int reg_offset;
4198
4199                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4200                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4201
4202                 val = REG_RD(bp, reg_offset);
4203                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4204                 REG_WR(bp, reg_offset, val);
4205
4206                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4207                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4208                 bnx2x_panic();
4209         }
4210 }
4211
4212 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4213 {
4214         u32 val;
4215
4216         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4217
4218                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4219                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4220                 /* CFC error attention */
4221                 if (val & 0x2)
4222                         BNX2X_ERR("FATAL error from CFC\n");
4223         }
4224
4225         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4226                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4227                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4228                 /* RQ_USDMDP_FIFO_OVERFLOW */
4229                 if (val & 0x18000)
4230                         BNX2X_ERR("FATAL error from PXP\n");
4231
4232                 if (!CHIP_IS_E1x(bp)) {
4233                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4234                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4235                 }
4236         }
4237
4238         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4239
4240                 int port = BP_PORT(bp);
4241                 int reg_offset;
4242
4243                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4244                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4245
4246                 val = REG_RD(bp, reg_offset);
4247                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4248                 REG_WR(bp, reg_offset, val);
4249
4250                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4251                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4252                 bnx2x_panic();
4253         }
4254 }
4255
4256 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4257 {
4258         u32 val;
4259
4260         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4261
4262                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4263                         int func = BP_FUNC(bp);
4264
4265                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4266                         bnx2x_read_mf_cfg(bp);
4267                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4268                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4269                         val = SHMEM_RD(bp,
4270                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4271
4272                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4273                                    DRV_STATUS_OEM_EVENT_MASK))
4274                                 bnx2x_oem_event(bp,
4275                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4276                                                 DRV_STATUS_OEM_EVENT_MASK)));
4277
4278                         if (val & DRV_STATUS_SET_MF_BW)
4279                                 bnx2x_set_mf_bw(bp);
4280
4281                         if (val & DRV_STATUS_DRV_INFO_REQ)
4282                                 bnx2x_handle_drv_info_req(bp);
4283
4284                         if (val & DRV_STATUS_VF_DISABLED)
4285                                 bnx2x_schedule_iov_task(bp,
4286                                                         BNX2X_IOV_HANDLE_FLR);
4287
4288                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4289                                 bnx2x_pmf_update(bp);
4290
4291                         if (bp->port.pmf &&
4292                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4293                                 bp->dcbx_enabled > 0)
4294                                 /* start dcbx state machine */
4295                                 bnx2x_dcbx_set_params(bp,
4296                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4297                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4298                                 bnx2x_handle_afex_cmd(bp,
4299                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4300                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4301                                 bnx2x_handle_eee_event(bp);
4302
4303                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4304                                 bnx2x_handle_update_svid_cmd(bp);
4305
4306                         if (bp->link_vars.periodic_flags &
4307                             PERIODIC_FLAGS_LINK_EVENT) {
4308                                 /*  sync with link */
4309                                 bnx2x_acquire_phy_lock(bp);
4310                                 bp->link_vars.periodic_flags &=
4311                                         ~PERIODIC_FLAGS_LINK_EVENT;
4312                                 bnx2x_release_phy_lock(bp);
4313                                 if (IS_MF(bp))
4314                                         bnx2x_link_sync_notify(bp);
4315                                 bnx2x_link_report(bp);
4316                         }
4317                         /* Always call it here: bnx2x_link_report() will
4318                          * prevent the link indication duplication.
4319                          */
4320                         bnx2x__link_status_update(bp);
4321                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4322
4323                         BNX2X_ERR("MC assert!\n");
4324                         bnx2x_mc_assert(bp);
4325                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4326                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4327                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4328                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4329                         bnx2x_panic();
4330
4331                 } else if (attn & BNX2X_MCP_ASSERT) {
4332
4333                         BNX2X_ERR("MCP assert!\n");
4334                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4335                         bnx2x_fw_dump(bp);
4336
4337                 } else
4338                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4339         }
4340
4341         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4342                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4343                 if (attn & BNX2X_GRC_TIMEOUT) {
4344                         val = CHIP_IS_E1(bp) ? 0 :
4345                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4346                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4347                 }
4348                 if (attn & BNX2X_GRC_RSV) {
4349                         val = CHIP_IS_E1(bp) ? 0 :
4350                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4351                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4352                 }
4353                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4354         }
4355 }
4356
4357 /*
4358  * Bits map:
4359  * 0-7   - Engine0 load counter.
4360  * 8-15  - Engine1 load counter.
4361  * 16    - Engine0 RESET_IN_PROGRESS bit.
4362  * 17    - Engine1 RESET_IN_PROGRESS bit.
4363  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4364  *         on the engine
4365  * 19    - Engine1 ONE_IS_LOADED.
4366  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4367  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4368  *         just the one belonging to its engine).
4369  *
4370  */
4371 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4372
4373 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4374 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4375 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4376 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4377 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4378 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4379 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4380
4381 /*
4382  * Set the GLOBAL_RESET bit.
4383  *
4384  * Should be run under rtnl lock
4385  */
4386 void bnx2x_set_reset_global(struct bnx2x *bp)
4387 {
4388         u32 val;
4389         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4390         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4391         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4392         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4393 }
4394
4395 /*
4396  * Clear the GLOBAL_RESET bit.
4397  *
4398  * Should be run under rtnl lock
4399  */
4400 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4401 {
4402         u32 val;
4403         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4404         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4405         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4406         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4407 }
4408
4409 /*
4410  * Checks the GLOBAL_RESET bit.
4411  *
4412  * should be run under rtnl lock
4413  */
4414 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4415 {
4416         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4417
4418         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4419         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4420 }
4421
4422 /*
4423  * Clear RESET_IN_PROGRESS bit for the current engine.
4424  *
4425  * Should be run under rtnl lock
4426  */
4427 static void bnx2x_set_reset_done(struct bnx2x *bp)
4428 {
4429         u32 val;
4430         u32 bit = BP_PATH(bp) ?
4431                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4432         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4433         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4434
4435         /* Clear the bit */
4436         val &= ~bit;
4437         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4438
4439         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4440 }
4441
4442 /*
4443  * Set RESET_IN_PROGRESS for the current engine.
4444  *
4445  * should be run under rtnl lock
4446  */
4447 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4448 {
4449         u32 val;
4450         u32 bit = BP_PATH(bp) ?
4451                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4452         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4453         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4454
4455         /* Set the bit */
4456         val |= bit;
4457         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4458         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4459 }
4460
4461 /*
4462  * Checks the RESET_IN_PROGRESS bit for the given engine.
4463  * should be run under rtnl lock
4464  */
4465 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4466 {
4467         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4468         u32 bit = engine ?
4469                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4470
4471         /* return false if bit is set */
4472         return (val & bit) ? false : true;
4473 }
4474
4475 /*
4476  * set pf load for the current pf.
4477  *
4478  * should be run under rtnl lock
4479  */
4480 void bnx2x_set_pf_load(struct bnx2x *bp)
4481 {
4482         u32 val1, val;
4483         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4484                              BNX2X_PATH0_LOAD_CNT_MASK;
4485         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4486                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4487
4488         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4489         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4490
4491         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4492
4493         /* get the current counter value */
4494         val1 = (val & mask) >> shift;
4495
4496         /* set bit of that PF */
4497         val1 |= (1 << bp->pf_num);
4498
4499         /* clear the old value */
4500         val &= ~mask;
4501
4502         /* set the new one */
4503         val |= ((val1 << shift) & mask);
4504
4505         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4506         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4507 }
4508
4509 /**
4510  * bnx2x_clear_pf_load - clear pf load mark
4511  *
4512  * @bp:         driver handle
4513  *
4514  * Should be run under rtnl lock.
4515  * Decrements the load counter for the current engine. Returns
4516  * whether other functions are still loaded
4517  */
4518 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4519 {
4520         u32 val1, val;
4521         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4522                              BNX2X_PATH0_LOAD_CNT_MASK;
4523         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4524                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4525
4526         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4527         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4528         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4529
4530         /* get the current counter value */
4531         val1 = (val & mask) >> shift;
4532
4533         /* clear bit of that PF */
4534         val1 &= ~(1 << bp->pf_num);
4535
4536         /* clear the old value */
4537         val &= ~mask;
4538
4539         /* set the new one */
4540         val |= ((val1 << shift) & mask);
4541
4542         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4543         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4544         return val1 != 0;
4545 }
4546
4547 /*
4548  * Read the load status for the current engine.
4549  *
4550  * should be run under rtnl lock
4551  */
4552 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4553 {
4554         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4555                              BNX2X_PATH0_LOAD_CNT_MASK);
4556         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4557                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4558         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4559
4560         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4561
4562         val = (val & mask) >> shift;
4563
4564         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4565            engine, val);
4566
4567         return val != 0;
4568 }
4569
4570 static void _print_parity(struct bnx2x *bp, u32 reg)
4571 {
4572         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4573 }
4574
4575 static void _print_next_block(int idx, const char *blk)
4576 {
4577         pr_cont("%s%s", idx ? ", " : "", blk);
4578 }
4579
4580 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4581                                             int *par_num, bool print)
4582 {
4583         u32 cur_bit;
4584         bool res;
4585         int i;
4586
4587         res = false;
4588
4589         for (i = 0; sig; i++) {
4590                 cur_bit = (0x1UL << i);
4591                 if (sig & cur_bit) {
4592                         res |= true; /* Each bit is real error! */
4593
4594                         if (print) {
4595                                 switch (cur_bit) {
4596                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4597                                         _print_next_block((*par_num)++, "BRB");
4598                                         _print_parity(bp,
4599                                                       BRB1_REG_BRB1_PRTY_STS);
4600                                         break;
4601                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4602                                         _print_next_block((*par_num)++,
4603                                                           "PARSER");
4604                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4605                                         break;
4606                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4607                                         _print_next_block((*par_num)++, "TSDM");
4608                                         _print_parity(bp,
4609                                                       TSDM_REG_TSDM_PRTY_STS);
4610                                         break;
4611                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4612                                         _print_next_block((*par_num)++,
4613                                                           "SEARCHER");
4614                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4615                                         break;
4616                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4617                                         _print_next_block((*par_num)++, "TCM");
4618                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4619                                         break;
4620                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4621                                         _print_next_block((*par_num)++,
4622                                                           "TSEMI");
4623                                         _print_parity(bp,
4624                                                       TSEM_REG_TSEM_PRTY_STS_0);
4625                                         _print_parity(bp,
4626                                                       TSEM_REG_TSEM_PRTY_STS_1);
4627                                         break;
4628                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4629                                         _print_next_block((*par_num)++, "XPB");
4630                                         _print_parity(bp, GRCBASE_XPB +
4631                                                           PB_REG_PB_PRTY_STS);
4632                                         break;
4633                                 }
4634                         }
4635
4636                         /* Clear the bit */
4637                         sig &= ~cur_bit;
4638                 }
4639         }
4640
4641         return res;
4642 }
4643
4644 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4645                                             int *par_num, bool *global,
4646                                             bool print)
4647 {
4648         u32 cur_bit;
4649         bool res;
4650         int i;
4651
4652         res = false;
4653
4654         for (i = 0; sig; i++) {
4655                 cur_bit = (0x1UL << i);
4656                 if (sig & cur_bit) {
4657                         res |= true; /* Each bit is real error! */
4658                         switch (cur_bit) {
4659                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4660                                 if (print) {
4661                                         _print_next_block((*par_num)++, "PBF");
4662                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4663                                 }
4664                                 break;
4665                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4666                                 if (print) {
4667                                         _print_next_block((*par_num)++, "QM");
4668                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4669                                 }
4670                                 break;
4671                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4672                                 if (print) {
4673                                         _print_next_block((*par_num)++, "TM");
4674                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4675                                 }
4676                                 break;
4677                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4678                                 if (print) {
4679                                         _print_next_block((*par_num)++, "XSDM");
4680                                         _print_parity(bp,
4681                                                       XSDM_REG_XSDM_PRTY_STS);
4682                                 }
4683                                 break;
4684                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4685                                 if (print) {
4686                                         _print_next_block((*par_num)++, "XCM");
4687                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4688                                 }
4689                                 break;
4690                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4691                                 if (print) {
4692                                         _print_next_block((*par_num)++,
4693                                                           "XSEMI");
4694                                         _print_parity(bp,
4695                                                       XSEM_REG_XSEM_PRTY_STS_0);
4696                                         _print_parity(bp,
4697                                                       XSEM_REG_XSEM_PRTY_STS_1);
4698                                 }
4699                                 break;
4700                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4701                                 if (print) {
4702                                         _print_next_block((*par_num)++,
4703                                                           "DOORBELLQ");
4704                                         _print_parity(bp,
4705                                                       DORQ_REG_DORQ_PRTY_STS);
4706                                 }
4707                                 break;
4708                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4709                                 if (print) {
4710                                         _print_next_block((*par_num)++, "NIG");
4711                                         if (CHIP_IS_E1x(bp)) {
4712                                                 _print_parity(bp,
4713                                                         NIG_REG_NIG_PRTY_STS);
4714                                         } else {
4715                                                 _print_parity(bp,
4716                                                         NIG_REG_NIG_PRTY_STS_0);
4717                                                 _print_parity(bp,
4718                                                         NIG_REG_NIG_PRTY_STS_1);
4719                                         }
4720                                 }
4721                                 break;
4722                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4723                                 if (print)
4724                                         _print_next_block((*par_num)++,
4725                                                           "VAUX PCI CORE");
4726                                 *global = true;
4727                                 break;
4728                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4729                                 if (print) {
4730                                         _print_next_block((*par_num)++,
4731                                                           "DEBUG");
4732                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4733                                 }
4734                                 break;
4735                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4736                                 if (print) {
4737                                         _print_next_block((*par_num)++, "USDM");
4738                                         _print_parity(bp,
4739                                                       USDM_REG_USDM_PRTY_STS);
4740                                 }
4741                                 break;
4742                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4743                                 if (print) {
4744                                         _print_next_block((*par_num)++, "UCM");
4745                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4746                                 }
4747                                 break;
4748                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4749                                 if (print) {
4750                                         _print_next_block((*par_num)++,
4751                                                           "USEMI");
4752                                         _print_parity(bp,
4753                                                       USEM_REG_USEM_PRTY_STS_0);
4754                                         _print_parity(bp,
4755                                                       USEM_REG_USEM_PRTY_STS_1);
4756                                 }
4757                                 break;
4758                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4759                                 if (print) {
4760                                         _print_next_block((*par_num)++, "UPB");
4761                                         _print_parity(bp, GRCBASE_UPB +
4762                                                           PB_REG_PB_PRTY_STS);
4763                                 }
4764                                 break;
4765                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4766                                 if (print) {
4767                                         _print_next_block((*par_num)++, "CSDM");
4768                                         _print_parity(bp,
4769                                                       CSDM_REG_CSDM_PRTY_STS);
4770                                 }
4771                                 break;
4772                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4773                                 if (print) {
4774                                         _print_next_block((*par_num)++, "CCM");
4775                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4776                                 }
4777                                 break;
4778                         }
4779
4780                         /* Clear the bit */
4781                         sig &= ~cur_bit;
4782                 }
4783         }
4784
4785         return res;
4786 }
4787
4788 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4789                                             int *par_num, bool print)
4790 {
4791         u32 cur_bit;
4792         bool res;
4793         int i;
4794
4795         res = false;
4796
4797         for (i = 0; sig; i++) {
4798                 cur_bit = (0x1UL << i);
4799                 if (sig & cur_bit) {
4800                         res = true; /* Each bit is real error! */
4801                         if (print) {
4802                                 switch (cur_bit) {
4803                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4804                                         _print_next_block((*par_num)++,
4805                                                           "CSEMI");
4806                                         _print_parity(bp,
4807                                                       CSEM_REG_CSEM_PRTY_STS_0);
4808                                         _print_parity(bp,
4809                                                       CSEM_REG_CSEM_PRTY_STS_1);
4810                                         break;
4811                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4812                                         _print_next_block((*par_num)++, "PXP");
4813                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4814                                         _print_parity(bp,
4815                                                       PXP2_REG_PXP2_PRTY_STS_0);
4816                                         _print_parity(bp,
4817                                                       PXP2_REG_PXP2_PRTY_STS_1);
4818                                         break;
4819                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4820                                         _print_next_block((*par_num)++,
4821                                                           "PXPPCICLOCKCLIENT");
4822                                         break;
4823                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4824                                         _print_next_block((*par_num)++, "CFC");
4825                                         _print_parity(bp,
4826                                                       CFC_REG_CFC_PRTY_STS);
4827                                         break;
4828                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4829                                         _print_next_block((*par_num)++, "CDU");
4830                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4831                                         break;
4832                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4833                                         _print_next_block((*par_num)++, "DMAE");
4834                                         _print_parity(bp,
4835                                                       DMAE_REG_DMAE_PRTY_STS);
4836                                         break;
4837                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4838                                         _print_next_block((*par_num)++, "IGU");
4839                                         if (CHIP_IS_E1x(bp))
4840                                                 _print_parity(bp,
4841                                                         HC_REG_HC_PRTY_STS);
4842                                         else
4843                                                 _print_parity(bp,
4844                                                         IGU_REG_IGU_PRTY_STS);
4845                                         break;
4846                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4847                                         _print_next_block((*par_num)++, "MISC");
4848                                         _print_parity(bp,
4849                                                       MISC_REG_MISC_PRTY_STS);
4850                                         break;
4851                                 }
4852                         }
4853
4854                         /* Clear the bit */
4855                         sig &= ~cur_bit;
4856                 }
4857         }
4858
4859         return res;
4860 }
4861
4862 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4863                                             int *par_num, bool *global,
4864                                             bool print)
4865 {
4866         bool res = false;
4867         u32 cur_bit;
4868         int i;
4869
4870         for (i = 0; sig; i++) {
4871                 cur_bit = (0x1UL << i);
4872                 if (sig & cur_bit) {
4873                         switch (cur_bit) {
4874                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4875                                 if (print)
4876                                         _print_next_block((*par_num)++,
4877                                                           "MCP ROM");
4878                                 *global = true;
4879                                 res = true;
4880                                 break;
4881                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4882                                 if (print)
4883                                         _print_next_block((*par_num)++,
4884                                                           "MCP UMP RX");
4885                                 *global = true;
4886                                 res = true;
4887                                 break;
4888                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4889                                 if (print)
4890                                         _print_next_block((*par_num)++,
4891                                                           "MCP UMP TX");
4892                                 *global = true;
4893                                 res = true;
4894                                 break;
4895                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4896                                 (*par_num)++;
4897                                 /* clear latched SCPAD PATIRY from MCP */
4898                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4899                                        1UL << 10);
4900                                 break;
4901                         }
4902
4903                         /* Clear the bit */
4904                         sig &= ~cur_bit;
4905                 }
4906         }
4907
4908         return res;
4909 }
4910
4911 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4912                                             int *par_num, bool print)
4913 {
4914         u32 cur_bit;
4915         bool res;
4916         int i;
4917
4918         res = false;
4919
4920         for (i = 0; sig; i++) {
4921                 cur_bit = (0x1UL << i);
4922                 if (sig & cur_bit) {
4923                         res = true; /* Each bit is real error! */
4924                         if (print) {
4925                                 switch (cur_bit) {
4926                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4927                                         _print_next_block((*par_num)++,
4928                                                           "PGLUE_B");
4929                                         _print_parity(bp,
4930                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4931                                         break;
4932                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4933                                         _print_next_block((*par_num)++, "ATC");
4934                                         _print_parity(bp,
4935                                                       ATC_REG_ATC_PRTY_STS);
4936                                         break;
4937                                 }
4938                         }
4939                         /* Clear the bit */
4940                         sig &= ~cur_bit;
4941                 }
4942         }
4943
4944         return res;
4945 }
4946
4947 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4948                               u32 *sig)
4949 {
4950         bool res = false;
4951
4952         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4953             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4954             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4955             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4956             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4957                 int par_num = 0;
4958
4959                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4960                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4961                           sig[0] & HW_PRTY_ASSERT_SET_0,
4962                           sig[1] & HW_PRTY_ASSERT_SET_1,
4963                           sig[2] & HW_PRTY_ASSERT_SET_2,
4964                           sig[3] & HW_PRTY_ASSERT_SET_3,
4965                           sig[4] & HW_PRTY_ASSERT_SET_4);
4966                 if (print) {
4967                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4968                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4969                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4970                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4971                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4972                                 netdev_err(bp->dev,
4973                                            "Parity errors detected in blocks: ");
4974                         } else {
4975                                 print = false;
4976                         }
4977                 }
4978                 res |= bnx2x_check_blocks_with_parity0(bp,
4979                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4980                 res |= bnx2x_check_blocks_with_parity1(bp,
4981                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4982                 res |= bnx2x_check_blocks_with_parity2(bp,
4983                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4984                 res |= bnx2x_check_blocks_with_parity3(bp,
4985                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4986                 res |= bnx2x_check_blocks_with_parity4(bp,
4987                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4988
4989                 if (print)
4990                         pr_cont("\n");
4991         }
4992
4993         return res;
4994 }
4995
4996 /**
4997  * bnx2x_chk_parity_attn - checks for parity attentions.
4998  *
4999  * @bp:         driver handle
5000  * @global:     true if there was a global attention
5001  * @print:      show parity attention in syslog
5002  */
5003 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5004 {
5005         struct attn_route attn = { {0} };
5006         int port = BP_PORT(bp);
5007
5008         attn.sig[0] = REG_RD(bp,
5009                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5010                              port*4);
5011         attn.sig[1] = REG_RD(bp,
5012                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5013                              port*4);
5014         attn.sig[2] = REG_RD(bp,
5015                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5016                              port*4);
5017         attn.sig[3] = REG_RD(bp,
5018                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5019                              port*4);
5020         /* Since MCP attentions can't be disabled inside the block, we need to
5021          * read AEU registers to see whether they're currently disabled
5022          */
5023         attn.sig[3] &= ((REG_RD(bp,
5024                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5025                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5026                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5027                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5028
5029         if (!CHIP_IS_E1x(bp))
5030                 attn.sig[4] = REG_RD(bp,
5031                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5032                                      port*4);
5033
5034         return bnx2x_parity_attn(bp, global, print, attn.sig);
5035 }
5036
5037 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5038 {
5039         u32 val;
5040         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5041
5042                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5043                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5044                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5045                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5046                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5047                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5048                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5049                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5050                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5051                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5052                 if (val &
5053                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5054                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5055                 if (val &
5056                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5057                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5058                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5059                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5060                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5061                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5062                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5063                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5064         }
5065         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5066                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5067                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5068                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5069                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5070                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5071                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5072                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5073                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5074                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5075                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5076                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5077                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5078                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5079                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5080         }
5081
5082         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5083                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5084                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5085                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5086                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5087         }
5088 }
5089
5090 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5091 {
5092         struct attn_route attn, *group_mask;
5093         int port = BP_PORT(bp);
5094         int index;
5095         u32 reg_addr;
5096         u32 val;
5097         u32 aeu_mask;
5098         bool global = false;
5099
5100         /* need to take HW lock because MCP or other port might also
5101            try to handle this event */
5102         bnx2x_acquire_alr(bp);
5103
5104         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5105 #ifndef BNX2X_STOP_ON_ERROR
5106                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5107                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5108                 /* Disable HW interrupts */
5109                 bnx2x_int_disable(bp);
5110                 /* In case of parity errors don't handle attentions so that
5111                  * other function would "see" parity errors.
5112                  */
5113 #else
5114                 bnx2x_panic();
5115 #endif
5116                 bnx2x_release_alr(bp);
5117                 return;
5118         }
5119
5120         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5121         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5122         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5123         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5124         if (!CHIP_IS_E1x(bp))
5125                 attn.sig[4] =
5126                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5127         else
5128                 attn.sig[4] = 0;
5129
5130         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5131            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5132
5133         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5134                 if (deasserted & (1 << index)) {
5135                         group_mask = &bp->attn_group[index];
5136
5137                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5138                            index,
5139                            group_mask->sig[0], group_mask->sig[1],
5140                            group_mask->sig[2], group_mask->sig[3],
5141                            group_mask->sig[4]);
5142
5143                         bnx2x_attn_int_deasserted4(bp,
5144                                         attn.sig[4] & group_mask->sig[4]);
5145                         bnx2x_attn_int_deasserted3(bp,
5146                                         attn.sig[3] & group_mask->sig[3]);
5147                         bnx2x_attn_int_deasserted1(bp,
5148                                         attn.sig[1] & group_mask->sig[1]);
5149                         bnx2x_attn_int_deasserted2(bp,
5150                                         attn.sig[2] & group_mask->sig[2]);
5151                         bnx2x_attn_int_deasserted0(bp,
5152                                         attn.sig[0] & group_mask->sig[0]);
5153                 }
5154         }
5155
5156         bnx2x_release_alr(bp);
5157
5158         if (bp->common.int_block == INT_BLOCK_HC)
5159                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5160                             COMMAND_REG_ATTN_BITS_CLR);
5161         else
5162                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5163
5164         val = ~deasserted;
5165         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5166            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5167         REG_WR(bp, reg_addr, val);
5168
5169         if (~bp->attn_state & deasserted)
5170                 BNX2X_ERR("IGU ERROR\n");
5171
5172         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5173                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5174
5175         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5176         aeu_mask = REG_RD(bp, reg_addr);
5177
5178         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5179            aeu_mask, deasserted);
5180         aeu_mask |= (deasserted & 0x3ff);
5181         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5182
5183         REG_WR(bp, reg_addr, aeu_mask);
5184         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5185
5186         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5187         bp->attn_state &= ~deasserted;
5188         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5189 }
5190
5191 static void bnx2x_attn_int(struct bnx2x *bp)
5192 {
5193         /* read local copy of bits */
5194         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5195                                                                 attn_bits);
5196         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5197                                                                 attn_bits_ack);
5198         u32 attn_state = bp->attn_state;
5199
5200         /* look for changed bits */
5201         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5202         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5203
5204         DP(NETIF_MSG_HW,
5205            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5206            attn_bits, attn_ack, asserted, deasserted);
5207
5208         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5209                 BNX2X_ERR("BAD attention state\n");
5210
5211         /* handle bits that were raised */
5212         if (asserted)
5213                 bnx2x_attn_int_asserted(bp, asserted);
5214
5215         if (deasserted)
5216                 bnx2x_attn_int_deasserted(bp, deasserted);
5217 }
5218
5219 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5220                       u16 index, u8 op, u8 update)
5221 {
5222         u32 igu_addr = bp->igu_base_addr;
5223         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5224         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5225                              igu_addr);
5226 }
5227
5228 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5229 {
5230         /* No memory barriers */
5231         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5232         mmiowb(); /* keep prod updates ordered */
5233 }
5234
5235 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5236                                       union event_ring_elem *elem)
5237 {
5238         u8 err = elem->message.error;
5239
5240         if (!bp->cnic_eth_dev.starting_cid  ||
5241             (cid < bp->cnic_eth_dev.starting_cid &&
5242             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5243                 return 1;
5244
5245         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5246
5247         if (unlikely(err)) {
5248
5249                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5250                           cid);
5251                 bnx2x_panic_dump(bp, false);
5252         }
5253         bnx2x_cnic_cfc_comp(bp, cid, err);
5254         return 0;
5255 }
5256
5257 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5258 {
5259         struct bnx2x_mcast_ramrod_params rparam;
5260         int rc;
5261
5262         memset(&rparam, 0, sizeof(rparam));
5263
5264         rparam.mcast_obj = &bp->mcast_obj;
5265
5266         netif_addr_lock_bh(bp->dev);
5267
5268         /* Clear pending state for the last command */
5269         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5270
5271         /* If there are pending mcast commands - send them */
5272         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5273                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5274                 if (rc < 0)
5275                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5276                                   rc);
5277         }
5278
5279         netif_addr_unlock_bh(bp->dev);
5280 }
5281
5282 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5283                                             union event_ring_elem *elem)
5284 {
5285         unsigned long ramrod_flags = 0;
5286         int rc = 0;
5287         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5288         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5289
5290         /* Always push next commands out, don't wait here */
5291         __set_bit(RAMROD_CONT, &ramrod_flags);
5292
5293         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5294                             >> BNX2X_SWCID_SHIFT) {
5295         case BNX2X_FILTER_MAC_PENDING:
5296                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5297                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5298                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5299                 else
5300                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5301
5302                 break;
5303         case BNX2X_FILTER_VLAN_PENDING:
5304                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5305                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5306                 break;
5307         case BNX2X_FILTER_MCAST_PENDING:
5308                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5309                 /* This is only relevant for 57710 where multicast MACs are
5310                  * configured as unicast MACs using the same ramrod.
5311                  */
5312                 bnx2x_handle_mcast_eqe(bp);
5313                 return;
5314         default:
5315                 BNX2X_ERR("Unsupported classification command: %d\n",
5316                           elem->message.data.eth_event.echo);
5317                 return;
5318         }
5319
5320         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5321
5322         if (rc < 0)
5323                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5324         else if (rc > 0)
5325                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5326 }
5327
5328 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5329
5330 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5331 {
5332         netif_addr_lock_bh(bp->dev);
5333
5334         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5335
5336         /* Send rx_mode command again if was requested */
5337         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5338                 bnx2x_set_storm_rx_mode(bp);
5339         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5340                                     &bp->sp_state))
5341                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5342         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5343                                     &bp->sp_state))
5344                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5345
5346         netif_addr_unlock_bh(bp->dev);
5347 }
5348
5349 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5350                                               union event_ring_elem *elem)
5351 {
5352         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5353                 DP(BNX2X_MSG_SP,
5354                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5355                    elem->message.data.vif_list_event.func_bit_map);
5356                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5357                         elem->message.data.vif_list_event.func_bit_map);
5358         } else if (elem->message.data.vif_list_event.echo ==
5359                    VIF_LIST_RULE_SET) {
5360                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5361                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5362         }
5363 }
5364
5365 /* called with rtnl_lock */
5366 static void bnx2x_after_function_update(struct bnx2x *bp)
5367 {
5368         int q, rc;
5369         struct bnx2x_fastpath *fp;
5370         struct bnx2x_queue_state_params queue_params = {NULL};
5371         struct bnx2x_queue_update_params *q_update_params =
5372                 &queue_params.params.update;
5373
5374         /* Send Q update command with afex vlan removal values for all Qs */
5375         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5376
5377         /* set silent vlan removal values according to vlan mode */
5378         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5379                   &q_update_params->update_flags);
5380         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5381                   &q_update_params->update_flags);
5382         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5383
5384         /* in access mode mark mask and value are 0 to strip all vlans */
5385         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5386                 q_update_params->silent_removal_value = 0;
5387                 q_update_params->silent_removal_mask = 0;
5388         } else {
5389                 q_update_params->silent_removal_value =
5390                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5391                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5392         }
5393
5394         for_each_eth_queue(bp, q) {
5395                 /* Set the appropriate Queue object */
5396                 fp = &bp->fp[q];
5397                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5398
5399                 /* send the ramrod */
5400                 rc = bnx2x_queue_state_change(bp, &queue_params);
5401                 if (rc < 0)
5402                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5403                                   q);
5404         }
5405
5406         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5407                 fp = &bp->fp[FCOE_IDX(bp)];
5408                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5409
5410                 /* clear pending completion bit */
5411                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5412
5413                 /* mark latest Q bit */
5414                 smp_mb__before_atomic();
5415                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5416                 smp_mb__after_atomic();
5417
5418                 /* send Q update ramrod for FCoE Q */
5419                 rc = bnx2x_queue_state_change(bp, &queue_params);
5420                 if (rc < 0)
5421                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5422                                   q);
5423         } else {
5424                 /* If no FCoE ring - ACK MCP now */
5425                 bnx2x_link_report(bp);
5426                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5427         }
5428 }
5429
5430 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5431         struct bnx2x *bp, u32 cid)
5432 {
5433         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5434
5435         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5436                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5437         else
5438                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5439 }
5440
5441 static void bnx2x_eq_int(struct bnx2x *bp)
5442 {
5443         u16 hw_cons, sw_cons, sw_prod;
5444         union event_ring_elem *elem;
5445         u8 echo;
5446         u32 cid;
5447         u8 opcode;
5448         int rc, spqe_cnt = 0;
5449         struct bnx2x_queue_sp_obj *q_obj;
5450         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5451         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5452
5453         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5454
5455         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5456          * when we get the next-page we need to adjust so the loop
5457          * condition below will be met. The next element is the size of a
5458          * regular element and hence incrementing by 1
5459          */
5460         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5461                 hw_cons++;
5462
5463         /* This function may never run in parallel with itself for a
5464          * specific bp, thus there is no need in "paired" read memory
5465          * barrier here.
5466          */
5467         sw_cons = bp->eq_cons;
5468         sw_prod = bp->eq_prod;
5469
5470         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5471                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5472
5473         for (; sw_cons != hw_cons;
5474               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5475
5476                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5477
5478                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5479                 if (!rc) {
5480                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5481                            rc);
5482                         goto next_spqe;
5483                 }
5484
5485                 /* elem CID originates from FW; actually LE */
5486                 cid = SW_CID((__force __le32)
5487                              elem->message.data.cfc_del_event.cid);
5488                 opcode = elem->message.opcode;
5489
5490                 /* handle eq element */
5491                 switch (opcode) {
5492                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5493                         bnx2x_vf_mbx_schedule(bp,
5494                                               &elem->message.data.vf_pf_event);
5495                         continue;
5496
5497                 case EVENT_RING_OPCODE_STAT_QUERY:
5498                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5499                                "got statistics comp event %d\n",
5500                                bp->stats_comp++);
5501                         /* nothing to do with stats comp */
5502                         goto next_spqe;
5503
5504                 case EVENT_RING_OPCODE_CFC_DEL:
5505                         /* handle according to cid range */
5506                         /*
5507                          * we may want to verify here that the bp state is
5508                          * HALTING
5509                          */
5510                         DP(BNX2X_MSG_SP,
5511                            "got delete ramrod for MULTI[%d]\n", cid);
5512
5513                         if (CNIC_LOADED(bp) &&
5514                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5515                                 goto next_spqe;
5516
5517                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5518
5519                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5520                                 break;
5521
5522                         goto next_spqe;
5523
5524                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5525                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5526                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5527                         if (f_obj->complete_cmd(bp, f_obj,
5528                                                 BNX2X_F_CMD_TX_STOP))
5529                                 break;
5530                         goto next_spqe;
5531
5532                 case EVENT_RING_OPCODE_START_TRAFFIC:
5533                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5534                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5535                         if (f_obj->complete_cmd(bp, f_obj,
5536                                                 BNX2X_F_CMD_TX_START))
5537                                 break;
5538                         goto next_spqe;
5539
5540                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5541                         echo = elem->message.data.function_update_event.echo;
5542                         if (echo == SWITCH_UPDATE) {
5543                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5544                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5545                                 if (f_obj->complete_cmd(
5546                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5547                                         break;
5548
5549                         } else {
5550                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5551
5552                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5553                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5554                                 f_obj->complete_cmd(bp, f_obj,
5555                                                     BNX2X_F_CMD_AFEX_UPDATE);
5556
5557                                 /* We will perform the Queues update from
5558                                  * sp_rtnl task as all Queue SP operations
5559                                  * should run under rtnl_lock.
5560                                  */
5561                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5562                         }
5563
5564                         goto next_spqe;
5565
5566                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5567                         f_obj->complete_cmd(bp, f_obj,
5568                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5569                         bnx2x_after_afex_vif_lists(bp, elem);
5570                         goto next_spqe;
5571                 case EVENT_RING_OPCODE_FUNCTION_START:
5572                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5573                            "got FUNC_START ramrod\n");
5574                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5575                                 break;
5576
5577                         goto next_spqe;
5578
5579                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5580                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5581                            "got FUNC_STOP ramrod\n");
5582                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5583                                 break;
5584
5585                         goto next_spqe;
5586
5587                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5588                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5589                            "got set_timesync ramrod completion\n");
5590                         if (f_obj->complete_cmd(bp, f_obj,
5591                                                 BNX2X_F_CMD_SET_TIMESYNC))
5592                                 break;
5593                         goto next_spqe;
5594                 }
5595
5596                 switch (opcode | bp->state) {
5597                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598                       BNX2X_STATE_OPEN):
5599                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5600                       BNX2X_STATE_OPENING_WAIT4_PORT):
5601                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5602                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5603                         cid = elem->message.data.eth_event.echo &
5604                                 BNX2X_SWCID_MASK;
5605                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5606                            cid);
5607                         rss_raw->clear_pending(rss_raw);
5608                         break;
5609
5610                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5611                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5612                 case (EVENT_RING_OPCODE_SET_MAC |
5613                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5614                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615                       BNX2X_STATE_OPEN):
5616                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5617                       BNX2X_STATE_DIAG):
5618                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5619                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5620                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5621                         bnx2x_handle_classification_eqe(bp, elem);
5622                         break;
5623
5624                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625                       BNX2X_STATE_OPEN):
5626                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5627                       BNX2X_STATE_DIAG):
5628                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5629                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5630                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5631                         bnx2x_handle_mcast_eqe(bp);
5632                         break;
5633
5634                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5635                       BNX2X_STATE_OPEN):
5636                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5637                       BNX2X_STATE_DIAG):
5638                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5639                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5640                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5641                         bnx2x_handle_rx_mode_eqe(bp);
5642                         break;
5643                 default:
5644                         /* unknown event log error and continue */
5645                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5646                                   elem->message.opcode, bp->state);
5647                 }
5648 next_spqe:
5649                 spqe_cnt++;
5650         } /* for */
5651
5652         smp_mb__before_atomic();
5653         atomic_add(spqe_cnt, &bp->eq_spq_left);
5654
5655         bp->eq_cons = sw_cons;
5656         bp->eq_prod = sw_prod;
5657         /* Make sure that above mem writes were issued towards the memory */
5658         smp_wmb();
5659
5660         /* update producer */
5661         bnx2x_update_eq_prod(bp, bp->eq_prod);
5662 }
5663
5664 static void bnx2x_sp_task(struct work_struct *work)
5665 {
5666         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5667
5668         DP(BNX2X_MSG_SP, "sp task invoked\n");
5669
5670         /* make sure the atomic interrupt_occurred has been written */
5671         smp_rmb();
5672         if (atomic_read(&bp->interrupt_occurred)) {
5673
5674                 /* what work needs to be performed? */
5675                 u16 status = bnx2x_update_dsb_idx(bp);
5676
5677                 DP(BNX2X_MSG_SP, "status %x\n", status);
5678                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5679                 atomic_set(&bp->interrupt_occurred, 0);
5680
5681                 /* HW attentions */
5682                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5683                         bnx2x_attn_int(bp);
5684                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5685                 }
5686
5687                 /* SP events: STAT_QUERY and others */
5688                 if (status & BNX2X_DEF_SB_IDX) {
5689                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5690
5691                 if (FCOE_INIT(bp) &&
5692                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5693                                 /* Prevent local bottom-halves from running as
5694                                  * we are going to change the local NAPI list.
5695                                  */
5696                                 local_bh_disable();
5697                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5698                                 local_bh_enable();
5699                         }
5700
5701                         /* Handle EQ completions */
5702                         bnx2x_eq_int(bp);
5703                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5704                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5705
5706                         status &= ~BNX2X_DEF_SB_IDX;
5707                 }
5708
5709                 /* if status is non zero then perhaps something went wrong */
5710                 if (unlikely(status))
5711                         DP(BNX2X_MSG_SP,
5712                            "got an unknown interrupt! (status 0x%x)\n", status);
5713
5714                 /* ack status block only if something was actually handled */
5715                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5716                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5717         }
5718
5719         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5720         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5721                                &bp->sp_state)) {
5722                 bnx2x_link_report(bp);
5723                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5724         }
5725 }
5726
5727 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5728 {
5729         struct net_device *dev = dev_instance;
5730         struct bnx2x *bp = netdev_priv(dev);
5731
5732         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5733                      IGU_INT_DISABLE, 0);
5734
5735 #ifdef BNX2X_STOP_ON_ERROR
5736         if (unlikely(bp->panic))
5737                 return IRQ_HANDLED;
5738 #endif
5739
5740         if (CNIC_LOADED(bp)) {
5741                 struct cnic_ops *c_ops;
5742
5743                 rcu_read_lock();
5744                 c_ops = rcu_dereference(bp->cnic_ops);
5745                 if (c_ops)
5746                         c_ops->cnic_handler(bp->cnic_data, NULL);
5747                 rcu_read_unlock();
5748         }
5749
5750         /* schedule sp task to perform default status block work, ack
5751          * attentions and enable interrupts.
5752          */
5753         bnx2x_schedule_sp_task(bp);
5754
5755         return IRQ_HANDLED;
5756 }
5757
5758 /* end of slow path */
5759
5760 void bnx2x_drv_pulse(struct bnx2x *bp)
5761 {
5762         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5763                  bp->fw_drv_pulse_wr_seq);
5764 }
5765
5766 static void bnx2x_timer(unsigned long data)
5767 {
5768         struct bnx2x *bp = (struct bnx2x *) data;
5769
5770         if (!netif_running(bp->dev))
5771                 return;
5772
5773         if (IS_PF(bp) &&
5774             !BP_NOMCP(bp)) {
5775                 int mb_idx = BP_FW_MB_IDX(bp);
5776                 u16 drv_pulse;
5777                 u16 mcp_pulse;
5778
5779                 ++bp->fw_drv_pulse_wr_seq;
5780                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5781                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5782                 bnx2x_drv_pulse(bp);
5783
5784                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5785                              MCP_PULSE_SEQ_MASK);
5786                 /* The delta between driver pulse and mcp response
5787                  * should not get too big. If the MFW is more than 5 pulses
5788                  * behind, we should worry about it enough to generate an error
5789                  * log.
5790                  */
5791                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5792                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5793                                   drv_pulse, mcp_pulse);
5794         }
5795
5796         if (bp->state == BNX2X_STATE_OPEN)
5797                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5798
5799         /* sample pf vf bulletin board for new posts from pf */
5800         if (IS_VF(bp))
5801                 bnx2x_timer_sriov(bp);
5802
5803         mod_timer(&bp->timer, jiffies + bp->current_interval);
5804 }
5805
5806 /* end of Statistics */
5807
5808 /* nic init */
5809
5810 /*
5811  * nic init service functions
5812  */
5813
5814 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5815 {
5816         u32 i;
5817         if (!(len%4) && !(addr%4))
5818                 for (i = 0; i < len; i += 4)
5819                         REG_WR(bp, addr + i, fill);
5820         else
5821                 for (i = 0; i < len; i++)
5822                         REG_WR8(bp, addr + i, fill);
5823 }
5824
5825 /* helper: writes FP SP data to FW - data_size in dwords */
5826 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5827                                 int fw_sb_id,
5828                                 u32 *sb_data_p,
5829                                 u32 data_size)
5830 {
5831         int index;
5832         for (index = 0; index < data_size; index++)
5833                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5834                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5835                         sizeof(u32)*index,
5836                         *(sb_data_p + index));
5837 }
5838
5839 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5840 {
5841         u32 *sb_data_p;
5842         u32 data_size = 0;
5843         struct hc_status_block_data_e2 sb_data_e2;
5844         struct hc_status_block_data_e1x sb_data_e1x;
5845
5846         /* disable the function first */
5847         if (!CHIP_IS_E1x(bp)) {
5848                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5849                 sb_data_e2.common.state = SB_DISABLED;
5850                 sb_data_e2.common.p_func.vf_valid = false;
5851                 sb_data_p = (u32 *)&sb_data_e2;
5852                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5853         } else {
5854                 memset(&sb_data_e1x, 0,
5855                        sizeof(struct hc_status_block_data_e1x));
5856                 sb_data_e1x.common.state = SB_DISABLED;
5857                 sb_data_e1x.common.p_func.vf_valid = false;
5858                 sb_data_p = (u32 *)&sb_data_e1x;
5859                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5860         }
5861         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5862
5863         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5864                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5865                         CSTORM_STATUS_BLOCK_SIZE);
5866         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5867                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5868                         CSTORM_SYNC_BLOCK_SIZE);
5869 }
5870
5871 /* helper:  writes SP SB data to FW */
5872 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5873                 struct hc_sp_status_block_data *sp_sb_data)
5874 {
5875         int func = BP_FUNC(bp);
5876         int i;
5877         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5878                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5879                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5880                         i*sizeof(u32),
5881                         *((u32 *)sp_sb_data + i));
5882 }
5883
5884 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5885 {
5886         int func = BP_FUNC(bp);
5887         struct hc_sp_status_block_data sp_sb_data;
5888         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5889
5890         sp_sb_data.state = SB_DISABLED;
5891         sp_sb_data.p_func.vf_valid = false;
5892
5893         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5894
5895         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5896                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5897                         CSTORM_SP_STATUS_BLOCK_SIZE);
5898         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5899                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5900                         CSTORM_SP_SYNC_BLOCK_SIZE);
5901 }
5902
5903 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5904                                            int igu_sb_id, int igu_seg_id)
5905 {
5906         hc_sm->igu_sb_id = igu_sb_id;
5907         hc_sm->igu_seg_id = igu_seg_id;
5908         hc_sm->timer_value = 0xFF;
5909         hc_sm->time_to_expire = 0xFFFFFFFF;
5910 }
5911
5912 /* allocates state machine ids. */
5913 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5914 {
5915         /* zero out state machine indices */
5916         /* rx indices */
5917         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5918
5919         /* tx indices */
5920         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5921         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5922         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5923         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5924
5925         /* map indices */
5926         /* rx indices */
5927         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5928                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929
5930         /* tx indices */
5931         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5932                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5934                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5936                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5937         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5938                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5939 }
5940
5941 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5942                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5943 {
5944         int igu_seg_id;
5945
5946         struct hc_status_block_data_e2 sb_data_e2;
5947         struct hc_status_block_data_e1x sb_data_e1x;
5948         struct hc_status_block_sm  *hc_sm_p;
5949         int data_size;
5950         u32 *sb_data_p;
5951
5952         if (CHIP_INT_MODE_IS_BC(bp))
5953                 igu_seg_id = HC_SEG_ACCESS_NORM;
5954         else
5955                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5956
5957         bnx2x_zero_fp_sb(bp, fw_sb_id);
5958
5959         if (!CHIP_IS_E1x(bp)) {
5960                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5961                 sb_data_e2.common.state = SB_ENABLED;
5962                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5963                 sb_data_e2.common.p_func.vf_id = vfid;
5964                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5965                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5966                 sb_data_e2.common.same_igu_sb_1b = true;
5967                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5968                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5969                 hc_sm_p = sb_data_e2.common.state_machine;
5970                 sb_data_p = (u32 *)&sb_data_e2;
5971                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5972                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5973         } else {
5974                 memset(&sb_data_e1x, 0,
5975                        sizeof(struct hc_status_block_data_e1x));
5976                 sb_data_e1x.common.state = SB_ENABLED;
5977                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5978                 sb_data_e1x.common.p_func.vf_id = 0xff;
5979                 sb_data_e1x.common.p_func.vf_valid = false;
5980                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5981                 sb_data_e1x.common.same_igu_sb_1b = true;
5982                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5983                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5984                 hc_sm_p = sb_data_e1x.common.state_machine;
5985                 sb_data_p = (u32 *)&sb_data_e1x;
5986                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5987                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5988         }
5989
5990         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5991                                        igu_sb_id, igu_seg_id);
5992         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5993                                        igu_sb_id, igu_seg_id);
5994
5995         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5996
5997         /* write indices to HW - PCI guarantees endianity of regpairs */
5998         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5999 }
6000
6001 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6002                                      u16 tx_usec, u16 rx_usec)
6003 {
6004         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6005                                     false, rx_usec);
6006         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6007                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6008                                        tx_usec);
6009         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6010                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6011                                        tx_usec);
6012         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6013                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6014                                        tx_usec);
6015 }
6016
6017 static void bnx2x_init_def_sb(struct bnx2x *bp)
6018 {
6019         struct host_sp_status_block *def_sb = bp->def_status_blk;
6020         dma_addr_t mapping = bp->def_status_blk_mapping;
6021         int igu_sp_sb_index;
6022         int igu_seg_id;
6023         int port = BP_PORT(bp);
6024         int func = BP_FUNC(bp);
6025         int reg_offset, reg_offset_en5;
6026         u64 section;
6027         int index;
6028         struct hc_sp_status_block_data sp_sb_data;
6029         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6030
6031         if (CHIP_INT_MODE_IS_BC(bp)) {
6032                 igu_sp_sb_index = DEF_SB_IGU_ID;
6033                 igu_seg_id = HC_SEG_ACCESS_DEF;
6034         } else {
6035                 igu_sp_sb_index = bp->igu_dsb_id;
6036                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6037         }
6038
6039         /* ATTN */
6040         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6041                                             atten_status_block);
6042         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6043
6044         bp->attn_state = 0;
6045
6046         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6047                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6048         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6049                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6050         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6051                 int sindex;
6052                 /* take care of sig[0]..sig[4] */
6053                 for (sindex = 0; sindex < 4; sindex++)
6054                         bp->attn_group[index].sig[sindex] =
6055                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6056
6057                 if (!CHIP_IS_E1x(bp))
6058                         /*
6059                          * enable5 is separate from the rest of the registers,
6060                          * and therefore the address skip is 4
6061                          * and not 16 between the different groups
6062                          */
6063                         bp->attn_group[index].sig[4] = REG_RD(bp,
6064                                         reg_offset_en5 + 0x4*index);
6065                 else
6066                         bp->attn_group[index].sig[4] = 0;
6067         }
6068
6069         if (bp->common.int_block == INT_BLOCK_HC) {
6070                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6071                                      HC_REG_ATTN_MSG0_ADDR_L);
6072
6073                 REG_WR(bp, reg_offset, U64_LO(section));
6074                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6075         } else if (!CHIP_IS_E1x(bp)) {
6076                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6077                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6078         }
6079
6080         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6081                                             sp_sb);
6082
6083         bnx2x_zero_sp_sb(bp);
6084
6085         /* PCI guarantees endianity of regpairs */
6086         sp_sb_data.state                = SB_ENABLED;
6087         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6088         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6089         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6090         sp_sb_data.igu_seg_id           = igu_seg_id;
6091         sp_sb_data.p_func.pf_id         = func;
6092         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6093         sp_sb_data.p_func.vf_id         = 0xff;
6094
6095         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6096
6097         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6098 }
6099
6100 void bnx2x_update_coalesce(struct bnx2x *bp)
6101 {
6102         int i;
6103
6104         for_each_eth_queue(bp, i)
6105                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6106                                          bp->tx_ticks, bp->rx_ticks);
6107 }
6108
6109 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6110 {
6111         spin_lock_init(&bp->spq_lock);
6112         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6113
6114         bp->spq_prod_idx = 0;
6115         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6116         bp->spq_prod_bd = bp->spq;
6117         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6118 }
6119
6120 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6121 {
6122         int i;
6123         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6124                 union event_ring_elem *elem =
6125                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6126
6127                 elem->next_page.addr.hi =
6128                         cpu_to_le32(U64_HI(bp->eq_mapping +
6129                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6130                 elem->next_page.addr.lo =
6131                         cpu_to_le32(U64_LO(bp->eq_mapping +
6132                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6133         }
6134         bp->eq_cons = 0;
6135         bp->eq_prod = NUM_EQ_DESC;
6136         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6137         /* we want a warning message before it gets wrought... */
6138         atomic_set(&bp->eq_spq_left,
6139                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6140 }
6141
6142 /* called with netif_addr_lock_bh() */
6143 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6144                                unsigned long rx_mode_flags,
6145                                unsigned long rx_accept_flags,
6146                                unsigned long tx_accept_flags,
6147                                unsigned long ramrod_flags)
6148 {
6149         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6150         int rc;
6151
6152         memset(&ramrod_param, 0, sizeof(ramrod_param));
6153
6154         /* Prepare ramrod parameters */
6155         ramrod_param.cid = 0;
6156         ramrod_param.cl_id = cl_id;
6157         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6158         ramrod_param.func_id = BP_FUNC(bp);
6159
6160         ramrod_param.pstate = &bp->sp_state;
6161         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6162
6163         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6164         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6165
6166         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6167
6168         ramrod_param.ramrod_flags = ramrod_flags;
6169         ramrod_param.rx_mode_flags = rx_mode_flags;
6170
6171         ramrod_param.rx_accept_flags = rx_accept_flags;
6172         ramrod_param.tx_accept_flags = tx_accept_flags;
6173
6174         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6175         if (rc < 0) {
6176                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6177                 return rc;
6178         }
6179
6180         return 0;
6181 }
6182
6183 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6184                                    unsigned long *rx_accept_flags,
6185                                    unsigned long *tx_accept_flags)
6186 {
6187         /* Clear the flags first */
6188         *rx_accept_flags = 0;
6189         *tx_accept_flags = 0;
6190
6191         switch (rx_mode) {
6192         case BNX2X_RX_MODE_NONE:
6193                 /*
6194                  * 'drop all' supersedes any accept flags that may have been
6195                  * passed to the function.
6196                  */
6197                 break;
6198         case BNX2X_RX_MODE_NORMAL:
6199                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6200                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6201                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6202
6203                 /* internal switching mode */
6204                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6205                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6206                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6207
6208                 if (bp->accept_any_vlan) {
6209                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6210                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6211                 }
6212
6213                 break;
6214         case BNX2X_RX_MODE_ALLMULTI:
6215                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6216                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6217                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6218
6219                 /* internal switching mode */
6220                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6221                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6222                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6223
6224                 if (bp->accept_any_vlan) {
6225                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6226                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6227                 }
6228
6229                 break;
6230         case BNX2X_RX_MODE_PROMISC:
6231                 /* According to definition of SI mode, iface in promisc mode
6232                  * should receive matched and unmatched (in resolution of port)
6233                  * unicast packets.
6234                  */
6235                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6236                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6237                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6238                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6239
6240                 /* internal switching mode */
6241                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6242                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6243
6244                 if (IS_MF_SI(bp))
6245                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6246                 else
6247                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6248
6249                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6250                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6251
6252                 break;
6253         default:
6254                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6255                 return -EINVAL;
6256         }
6257
6258         return 0;
6259 }
6260
6261 /* called with netif_addr_lock_bh() */
6262 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6263 {
6264         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6265         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6266         int rc;
6267
6268         if (!NO_FCOE(bp))
6269                 /* Configure rx_mode of FCoE Queue */
6270                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6271
6272         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6273                                      &tx_accept_flags);
6274         if (rc)
6275                 return rc;
6276
6277         __set_bit(RAMROD_RX, &ramrod_flags);
6278         __set_bit(RAMROD_TX, &ramrod_flags);
6279
6280         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6281                                    rx_accept_flags, tx_accept_flags,
6282                                    ramrod_flags);
6283 }
6284
6285 static void bnx2x_init_internal_common(struct bnx2x *bp)
6286 {
6287         int i;
6288
6289         /* Zero this manually as its initialization is
6290            currently missing in the initTool */
6291         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6292                 REG_WR(bp, BAR_USTRORM_INTMEM +
6293                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6294         if (!CHIP_IS_E1x(bp)) {
6295                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6296                         CHIP_INT_MODE_IS_BC(bp) ?
6297                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6298         }
6299 }
6300
6301 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6302 {
6303         switch (load_code) {
6304         case FW_MSG_CODE_DRV_LOAD_COMMON:
6305         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6306                 bnx2x_init_internal_common(bp);
6307                 /* no break */
6308
6309         case FW_MSG_CODE_DRV_LOAD_PORT:
6310                 /* nothing to do */
6311                 /* no break */
6312
6313         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6314                 /* internal memory per function is
6315                    initialized inside bnx2x_pf_init */
6316                 break;
6317
6318         default:
6319                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6320                 break;
6321         }
6322 }
6323
6324 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6325 {
6326         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6327 }
6328
6329 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6330 {
6331         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6332 }
6333
6334 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6335 {
6336         if (CHIP_IS_E1x(fp->bp))
6337                 return BP_L_ID(fp->bp) + fp->index;
6338         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6339                 return bnx2x_fp_igu_sb_id(fp);
6340 }
6341
6342 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6343 {
6344         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6345         u8 cos;
6346         unsigned long q_type = 0;
6347         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6348         fp->rx_queue = fp_idx;
6349         fp->cid = fp_idx;
6350         fp->cl_id = bnx2x_fp_cl_id(fp);
6351         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6352         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6353         /* qZone id equals to FW (per path) client id */
6354         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6355
6356         /* init shortcut */
6357         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6358
6359         /* Setup SB indices */
6360         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6361
6362         /* Configure Queue State object */
6363         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6364         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6365
6366         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6367
6368         /* init tx data */
6369         for_each_cos_in_tx_queue(fp, cos) {
6370                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6371                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6372                                   FP_COS_TO_TXQ(fp, cos, bp),
6373                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6374                 cids[cos] = fp->txdata_ptr[cos]->cid;
6375         }
6376
6377         /* nothing more for vf to do here */
6378         if (IS_VF(bp))
6379                 return;
6380
6381         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6382                       fp->fw_sb_id, fp->igu_sb_id);
6383         bnx2x_update_fpsb_idx(fp);
6384         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6385                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6386                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6387
6388         /**
6389          * Configure classification DBs: Always enable Tx switching
6390          */
6391         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6392
6393         DP(NETIF_MSG_IFUP,
6394            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6395            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6396            fp->igu_sb_id);
6397 }
6398
6399 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6400 {
6401         int i;
6402
6403         for (i = 1; i <= NUM_TX_RINGS; i++) {
6404                 struct eth_tx_next_bd *tx_next_bd =
6405                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6406
6407                 tx_next_bd->addr_hi =
6408                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6409                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6410                 tx_next_bd->addr_lo =
6411                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6412                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6413         }
6414
6415         *txdata->tx_cons_sb = cpu_to_le16(0);
6416
6417         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6418         txdata->tx_db.data.zero_fill1 = 0;
6419         txdata->tx_db.data.prod = 0;
6420
6421         txdata->tx_pkt_prod = 0;
6422         txdata->tx_pkt_cons = 0;
6423         txdata->tx_bd_prod = 0;
6424         txdata->tx_bd_cons = 0;
6425         txdata->tx_pkt = 0;
6426 }
6427
6428 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6429 {
6430         int i;
6431
6432         for_each_tx_queue_cnic(bp, i)
6433                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6434 }
6435
6436 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6437 {
6438         int i;
6439         u8 cos;
6440
6441         for_each_eth_queue(bp, i)
6442                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6443                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6444 }
6445
6446 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6447 {
6448         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6449         unsigned long q_type = 0;
6450
6451         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6452         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6453                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6454         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6455         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6456         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6457         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6458         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6459                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6460                           fp);
6461
6462         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6463
6464         /* qZone id equals to FW (per path) client id */
6465         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6466         /* init shortcut */
6467         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6468                 bnx2x_rx_ustorm_prods_offset(fp);
6469
6470         /* Configure Queue State object */
6471         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6472         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6473
6474         /* No multi-CoS for FCoE L2 client */
6475         BUG_ON(fp->max_cos != 1);
6476
6477         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6478                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6479                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6480
6481         DP(NETIF_MSG_IFUP,
6482            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6483            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6484            fp->igu_sb_id);
6485 }
6486
6487 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6488 {
6489         if (!NO_FCOE(bp))
6490                 bnx2x_init_fcoe_fp(bp);
6491
6492         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6493                       BNX2X_VF_ID_INVALID, false,
6494                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6495
6496         /* ensure status block indices were read */
6497         rmb();
6498         bnx2x_init_rx_rings_cnic(bp);
6499         bnx2x_init_tx_rings_cnic(bp);
6500
6501         /* flush all */
6502         mb();
6503         mmiowb();
6504 }
6505
6506 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6507 {
6508         int i;
6509
6510         /* Setup NIC internals and enable interrupts */
6511         for_each_eth_queue(bp, i)
6512                 bnx2x_init_eth_fp(bp, i);
6513
6514         /* ensure status block indices were read */
6515         rmb();
6516         bnx2x_init_rx_rings(bp);
6517         bnx2x_init_tx_rings(bp);
6518
6519         if (IS_PF(bp)) {
6520                 /* Initialize MOD_ABS interrupts */
6521                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6522                                        bp->common.shmem_base,
6523                                        bp->common.shmem2_base, BP_PORT(bp));
6524
6525                 /* initialize the default status block and sp ring */
6526                 bnx2x_init_def_sb(bp);
6527                 bnx2x_update_dsb_idx(bp);
6528                 bnx2x_init_sp_ring(bp);
6529         } else {
6530                 bnx2x_memset_stats(bp);
6531         }
6532 }
6533
6534 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6535 {
6536         bnx2x_init_eq_ring(bp);
6537         bnx2x_init_internal(bp, load_code);
6538         bnx2x_pf_init(bp);
6539         bnx2x_stats_init(bp);
6540
6541         /* flush all before enabling interrupts */
6542         mb();
6543         mmiowb();
6544
6545         bnx2x_int_enable(bp);
6546
6547         /* Check for SPIO5 */
6548         bnx2x_attn_int_deasserted0(bp,
6549                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6550                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6551 }
6552
6553 /* gzip service functions */
6554 static int bnx2x_gunzip_init(struct bnx2x *bp)
6555 {
6556         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6557                                             &bp->gunzip_mapping, GFP_KERNEL);
6558         if (bp->gunzip_buf  == NULL)
6559                 goto gunzip_nomem1;
6560
6561         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6562         if (bp->strm  == NULL)
6563                 goto gunzip_nomem2;
6564
6565         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6566         if (bp->strm->workspace == NULL)
6567                 goto gunzip_nomem3;
6568
6569         return 0;
6570
6571 gunzip_nomem3:
6572         kfree(bp->strm);
6573         bp->strm = NULL;
6574
6575 gunzip_nomem2:
6576         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6577                           bp->gunzip_mapping);
6578         bp->gunzip_buf = NULL;
6579
6580 gunzip_nomem1:
6581         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6582         return -ENOMEM;
6583 }
6584
6585 static void bnx2x_gunzip_end(struct bnx2x *bp)
6586 {
6587         if (bp->strm) {
6588                 vfree(bp->strm->workspace);
6589                 kfree(bp->strm);
6590                 bp->strm = NULL;
6591         }
6592
6593         if (bp->gunzip_buf) {
6594                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6595                                   bp->gunzip_mapping);
6596                 bp->gunzip_buf = NULL;
6597         }
6598 }
6599
6600 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6601 {
6602         int n, rc;
6603
6604         /* check gzip header */
6605         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6606                 BNX2X_ERR("Bad gzip header\n");
6607                 return -EINVAL;
6608         }
6609
6610         n = 10;
6611
6612 #define FNAME                           0x8
6613
6614         if (zbuf[3] & FNAME)
6615                 while ((zbuf[n++] != 0) && (n < len));
6616
6617         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6618         bp->strm->avail_in = len - n;
6619         bp->strm->next_out = bp->gunzip_buf;
6620         bp->strm->avail_out = FW_BUF_SIZE;
6621
6622         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6623         if (rc != Z_OK)
6624                 return rc;
6625
6626         rc = zlib_inflate(bp->strm, Z_FINISH);
6627         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6628                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6629                            bp->strm->msg);
6630
6631         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6632         if (bp->gunzip_outlen & 0x3)
6633                 netdev_err(bp->dev,
6634                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6635                                 bp->gunzip_outlen);
6636         bp->gunzip_outlen >>= 2;
6637
6638         zlib_inflateEnd(bp->strm);
6639
6640         if (rc == Z_STREAM_END)
6641                 return 0;
6642
6643         return rc;
6644 }
6645
6646 /* nic load/unload */
6647
6648 /*
6649  * General service functions
6650  */
6651
6652 /* send a NIG loopback debug packet */
6653 static void bnx2x_lb_pckt(struct bnx2x *bp)
6654 {
6655         u32 wb_write[3];
6656
6657         /* Ethernet source and destination addresses */
6658         wb_write[0] = 0x55555555;
6659         wb_write[1] = 0x55555555;
6660         wb_write[2] = 0x20;             /* SOP */
6661         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6662
6663         /* NON-IP protocol */
6664         wb_write[0] = 0x09000000;
6665         wb_write[1] = 0x55555555;
6666         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6667         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6668 }
6669
6670 /* some of the internal memories
6671  * are not directly readable from the driver
6672  * to test them we send debug packets
6673  */
6674 static int bnx2x_int_mem_test(struct bnx2x *bp)
6675 {
6676         int factor;
6677         int count, i;
6678         u32 val = 0;
6679
6680         if (CHIP_REV_IS_FPGA(bp))
6681                 factor = 120;
6682         else if (CHIP_REV_IS_EMUL(bp))
6683                 factor = 200;
6684         else
6685                 factor = 1;
6686
6687         /* Disable inputs of parser neighbor blocks */
6688         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6689         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6690         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6691         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6692
6693         /*  Write 0 to parser credits for CFC search request */
6694         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6695
6696         /* send Ethernet packet */
6697         bnx2x_lb_pckt(bp);
6698
6699         /* TODO do i reset NIG statistic? */
6700         /* Wait until NIG register shows 1 packet of size 0x10 */
6701         count = 1000 * factor;
6702         while (count) {
6703
6704                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6705                 val = *bnx2x_sp(bp, wb_data[0]);
6706                 if (val == 0x10)
6707                         break;
6708
6709                 usleep_range(10000, 20000);
6710                 count--;
6711         }
6712         if (val != 0x10) {
6713                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6714                 return -1;
6715         }
6716
6717         /* Wait until PRS register shows 1 packet */
6718         count = 1000 * factor;
6719         while (count) {
6720                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6721                 if (val == 1)
6722                         break;
6723
6724                 usleep_range(10000, 20000);
6725                 count--;
6726         }
6727         if (val != 0x1) {
6728                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6729                 return -2;
6730         }
6731
6732         /* Reset and init BRB, PRS */
6733         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6734         msleep(50);
6735         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6736         msleep(50);
6737         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6738         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6739
6740         DP(NETIF_MSG_HW, "part2\n");
6741
6742         /* Disable inputs of parser neighbor blocks */
6743         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6744         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6745         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6746         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6747
6748         /* Write 0 to parser credits for CFC search request */
6749         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6750
6751         /* send 10 Ethernet packets */
6752         for (i = 0; i < 10; i++)
6753                 bnx2x_lb_pckt(bp);
6754
6755         /* Wait until NIG register shows 10 + 1
6756            packets of size 11*0x10 = 0xb0 */
6757         count = 1000 * factor;
6758         while (count) {
6759
6760                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6761                 val = *bnx2x_sp(bp, wb_data[0]);
6762                 if (val == 0xb0)
6763                         break;
6764
6765                 usleep_range(10000, 20000);
6766                 count--;
6767         }
6768         if (val != 0xb0) {
6769                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6770                 return -3;
6771         }
6772
6773         /* Wait until PRS register shows 2 packets */
6774         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6775         if (val != 2)
6776                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6777
6778         /* Write 1 to parser credits for CFC search request */
6779         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6780
6781         /* Wait until PRS register shows 3 packets */
6782         msleep(10 * factor);
6783         /* Wait until NIG register shows 1 packet of size 0x10 */
6784         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6785         if (val != 3)
6786                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6787
6788         /* clear NIG EOP FIFO */
6789         for (i = 0; i < 11; i++)
6790                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6791         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6792         if (val != 1) {
6793                 BNX2X_ERR("clear of NIG failed\n");
6794                 return -4;
6795         }
6796
6797         /* Reset and init BRB, PRS, NIG */
6798         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6799         msleep(50);
6800         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6801         msleep(50);
6802         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6803         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6804         if (!CNIC_SUPPORT(bp))
6805                 /* set NIC mode */
6806                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6807
6808         /* Enable inputs of parser neighbor blocks */
6809         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6810         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6811         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6812         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6813
6814         DP(NETIF_MSG_HW, "done\n");
6815
6816         return 0; /* OK */
6817 }
6818
6819 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6820 {
6821         u32 val;
6822
6823         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6824         if (!CHIP_IS_E1x(bp))
6825                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6826         else
6827                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6828         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6829         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6830         /*
6831          * mask read length error interrupts in brb for parser
6832          * (parsing unit and 'checksum and crc' unit)
6833          * these errors are legal (PU reads fixed length and CAC can cause
6834          * read length error on truncated packets)
6835          */
6836         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6837         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6838         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6839         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6840         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6841         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6842 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6843 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6844         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6845         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6846         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6847 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6848 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6849         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6850         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6851         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6852         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6853 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6854 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6855
6856         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6857                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6858                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6859         if (!CHIP_IS_E1x(bp))
6860                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6861                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6862         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6863
6864         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6865         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6866         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6867 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6868
6869         if (!CHIP_IS_E1x(bp))
6870                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6871                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6872
6873         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6874         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6875 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6876         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6877 }
6878
6879 static void bnx2x_reset_common(struct bnx2x *bp)
6880 {
6881         u32 val = 0x1400;
6882
6883         /* reset_common */
6884         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6885                0xd3ffff7f);
6886
6887         if (CHIP_IS_E3(bp)) {
6888                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6889                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6890         }
6891
6892         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6893 }
6894
6895 static void bnx2x_setup_dmae(struct bnx2x *bp)
6896 {
6897         bp->dmae_ready = 0;
6898         spin_lock_init(&bp->dmae_lock);
6899 }
6900
6901 static void bnx2x_init_pxp(struct bnx2x *bp)
6902 {
6903         u16 devctl;
6904         int r_order, w_order;
6905
6906         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6907         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6908         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6909         if (bp->mrrs == -1)
6910                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6911         else {
6912                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6913                 r_order = bp->mrrs;
6914         }
6915
6916         bnx2x_init_pxp_arb(bp, r_order, w_order);
6917 }
6918
6919 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6920 {
6921         int is_required;
6922         u32 val;
6923         int port;
6924
6925         if (BP_NOMCP(bp))
6926                 return;
6927
6928         is_required = 0;
6929         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6930               SHARED_HW_CFG_FAN_FAILURE_MASK;
6931
6932         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6933                 is_required = 1;
6934
6935         /*
6936          * The fan failure mechanism is usually related to the PHY type since
6937          * the power consumption of the board is affected by the PHY. Currently,
6938          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6939          */
6940         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6941                 for (port = PORT_0; port < PORT_MAX; port++) {
6942                         is_required |=
6943                                 bnx2x_fan_failure_det_req(
6944                                         bp,
6945                                         bp->common.shmem_base,
6946                                         bp->common.shmem2_base,
6947                                         port);
6948                 }
6949
6950         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6951
6952         if (is_required == 0)
6953                 return;
6954
6955         /* Fan failure is indicated by SPIO 5 */
6956         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6957
6958         /* set to active low mode */
6959         val = REG_RD(bp, MISC_REG_SPIO_INT);
6960         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6961         REG_WR(bp, MISC_REG_SPIO_INT, val);
6962
6963         /* enable interrupt to signal the IGU */
6964         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6965         val |= MISC_SPIO_SPIO5;
6966         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6967 }
6968
6969 void bnx2x_pf_disable(struct bnx2x *bp)
6970 {
6971         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6972         val &= ~IGU_PF_CONF_FUNC_EN;
6973
6974         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6975         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6976         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6977 }
6978
6979 static void bnx2x__common_init_phy(struct bnx2x *bp)
6980 {
6981         u32 shmem_base[2], shmem2_base[2];
6982         /* Avoid common init in case MFW supports LFA */
6983         if (SHMEM2_RD(bp, size) >
6984             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6985                 return;
6986         shmem_base[0] =  bp->common.shmem_base;
6987         shmem2_base[0] = bp->common.shmem2_base;
6988         if (!CHIP_IS_E1x(bp)) {
6989                 shmem_base[1] =
6990                         SHMEM2_RD(bp, other_shmem_base_addr);
6991                 shmem2_base[1] =
6992                         SHMEM2_RD(bp, other_shmem2_base_addr);
6993         }
6994         bnx2x_acquire_phy_lock(bp);
6995         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6996                               bp->common.chip_id);
6997         bnx2x_release_phy_lock(bp);
6998 }
6999
7000 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
7001 {
7002         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7003         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7004         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7005         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7006         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7007
7008         /* make sure this value is 0 */
7009         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7010
7011         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7012         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7013         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7014         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7015 }
7016
7017 static void bnx2x_set_endianity(struct bnx2x *bp)
7018 {
7019 #ifdef __BIG_ENDIAN
7020         bnx2x_config_endianity(bp, 1);
7021 #else
7022         bnx2x_config_endianity(bp, 0);
7023 #endif
7024 }
7025
7026 static void bnx2x_reset_endianity(struct bnx2x *bp)
7027 {
7028         bnx2x_config_endianity(bp, 0);
7029 }
7030
7031 /**
7032  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7033  *
7034  * @bp:         driver handle
7035  */
7036 static int bnx2x_init_hw_common(struct bnx2x *bp)
7037 {
7038         u32 val;
7039
7040         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7041
7042         /*
7043          * take the RESET lock to protect undi_unload flow from accessing
7044          * registers while we're resetting the chip
7045          */
7046         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7047
7048         bnx2x_reset_common(bp);
7049         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7050
7051         val = 0xfffc;
7052         if (CHIP_IS_E3(bp)) {
7053                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7054                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7055         }
7056         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7057
7058         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7059
7060         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7061
7062         if (!CHIP_IS_E1x(bp)) {
7063                 u8 abs_func_id;
7064
7065                 /**
7066                  * 4-port mode or 2-port mode we need to turn of master-enable
7067                  * for everyone, after that, turn it back on for self.
7068                  * so, we disregard multi-function or not, and always disable
7069                  * for all functions on the given path, this means 0,2,4,6 for
7070                  * path 0 and 1,3,5,7 for path 1
7071                  */
7072                 for (abs_func_id = BP_PATH(bp);
7073                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7074                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7075                                 REG_WR(bp,
7076                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7077                                     1);
7078                                 continue;
7079                         }
7080
7081                         bnx2x_pretend_func(bp, abs_func_id);
7082                         /* clear pf enable */
7083                         bnx2x_pf_disable(bp);
7084                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7085                 }
7086         }
7087
7088         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7089         if (CHIP_IS_E1(bp)) {
7090                 /* enable HW interrupt from PXP on USDM overflow
7091                    bit 16 on INT_MASK_0 */
7092                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7093         }
7094
7095         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7096         bnx2x_init_pxp(bp);
7097         bnx2x_set_endianity(bp);
7098         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7099
7100         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7101                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7102
7103         /* let the HW do it's magic ... */
7104         msleep(100);
7105         /* finish PXP init */
7106         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7107         if (val != 1) {
7108                 BNX2X_ERR("PXP2 CFG failed\n");
7109                 return -EBUSY;
7110         }
7111         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7112         if (val != 1) {
7113                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7114                 return -EBUSY;
7115         }
7116
7117         /* Timers bug workaround E2 only. We need to set the entire ILT to
7118          * have entries with value "0" and valid bit on.
7119          * This needs to be done by the first PF that is loaded in a path
7120          * (i.e. common phase)
7121          */
7122         if (!CHIP_IS_E1x(bp)) {
7123 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7124  * (i.e. vnic3) to start even if it is marked as "scan-off".
7125  * This occurs when a different function (func2,3) is being marked
7126  * as "scan-off". Real-life scenario for example: if a driver is being
7127  * load-unloaded while func6,7 are down. This will cause the timer to access
7128  * the ilt, translate to a logical address and send a request to read/write.
7129  * Since the ilt for the function that is down is not valid, this will cause
7130  * a translation error which is unrecoverable.
7131  * The Workaround is intended to make sure that when this happens nothing fatal
7132  * will occur. The workaround:
7133  *      1.  First PF driver which loads on a path will:
7134  *              a.  After taking the chip out of reset, by using pretend,
7135  *                  it will write "0" to the following registers of
7136  *                  the other vnics.
7137  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7138  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7139  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7140  *                  And for itself it will write '1' to
7141  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7142  *                  dmae-operations (writing to pram for example.)
7143  *                  note: can be done for only function 6,7 but cleaner this
7144  *                        way.
7145  *              b.  Write zero+valid to the entire ILT.
7146  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7147  *                  VNIC3 (of that port). The range allocated will be the
7148  *                  entire ILT. This is needed to prevent  ILT range error.
7149  *      2.  Any PF driver load flow:
7150  *              a.  ILT update with the physical addresses of the allocated
7151  *                  logical pages.
7152  *              b.  Wait 20msec. - note that this timeout is needed to make
7153  *                  sure there are no requests in one of the PXP internal
7154  *                  queues with "old" ILT addresses.
7155  *              c.  PF enable in the PGLC.
7156  *              d.  Clear the was_error of the PF in the PGLC. (could have
7157  *                  occurred while driver was down)
7158  *              e.  PF enable in the CFC (WEAK + STRONG)
7159  *              f.  Timers scan enable
7160  *      3.  PF driver unload flow:
7161  *              a.  Clear the Timers scan_en.
7162  *              b.  Polling for scan_on=0 for that PF.
7163  *              c.  Clear the PF enable bit in the PXP.
7164  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7165  *              e.  Write zero+valid to all ILT entries (The valid bit must
7166  *                  stay set)
7167  *              f.  If this is VNIC 3 of a port then also init
7168  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7169  *                  to the last entry in the ILT.
7170  *
7171  *      Notes:
7172  *      Currently the PF error in the PGLC is non recoverable.
7173  *      In the future the there will be a recovery routine for this error.
7174  *      Currently attention is masked.
7175  *      Having an MCP lock on the load/unload process does not guarantee that
7176  *      there is no Timer disable during Func6/7 enable. This is because the
7177  *      Timers scan is currently being cleared by the MCP on FLR.
7178  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7179  *      there is error before clearing it. But the flow above is simpler and
7180  *      more general.
7181  *      All ILT entries are written by zero+valid and not just PF6/7
7182  *      ILT entries since in the future the ILT entries allocation for
7183  *      PF-s might be dynamic.
7184  */
7185                 struct ilt_client_info ilt_cli;
7186                 struct bnx2x_ilt ilt;
7187                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7188                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7189
7190                 /* initialize dummy TM client */
7191                 ilt_cli.start = 0;
7192                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7193                 ilt_cli.client_num = ILT_CLIENT_TM;
7194
7195                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7196                  * Step 2: set the timers first/last ilt entry to point
7197                  * to the entire range to prevent ILT range error for 3rd/4th
7198                  * vnic (this code assumes existence of the vnic)
7199                  *
7200                  * both steps performed by call to bnx2x_ilt_client_init_op()
7201                  * with dummy TM client
7202                  *
7203                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7204                  * and his brother are split registers
7205                  */
7206                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7207                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7208                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7209
7210                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7211                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7212                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7213         }
7214
7215         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7216         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7217
7218         if (!CHIP_IS_E1x(bp)) {
7219                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7220                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7221                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7222
7223                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7224
7225                 /* let the HW do it's magic ... */
7226                 do {
7227                         msleep(200);
7228                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7229                 } while (factor-- && (val != 1));
7230
7231                 if (val != 1) {
7232                         BNX2X_ERR("ATC_INIT failed\n");
7233                         return -EBUSY;
7234                 }
7235         }
7236
7237         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7238
7239         bnx2x_iov_init_dmae(bp);
7240
7241         /* clean the DMAE memory */
7242         bp->dmae_ready = 1;
7243         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7244
7245         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7246
7247         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7248
7249         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7250
7251         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7252
7253         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7254         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7255         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7256         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7257
7258         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7259
7260         /* QM queues pointers table */
7261         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7262
7263         /* soft reset pulse */
7264         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7265         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7266
7267         if (CNIC_SUPPORT(bp))
7268                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7269
7270         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7271
7272         if (!CHIP_REV_IS_SLOW(bp))
7273                 /* enable hw interrupt from doorbell Q */
7274                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7275
7276         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7277
7278         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7279         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7280
7281         if (!CHIP_IS_E1(bp))
7282                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7283
7284         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7285                 if (IS_MF_AFEX(bp)) {
7286                         /* configure that VNTag and VLAN headers must be
7287                          * received in afex mode
7288                          */
7289                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7290                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7291                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7292                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7293                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7294                 } else {
7295                         /* Bit-map indicating which L2 hdrs may appear
7296                          * after the basic Ethernet header
7297                          */
7298                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7299                                bp->path_has_ovlan ? 7 : 6);
7300                 }
7301         }
7302
7303         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7304         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7305         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7306         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7307
7308         if (!CHIP_IS_E1x(bp)) {
7309                 /* reset VFC memories */
7310                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7311                            VFC_MEMORIES_RST_REG_CAM_RST |
7312                            VFC_MEMORIES_RST_REG_RAM_RST);
7313                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7314                            VFC_MEMORIES_RST_REG_CAM_RST |
7315                            VFC_MEMORIES_RST_REG_RAM_RST);
7316
7317                 msleep(20);
7318         }
7319
7320         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7321         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7322         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7323         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7324
7325         /* sync semi rtc */
7326         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7327                0x80000000);
7328         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7329                0x80000000);
7330
7331         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7332         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7333         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7334
7335         if (!CHIP_IS_E1x(bp)) {
7336                 if (IS_MF_AFEX(bp)) {
7337                         /* configure that VNTag and VLAN headers must be
7338                          * sent in afex mode
7339                          */
7340                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7341                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7342                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7343                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7344                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7345                 } else {
7346                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7347                                bp->path_has_ovlan ? 7 : 6);
7348                 }
7349         }
7350
7351         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7352
7353         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7354
7355         if (CNIC_SUPPORT(bp)) {
7356                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7357                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7358                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7359                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7360                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7361                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7362                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7363                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7364                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7365                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7366         }
7367         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7368
7369         if (sizeof(union cdu_context) != 1024)
7370                 /* we currently assume that a context is 1024 bytes */
7371                 dev_alert(&bp->pdev->dev,
7372                           "please adjust the size of cdu_context(%ld)\n",
7373                           (long)sizeof(union cdu_context));
7374
7375         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7376         val = (4 << 24) + (0 << 12) + 1024;
7377         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7378
7379         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7380         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7381         /* enable context validation interrupt from CFC */
7382         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7383
7384         /* set the thresholds to prevent CFC/CDU race */
7385         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7386
7387         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7388
7389         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7390                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7391
7392         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7393         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7394
7395         /* Reset PCIE errors for debug */
7396         REG_WR(bp, 0x2814, 0xffffffff);
7397         REG_WR(bp, 0x3820, 0xffffffff);
7398
7399         if (!CHIP_IS_E1x(bp)) {
7400                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7401                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7402                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7403                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7404                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7405                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7406                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7407                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7408                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7409                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7410                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7411         }
7412
7413         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7414         if (!CHIP_IS_E1(bp)) {
7415                 /* in E3 this done in per-port section */
7416                 if (!CHIP_IS_E3(bp))
7417                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7418         }
7419         if (CHIP_IS_E1H(bp))
7420                 /* not applicable for E2 (and above ...) */
7421                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7422
7423         if (CHIP_REV_IS_SLOW(bp))
7424                 msleep(200);
7425
7426         /* finish CFC init */
7427         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7428         if (val != 1) {
7429                 BNX2X_ERR("CFC LL_INIT failed\n");
7430                 return -EBUSY;
7431         }
7432         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7433         if (val != 1) {
7434                 BNX2X_ERR("CFC AC_INIT failed\n");
7435                 return -EBUSY;
7436         }
7437         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7438         if (val != 1) {
7439                 BNX2X_ERR("CFC CAM_INIT failed\n");
7440                 return -EBUSY;
7441         }
7442         REG_WR(bp, CFC_REG_DEBUG0, 0);
7443
7444         if (CHIP_IS_E1(bp)) {
7445                 /* read NIG statistic
7446                    to see if this is our first up since powerup */
7447                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7448                 val = *bnx2x_sp(bp, wb_data[0]);
7449
7450                 /* do internal memory self test */
7451                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7452                         BNX2X_ERR("internal mem self test failed\n");
7453                         return -EBUSY;
7454                 }
7455         }
7456
7457         bnx2x_setup_fan_failure_detection(bp);
7458
7459         /* clear PXP2 attentions */
7460         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7461
7462         bnx2x_enable_blocks_attention(bp);
7463         bnx2x_enable_blocks_parity(bp);
7464
7465         if (!BP_NOMCP(bp)) {
7466                 if (CHIP_IS_E1x(bp))
7467                         bnx2x__common_init_phy(bp);
7468         } else
7469                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7470
7471         if (SHMEM2_HAS(bp, netproc_fw_ver))
7472                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7473
7474         return 0;
7475 }
7476
7477 /**
7478  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7479  *
7480  * @bp:         driver handle
7481  */
7482 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7483 {
7484         int rc = bnx2x_init_hw_common(bp);
7485
7486         if (rc)
7487                 return rc;
7488
7489         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7490         if (!BP_NOMCP(bp))
7491                 bnx2x__common_init_phy(bp);
7492
7493         return 0;
7494 }
7495
7496 static int bnx2x_init_hw_port(struct bnx2x *bp)
7497 {
7498         int port = BP_PORT(bp);
7499         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7500         u32 low, high;
7501         u32 val, reg;
7502
7503         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7504
7505         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7506
7507         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7508         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7509         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7510
7511         /* Timers bug workaround: disables the pf_master bit in pglue at
7512          * common phase, we need to enable it here before any dmae access are
7513          * attempted. Therefore we manually added the enable-master to the
7514          * port phase (it also happens in the function phase)
7515          */
7516         if (!CHIP_IS_E1x(bp))
7517                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7518
7519         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7520         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7521         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7522         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7523
7524         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7525         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7526         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7527         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7528
7529         /* QM cid (connection) count */
7530         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7531
7532         if (CNIC_SUPPORT(bp)) {
7533                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7534                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7535                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7536         }
7537
7538         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7539
7540         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7541
7542         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7543
7544                 if (IS_MF(bp))
7545                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7546                 else if (bp->dev->mtu > 4096) {
7547                         if (bp->flags & ONE_PORT_FLAG)
7548                                 low = 160;
7549                         else {
7550                                 val = bp->dev->mtu;
7551                                 /* (24*1024 + val*4)/256 */
7552                                 low = 96 + (val/64) +
7553                                                 ((val % 64) ? 1 : 0);
7554                         }
7555                 } else
7556                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7557                 high = low + 56;        /* 14*1024/256 */
7558                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7559                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7560         }
7561
7562         if (CHIP_MODE_IS_4_PORT(bp))
7563                 REG_WR(bp, (BP_PORT(bp) ?
7564                             BRB1_REG_MAC_GUARANTIED_1 :
7565                             BRB1_REG_MAC_GUARANTIED_0), 40);
7566
7567         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7568         if (CHIP_IS_E3B0(bp)) {
7569                 if (IS_MF_AFEX(bp)) {
7570                         /* configure headers for AFEX mode */
7571                         REG_WR(bp, BP_PORT(bp) ?
7572                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7573                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7574                         REG_WR(bp, BP_PORT(bp) ?
7575                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7576                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7577                         REG_WR(bp, BP_PORT(bp) ?
7578                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7579                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7580                 } else {
7581                         /* Ovlan exists only if we are in multi-function +
7582                          * switch-dependent mode, in switch-independent there
7583                          * is no ovlan headers
7584                          */
7585                         REG_WR(bp, BP_PORT(bp) ?
7586                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7587                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7588                                (bp->path_has_ovlan ? 7 : 6));
7589                 }
7590         }
7591
7592         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7593         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7594         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7595         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7596
7597         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7598         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7599         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7600         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7601
7602         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7603         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7604
7605         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7606
7607         if (CHIP_IS_E1x(bp)) {
7608                 /* configure PBF to work without PAUSE mtu 9000 */
7609                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7610
7611                 /* update threshold */
7612                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7613                 /* update init credit */
7614                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7615
7616                 /* probe changes */
7617                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7618                 udelay(50);
7619                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7620         }
7621
7622         if (CNIC_SUPPORT(bp))
7623                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7624
7625         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7626         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7627
7628         if (CHIP_IS_E1(bp)) {
7629                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7630                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7631         }
7632         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7633
7634         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7635
7636         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7637         /* init aeu_mask_attn_func_0/1:
7638          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7639          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7640          *             bits 4-7 are used for "per vn group attention" */
7641         val = IS_MF(bp) ? 0xF7 : 0x7;
7642         /* Enable DCBX attention for all but E1 */
7643         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7644         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7645
7646         /* SCPAD_PARITY should NOT trigger close the gates */
7647         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7648         REG_WR(bp, reg,
7649                REG_RD(bp, reg) &
7650                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7651
7652         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7653         REG_WR(bp, reg,
7654                REG_RD(bp, reg) &
7655                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7656
7657         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7658
7659         if (!CHIP_IS_E1x(bp)) {
7660                 /* Bit-map indicating which L2 hdrs may appear after the
7661                  * basic Ethernet header
7662                  */
7663                 if (IS_MF_AFEX(bp))
7664                         REG_WR(bp, BP_PORT(bp) ?
7665                                NIG_REG_P1_HDRS_AFTER_BASIC :
7666                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7667                 else
7668                         REG_WR(bp, BP_PORT(bp) ?
7669                                NIG_REG_P1_HDRS_AFTER_BASIC :
7670                                NIG_REG_P0_HDRS_AFTER_BASIC,
7671                                IS_MF_SD(bp) ? 7 : 6);
7672
7673                 if (CHIP_IS_E3(bp))
7674                         REG_WR(bp, BP_PORT(bp) ?
7675                                    NIG_REG_LLH1_MF_MODE :
7676                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7677         }
7678         if (!CHIP_IS_E3(bp))
7679                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7680
7681         if (!CHIP_IS_E1(bp)) {
7682                 /* 0x2 disable mf_ov, 0x1 enable */
7683                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7684                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7685
7686                 if (!CHIP_IS_E1x(bp)) {
7687                         val = 0;
7688                         switch (bp->mf_mode) {
7689                         case MULTI_FUNCTION_SD:
7690                                 val = 1;
7691                                 break;
7692                         case MULTI_FUNCTION_SI:
7693                         case MULTI_FUNCTION_AFEX:
7694                                 val = 2;
7695                                 break;
7696                         }
7697
7698                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7699                                                   NIG_REG_LLH0_CLS_TYPE), val);
7700                 }
7701                 {
7702                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7703                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7704                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7705                 }
7706         }
7707
7708         /* If SPIO5 is set to generate interrupts, enable it for this port */
7709         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7710         if (val & MISC_SPIO_SPIO5) {
7711                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7712                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7713                 val = REG_RD(bp, reg_addr);
7714                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7715                 REG_WR(bp, reg_addr, val);
7716         }
7717
7718         return 0;
7719 }
7720
7721 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7722 {
7723         int reg;
7724         u32 wb_write[2];
7725
7726         if (CHIP_IS_E1(bp))
7727                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7728         else
7729                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7730
7731         wb_write[0] = ONCHIP_ADDR1(addr);
7732         wb_write[1] = ONCHIP_ADDR2(addr);
7733         REG_WR_DMAE(bp, reg, wb_write, 2);
7734 }
7735
7736 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7737 {
7738         u32 data, ctl, cnt = 100;
7739         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7740         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7741         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7742         u32 sb_bit =  1 << (idu_sb_id%32);
7743         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7744         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7745
7746         /* Not supported in BC mode */
7747         if (CHIP_INT_MODE_IS_BC(bp))
7748                 return;
7749
7750         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7751                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7752                 IGU_REGULAR_CLEANUP_SET                         |
7753                 IGU_REGULAR_BCLEANUP;
7754
7755         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7756               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7757               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7758
7759         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7760                          data, igu_addr_data);
7761         REG_WR(bp, igu_addr_data, data);
7762         mmiowb();
7763         barrier();
7764         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7765                           ctl, igu_addr_ctl);
7766         REG_WR(bp, igu_addr_ctl, ctl);
7767         mmiowb();
7768         barrier();
7769
7770         /* wait for clean up to finish */
7771         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7772                 msleep(20);
7773
7774         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7775                 DP(NETIF_MSG_HW,
7776                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7777                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7778         }
7779 }
7780
7781 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7782 {
7783         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7784 }
7785
7786 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7787 {
7788         u32 i, base = FUNC_ILT_BASE(func);
7789         for (i = base; i < base + ILT_PER_FUNC; i++)
7790                 bnx2x_ilt_wr(bp, i, 0);
7791 }
7792
7793 static void bnx2x_init_searcher(struct bnx2x *bp)
7794 {
7795         int port = BP_PORT(bp);
7796         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7797         /* T1 hash bits value determines the T1 number of entries */
7798         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7799 }
7800
7801 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7802 {
7803         int rc;
7804         struct bnx2x_func_state_params func_params = {NULL};
7805         struct bnx2x_func_switch_update_params *switch_update_params =
7806                 &func_params.params.switch_update;
7807
7808         /* Prepare parameters for function state transitions */
7809         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7810         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7811
7812         func_params.f_obj = &bp->func_obj;
7813         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7814
7815         /* Function parameters */
7816         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7817                   &switch_update_params->changes);
7818         if (suspend)
7819                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7820                           &switch_update_params->changes);
7821
7822         rc = bnx2x_func_state_change(bp, &func_params);
7823
7824         return rc;
7825 }
7826
7827 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7828 {
7829         int rc, i, port = BP_PORT(bp);
7830         int vlan_en = 0, mac_en[NUM_MACS];
7831
7832         /* Close input from network */
7833         if (bp->mf_mode == SINGLE_FUNCTION) {
7834                 bnx2x_set_rx_filter(&bp->link_params, 0);
7835         } else {
7836                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7837                                    NIG_REG_LLH0_FUNC_EN);
7838                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7839                           NIG_REG_LLH0_FUNC_EN, 0);
7840                 for (i = 0; i < NUM_MACS; i++) {
7841                         mac_en[i] = REG_RD(bp, port ?
7842                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7843                                               4 * i) :
7844                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7845                                               4 * i));
7846                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7847                                               4 * i) :
7848                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7849                 }
7850         }
7851
7852         /* Close BMC to host */
7853         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7854                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7855
7856         /* Suspend Tx switching to the PF. Completion of this ramrod
7857          * further guarantees that all the packets of that PF / child
7858          * VFs in BRB were processed by the Parser, so it is safe to
7859          * change the NIC_MODE register.
7860          */
7861         rc = bnx2x_func_switch_update(bp, 1);
7862         if (rc) {
7863                 BNX2X_ERR("Can't suspend tx-switching!\n");
7864                 return rc;
7865         }
7866
7867         /* Change NIC_MODE register */
7868         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7869
7870         /* Open input from network */
7871         if (bp->mf_mode == SINGLE_FUNCTION) {
7872                 bnx2x_set_rx_filter(&bp->link_params, 1);
7873         } else {
7874                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7875                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7876                 for (i = 0; i < NUM_MACS; i++) {
7877                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7878                                               4 * i) :
7879                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7880                                   mac_en[i]);
7881                 }
7882         }
7883
7884         /* Enable BMC to host */
7885         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7886                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7887
7888         /* Resume Tx switching to the PF */
7889         rc = bnx2x_func_switch_update(bp, 0);
7890         if (rc) {
7891                 BNX2X_ERR("Can't resume tx-switching!\n");
7892                 return rc;
7893         }
7894
7895         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7896         return 0;
7897 }
7898
7899 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7900 {
7901         int rc;
7902
7903         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7904
7905         if (CONFIGURE_NIC_MODE(bp)) {
7906                 /* Configure searcher as part of function hw init */
7907                 bnx2x_init_searcher(bp);
7908
7909                 /* Reset NIC mode */
7910                 rc = bnx2x_reset_nic_mode(bp);
7911                 if (rc)
7912                         BNX2X_ERR("Can't change NIC mode!\n");
7913                 return rc;
7914         }
7915
7916         return 0;
7917 }
7918
7919 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7920  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7921  * the addresses of the transaction, resulting in was-error bit set in the pci
7922  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7923  * to clear the interrupt which detected this from the pglueb and the was done
7924  * bit
7925  */
7926 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7927 {
7928         if (!CHIP_IS_E1x(bp))
7929                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7930                        1 << BP_ABS_FUNC(bp));
7931 }
7932
7933 static int bnx2x_init_hw_func(struct bnx2x *bp)
7934 {
7935         int port = BP_PORT(bp);
7936         int func = BP_FUNC(bp);
7937         int init_phase = PHASE_PF0 + func;
7938         struct bnx2x_ilt *ilt = BP_ILT(bp);
7939         u16 cdu_ilt_start;
7940         u32 addr, val;
7941         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7942         int i, main_mem_width, rc;
7943
7944         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7945
7946         /* FLR cleanup - hmmm */
7947         if (!CHIP_IS_E1x(bp)) {
7948                 rc = bnx2x_pf_flr_clnup(bp);
7949                 if (rc) {
7950                         bnx2x_fw_dump(bp);
7951                         return rc;
7952                 }
7953         }
7954
7955         /* set MSI reconfigure capability */
7956         if (bp->common.int_block == INT_BLOCK_HC) {
7957                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7958                 val = REG_RD(bp, addr);
7959                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7960                 REG_WR(bp, addr, val);
7961         }
7962
7963         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7964         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7965
7966         ilt = BP_ILT(bp);
7967         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7968
7969         if (IS_SRIOV(bp))
7970                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7971         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7972
7973         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7974          * those of the VFs, so start line should be reset
7975          */
7976         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7977         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7978                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7979                 ilt->lines[cdu_ilt_start + i].page_mapping =
7980                         bp->context[i].cxt_mapping;
7981                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7982         }
7983
7984         bnx2x_ilt_init_op(bp, INITOP_SET);
7985
7986         if (!CONFIGURE_NIC_MODE(bp)) {
7987                 bnx2x_init_searcher(bp);
7988                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7989                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7990         } else {
7991                 /* Set NIC mode */
7992                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7993                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7994         }
7995
7996         if (!CHIP_IS_E1x(bp)) {
7997                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7998
7999                 /* Turn on a single ISR mode in IGU if driver is going to use
8000                  * INT#x or MSI
8001                  */
8002                 if (!(bp->flags & USING_MSIX_FLAG))
8003                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8004                 /*
8005                  * Timers workaround bug: function init part.
8006                  * Need to wait 20msec after initializing ILT,
8007                  * needed to make sure there are no requests in
8008                  * one of the PXP internal queues with "old" ILT addresses
8009                  */
8010                 msleep(20);
8011                 /*
8012                  * Master enable - Due to WB DMAE writes performed before this
8013                  * register is re-initialized as part of the regular function
8014                  * init
8015                  */
8016                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8017                 /* Enable the function in IGU */
8018                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8019         }
8020
8021         bp->dmae_ready = 1;
8022
8023         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8024
8025         bnx2x_clean_pglue_errors(bp);
8026
8027         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8028         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8029         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8030         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8031         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8032         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8033         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8034         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8035         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8036         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8037         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8038         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8039         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8040
8041         if (!CHIP_IS_E1x(bp))
8042                 REG_WR(bp, QM_REG_PF_EN, 1);
8043
8044         if (!CHIP_IS_E1x(bp)) {
8045                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8046                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8047                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8048                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8049         }
8050         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8051
8052         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8053         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8054         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8055
8056         bnx2x_iov_init_dq(bp);
8057
8058         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8059         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8060         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8061         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8062         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8063         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8064         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8065         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8066         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8067         if (!CHIP_IS_E1x(bp))
8068                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8069
8070         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8071
8072         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8073
8074         if (!CHIP_IS_E1x(bp))
8075                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8076
8077         if (IS_MF(bp)) {
8078                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8079                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8080                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8081                                bp->mf_ov);
8082                 }
8083         }
8084
8085         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8086
8087         /* HC init per function */
8088         if (bp->common.int_block == INT_BLOCK_HC) {
8089                 if (CHIP_IS_E1H(bp)) {
8090                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8091
8092                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8093                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8094                 }
8095                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8096
8097         } else {
8098                 int num_segs, sb_idx, prod_offset;
8099
8100                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8101
8102                 if (!CHIP_IS_E1x(bp)) {
8103                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8104                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8105                 }
8106
8107                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8108
8109                 if (!CHIP_IS_E1x(bp)) {
8110                         int dsb_idx = 0;
8111                         /**
8112                          * Producer memory:
8113                          * E2 mode: address 0-135 match to the mapping memory;
8114                          * 136 - PF0 default prod; 137 - PF1 default prod;
8115                          * 138 - PF2 default prod; 139 - PF3 default prod;
8116                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8117                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8118                          * 144-147 reserved.
8119                          *
8120                          * E1.5 mode - In backward compatible mode;
8121                          * for non default SB; each even line in the memory
8122                          * holds the U producer and each odd line hold
8123                          * the C producer. The first 128 producers are for
8124                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8125                          * producers are for the DSB for each PF.
8126                          * Each PF has five segments: (the order inside each
8127                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8128                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8129                          * 144-147 attn prods;
8130                          */
8131                         /* non-default-status-blocks */
8132                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8133                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8134                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8135                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8136                                         num_segs;
8137
8138                                 for (i = 0; i < num_segs; i++) {
8139                                         addr = IGU_REG_PROD_CONS_MEMORY +
8140                                                         (prod_offset + i) * 4;
8141                                         REG_WR(bp, addr, 0);
8142                                 }
8143                                 /* send consumer update with value 0 */
8144                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8145                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8146                                 bnx2x_igu_clear_sb(bp,
8147                                                    bp->igu_base_sb + sb_idx);
8148                         }
8149
8150                         /* default-status-blocks */
8151                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8152                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8153
8154                         if (CHIP_MODE_IS_4_PORT(bp))
8155                                 dsb_idx = BP_FUNC(bp);
8156                         else
8157                                 dsb_idx = BP_VN(bp);
8158
8159                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8160                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8161                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8162
8163                         /*
8164                          * igu prods come in chunks of E1HVN_MAX (4) -
8165                          * does not matters what is the current chip mode
8166                          */
8167                         for (i = 0; i < (num_segs * E1HVN_MAX);
8168                              i += E1HVN_MAX) {
8169                                 addr = IGU_REG_PROD_CONS_MEMORY +
8170                                                         (prod_offset + i)*4;
8171                                 REG_WR(bp, addr, 0);
8172                         }
8173                         /* send consumer update with 0 */
8174                         if (CHIP_INT_MODE_IS_BC(bp)) {
8175                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8176                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8177                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8178                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8179                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8180                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8181                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8182                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8183                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8184                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8185                         } else {
8186                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8187                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8188                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8189                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8190                         }
8191                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8192
8193                         /* !!! These should become driver const once
8194                            rf-tool supports split-68 const */
8195                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8196                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8197                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8198                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8199                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8200                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8201                 }
8202         }
8203
8204         /* Reset PCIE errors for debug */
8205         REG_WR(bp, 0x2114, 0xffffffff);
8206         REG_WR(bp, 0x2120, 0xffffffff);
8207
8208         if (CHIP_IS_E1x(bp)) {
8209                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8210                 main_mem_base = HC_REG_MAIN_MEMORY +
8211                                 BP_PORT(bp) * (main_mem_size * 4);
8212                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8213                 main_mem_width = 8;
8214
8215                 val = REG_RD(bp, main_mem_prty_clr);
8216                 if (val)
8217                         DP(NETIF_MSG_HW,
8218                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8219                            val);
8220
8221                 /* Clear "false" parity errors in MSI-X table */
8222                 for (i = main_mem_base;
8223                      i < main_mem_base + main_mem_size * 4;
8224                      i += main_mem_width) {
8225                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8226                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8227                                          i, main_mem_width / 4);
8228                 }
8229                 /* Clear HC parity attention */
8230                 REG_RD(bp, main_mem_prty_clr);
8231         }
8232
8233 #ifdef BNX2X_STOP_ON_ERROR
8234         /* Enable STORMs SP logging */
8235         REG_WR8(bp, BAR_USTRORM_INTMEM +
8236                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8237         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8238                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8239         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8240                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8241         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8242                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8243 #endif
8244
8245         bnx2x_phy_probe(&bp->link_params);
8246
8247         return 0;
8248 }
8249
8250 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8251 {
8252         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8253
8254         if (!CHIP_IS_E1x(bp))
8255                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8256                                sizeof(struct host_hc_status_block_e2));
8257         else
8258                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8259                                sizeof(struct host_hc_status_block_e1x));
8260
8261         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8262 }
8263
8264 void bnx2x_free_mem(struct bnx2x *bp)
8265 {
8266         int i;
8267
8268         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8269                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8270
8271         if (IS_VF(bp))
8272                 return;
8273
8274         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8275                        sizeof(struct host_sp_status_block));
8276
8277         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8278                        sizeof(struct bnx2x_slowpath));
8279
8280         for (i = 0; i < L2_ILT_LINES(bp); i++)
8281                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8282                                bp->context[i].size);
8283         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8284
8285         BNX2X_FREE(bp->ilt->lines);
8286
8287         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8288
8289         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8290                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8291
8292         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8293
8294         bnx2x_iov_free_mem(bp);
8295 }
8296
8297 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8298 {
8299         if (!CHIP_IS_E1x(bp)) {
8300                 /* size = the status block + ramrod buffers */
8301                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8302                                                     sizeof(struct host_hc_status_block_e2));
8303                 if (!bp->cnic_sb.e2_sb)
8304                         goto alloc_mem_err;
8305         } else {
8306                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8307                                                      sizeof(struct host_hc_status_block_e1x));
8308                 if (!bp->cnic_sb.e1x_sb)
8309                         goto alloc_mem_err;
8310         }
8311
8312         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8313                 /* allocate searcher T2 table, as it wasn't allocated before */
8314                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8315                 if (!bp->t2)
8316                         goto alloc_mem_err;
8317         }
8318
8319         /* write address to which L5 should insert its values */
8320         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8321                 &bp->slowpath->drv_info_to_mcp;
8322
8323         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8324                 goto alloc_mem_err;
8325
8326         return 0;
8327
8328 alloc_mem_err:
8329         bnx2x_free_mem_cnic(bp);
8330         BNX2X_ERR("Can't allocate memory\n");
8331         return -ENOMEM;
8332 }
8333
8334 int bnx2x_alloc_mem(struct bnx2x *bp)
8335 {
8336         int i, allocated, context_size;
8337
8338         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8339                 /* allocate searcher T2 table */
8340                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8341                 if (!bp->t2)
8342                         goto alloc_mem_err;
8343         }
8344
8345         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8346                                              sizeof(struct host_sp_status_block));
8347         if (!bp->def_status_blk)
8348                 goto alloc_mem_err;
8349
8350         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8351                                        sizeof(struct bnx2x_slowpath));
8352         if (!bp->slowpath)
8353                 goto alloc_mem_err;
8354
8355         /* Allocate memory for CDU context:
8356          * This memory is allocated separately and not in the generic ILT
8357          * functions because CDU differs in few aspects:
8358          * 1. There are multiple entities allocating memory for context -
8359          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8360          * its own ILT lines.
8361          * 2. Since CDU page-size is not a single 4KB page (which is the case
8362          * for the other ILT clients), to be efficient we want to support
8363          * allocation of sub-page-size in the last entry.
8364          * 3. Context pointers are used by the driver to pass to FW / update
8365          * the context (for the other ILT clients the pointers are used just to
8366          * free the memory during unload).
8367          */
8368         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8369
8370         for (i = 0, allocated = 0; allocated < context_size; i++) {
8371                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8372                                           (context_size - allocated));
8373                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8374                                                       bp->context[i].size);
8375                 if (!bp->context[i].vcxt)
8376                         goto alloc_mem_err;
8377                 allocated += bp->context[i].size;
8378         }
8379         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8380                                  GFP_KERNEL);
8381         if (!bp->ilt->lines)
8382                 goto alloc_mem_err;
8383
8384         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8385                 goto alloc_mem_err;
8386
8387         if (bnx2x_iov_alloc_mem(bp))
8388                 goto alloc_mem_err;
8389
8390         /* Slow path ring */
8391         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8392         if (!bp->spq)
8393                 goto alloc_mem_err;
8394
8395         /* EQ */
8396         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8397                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8398         if (!bp->eq_ring)
8399                 goto alloc_mem_err;
8400
8401         return 0;
8402
8403 alloc_mem_err:
8404         bnx2x_free_mem(bp);
8405         BNX2X_ERR("Can't allocate memory\n");
8406         return -ENOMEM;
8407 }
8408
8409 /*
8410  * Init service functions
8411  */
8412
8413 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8414                       struct bnx2x_vlan_mac_obj *obj, bool set,
8415                       int mac_type, unsigned long *ramrod_flags)
8416 {
8417         int rc;
8418         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8419
8420         memset(&ramrod_param, 0, sizeof(ramrod_param));
8421
8422         /* Fill general parameters */
8423         ramrod_param.vlan_mac_obj = obj;
8424         ramrod_param.ramrod_flags = *ramrod_flags;
8425
8426         /* Fill a user request section if needed */
8427         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8428                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8429
8430                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8431
8432                 /* Set the command: ADD or DEL */
8433                 if (set)
8434                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8435                 else
8436                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8437         }
8438
8439         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8440
8441         if (rc == -EEXIST) {
8442                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8443                 /* do not treat adding same MAC as error */
8444                 rc = 0;
8445         } else if (rc < 0)
8446                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8447
8448         return rc;
8449 }
8450
8451 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8452                        struct bnx2x_vlan_mac_obj *obj, bool set,
8453                        unsigned long *ramrod_flags)
8454 {
8455         int rc;
8456         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8457
8458         memset(&ramrod_param, 0, sizeof(ramrod_param));
8459
8460         /* Fill general parameters */
8461         ramrod_param.vlan_mac_obj = obj;
8462         ramrod_param.ramrod_flags = *ramrod_flags;
8463
8464         /* Fill a user request section if needed */
8465         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8466                 ramrod_param.user_req.u.vlan.vlan = vlan;
8467                 /* Set the command: ADD or DEL */
8468                 if (set)
8469                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8470                 else
8471                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8472         }
8473
8474         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8475
8476         if (rc == -EEXIST) {
8477                 /* Do not treat adding same vlan as error. */
8478                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8479                 rc = 0;
8480         } else if (rc < 0) {
8481                 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8482         }
8483
8484         return rc;
8485 }
8486
8487 int bnx2x_del_all_macs(struct bnx2x *bp,
8488                        struct bnx2x_vlan_mac_obj *mac_obj,
8489                        int mac_type, bool wait_for_comp)
8490 {
8491         int rc;
8492         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8493
8494         /* Wait for completion of requested */
8495         if (wait_for_comp)
8496                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8497
8498         /* Set the mac type of addresses we want to clear */
8499         __set_bit(mac_type, &vlan_mac_flags);
8500
8501         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8502         if (rc < 0)
8503                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8504
8505         return rc;
8506 }
8507
8508 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8509 {
8510         if (IS_PF(bp)) {
8511                 unsigned long ramrod_flags = 0;
8512
8513                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8514                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8515                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8516                                          &bp->sp_objs->mac_obj, set,
8517                                          BNX2X_ETH_MAC, &ramrod_flags);
8518         } else { /* vf */
8519                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8520                                              bp->fp->index, set);
8521         }
8522 }
8523
8524 int bnx2x_setup_leading(struct bnx2x *bp)
8525 {
8526         if (IS_PF(bp))
8527                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8528         else /* VF */
8529                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8530 }
8531
8532 /**
8533  * bnx2x_set_int_mode - configure interrupt mode
8534  *
8535  * @bp:         driver handle
8536  *
8537  * In case of MSI-X it will also try to enable MSI-X.
8538  */
8539 int bnx2x_set_int_mode(struct bnx2x *bp)
8540 {
8541         int rc = 0;
8542
8543         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8544                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8545                 return -EINVAL;
8546         }
8547
8548         switch (int_mode) {
8549         case BNX2X_INT_MODE_MSIX:
8550                 /* attempt to enable msix */
8551                 rc = bnx2x_enable_msix(bp);
8552
8553                 /* msix attained */
8554                 if (!rc)
8555                         return 0;
8556
8557                 /* vfs use only msix */
8558                 if (rc && IS_VF(bp))
8559                         return rc;
8560
8561                 /* failed to enable multiple MSI-X */
8562                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8563                                bp->num_queues,
8564                                1 + bp->num_cnic_queues);
8565
8566                 /* falling through... */
8567         case BNX2X_INT_MODE_MSI:
8568                 bnx2x_enable_msi(bp);
8569
8570                 /* falling through... */
8571         case BNX2X_INT_MODE_INTX:
8572                 bp->num_ethernet_queues = 1;
8573                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8574                 BNX2X_DEV_INFO("set number of queues to 1\n");
8575                 break;
8576         default:
8577                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8578                 return -EINVAL;
8579         }
8580         return 0;
8581 }
8582
8583 /* must be called prior to any HW initializations */
8584 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8585 {
8586         if (IS_SRIOV(bp))
8587                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8588         return L2_ILT_LINES(bp);
8589 }
8590
8591 void bnx2x_ilt_set_info(struct bnx2x *bp)
8592 {
8593         struct ilt_client_info *ilt_client;
8594         struct bnx2x_ilt *ilt = BP_ILT(bp);
8595         u16 line = 0;
8596
8597         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8598         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8599
8600         /* CDU */
8601         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8602         ilt_client->client_num = ILT_CLIENT_CDU;
8603         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8604         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8605         ilt_client->start = line;
8606         line += bnx2x_cid_ilt_lines(bp);
8607
8608         if (CNIC_SUPPORT(bp))
8609                 line += CNIC_ILT_LINES;
8610         ilt_client->end = line - 1;
8611
8612         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8613            ilt_client->start,
8614            ilt_client->end,
8615            ilt_client->page_size,
8616            ilt_client->flags,
8617            ilog2(ilt_client->page_size >> 12));
8618
8619         /* QM */
8620         if (QM_INIT(bp->qm_cid_count)) {
8621                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8622                 ilt_client->client_num = ILT_CLIENT_QM;
8623                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8624                 ilt_client->flags = 0;
8625                 ilt_client->start = line;
8626
8627                 /* 4 bytes for each cid */
8628                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8629                                                          QM_ILT_PAGE_SZ);
8630
8631                 ilt_client->end = line - 1;
8632
8633                 DP(NETIF_MSG_IFUP,
8634                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8635                    ilt_client->start,
8636                    ilt_client->end,
8637                    ilt_client->page_size,
8638                    ilt_client->flags,
8639                    ilog2(ilt_client->page_size >> 12));
8640         }
8641
8642         if (CNIC_SUPPORT(bp)) {
8643                 /* SRC */
8644                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8645                 ilt_client->client_num = ILT_CLIENT_SRC;
8646                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8647                 ilt_client->flags = 0;
8648                 ilt_client->start = line;
8649                 line += SRC_ILT_LINES;
8650                 ilt_client->end = line - 1;
8651
8652                 DP(NETIF_MSG_IFUP,
8653                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8654                    ilt_client->start,
8655                    ilt_client->end,
8656                    ilt_client->page_size,
8657                    ilt_client->flags,
8658                    ilog2(ilt_client->page_size >> 12));
8659
8660                 /* TM */
8661                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8662                 ilt_client->client_num = ILT_CLIENT_TM;
8663                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8664                 ilt_client->flags = 0;
8665                 ilt_client->start = line;
8666                 line += TM_ILT_LINES;
8667                 ilt_client->end = line - 1;
8668
8669                 DP(NETIF_MSG_IFUP,
8670                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8671                    ilt_client->start,
8672                    ilt_client->end,
8673                    ilt_client->page_size,
8674                    ilt_client->flags,
8675                    ilog2(ilt_client->page_size >> 12));
8676         }
8677
8678         BUG_ON(line > ILT_MAX_LINES);
8679 }
8680
8681 /**
8682  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8683  *
8684  * @bp:                 driver handle
8685  * @fp:                 pointer to fastpath
8686  * @init_params:        pointer to parameters structure
8687  *
8688  * parameters configured:
8689  *      - HC configuration
8690  *      - Queue's CDU context
8691  */
8692 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8693         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8694 {
8695         u8 cos;
8696         int cxt_index, cxt_offset;
8697
8698         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8699         if (!IS_FCOE_FP(fp)) {
8700                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8701                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8702
8703                 /* If HC is supported, enable host coalescing in the transition
8704                  * to INIT state.
8705                  */
8706                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8707                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8708
8709                 /* HC rate */
8710                 init_params->rx.hc_rate = bp->rx_ticks ?
8711                         (1000000 / bp->rx_ticks) : 0;
8712                 init_params->tx.hc_rate = bp->tx_ticks ?
8713                         (1000000 / bp->tx_ticks) : 0;
8714
8715                 /* FW SB ID */
8716                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8717                         fp->fw_sb_id;
8718
8719                 /*
8720                  * CQ index among the SB indices: FCoE clients uses the default
8721                  * SB, therefore it's different.
8722                  */
8723                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8724                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8725         }
8726
8727         /* set maximum number of COSs supported by this queue */
8728         init_params->max_cos = fp->max_cos;
8729
8730         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8731             fp->index, init_params->max_cos);
8732
8733         /* set the context pointers queue object */
8734         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8735                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8736                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8737                                 ILT_PAGE_CIDS);
8738                 init_params->cxts[cos] =
8739                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8740         }
8741 }
8742
8743 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8744                         struct bnx2x_queue_state_params *q_params,
8745                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8746                         int tx_index, bool leading)
8747 {
8748         memset(tx_only_params, 0, sizeof(*tx_only_params));
8749
8750         /* Set the command */
8751         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8752
8753         /* Set tx-only QUEUE flags: don't zero statistics */
8754         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8755
8756         /* choose the index of the cid to send the slow path on */
8757         tx_only_params->cid_index = tx_index;
8758
8759         /* Set general TX_ONLY_SETUP parameters */
8760         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8761
8762         /* Set Tx TX_ONLY_SETUP parameters */
8763         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8764
8765         DP(NETIF_MSG_IFUP,
8766            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8767            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8768            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8769            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8770
8771         /* send the ramrod */
8772         return bnx2x_queue_state_change(bp, q_params);
8773 }
8774
8775 /**
8776  * bnx2x_setup_queue - setup queue
8777  *
8778  * @bp:         driver handle
8779  * @fp:         pointer to fastpath
8780  * @leading:    is leading
8781  *
8782  * This function performs 2 steps in a Queue state machine
8783  *      actually: 1) RESET->INIT 2) INIT->SETUP
8784  */
8785
8786 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8787                        bool leading)
8788 {
8789         struct bnx2x_queue_state_params q_params = {NULL};
8790         struct bnx2x_queue_setup_params *setup_params =
8791                                                 &q_params.params.setup;
8792         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8793                                                 &q_params.params.tx_only;
8794         int rc;
8795         u8 tx_index;
8796
8797         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8798
8799         /* reset IGU state skip FCoE L2 queue */
8800         if (!IS_FCOE_FP(fp))
8801                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8802                              IGU_INT_ENABLE, 0);
8803
8804         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8805         /* We want to wait for completion in this context */
8806         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8807
8808         /* Prepare the INIT parameters */
8809         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8810
8811         /* Set the command */
8812         q_params.cmd = BNX2X_Q_CMD_INIT;
8813
8814         /* Change the state to INIT */
8815         rc = bnx2x_queue_state_change(bp, &q_params);
8816         if (rc) {
8817                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8818                 return rc;
8819         }
8820
8821         DP(NETIF_MSG_IFUP, "init complete\n");
8822
8823         /* Now move the Queue to the SETUP state... */
8824         memset(setup_params, 0, sizeof(*setup_params));
8825
8826         /* Set QUEUE flags */
8827         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8828
8829         /* Set general SETUP parameters */
8830         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8831                                 FIRST_TX_COS_INDEX);
8832
8833         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8834                             &setup_params->rxq_params);
8835
8836         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8837                            FIRST_TX_COS_INDEX);
8838
8839         /* Set the command */
8840         q_params.cmd = BNX2X_Q_CMD_SETUP;
8841
8842         if (IS_FCOE_FP(fp))
8843                 bp->fcoe_init = true;
8844
8845         /* Change the state to SETUP */
8846         rc = bnx2x_queue_state_change(bp, &q_params);
8847         if (rc) {
8848                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8849                 return rc;
8850         }
8851
8852         /* loop through the relevant tx-only indices */
8853         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8854               tx_index < fp->max_cos;
8855               tx_index++) {
8856
8857                 /* prepare and send tx-only ramrod*/
8858                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8859                                           tx_only_params, tx_index, leading);
8860                 if (rc) {
8861                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8862                                   fp->index, tx_index);
8863                         return rc;
8864                 }
8865         }
8866
8867         return rc;
8868 }
8869
8870 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8871 {
8872         struct bnx2x_fastpath *fp = &bp->fp[index];
8873         struct bnx2x_fp_txdata *txdata;
8874         struct bnx2x_queue_state_params q_params = {NULL};
8875         int rc, tx_index;
8876
8877         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8878
8879         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8880         /* We want to wait for completion in this context */
8881         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8882
8883         /* close tx-only connections */
8884         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8885              tx_index < fp->max_cos;
8886              tx_index++){
8887
8888                 /* ascertain this is a normal queue*/
8889                 txdata = fp->txdata_ptr[tx_index];
8890
8891                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8892                                                         txdata->txq_index);
8893
8894                 /* send halt terminate on tx-only connection */
8895                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8896                 memset(&q_params.params.terminate, 0,
8897                        sizeof(q_params.params.terminate));
8898                 q_params.params.terminate.cid_index = tx_index;
8899
8900                 rc = bnx2x_queue_state_change(bp, &q_params);
8901                 if (rc)
8902                         return rc;
8903
8904                 /* send halt terminate on tx-only connection */
8905                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8906                 memset(&q_params.params.cfc_del, 0,
8907                        sizeof(q_params.params.cfc_del));
8908                 q_params.params.cfc_del.cid_index = tx_index;
8909                 rc = bnx2x_queue_state_change(bp, &q_params);
8910                 if (rc)
8911                         return rc;
8912         }
8913         /* Stop the primary connection: */
8914         /* ...halt the connection */
8915         q_params.cmd = BNX2X_Q_CMD_HALT;
8916         rc = bnx2x_queue_state_change(bp, &q_params);
8917         if (rc)
8918                 return rc;
8919
8920         /* ...terminate the connection */
8921         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8922         memset(&q_params.params.terminate, 0,
8923                sizeof(q_params.params.terminate));
8924         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8925         rc = bnx2x_queue_state_change(bp, &q_params);
8926         if (rc)
8927                 return rc;
8928         /* ...delete cfc entry */
8929         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8930         memset(&q_params.params.cfc_del, 0,
8931                sizeof(q_params.params.cfc_del));
8932         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8933         return bnx2x_queue_state_change(bp, &q_params);
8934 }
8935
8936 static void bnx2x_reset_func(struct bnx2x *bp)
8937 {
8938         int port = BP_PORT(bp);
8939         int func = BP_FUNC(bp);
8940         int i;
8941
8942         /* Disable the function in the FW */
8943         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8944         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8945         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8946         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8947
8948         /* FP SBs */
8949         for_each_eth_queue(bp, i) {
8950                 struct bnx2x_fastpath *fp = &bp->fp[i];
8951                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8952                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8953                            SB_DISABLED);
8954         }
8955
8956         if (CNIC_LOADED(bp))
8957                 /* CNIC SB */
8958                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8959                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8960                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8961
8962         /* SP SB */
8963         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8964                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8965                 SB_DISABLED);
8966
8967         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8968                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8969                        0);
8970
8971         /* Configure IGU */
8972         if (bp->common.int_block == INT_BLOCK_HC) {
8973                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8974                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8975         } else {
8976                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8977                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8978         }
8979
8980         if (CNIC_LOADED(bp)) {
8981                 /* Disable Timer scan */
8982                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8983                 /*
8984                  * Wait for at least 10ms and up to 2 second for the timers
8985                  * scan to complete
8986                  */
8987                 for (i = 0; i < 200; i++) {
8988                         usleep_range(10000, 20000);
8989                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8990                                 break;
8991                 }
8992         }
8993         /* Clear ILT */
8994         bnx2x_clear_func_ilt(bp, func);
8995
8996         /* Timers workaround bug for E2: if this is vnic-3,
8997          * we need to set the entire ilt range for this timers.
8998          */
8999         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
9000                 struct ilt_client_info ilt_cli;
9001                 /* use dummy TM client */
9002                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9003                 ilt_cli.start = 0;
9004                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9005                 ilt_cli.client_num = ILT_CLIENT_TM;
9006
9007                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9008         }
9009
9010         /* this assumes that reset_port() called before reset_func()*/
9011         if (!CHIP_IS_E1x(bp))
9012                 bnx2x_pf_disable(bp);
9013
9014         bp->dmae_ready = 0;
9015 }
9016
9017 static void bnx2x_reset_port(struct bnx2x *bp)
9018 {
9019         int port = BP_PORT(bp);
9020         u32 val;
9021
9022         /* Reset physical Link */
9023         bnx2x__link_reset(bp);
9024
9025         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9026
9027         /* Do not rcv packets to BRB */
9028         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9029         /* Do not direct rcv packets that are not for MCP to the BRB */
9030         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9031                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9032
9033         /* Configure AEU */
9034         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9035
9036         msleep(100);
9037         /* Check for BRB port occupancy */
9038         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9039         if (val)
9040                 DP(NETIF_MSG_IFDOWN,
9041                    "BRB1 is not empty  %d blocks are occupied\n", val);
9042
9043         /* TODO: Close Doorbell port? */
9044 }
9045
9046 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9047 {
9048         struct bnx2x_func_state_params func_params = {NULL};
9049
9050         /* Prepare parameters for function state transitions */
9051         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9052
9053         func_params.f_obj = &bp->func_obj;
9054         func_params.cmd = BNX2X_F_CMD_HW_RESET;
9055
9056         func_params.params.hw_init.load_phase = load_code;
9057
9058         return bnx2x_func_state_change(bp, &func_params);
9059 }
9060
9061 static int bnx2x_func_stop(struct bnx2x *bp)
9062 {
9063         struct bnx2x_func_state_params func_params = {NULL};
9064         int rc;
9065
9066         /* Prepare parameters for function state transitions */
9067         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9068         func_params.f_obj = &bp->func_obj;
9069         func_params.cmd = BNX2X_F_CMD_STOP;
9070
9071         /*
9072          * Try to stop the function the 'good way'. If fails (in case
9073          * of a parity error during bnx2x_chip_cleanup()) and we are
9074          * not in a debug mode, perform a state transaction in order to
9075          * enable further HW_RESET transaction.
9076          */
9077         rc = bnx2x_func_state_change(bp, &func_params);
9078         if (rc) {
9079 #ifdef BNX2X_STOP_ON_ERROR
9080                 return rc;
9081 #else
9082                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9083                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9084                 return bnx2x_func_state_change(bp, &func_params);
9085 #endif
9086         }
9087
9088         return 0;
9089 }
9090
9091 /**
9092  * bnx2x_send_unload_req - request unload mode from the MCP.
9093  *
9094  * @bp:                 driver handle
9095  * @unload_mode:        requested function's unload mode
9096  *
9097  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9098  */
9099 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9100 {
9101         u32 reset_code = 0;
9102         int port = BP_PORT(bp);
9103
9104         /* Select the UNLOAD request mode */
9105         if (unload_mode == UNLOAD_NORMAL)
9106                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9107
9108         else if (bp->flags & NO_WOL_FLAG)
9109                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9110
9111         else if (bp->wol) {
9112                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9113                 u8 *mac_addr = bp->dev->dev_addr;
9114                 struct pci_dev *pdev = bp->pdev;
9115                 u32 val;
9116                 u16 pmc;
9117
9118                 /* The mac address is written to entries 1-4 to
9119                  * preserve entry 0 which is used by the PMF
9120                  */
9121                 u8 entry = (BP_VN(bp) + 1)*8;
9122
9123                 val = (mac_addr[0] << 8) | mac_addr[1];
9124                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9125
9126                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9127                       (mac_addr[4] << 8) | mac_addr[5];
9128                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9129
9130                 /* Enable the PME and clear the status */
9131                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9132                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9133                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9134
9135                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9136
9137         } else
9138                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9139
9140         /* Send the request to the MCP */
9141         if (!BP_NOMCP(bp))
9142                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9143         else {
9144                 int path = BP_PATH(bp);
9145
9146                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9147                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9148                    bnx2x_load_count[path][2]);
9149                 bnx2x_load_count[path][0]--;
9150                 bnx2x_load_count[path][1 + port]--;
9151                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9152                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9153                    bnx2x_load_count[path][2]);
9154                 if (bnx2x_load_count[path][0] == 0)
9155                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9156                 else if (bnx2x_load_count[path][1 + port] == 0)
9157                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9158                 else
9159                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9160         }
9161
9162         return reset_code;
9163 }
9164
9165 /**
9166  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9167  *
9168  * @bp:         driver handle
9169  * @keep_link:          true iff link should be kept up
9170  */
9171 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9172 {
9173         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9174
9175         /* Report UNLOAD_DONE to MCP */
9176         if (!BP_NOMCP(bp))
9177                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9178 }
9179
9180 static int bnx2x_func_wait_started(struct bnx2x *bp)
9181 {
9182         int tout = 50;
9183         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9184
9185         if (!bp->port.pmf)
9186                 return 0;
9187
9188         /*
9189          * (assumption: No Attention from MCP at this stage)
9190          * PMF probably in the middle of TX disable/enable transaction
9191          * 1. Sync IRS for default SB
9192          * 2. Sync SP queue - this guarantees us that attention handling started
9193          * 3. Wait, that TX disable/enable transaction completes
9194          *
9195          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9196          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9197          * received completion for the transaction the state is TX_STOPPED.
9198          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9199          * transaction.
9200          */
9201
9202         /* make sure default SB ISR is done */
9203         if (msix)
9204                 synchronize_irq(bp->msix_table[0].vector);
9205         else
9206                 synchronize_irq(bp->pdev->irq);
9207
9208         flush_workqueue(bnx2x_wq);
9209         flush_workqueue(bnx2x_iov_wq);
9210
9211         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9212                                 BNX2X_F_STATE_STARTED && tout--)
9213                 msleep(20);
9214
9215         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9216                                                 BNX2X_F_STATE_STARTED) {
9217 #ifdef BNX2X_STOP_ON_ERROR
9218                 BNX2X_ERR("Wrong function state\n");
9219                 return -EBUSY;
9220 #else
9221                 /*
9222                  * Failed to complete the transaction in a "good way"
9223                  * Force both transactions with CLR bit
9224                  */
9225                 struct bnx2x_func_state_params func_params = {NULL};
9226
9227                 DP(NETIF_MSG_IFDOWN,
9228                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9229
9230                 func_params.f_obj = &bp->func_obj;
9231                 __set_bit(RAMROD_DRV_CLR_ONLY,
9232                                         &func_params.ramrod_flags);
9233
9234                 /* STARTED-->TX_ST0PPED */
9235                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9236                 bnx2x_func_state_change(bp, &func_params);
9237
9238                 /* TX_ST0PPED-->STARTED */
9239                 func_params.cmd = BNX2X_F_CMD_TX_START;
9240                 return bnx2x_func_state_change(bp, &func_params);
9241 #endif
9242         }
9243
9244         return 0;
9245 }
9246
9247 static void bnx2x_disable_ptp(struct bnx2x *bp)
9248 {
9249         int port = BP_PORT(bp);
9250
9251         /* Disable sending PTP packets to host */
9252         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9253                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9254
9255         /* Reset PTP event detection rules */
9256         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9257                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9258         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9259                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9260         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9261                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9262         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9263                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9264
9265         /* Disable the PTP feature */
9266         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9267                NIG_REG_P0_PTP_EN, 0x0);
9268 }
9269
9270 /* Called during unload, to stop PTP-related stuff */
9271 static void bnx2x_stop_ptp(struct bnx2x *bp)
9272 {
9273         /* Cancel PTP work queue. Should be done after the Tx queues are
9274          * drained to prevent additional scheduling.
9275          */
9276         cancel_work_sync(&bp->ptp_task);
9277
9278         if (bp->ptp_tx_skb) {
9279                 dev_kfree_skb_any(bp->ptp_tx_skb);
9280                 bp->ptp_tx_skb = NULL;
9281         }
9282
9283         /* Disable PTP in HW */
9284         bnx2x_disable_ptp(bp);
9285
9286         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9287 }
9288
9289 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9290 {
9291         int port = BP_PORT(bp);
9292         int i, rc = 0;
9293         u8 cos;
9294         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9295         u32 reset_code;
9296
9297         /* Wait until tx fastpath tasks complete */
9298         for_each_tx_queue(bp, i) {
9299                 struct bnx2x_fastpath *fp = &bp->fp[i];
9300
9301                 for_each_cos_in_tx_queue(fp, cos)
9302                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9303 #ifdef BNX2X_STOP_ON_ERROR
9304                 if (rc)
9305                         return;
9306 #endif
9307         }
9308
9309         /* Give HW time to discard old tx messages */
9310         usleep_range(1000, 2000);
9311
9312         /* Clean all ETH MACs */
9313         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9314                                 false);
9315         if (rc < 0)
9316                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9317
9318         /* Clean up UC list  */
9319         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9320                                 true);
9321         if (rc < 0)
9322                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9323                           rc);
9324
9325         /* Disable LLH */
9326         if (!CHIP_IS_E1(bp))
9327                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9328
9329         /* Set "drop all" (stop Rx).
9330          * We need to take a netif_addr_lock() here in order to prevent
9331          * a race between the completion code and this code.
9332          */
9333         netif_addr_lock_bh(bp->dev);
9334         /* Schedule the rx_mode command */
9335         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9336                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9337         else
9338                 bnx2x_set_storm_rx_mode(bp);
9339
9340         /* Cleanup multicast configuration */
9341         rparam.mcast_obj = &bp->mcast_obj;
9342         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9343         if (rc < 0)
9344                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9345
9346         netif_addr_unlock_bh(bp->dev);
9347
9348         bnx2x_iov_chip_cleanup(bp);
9349
9350         /*
9351          * Send the UNLOAD_REQUEST to the MCP. This will return if
9352          * this function should perform FUNC, PORT or COMMON HW
9353          * reset.
9354          */
9355         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9356
9357         /*
9358          * (assumption: No Attention from MCP at this stage)
9359          * PMF probably in the middle of TX disable/enable transaction
9360          */
9361         rc = bnx2x_func_wait_started(bp);
9362         if (rc) {
9363                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9364 #ifdef BNX2X_STOP_ON_ERROR
9365                 return;
9366 #endif
9367         }
9368
9369         /* Close multi and leading connections
9370          * Completions for ramrods are collected in a synchronous way
9371          */
9372         for_each_eth_queue(bp, i)
9373                 if (bnx2x_stop_queue(bp, i))
9374 #ifdef BNX2X_STOP_ON_ERROR
9375                         return;
9376 #else
9377                         goto unload_error;
9378 #endif
9379
9380         if (CNIC_LOADED(bp)) {
9381                 for_each_cnic_queue(bp, i)
9382                         if (bnx2x_stop_queue(bp, i))
9383 #ifdef BNX2X_STOP_ON_ERROR
9384                                 return;
9385 #else
9386                                 goto unload_error;
9387 #endif
9388         }
9389
9390         /* If SP settings didn't get completed so far - something
9391          * very wrong has happen.
9392          */
9393         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9394                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9395
9396 #ifndef BNX2X_STOP_ON_ERROR
9397 unload_error:
9398 #endif
9399         rc = bnx2x_func_stop(bp);
9400         if (rc) {
9401                 BNX2X_ERR("Function stop failed!\n");
9402 #ifdef BNX2X_STOP_ON_ERROR
9403                 return;
9404 #endif
9405         }
9406
9407         /* stop_ptp should be after the Tx queues are drained to prevent
9408          * scheduling to the cancelled PTP work queue. It should also be after
9409          * function stop ramrod is sent, since as part of this ramrod FW access
9410          * PTP registers.
9411          */
9412         if (bp->flags & PTP_SUPPORTED)
9413                 bnx2x_stop_ptp(bp);
9414
9415         /* Disable HW interrupts, NAPI */
9416         bnx2x_netif_stop(bp, 1);
9417         /* Delete all NAPI objects */
9418         bnx2x_del_all_napi(bp);
9419         if (CNIC_LOADED(bp))
9420                 bnx2x_del_all_napi_cnic(bp);
9421
9422         /* Release IRQs */
9423         bnx2x_free_irq(bp);
9424
9425         /* Reset the chip */
9426         rc = bnx2x_reset_hw(bp, reset_code);
9427         if (rc)
9428                 BNX2X_ERR("HW_RESET failed\n");
9429
9430         /* Report UNLOAD_DONE to MCP */
9431         bnx2x_send_unload_done(bp, keep_link);
9432 }
9433
9434 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9435 {
9436         u32 val;
9437
9438         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9439
9440         if (CHIP_IS_E1(bp)) {
9441                 int port = BP_PORT(bp);
9442                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9443                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9444
9445                 val = REG_RD(bp, addr);
9446                 val &= ~(0x300);
9447                 REG_WR(bp, addr, val);
9448         } else {
9449                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9450                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9451                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9452                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9453         }
9454 }
9455
9456 /* Close gates #2, #3 and #4: */
9457 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9458 {
9459         u32 val;
9460
9461         /* Gates #2 and #4a are closed/opened for "not E1" only */
9462         if (!CHIP_IS_E1(bp)) {
9463                 /* #4 */
9464                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9465                 /* #2 */
9466                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9467         }
9468
9469         /* #3 */
9470         if (CHIP_IS_E1x(bp)) {
9471                 /* Prevent interrupts from HC on both ports */
9472                 val = REG_RD(bp, HC_REG_CONFIG_1);
9473                 REG_WR(bp, HC_REG_CONFIG_1,
9474                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9475                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9476
9477                 val = REG_RD(bp, HC_REG_CONFIG_0);
9478                 REG_WR(bp, HC_REG_CONFIG_0,
9479                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9480                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9481         } else {
9482                 /* Prevent incoming interrupts in IGU */
9483                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9484
9485                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9486                        (!close) ?
9487                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9488                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9489         }
9490
9491         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9492                 close ? "closing" : "opening");
9493         mmiowb();
9494 }
9495
9496 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9497
9498 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9499 {
9500         /* Do some magic... */
9501         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9502         *magic_val = val & SHARED_MF_CLP_MAGIC;
9503         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9504 }
9505
9506 /**
9507  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9508  *
9509  * @bp:         driver handle
9510  * @magic_val:  old value of the `magic' bit.
9511  */
9512 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9513 {
9514         /* Restore the `magic' bit value... */
9515         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9516         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9517                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9518 }
9519
9520 /**
9521  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9522  *
9523  * @bp:         driver handle
9524  * @magic_val:  old value of 'magic' bit.
9525  *
9526  * Takes care of CLP configurations.
9527  */
9528 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9529 {
9530         u32 shmem;
9531         u32 validity_offset;
9532
9533         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9534
9535         /* Set `magic' bit in order to save MF config */
9536         if (!CHIP_IS_E1(bp))
9537                 bnx2x_clp_reset_prep(bp, magic_val);
9538
9539         /* Get shmem offset */
9540         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9541         validity_offset =
9542                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9543
9544         /* Clear validity map flags */
9545         if (shmem > 0)
9546                 REG_WR(bp, shmem + validity_offset, 0);
9547 }
9548
9549 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9550 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9551
9552 /**
9553  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9554  *
9555  * @bp: driver handle
9556  */
9557 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9558 {
9559         /* special handling for emulation and FPGA,
9560            wait 10 times longer */
9561         if (CHIP_REV_IS_SLOW(bp))
9562                 msleep(MCP_ONE_TIMEOUT*10);
9563         else
9564                 msleep(MCP_ONE_TIMEOUT);
9565 }
9566
9567 /*
9568  * initializes bp->common.shmem_base and waits for validity signature to appear
9569  */
9570 static int bnx2x_init_shmem(struct bnx2x *bp)
9571 {
9572         int cnt = 0;
9573         u32 val = 0;
9574
9575         do {
9576                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9577
9578                 /* If we read all 0xFFs, means we are in PCI error state and
9579                  * should bail out to avoid crashes on adapter's FW reads.
9580                  */
9581                 if (bp->common.shmem_base == 0xFFFFFFFF) {
9582                         bp->flags |= NO_MCP_FLAG;
9583                         return -ENODEV;
9584                 }
9585
9586                 if (bp->common.shmem_base) {
9587                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9588                         if (val & SHR_MEM_VALIDITY_MB)
9589                                 return 0;
9590                 }
9591
9592                 bnx2x_mcp_wait_one(bp);
9593
9594         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9595
9596         BNX2X_ERR("BAD MCP validity signature\n");
9597
9598         return -ENODEV;
9599 }
9600
9601 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9602 {
9603         int rc = bnx2x_init_shmem(bp);
9604
9605         /* Restore the `magic' bit value */
9606         if (!CHIP_IS_E1(bp))
9607                 bnx2x_clp_reset_done(bp, magic_val);
9608
9609         return rc;
9610 }
9611
9612 static void bnx2x_pxp_prep(struct bnx2x *bp)
9613 {
9614         if (!CHIP_IS_E1(bp)) {
9615                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9616                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9617                 mmiowb();
9618         }
9619 }
9620
9621 /*
9622  * Reset the whole chip except for:
9623  *      - PCIE core
9624  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9625  *              one reset bit)
9626  *      - IGU
9627  *      - MISC (including AEU)
9628  *      - GRC
9629  *      - RBCN, RBCP
9630  */
9631 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9632 {
9633         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9634         u32 global_bits2, stay_reset2;
9635
9636         /*
9637          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9638          * (per chip) blocks.
9639          */
9640         global_bits2 =
9641                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9642                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9643
9644         /* Don't reset the following blocks.
9645          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9646          *            reset, as in 4 port device they might still be owned
9647          *            by the MCP (there is only one leader per path).
9648          */
9649         not_reset_mask1 =
9650                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9651                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9652                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9653
9654         not_reset_mask2 =
9655                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9656                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9657                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9658                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9659                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9660                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9661                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9662                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9663                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9664                 MISC_REGISTERS_RESET_REG_2_PGLC |
9665                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9666                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9667                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9668                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9669                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9670                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9671
9672         /*
9673          * Keep the following blocks in reset:
9674          *  - all xxMACs are handled by the bnx2x_link code.
9675          */
9676         stay_reset2 =
9677                 MISC_REGISTERS_RESET_REG_2_XMAC |
9678                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9679
9680         /* Full reset masks according to the chip */
9681         reset_mask1 = 0xffffffff;
9682
9683         if (CHIP_IS_E1(bp))
9684                 reset_mask2 = 0xffff;
9685         else if (CHIP_IS_E1H(bp))
9686                 reset_mask2 = 0x1ffff;
9687         else if (CHIP_IS_E2(bp))
9688                 reset_mask2 = 0xfffff;
9689         else /* CHIP_IS_E3 */
9690                 reset_mask2 = 0x3ffffff;
9691
9692         /* Don't reset global blocks unless we need to */
9693         if (!global)
9694                 reset_mask2 &= ~global_bits2;
9695
9696         /*
9697          * In case of attention in the QM, we need to reset PXP
9698          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9699          * because otherwise QM reset would release 'close the gates' shortly
9700          * before resetting the PXP, then the PSWRQ would send a write
9701          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9702          * read the payload data from PSWWR, but PSWWR would not
9703          * respond. The write queue in PGLUE would stuck, dmae commands
9704          * would not return. Therefore it's important to reset the second
9705          * reset register (containing the
9706          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9707          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9708          * bit).
9709          */
9710         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9711                reset_mask2 & (~not_reset_mask2));
9712
9713         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9714                reset_mask1 & (~not_reset_mask1));
9715
9716         barrier();
9717         mmiowb();
9718
9719         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9720                reset_mask2 & (~stay_reset2));
9721
9722         barrier();
9723         mmiowb();
9724
9725         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9726         mmiowb();
9727 }
9728
9729 /**
9730  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9731  * It should get cleared in no more than 1s.
9732  *
9733  * @bp: driver handle
9734  *
9735  * It should get cleared in no more than 1s. Returns 0 if
9736  * pending writes bit gets cleared.
9737  */
9738 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9739 {
9740         u32 cnt = 1000;
9741         u32 pend_bits = 0;
9742
9743         do {
9744                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9745
9746                 if (pend_bits == 0)
9747                         break;
9748
9749                 usleep_range(1000, 2000);
9750         } while (cnt-- > 0);
9751
9752         if (cnt <= 0) {
9753                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9754                           pend_bits);
9755                 return -EBUSY;
9756         }
9757
9758         return 0;
9759 }
9760
9761 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9762 {
9763         int cnt = 1000;
9764         u32 val = 0;
9765         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9766         u32 tags_63_32 = 0;
9767
9768         /* Empty the Tetris buffer, wait for 1s */
9769         do {
9770                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9771                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9772                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9773                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9774                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9775                 if (CHIP_IS_E3(bp))
9776                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9777
9778                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9779                     ((port_is_idle_0 & 0x1) == 0x1) &&
9780                     ((port_is_idle_1 & 0x1) == 0x1) &&
9781                     (pgl_exp_rom2 == 0xffffffff) &&
9782                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9783                         break;
9784                 usleep_range(1000, 2000);
9785         } while (cnt-- > 0);
9786
9787         if (cnt <= 0) {
9788                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9789                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9790                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9791                           pgl_exp_rom2);
9792                 return -EAGAIN;
9793         }
9794
9795         barrier();
9796
9797         /* Close gates #2, #3 and #4 */
9798         bnx2x_set_234_gates(bp, true);
9799
9800         /* Poll for IGU VQs for 57712 and newer chips */
9801         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9802                 return -EAGAIN;
9803
9804         /* TBD: Indicate that "process kill" is in progress to MCP */
9805
9806         /* Clear "unprepared" bit */
9807         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9808         barrier();
9809
9810         /* Make sure all is written to the chip before the reset */
9811         mmiowb();
9812
9813         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9814          * PSWHST, GRC and PSWRD Tetris buffer.
9815          */
9816         usleep_range(1000, 2000);
9817
9818         /* Prepare to chip reset: */
9819         /* MCP */
9820         if (global)
9821                 bnx2x_reset_mcp_prep(bp, &val);
9822
9823         /* PXP */
9824         bnx2x_pxp_prep(bp);
9825         barrier();
9826
9827         /* reset the chip */
9828         bnx2x_process_kill_chip_reset(bp, global);
9829         barrier();
9830
9831         /* clear errors in PGB */
9832         if (!CHIP_IS_E1x(bp))
9833                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9834
9835         /* Recover after reset: */
9836         /* MCP */
9837         if (global && bnx2x_reset_mcp_comp(bp, val))
9838                 return -EAGAIN;
9839
9840         /* TBD: Add resetting the NO_MCP mode DB here */
9841
9842         /* Open the gates #2, #3 and #4 */
9843         bnx2x_set_234_gates(bp, false);
9844
9845         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9846          * reset state, re-enable attentions. */
9847
9848         return 0;
9849 }
9850
9851 static int bnx2x_leader_reset(struct bnx2x *bp)
9852 {
9853         int rc = 0;
9854         bool global = bnx2x_reset_is_global(bp);
9855         u32 load_code;
9856
9857         /* if not going to reset MCP - load "fake" driver to reset HW while
9858          * driver is owner of the HW
9859          */
9860         if (!global && !BP_NOMCP(bp)) {
9861                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9862                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9863                 if (!load_code) {
9864                         BNX2X_ERR("MCP response failure, aborting\n");
9865                         rc = -EAGAIN;
9866                         goto exit_leader_reset;
9867                 }
9868                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9869                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9870                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9871                         rc = -EAGAIN;
9872                         goto exit_leader_reset2;
9873                 }
9874                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9875                 if (!load_code) {
9876                         BNX2X_ERR("MCP response failure, aborting\n");
9877                         rc = -EAGAIN;
9878                         goto exit_leader_reset2;
9879                 }
9880         }
9881
9882         /* Try to recover after the failure */
9883         if (bnx2x_process_kill(bp, global)) {
9884                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9885                           BP_PATH(bp));
9886                 rc = -EAGAIN;
9887                 goto exit_leader_reset2;
9888         }
9889
9890         /*
9891          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9892          * state.
9893          */
9894         bnx2x_set_reset_done(bp);
9895         if (global)
9896                 bnx2x_clear_reset_global(bp);
9897
9898 exit_leader_reset2:
9899         /* unload "fake driver" if it was loaded */
9900         if (!global && !BP_NOMCP(bp)) {
9901                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9902                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9903         }
9904 exit_leader_reset:
9905         bp->is_leader = 0;
9906         bnx2x_release_leader_lock(bp);
9907         smp_mb();
9908         return rc;
9909 }
9910
9911 static void bnx2x_recovery_failed(struct bnx2x *bp)
9912 {
9913         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9914
9915         /* Disconnect this device */
9916         netif_device_detach(bp->dev);
9917
9918         /*
9919          * Block ifup for all function on this engine until "process kill"
9920          * or power cycle.
9921          */
9922         bnx2x_set_reset_in_progress(bp);
9923
9924         /* Shut down the power */
9925         bnx2x_set_power_state(bp, PCI_D3hot);
9926
9927         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9928
9929         smp_mb();
9930 }
9931
9932 /*
9933  * Assumption: runs under rtnl lock. This together with the fact
9934  * that it's called only from bnx2x_sp_rtnl() ensure that it
9935  * will never be called when netif_running(bp->dev) is false.
9936  */
9937 static void bnx2x_parity_recover(struct bnx2x *bp)
9938 {
9939         u32 error_recovered, error_unrecovered;
9940         bool is_parity, global = false;
9941 #ifdef CONFIG_BNX2X_SRIOV
9942         int vf_idx;
9943
9944         for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) {
9945                 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
9946
9947                 if (vf)
9948                         vf->state = VF_LOST;
9949         }
9950 #endif
9951         DP(NETIF_MSG_HW, "Handling parity\n");
9952         while (1) {
9953                 switch (bp->recovery_state) {
9954                 case BNX2X_RECOVERY_INIT:
9955                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9956                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9957                         WARN_ON(!is_parity);
9958
9959                         /* Try to get a LEADER_LOCK HW lock */
9960                         if (bnx2x_trylock_leader_lock(bp)) {
9961                                 bnx2x_set_reset_in_progress(bp);
9962                                 /*
9963                                  * Check if there is a global attention and if
9964                                  * there was a global attention, set the global
9965                                  * reset bit.
9966                                  */
9967
9968                                 if (global)
9969                                         bnx2x_set_reset_global(bp);
9970
9971                                 bp->is_leader = 1;
9972                         }
9973
9974                         /* Stop the driver */
9975                         /* If interface has been removed - break */
9976                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9977                                 return;
9978
9979                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9980
9981                         /* Ensure "is_leader", MCP command sequence and
9982                          * "recovery_state" update values are seen on other
9983                          * CPUs.
9984                          */
9985                         smp_mb();
9986                         break;
9987
9988                 case BNX2X_RECOVERY_WAIT:
9989                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9990                         if (bp->is_leader) {
9991                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9992                                 bool other_load_status =
9993                                         bnx2x_get_load_status(bp, other_engine);
9994                                 bool load_status =
9995                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9996                                 global = bnx2x_reset_is_global(bp);
9997
9998                                 /*
9999                                  * In case of a parity in a global block, let
10000                                  * the first leader that performs a
10001                                  * leader_reset() reset the global blocks in
10002                                  * order to clear global attentions. Otherwise
10003                                  * the gates will remain closed for that
10004                                  * engine.
10005                                  */
10006                                 if (load_status ||
10007                                     (global && other_load_status)) {
10008                                         /* Wait until all other functions get
10009                                          * down.
10010                                          */
10011                                         schedule_delayed_work(&bp->sp_rtnl_task,
10012                                                                 HZ/10);
10013                                         return;
10014                                 } else {
10015                                         /* If all other functions got down -
10016                                          * try to bring the chip back to
10017                                          * normal. In any case it's an exit
10018                                          * point for a leader.
10019                                          */
10020                                         if (bnx2x_leader_reset(bp)) {
10021                                                 bnx2x_recovery_failed(bp);
10022                                                 return;
10023                                         }
10024
10025                                         /* If we are here, means that the
10026                                          * leader has succeeded and doesn't
10027                                          * want to be a leader any more. Try
10028                                          * to continue as a none-leader.
10029                                          */
10030                                         break;
10031                                 }
10032                         } else { /* non-leader */
10033                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10034                                         /* Try to get a LEADER_LOCK HW lock as
10035                                          * long as a former leader may have
10036                                          * been unloaded by the user or
10037                                          * released a leadership by another
10038                                          * reason.
10039                                          */
10040                                         if (bnx2x_trylock_leader_lock(bp)) {
10041                                                 /* I'm a leader now! Restart a
10042                                                  * switch case.
10043                                                  */
10044                                                 bp->is_leader = 1;
10045                                                 break;
10046                                         }
10047
10048                                         schedule_delayed_work(&bp->sp_rtnl_task,
10049                                                                 HZ/10);
10050                                         return;
10051
10052                                 } else {
10053                                         /*
10054                                          * If there was a global attention, wait
10055                                          * for it to be cleared.
10056                                          */
10057                                         if (bnx2x_reset_is_global(bp)) {
10058                                                 schedule_delayed_work(
10059                                                         &bp->sp_rtnl_task,
10060                                                         HZ/10);
10061                                                 return;
10062                                         }
10063
10064                                         error_recovered =
10065                                           bp->eth_stats.recoverable_error;
10066                                         error_unrecovered =
10067                                           bp->eth_stats.unrecoverable_error;
10068                                         bp->recovery_state =
10069                                                 BNX2X_RECOVERY_NIC_LOADING;
10070                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10071                                                 error_unrecovered++;
10072                                                 netdev_err(bp->dev,
10073                                                            "Recovery failed. Power cycle needed\n");
10074                                                 /* Disconnect this device */
10075                                                 netif_device_detach(bp->dev);
10076                                                 /* Shut down the power */
10077                                                 bnx2x_set_power_state(
10078                                                         bp, PCI_D3hot);
10079                                                 smp_mb();
10080                                         } else {
10081                                                 bp->recovery_state =
10082                                                         BNX2X_RECOVERY_DONE;
10083                                                 error_recovered++;
10084                                                 smp_mb();
10085                                         }
10086                                         bp->eth_stats.recoverable_error =
10087                                                 error_recovered;
10088                                         bp->eth_stats.unrecoverable_error =
10089                                                 error_unrecovered;
10090
10091                                         return;
10092                                 }
10093                         }
10094                 default:
10095                         return;
10096                 }
10097         }
10098 }
10099
10100 #ifdef CONFIG_BNX2X_VXLAN
10101 static int bnx2x_vxlan_port_update(struct bnx2x *bp, u16 port)
10102 {
10103         struct bnx2x_func_switch_update_params *switch_update_params;
10104         struct bnx2x_func_state_params func_params = {NULL};
10105         int rc;
10106
10107         switch_update_params = &func_params.params.switch_update;
10108
10109         /* Prepare parameters for function state transitions */
10110         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10111         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10112
10113         func_params.f_obj = &bp->func_obj;
10114         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10115
10116         /* Function parameters */
10117         __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10118                   &switch_update_params->changes);
10119         switch_update_params->vxlan_dst_port = port;
10120         rc = bnx2x_func_state_change(bp, &func_params);
10121         if (rc)
10122                 BNX2X_ERR("failed to change vxlan dst port to %d (rc = 0x%x)\n",
10123                           port, rc);
10124         return rc;
10125 }
10126
10127 static void __bnx2x_add_vxlan_port(struct bnx2x *bp, u16 port)
10128 {
10129         if (!netif_running(bp->dev))
10130                 return;
10131
10132         if (bp->vxlan_dst_port_count && bp->vxlan_dst_port == port) {
10133                 bp->vxlan_dst_port_count++;
10134                 return;
10135         }
10136
10137         if (bp->vxlan_dst_port_count || !IS_PF(bp)) {
10138                 DP(BNX2X_MSG_SP, "Vxlan destination port limit reached\n");
10139                 return;
10140         }
10141
10142         bp->vxlan_dst_port = port;
10143         bp->vxlan_dst_port_count = 1;
10144         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_ADD_VXLAN_PORT, 0);
10145 }
10146
10147 static void bnx2x_add_vxlan_port(struct net_device *netdev,
10148                                  sa_family_t sa_family, __be16 port)
10149 {
10150         struct bnx2x *bp = netdev_priv(netdev);
10151         u16 t_port = ntohs(port);
10152
10153         __bnx2x_add_vxlan_port(bp, t_port);
10154 }
10155
10156 static void __bnx2x_del_vxlan_port(struct bnx2x *bp, u16 port)
10157 {
10158         if (!bp->vxlan_dst_port_count || bp->vxlan_dst_port != port ||
10159             !IS_PF(bp)) {
10160                 DP(BNX2X_MSG_SP, "Invalid vxlan port\n");
10161                 return;
10162         }
10163         bp->vxlan_dst_port_count--;
10164         if (bp->vxlan_dst_port_count)
10165                 return;
10166
10167         if (netif_running(bp->dev)) {
10168                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_DEL_VXLAN_PORT, 0);
10169         } else {
10170                 bp->vxlan_dst_port = 0;
10171                 netdev_info(bp->dev, "Deleted vxlan dest port %d", port);
10172         }
10173 }
10174
10175 static void bnx2x_del_vxlan_port(struct net_device *netdev,
10176                                  sa_family_t sa_family, __be16 port)
10177 {
10178         struct bnx2x *bp = netdev_priv(netdev);
10179         u16 t_port = ntohs(port);
10180
10181         __bnx2x_del_vxlan_port(bp, t_port);
10182 }
10183 #endif
10184
10185 static int bnx2x_close(struct net_device *dev);
10186
10187 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10188  * scheduled on a general queue in order to prevent a dead lock.
10189  */
10190 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10191 {
10192         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10193 #ifdef CONFIG_BNX2X_VXLAN
10194         u16 port;
10195 #endif
10196
10197         rtnl_lock();
10198
10199         if (!netif_running(bp->dev)) {
10200                 rtnl_unlock();
10201                 return;
10202         }
10203
10204         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10205 #ifdef BNX2X_STOP_ON_ERROR
10206                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10207                           "you will need to reboot when done\n");
10208                 goto sp_rtnl_not_reset;
10209 #endif
10210                 /*
10211                  * Clear all pending SP commands as we are going to reset the
10212                  * function anyway.
10213                  */
10214                 bp->sp_rtnl_state = 0;
10215                 smp_mb();
10216
10217                 bnx2x_parity_recover(bp);
10218
10219                 rtnl_unlock();
10220                 return;
10221         }
10222
10223         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10224 #ifdef BNX2X_STOP_ON_ERROR
10225                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10226                           "you will need to reboot when done\n");
10227                 goto sp_rtnl_not_reset;
10228 #endif
10229
10230                 /*
10231                  * Clear all pending SP commands as we are going to reset the
10232                  * function anyway.
10233                  */
10234                 bp->sp_rtnl_state = 0;
10235                 smp_mb();
10236
10237                 /* Immediately indicate link as down */
10238                 bp->link_vars.link_up = 0;
10239                 bp->force_link_down = true;
10240                 netif_carrier_off(bp->dev);
10241                 BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
10242
10243                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10244                 bnx2x_nic_load(bp, LOAD_NORMAL);
10245
10246                 rtnl_unlock();
10247                 return;
10248         }
10249 #ifdef BNX2X_STOP_ON_ERROR
10250 sp_rtnl_not_reset:
10251 #endif
10252         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10253                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10254         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10255                 bnx2x_after_function_update(bp);
10256         /*
10257          * in case of fan failure we need to reset id if the "stop on error"
10258          * debug flag is set, since we trying to prevent permanent overheating
10259          * damage
10260          */
10261         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10262                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10263                 netif_device_detach(bp->dev);
10264                 bnx2x_close(bp->dev);
10265                 rtnl_unlock();
10266                 return;
10267         }
10268
10269         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10270                 DP(BNX2X_MSG_SP,
10271                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10272                 bnx2x_vfpf_set_mcast(bp->dev);
10273         }
10274         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10275                                &bp->sp_rtnl_state)){
10276                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10277                         bnx2x_tx_disable(bp);
10278                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10279                 }
10280         }
10281
10282         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10283                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10284                 bnx2x_set_rx_mode_inner(bp);
10285         }
10286
10287         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10288                                &bp->sp_rtnl_state))
10289                 bnx2x_pf_set_vfs_vlan(bp);
10290
10291         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10292                 bnx2x_dcbx_stop_hw_tx(bp);
10293                 bnx2x_dcbx_resume_hw_tx(bp);
10294         }
10295
10296         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10297                                &bp->sp_rtnl_state))
10298                 bnx2x_update_mng_version(bp);
10299
10300 #ifdef CONFIG_BNX2X_VXLAN
10301         port = bp->vxlan_dst_port;
10302         if (test_and_clear_bit(BNX2X_SP_RTNL_ADD_VXLAN_PORT,
10303                                &bp->sp_rtnl_state)) {
10304                 if (!bnx2x_vxlan_port_update(bp, port))
10305                         netdev_info(bp->dev, "Added vxlan dest port %d", port);
10306                 else
10307                         bp->vxlan_dst_port = 0;
10308         }
10309
10310         if (test_and_clear_bit(BNX2X_SP_RTNL_DEL_VXLAN_PORT,
10311                                &bp->sp_rtnl_state)) {
10312                 if (!bnx2x_vxlan_port_update(bp, 0)) {
10313                         netdev_info(bp->dev,
10314                                     "Deleted vxlan dest port %d", port);
10315                         bp->vxlan_dst_port = 0;
10316                         vxlan_get_rx_port(bp->dev);
10317                 }
10318         }
10319 #endif
10320
10321         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10322          * can be called from other contexts as well)
10323          */
10324         rtnl_unlock();
10325
10326         /* enable SR-IOV if applicable */
10327         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10328                                                &bp->sp_rtnl_state)) {
10329                 bnx2x_disable_sriov(bp);
10330                 bnx2x_enable_sriov(bp);
10331         }
10332 }
10333
10334 static void bnx2x_period_task(struct work_struct *work)
10335 {
10336         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10337
10338         if (!netif_running(bp->dev))
10339                 goto period_task_exit;
10340
10341         if (CHIP_REV_IS_SLOW(bp)) {
10342                 BNX2X_ERR("period task called on emulation, ignoring\n");
10343                 goto period_task_exit;
10344         }
10345
10346         bnx2x_acquire_phy_lock(bp);
10347         /*
10348          * The barrier is needed to ensure the ordering between the writing to
10349          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10350          * the reading here.
10351          */
10352         smp_mb();
10353         if (bp->port.pmf) {
10354                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10355
10356                 /* Re-queue task in 1 sec */
10357                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10358         }
10359
10360         bnx2x_release_phy_lock(bp);
10361 period_task_exit:
10362         return;
10363 }
10364
10365 /*
10366  * Init service functions
10367  */
10368
10369 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10370 {
10371         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10372         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10373         return base + (BP_ABS_FUNC(bp)) * stride;
10374 }
10375
10376 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10377                                          u8 port, u32 reset_reg,
10378                                          struct bnx2x_mac_vals *vals)
10379 {
10380         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10381         u32 base_addr;
10382
10383         if (!(mask & reset_reg))
10384                 return false;
10385
10386         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10387         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10388         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10389         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10390         REG_WR(bp, vals->umac_addr[port], 0);
10391
10392         return true;
10393 }
10394
10395 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10396                                         struct bnx2x_mac_vals *vals)
10397 {
10398         u32 val, base_addr, offset, mask, reset_reg;
10399         bool mac_stopped = false;
10400         u8 port = BP_PORT(bp);
10401
10402         /* reset addresses as they also mark which values were changed */
10403         memset(vals, 0, sizeof(*vals));
10404
10405         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10406
10407         if (!CHIP_IS_E3(bp)) {
10408                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10409                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10410                 if ((mask & reset_reg) && val) {
10411                         u32 wb_data[2];
10412                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10413                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10414                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10415                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10416                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10417
10418                         /*
10419                          * use rd/wr since we cannot use dmae. This is safe
10420                          * since MCP won't access the bus due to the request
10421                          * to unload, and no function on the path can be
10422                          * loaded at this time.
10423                          */
10424                         wb_data[0] = REG_RD(bp, base_addr + offset);
10425                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10426                         vals->bmac_addr = base_addr + offset;
10427                         vals->bmac_val[0] = wb_data[0];
10428                         vals->bmac_val[1] = wb_data[1];
10429                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10430                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10431                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10432                 }
10433                 BNX2X_DEV_INFO("Disable emac Rx\n");
10434                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10435                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10436                 REG_WR(bp, vals->emac_addr, 0);
10437                 mac_stopped = true;
10438         } else {
10439                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10440                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10441                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10442                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10443                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10444                                val & ~(1 << 1));
10445                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10446                                val | (1 << 1));
10447                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10448                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10449                         REG_WR(bp, vals->xmac_addr, 0);
10450                         mac_stopped = true;
10451                 }
10452
10453                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10454                                                             reset_reg, vals);
10455                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10456                                                             reset_reg, vals);
10457         }
10458
10459         if (mac_stopped)
10460                 msleep(20);
10461 }
10462
10463 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10464 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10465                                         0x1848 + ((f) << 4))
10466 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10467 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10468 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10469
10470 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10471 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10472 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10473
10474 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10475 {
10476         /* UNDI marks its presence in DORQ -
10477          * it initializes CID offset for normal bell to 0x7
10478          */
10479         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10480             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10481                 return false;
10482
10483         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10484                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10485                 return true;
10486         }
10487
10488         return false;
10489 }
10490
10491 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10492 {
10493         u16 rcq, bd;
10494         u32 addr, tmp_reg;
10495
10496         if (BP_FUNC(bp) < 2)
10497                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10498         else
10499                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10500
10501         tmp_reg = REG_RD(bp, addr);
10502         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10503         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10504
10505         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10506         REG_WR(bp, addr, tmp_reg);
10507
10508         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10509                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10510 }
10511
10512 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10513 {
10514         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10515                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10516         if (!rc) {
10517                 BNX2X_ERR("MCP response failure, aborting\n");
10518                 return -EBUSY;
10519         }
10520
10521         return 0;
10522 }
10523
10524 static struct bnx2x_prev_path_list *
10525                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10526 {
10527         struct bnx2x_prev_path_list *tmp_list;
10528
10529         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10530                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10531                     bp->pdev->bus->number == tmp_list->bus &&
10532                     BP_PATH(bp) == tmp_list->path)
10533                         return tmp_list;
10534
10535         return NULL;
10536 }
10537
10538 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10539 {
10540         struct bnx2x_prev_path_list *tmp_list;
10541         int rc;
10542
10543         rc = down_interruptible(&bnx2x_prev_sem);
10544         if (rc) {
10545                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10546                 return rc;
10547         }
10548
10549         tmp_list = bnx2x_prev_path_get_entry(bp);
10550         if (tmp_list) {
10551                 tmp_list->aer = 1;
10552                 rc = 0;
10553         } else {
10554                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10555                           BP_PATH(bp));
10556         }
10557
10558         up(&bnx2x_prev_sem);
10559
10560         return rc;
10561 }
10562
10563 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10564 {
10565         struct bnx2x_prev_path_list *tmp_list;
10566         bool rc = false;
10567
10568         if (down_trylock(&bnx2x_prev_sem))
10569                 return false;
10570
10571         tmp_list = bnx2x_prev_path_get_entry(bp);
10572         if (tmp_list) {
10573                 if (tmp_list->aer) {
10574                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10575                            BP_PATH(bp));
10576                 } else {
10577                         rc = true;
10578                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10579                                        BP_PATH(bp));
10580                 }
10581         }
10582
10583         up(&bnx2x_prev_sem);
10584
10585         return rc;
10586 }
10587
10588 bool bnx2x_port_after_undi(struct bnx2x *bp)
10589 {
10590         struct bnx2x_prev_path_list *entry;
10591         bool val;
10592
10593         down(&bnx2x_prev_sem);
10594
10595         entry = bnx2x_prev_path_get_entry(bp);
10596         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10597
10598         up(&bnx2x_prev_sem);
10599
10600         return val;
10601 }
10602
10603 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10604 {
10605         struct bnx2x_prev_path_list *tmp_list;
10606         int rc;
10607
10608         rc = down_interruptible(&bnx2x_prev_sem);
10609         if (rc) {
10610                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10611                 return rc;
10612         }
10613
10614         /* Check whether the entry for this path already exists */
10615         tmp_list = bnx2x_prev_path_get_entry(bp);
10616         if (tmp_list) {
10617                 if (!tmp_list->aer) {
10618                         BNX2X_ERR("Re-Marking the path.\n");
10619                 } else {
10620                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10621                            BP_PATH(bp));
10622                         tmp_list->aer = 0;
10623                 }
10624                 up(&bnx2x_prev_sem);
10625                 return 0;
10626         }
10627         up(&bnx2x_prev_sem);
10628
10629         /* Create an entry for this path and add it */
10630         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10631         if (!tmp_list) {
10632                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10633                 return -ENOMEM;
10634         }
10635
10636         tmp_list->bus = bp->pdev->bus->number;
10637         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10638         tmp_list->path = BP_PATH(bp);
10639         tmp_list->aer = 0;
10640         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10641
10642         rc = down_interruptible(&bnx2x_prev_sem);
10643         if (rc) {
10644                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10645                 kfree(tmp_list);
10646         } else {
10647                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10648                    BP_PATH(bp));
10649                 list_add(&tmp_list->list, &bnx2x_prev_list);
10650                 up(&bnx2x_prev_sem);
10651         }
10652
10653         return rc;
10654 }
10655
10656 static int bnx2x_do_flr(struct bnx2x *bp)
10657 {
10658         struct pci_dev *dev = bp->pdev;
10659
10660         if (CHIP_IS_E1x(bp)) {
10661                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10662                 return -EINVAL;
10663         }
10664
10665         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10666         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10667                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10668                           bp->common.bc_ver);
10669                 return -EINVAL;
10670         }
10671
10672         if (!pci_wait_for_pending_transaction(dev))
10673                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10674
10675         BNX2X_DEV_INFO("Initiating FLR\n");
10676         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10677
10678         return 0;
10679 }
10680
10681 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10682 {
10683         int rc;
10684
10685         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10686
10687         /* Test if previous unload process was already finished for this path */
10688         if (bnx2x_prev_is_path_marked(bp))
10689                 return bnx2x_prev_mcp_done(bp);
10690
10691         BNX2X_DEV_INFO("Path is unmarked\n");
10692
10693         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10694         if (bnx2x_prev_is_after_undi(bp))
10695                 goto out;
10696
10697         /* If function has FLR capabilities, and existing FW version matches
10698          * the one required, then FLR will be sufficient to clean any residue
10699          * left by previous driver
10700          */
10701         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10702
10703         if (!rc) {
10704                 /* fw version is good */
10705                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10706                 rc = bnx2x_do_flr(bp);
10707         }
10708
10709         if (!rc) {
10710                 /* FLR was performed */
10711                 BNX2X_DEV_INFO("FLR successful\n");
10712                 return 0;
10713         }
10714
10715         BNX2X_DEV_INFO("Could not FLR\n");
10716
10717 out:
10718         /* Close the MCP request, return failure*/
10719         rc = bnx2x_prev_mcp_done(bp);
10720         if (!rc)
10721                 rc = BNX2X_PREV_WAIT_NEEDED;
10722
10723         return rc;
10724 }
10725
10726 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10727 {
10728         u32 reset_reg, tmp_reg = 0, rc;
10729         bool prev_undi = false;
10730         struct bnx2x_mac_vals mac_vals;
10731
10732         /* It is possible a previous function received 'common' answer,
10733          * but hasn't loaded yet, therefore creating a scenario of
10734          * multiple functions receiving 'common' on the same path.
10735          */
10736         BNX2X_DEV_INFO("Common unload Flow\n");
10737
10738         memset(&mac_vals, 0, sizeof(mac_vals));
10739
10740         if (bnx2x_prev_is_path_marked(bp))
10741                 return bnx2x_prev_mcp_done(bp);
10742
10743         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10744
10745         /* Reset should be performed after BRB is emptied */
10746         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10747                 u32 timer_count = 1000;
10748
10749                 /* Close the MAC Rx to prevent BRB from filling up */
10750                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10751
10752                 /* close LLH filters for both ports towards the BRB */
10753                 bnx2x_set_rx_filter(&bp->link_params, 0);
10754                 bp->link_params.port ^= 1;
10755                 bnx2x_set_rx_filter(&bp->link_params, 0);
10756                 bp->link_params.port ^= 1;
10757
10758                 /* Check if the UNDI driver was previously loaded */
10759                 if (bnx2x_prev_is_after_undi(bp)) {
10760                         prev_undi = true;
10761                         /* clear the UNDI indication */
10762                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10763                         /* clear possible idle check errors */
10764                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10765                 }
10766                 if (!CHIP_IS_E1x(bp))
10767                         /* block FW from writing to host */
10768                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10769
10770                 /* wait until BRB is empty */
10771                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10772                 while (timer_count) {
10773                         u32 prev_brb = tmp_reg;
10774
10775                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10776                         if (!tmp_reg)
10777                                 break;
10778
10779                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10780
10781                         /* reset timer as long as BRB actually gets emptied */
10782                         if (prev_brb > tmp_reg)
10783                                 timer_count = 1000;
10784                         else
10785                                 timer_count--;
10786
10787                         /* If UNDI resides in memory, manually increment it */
10788                         if (prev_undi)
10789                                 bnx2x_prev_unload_undi_inc(bp, 1);
10790
10791                         udelay(10);
10792                 }
10793
10794                 if (!timer_count)
10795                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10796         }
10797
10798         /* No packets are in the pipeline, path is ready for reset */
10799         bnx2x_reset_common(bp);
10800
10801         if (mac_vals.xmac_addr)
10802                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10803         if (mac_vals.umac_addr[0])
10804                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10805         if (mac_vals.umac_addr[1])
10806                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10807         if (mac_vals.emac_addr)
10808                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10809         if (mac_vals.bmac_addr) {
10810                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10811                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10812         }
10813
10814         rc = bnx2x_prev_mark_path(bp, prev_undi);
10815         if (rc) {
10816                 bnx2x_prev_mcp_done(bp);
10817                 return rc;
10818         }
10819
10820         return bnx2x_prev_mcp_done(bp);
10821 }
10822
10823 static int bnx2x_prev_unload(struct bnx2x *bp)
10824 {
10825         int time_counter = 10;
10826         u32 rc, fw, hw_lock_reg, hw_lock_val;
10827         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10828
10829         /* clear hw from errors which may have resulted from an interrupted
10830          * dmae transaction.
10831          */
10832         bnx2x_clean_pglue_errors(bp);
10833
10834         /* Release previously held locks */
10835         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10836                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10837                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10838
10839         hw_lock_val = REG_RD(bp, hw_lock_reg);
10840         if (hw_lock_val) {
10841                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10842                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10843                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10844                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10845                 }
10846
10847                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10848                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10849         } else
10850                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10851
10852         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10853                 BNX2X_DEV_INFO("Release previously held alr\n");
10854                 bnx2x_release_alr(bp);
10855         }
10856
10857         do {
10858                 int aer = 0;
10859                 /* Lock MCP using an unload request */
10860                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10861                 if (!fw) {
10862                         BNX2X_ERR("MCP response failure, aborting\n");
10863                         rc = -EBUSY;
10864                         break;
10865                 }
10866
10867                 rc = down_interruptible(&bnx2x_prev_sem);
10868                 if (rc) {
10869                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10870                                   rc);
10871                 } else {
10872                         /* If Path is marked by EEH, ignore unload status */
10873                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10874                                  bnx2x_prev_path_get_entry(bp)->aer);
10875                         up(&bnx2x_prev_sem);
10876                 }
10877
10878                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10879                         rc = bnx2x_prev_unload_common(bp);
10880                         break;
10881                 }
10882
10883                 /* non-common reply from MCP might require looping */
10884                 rc = bnx2x_prev_unload_uncommon(bp);
10885                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10886                         break;
10887
10888                 msleep(20);
10889         } while (--time_counter);
10890
10891         if (!time_counter || rc) {
10892                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10893                 rc = -EPROBE_DEFER;
10894         }
10895
10896         /* Mark function if its port was used to boot from SAN */
10897         if (bnx2x_port_after_undi(bp))
10898                 bp->link_params.feature_config_flags |=
10899                         FEATURE_CONFIG_BOOT_FROM_SAN;
10900
10901         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10902
10903         return rc;
10904 }
10905
10906 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10907 {
10908         u32 val, val2, val3, val4, id, boot_mode;
10909         u16 pmc;
10910
10911         /* Get the chip revision id and number. */
10912         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10913         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10914         id = ((val & 0xffff) << 16);
10915         val = REG_RD(bp, MISC_REG_CHIP_REV);
10916         id |= ((val & 0xf) << 12);
10917
10918         /* Metal is read from PCI regs, but we can't access >=0x400 from
10919          * the configuration space (so we need to reg_rd)
10920          */
10921         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10922         id |= (((val >> 24) & 0xf) << 4);
10923         val = REG_RD(bp, MISC_REG_BOND_ID);
10924         id |= (val & 0xf);
10925         bp->common.chip_id = id;
10926
10927         /* force 57811 according to MISC register */
10928         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10929                 if (CHIP_IS_57810(bp))
10930                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10931                                 (bp->common.chip_id & 0x0000FFFF);
10932                 else if (CHIP_IS_57810_MF(bp))
10933                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10934                                 (bp->common.chip_id & 0x0000FFFF);
10935                 bp->common.chip_id |= 0x1;
10936         }
10937
10938         /* Set doorbell size */
10939         bp->db_size = (1 << BNX2X_DB_SHIFT);
10940
10941         if (!CHIP_IS_E1x(bp)) {
10942                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10943                 if ((val & 1) == 0)
10944                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10945                 else
10946                         val = (val >> 1) & 1;
10947                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10948                                                        "2_PORT_MODE");
10949                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10950                                                  CHIP_2_PORT_MODE;
10951
10952                 if (CHIP_MODE_IS_4_PORT(bp))
10953                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10954                 else
10955                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10956         } else {
10957                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10958                 bp->pfid = bp->pf_num;                  /* 0..7 */
10959         }
10960
10961         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10962
10963         bp->link_params.chip_id = bp->common.chip_id;
10964         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10965
10966         val = (REG_RD(bp, 0x2874) & 0x55);
10967         if ((bp->common.chip_id & 0x1) ||
10968             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10969                 bp->flags |= ONE_PORT_FLAG;
10970                 BNX2X_DEV_INFO("single port device\n");
10971         }
10972
10973         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10974         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10975                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10976         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10977                        bp->common.flash_size, bp->common.flash_size);
10978
10979         bnx2x_init_shmem(bp);
10980
10981         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10982                                         MISC_REG_GENERIC_CR_1 :
10983                                         MISC_REG_GENERIC_CR_0));
10984
10985         bp->link_params.shmem_base = bp->common.shmem_base;
10986         bp->link_params.shmem2_base = bp->common.shmem2_base;
10987         if (SHMEM2_RD(bp, size) >
10988             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10989                 bp->link_params.lfa_base =
10990                 REG_RD(bp, bp->common.shmem2_base +
10991                        (u32)offsetof(struct shmem2_region,
10992                                      lfa_host_addr[BP_PORT(bp)]));
10993         else
10994                 bp->link_params.lfa_base = 0;
10995         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10996                        bp->common.shmem_base, bp->common.shmem2_base);
10997
10998         if (!bp->common.shmem_base) {
10999                 BNX2X_DEV_INFO("MCP not active\n");
11000                 bp->flags |= NO_MCP_FLAG;
11001                 return;
11002         }
11003
11004         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
11005         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
11006
11007         bp->link_params.hw_led_mode = ((bp->common.hw_config &
11008                                         SHARED_HW_CFG_LED_MODE_MASK) >>
11009                                        SHARED_HW_CFG_LED_MODE_SHIFT);
11010
11011         bp->link_params.feature_config_flags = 0;
11012         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11013         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11014                 bp->link_params.feature_config_flags |=
11015                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11016         else
11017                 bp->link_params.feature_config_flags &=
11018                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11019
11020         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11021         bp->common.bc_ver = val;
11022         BNX2X_DEV_INFO("bc_ver %X\n", val);
11023         if (val < BNX2X_BC_VER) {
11024                 /* for now only warn
11025                  * later we might need to enforce this */
11026                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11027                           BNX2X_BC_VER, val);
11028         }
11029         bp->link_params.feature_config_flags |=
11030                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11031                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11032
11033         bp->link_params.feature_config_flags |=
11034                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11035                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11036         bp->link_params.feature_config_flags |=
11037                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11038                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11039         bp->link_params.feature_config_flags |=
11040                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11041                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11042
11043         bp->link_params.feature_config_flags |=
11044                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11045                 FEATURE_CONFIG_MT_SUPPORT : 0;
11046
11047         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11048                         BC_SUPPORTS_PFC_STATS : 0;
11049
11050         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11051                         BC_SUPPORTS_FCOE_FEATURES : 0;
11052
11053         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11054                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11055
11056         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11057                         BC_SUPPORTS_RMMOD_CMD : 0;
11058
11059         boot_mode = SHMEM_RD(bp,
11060                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11061                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11062         switch (boot_mode) {
11063         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11064                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11065                 break;
11066         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11067                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11068                 break;
11069         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11070                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11071                 break;
11072         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11073                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11074                 break;
11075         }
11076
11077         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11078         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11079
11080         BNX2X_DEV_INFO("%sWoL capable\n",
11081                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
11082
11083         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11084         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11085         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11086         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11087
11088         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11089                  val, val2, val3, val4);
11090 }
11091
11092 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11093 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11094
11095 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11096 {
11097         int pfid = BP_FUNC(bp);
11098         int igu_sb_id;
11099         u32 val;
11100         u8 fid, igu_sb_cnt = 0;
11101
11102         bp->igu_base_sb = 0xff;
11103         if (CHIP_INT_MODE_IS_BC(bp)) {
11104                 int vn = BP_VN(bp);
11105                 igu_sb_cnt = bp->igu_sb_cnt;
11106                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11107                         FP_SB_MAX_E1x;
11108
11109                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
11110                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11111
11112                 return 0;
11113         }
11114
11115         /* IGU in normal mode - read CAM */
11116         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11117              igu_sb_id++) {
11118                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11119                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11120                         continue;
11121                 fid = IGU_FID(val);
11122                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11123                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11124                                 continue;
11125                         if (IGU_VEC(val) == 0)
11126                                 /* default status block */
11127                                 bp->igu_dsb_id = igu_sb_id;
11128                         else {
11129                                 if (bp->igu_base_sb == 0xff)
11130                                         bp->igu_base_sb = igu_sb_id;
11131                                 igu_sb_cnt++;
11132                         }
11133                 }
11134         }
11135
11136 #ifdef CONFIG_PCI_MSI
11137         /* Due to new PF resource allocation by MFW T7.4 and above, it's
11138          * optional that number of CAM entries will not be equal to the value
11139          * advertised in PCI.
11140          * Driver should use the minimal value of both as the actual status
11141          * block count
11142          */
11143         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11144 #endif
11145
11146         if (igu_sb_cnt == 0) {
11147                 BNX2X_ERR("CAM configuration error\n");
11148                 return -EINVAL;
11149         }
11150
11151         return 0;
11152 }
11153
11154 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11155 {
11156         int cfg_size = 0, idx, port = BP_PORT(bp);
11157
11158         /* Aggregation of supported attributes of all external phys */
11159         bp->port.supported[0] = 0;
11160         bp->port.supported[1] = 0;
11161         switch (bp->link_params.num_phys) {
11162         case 1:
11163                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11164                 cfg_size = 1;
11165                 break;
11166         case 2:
11167                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11168                 cfg_size = 1;
11169                 break;
11170         case 3:
11171                 if (bp->link_params.multi_phy_config &
11172                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11173                         bp->port.supported[1] =
11174                                 bp->link_params.phy[EXT_PHY1].supported;
11175                         bp->port.supported[0] =
11176                                 bp->link_params.phy[EXT_PHY2].supported;
11177                 } else {
11178                         bp->port.supported[0] =
11179                                 bp->link_params.phy[EXT_PHY1].supported;
11180                         bp->port.supported[1] =
11181                                 bp->link_params.phy[EXT_PHY2].supported;
11182                 }
11183                 cfg_size = 2;
11184                 break;
11185         }
11186
11187         if (!(bp->port.supported[0] || bp->port.supported[1])) {
11188                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11189                            SHMEM_RD(bp,
11190                            dev_info.port_hw_config[port].external_phy_config),
11191                            SHMEM_RD(bp,
11192                            dev_info.port_hw_config[port].external_phy_config2));
11193                         return;
11194         }
11195
11196         if (CHIP_IS_E3(bp))
11197                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11198         else {
11199                 switch (switch_cfg) {
11200                 case SWITCH_CFG_1G:
11201                         bp->port.phy_addr = REG_RD(
11202                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11203                         break;
11204                 case SWITCH_CFG_10G:
11205                         bp->port.phy_addr = REG_RD(
11206                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11207                         break;
11208                 default:
11209                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11210                                   bp->port.link_config[0]);
11211                         return;
11212                 }
11213         }
11214         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11215         /* mask what we support according to speed_cap_mask per configuration */
11216         for (idx = 0; idx < cfg_size; idx++) {
11217                 if (!(bp->link_params.speed_cap_mask[idx] &
11218                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11219                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11220
11221                 if (!(bp->link_params.speed_cap_mask[idx] &
11222                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11223                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11224
11225                 if (!(bp->link_params.speed_cap_mask[idx] &
11226                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11227                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11228
11229                 if (!(bp->link_params.speed_cap_mask[idx] &
11230                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11231                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11232
11233                 if (!(bp->link_params.speed_cap_mask[idx] &
11234                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11235                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11236                                                      SUPPORTED_1000baseT_Full);
11237
11238                 if (!(bp->link_params.speed_cap_mask[idx] &
11239                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11240                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11241
11242                 if (!(bp->link_params.speed_cap_mask[idx] &
11243                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11244                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11245
11246                 if (!(bp->link_params.speed_cap_mask[idx] &
11247                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11248                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11249         }
11250
11251         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11252                        bp->port.supported[1]);
11253 }
11254
11255 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11256 {
11257         u32 link_config, idx, cfg_size = 0;
11258         bp->port.advertising[0] = 0;
11259         bp->port.advertising[1] = 0;
11260         switch (bp->link_params.num_phys) {
11261         case 1:
11262         case 2:
11263                 cfg_size = 1;
11264                 break;
11265         case 3:
11266                 cfg_size = 2;
11267                 break;
11268         }
11269         for (idx = 0; idx < cfg_size; idx++) {
11270                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11271                 link_config = bp->port.link_config[idx];
11272                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11273                 case PORT_FEATURE_LINK_SPEED_AUTO:
11274                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11275                                 bp->link_params.req_line_speed[idx] =
11276                                         SPEED_AUTO_NEG;
11277                                 bp->port.advertising[idx] |=
11278                                         bp->port.supported[idx];
11279                                 if (bp->link_params.phy[EXT_PHY1].type ==
11280                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11281                                         bp->port.advertising[idx] |=
11282                                         (SUPPORTED_100baseT_Half |
11283                                          SUPPORTED_100baseT_Full);
11284                         } else {
11285                                 /* force 10G, no AN */
11286                                 bp->link_params.req_line_speed[idx] =
11287                                         SPEED_10000;
11288                                 bp->port.advertising[idx] |=
11289                                         (ADVERTISED_10000baseT_Full |
11290                                          ADVERTISED_FIBRE);
11291                                 continue;
11292                         }
11293                         break;
11294
11295                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11296                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11297                                 bp->link_params.req_line_speed[idx] =
11298                                         SPEED_10;
11299                                 bp->port.advertising[idx] |=
11300                                         (ADVERTISED_10baseT_Full |
11301                                          ADVERTISED_TP);
11302                         } else {
11303                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11304                                             link_config,
11305                                     bp->link_params.speed_cap_mask[idx]);
11306                                 return;
11307                         }
11308                         break;
11309
11310                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11311                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11312                                 bp->link_params.req_line_speed[idx] =
11313                                         SPEED_10;
11314                                 bp->link_params.req_duplex[idx] =
11315                                         DUPLEX_HALF;
11316                                 bp->port.advertising[idx] |=
11317                                         (ADVERTISED_10baseT_Half |
11318                                          ADVERTISED_TP);
11319                         } else {
11320                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11321                                             link_config,
11322                                           bp->link_params.speed_cap_mask[idx]);
11323                                 return;
11324                         }
11325                         break;
11326
11327                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11328                         if (bp->port.supported[idx] &
11329                             SUPPORTED_100baseT_Full) {
11330                                 bp->link_params.req_line_speed[idx] =
11331                                         SPEED_100;
11332                                 bp->port.advertising[idx] |=
11333                                         (ADVERTISED_100baseT_Full |
11334                                          ADVERTISED_TP);
11335                         } else {
11336                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11337                                             link_config,
11338                                           bp->link_params.speed_cap_mask[idx]);
11339                                 return;
11340                         }
11341                         break;
11342
11343                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11344                         if (bp->port.supported[idx] &
11345                             SUPPORTED_100baseT_Half) {
11346                                 bp->link_params.req_line_speed[idx] =
11347                                                                 SPEED_100;
11348                                 bp->link_params.req_duplex[idx] =
11349                                                                 DUPLEX_HALF;
11350                                 bp->port.advertising[idx] |=
11351                                         (ADVERTISED_100baseT_Half |
11352                                          ADVERTISED_TP);
11353                         } else {
11354                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11355                                     link_config,
11356                                     bp->link_params.speed_cap_mask[idx]);
11357                                 return;
11358                         }
11359                         break;
11360
11361                 case PORT_FEATURE_LINK_SPEED_1G:
11362                         if (bp->port.supported[idx] &
11363                             SUPPORTED_1000baseT_Full) {
11364                                 bp->link_params.req_line_speed[idx] =
11365                                         SPEED_1000;
11366                                 bp->port.advertising[idx] |=
11367                                         (ADVERTISED_1000baseT_Full |
11368                                          ADVERTISED_TP);
11369                         } else if (bp->port.supported[idx] &
11370                                    SUPPORTED_1000baseKX_Full) {
11371                                 bp->link_params.req_line_speed[idx] =
11372                                         SPEED_1000;
11373                                 bp->port.advertising[idx] |=
11374                                         ADVERTISED_1000baseKX_Full;
11375                         } else {
11376                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11377                                     link_config,
11378                                     bp->link_params.speed_cap_mask[idx]);
11379                                 return;
11380                         }
11381                         break;
11382
11383                 case PORT_FEATURE_LINK_SPEED_2_5G:
11384                         if (bp->port.supported[idx] &
11385                             SUPPORTED_2500baseX_Full) {
11386                                 bp->link_params.req_line_speed[idx] =
11387                                         SPEED_2500;
11388                                 bp->port.advertising[idx] |=
11389                                         (ADVERTISED_2500baseX_Full |
11390                                                 ADVERTISED_TP);
11391                         } else {
11392                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11393                                     link_config,
11394                                     bp->link_params.speed_cap_mask[idx]);
11395                                 return;
11396                         }
11397                         break;
11398
11399                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11400                         if (bp->port.supported[idx] &
11401                             SUPPORTED_10000baseT_Full) {
11402                                 bp->link_params.req_line_speed[idx] =
11403                                         SPEED_10000;
11404                                 bp->port.advertising[idx] |=
11405                                         (ADVERTISED_10000baseT_Full |
11406                                                 ADVERTISED_FIBRE);
11407                         } else if (bp->port.supported[idx] &
11408                                    SUPPORTED_10000baseKR_Full) {
11409                                 bp->link_params.req_line_speed[idx] =
11410                                         SPEED_10000;
11411                                 bp->port.advertising[idx] |=
11412                                         (ADVERTISED_10000baseKR_Full |
11413                                                 ADVERTISED_FIBRE);
11414                         } else {
11415                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11416                                     link_config,
11417                                     bp->link_params.speed_cap_mask[idx]);
11418                                 return;
11419                         }
11420                         break;
11421                 case PORT_FEATURE_LINK_SPEED_20G:
11422                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11423
11424                         break;
11425                 default:
11426                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11427                                   link_config);
11428                                 bp->link_params.req_line_speed[idx] =
11429                                                         SPEED_AUTO_NEG;
11430                                 bp->port.advertising[idx] =
11431                                                 bp->port.supported[idx];
11432                         break;
11433                 }
11434
11435                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11436                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11437                 if (bp->link_params.req_flow_ctrl[idx] ==
11438                     BNX2X_FLOW_CTRL_AUTO) {
11439                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11440                                 bp->link_params.req_flow_ctrl[idx] =
11441                                                         BNX2X_FLOW_CTRL_NONE;
11442                         else
11443                                 bnx2x_set_requested_fc(bp);
11444                 }
11445
11446                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11447                                bp->link_params.req_line_speed[idx],
11448                                bp->link_params.req_duplex[idx],
11449                                bp->link_params.req_flow_ctrl[idx],
11450                                bp->port.advertising[idx]);
11451         }
11452 }
11453
11454 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11455 {
11456         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11457         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11458         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11459         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11460 }
11461
11462 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11463 {
11464         int port = BP_PORT(bp);
11465         u32 config;
11466         u32 ext_phy_type, ext_phy_config, eee_mode;
11467
11468         bp->link_params.bp = bp;
11469         bp->link_params.port = port;
11470
11471         bp->link_params.lane_config =
11472                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11473
11474         bp->link_params.speed_cap_mask[0] =
11475                 SHMEM_RD(bp,
11476                          dev_info.port_hw_config[port].speed_capability_mask) &
11477                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11478         bp->link_params.speed_cap_mask[1] =
11479                 SHMEM_RD(bp,
11480                          dev_info.port_hw_config[port].speed_capability_mask2) &
11481                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11482         bp->port.link_config[0] =
11483                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11484
11485         bp->port.link_config[1] =
11486                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11487
11488         bp->link_params.multi_phy_config =
11489                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11490         /* If the device is capable of WoL, set the default state according
11491          * to the HW
11492          */
11493         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11494         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11495                    (config & PORT_FEATURE_WOL_ENABLED));
11496
11497         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11498             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11499                 bp->flags |= NO_ISCSI_FLAG;
11500         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11501             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11502                 bp->flags |= NO_FCOE_FLAG;
11503
11504         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11505                        bp->link_params.lane_config,
11506                        bp->link_params.speed_cap_mask[0],
11507                        bp->port.link_config[0]);
11508
11509         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11510                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11511         bnx2x_phy_probe(&bp->link_params);
11512         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11513
11514         bnx2x_link_settings_requested(bp);
11515
11516         /*
11517          * If connected directly, work with the internal PHY, otherwise, work
11518          * with the external PHY
11519          */
11520         ext_phy_config =
11521                 SHMEM_RD(bp,
11522                          dev_info.port_hw_config[port].external_phy_config);
11523         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11524         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11525                 bp->mdio.prtad = bp->port.phy_addr;
11526
11527         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11528                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11529                 bp->mdio.prtad =
11530                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11531
11532         /* Configure link feature according to nvram value */
11533         eee_mode = (((SHMEM_RD(bp, dev_info.
11534                       port_feature_config[port].eee_power_mode)) &
11535                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11536                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11537         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11538                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11539                                            EEE_MODE_ENABLE_LPI |
11540                                            EEE_MODE_OUTPUT_TIME;
11541         } else {
11542                 bp->link_params.eee_mode = 0;
11543         }
11544 }
11545
11546 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11547 {
11548         u32 no_flags = NO_ISCSI_FLAG;
11549         int port = BP_PORT(bp);
11550         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11551                                 drv_lic_key[port].max_iscsi_conn);
11552
11553         if (!CNIC_SUPPORT(bp)) {
11554                 bp->flags |= no_flags;
11555                 return;
11556         }
11557
11558         /* Get the number of maximum allowed iSCSI connections */
11559         bp->cnic_eth_dev.max_iscsi_conn =
11560                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11561                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11562
11563         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11564                        bp->cnic_eth_dev.max_iscsi_conn);
11565
11566         /*
11567          * If maximum allowed number of connections is zero -
11568          * disable the feature.
11569          */
11570         if (!bp->cnic_eth_dev.max_iscsi_conn)
11571                 bp->flags |= no_flags;
11572 }
11573
11574 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11575 {
11576         /* Port info */
11577         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11578                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11579         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11580                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11581
11582         /* Node info */
11583         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11584                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11585         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11586                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11587 }
11588
11589 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11590 {
11591         u8 count = 0;
11592
11593         if (IS_MF(bp)) {
11594                 u8 fid;
11595
11596                 /* iterate over absolute function ids for this path: */
11597                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11598                         if (IS_MF_SD(bp)) {
11599                                 u32 cfg = MF_CFG_RD(bp,
11600                                                     func_mf_config[fid].config);
11601
11602                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11603                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11604                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11605                                         count++;
11606                         } else {
11607                                 u32 cfg = MF_CFG_RD(bp,
11608                                                     func_ext_config[fid].
11609                                                                       func_cfg);
11610
11611                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11612                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11613                                         count++;
11614                         }
11615                 }
11616         } else { /* SF */
11617                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11618
11619                 for (port = 0; port < port_cnt; port++) {
11620                         u32 lic = SHMEM_RD(bp,
11621                                            drv_lic_key[port].max_fcoe_conn) ^
11622                                   FW_ENCODE_32BIT_PATTERN;
11623                         if (lic)
11624                                 count++;
11625                 }
11626         }
11627
11628         return count;
11629 }
11630
11631 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11632 {
11633         int port = BP_PORT(bp);
11634         int func = BP_ABS_FUNC(bp);
11635         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11636                                 drv_lic_key[port].max_fcoe_conn);
11637         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11638
11639         if (!CNIC_SUPPORT(bp)) {
11640                 bp->flags |= NO_FCOE_FLAG;
11641                 return;
11642         }
11643
11644         /* Get the number of maximum allowed FCoE connections */
11645         bp->cnic_eth_dev.max_fcoe_conn =
11646                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11647                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11648
11649         /* Calculate the number of maximum allowed FCoE tasks */
11650         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11651
11652         /* check if FCoE resources must be shared between different functions */
11653         if (num_fcoe_func)
11654                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11655
11656         /* Read the WWN: */
11657         if (!IS_MF(bp)) {
11658                 /* Port info */
11659                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11660                         SHMEM_RD(bp,
11661                                  dev_info.port_hw_config[port].
11662                                  fcoe_wwn_port_name_upper);
11663                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11664                         SHMEM_RD(bp,
11665                                  dev_info.port_hw_config[port].
11666                                  fcoe_wwn_port_name_lower);
11667
11668                 /* Node info */
11669                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11670                         SHMEM_RD(bp,
11671                                  dev_info.port_hw_config[port].
11672                                  fcoe_wwn_node_name_upper);
11673                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11674                         SHMEM_RD(bp,
11675                                  dev_info.port_hw_config[port].
11676                                  fcoe_wwn_node_name_lower);
11677         } else if (!IS_MF_SD(bp)) {
11678                 /* Read the WWN info only if the FCoE feature is enabled for
11679                  * this function.
11680                  */
11681                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11682                         bnx2x_get_ext_wwn_info(bp, func);
11683         } else {
11684                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11685                         bnx2x_get_ext_wwn_info(bp, func);
11686         }
11687
11688         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11689
11690         /*
11691          * If maximum allowed number of connections is zero -
11692          * disable the feature.
11693          */
11694         if (!bp->cnic_eth_dev.max_fcoe_conn)
11695                 bp->flags |= NO_FCOE_FLAG;
11696 }
11697
11698 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11699 {
11700         /*
11701          * iSCSI may be dynamically disabled but reading
11702          * info here we will decrease memory usage by driver
11703          * if the feature is disabled for good
11704          */
11705         bnx2x_get_iscsi_info(bp);
11706         bnx2x_get_fcoe_info(bp);
11707 }
11708
11709 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11710 {
11711         u32 val, val2;
11712         int func = BP_ABS_FUNC(bp);
11713         int port = BP_PORT(bp);
11714         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11715         u8 *fip_mac = bp->fip_mac;
11716
11717         if (IS_MF(bp)) {
11718                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11719                  * FCoE MAC then the appropriate feature should be disabled.
11720                  * In non SD mode features configuration comes from struct
11721                  * func_ext_config.
11722                  */
11723                 if (!IS_MF_SD(bp)) {
11724                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11725                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11726                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11727                                                  iscsi_mac_addr_upper);
11728                                 val = MF_CFG_RD(bp, func_ext_config[func].
11729                                                 iscsi_mac_addr_lower);
11730                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11731                                 BNX2X_DEV_INFO
11732                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11733                         } else {
11734                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11735                         }
11736
11737                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11738                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11739                                                  fcoe_mac_addr_upper);
11740                                 val = MF_CFG_RD(bp, func_ext_config[func].
11741                                                 fcoe_mac_addr_lower);
11742                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11743                                 BNX2X_DEV_INFO
11744                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11745                         } else {
11746                                 bp->flags |= NO_FCOE_FLAG;
11747                         }
11748
11749                         bp->mf_ext_config = cfg;
11750
11751                 } else { /* SD MODE */
11752                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11753                                 /* use primary mac as iscsi mac */
11754                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11755
11756                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11757                                 BNX2X_DEV_INFO
11758                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11759                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11760                                 /* use primary mac as fip mac */
11761                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11762                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11763                                 BNX2X_DEV_INFO
11764                                         ("Read FIP MAC: %pM\n", fip_mac);
11765                         }
11766                 }
11767
11768                 /* If this is a storage-only interface, use SAN mac as
11769                  * primary MAC. Notice that for SD this is already the case,
11770                  * as the SAN mac was copied from the primary MAC.
11771                  */
11772                 if (IS_MF_FCOE_AFEX(bp))
11773                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11774         } else {
11775                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11776                                 iscsi_mac_upper);
11777                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11778                                iscsi_mac_lower);
11779                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11780
11781                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11782                                 fcoe_fip_mac_upper);
11783                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11784                                fcoe_fip_mac_lower);
11785                 bnx2x_set_mac_buf(fip_mac, val, val2);
11786         }
11787
11788         /* Disable iSCSI OOO if MAC configuration is invalid. */
11789         if (!is_valid_ether_addr(iscsi_mac)) {
11790                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11791                 eth_zero_addr(iscsi_mac);
11792         }
11793
11794         /* Disable FCoE if MAC configuration is invalid. */
11795         if (!is_valid_ether_addr(fip_mac)) {
11796                 bp->flags |= NO_FCOE_FLAG;
11797                 eth_zero_addr(bp->fip_mac);
11798         }
11799 }
11800
11801 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11802 {
11803         u32 val, val2;
11804         int func = BP_ABS_FUNC(bp);
11805         int port = BP_PORT(bp);
11806
11807         /* Zero primary MAC configuration */
11808         eth_zero_addr(bp->dev->dev_addr);
11809
11810         if (BP_NOMCP(bp)) {
11811                 BNX2X_ERROR("warning: random MAC workaround active\n");
11812                 eth_hw_addr_random(bp->dev);
11813         } else if (IS_MF(bp)) {
11814                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11815                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11816                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11817                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11818                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11819
11820                 if (CNIC_SUPPORT(bp))
11821                         bnx2x_get_cnic_mac_hwinfo(bp);
11822         } else {
11823                 /* in SF read MACs from port configuration */
11824                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11825                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11826                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11827
11828                 if (CNIC_SUPPORT(bp))
11829                         bnx2x_get_cnic_mac_hwinfo(bp);
11830         }
11831
11832         if (!BP_NOMCP(bp)) {
11833                 /* Read physical port identifier from shmem */
11834                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11835                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11836                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11837                 bp->flags |= HAS_PHYS_PORT_ID;
11838         }
11839
11840         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11841
11842         if (!is_valid_ether_addr(bp->dev->dev_addr))
11843                 dev_err(&bp->pdev->dev,
11844                         "bad Ethernet MAC address configuration: %pM\n"
11845                         "change it manually before bringing up the appropriate network interface\n",
11846                         bp->dev->dev_addr);
11847 }
11848
11849 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11850 {
11851         int tmp;
11852         u32 cfg;
11853
11854         if (IS_VF(bp))
11855                 return false;
11856
11857         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11858                 /* Take function: tmp = func */
11859                 tmp = BP_ABS_FUNC(bp);
11860                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11861                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11862         } else {
11863                 /* Take port: tmp = port */
11864                 tmp = BP_PORT(bp);
11865                 cfg = SHMEM_RD(bp,
11866                                dev_info.port_hw_config[tmp].generic_features);
11867                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11868         }
11869         return cfg;
11870 }
11871
11872 static void validate_set_si_mode(struct bnx2x *bp)
11873 {
11874         u8 func = BP_ABS_FUNC(bp);
11875         u32 val;
11876
11877         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11878
11879         /* check for legal mac (upper bytes) */
11880         if (val != 0xffff) {
11881                 bp->mf_mode = MULTI_FUNCTION_SI;
11882                 bp->mf_config[BP_VN(bp)] =
11883                         MF_CFG_RD(bp, func_mf_config[func].config);
11884         } else
11885                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11886 }
11887
11888 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11889 {
11890         int /*abs*/func = BP_ABS_FUNC(bp);
11891         int vn, mfw_vn;
11892         u32 val = 0, val2 = 0;
11893         int rc = 0;
11894
11895         /* Validate that chip access is feasible */
11896         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11897                 dev_err(&bp->pdev->dev,
11898                         "Chip read returns all Fs. Preventing probe from continuing\n");
11899                 return -EINVAL;
11900         }
11901
11902         bnx2x_get_common_hwinfo(bp);
11903
11904         /*
11905          * initialize IGU parameters
11906          */
11907         if (CHIP_IS_E1x(bp)) {
11908                 bp->common.int_block = INT_BLOCK_HC;
11909
11910                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11911                 bp->igu_base_sb = 0;
11912         } else {
11913                 bp->common.int_block = INT_BLOCK_IGU;
11914
11915                 /* do not allow device reset during IGU info processing */
11916                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11917
11918                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11919
11920                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11921                         int tout = 5000;
11922
11923                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11924
11925                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11926                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11927                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11928
11929                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11930                                 tout--;
11931                                 usleep_range(1000, 2000);
11932                         }
11933
11934                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11935                                 dev_err(&bp->pdev->dev,
11936                                         "FORCING Normal Mode failed!!!\n");
11937                                 bnx2x_release_hw_lock(bp,
11938                                                       HW_LOCK_RESOURCE_RESET);
11939                                 return -EPERM;
11940                         }
11941                 }
11942
11943                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11944                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11945                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11946                 } else
11947                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11948
11949                 rc = bnx2x_get_igu_cam_info(bp);
11950                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11951                 if (rc)
11952                         return rc;
11953         }
11954
11955         /*
11956          * set base FW non-default (fast path) status block id, this value is
11957          * used to initialize the fw_sb_id saved on the fp/queue structure to
11958          * determine the id used by the FW.
11959          */
11960         if (CHIP_IS_E1x(bp))
11961                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11962         else /*
11963               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11964               * the same queue are indicated on the same IGU SB). So we prefer
11965               * FW and IGU SBs to be the same value.
11966               */
11967                 bp->base_fw_ndsb = bp->igu_base_sb;
11968
11969         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11970                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11971                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11972
11973         /*
11974          * Initialize MF configuration
11975          */
11976
11977         bp->mf_ov = 0;
11978         bp->mf_mode = 0;
11979         bp->mf_sub_mode = 0;
11980         vn = BP_VN(bp);
11981         mfw_vn = BP_FW_MB_IDX(bp);
11982
11983         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11984                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11985                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11986                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11987
11988                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11989                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11990                 else
11991                         bp->common.mf_cfg_base = bp->common.shmem_base +
11992                                 offsetof(struct shmem_region, func_mb) +
11993                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11994                 /*
11995                  * get mf configuration:
11996                  * 1. Existence of MF configuration
11997                  * 2. MAC address must be legal (check only upper bytes)
11998                  *    for  Switch-Independent mode;
11999                  *    OVLAN must be legal for Switch-Dependent mode
12000                  * 3. SF_MODE configures specific MF mode
12001                  */
12002                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12003                         /* get mf configuration */
12004                         val = SHMEM_RD(bp,
12005                                        dev_info.shared_feature_config.config);
12006                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12007
12008                         switch (val) {
12009                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
12010                                 validate_set_si_mode(bp);
12011                                 break;
12012                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12013                                 if ((!CHIP_IS_E1x(bp)) &&
12014                                     (MF_CFG_RD(bp, func_mf_config[func].
12015                                                mac_upper) != 0xffff) &&
12016                                     (SHMEM2_HAS(bp,
12017                                                 afex_driver_support))) {
12018                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
12019                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12020                                                 func_mf_config[func].config);
12021                                 } else {
12022                                         BNX2X_DEV_INFO("can not configure afex mode\n");
12023                                 }
12024                                 break;
12025                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12026                                 /* get OV configuration */
12027                                 val = MF_CFG_RD(bp,
12028                                         func_mf_config[FUNC_0].e1hov_tag);
12029                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12030
12031                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12032                                         bp->mf_mode = MULTI_FUNCTION_SD;
12033                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12034                                                 func_mf_config[func].config);
12035                                 } else
12036                                         BNX2X_DEV_INFO("illegal OV for SD\n");
12037                                 break;
12038                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12039                                 bp->mf_mode = MULTI_FUNCTION_SD;
12040                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
12041                                 bp->mf_config[vn] =
12042                                         MF_CFG_RD(bp,
12043                                                   func_mf_config[func].config);
12044
12045                                 if (SHMEM2_HAS(bp, mtu_size)) {
12046                                         int mtu_idx = BP_FW_MB_IDX(bp);
12047                                         u16 mtu_size;
12048                                         u32 mtu;
12049
12050                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12051                                         mtu_size = (u16)mtu;
12052                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12053                                            mtu_size, mtu);
12054
12055                                         /* if valid: update device mtu */
12056                                         if (((mtu_size + ETH_HLEN) >=
12057                                              ETH_MIN_PACKET_SIZE) &&
12058                                             (mtu_size <=
12059                                              ETH_MAX_JUMBO_PACKET_SIZE))
12060                                                 bp->dev->mtu = mtu_size;
12061                                 }
12062                                 break;
12063                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12064                                 bp->mf_mode = MULTI_FUNCTION_SD;
12065                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12066                                 bp->mf_config[vn] =
12067                                         MF_CFG_RD(bp,
12068                                                   func_mf_config[func].config);
12069                                 break;
12070                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12071                                 bp->mf_config[vn] = 0;
12072                                 break;
12073                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12074                                 val2 = SHMEM_RD(bp,
12075                                         dev_info.shared_hw_config.config_3);
12076                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12077                                 switch (val2) {
12078                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12079                                         validate_set_si_mode(bp);
12080                                         bp->mf_sub_mode =
12081                                                         SUB_MF_MODE_NPAR1_DOT_5;
12082                                         break;
12083                                 default:
12084                                         /* Unknown configuration */
12085                                         bp->mf_config[vn] = 0;
12086                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12087                                                        val);
12088                                 }
12089                                 break;
12090                         default:
12091                                 /* Unknown configuration: reset mf_config */
12092                                 bp->mf_config[vn] = 0;
12093                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12094                         }
12095                 }
12096
12097                 BNX2X_DEV_INFO("%s function mode\n",
12098                                IS_MF(bp) ? "multi" : "single");
12099
12100                 switch (bp->mf_mode) {
12101                 case MULTI_FUNCTION_SD:
12102                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12103                               FUNC_MF_CFG_E1HOV_TAG_MASK;
12104                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12105                                 bp->mf_ov = val;
12106                                 bp->path_has_ovlan = true;
12107
12108                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12109                                                func, bp->mf_ov, bp->mf_ov);
12110                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12111                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12112                                 dev_err(&bp->pdev->dev,
12113                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12114                                         func);
12115                                 bp->path_has_ovlan = true;
12116                         } else {
12117                                 dev_err(&bp->pdev->dev,
12118                                         "No valid MF OV for func %d, aborting\n",
12119                                         func);
12120                                 return -EPERM;
12121                         }
12122                         break;
12123                 case MULTI_FUNCTION_AFEX:
12124                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12125                         break;
12126                 case MULTI_FUNCTION_SI:
12127                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12128                                        func);
12129                         break;
12130                 default:
12131                         if (vn) {
12132                                 dev_err(&bp->pdev->dev,
12133                                         "VN %d is in a single function mode, aborting\n",
12134                                         vn);
12135                                 return -EPERM;
12136                         }
12137                         break;
12138                 }
12139
12140                 /* check if other port on the path needs ovlan:
12141                  * Since MF configuration is shared between ports
12142                  * Possible mixed modes are only
12143                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12144                  */
12145                 if (CHIP_MODE_IS_4_PORT(bp) &&
12146                     !bp->path_has_ovlan &&
12147                     !IS_MF(bp) &&
12148                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12149                         u8 other_port = !BP_PORT(bp);
12150                         u8 other_func = BP_PATH(bp) + 2*other_port;
12151                         val = MF_CFG_RD(bp,
12152                                         func_mf_config[other_func].e1hov_tag);
12153                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12154                                 bp->path_has_ovlan = true;
12155                 }
12156         }
12157
12158         /* adjust igu_sb_cnt to MF for E1H */
12159         if (CHIP_IS_E1H(bp) && IS_MF(bp))
12160                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12161
12162         /* port info */
12163         bnx2x_get_port_hwinfo(bp);
12164
12165         /* Get MAC addresses */
12166         bnx2x_get_mac_hwinfo(bp);
12167
12168         bnx2x_get_cnic_info(bp);
12169
12170         return rc;
12171 }
12172
12173 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12174 {
12175         int cnt, i, block_end, rodi;
12176         char vpd_start[BNX2X_VPD_LEN+1];
12177         char str_id_reg[VENDOR_ID_LEN+1];
12178         char str_id_cap[VENDOR_ID_LEN+1];
12179         char *vpd_data;
12180         char *vpd_extended_data = NULL;
12181         u8 len;
12182
12183         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12184         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12185
12186         if (cnt < BNX2X_VPD_LEN)
12187                 goto out_not_found;
12188
12189         /* VPD RO tag should be first tag after identifier string, hence
12190          * we should be able to find it in first BNX2X_VPD_LEN chars
12191          */
12192         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12193                              PCI_VPD_LRDT_RO_DATA);
12194         if (i < 0)
12195                 goto out_not_found;
12196
12197         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12198                     pci_vpd_lrdt_size(&vpd_start[i]);
12199
12200         i += PCI_VPD_LRDT_TAG_SIZE;
12201
12202         if (block_end > BNX2X_VPD_LEN) {
12203                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12204                 if (vpd_extended_data  == NULL)
12205                         goto out_not_found;
12206
12207                 /* read rest of vpd image into vpd_extended_data */
12208                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12209                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12210                                    block_end - BNX2X_VPD_LEN,
12211                                    vpd_extended_data + BNX2X_VPD_LEN);
12212                 if (cnt < (block_end - BNX2X_VPD_LEN))
12213                         goto out_not_found;
12214                 vpd_data = vpd_extended_data;
12215         } else
12216                 vpd_data = vpd_start;
12217
12218         /* now vpd_data holds full vpd content in both cases */
12219
12220         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12221                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12222         if (rodi < 0)
12223                 goto out_not_found;
12224
12225         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12226
12227         if (len != VENDOR_ID_LEN)
12228                 goto out_not_found;
12229
12230         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12231
12232         /* vendor specific info */
12233         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12234         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12235         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12236             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12237
12238                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12239                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12240                 if (rodi >= 0) {
12241                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12242
12243                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12244
12245                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12246                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12247                                 bp->fw_ver[len] = ' ';
12248                         }
12249                 }
12250                 kfree(vpd_extended_data);
12251                 return;
12252         }
12253 out_not_found:
12254         kfree(vpd_extended_data);
12255         return;
12256 }
12257
12258 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12259 {
12260         u32 flags = 0;
12261
12262         if (CHIP_REV_IS_FPGA(bp))
12263                 SET_FLAGS(flags, MODE_FPGA);
12264         else if (CHIP_REV_IS_EMUL(bp))
12265                 SET_FLAGS(flags, MODE_EMUL);
12266         else
12267                 SET_FLAGS(flags, MODE_ASIC);
12268
12269         if (CHIP_MODE_IS_4_PORT(bp))
12270                 SET_FLAGS(flags, MODE_PORT4);
12271         else
12272                 SET_FLAGS(flags, MODE_PORT2);
12273
12274         if (CHIP_IS_E2(bp))
12275                 SET_FLAGS(flags, MODE_E2);
12276         else if (CHIP_IS_E3(bp)) {
12277                 SET_FLAGS(flags, MODE_E3);
12278                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12279                         SET_FLAGS(flags, MODE_E3_A0);
12280                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12281                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12282         }
12283
12284         if (IS_MF(bp)) {
12285                 SET_FLAGS(flags, MODE_MF);
12286                 switch (bp->mf_mode) {
12287                 case MULTI_FUNCTION_SD:
12288                         SET_FLAGS(flags, MODE_MF_SD);
12289                         break;
12290                 case MULTI_FUNCTION_SI:
12291                         SET_FLAGS(flags, MODE_MF_SI);
12292                         break;
12293                 case MULTI_FUNCTION_AFEX:
12294                         SET_FLAGS(flags, MODE_MF_AFEX);
12295                         break;
12296                 }
12297         } else
12298                 SET_FLAGS(flags, MODE_SF);
12299
12300 #if defined(__LITTLE_ENDIAN)
12301         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12302 #else /*(__BIG_ENDIAN)*/
12303         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12304 #endif
12305         INIT_MODE_FLAGS(bp) = flags;
12306 }
12307
12308 static int bnx2x_init_bp(struct bnx2x *bp)
12309 {
12310         int func;
12311         int rc;
12312
12313         mutex_init(&bp->port.phy_mutex);
12314         mutex_init(&bp->fw_mb_mutex);
12315         mutex_init(&bp->drv_info_mutex);
12316         sema_init(&bp->stats_lock, 1);
12317         bp->drv_info_mng_owner = false;
12318         INIT_LIST_HEAD(&bp->vlan_reg);
12319
12320         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12321         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12322         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12323         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12324         if (IS_PF(bp)) {
12325                 rc = bnx2x_get_hwinfo(bp);
12326                 if (rc)
12327                         return rc;
12328         } else {
12329                 eth_zero_addr(bp->dev->dev_addr);
12330         }
12331
12332         bnx2x_set_modes_bitmap(bp);
12333
12334         rc = bnx2x_alloc_mem_bp(bp);
12335         if (rc)
12336                 return rc;
12337
12338         bnx2x_read_fwinfo(bp);
12339
12340         func = BP_FUNC(bp);
12341
12342         /* need to reset chip if undi was active */
12343         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12344                 /* init fw_seq */
12345                 bp->fw_seq =
12346                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12347                                                         DRV_MSG_SEQ_NUMBER_MASK;
12348                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12349
12350                 rc = bnx2x_prev_unload(bp);
12351                 if (rc) {
12352                         bnx2x_free_mem_bp(bp);
12353                         return rc;
12354                 }
12355         }
12356
12357         if (CHIP_REV_IS_FPGA(bp))
12358                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12359
12360         if (BP_NOMCP(bp) && (func == 0))
12361                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12362
12363         bp->disable_tpa = disable_tpa;
12364         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12365         /* Reduce memory usage in kdump environment by disabling TPA */
12366         bp->disable_tpa |= is_kdump_kernel();
12367
12368         /* Set TPA flags */
12369         if (bp->disable_tpa) {
12370                 bp->dev->hw_features &= ~NETIF_F_LRO;
12371                 bp->dev->features &= ~NETIF_F_LRO;
12372         }
12373
12374         if (CHIP_IS_E1(bp))
12375                 bp->dropless_fc = 0;
12376         else
12377                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12378
12379         bp->mrrs = mrrs;
12380
12381         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12382         if (IS_VF(bp))
12383                 bp->rx_ring_size = MAX_RX_AVAIL;
12384
12385         /* make sure that the numbers are in the right granularity */
12386         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12387         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12388
12389         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12390
12391         init_timer(&bp->timer);
12392         bp->timer.expires = jiffies + bp->current_interval;
12393         bp->timer.data = (unsigned long) bp;
12394         bp->timer.function = bnx2x_timer;
12395
12396         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12397             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12398             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12399             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12400                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12401                 bnx2x_dcbx_init_params(bp);
12402         } else {
12403                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12404         }
12405
12406         if (CHIP_IS_E1x(bp))
12407                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12408         else
12409                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12410
12411         /* multiple tx priority */
12412         if (IS_VF(bp))
12413                 bp->max_cos = 1;
12414         else if (CHIP_IS_E1x(bp))
12415                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12416         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12417                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12418         else if (CHIP_IS_E3B0(bp))
12419                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12420         else
12421                 BNX2X_ERR("unknown chip %x revision %x\n",
12422                           CHIP_NUM(bp), CHIP_REV(bp));
12423         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12424
12425         /* We need at least one default status block for slow-path events,
12426          * second status block for the L2 queue, and a third status block for
12427          * CNIC if supported.
12428          */
12429         if (IS_VF(bp))
12430                 bp->min_msix_vec_cnt = 1;
12431         else if (CNIC_SUPPORT(bp))
12432                 bp->min_msix_vec_cnt = 3;
12433         else /* PF w/o cnic */
12434                 bp->min_msix_vec_cnt = 2;
12435         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12436
12437         bp->dump_preset_idx = 1;
12438
12439         if (CHIP_IS_E3B0(bp))
12440                 bp->flags |= PTP_SUPPORTED;
12441
12442         return rc;
12443 }
12444
12445 /****************************************************************************
12446 * General service functions
12447 ****************************************************************************/
12448
12449 /*
12450  * net_device service functions
12451  */
12452
12453 /* called with rtnl_lock */
12454 static int bnx2x_open(struct net_device *dev)
12455 {
12456         struct bnx2x *bp = netdev_priv(dev);
12457         int rc;
12458
12459         bp->stats_init = true;
12460
12461         netif_carrier_off(dev);
12462
12463         bnx2x_set_power_state(bp, PCI_D0);
12464
12465         /* If parity had happen during the unload, then attentions
12466          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12467          * want the first function loaded on the current engine to
12468          * complete the recovery.
12469          * Parity recovery is only relevant for PF driver.
12470          */
12471         if (IS_PF(bp)) {
12472                 int other_engine = BP_PATH(bp) ? 0 : 1;
12473                 bool other_load_status, load_status;
12474                 bool global = false;
12475
12476                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12477                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12478                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12479                     bnx2x_chk_parity_attn(bp, &global, true)) {
12480                         do {
12481                                 /* If there are attentions and they are in a
12482                                  * global blocks, set the GLOBAL_RESET bit
12483                                  * regardless whether it will be this function
12484                                  * that will complete the recovery or not.
12485                                  */
12486                                 if (global)
12487                                         bnx2x_set_reset_global(bp);
12488
12489                                 /* Only the first function on the current
12490                                  * engine should try to recover in open. In case
12491                                  * of attentions in global blocks only the first
12492                                  * in the chip should try to recover.
12493                                  */
12494                                 if ((!load_status &&
12495                                      (!global || !other_load_status)) &&
12496                                       bnx2x_trylock_leader_lock(bp) &&
12497                                       !bnx2x_leader_reset(bp)) {
12498                                         netdev_info(bp->dev,
12499                                                     "Recovered in open\n");
12500                                         break;
12501                                 }
12502
12503                                 /* recovery has failed... */
12504                                 bnx2x_set_power_state(bp, PCI_D3hot);
12505                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12506
12507                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12508                                           "If you still see this message after a few retries then power cycle is required.\n");
12509
12510                                 return -EAGAIN;
12511                         } while (0);
12512                 }
12513         }
12514
12515         bp->recovery_state = BNX2X_RECOVERY_DONE;
12516         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12517         if (rc)
12518                 return rc;
12519
12520 #ifdef CONFIG_BNX2X_VXLAN
12521         if (IS_PF(bp))
12522                 vxlan_get_rx_port(dev);
12523 #endif
12524
12525         return 0;
12526 }
12527
12528 /* called with rtnl_lock */
12529 static int bnx2x_close(struct net_device *dev)
12530 {
12531         struct bnx2x *bp = netdev_priv(dev);
12532
12533         /* Unload the driver, release IRQs */
12534         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12535
12536         return 0;
12537 }
12538
12539 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12540                                       struct bnx2x_mcast_ramrod_params *p)
12541 {
12542         int mc_count = netdev_mc_count(bp->dev);
12543         struct bnx2x_mcast_list_elem *mc_mac =
12544                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12545         struct netdev_hw_addr *ha;
12546
12547         if (!mc_mac)
12548                 return -ENOMEM;
12549
12550         INIT_LIST_HEAD(&p->mcast_list);
12551
12552         netdev_for_each_mc_addr(ha, bp->dev) {
12553                 mc_mac->mac = bnx2x_mc_addr(ha);
12554                 list_add_tail(&mc_mac->link, &p->mcast_list);
12555                 mc_mac++;
12556         }
12557
12558         p->mcast_list_len = mc_count;
12559
12560         return 0;
12561 }
12562
12563 static void bnx2x_free_mcast_macs_list(
12564         struct bnx2x_mcast_ramrod_params *p)
12565 {
12566         struct bnx2x_mcast_list_elem *mc_mac =
12567                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12568                                  link);
12569
12570         WARN_ON(!mc_mac);
12571         kfree(mc_mac);
12572 }
12573
12574 /**
12575  * bnx2x_set_uc_list - configure a new unicast MACs list.
12576  *
12577  * @bp: driver handle
12578  *
12579  * We will use zero (0) as a MAC type for these MACs.
12580  */
12581 static int bnx2x_set_uc_list(struct bnx2x *bp)
12582 {
12583         int rc;
12584         struct net_device *dev = bp->dev;
12585         struct netdev_hw_addr *ha;
12586         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12587         unsigned long ramrod_flags = 0;
12588
12589         /* First schedule a cleanup up of old configuration */
12590         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12591         if (rc < 0) {
12592                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12593                 return rc;
12594         }
12595
12596         netdev_for_each_uc_addr(ha, dev) {
12597                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12598                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12599                 if (rc == -EEXIST) {
12600                         DP(BNX2X_MSG_SP,
12601                            "Failed to schedule ADD operations: %d\n", rc);
12602                         /* do not treat adding same MAC as error */
12603                         rc = 0;
12604
12605                 } else if (rc < 0) {
12606
12607                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12608                                   rc);
12609                         return rc;
12610                 }
12611         }
12612
12613         /* Execute the pending commands */
12614         __set_bit(RAMROD_CONT, &ramrod_flags);
12615         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12616                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12617 }
12618
12619 static int bnx2x_set_mc_list(struct bnx2x *bp)
12620 {
12621         struct net_device *dev = bp->dev;
12622         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12623         int rc = 0;
12624
12625         rparam.mcast_obj = &bp->mcast_obj;
12626
12627         /* first, clear all configured multicast MACs */
12628         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12629         if (rc < 0) {
12630                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12631                 return rc;
12632         }
12633
12634         /* then, configure a new MACs list */
12635         if (netdev_mc_count(dev)) {
12636                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12637                 if (rc) {
12638                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12639                                   rc);
12640                         return rc;
12641                 }
12642
12643                 /* Now add the new MACs */
12644                 rc = bnx2x_config_mcast(bp, &rparam,
12645                                         BNX2X_MCAST_CMD_ADD);
12646                 if (rc < 0)
12647                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12648                                   rc);
12649
12650                 bnx2x_free_mcast_macs_list(&rparam);
12651         }
12652
12653         return rc;
12654 }
12655
12656 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12657 static void bnx2x_set_rx_mode(struct net_device *dev)
12658 {
12659         struct bnx2x *bp = netdev_priv(dev);
12660
12661         if (bp->state != BNX2X_STATE_OPEN) {
12662                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12663                 return;
12664         } else {
12665                 /* Schedule an SP task to handle rest of change */
12666                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12667                                        NETIF_MSG_IFUP);
12668         }
12669 }
12670
12671 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12672 {
12673         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12674
12675         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12676
12677         netif_addr_lock_bh(bp->dev);
12678
12679         if (bp->dev->flags & IFF_PROMISC) {
12680                 rx_mode = BNX2X_RX_MODE_PROMISC;
12681         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12682                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12683                     CHIP_IS_E1(bp))) {
12684                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12685         } else {
12686                 if (IS_PF(bp)) {
12687                         /* some multicasts */
12688                         if (bnx2x_set_mc_list(bp) < 0)
12689                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12690
12691                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12692                         netif_addr_unlock_bh(bp->dev);
12693                         if (bnx2x_set_uc_list(bp) < 0)
12694                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12695                         netif_addr_lock_bh(bp->dev);
12696                 } else {
12697                         /* configuring mcast to a vf involves sleeping (when we
12698                          * wait for the pf's response).
12699                          */
12700                         bnx2x_schedule_sp_rtnl(bp,
12701                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12702                 }
12703         }
12704
12705         bp->rx_mode = rx_mode;
12706         /* handle ISCSI SD mode */
12707         if (IS_MF_ISCSI_ONLY(bp))
12708                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12709
12710         /* Schedule the rx_mode command */
12711         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12712                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12713                 netif_addr_unlock_bh(bp->dev);
12714                 return;
12715         }
12716
12717         if (IS_PF(bp)) {
12718                 bnx2x_set_storm_rx_mode(bp);
12719                 netif_addr_unlock_bh(bp->dev);
12720         } else {
12721                 /* VF will need to request the PF to make this change, and so
12722                  * the VF needs to release the bottom-half lock prior to the
12723                  * request (as it will likely require sleep on the VF side)
12724                  */
12725                 netif_addr_unlock_bh(bp->dev);
12726                 bnx2x_vfpf_storm_rx_mode(bp);
12727         }
12728 }
12729
12730 /* called with rtnl_lock */
12731 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12732                            int devad, u16 addr)
12733 {
12734         struct bnx2x *bp = netdev_priv(netdev);
12735         u16 value;
12736         int rc;
12737
12738         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12739            prtad, devad, addr);
12740
12741         /* The HW expects different devad if CL22 is used */
12742         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12743
12744         bnx2x_acquire_phy_lock(bp);
12745         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12746         bnx2x_release_phy_lock(bp);
12747         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12748
12749         if (!rc)
12750                 rc = value;
12751         return rc;
12752 }
12753
12754 /* called with rtnl_lock */
12755 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12756                             u16 addr, u16 value)
12757 {
12758         struct bnx2x *bp = netdev_priv(netdev);
12759         int rc;
12760
12761         DP(NETIF_MSG_LINK,
12762            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12763            prtad, devad, addr, value);
12764
12765         /* The HW expects different devad if CL22 is used */
12766         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12767
12768         bnx2x_acquire_phy_lock(bp);
12769         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12770         bnx2x_release_phy_lock(bp);
12771         return rc;
12772 }
12773
12774 /* called with rtnl_lock */
12775 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12776 {
12777         struct bnx2x *bp = netdev_priv(dev);
12778         struct mii_ioctl_data *mdio = if_mii(ifr);
12779
12780         if (!netif_running(dev))
12781                 return -EAGAIN;
12782
12783         switch (cmd) {
12784         case SIOCSHWTSTAMP:
12785                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12786         default:
12787                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12788                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12789                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12790         }
12791 }
12792
12793 #ifdef CONFIG_NET_POLL_CONTROLLER
12794 static void poll_bnx2x(struct net_device *dev)
12795 {
12796         struct bnx2x *bp = netdev_priv(dev);
12797         int i;
12798
12799         for_each_eth_queue(bp, i) {
12800                 struct bnx2x_fastpath *fp = &bp->fp[i];
12801                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12802         }
12803 }
12804 #endif
12805
12806 static int bnx2x_validate_addr(struct net_device *dev)
12807 {
12808         struct bnx2x *bp = netdev_priv(dev);
12809
12810         /* query the bulletin board for mac address configured by the PF */
12811         if (IS_VF(bp))
12812                 bnx2x_sample_bulletin(bp);
12813
12814         if (!is_valid_ether_addr(dev->dev_addr)) {
12815                 BNX2X_ERR("Non-valid Ethernet address\n");
12816                 return -EADDRNOTAVAIL;
12817         }
12818         return 0;
12819 }
12820
12821 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12822                                   struct netdev_phys_item_id *ppid)
12823 {
12824         struct bnx2x *bp = netdev_priv(netdev);
12825
12826         if (!(bp->flags & HAS_PHYS_PORT_ID))
12827                 return -EOPNOTSUPP;
12828
12829         ppid->id_len = sizeof(bp->phys_port_id);
12830         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12831
12832         return 0;
12833 }
12834
12835 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12836                                               struct net_device *dev,
12837                                               netdev_features_t features)
12838 {
12839         /*
12840          * A skb with gso_size + header length > 9700 will cause a
12841          * firmware panic. Drop GSO support.
12842          *
12843          * Eventually the upper layer should not pass these packets down.
12844          *
12845          * For speed, if the gso_size is <= 9000, assume there will
12846          * not be 700 bytes of headers and pass it through. Only do a
12847          * full (slow) validation if the gso_size is > 9000.
12848          *
12849          * (Due to the way SKB_BY_FRAGS works this will also do a full
12850          * validation in that case.)
12851          */
12852         if (unlikely(skb_is_gso(skb) &&
12853                      (skb_shinfo(skb)->gso_size > 9000) &&
12854                      !skb_gso_validate_mac_len(skb, 9700)))
12855                 features &= ~NETIF_F_GSO_MASK;
12856
12857         features = vlan_features_check(skb, features);
12858         return vxlan_features_check(skb, features);
12859 }
12860
12861 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12862 {
12863         int rc;
12864
12865         if (IS_PF(bp)) {
12866                 unsigned long ramrod_flags = 0;
12867
12868                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12869                 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12870                                         add, &ramrod_flags);
12871         } else {
12872                 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12873         }
12874
12875         return rc;
12876 }
12877
12878 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12879 {
12880         struct bnx2x_vlan_entry *vlan;
12881         int rc = 0;
12882
12883         if (!bp->vlan_cnt) {
12884                 DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n");
12885                 return 0;
12886         }
12887
12888         list_for_each_entry(vlan, &bp->vlan_reg, link) {
12889                 /* Prepare for cleanup in case of errors */
12890                 if (rc) {
12891                         vlan->hw = false;
12892                         continue;
12893                 }
12894
12895                 if (!vlan->hw)
12896                         continue;
12897
12898                 DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid);
12899
12900                 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12901                 if (rc) {
12902                         BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid);
12903                         vlan->hw = false;
12904                         rc = -EINVAL;
12905                         continue;
12906                 }
12907         }
12908
12909         return rc;
12910 }
12911
12912 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12913 {
12914         struct bnx2x *bp = netdev_priv(dev);
12915         struct bnx2x_vlan_entry *vlan;
12916         bool hw = false;
12917         int rc = 0;
12918
12919         if (!netif_running(bp->dev)) {
12920                 DP(NETIF_MSG_IFUP,
12921                    "Ignoring VLAN configuration the interface is down\n");
12922                 return -EFAULT;
12923         }
12924
12925         DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12926
12927         vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12928         if (!vlan)
12929                 return -ENOMEM;
12930
12931         bp->vlan_cnt++;
12932         if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) {
12933                 DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n");
12934                 bp->accept_any_vlan = true;
12935                 if (IS_PF(bp))
12936                         bnx2x_set_rx_mode_inner(bp);
12937                 else
12938                         bnx2x_vfpf_storm_rx_mode(bp);
12939         } else if (bp->vlan_cnt <= bp->vlan_credit) {
12940                 rc = __bnx2x_vlan_configure_vid(bp, vid, true);
12941                 hw = true;
12942         }
12943
12944         vlan->vid = vid;
12945         vlan->hw = hw;
12946
12947         if (!rc) {
12948                 list_add(&vlan->link, &bp->vlan_reg);
12949         } else {
12950                 bp->vlan_cnt--;
12951                 kfree(vlan);
12952         }
12953
12954         DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc);
12955
12956         return rc;
12957 }
12958
12959 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12960 {
12961         struct bnx2x *bp = netdev_priv(dev);
12962         struct bnx2x_vlan_entry *vlan;
12963         int rc = 0;
12964
12965         if (!netif_running(bp->dev)) {
12966                 DP(NETIF_MSG_IFUP,
12967                    "Ignoring VLAN configuration the interface is down\n");
12968                 return -EFAULT;
12969         }
12970
12971         DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12972
12973         if (!bp->vlan_cnt) {
12974                 BNX2X_ERR("Unable to kill VLAN %d\n", vid);
12975                 return -EINVAL;
12976         }
12977
12978         list_for_each_entry(vlan, &bp->vlan_reg, link)
12979                 if (vlan->vid == vid)
12980                         break;
12981
12982         if (vlan->vid != vid) {
12983                 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
12984                 return -EINVAL;
12985         }
12986
12987         if (vlan->hw)
12988                 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
12989
12990         list_del(&vlan->link);
12991         kfree(vlan);
12992
12993         bp->vlan_cnt--;
12994
12995         if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) {
12996                 /* Configure all non-configured entries */
12997                 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12998                         if (vlan->hw)
12999                                 continue;
13000
13001                         rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
13002                         if (rc) {
13003                                 BNX2X_ERR("Unable to config VLAN %d\n",
13004                                           vlan->vid);
13005                                 continue;
13006                         }
13007                         DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n",
13008                            vlan->vid);
13009                         vlan->hw = true;
13010                 }
13011                 DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n");
13012                 bp->accept_any_vlan = false;
13013                 if (IS_PF(bp))
13014                         bnx2x_set_rx_mode_inner(bp);
13015                 else
13016                         bnx2x_vfpf_storm_rx_mode(bp);
13017         }
13018
13019         DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13020
13021         return rc;
13022 }
13023
13024 static const struct net_device_ops bnx2x_netdev_ops = {
13025         .ndo_open               = bnx2x_open,
13026         .ndo_stop               = bnx2x_close,
13027         .ndo_start_xmit         = bnx2x_start_xmit,
13028         .ndo_select_queue       = bnx2x_select_queue,
13029         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
13030         .ndo_set_mac_address    = bnx2x_change_mac_addr,
13031         .ndo_validate_addr      = bnx2x_validate_addr,
13032         .ndo_do_ioctl           = bnx2x_ioctl,
13033         .ndo_change_mtu         = bnx2x_change_mtu,
13034         .ndo_fix_features       = bnx2x_fix_features,
13035         .ndo_set_features       = bnx2x_set_features,
13036         .ndo_tx_timeout         = bnx2x_tx_timeout,
13037         .ndo_vlan_rx_add_vid    = bnx2x_vlan_rx_add_vid,
13038         .ndo_vlan_rx_kill_vid   = bnx2x_vlan_rx_kill_vid,
13039 #ifdef CONFIG_NET_POLL_CONTROLLER
13040         .ndo_poll_controller    = poll_bnx2x,
13041 #endif
13042         .ndo_setup_tc           = bnx2x_setup_tc,
13043 #ifdef CONFIG_BNX2X_SRIOV
13044         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
13045         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
13046         .ndo_get_vf_config      = bnx2x_get_vf_config,
13047 #endif
13048 #ifdef NETDEV_FCOE_WWNN
13049         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
13050 #endif
13051
13052 #ifdef CONFIG_NET_RX_BUSY_POLL
13053         .ndo_busy_poll          = bnx2x_low_latency_recv,
13054 #endif
13055         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
13056         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
13057         .ndo_features_check     = bnx2x_features_check,
13058 #ifdef CONFIG_BNX2X_VXLAN
13059         .ndo_add_vxlan_port     = bnx2x_add_vxlan_port,
13060         .ndo_del_vxlan_port     = bnx2x_del_vxlan_port,
13061 #endif
13062 };
13063
13064 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13065 {
13066         struct device *dev = &bp->pdev->dev;
13067
13068         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13069             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13070                 dev_err(dev, "System does not support DMA, aborting\n");
13071                 return -EIO;
13072         }
13073
13074         return 0;
13075 }
13076
13077 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13078 {
13079         if (bp->flags & AER_ENABLED) {
13080                 pci_disable_pcie_error_reporting(bp->pdev);
13081                 bp->flags &= ~AER_ENABLED;
13082         }
13083 }
13084
13085 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13086                           struct net_device *dev, unsigned long board_type)
13087 {
13088         int rc;
13089         u32 pci_cfg_dword;
13090         bool chip_is_e1x = (board_type == BCM57710 ||
13091                             board_type == BCM57711 ||
13092                             board_type == BCM57711E);
13093
13094         SET_NETDEV_DEV(dev, &pdev->dev);
13095
13096         bp->dev = dev;
13097         bp->pdev = pdev;
13098
13099         rc = pci_enable_device(pdev);
13100         if (rc) {
13101                 dev_err(&bp->pdev->dev,
13102                         "Cannot enable PCI device, aborting\n");
13103                 goto err_out;
13104         }
13105
13106         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13107                 dev_err(&bp->pdev->dev,
13108                         "Cannot find PCI device base address, aborting\n");
13109                 rc = -ENODEV;
13110                 goto err_out_disable;
13111         }
13112
13113         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13114                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13115                 rc = -ENODEV;
13116                 goto err_out_disable;
13117         }
13118
13119         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13120         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13121             PCICFG_REVESION_ID_ERROR_VAL) {
13122                 pr_err("PCI device error, probably due to fan failure, aborting\n");
13123                 rc = -ENODEV;
13124                 goto err_out_disable;
13125         }
13126
13127         if (atomic_read(&pdev->enable_cnt) == 1) {
13128                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13129                 if (rc) {
13130                         dev_err(&bp->pdev->dev,
13131                                 "Cannot obtain PCI resources, aborting\n");
13132                         goto err_out_disable;
13133                 }
13134
13135                 pci_set_master(pdev);
13136                 pci_save_state(pdev);
13137         }
13138
13139         if (IS_PF(bp)) {
13140                 if (!pdev->pm_cap) {
13141                         dev_err(&bp->pdev->dev,
13142                                 "Cannot find power management capability, aborting\n");
13143                         rc = -EIO;
13144                         goto err_out_release;
13145                 }
13146         }
13147
13148         if (!pci_is_pcie(pdev)) {
13149                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13150                 rc = -EIO;
13151                 goto err_out_release;
13152         }
13153
13154         rc = bnx2x_set_coherency_mask(bp);
13155         if (rc)
13156                 goto err_out_release;
13157
13158         dev->mem_start = pci_resource_start(pdev, 0);
13159         dev->base_addr = dev->mem_start;
13160         dev->mem_end = pci_resource_end(pdev, 0);
13161
13162         dev->irq = pdev->irq;
13163
13164         bp->regview = pci_ioremap_bar(pdev, 0);
13165         if (!bp->regview) {
13166                 dev_err(&bp->pdev->dev,
13167                         "Cannot map register space, aborting\n");
13168                 rc = -ENOMEM;
13169                 goto err_out_release;
13170         }
13171
13172         /* In E1/E1H use pci device function given by kernel.
13173          * In E2/E3 read physical function from ME register since these chips
13174          * support Physical Device Assignment where kernel BDF maybe arbitrary
13175          * (depending on hypervisor).
13176          */
13177         if (chip_is_e1x) {
13178                 bp->pf_num = PCI_FUNC(pdev->devfn);
13179         } else {
13180                 /* chip is E2/3*/
13181                 pci_read_config_dword(bp->pdev,
13182                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
13183                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13184                                   ME_REG_ABS_PF_NUM_SHIFT);
13185         }
13186         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13187
13188         /* clean indirect addresses */
13189         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13190                                PCICFG_VENDOR_ID_OFFSET);
13191
13192         /* Set PCIe reset type to fundamental for EEH recovery */
13193         pdev->needs_freset = 1;
13194
13195         /* AER (Advanced Error reporting) configuration */
13196         rc = pci_enable_pcie_error_reporting(pdev);
13197         if (!rc)
13198                 bp->flags |= AER_ENABLED;
13199         else
13200                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13201
13202         /*
13203          * Clean the following indirect addresses for all functions since it
13204          * is not used by the driver.
13205          */
13206         if (IS_PF(bp)) {
13207                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13208                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13209                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13210                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13211
13212                 if (chip_is_e1x) {
13213                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13214                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13215                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13216                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13217                 }
13218
13219                 /* Enable internal target-read (in case we are probed after PF
13220                  * FLR). Must be done prior to any BAR read access. Only for
13221                  * 57712 and up
13222                  */
13223                 if (!chip_is_e1x)
13224                         REG_WR(bp,
13225                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13226         }
13227
13228         dev->watchdog_timeo = TX_TIMEOUT;
13229
13230         dev->netdev_ops = &bnx2x_netdev_ops;
13231         bnx2x_set_ethtool_ops(bp, dev);
13232
13233         dev->priv_flags |= IFF_UNICAST_FLT;
13234
13235         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13236                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13237                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13238                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13239         if (!chip_is_e1x) {
13240                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
13241                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
13242                 dev->hw_enc_features =
13243                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13244                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13245                         NETIF_F_GSO_IPIP |
13246                         NETIF_F_GSO_SIT |
13247                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
13248         }
13249
13250         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13251                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13252
13253         /* VF with OLD Hypervisor or old PF do not support filtering */
13254         if (IS_PF(bp)) {
13255                 if (chip_is_e1x)
13256                         bp->accept_any_vlan = true;
13257                 else
13258                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13259 #ifdef CONFIG_BNX2X_SRIOV
13260         } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13261                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13262 #endif
13263         }
13264
13265         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13266         dev->features |= NETIF_F_HIGHDMA;
13267
13268         /* Add Loopback capability to the device */
13269         dev->hw_features |= NETIF_F_LOOPBACK;
13270
13271 #ifdef BCM_DCBNL
13272         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13273 #endif
13274
13275         /* get_port_hwinfo() will set prtad and mmds properly */
13276         bp->mdio.prtad = MDIO_PRTAD_NONE;
13277         bp->mdio.mmds = 0;
13278         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13279         bp->mdio.dev = dev;
13280         bp->mdio.mdio_read = bnx2x_mdio_read;
13281         bp->mdio.mdio_write = bnx2x_mdio_write;
13282
13283         return 0;
13284
13285 err_out_release:
13286         if (atomic_read(&pdev->enable_cnt) == 1)
13287                 pci_release_regions(pdev);
13288
13289 err_out_disable:
13290         pci_disable_device(pdev);
13291
13292 err_out:
13293         return rc;
13294 }
13295
13296 /*(DEBLOBBED)*/
13297
13298 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13299 {
13300         const __be32 *source = (const __be32 *)_source;
13301         u32 *target = (u32 *)_target;
13302         u32 i;
13303
13304         for (i = 0; i < n/4; i++)
13305                 target[i] = be32_to_cpu(source[i]);
13306 }
13307
13308 /*
13309    Ops array is stored in the following format:
13310    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13311  */
13312 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13313 {
13314         const __be32 *source = (const __be32 *)_source;
13315         struct raw_op *target = (struct raw_op *)_target;
13316         u32 i, j, tmp;
13317
13318         for (i = 0, j = 0; i < n/8; i++, j += 2) {
13319                 tmp = be32_to_cpu(source[j]);
13320                 target[i].op = (tmp >> 24) & 0xff;
13321                 target[i].offset = tmp & 0xffffff;
13322                 target[i].raw_data = be32_to_cpu(source[j + 1]);
13323         }
13324 }
13325
13326 /* IRO array is stored in the following format:
13327  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13328  */
13329 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13330 {
13331         const __be32 *source = (const __be32 *)_source;
13332         struct iro *target = (struct iro *)_target;
13333         u32 i, j, tmp;
13334
13335         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13336                 target[i].base = be32_to_cpu(source[j]);
13337                 j++;
13338                 tmp = be32_to_cpu(source[j]);
13339                 target[i].m1 = (tmp >> 16) & 0xffff;
13340                 target[i].m2 = tmp & 0xffff;
13341                 j++;
13342                 tmp = be32_to_cpu(source[j]);
13343                 target[i].m3 = (tmp >> 16) & 0xffff;
13344                 target[i].size = tmp & 0xffff;
13345                 j++;
13346         }
13347 }
13348
13349 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13350 {
13351         const __be16 *source = (const __be16 *)_source;
13352         u16 *target = (u16 *)_target;
13353         u32 i;
13354
13355         for (i = 0; i < n/2; i++)
13356                 target[i] = be16_to_cpu(source[i]);
13357 }
13358
13359 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13360 do {                                                                    \
13361         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13362         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13363         if (!bp->arr)                                                   \
13364                 goto lbl;                                               \
13365         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13366              (u8 *)bp->arr, len);                                       \
13367 } while (0)
13368
13369 static int bnx2x_init_firmware(struct bnx2x *bp)
13370 {
13371         const char *fw_file_name;
13372         struct bnx2x_fw_file_hdr *fw_hdr;
13373         int rc;
13374
13375         if (bp->firmware)
13376                 return 0;
13377
13378         if (CHIP_IS_E1(bp))
13379                 fw_file_name = FW_FILE_NAME_E1;
13380         else if (CHIP_IS_E1H(bp))
13381                 fw_file_name = FW_FILE_NAME_E1H;
13382         else if (!CHIP_IS_E1x(bp))
13383                 fw_file_name = FW_FILE_NAME_E2;
13384         else {
13385                 BNX2X_ERR("Unsupported chip revision\n");
13386                 return -EINVAL;
13387         }
13388         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13389
13390         rc = reject_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13391         if (rc) {
13392                 BNX2X_ERR("Can't load firmware file %s\n",
13393                           fw_file_name);
13394                 goto request_firmware_exit;
13395         }
13396
13397         /*(DEBLOBBED)*/
13398         if (rc) {
13399                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13400                 goto request_firmware_exit;
13401         }
13402
13403         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13404
13405         /* Initialize the pointers to the init arrays */
13406         /* Blob */
13407         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13408
13409         /* Opcodes */
13410         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13411
13412         /* Offsets */
13413         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13414                             be16_to_cpu_n);
13415
13416         /* STORMs firmware */
13417         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13418                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13419         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13420                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13421         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13422                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13423         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13424                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13425         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13426                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13427         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13428                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13429         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13430                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13431         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13432                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13433         /* IRO */
13434         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13435
13436         return 0;
13437
13438 iro_alloc_err:
13439         kfree(bp->init_ops_offsets);
13440 init_offsets_alloc_err:
13441         kfree(bp->init_ops);
13442 init_ops_alloc_err:
13443         kfree(bp->init_data);
13444 request_firmware_exit:
13445         release_firmware(bp->firmware);
13446         bp->firmware = NULL;
13447
13448         return rc;
13449 }
13450
13451 static void bnx2x_release_firmware(struct bnx2x *bp)
13452 {
13453         kfree(bp->init_ops_offsets);
13454         kfree(bp->init_ops);
13455         kfree(bp->init_data);
13456         release_firmware(bp->firmware);
13457         bp->firmware = NULL;
13458 }
13459
13460 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13461         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13462         .init_hw_cmn      = bnx2x_init_hw_common,
13463         .init_hw_port     = bnx2x_init_hw_port,
13464         .init_hw_func     = bnx2x_init_hw_func,
13465
13466         .reset_hw_cmn     = bnx2x_reset_common,
13467         .reset_hw_port    = bnx2x_reset_port,
13468         .reset_hw_func    = bnx2x_reset_func,
13469
13470         .gunzip_init      = bnx2x_gunzip_init,
13471         .gunzip_end       = bnx2x_gunzip_end,
13472
13473         .init_fw          = bnx2x_init_firmware,
13474         .release_fw       = bnx2x_release_firmware,
13475 };
13476
13477 void bnx2x__init_func_obj(struct bnx2x *bp)
13478 {
13479         /* Prepare DMAE related driver resources */
13480         bnx2x_setup_dmae(bp);
13481
13482         bnx2x_init_func_obj(bp, &bp->func_obj,
13483                             bnx2x_sp(bp, func_rdata),
13484                             bnx2x_sp_mapping(bp, func_rdata),
13485                             bnx2x_sp(bp, func_afex_rdata),
13486                             bnx2x_sp_mapping(bp, func_afex_rdata),
13487                             &bnx2x_func_sp_drv);
13488 }
13489
13490 /* must be called after sriov-enable */
13491 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13492 {
13493         int cid_count = BNX2X_L2_MAX_CID(bp);
13494
13495         if (IS_SRIOV(bp))
13496                 cid_count += BNX2X_VF_CIDS;
13497
13498         if (CNIC_SUPPORT(bp))
13499                 cid_count += CNIC_CID_MAX;
13500
13501         return roundup(cid_count, QM_CID_ROUND);
13502 }
13503
13504 /**
13505  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13506  *
13507  * @dev:        pci device
13508  *
13509  */
13510 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13511 {
13512         int index;
13513         u16 control = 0;
13514
13515         /*
13516          * If MSI-X is not supported - return number of SBs needed to support
13517          * one fast path queue: one FP queue + SB for CNIC
13518          */
13519         if (!pdev->msix_cap) {
13520                 dev_info(&pdev->dev, "no msix capability found\n");
13521                 return 1 + cnic_cnt;
13522         }
13523         dev_info(&pdev->dev, "msix capability found\n");
13524
13525         /*
13526          * The value in the PCI configuration space is the index of the last
13527          * entry, namely one less than the actual size of the table, which is
13528          * exactly what we want to return from this function: number of all SBs
13529          * without the default SB.
13530          * For VFs there is no default SB, then we return (index+1).
13531          */
13532         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13533
13534         index = control & PCI_MSIX_FLAGS_QSIZE;
13535
13536         return index;
13537 }
13538
13539 static int set_max_cos_est(int chip_id)
13540 {
13541         switch (chip_id) {
13542         case BCM57710:
13543         case BCM57711:
13544         case BCM57711E:
13545                 return BNX2X_MULTI_TX_COS_E1X;
13546         case BCM57712:
13547         case BCM57712_MF:
13548                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13549         case BCM57800:
13550         case BCM57800_MF:
13551         case BCM57810:
13552         case BCM57810_MF:
13553         case BCM57840_4_10:
13554         case BCM57840_2_20:
13555         case BCM57840_O:
13556         case BCM57840_MFO:
13557         case BCM57840_MF:
13558         case BCM57811:
13559         case BCM57811_MF:
13560                 return BNX2X_MULTI_TX_COS_E3B0;
13561         case BCM57712_VF:
13562         case BCM57800_VF:
13563         case BCM57810_VF:
13564         case BCM57840_VF:
13565         case BCM57811_VF:
13566                 return 1;
13567         default:
13568                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13569                 return -ENODEV;
13570         }
13571 }
13572
13573 static int set_is_vf(int chip_id)
13574 {
13575         switch (chip_id) {
13576         case BCM57712_VF:
13577         case BCM57800_VF:
13578         case BCM57810_VF:
13579         case BCM57840_VF:
13580         case BCM57811_VF:
13581                 return true;
13582         default:
13583                 return false;
13584         }
13585 }
13586
13587 /* nig_tsgen registers relative address */
13588 #define tsgen_ctrl 0x0
13589 #define tsgen_freecount 0x10
13590 #define tsgen_synctime_t0 0x20
13591 #define tsgen_offset_t0 0x28
13592 #define tsgen_drift_t0 0x30
13593 #define tsgen_synctime_t1 0x58
13594 #define tsgen_offset_t1 0x60
13595 #define tsgen_drift_t1 0x68
13596
13597 /* FW workaround for setting drift */
13598 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13599                                           int best_val, int best_period)
13600 {
13601         struct bnx2x_func_state_params func_params = {NULL};
13602         struct bnx2x_func_set_timesync_params *set_timesync_params =
13603                 &func_params.params.set_timesync;
13604
13605         /* Prepare parameters for function state transitions */
13606         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13607         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13608
13609         func_params.f_obj = &bp->func_obj;
13610         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13611
13612         /* Function parameters */
13613         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13614         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13615         set_timesync_params->add_sub_drift_adjust_value =
13616                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13617         set_timesync_params->drift_adjust_value = best_val;
13618         set_timesync_params->drift_adjust_period = best_period;
13619
13620         return bnx2x_func_state_change(bp, &func_params);
13621 }
13622
13623 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13624 {
13625         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13626         int rc;
13627         int drift_dir = 1;
13628         int val, period, period1, period2, dif, dif1, dif2;
13629         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13630
13631         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13632
13633         if (!netif_running(bp->dev)) {
13634                 DP(BNX2X_MSG_PTP,
13635                    "PTP adjfreq called while the interface is down\n");
13636                 return -ENETDOWN;
13637         }
13638
13639         if (ppb < 0) {
13640                 ppb = -ppb;
13641                 drift_dir = 0;
13642         }
13643
13644         if (ppb == 0) {
13645                 best_val = 1;
13646                 best_period = 0x1FFFFFF;
13647         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13648                 best_val = 31;
13649                 best_period = 1;
13650         } else {
13651                 /* Changed not to allow val = 8, 16, 24 as these values
13652                  * are not supported in workaround.
13653                  */
13654                 for (val = 0; val <= 31; val++) {
13655                         if ((val & 0x7) == 0)
13656                                 continue;
13657                         period1 = val * 1000000 / ppb;
13658                         period2 = period1 + 1;
13659                         if (period1 != 0)
13660                                 dif1 = ppb - (val * 1000000 / period1);
13661                         else
13662                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13663                         if (dif1 < 0)
13664                                 dif1 = -dif1;
13665                         dif2 = ppb - (val * 1000000 / period2);
13666                         if (dif2 < 0)
13667                                 dif2 = -dif2;
13668                         dif = (dif1 < dif2) ? dif1 : dif2;
13669                         period = (dif1 < dif2) ? period1 : period2;
13670                         if (dif < best_dif) {
13671                                 best_dif = dif;
13672                                 best_val = val;
13673                                 best_period = period;
13674                         }
13675                 }
13676         }
13677
13678         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13679                                             best_period);
13680         if (rc) {
13681                 BNX2X_ERR("Failed to set drift\n");
13682                 return -EFAULT;
13683         }
13684
13685         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13686            best_period);
13687
13688         return 0;
13689 }
13690
13691 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13692 {
13693         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13694
13695         if (!netif_running(bp->dev)) {
13696                 DP(BNX2X_MSG_PTP,
13697                    "PTP adjtime called while the interface is down\n");
13698                 return -ENETDOWN;
13699         }
13700
13701         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13702
13703         timecounter_adjtime(&bp->timecounter, delta);
13704
13705         return 0;
13706 }
13707
13708 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13709 {
13710         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13711         u64 ns;
13712
13713         if (!netif_running(bp->dev)) {
13714                 DP(BNX2X_MSG_PTP,
13715                    "PTP gettime called while the interface is down\n");
13716                 return -ENETDOWN;
13717         }
13718
13719         ns = timecounter_read(&bp->timecounter);
13720
13721         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13722
13723         *ts = ns_to_timespec64(ns);
13724
13725         return 0;
13726 }
13727
13728 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13729                              const struct timespec64 *ts)
13730 {
13731         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13732         u64 ns;
13733
13734         if (!netif_running(bp->dev)) {
13735                 DP(BNX2X_MSG_PTP,
13736                    "PTP settime called while the interface is down\n");
13737                 return -ENETDOWN;
13738         }
13739
13740         ns = timespec64_to_ns(ts);
13741
13742         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13743
13744         /* Re-init the timecounter */
13745         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13746
13747         return 0;
13748 }
13749
13750 /* Enable (or disable) ancillary features of the phc subsystem */
13751 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13752                             struct ptp_clock_request *rq, int on)
13753 {
13754         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13755
13756         BNX2X_ERR("PHC ancillary features are not supported\n");
13757         return -ENOTSUPP;
13758 }
13759
13760 static void bnx2x_register_phc(struct bnx2x *bp)
13761 {
13762         /* Fill the ptp_clock_info struct and register PTP clock*/
13763         bp->ptp_clock_info.owner = THIS_MODULE;
13764         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13765         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13766         bp->ptp_clock_info.n_alarm = 0;
13767         bp->ptp_clock_info.n_ext_ts = 0;
13768         bp->ptp_clock_info.n_per_out = 0;
13769         bp->ptp_clock_info.pps = 0;
13770         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13771         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13772         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13773         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13774         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13775
13776         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13777         if (IS_ERR(bp->ptp_clock)) {
13778                 bp->ptp_clock = NULL;
13779                 BNX2X_ERR("PTP clock registeration failed\n");
13780         }
13781 }
13782
13783 static int bnx2x_init_one(struct pci_dev *pdev,
13784                                     const struct pci_device_id *ent)
13785 {
13786         struct net_device *dev = NULL;
13787         struct bnx2x *bp;
13788         enum pcie_link_width pcie_width;
13789         enum pci_bus_speed pcie_speed;
13790         int rc, max_non_def_sbs;
13791         int rx_count, tx_count, rss_count, doorbell_size;
13792         int max_cos_est;
13793         bool is_vf;
13794         int cnic_cnt;
13795
13796         /* Management FW 'remembers' living interfaces. Allow it some time
13797          * to forget previously living interfaces, allowing a proper re-load.
13798          */
13799         if (is_kdump_kernel()) {
13800                 ktime_t now = ktime_get_boottime();
13801                 ktime_t fw_ready_time = ktime_set(5, 0);
13802
13803                 if (ktime_before(now, fw_ready_time))
13804                         msleep(ktime_ms_delta(fw_ready_time, now));
13805         }
13806
13807         /* An estimated maximum supported CoS number according to the chip
13808          * version.
13809          * We will try to roughly estimate the maximum number of CoSes this chip
13810          * may support in order to minimize the memory allocated for Tx
13811          * netdev_queue's. This number will be accurately calculated during the
13812          * initialization of bp->max_cos based on the chip versions AND chip
13813          * revision in the bnx2x_init_bp().
13814          */
13815         max_cos_est = set_max_cos_est(ent->driver_data);
13816         if (max_cos_est < 0)
13817                 return max_cos_est;
13818         is_vf = set_is_vf(ent->driver_data);
13819         cnic_cnt = is_vf ? 0 : 1;
13820
13821         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13822
13823         /* add another SB for VF as it has no default SB */
13824         max_non_def_sbs += is_vf ? 1 : 0;
13825
13826         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13827         rss_count = max_non_def_sbs - cnic_cnt;
13828
13829         if (rss_count < 1)
13830                 return -EINVAL;
13831
13832         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13833         rx_count = rss_count + cnic_cnt;
13834
13835         /* Maximum number of netdev Tx queues:
13836          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13837          */
13838         tx_count = rss_count * max_cos_est + cnic_cnt;
13839
13840         /* dev zeroed in init_etherdev */
13841         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13842         if (!dev)
13843                 return -ENOMEM;
13844
13845         bp = netdev_priv(dev);
13846
13847         bp->flags = 0;
13848         if (is_vf)
13849                 bp->flags |= IS_VF_FLAG;
13850
13851         bp->igu_sb_cnt = max_non_def_sbs;
13852         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13853         bp->msg_enable = debug;
13854         bp->cnic_support = cnic_cnt;
13855         bp->cnic_probe = bnx2x_cnic_probe;
13856
13857         pci_set_drvdata(pdev, dev);
13858
13859         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13860         if (rc < 0) {
13861                 free_netdev(dev);
13862                 return rc;
13863         }
13864
13865         BNX2X_DEV_INFO("This is a %s function\n",
13866                        IS_PF(bp) ? "physical" : "virtual");
13867         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13868         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13869         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13870                        tx_count, rx_count);
13871
13872         rc = bnx2x_init_bp(bp);
13873         if (rc)
13874                 goto init_one_exit;
13875
13876         /* Map doorbells here as we need the real value of bp->max_cos which
13877          * is initialized in bnx2x_init_bp() to determine the number of
13878          * l2 connections.
13879          */
13880         if (IS_VF(bp)) {
13881                 bp->doorbells = bnx2x_vf_doorbells(bp);
13882                 rc = bnx2x_vf_pci_alloc(bp);
13883                 if (rc)
13884                         goto init_one_exit;
13885         } else {
13886                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13887                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13888                         dev_err(&bp->pdev->dev,
13889                                 "Cannot map doorbells, bar size too small, aborting\n");
13890                         rc = -ENOMEM;
13891                         goto init_one_exit;
13892                 }
13893                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13894                                                 doorbell_size);
13895         }
13896         if (!bp->doorbells) {
13897                 dev_err(&bp->pdev->dev,
13898                         "Cannot map doorbell space, aborting\n");
13899                 rc = -ENOMEM;
13900                 goto init_one_exit;
13901         }
13902
13903         if (IS_VF(bp)) {
13904                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13905                 if (rc)
13906                         goto init_one_exit;
13907         }
13908
13909         /* Enable SRIOV if capability found in configuration space */
13910         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13911         if (rc)
13912                 goto init_one_exit;
13913
13914         /* calc qm_cid_count */
13915         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13916         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13917
13918         /* disable FCOE L2 queue for E1x*/
13919         if (CHIP_IS_E1x(bp))
13920                 bp->flags |= NO_FCOE_FLAG;
13921
13922         /* Set bp->num_queues for MSI-X mode*/
13923         bnx2x_set_num_queues(bp);
13924
13925         /* Configure interrupt mode: try to enable MSI-X/MSI if
13926          * needed.
13927          */
13928         rc = bnx2x_set_int_mode(bp);
13929         if (rc) {
13930                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13931                 goto init_one_exit;
13932         }
13933         BNX2X_DEV_INFO("set interrupts successfully\n");
13934
13935         /* register the net device */
13936         rc = register_netdev(dev);
13937         if (rc) {
13938                 dev_err(&pdev->dev, "Cannot register net device\n");
13939                 goto init_one_exit;
13940         }
13941         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13942
13943         if (!NO_FCOE(bp)) {
13944                 /* Add storage MAC address */
13945                 rtnl_lock();
13946                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13947                 rtnl_unlock();
13948         }
13949         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13950             pcie_speed == PCI_SPEED_UNKNOWN ||
13951             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13952                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13953         else
13954                 BNX2X_DEV_INFO(
13955                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13956                        board_info[ent->driver_data].name,
13957                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13958                        pcie_width,
13959                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13960                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13961                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13962                        "Unknown",
13963                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13964
13965         bnx2x_register_phc(bp);
13966
13967         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13968                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13969
13970         return 0;
13971
13972 init_one_exit:
13973         bnx2x_disable_pcie_error_reporting(bp);
13974
13975         if (bp->regview)
13976                 iounmap(bp->regview);
13977
13978         if (IS_PF(bp) && bp->doorbells)
13979                 iounmap(bp->doorbells);
13980
13981         free_netdev(dev);
13982
13983         if (atomic_read(&pdev->enable_cnt) == 1)
13984                 pci_release_regions(pdev);
13985
13986         pci_disable_device(pdev);
13987
13988         return rc;
13989 }
13990
13991 static void __bnx2x_remove(struct pci_dev *pdev,
13992                            struct net_device *dev,
13993                            struct bnx2x *bp,
13994                            bool remove_netdev)
13995 {
13996         if (bp->ptp_clock) {
13997                 ptp_clock_unregister(bp->ptp_clock);
13998                 bp->ptp_clock = NULL;
13999         }
14000
14001         /* Delete storage MAC address */
14002         if (!NO_FCOE(bp)) {
14003                 rtnl_lock();
14004                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14005                 rtnl_unlock();
14006         }
14007
14008 #ifdef BCM_DCBNL
14009         /* Delete app tlvs from dcbnl */
14010         bnx2x_dcbnl_update_applist(bp, true);
14011 #endif
14012
14013         if (IS_PF(bp) &&
14014             !BP_NOMCP(bp) &&
14015             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14016                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14017
14018         /* Close the interface - either directly or implicitly */
14019         if (remove_netdev) {
14020                 unregister_netdev(dev);
14021         } else {
14022                 rtnl_lock();
14023                 dev_close(dev);
14024                 rtnl_unlock();
14025         }
14026
14027         bnx2x_iov_remove_one(bp);
14028
14029         /* Power on: we can't let PCI layer write to us while we are in D3 */
14030         if (IS_PF(bp)) {
14031                 bnx2x_set_power_state(bp, PCI_D0);
14032                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14033
14034                 /* Set endianity registers to reset values in case next driver
14035                  * boots in different endianty environment.
14036                  */
14037                 bnx2x_reset_endianity(bp);
14038         }
14039
14040         /* Disable MSI/MSI-X */
14041         bnx2x_disable_msi(bp);
14042
14043         /* Power off */
14044         if (IS_PF(bp))
14045                 bnx2x_set_power_state(bp, PCI_D3hot);
14046
14047         /* Make sure RESET task is not scheduled before continuing */
14048         cancel_delayed_work_sync(&bp->sp_rtnl_task);
14049
14050         /* send message via vfpf channel to release the resources of this vf */
14051         if (IS_VF(bp))
14052                 bnx2x_vfpf_release(bp);
14053
14054         /* Assumes no further PCIe PM changes will occur */
14055         if (system_state == SYSTEM_POWER_OFF) {
14056                 pci_wake_from_d3(pdev, bp->wol);
14057                 pci_set_power_state(pdev, PCI_D3hot);
14058         }
14059
14060         bnx2x_disable_pcie_error_reporting(bp);
14061         if (remove_netdev) {
14062                 if (bp->regview)
14063                         iounmap(bp->regview);
14064
14065                 /* For vfs, doorbells are part of the regview and were unmapped
14066                  * along with it. FW is only loaded by PF.
14067                  */
14068                 if (IS_PF(bp)) {
14069                         if (bp->doorbells)
14070                                 iounmap(bp->doorbells);
14071
14072                         bnx2x_release_firmware(bp);
14073                 } else {
14074                         bnx2x_vf_pci_dealloc(bp);
14075                 }
14076                 bnx2x_free_mem_bp(bp);
14077
14078                 free_netdev(dev);
14079
14080                 if (atomic_read(&pdev->enable_cnt) == 1)
14081                         pci_release_regions(pdev);
14082
14083                 pci_disable_device(pdev);
14084         }
14085 }
14086
14087 static void bnx2x_remove_one(struct pci_dev *pdev)
14088 {
14089         struct net_device *dev = pci_get_drvdata(pdev);
14090         struct bnx2x *bp;
14091
14092         if (!dev) {
14093                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14094                 return;
14095         }
14096         bp = netdev_priv(dev);
14097
14098         __bnx2x_remove(pdev, dev, bp, true);
14099 }
14100
14101 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14102 {
14103         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14104
14105         bp->rx_mode = BNX2X_RX_MODE_NONE;
14106
14107         if (CNIC_LOADED(bp))
14108                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14109
14110         /* Stop Tx */
14111         bnx2x_tx_disable(bp);
14112         /* Delete all NAPI objects */
14113         bnx2x_del_all_napi(bp);
14114         if (CNIC_LOADED(bp))
14115                 bnx2x_del_all_napi_cnic(bp);
14116         netdev_reset_tc(bp->dev);
14117
14118         del_timer_sync(&bp->timer);
14119         cancel_delayed_work_sync(&bp->sp_task);
14120         cancel_delayed_work_sync(&bp->period_task);
14121
14122         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14123                 bp->stats_state = STATS_STATE_DISABLED;
14124                 up(&bp->stats_lock);
14125         }
14126
14127         bnx2x_save_statistics(bp);
14128
14129         netif_carrier_off(bp->dev);
14130
14131         return 0;
14132 }
14133
14134 /**
14135  * bnx2x_io_error_detected - called when PCI error is detected
14136  * @pdev: Pointer to PCI device
14137  * @state: The current pci connection state
14138  *
14139  * This function is called after a PCI bus error affecting
14140  * this device has been detected.
14141  */
14142 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14143                                                 pci_channel_state_t state)
14144 {
14145         struct net_device *dev = pci_get_drvdata(pdev);
14146         struct bnx2x *bp = netdev_priv(dev);
14147
14148         rtnl_lock();
14149
14150         BNX2X_ERR("IO error detected\n");
14151
14152         netif_device_detach(dev);
14153
14154         if (state == pci_channel_io_perm_failure) {
14155                 rtnl_unlock();
14156                 return PCI_ERS_RESULT_DISCONNECT;
14157         }
14158
14159         if (netif_running(dev))
14160                 bnx2x_eeh_nic_unload(bp);
14161
14162         bnx2x_prev_path_mark_eeh(bp);
14163
14164         pci_disable_device(pdev);
14165
14166         rtnl_unlock();
14167
14168         /* Request a slot reset */
14169         return PCI_ERS_RESULT_NEED_RESET;
14170 }
14171
14172 /**
14173  * bnx2x_io_slot_reset - called after the PCI bus has been reset
14174  * @pdev: Pointer to PCI device
14175  *
14176  * Restart the card from scratch, as if from a cold-boot.
14177  */
14178 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14179 {
14180         struct net_device *dev = pci_get_drvdata(pdev);
14181         struct bnx2x *bp = netdev_priv(dev);
14182         int i;
14183
14184         rtnl_lock();
14185         BNX2X_ERR("IO slot reset initializing...\n");
14186         if (pci_enable_device(pdev)) {
14187                 dev_err(&pdev->dev,
14188                         "Cannot re-enable PCI device after reset\n");
14189                 rtnl_unlock();
14190                 return PCI_ERS_RESULT_DISCONNECT;
14191         }
14192
14193         pci_set_master(pdev);
14194         pci_restore_state(pdev);
14195         pci_save_state(pdev);
14196
14197         if (netif_running(dev))
14198                 bnx2x_set_power_state(bp, PCI_D0);
14199
14200         if (netif_running(dev)) {
14201                 BNX2X_ERR("IO slot reset --> driver unload\n");
14202
14203                 /* MCP should have been reset; Need to wait for validity */
14204                 if (bnx2x_init_shmem(bp)) {
14205                         rtnl_unlock();
14206                         return PCI_ERS_RESULT_DISCONNECT;
14207                 }
14208
14209                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14210                         u32 v;
14211
14212                         v = SHMEM2_RD(bp,
14213                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14214                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14215                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14216                 }
14217                 bnx2x_drain_tx_queues(bp);
14218                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14219                 bnx2x_netif_stop(bp, 1);
14220                 bnx2x_free_irq(bp);
14221
14222                 /* Report UNLOAD_DONE to MCP */
14223                 bnx2x_send_unload_done(bp, true);
14224
14225                 bp->sp_state = 0;
14226                 bp->port.pmf = 0;
14227
14228                 bnx2x_prev_unload(bp);
14229
14230                 /* We should have reseted the engine, so It's fair to
14231                  * assume the FW will no longer write to the bnx2x driver.
14232                  */
14233                 bnx2x_squeeze_objects(bp);
14234                 bnx2x_free_skbs(bp);
14235                 for_each_rx_queue(bp, i)
14236                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14237                 bnx2x_free_fp_mem(bp);
14238                 bnx2x_free_mem(bp);
14239
14240                 bp->state = BNX2X_STATE_CLOSED;
14241         }
14242
14243         rtnl_unlock();
14244
14245         /* If AER, perform cleanup of the PCIe registers */
14246         if (bp->flags & AER_ENABLED) {
14247                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14248                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14249                 else
14250                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14251         }
14252
14253         return PCI_ERS_RESULT_RECOVERED;
14254 }
14255
14256 /**
14257  * bnx2x_io_resume - called when traffic can start flowing again
14258  * @pdev: Pointer to PCI device
14259  *
14260  * This callback is called when the error recovery driver tells us that
14261  * its OK to resume normal operation.
14262  */
14263 static void bnx2x_io_resume(struct pci_dev *pdev)
14264 {
14265         struct net_device *dev = pci_get_drvdata(pdev);
14266         struct bnx2x *bp = netdev_priv(dev);
14267
14268         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14269                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14270                 return;
14271         }
14272
14273         rtnl_lock();
14274
14275         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14276                                                         DRV_MSG_SEQ_NUMBER_MASK;
14277
14278         if (netif_running(dev))
14279                 bnx2x_nic_load(bp, LOAD_NORMAL);
14280
14281         netif_device_attach(dev);
14282
14283         rtnl_unlock();
14284 }
14285
14286 static const struct pci_error_handlers bnx2x_err_handler = {
14287         .error_detected = bnx2x_io_error_detected,
14288         .slot_reset     = bnx2x_io_slot_reset,
14289         .resume         = bnx2x_io_resume,
14290 };
14291
14292 static void bnx2x_shutdown(struct pci_dev *pdev)
14293 {
14294         struct net_device *dev = pci_get_drvdata(pdev);
14295         struct bnx2x *bp;
14296
14297         if (!dev)
14298                 return;
14299
14300         bp = netdev_priv(dev);
14301         if (!bp)
14302                 return;
14303
14304         rtnl_lock();
14305         netif_device_detach(dev);
14306         rtnl_unlock();
14307
14308         /* Don't remove the netdevice, as there are scenarios which will cause
14309          * the kernel to hang, e.g., when trying to remove bnx2i while the
14310          * rootfs is mounted from SAN.
14311          */
14312         __bnx2x_remove(pdev, dev, bp, false);
14313 }
14314
14315 static struct pci_driver bnx2x_pci_driver = {
14316         .name        = DRV_MODULE_NAME,
14317         .id_table    = bnx2x_pci_tbl,
14318         .probe       = bnx2x_init_one,
14319         .remove      = bnx2x_remove_one,
14320         .suspend     = bnx2x_suspend,
14321         .resume      = bnx2x_resume,
14322         .err_handler = &bnx2x_err_handler,
14323 #ifdef CONFIG_BNX2X_SRIOV
14324         .sriov_configure = bnx2x_sriov_configure,
14325 #endif
14326         .shutdown    = bnx2x_shutdown,
14327 };
14328
14329 static int __init bnx2x_init(void)
14330 {
14331         int ret;
14332
14333         pr_info("%s", version);
14334
14335         bnx2x_wq = create_singlethread_workqueue("bnx2x");
14336         if (bnx2x_wq == NULL) {
14337                 pr_err("Cannot create workqueue\n");
14338                 return -ENOMEM;
14339         }
14340         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14341         if (!bnx2x_iov_wq) {
14342                 pr_err("Cannot create iov workqueue\n");
14343                 destroy_workqueue(bnx2x_wq);
14344                 return -ENOMEM;
14345         }
14346
14347         ret = pci_register_driver(&bnx2x_pci_driver);
14348         if (ret) {
14349                 pr_err("Cannot register driver\n");
14350                 destroy_workqueue(bnx2x_wq);
14351                 destroy_workqueue(bnx2x_iov_wq);
14352         }
14353         return ret;
14354 }
14355
14356 static void __exit bnx2x_cleanup(void)
14357 {
14358         struct list_head *pos, *q;
14359
14360         pci_unregister_driver(&bnx2x_pci_driver);
14361
14362         destroy_workqueue(bnx2x_wq);
14363         destroy_workqueue(bnx2x_iov_wq);
14364
14365         /* Free globally allocated resources */
14366         list_for_each_safe(pos, q, &bnx2x_prev_list) {
14367                 struct bnx2x_prev_path_list *tmp =
14368                         list_entry(pos, struct bnx2x_prev_path_list, list);
14369                 list_del(pos);
14370                 kfree(tmp);
14371         }
14372 }
14373
14374 void bnx2x_notify_link_changed(struct bnx2x *bp)
14375 {
14376         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14377 }
14378
14379 module_init(bnx2x_init);
14380 module_exit(bnx2x_cleanup);
14381
14382 /**
14383  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14384  *
14385  * @bp:         driver handle
14386  * @set:        set or clear the CAM entry
14387  *
14388  * This function will wait until the ramrod completion returns.
14389  * Return 0 if success, -ENODEV if ramrod doesn't return.
14390  */
14391 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14392 {
14393         unsigned long ramrod_flags = 0;
14394
14395         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14396         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14397                                  &bp->iscsi_l2_mac_obj, true,
14398                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14399 }
14400
14401 /* count denotes the number of new completions we have seen */
14402 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14403 {
14404         struct eth_spe *spe;
14405         int cxt_index, cxt_offset;
14406
14407 #ifdef BNX2X_STOP_ON_ERROR
14408         if (unlikely(bp->panic))
14409                 return;
14410 #endif
14411
14412         spin_lock_bh(&bp->spq_lock);
14413         BUG_ON(bp->cnic_spq_pending < count);
14414         bp->cnic_spq_pending -= count;
14415
14416         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14417                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14418                                 & SPE_HDR_CONN_TYPE) >>
14419                                 SPE_HDR_CONN_TYPE_SHIFT;
14420                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14421                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14422
14423                 /* Set validation for iSCSI L2 client before sending SETUP
14424                  *  ramrod
14425                  */
14426                 if (type == ETH_CONNECTION_TYPE) {
14427                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14428                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14429                                         ILT_PAGE_CIDS;
14430                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14431                                         (cxt_index * ILT_PAGE_CIDS);
14432                                 bnx2x_set_ctx_validation(bp,
14433                                         &bp->context[cxt_index].
14434                                                          vcxt[cxt_offset].eth,
14435                                         BNX2X_ISCSI_ETH_CID(bp));
14436                         }
14437                 }
14438
14439                 /*
14440                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14441                  * and in the air. We also check that number of outstanding
14442                  * COMMON ramrods is not more than the EQ and SPQ can
14443                  * accommodate.
14444                  */
14445                 if (type == ETH_CONNECTION_TYPE) {
14446                         if (!atomic_read(&bp->cq_spq_left))
14447                                 break;
14448                         else
14449                                 atomic_dec(&bp->cq_spq_left);
14450                 } else if (type == NONE_CONNECTION_TYPE) {
14451                         if (!atomic_read(&bp->eq_spq_left))
14452                                 break;
14453                         else
14454                                 atomic_dec(&bp->eq_spq_left);
14455                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14456                            (type == FCOE_CONNECTION_TYPE)) {
14457                         if (bp->cnic_spq_pending >=
14458                             bp->cnic_eth_dev.max_kwqe_pending)
14459                                 break;
14460                         else
14461                                 bp->cnic_spq_pending++;
14462                 } else {
14463                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14464                         bnx2x_panic();
14465                         break;
14466                 }
14467
14468                 spe = bnx2x_sp_get_next(bp);
14469                 *spe = *bp->cnic_kwq_cons;
14470
14471                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14472                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14473
14474                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14475                         bp->cnic_kwq_cons = bp->cnic_kwq;
14476                 else
14477                         bp->cnic_kwq_cons++;
14478         }
14479         bnx2x_sp_prod_update(bp);
14480         spin_unlock_bh(&bp->spq_lock);
14481 }
14482
14483 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14484                                struct kwqe_16 *kwqes[], u32 count)
14485 {
14486         struct bnx2x *bp = netdev_priv(dev);
14487         int i;
14488
14489 #ifdef BNX2X_STOP_ON_ERROR
14490         if (unlikely(bp->panic)) {
14491                 BNX2X_ERR("Can't post to SP queue while panic\n");
14492                 return -EIO;
14493         }
14494 #endif
14495
14496         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14497             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14498                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14499                 return -EAGAIN;
14500         }
14501
14502         spin_lock_bh(&bp->spq_lock);
14503
14504         for (i = 0; i < count; i++) {
14505                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14506
14507                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14508                         break;
14509
14510                 *bp->cnic_kwq_prod = *spe;
14511
14512                 bp->cnic_kwq_pending++;
14513
14514                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14515                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14516                    spe->data.update_data_addr.hi,
14517                    spe->data.update_data_addr.lo,
14518                    bp->cnic_kwq_pending);
14519
14520                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14521                         bp->cnic_kwq_prod = bp->cnic_kwq;
14522                 else
14523                         bp->cnic_kwq_prod++;
14524         }
14525
14526         spin_unlock_bh(&bp->spq_lock);
14527
14528         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14529                 bnx2x_cnic_sp_post(bp, 0);
14530
14531         return i;
14532 }
14533
14534 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14535 {
14536         struct cnic_ops *c_ops;
14537         int rc = 0;
14538
14539         mutex_lock(&bp->cnic_mutex);
14540         c_ops = rcu_dereference_protected(bp->cnic_ops,
14541                                           lockdep_is_held(&bp->cnic_mutex));
14542         if (c_ops)
14543                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14544         mutex_unlock(&bp->cnic_mutex);
14545
14546         return rc;
14547 }
14548
14549 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14550 {
14551         struct cnic_ops *c_ops;
14552         int rc = 0;
14553
14554         rcu_read_lock();
14555         c_ops = rcu_dereference(bp->cnic_ops);
14556         if (c_ops)
14557                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14558         rcu_read_unlock();
14559
14560         return rc;
14561 }
14562
14563 /*
14564  * for commands that have no data
14565  */
14566 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14567 {
14568         struct cnic_ctl_info ctl = {0};
14569
14570         ctl.cmd = cmd;
14571
14572         return bnx2x_cnic_ctl_send(bp, &ctl);
14573 }
14574
14575 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14576 {
14577         struct cnic_ctl_info ctl = {0};
14578
14579         /* first we tell CNIC and only then we count this as a completion */
14580         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14581         ctl.data.comp.cid = cid;
14582         ctl.data.comp.error = err;
14583
14584         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14585         bnx2x_cnic_sp_post(bp, 0);
14586 }
14587
14588 /* Called with netif_addr_lock_bh() taken.
14589  * Sets an rx_mode config for an iSCSI ETH client.
14590  * Doesn't block.
14591  * Completion should be checked outside.
14592  */
14593 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14594 {
14595         unsigned long accept_flags = 0, ramrod_flags = 0;
14596         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14597         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14598
14599         if (start) {
14600                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14601                  * because it's the only way for UIO Queue to accept
14602                  * multicasts (in non-promiscuous mode only one Queue per
14603                  * function will receive multicast packets (leading in our
14604                  * case).
14605                  */
14606                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14607                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14608                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14609                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14610
14611                 /* Clear STOP_PENDING bit if START is requested */
14612                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14613
14614                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14615         } else
14616                 /* Clear START_PENDING bit if STOP is requested */
14617                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14618
14619         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14620                 set_bit(sched_state, &bp->sp_state);
14621         else {
14622                 __set_bit(RAMROD_RX, &ramrod_flags);
14623                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14624                                     ramrod_flags);
14625         }
14626 }
14627
14628 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14629 {
14630         struct bnx2x *bp = netdev_priv(dev);
14631         int rc = 0;
14632
14633         switch (ctl->cmd) {
14634         case DRV_CTL_CTXTBL_WR_CMD: {
14635                 u32 index = ctl->data.io.offset;
14636                 dma_addr_t addr = ctl->data.io.dma_addr;
14637
14638                 bnx2x_ilt_wr(bp, index, addr);
14639                 break;
14640         }
14641
14642         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14643                 int count = ctl->data.credit.credit_count;
14644
14645                 bnx2x_cnic_sp_post(bp, count);
14646                 break;
14647         }
14648
14649         /* rtnl_lock is held.  */
14650         case DRV_CTL_START_L2_CMD: {
14651                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14652                 unsigned long sp_bits = 0;
14653
14654                 /* Configure the iSCSI classification object */
14655                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14656                                    cp->iscsi_l2_client_id,
14657                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14658                                    bnx2x_sp(bp, mac_rdata),
14659                                    bnx2x_sp_mapping(bp, mac_rdata),
14660                                    BNX2X_FILTER_MAC_PENDING,
14661                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14662                                    &bp->macs_pool);
14663
14664                 /* Set iSCSI MAC address */
14665                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14666                 if (rc)
14667                         break;
14668
14669                 mmiowb();
14670                 barrier();
14671
14672                 /* Start accepting on iSCSI L2 ring */
14673
14674                 netif_addr_lock_bh(dev);
14675                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14676                 netif_addr_unlock_bh(dev);
14677
14678                 /* bits to wait on */
14679                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14680                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14681
14682                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14683                         BNX2X_ERR("rx_mode completion timed out!\n");
14684
14685                 break;
14686         }
14687
14688         /* rtnl_lock is held.  */
14689         case DRV_CTL_STOP_L2_CMD: {
14690                 unsigned long sp_bits = 0;
14691
14692                 /* Stop accepting on iSCSI L2 ring */
14693                 netif_addr_lock_bh(dev);
14694                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14695                 netif_addr_unlock_bh(dev);
14696
14697                 /* bits to wait on */
14698                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14699                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14700
14701                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14702                         BNX2X_ERR("rx_mode completion timed out!\n");
14703
14704                 mmiowb();
14705                 barrier();
14706
14707                 /* Unset iSCSI L2 MAC */
14708                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14709                                         BNX2X_ISCSI_ETH_MAC, true);
14710                 break;
14711         }
14712         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14713                 int count = ctl->data.credit.credit_count;
14714
14715                 smp_mb__before_atomic();
14716                 atomic_add(count, &bp->cq_spq_left);
14717                 smp_mb__after_atomic();
14718                 break;
14719         }
14720         case DRV_CTL_ULP_REGISTER_CMD: {
14721                 int ulp_type = ctl->data.register_data.ulp_type;
14722
14723                 if (CHIP_IS_E3(bp)) {
14724                         int idx = BP_FW_MB_IDX(bp);
14725                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14726                         int path = BP_PATH(bp);
14727                         int port = BP_PORT(bp);
14728                         int i;
14729                         u32 scratch_offset;
14730                         u32 *host_addr;
14731
14732                         /* first write capability to shmem2 */
14733                         if (ulp_type == CNIC_ULP_ISCSI)
14734                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14735                         else if (ulp_type == CNIC_ULP_FCOE)
14736                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14737                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14738
14739                         if ((ulp_type != CNIC_ULP_FCOE) ||
14740                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14741                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14742                                 break;
14743
14744                         /* if reached here - should write fcoe capabilities */
14745                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14746                         if (!scratch_offset)
14747                                 break;
14748                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14749                                                    fcoe_features[path][port]);
14750                         host_addr = (u32 *) &(ctl->data.register_data.
14751                                               fcoe_features);
14752                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14753                              i += 4)
14754                                 REG_WR(bp, scratch_offset + i,
14755                                        *(host_addr + i/4));
14756                 }
14757                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14758                 break;
14759         }
14760
14761         case DRV_CTL_ULP_UNREGISTER_CMD: {
14762                 int ulp_type = ctl->data.ulp_type;
14763
14764                 if (CHIP_IS_E3(bp)) {
14765                         int idx = BP_FW_MB_IDX(bp);
14766                         u32 cap;
14767
14768                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14769                         if (ulp_type == CNIC_ULP_ISCSI)
14770                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14771                         else if (ulp_type == CNIC_ULP_FCOE)
14772                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14773                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14774                 }
14775                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14776                 break;
14777         }
14778
14779         default:
14780                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14781                 rc = -EINVAL;
14782         }
14783
14784         /* For storage-only interfaces, change driver state */
14785         if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14786                 switch (ctl->drv_state) {
14787                 case DRV_NOP:
14788                         break;
14789                 case DRV_ACTIVE:
14790                         bnx2x_set_os_driver_state(bp,
14791                                                   OS_DRIVER_STATE_ACTIVE);
14792                         break;
14793                 case DRV_INACTIVE:
14794                         bnx2x_set_os_driver_state(bp,
14795                                                   OS_DRIVER_STATE_DISABLED);
14796                         break;
14797                 case DRV_UNLOADED:
14798                         bnx2x_set_os_driver_state(bp,
14799                                                   OS_DRIVER_STATE_NOT_LOADED);
14800                         break;
14801                 default:
14802                 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14803                 }
14804         }
14805
14806         return rc;
14807 }
14808
14809 static int bnx2x_get_fc_npiv(struct net_device *dev,
14810                              struct cnic_fc_npiv_tbl *cnic_tbl)
14811 {
14812         struct bnx2x *bp = netdev_priv(dev);
14813         struct bdn_fc_npiv_tbl *tbl = NULL;
14814         u32 offset, entries;
14815         int rc = -EINVAL;
14816         int i;
14817
14818         if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14819                 goto out;
14820
14821         DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14822
14823         tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14824         if (!tbl) {
14825                 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14826                 goto out;
14827         }
14828
14829         offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14830         if (!offset) {
14831                 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14832                 goto out;
14833         }
14834         DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14835
14836         /* Read the table contents from nvram */
14837         if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14838                 BNX2X_ERR("Failed to read FC-NPIV table\n");
14839                 goto out;
14840         }
14841
14842         /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14843          * the number of entries back to cpu endianness.
14844          */
14845         entries = tbl->fc_npiv_cfg.num_of_npiv;
14846         entries = (__force u32)be32_to_cpu((__force __be32)entries);
14847         tbl->fc_npiv_cfg.num_of_npiv = entries;
14848
14849         if (!tbl->fc_npiv_cfg.num_of_npiv) {
14850                 DP(BNX2X_MSG_MCP,
14851                    "No FC-NPIV table [valid, simply not present]\n");
14852                 goto out;
14853         } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14854                 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14855                           tbl->fc_npiv_cfg.num_of_npiv);
14856                 goto out;
14857         } else {
14858                 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14859                    tbl->fc_npiv_cfg.num_of_npiv);
14860         }
14861
14862         /* Copy the data into cnic-provided struct */
14863         cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14864         for (i = 0; i < cnic_tbl->count; i++) {
14865                 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14866                 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14867         }
14868
14869         rc = 0;
14870 out:
14871         kfree(tbl);
14872         return rc;
14873 }
14874
14875 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14876 {
14877         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14878
14879         if (bp->flags & USING_MSIX_FLAG) {
14880                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14881                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14882                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14883         } else {
14884                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14885                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14886         }
14887         if (!CHIP_IS_E1x(bp))
14888                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14889         else
14890                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14891
14892         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14893         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14894         cp->irq_arr[1].status_blk = bp->def_status_blk;
14895         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14896         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14897
14898         cp->num_irq = 2;
14899 }
14900
14901 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14902 {
14903         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14904
14905         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14906                              bnx2x_cid_ilt_lines(bp);
14907         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14908         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14909         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14910
14911         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14912            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14913            cp->iscsi_l2_cid);
14914
14915         if (NO_ISCSI_OOO(bp))
14916                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14917 }
14918
14919 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14920                                void *data)
14921 {
14922         struct bnx2x *bp = netdev_priv(dev);
14923         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14924         int rc;
14925
14926         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14927
14928         if (ops == NULL) {
14929                 BNX2X_ERR("NULL ops received\n");
14930                 return -EINVAL;
14931         }
14932
14933         if (!CNIC_SUPPORT(bp)) {
14934                 BNX2X_ERR("Can't register CNIC when not supported\n");
14935                 return -EOPNOTSUPP;
14936         }
14937
14938         if (!CNIC_LOADED(bp)) {
14939                 rc = bnx2x_load_cnic(bp);
14940                 if (rc) {
14941                         BNX2X_ERR("CNIC-related load failed\n");
14942                         return rc;
14943                 }
14944         }
14945
14946         bp->cnic_enabled = true;
14947
14948         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14949         if (!bp->cnic_kwq)
14950                 return -ENOMEM;
14951
14952         bp->cnic_kwq_cons = bp->cnic_kwq;
14953         bp->cnic_kwq_prod = bp->cnic_kwq;
14954         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14955
14956         bp->cnic_spq_pending = 0;
14957         bp->cnic_kwq_pending = 0;
14958
14959         bp->cnic_data = data;
14960
14961         cp->num_irq = 0;
14962         cp->drv_state |= CNIC_DRV_STATE_REGD;
14963         cp->iro_arr = bp->iro_arr;
14964
14965         bnx2x_setup_cnic_irq_info(bp);
14966
14967         rcu_assign_pointer(bp->cnic_ops, ops);
14968
14969         /* Schedule driver to read CNIC driver versions */
14970         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14971
14972         return 0;
14973 }
14974
14975 static int bnx2x_unregister_cnic(struct net_device *dev)
14976 {
14977         struct bnx2x *bp = netdev_priv(dev);
14978         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14979
14980         mutex_lock(&bp->cnic_mutex);
14981         cp->drv_state = 0;
14982         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14983         mutex_unlock(&bp->cnic_mutex);
14984         synchronize_rcu();
14985         bp->cnic_enabled = false;
14986         kfree(bp->cnic_kwq);
14987         bp->cnic_kwq = NULL;
14988
14989         return 0;
14990 }
14991
14992 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14993 {
14994         struct bnx2x *bp = netdev_priv(dev);
14995         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14996
14997         /* If both iSCSI and FCoE are disabled - return NULL in
14998          * order to indicate CNIC that it should not try to work
14999          * with this device.
15000          */
15001         if (NO_ISCSI(bp) && NO_FCOE(bp))
15002                 return NULL;
15003
15004         cp->drv_owner = THIS_MODULE;
15005         cp->chip_id = CHIP_ID(bp);
15006         cp->pdev = bp->pdev;
15007         cp->io_base = bp->regview;
15008         cp->io_base2 = bp->doorbells;
15009         cp->max_kwqe_pending = 8;
15010         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
15011         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15012                              bnx2x_cid_ilt_lines(bp);
15013         cp->ctx_tbl_len = CNIC_ILT_LINES;
15014         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15015         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15016         cp->drv_ctl = bnx2x_drv_ctl;
15017         cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15018         cp->drv_register_cnic = bnx2x_register_cnic;
15019         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15020         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15021         cp->iscsi_l2_client_id =
15022                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15023         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15024
15025         if (NO_ISCSI_OOO(bp))
15026                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15027
15028         if (NO_ISCSI(bp))
15029                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15030
15031         if (NO_FCOE(bp))
15032                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15033
15034         BNX2X_DEV_INFO(
15035                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15036            cp->ctx_blk_size,
15037            cp->ctx_tbl_offset,
15038            cp->ctx_tbl_len,
15039            cp->starting_cid);
15040         return cp;
15041 }
15042
15043 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15044 {
15045         struct bnx2x *bp = fp->bp;
15046         u32 offset = BAR_USTRORM_INTMEM;
15047
15048         if (IS_VF(bp))
15049                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15050         else if (!CHIP_IS_E1x(bp))
15051                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15052         else
15053                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15054
15055         return offset;
15056 }
15057
15058 /* called only on E1H or E2.
15059  * When pretending to be PF, the pretend value is the function number 0...7
15060  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15061  * combination
15062  */
15063 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15064 {
15065         u32 pretend_reg;
15066
15067         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15068                 return -1;
15069
15070         /* get my own pretend register */
15071         pretend_reg = bnx2x_get_pretend_reg(bp);
15072         REG_WR(bp, pretend_reg, pretend_func_val);
15073         REG_RD(bp, pretend_reg);
15074         return 0;
15075 }
15076
15077 static void bnx2x_ptp_task(struct work_struct *work)
15078 {
15079         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15080         int port = BP_PORT(bp);
15081         u32 val_seq;
15082         u64 timestamp, ns;
15083         struct skb_shared_hwtstamps shhwtstamps;
15084
15085         /* Read Tx timestamp registers */
15086         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15087                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15088         if (val_seq & 0x10000) {
15089                 /* There is a valid timestamp value */
15090                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15091                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15092                 timestamp <<= 32;
15093                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15094                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15095                 /* Reset timestamp register to allow new timestamp */
15096                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15097                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15098                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15099
15100                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15101                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15102                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15103                 dev_kfree_skb_any(bp->ptp_tx_skb);
15104                 bp->ptp_tx_skb = NULL;
15105
15106                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15107                    timestamp, ns);
15108         } else {
15109                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15110                 /* Reschedule to keep checking for a valid timestamp value */
15111                 schedule_work(&bp->ptp_task);
15112         }
15113 }
15114
15115 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15116 {
15117         int port = BP_PORT(bp);
15118         u64 timestamp, ns;
15119
15120         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15121                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15122         timestamp <<= 32;
15123         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15124                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15125
15126         /* Reset timestamp register to allow new timestamp */
15127         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15128                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15129
15130         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15131
15132         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15133
15134         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15135            timestamp, ns);
15136 }
15137
15138 /* Read the PHC */
15139 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15140 {
15141         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15142         int port = BP_PORT(bp);
15143         u32 wb_data[2];
15144         u64 phc_cycles;
15145
15146         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15147                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15148         phc_cycles = wb_data[1];
15149         phc_cycles = (phc_cycles << 32) + wb_data[0];
15150
15151         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15152
15153         return phc_cycles;
15154 }
15155
15156 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15157 {
15158         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15159         bp->cyclecounter.read = bnx2x_cyclecounter_read;
15160         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15161         bp->cyclecounter.shift = 1;
15162         bp->cyclecounter.mult = 1;
15163 }
15164
15165 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15166 {
15167         struct bnx2x_func_state_params func_params = {NULL};
15168         struct bnx2x_func_set_timesync_params *set_timesync_params =
15169                 &func_params.params.set_timesync;
15170
15171         /* Prepare parameters for function state transitions */
15172         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15173         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15174
15175         func_params.f_obj = &bp->func_obj;
15176         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15177
15178         /* Function parameters */
15179         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15180         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15181
15182         return bnx2x_func_state_change(bp, &func_params);
15183 }
15184
15185 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15186 {
15187         struct bnx2x_queue_state_params q_params;
15188         int rc, i;
15189
15190         /* send queue update ramrod to enable PTP packets */
15191         memset(&q_params, 0, sizeof(q_params));
15192         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15193         q_params.cmd = BNX2X_Q_CMD_UPDATE;
15194         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15195                   &q_params.params.update.update_flags);
15196         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15197                   &q_params.params.update.update_flags);
15198
15199         /* send the ramrod on all the queues of the PF */
15200         for_each_eth_queue(bp, i) {
15201                 struct bnx2x_fastpath *fp = &bp->fp[i];
15202
15203                 /* Set the appropriate Queue object */
15204                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15205
15206                 /* Update the Queue state */
15207                 rc = bnx2x_queue_state_change(bp, &q_params);
15208                 if (rc) {
15209                         BNX2X_ERR("Failed to enable PTP packets\n");
15210                         return rc;
15211                 }
15212         }
15213
15214         return 0;
15215 }
15216
15217 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15218 {
15219         int port = BP_PORT(bp);
15220         int rc;
15221
15222         if (!bp->hwtstamp_ioctl_called)
15223                 return 0;
15224
15225         switch (bp->tx_type) {
15226         case HWTSTAMP_TX_ON:
15227                 bp->flags |= TX_TIMESTAMPING_EN;
15228                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15229                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15230                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15231                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15232                 break;
15233         case HWTSTAMP_TX_ONESTEP_SYNC:
15234                 BNX2X_ERR("One-step timestamping is not supported\n");
15235                 return -ERANGE;
15236         }
15237
15238         switch (bp->rx_filter) {
15239         case HWTSTAMP_FILTER_NONE:
15240                 break;
15241         case HWTSTAMP_FILTER_ALL:
15242         case HWTSTAMP_FILTER_SOME:
15243                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15244                 break;
15245         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15246         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15247         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15248                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15249                 /* Initialize PTP detection for UDP/IPv4 events */
15250                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15251                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15252                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15253                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15254                 break;
15255         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15256         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15257         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15258                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15259                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15260                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15261                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15262                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15263                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15264                 break;
15265         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15266         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15267         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15268                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15269                 /* Initialize PTP detection L2 events */
15270                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15271                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15272                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15273                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15274
15275                 break;
15276         case HWTSTAMP_FILTER_PTP_V2_EVENT:
15277         case HWTSTAMP_FILTER_PTP_V2_SYNC:
15278         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15279                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15280                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15281                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15282                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15283                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15284                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15285                 break;
15286         }
15287
15288         /* Indicate to FW that this PF expects recorded PTP packets */
15289         rc = bnx2x_enable_ptp_packets(bp);
15290         if (rc)
15291                 return rc;
15292
15293         /* Enable sending PTP packets to host */
15294         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15295                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15296
15297         return 0;
15298 }
15299
15300 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15301 {
15302         struct hwtstamp_config config;
15303         int rc;
15304
15305         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15306
15307         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15308                 return -EFAULT;
15309
15310         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15311            config.tx_type, config.rx_filter);
15312
15313         if (config.flags) {
15314                 BNX2X_ERR("config.flags is reserved for future use\n");
15315                 return -EINVAL;
15316         }
15317
15318         bp->hwtstamp_ioctl_called = 1;
15319         bp->tx_type = config.tx_type;
15320         bp->rx_filter = config.rx_filter;
15321
15322         rc = bnx2x_configure_ptp_filters(bp);
15323         if (rc)
15324                 return rc;
15325
15326         config.rx_filter = bp->rx_filter;
15327
15328         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15329                 -EFAULT : 0;
15330 }
15331
15332 /* Configures HW for PTP */
15333 static int bnx2x_configure_ptp(struct bnx2x *bp)
15334 {
15335         int rc, port = BP_PORT(bp);
15336         u32 wb_data[2];
15337
15338         /* Reset PTP event detection rules - will be configured in the IOCTL */
15339         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15340                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15341         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15342                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15343         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15344                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15345         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15346                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15347
15348         /* Disable PTP packets to host - will be configured in the IOCTL*/
15349         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15350                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15351
15352         /* Enable the PTP feature */
15353         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15354                NIG_REG_P0_PTP_EN, 0x3F);
15355
15356         /* Enable the free-running counter */
15357         wb_data[0] = 0;
15358         wb_data[1] = 0;
15359         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15360
15361         /* Reset drift register (offset register is not reset) */
15362         rc = bnx2x_send_reset_timesync_ramrod(bp);
15363         if (rc) {
15364                 BNX2X_ERR("Failed to reset PHC drift register\n");
15365                 return -EFAULT;
15366         }
15367
15368         /* Reset possibly old timestamps */
15369         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15370                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15371         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15372                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15373
15374         return 0;
15375 }
15376
15377 /* Called during load, to initialize PTP-related stuff */
15378 void bnx2x_init_ptp(struct bnx2x *bp)
15379 {
15380         int rc;
15381
15382         /* Configure PTP in HW */
15383         rc = bnx2x_configure_ptp(bp);
15384         if (rc) {
15385                 BNX2X_ERR("Stopping PTP initialization\n");
15386                 return;
15387         }
15388
15389         /* Init work queue for Tx timestamping */
15390         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15391
15392         /* Init cyclecounter and timecounter. This is done only in the first
15393          * load. If done in every load, PTP application will fail when doing
15394          * unload / load (e.g. MTU change) while it is running.
15395          */
15396         if (!bp->timecounter_init_done) {
15397                 bnx2x_init_cyclecounter(bp);
15398                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15399                                  ktime_to_ns(ktime_get_real()));
15400                 bp->timecounter_init_done = 1;
15401         }
15402
15403         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15404 }