drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62 #include "bnx2x.h"
  63 #include "bnx2x_init.h"
  64 #include "bnx2x_init_ops.h"
  65 #include "bnx2x_cmn.h"
  66 #include "bnx2x_vfpf.h"
  67 #include "bnx2x_dcb.h"
  68 #include "bnx2x_sp.h"
  69 #include <linux/firmware.h>
  70 #include "bnx2x_fw_file_hdr.h"
  71 /* FW files */
  72 /*(DEBLOBBED)*/
  73 #define FW_FILE_NAME_E1         "/*(DEBLOBBED)*/"
  74 #define FW_FILE_NAME_E1H        "/*(DEBLOBBED)*/"
  75 #define FW_FILE_NAME_E2         "/*(DEBLOBBED)*/"
  76 #define bnx2x_init_block(bp, start, end) \
  77   return (printk(KERN_ERR "%s: Missing Free firmware\n", bp->dev->name),\
  78           -EINVAL)
  79
  80 /* Time in jiffies before concluding the transmitter is hung */
  81 #define TX_TIMEOUT              (5*HZ)
  82
  83 static char version[] =
  84         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  86
  87 MODULE_AUTHOR("Eliezer Tamir");
  88 MODULE_DESCRIPTION("QLogic "
  89                    "BCM57710/57711/57711E/"
  90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  91                    "57840/57840_MF Driver");
  92 MODULE_LICENSE("GPL");
  93 MODULE_VERSION(DRV_MODULE_VERSION);
  94 /*(DEBLOBBED)*/
  95
  96 int bnx2x_num_queues;
  97 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  98 MODULE_PARM_DESC(num_queues,
  99                  " Set number of queues (default is as a number of CPUs)");
 100
 101 static int disable_tpa;
 102 module_param(disable_tpa, int, S_IRUGO);
 103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 104
 105 static int int_mode;
 106 module_param(int_mode, int, S_IRUGO);
 107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 108                                 "(1 INT#x; 2 MSI)");
 109
 110 static int dropless_fc;
 111 module_param(dropless_fc, int, S_IRUGO);
 112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 113
 114 static int mrrs = -1;
 115 module_param(mrrs, int, S_IRUGO);
 116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 117
 118 static int debug;
 119 module_param(debug, int, S_IRUGO);
 120 MODULE_PARM_DESC(debug, " Default debug msglevel");
 121
 122 static struct workqueue_struct *bnx2x_wq;
 123 struct workqueue_struct *bnx2x_iov_wq;
 124
 125 struct bnx2x_mac_vals {
 126         u32 xmac_addr;
 127         u32 xmac_val;
 128         u32 emac_addr;
 129         u32 emac_val;
 130         u32 umac_addr[2];
 131         u32 umac_val[2];
 132         u32 bmac_addr;
 133         u32 bmac_val[2];
 134 };
 135
 136 enum bnx2x_board_type {
 137         BCM57710 = 0,
 138         BCM57711,
 139         BCM57711E,
 140         BCM57712,
 141         BCM57712_MF,
 142         BCM57712_VF,
 143         BCM57800,
 144         BCM57800_MF,
 145         BCM57800_VF,
 146         BCM57810,
 147         BCM57810_MF,
 148         BCM57810_VF,
 149         BCM57840_4_10,
 150         BCM57840_2_20,
 151         BCM57840_MF,
 152         BCM57840_VF,
 153         BCM57811,
 154         BCM57811_MF,
 155         BCM57840_O,
 156         BCM57840_MFO,
 157         BCM57811_VF
 158 };
 159
 160 /* indexed by board_type, above */
 161 static struct {
 162         char *name;
 163 } board_info[] = {
 164         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 165         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 166         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 167         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 168         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 169         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 170         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 171         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 172         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 173         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 174         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 175         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 177         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 178         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 179         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 180         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 181         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 182         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 183         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 184         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 185 };
 186
 187 #ifndef PCI_DEVICE_ID_NX2_57710
 188 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 189 #endif
 190 #ifndef PCI_DEVICE_ID_NX2_57711
 191 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 192 #endif
 193 #ifndef PCI_DEVICE_ID_NX2_57711E
 194 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57712
 197 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 200 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 203 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57800
 206 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 209 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 212 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57810
 215 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 218 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57840_O
 221 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 224 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 227 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 230 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 233 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 236 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 239 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57811
 242 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 245 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 248 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 249 #endif
 250
 251 static const struct pci_device_id bnx2x_pci_tbl[] = {
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 265         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 270         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 272         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 276         { 0 }
 277 };
 278
 279 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 280
 281 /* Global resources for unloading a previously loaded device */
 282 #define BNX2X_PREV_WAIT_NEEDED 1
 283 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 284 static LIST_HEAD(bnx2x_prev_list);
 285
 286 /* Forward declaration */
 287 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 288 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 289 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 290
 291 /****************************************************************************
 292 * General service functions
 293 ****************************************************************************/
 294
 295 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 296
 297 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 298                                        u32 addr, dma_addr_t mapping)
 299 {
 300         REG_WR(bp,  addr, U64_LO(mapping));
 301         REG_WR(bp,  addr + 4, U64_HI(mapping));
 302 }
 303
 304 static void storm_memset_spq_addr(struct bnx2x *bp,
 305                                   dma_addr_t mapping, u16 abs_fid)
 306 {
 307         u32 addr = XSEM_REG_FAST_MEMORY +
 308                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 309
 310         __storm_memset_dma_mapping(bp, addr, mapping);
 311 }
 312
 313 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 314                                   u16 pf_id)
 315 {
 316         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 317                 pf_id);
 318         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 319                 pf_id);
 320         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 321                 pf_id);
 322         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 323                 pf_id);
 324 }
 325
 326 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 327                                  u8 enable)
 328 {
 329         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 330                 enable);
 331         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 332                 enable);
 333         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 334                 enable);
 335         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 336                 enable);
 337 }
 338
 339 static void storm_memset_eq_data(struct bnx2x *bp,
 340                                  struct event_ring_data *eq_data,
 341                                 u16 pfid)
 342 {
 343         size_t size = sizeof(struct event_ring_data);
 344
 345         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 346
 347         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 348 }
 349
 350 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 351                                  u16 pfid)
 352 {
 353         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 354         REG_WR16(bp, addr, eq_prod);
 355 }
 356
 357 /* used only at init
 358  * locking is done by mcp
 359  */
 360 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 361 {
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 364         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 365                                PCICFG_VENDOR_ID_OFFSET);
 366 }
 367
 368 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 369 {
 370         u32 val;
 371
 372         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 373         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 374         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 375                                PCICFG_VENDOR_ID_OFFSET);
 376
 377         return val;
 378 }
 379
 380 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 381 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 382 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 383 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 384 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 385
 386 static void bnx2x_dp_dmae(struct bnx2x *bp,
 387                           struct dmae_command *dmae, int msglvl)
 388 {
 389         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 390         int i;
 391
 392         switch (dmae->opcode & DMAE_COMMAND_DST) {
 393         case DMAE_CMD_DST_PCI:
 394                 if (src_type == DMAE_CMD_SRC_PCI)
 395                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 396                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 397                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 398                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 399                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 400                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 401                            dmae->comp_val);
 402                 else
 403                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 404                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 405                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 406                            dmae->opcode, dmae->src_addr_lo >> 2,
 407                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 408                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 409                            dmae->comp_val);
 410                 break;
 411         case DMAE_CMD_DST_GRC:
 412                 if (src_type == DMAE_CMD_SRC_PCI)
 413                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 414                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 415                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 416                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 417                            dmae->len, dmae->dst_addr_lo >> 2,
 418                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 419                            dmae->comp_val);
 420                 else
 421                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 422                            "src [%08x], len [%d*4], dst [%08x]\n"
 423                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 424                            dmae->opcode, dmae->src_addr_lo >> 2,
 425                            dmae->len, dmae->dst_addr_lo >> 2,
 426                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 427                            dmae->comp_val);
 428                 break;
 429         default:
 430                 if (src_type == DMAE_CMD_SRC_PCI)
 431                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 432                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 433                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 434                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 435                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 436                            dmae->comp_val);
 437                 else
 438                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 439                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 440                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 441                            dmae->opcode, dmae->src_addr_lo >> 2,
 442                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 443                            dmae->comp_val);
 444                 break;
 445         }
 446
 447         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 448                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 449                    i, *(((u32 *)dmae) + i));
 450 }
 451
 452 /* copy command into DMAE command memory and set DMAE command go */
 453 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 454 {
 455         u32 cmd_offset;
 456         int i;
 457
 458         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 459         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 460                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 461         }
 462         REG_WR(bp, dmae_reg_go_c[idx], 1);
 463 }
 464
 465 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 466 {
 467         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 468                            DMAE_CMD_C_ENABLE);
 469 }
 470
 471 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 472 {
 473         return opcode & ~DMAE_CMD_SRC_RESET;
 474 }
 475
 476 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 477                              bool with_comp, u8 comp_type)
 478 {
 479         u32 opcode = 0;
 480
 481         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 482                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 483
 484         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 485
 486         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 487         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 488                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 489         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 490
 491 #ifdef __BIG_ENDIAN
 492         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 493 #else
 494         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 495 #endif
 496         if (with_comp)
 497                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 498         return opcode;
 499 }
 500
 501 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 502                                       struct dmae_command *dmae,
 503                                       u8 src_type, u8 dst_type)
 504 {
 505         memset(dmae, 0, sizeof(struct dmae_command));
 506
 507         /* set the opcode */
 508         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 509                                          true, DMAE_COMP_PCI);
 510
 511         /* fill in the completion parameters */
 512         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 513         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 514         dmae->comp_val = DMAE_COMP_VAL;
 515 }
 516
 517 /* issue a dmae command over the init-channel and wait for completion */
 518 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 519                                u32 *comp)
 520 {
 521         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 522         int rc = 0;
 523
 524         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 525
 526         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 527          * as long as this code is called both from syscall context and
 528          * from ndo_set_rx_mode() flow that may be called from BH.
 529          */
 530
 531         spin_lock_bh(&bp->dmae_lock);
 532
 533         /* reset completion */
 534         *comp = 0;
 535
 536         /* post the command on the channel used for initializations */
 537         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 538
 539         /* wait for completion */
 540         udelay(5);
 541         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 542
 543                 if (!cnt ||
 544                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 545                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 546                         BNX2X_ERR("DMAE timeout!\n");
 547                         rc = DMAE_TIMEOUT;
 548                         goto unlock;
 549                 }
 550                 cnt--;
 551                 udelay(50);
 552         }
 553         if (*comp & DMAE_PCI_ERR_FLAG) {
 554                 BNX2X_ERR("DMAE PCI error!\n");
 555                 rc = DMAE_PCI_ERROR;
 556         }
 557
 558 unlock:
 559
 560         spin_unlock_bh(&bp->dmae_lock);
 561
 562         return rc;
 563 }
 564
 565 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 566                       u32 len32)
 567 {
 568         int rc;
 569         struct dmae_command dmae;
 570
 571         if (!bp->dmae_ready) {
 572                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 573
 574                 if (CHIP_IS_E1(bp))
 575                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 576                 else
 577                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 578                 return;
 579         }
 580
 581         /* set opcode and fixed command fields */
 582         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 583
 584         /* fill in addresses and len */
 585         dmae.src_addr_lo = U64_LO(dma_addr);
 586         dmae.src_addr_hi = U64_HI(dma_addr);
 587         dmae.dst_addr_lo = dst_addr >> 2;
 588         dmae.dst_addr_hi = 0;
 589         dmae.len = len32;
 590
 591         /* issue the command and wait for completion */
 592         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 593         if (rc) {
 594                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 595 #ifdef BNX2X_STOP_ON_ERROR
 596                 bnx2x_panic();
 597 #endif
 598         }
 599 }
 600
 601 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 602 {
 603         int rc;
 604         struct dmae_command dmae;
 605
 606         if (!bp->dmae_ready) {
 607                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 608                 int i;
 609
 610                 if (CHIP_IS_E1(bp))
 611                         for (i = 0; i < len32; i++)
 612                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 613                 else
 614                         for (i = 0; i < len32; i++)
 615                                 data[i] = REG_RD(bp, src_addr + i*4);
 616
 617                 return;
 618         }
 619
 620         /* set opcode and fixed command fields */
 621         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 622
 623         /* fill in addresses and len */
 624         dmae.src_addr_lo = src_addr >> 2;
 625         dmae.src_addr_hi = 0;
 626         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 627         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 628         dmae.len = len32;
 629
 630         /* issue the command and wait for completion */
 631         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 632         if (rc) {
 633                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 634 #ifdef BNX2X_STOP_ON_ERROR
 635                 bnx2x_panic();
 636 #endif
 637         }
 638 }
 639
 640 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 641                                       u32 addr, u32 len)
 642 {
 643         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 644         int offset = 0;
 645
 646         while (len > dmae_wr_max) {
 647                 bnx2x_write_dmae(bp, phys_addr + offset,
 648                                  addr + offset, dmae_wr_max);
 649                 offset += dmae_wr_max * 4;
 650                 len -= dmae_wr_max;
 651         }
 652
 653         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 654 }
 655
 656 enum storms {
 657            XSTORM,
 658            TSTORM,
 659            CSTORM,
 660            USTORM,
 661            MAX_STORMS
 662 };
 663
 664 #define STORMS_NUM 4
 665 #define REGS_IN_ENTRY 4
 666
 667 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 668                                               enum storms storm,
 669                                               int entry)
 670 {
 671         switch (storm) {
 672         case XSTORM:
 673                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 674         case TSTORM:
 675                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 676         case CSTORM:
 677                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 678         case USTORM:
 679                 return USTORM_ASSERT_LIST_OFFSET(entry);
 680         case MAX_STORMS:
 681         default:
 682                 BNX2X_ERR("unknown storm\n");
 683         }
 684         return -EINVAL;
 685 }
 686
 687 static int bnx2x_mc_assert(struct bnx2x *bp)
 688 {
 689         char last_idx;
 690         int i, j, rc = 0;
 691         enum storms storm;
 692         u32 regs[REGS_IN_ENTRY];
 693         u32 bar_storm_intmem[STORMS_NUM] = {
 694                 BAR_XSTRORM_INTMEM,
 695                 BAR_TSTRORM_INTMEM,
 696                 BAR_CSTRORM_INTMEM,
 697                 BAR_USTRORM_INTMEM
 698         };
 699         u32 storm_assert_list_index[STORMS_NUM] = {
 700                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 703                 USTORM_ASSERT_LIST_INDEX_OFFSET
 704         };
 705         char *storms_string[STORMS_NUM] = {
 706                 "XSTORM",
 707                 "TSTORM",
 708                 "CSTORM",
 709                 "USTORM"
 710         };
 711
 712         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 713                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 714                                    storm_assert_list_index[storm]);
 715                 if (last_idx)
 716                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 717                                   storms_string[storm], last_idx);
 718
 719                 /* print the asserts */
 720                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 721                         /* read a single assert entry */
 722                         for (j = 0; j < REGS_IN_ENTRY; j++)
 723                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 724                                           bnx2x_get_assert_list_entry(bp,
 725                                                                       storm,
 726                                                                       i) +
 727                                           sizeof(u32) * j);
 728
 729                         /* log entry if it contains a valid assert */
 730                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 731                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 732                                           storms_string[storm], i, regs[3],
 733                                           regs[2], regs[1], regs[0]);
 734                                 rc++;
 735                         } else {
 736                                 break;
 737                         }
 738                 }
 739         }
 740
 741         BNX2X_ERR("Chip Revision: %s, /*(DEBLOBBED)*/\n",
 742                   CHIP_IS_E1(bp) ? "everest1" :
 743                   CHIP_IS_E1H(bp) ? "everest1h" :
 744                   CHIP_IS_E2(bp) ? "everest2" : "everest3"/*(DEBLOBBED)*/);
 745
 746         return rc;
 747 }
 748
 749 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 750 #define SCRATCH_BUFFER_SIZE(bp) \
 751         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 752
 753 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 754 {
 755         u32 addr, val;
 756         u32 mark, offset;
 757         __be32 data[9];
 758         int word;
 759         u32 trace_shmem_base;
 760         if (BP_NOMCP(bp)) {
 761                 BNX2X_ERR("NO MCP - can not dump\n");
 762                 return;
 763         }
 764         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 765                 (bp->common.bc_ver & 0xff0000) >> 16,
 766                 (bp->common.bc_ver & 0xff00) >> 8,
 767                 (bp->common.bc_ver & 0xff));
 768
 769         if (pci_channel_offline(bp->pdev)) {
 770                 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
 771                 return;
 772         }
 773
 774         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 775         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 776                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 777
 778         if (BP_PATH(bp) == 0)
 779                 trace_shmem_base = bp->common.shmem_base;
 780         else
 781                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 782
 783         /* sanity */
 784         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 785             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 786                                 SCRATCH_BUFFER_SIZE(bp)) {
 787                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 788                           trace_shmem_base);
 789                 return;
 790         }
 791
 792         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 793
 794         /* validate TRCB signature */
 795         mark = REG_RD(bp, addr);
 796         if (mark != MFW_TRACE_SIGNATURE) {
 797                 BNX2X_ERR("Trace buffer signature is missing.");
 798                 return ;
 799         }
 800
 801         /* read cyclic buffer pointer */
 802         addr += 4;
 803         mark = REG_RD(bp, addr);
 804         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 805         if (mark >= trace_shmem_base || mark < addr + 4) {
 806                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 807                 return;
 808         }
 809         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 810
 811         printk("%s", lvl);
 812
 813         /* dump buffer after the mark */
 814         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 815                 for (word = 0; word < 8; word++)
 816                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 817                 data[8] = 0x0;
 818                 pr_cont("%s", (char *)data);
 819         }
 820
 821         /* dump buffer before the mark */
 822         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 823                 for (word = 0; word < 8; word++)
 824                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 825                 data[8] = 0x0;
 826                 pr_cont("%s", (char *)data);
 827         }
 828         printk("%s" "end of fw dump\n", lvl);
 829 }
 830
 831 static void bnx2x_fw_dump(struct bnx2x *bp)
 832 {
 833         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 834 }
 835
 836 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 837 {
 838         int port = BP_PORT(bp);
 839         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 840         u32 val = REG_RD(bp, addr);
 841
 842         /* in E1 we must use only PCI configuration space to disable
 843          * MSI/MSIX capability
 844          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 845          */
 846         if (CHIP_IS_E1(bp)) {
 847                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 848                  * Use mask register to prevent from HC sending interrupts
 849                  * after we exit the function
 850                  */
 851                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 852
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 855                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 856         } else
 857                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 858                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 859                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 860                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 861
 862         DP(NETIF_MSG_IFDOWN,
 863            "write %x to HC %d (addr 0x%x)\n",
 864            val, port, addr);
 865
 866         /* flush all outstanding writes */
 867         mmiowb();
 868
 869         REG_WR(bp, addr, val);
 870         if (REG_RD(bp, addr) != val)
 871                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 872 }
 873
 874 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 875 {
 876         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 877
 878         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 879                  IGU_PF_CONF_INT_LINE_EN |
 880                  IGU_PF_CONF_ATTN_BIT_EN);
 881
 882         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 883
 884         /* flush all outstanding writes */
 885         mmiowb();
 886
 887         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 888         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 889                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 890 }
 891
 892 static void bnx2x_int_disable(struct bnx2x *bp)
 893 {
 894         if (bp->common.int_block == INT_BLOCK_HC)
 895                 bnx2x_hc_int_disable(bp);
 896         else
 897                 bnx2x_igu_int_disable(bp);
 898 }
 899
 900 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 901 {
 902         int i;
 903         u16 j;
 904         struct hc_sp_status_block_data sp_sb_data;
 905         int func = BP_FUNC(bp);
 906 #ifdef BNX2X_STOP_ON_ERROR
 907         u16 start = 0, end = 0;
 908         u8 cos;
 909 #endif
 910         if (IS_PF(bp) && disable_int)
 911                 bnx2x_int_disable(bp);
 912
 913         bp->stats_state = STATS_STATE_DISABLED;
 914         bp->eth_stats.unrecoverable_error++;
 915         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 916
 917         BNX2X_ERR("begin crash dump -----------------\n");
 918
 919         /* Indices */
 920         /* Common */
 921         if (IS_PF(bp)) {
 922                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 923                 int data_size, cstorm_offset;
 924
 925                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 926                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 927                           bp->spq_prod_idx, bp->stats_counter);
 928                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 929                           def_sb->atten_status_block.attn_bits,
 930                           def_sb->atten_status_block.attn_bits_ack,
 931                           def_sb->atten_status_block.status_block_id,
 932                           def_sb->atten_status_block.attn_bits_index);
 933                 BNX2X_ERR("     def (");
 934                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 935                         pr_cont("0x%x%s",
 936                                 def_sb->sp_sb.index_values[i],
 937                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 938
 939                 data_size = sizeof(struct hc_sp_status_block_data) /
 940                             sizeof(u32);
 941                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 942                 for (i = 0; i < data_size; i++)
 943                         *((u32 *)&sp_sb_data + i) =
 944                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 945                                            i * sizeof(u32));
 946
 947                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 948                         sp_sb_data.igu_sb_id,
 949                         sp_sb_data.igu_seg_id,
 950                         sp_sb_data.p_func.pf_id,
 951                         sp_sb_data.p_func.vnic_id,
 952                         sp_sb_data.p_func.vf_id,
 953                         sp_sb_data.p_func.vf_valid,
 954                         sp_sb_data.state);
 955         }
 956
 957         for_each_eth_queue(bp, i) {
 958                 struct bnx2x_fastpath *fp = &bp->fp[i];
 959                 int loop;
 960                 struct hc_status_block_data_e2 sb_data_e2;
 961                 struct hc_status_block_data_e1x sb_data_e1x;
 962                 struct hc_status_block_sm  *hc_sm_p =
 963                         CHIP_IS_E1x(bp) ?
 964                         sb_data_e1x.common.state_machine :
 965                         sb_data_e2.common.state_machine;
 966                 struct hc_index_data *hc_index_p =
 967                         CHIP_IS_E1x(bp) ?
 968                         sb_data_e1x.index_data :
 969                         sb_data_e2.index_data;
 970                 u8 data_size, cos;
 971                 u32 *sb_data_p;
 972                 struct bnx2x_fp_txdata txdata;
 973
 974                 if (!bp->fp)
 975                         break;
 976
 977                 if (!fp->rx_cons_sb)
 978                         continue;
 979
 980                 /* Rx */
 981                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 982                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 983                           fp->rx_comp_prod,
 984                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 985                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 986                           fp->rx_sge_prod, fp->last_max_sge,
 987                           le16_to_cpu(fp->fp_hc_idx));
 988
 989                 /* Tx */
 990                 for_each_cos_in_tx_queue(fp, cos)
 991                 {
 992                         if (!fp->txdata_ptr[cos])
 993                                 break;
 994
 995                         txdata = *fp->txdata_ptr[cos];
 996
 997                         if (!txdata.tx_cons_sb)
 998                                 continue;
 999
1000                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1001                                   i, txdata.tx_pkt_prod,
1002                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1003                                   txdata.tx_bd_cons,
1004                                   le16_to_cpu(*txdata.tx_cons_sb));
1005                 }
1006
1007                 loop = CHIP_IS_E1x(bp) ?
1008                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1009
1010                 /* host sb data */
1011
1012                 if (IS_FCOE_FP(fp))
1013                         continue;
1014
1015                 BNX2X_ERR("     run indexes (");
1016                 for (j = 0; j < HC_SB_MAX_SM; j++)
1017                         pr_cont("0x%x%s",
1018                                fp->sb_running_index[j],
1019                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1020
1021                 BNX2X_ERR("     indexes (");
1022                 for (j = 0; j < loop; j++)
1023                         pr_cont("0x%x%s",
1024                                fp->sb_index_values[j],
1025                                (j == loop - 1) ? ")" : " ");
1026
1027                 /* VF cannot access FW refelection for status block */
1028                 if (IS_VF(bp))
1029                         continue;
1030
1031                 /* fw sb data */
1032                 data_size = CHIP_IS_E1x(bp) ?
1033                         sizeof(struct hc_status_block_data_e1x) :
1034                         sizeof(struct hc_status_block_data_e2);
1035                 data_size /= sizeof(u32);
1036                 sb_data_p = CHIP_IS_E1x(bp) ?
1037                         (u32 *)&sb_data_e1x :
1038                         (u32 *)&sb_data_e2;
1039                 /* copy sb data in here */
1040                 for (j = 0; j < data_size; j++)
1041                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1042                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1043                                 j * sizeof(u32));
1044
1045                 if (!CHIP_IS_E1x(bp)) {
1046                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1047                                 sb_data_e2.common.p_func.pf_id,
1048                                 sb_data_e2.common.p_func.vf_id,
1049                                 sb_data_e2.common.p_func.vf_valid,
1050                                 sb_data_e2.common.p_func.vnic_id,
1051                                 sb_data_e2.common.same_igu_sb_1b,
1052                                 sb_data_e2.common.state);
1053                 } else {
1054                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1055                                 sb_data_e1x.common.p_func.pf_id,
1056                                 sb_data_e1x.common.p_func.vf_id,
1057                                 sb_data_e1x.common.p_func.vf_valid,
1058                                 sb_data_e1x.common.p_func.vnic_id,
1059                                 sb_data_e1x.common.same_igu_sb_1b,
1060                                 sb_data_e1x.common.state);
1061                 }
1062
1063                 /* SB_SMs data */
1064                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1065                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1066                                 j, hc_sm_p[j].__flags,
1067                                 hc_sm_p[j].igu_sb_id,
1068                                 hc_sm_p[j].igu_seg_id,
1069                                 hc_sm_p[j].time_to_expire,
1070                                 hc_sm_p[j].timer_value);
1071                 }
1072
1073                 /* Indices data */
1074                 for (j = 0; j < loop; j++) {
1075                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1076                                hc_index_p[j].flags,
1077                                hc_index_p[j].timeout);
1078                 }
1079         }
1080
1081 #ifdef BNX2X_STOP_ON_ERROR
1082         if (IS_PF(bp)) {
1083                 /* event queue */
1084                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1085                 for (i = 0; i < NUM_EQ_DESC; i++) {
1086                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1087
1088                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1089                                   i, bp->eq_ring[i].message.opcode,
1090                                   bp->eq_ring[i].message.error);
1091                         BNX2X_ERR("data: %x %x %x\n",
1092                                   data[0], data[1], data[2]);
1093                 }
1094         }
1095
1096         /* Rings */
1097         /* Rx */
1098         for_each_valid_rx_queue(bp, i) {
1099                 struct bnx2x_fastpath *fp = &bp->fp[i];
1100
1101                 if (!bp->fp)
1102                         break;
1103
1104                 if (!fp->rx_cons_sb)
1105                         continue;
1106
1107                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1108                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1109                 for (j = start; j != end; j = RX_BD(j + 1)) {
1110                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1111                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1112
1113                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1114                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1115                 }
1116
1117                 start = RX_SGE(fp->rx_sge_prod);
1118                 end = RX_SGE(fp->last_max_sge);
1119                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1120                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1121                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1122
1123                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1124                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1125                 }
1126
1127                 start = RCQ_BD(fp->rx_comp_cons - 10);
1128                 end = RCQ_BD(fp->rx_comp_cons + 503);
1129                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1130                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1131
1132                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1133                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1134                 }
1135         }
1136
1137         /* Tx */
1138         for_each_valid_tx_queue(bp, i) {
1139                 struct bnx2x_fastpath *fp = &bp->fp[i];
1140
1141                 if (!bp->fp)
1142                         break;
1143
1144                 for_each_cos_in_tx_queue(fp, cos) {
1145                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1146
1147                         if (!fp->txdata_ptr[cos])
1148                                 break;
1149
1150                         if (!txdata->tx_cons_sb)
1151                                 continue;
1152
1153                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1154                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1155                         for (j = start; j != end; j = TX_BD(j + 1)) {
1156                                 struct sw_tx_bd *sw_bd =
1157                                         &txdata->tx_buf_ring[j];
1158
1159                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1160                                           i, cos, j, sw_bd->skb,
1161                                           sw_bd->first_bd);
1162                         }
1163
1164                         start = TX_BD(txdata->tx_bd_cons - 10);
1165                         end = TX_BD(txdata->tx_bd_cons + 254);
1166                         for (j = start; j != end; j = TX_BD(j + 1)) {
1167                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1168
1169                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1170                                           i, cos, j, tx_bd[0], tx_bd[1],
1171                                           tx_bd[2], tx_bd[3]);
1172                         }
1173                 }
1174         }
1175 #endif
1176         if (IS_PF(bp)) {
1177                 bnx2x_fw_dump(bp);
1178                 bnx2x_mc_assert(bp);
1179         }
1180         BNX2X_ERR("end crash dump -----------------\n");
1181 }
1182
1183 /*
1184  * FLR Support for E2
1185  *
1186  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1187  * initialization.
1188  */
1189 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1190 #define FLR_WAIT_INTERVAL       50      /* usec */
1191 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1192
1193 struct pbf_pN_buf_regs {
1194         int pN;
1195         u32 init_crd;
1196         u32 crd;
1197         u32 crd_freed;
1198 };
1199
1200 struct pbf_pN_cmd_regs {
1201         int pN;
1202         u32 lines_occup;
1203         u32 lines_freed;
1204 };
1205
1206 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1207                                      struct pbf_pN_buf_regs *regs,
1208                                      u32 poll_count)
1209 {
1210         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1211         u32 cur_cnt = poll_count;
1212
1213         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1214         crd = crd_start = REG_RD(bp, regs->crd);
1215         init_crd = REG_RD(bp, regs->init_crd);
1216
1217         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1218         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1219         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1220
1221         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1222                (init_crd - crd_start))) {
1223                 if (cur_cnt--) {
1224                         udelay(FLR_WAIT_INTERVAL);
1225                         crd = REG_RD(bp, regs->crd);
1226                         crd_freed = REG_RD(bp, regs->crd_freed);
1227                 } else {
1228                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1229                            regs->pN);
1230                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1231                            regs->pN, crd);
1232                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1233                            regs->pN, crd_freed);
1234                         break;
1235                 }
1236         }
1237         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1238            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1239 }
1240
1241 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1242                                      struct pbf_pN_cmd_regs *regs,
1243                                      u32 poll_count)
1244 {
1245         u32 occup, to_free, freed, freed_start;
1246         u32 cur_cnt = poll_count;
1247
1248         occup = to_free = REG_RD(bp, regs->lines_occup);
1249         freed = freed_start = REG_RD(bp, regs->lines_freed);
1250
1251         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1252         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1253
1254         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1255                 if (cur_cnt--) {
1256                         udelay(FLR_WAIT_INTERVAL);
1257                         occup = REG_RD(bp, regs->lines_occup);
1258                         freed = REG_RD(bp, regs->lines_freed);
1259                 } else {
1260                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1261                            regs->pN);
1262                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1263                            regs->pN, occup);
1264                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1265                            regs->pN, freed);
1266                         break;
1267                 }
1268         }
1269         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1270            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1271 }
1272
1273 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1274                                     u32 expected, u32 poll_count)
1275 {
1276         u32 cur_cnt = poll_count;
1277         u32 val;
1278
1279         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1280                 udelay(FLR_WAIT_INTERVAL);
1281
1282         return val;
1283 }
1284
1285 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1286                                     char *msg, u32 poll_cnt)
1287 {
1288         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1289         if (val != 0) {
1290                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1291                 return 1;
1292         }
1293         return 0;
1294 }
1295
1296 /* Common routines with VF FLR cleanup */
1297 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1298 {
1299         /* adjust polling timeout */
1300         if (CHIP_REV_IS_EMUL(bp))
1301                 return FLR_POLL_CNT * 2000;
1302
1303         if (CHIP_REV_IS_FPGA(bp))
1304                 return FLR_POLL_CNT * 120;
1305
1306         return FLR_POLL_CNT;
1307 }
1308
1309 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1310 {
1311         struct pbf_pN_cmd_regs cmd_regs[] = {
1312                 {0, (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_OCCUPANCY_Q0 :
1314                         PBF_REG_P0_TQ_OCCUPANCY,
1315                     (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1317                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1318                 {1, (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_OCCUPANCY_Q1 :
1320                         PBF_REG_P1_TQ_OCCUPANCY,
1321                     (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1323                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1324                 {4, (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1326                         PBF_REG_P4_TQ_OCCUPANCY,
1327                     (CHIP_IS_E3B0(bp)) ?
1328                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1329                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1330         };
1331
1332         struct pbf_pN_buf_regs buf_regs[] = {
1333                 {0, (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_INIT_CRD_Q0 :
1335                         PBF_REG_P0_INIT_CRD ,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_CREDIT_Q0 :
1338                         PBF_REG_P0_CREDIT,
1339                     (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1341                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1342                 {1, (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_INIT_CRD_Q1 :
1344                         PBF_REG_P1_INIT_CRD,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_CREDIT_Q1 :
1347                         PBF_REG_P1_CREDIT,
1348                     (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1350                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1351                 {4, (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_INIT_CRD_LB_Q :
1353                         PBF_REG_P4_INIT_CRD,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_CREDIT_LB_Q :
1356                         PBF_REG_P4_CREDIT,
1357                     (CHIP_IS_E3B0(bp)) ?
1358                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1359                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1360         };
1361
1362         int i;
1363
1364         /* Verify the command queues are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1366                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1367
1368         /* Verify the transmission buffers are flushed P0, P1, P4 */
1369         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1370                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1371 }
1372
1373 #define OP_GEN_PARAM(param) \
1374         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1375
1376 #define OP_GEN_TYPE(type) \
1377         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1378
1379 #define OP_GEN_AGG_VECT(index) \
1380         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1381
1382 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1383 {
1384         u32 op_gen_command = 0;
1385         u32 comp_addr = BAR_CSTRORM_INTMEM +
1386                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1387         int ret = 0;
1388
1389         if (REG_RD(bp, comp_addr)) {
1390                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1391                 return 1;
1392         }
1393
1394         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1395         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1396         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1397         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1398
1399         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1400         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1401
1402         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1403                 BNX2X_ERR("FW final cleanup did not succeed\n");
1404                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1405                    (REG_RD(bp, comp_addr)));
1406                 bnx2x_panic();
1407                 return 1;
1408         }
1409         /* Zero completion for next FLR */
1410         REG_WR(bp, comp_addr, 0);
1411
1412         return ret;
1413 }
1414
1415 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1416 {
1417         u16 status;
1418
1419         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1420         return status & PCI_EXP_DEVSTA_TRPND;
1421 }
1422
1423 /* PF FLR specific routines
1424 */
1425 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1426 {
1427         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1428         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1429                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1430                         "CFC PF usage counter timed out",
1431                         poll_cnt))
1432                 return 1;
1433
1434         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1435         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1436                         DORQ_REG_PF_USAGE_CNT,
1437                         "DQ PF usage counter timed out",
1438                         poll_cnt))
1439                 return 1;
1440
1441         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1442         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1443                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1444                         "QM PF usage counter timed out",
1445                         poll_cnt))
1446                 return 1;
1447
1448         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1449         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1450                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1451                         "Timers VNIC usage counter timed out",
1452                         poll_cnt))
1453                 return 1;
1454         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1455                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1456                         "Timers NUM_SCANS usage counter timed out",
1457                         poll_cnt))
1458                 return 1;
1459
1460         /* Wait DMAE PF usage counter to zero */
1461         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1462                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1463                         "DMAE command register timed out",
1464                         poll_cnt))
1465                 return 1;
1466
1467         return 0;
1468 }
1469
1470 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1471 {
1472         u32 val;
1473
1474         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1475         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1476
1477         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1478         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1479
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1482
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1485
1486         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1487         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1488
1489         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1491
1492         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1494
1495         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1496         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1497            val);
1498 }
1499
1500 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1501 {
1502         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1503
1504         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1505
1506         /* Re-enable PF target read access */
1507         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1508
1509         /* Poll HW usage counters */
1510         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1511         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1512                 return -EBUSY;
1513
1514         /* Zero the igu 'trailing edge' and 'leading edge' */
1515
1516         /* Send the FW cleanup command */
1517         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1518                 return -EBUSY;
1519
1520         /* ATC cleanup */
1521
1522         /* Verify TX hw is flushed */
1523         bnx2x_tx_hw_flushed(bp, poll_cnt);
1524
1525         /* Wait 100ms (not adjusted according to platform) */
1526         msleep(100);
1527
1528         /* Verify no pending pci transactions */
1529         if (bnx2x_is_pcie_pending(bp->pdev))
1530                 BNX2X_ERR("PCIE Transactions still pending\n");
1531
1532         /* Debug */
1533         bnx2x_hw_enable_status(bp);
1534
1535         /*
1536          * Master enable - Due to WB DMAE writes performed before this
1537          * register is re-initialized as part of the regular function init
1538          */
1539         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1540
1541         return 0;
1542 }
1543
1544 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1545 {
1546         int port = BP_PORT(bp);
1547         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1548         u32 val = REG_RD(bp, addr);
1549         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1550         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1551         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1552
1553         if (msix) {
1554                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1555                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1556                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1557                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1558                 if (single_msix)
1559                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1560         } else if (msi) {
1561                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1565         } else {
1566                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1567                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1568                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1569                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1570
1571                 if (!CHIP_IS_E1(bp)) {
1572                         DP(NETIF_MSG_IFUP,
1573                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1574
1575                         REG_WR(bp, addr, val);
1576
1577                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1578                 }
1579         }
1580
1581         if (CHIP_IS_E1(bp))
1582                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1583
1584         DP(NETIF_MSG_IFUP,
1585            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1586            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1587
1588         REG_WR(bp, addr, val);
1589         /*
1590          * Ensure that HC_CONFIG is written before leading/trailing edge config
1591          */
1592         mmiowb();
1593         barrier();
1594
1595         if (!CHIP_IS_E1(bp)) {
1596                 /* init leading/trailing edge */
1597                 if (IS_MF(bp)) {
1598                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1599                         if (bp->port.pmf)
1600                                 /* enable nig and gpio3 attention */
1601                                 val |= 0x1100;
1602                 } else
1603                         val = 0xffff;
1604
1605                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1606                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1607         }
1608
1609         /* Make sure that interrupts are indeed enabled from here on */
1610         mmiowb();
1611 }
1612
1613 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1614 {
1615         u32 val;
1616         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1617         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1618         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1619
1620         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1621
1622         if (msix) {
1623                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1624                          IGU_PF_CONF_SINGLE_ISR_EN);
1625                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1626                         IGU_PF_CONF_ATTN_BIT_EN);
1627
1628                 if (single_msix)
1629                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1630         } else if (msi) {
1631                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1632                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1633                         IGU_PF_CONF_ATTN_BIT_EN |
1634                         IGU_PF_CONF_SINGLE_ISR_EN);
1635         } else {
1636                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1637                 val |= (IGU_PF_CONF_INT_LINE_EN |
1638                         IGU_PF_CONF_ATTN_BIT_EN |
1639                         IGU_PF_CONF_SINGLE_ISR_EN);
1640         }
1641
1642         /* Clean previous status - need to configure igu prior to ack*/
1643         if ((!msix) || single_msix) {
1644                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1645                 bnx2x_ack_int(bp);
1646         }
1647
1648         val |= IGU_PF_CONF_FUNC_EN;
1649
1650         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1651            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1652
1653         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1654
1655         if (val & IGU_PF_CONF_INT_LINE_EN)
1656                 pci_intx(bp->pdev, true);
1657
1658         barrier();
1659
1660         /* init leading/trailing edge */
1661         if (IS_MF(bp)) {
1662                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1663                 if (bp->port.pmf)
1664                         /* enable nig and gpio3 attention */
1665                         val |= 0x1100;
1666         } else
1667                 val = 0xffff;
1668
1669         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1670         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1671
1672         /* Make sure that interrupts are indeed enabled from here on */
1673         mmiowb();
1674 }
1675
1676 void bnx2x_int_enable(struct bnx2x *bp)
1677 {
1678         if (bp->common.int_block == INT_BLOCK_HC)
1679                 bnx2x_hc_int_enable(bp);
1680         else
1681                 bnx2x_igu_int_enable(bp);
1682 }
1683
1684 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1685 {
1686         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1687         int i, offset;
1688
1689         if (disable_hw)
1690                 /* prevent the HW from sending interrupts */
1691                 bnx2x_int_disable(bp);
1692
1693         /* make sure all ISRs are done */
1694         if (msix) {
1695                 synchronize_irq(bp->msix_table[0].vector);
1696                 offset = 1;
1697                 if (CNIC_SUPPORT(bp))
1698                         offset++;
1699                 for_each_eth_queue(bp, i)
1700                         synchronize_irq(bp->msix_table[offset++].vector);
1701         } else
1702                 synchronize_irq(bp->pdev->irq);
1703
1704         /* make sure sp_task is not running */
1705         cancel_delayed_work(&bp->sp_task);
1706         cancel_delayed_work(&bp->period_task);
1707         flush_workqueue(bnx2x_wq);
1708 }
1709
1710 /* fast path */
1711
1712 /*
1713  * General service functions
1714  */
1715
1716 /* Return true if succeeded to acquire the lock */
1717 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1718 {
1719         u32 lock_status;
1720         u32 resource_bit = (1 << resource);
1721         int func = BP_FUNC(bp);
1722         u32 hw_lock_control_reg;
1723
1724         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1725            "Trying to take a lock on resource %d\n", resource);
1726
1727         /* Validating that the resource is within range */
1728         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1729                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1730                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1731                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1732                 return false;
1733         }
1734
1735         if (func <= 5)
1736                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1737         else
1738                 hw_lock_control_reg =
1739                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1740
1741         /* Try to acquire the lock */
1742         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1743         lock_status = REG_RD(bp, hw_lock_control_reg);
1744         if (lock_status & resource_bit)
1745                 return true;
1746
1747         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1748            "Failed to get a lock on resource %d\n", resource);
1749         return false;
1750 }
1751
1752 /**
1753  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1754  *
1755  * @bp: driver handle
1756  *
1757  * Returns the recovery leader resource id according to the engine this function
1758  * belongs to. Currently only only 2 engines is supported.
1759  */
1760 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1761 {
1762         if (BP_PATH(bp))
1763                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1764         else
1765                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1766 }
1767
1768 /**
1769  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1770  *
1771  * @bp: driver handle
1772  *
1773  * Tries to acquire a leader lock for current engine.
1774  */
1775 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1776 {
1777         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1778 }
1779
1780 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1781
1782 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1783 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1784 {
1785         /* Set the interrupt occurred bit for the sp-task to recognize it
1786          * must ack the interrupt and transition according to the IGU
1787          * state machine.
1788          */
1789         atomic_set(&bp->interrupt_occurred, 1);
1790
1791         /* The sp_task must execute only after this bit
1792          * is set, otherwise we will get out of sync and miss all
1793          * further interrupts. Hence, the barrier.
1794          */
1795         smp_wmb();
1796
1797         /* schedule sp_task to workqueue */
1798         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1799 }
1800
1801 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1802 {
1803         struct bnx2x *bp = fp->bp;
1804         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1805         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1806         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1807         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1808
1809         DP(BNX2X_MSG_SP,
1810            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1811            fp->index, cid, command, bp->state,
1812            rr_cqe->ramrod_cqe.ramrod_type);
1813
1814         /* If cid is within VF range, replace the slowpath object with the
1815          * one corresponding to this VF
1816          */
1817         if (cid >= BNX2X_FIRST_VF_CID  &&
1818             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1819                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1820
1821         switch (command) {
1822         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1823                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1824                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1825                 break;
1826
1827         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1828                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1829                 drv_cmd = BNX2X_Q_CMD_SETUP;
1830                 break;
1831
1832         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1833                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1834                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1835                 break;
1836
1837         case (RAMROD_CMD_ID_ETH_HALT):
1838                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1839                 drv_cmd = BNX2X_Q_CMD_HALT;
1840                 break;
1841
1842         case (RAMROD_CMD_ID_ETH_TERMINATE):
1843                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1844                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1845                 break;
1846
1847         case (RAMROD_CMD_ID_ETH_EMPTY):
1848                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1849                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1850                 break;
1851
1852         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1853                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1854                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1855                 break;
1856
1857         default:
1858                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1859                           command, fp->index);
1860                 return;
1861         }
1862
1863         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1864             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1865                 /* q_obj->complete_cmd() failure means that this was
1866                  * an unexpected completion.
1867                  *
1868                  * In this case we don't want to increase the bp->spq_left
1869                  * because apparently we haven't sent this command the first
1870                  * place.
1871                  */
1872 #ifdef BNX2X_STOP_ON_ERROR
1873                 bnx2x_panic();
1874 #else
1875                 return;
1876 #endif
1877
1878         smp_mb__before_atomic();
1879         atomic_inc(&bp->cq_spq_left);
1880         /* push the change in bp->spq_left and towards the memory */
1881         smp_mb__after_atomic();
1882
1883         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1884
1885         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1886             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1887                 /* if Q update ramrod is completed for last Q in AFEX vif set
1888                  * flow, then ACK MCP at the end
1889                  *
1890                  * mark pending ACK to MCP bit.
1891                  * prevent case that both bits are cleared.
1892                  * At the end of load/unload driver checks that
1893                  * sp_state is cleared, and this order prevents
1894                  * races
1895                  */
1896                 smp_mb__before_atomic();
1897                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1898                 wmb();
1899                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1900                 smp_mb__after_atomic();
1901
1902                 /* schedule the sp task as mcp ack is required */
1903                 bnx2x_schedule_sp_task(bp);
1904         }
1905
1906         return;
1907 }
1908
1909 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1910 {
1911         struct bnx2x *bp = netdev_priv(dev_instance);
1912         u16 status = bnx2x_ack_int(bp);
1913         u16 mask;
1914         int i;
1915         u8 cos;
1916
1917         /* Return here if interrupt is shared and it's not for us */
1918         if (unlikely(status == 0)) {
1919                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1920                 return IRQ_NONE;
1921         }
1922         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1923
1924 #ifdef BNX2X_STOP_ON_ERROR
1925         if (unlikely(bp->panic))
1926                 return IRQ_HANDLED;
1927 #endif
1928
1929         for_each_eth_queue(bp, i) {
1930                 struct bnx2x_fastpath *fp = &bp->fp[i];
1931
1932                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1933                 if (status & mask) {
1934                         /* Handle Rx or Tx according to SB id */
1935                         for_each_cos_in_tx_queue(fp, cos)
1936                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1937                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1938                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1939                         status &= ~mask;
1940                 }
1941         }
1942
1943         if (CNIC_SUPPORT(bp)) {
1944                 mask = 0x2;
1945                 if (status & (mask | 0x1)) {
1946                         struct cnic_ops *c_ops = NULL;
1947
1948                         rcu_read_lock();
1949                         c_ops = rcu_dereference(bp->cnic_ops);
1950                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1951                                       CNIC_DRV_STATE_HANDLES_IRQ))
1952                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1953                         rcu_read_unlock();
1954
1955                         status &= ~mask;
1956                 }
1957         }
1958
1959         if (unlikely(status & 0x1)) {
1960
1961                 /* schedule sp task to perform default status block work, ack
1962                  * attentions and enable interrupts.
1963                  */
1964                 bnx2x_schedule_sp_task(bp);
1965
1966                 status &= ~0x1;
1967                 if (!status)
1968                         return IRQ_HANDLED;
1969         }
1970
1971         if (unlikely(status))
1972                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1973                    status);
1974
1975         return IRQ_HANDLED;
1976 }
1977
1978 /* Link */
1979
1980 /*
1981  * General service functions
1982  */
1983
1984 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1985 {
1986         u32 lock_status;
1987         u32 resource_bit = (1 << resource);
1988         int func = BP_FUNC(bp);
1989         u32 hw_lock_control_reg;
1990         int cnt;
1991
1992         /* Validating that the resource is within range */
1993         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1994                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1995                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1996                 return -EINVAL;
1997         }
1998
1999         if (func <= 5) {
2000                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2001         } else {
2002                 hw_lock_control_reg =
2003                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2004         }
2005
2006         /* Validating that the resource is not already taken */
2007         lock_status = REG_RD(bp, hw_lock_control_reg);
2008         if (lock_status & resource_bit) {
2009                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2010                    lock_status, resource_bit);
2011                 return -EEXIST;
2012         }
2013
2014         /* Try for 5 second every 5ms */
2015         for (cnt = 0; cnt < 1000; cnt++) {
2016                 /* Try to acquire the lock */
2017                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2018                 lock_status = REG_RD(bp, hw_lock_control_reg);
2019                 if (lock_status & resource_bit)
2020                         return 0;
2021
2022                 usleep_range(5000, 10000);
2023         }
2024         BNX2X_ERR("Timeout\n");
2025         return -EAGAIN;
2026 }
2027
2028 int bnx2x_release_leader_lock(struct bnx2x *bp)
2029 {
2030         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2031 }
2032
2033 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2034 {
2035         u32 lock_status;
2036         u32 resource_bit = (1 << resource);
2037         int func = BP_FUNC(bp);
2038         u32 hw_lock_control_reg;
2039
2040         /* Validating that the resource is within range */
2041         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2042                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2043                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2044                 return -EINVAL;
2045         }
2046
2047         if (func <= 5) {
2048                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2049         } else {
2050                 hw_lock_control_reg =
2051                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2052         }
2053
2054         /* Validating that the resource is currently taken */
2055         lock_status = REG_RD(bp, hw_lock_control_reg);
2056         if (!(lock_status & resource_bit)) {
2057                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2058                           lock_status, resource_bit);
2059                 return -EFAULT;
2060         }
2061
2062         REG_WR(bp, hw_lock_control_reg, resource_bit);
2063         return 0;
2064 }
2065
2066 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2067 {
2068         /* The GPIO should be swapped if swap register is set and active */
2069         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2070                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2071         int gpio_shift = gpio_num +
2072                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2073         u32 gpio_mask = (1 << gpio_shift);
2074         u32 gpio_reg;
2075         int value;
2076
2077         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2078                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2079                 return -EINVAL;
2080         }
2081
2082         /* read GPIO value */
2083         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2084
2085         /* get the requested pin value */
2086         if ((gpio_reg & gpio_mask) == gpio_mask)
2087                 value = 1;
2088         else
2089                 value = 0;
2090
2091         return value;
2092 }
2093
2094 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2095 {
2096         /* The GPIO should be swapped if swap register is set and active */
2097         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2098                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2099         int gpio_shift = gpio_num +
2100                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2101         u32 gpio_mask = (1 << gpio_shift);
2102         u32 gpio_reg;
2103
2104         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2105                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2106                 return -EINVAL;
2107         }
2108
2109         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2110         /* read GPIO and mask except the float bits */
2111         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2112
2113         switch (mode) {
2114         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2115                 DP(NETIF_MSG_LINK,
2116                    "Set GPIO %d (shift %d) -> output low\n",
2117                    gpio_num, gpio_shift);
2118                 /* clear FLOAT and set CLR */
2119                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2120                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2121                 break;
2122
2123         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2124                 DP(NETIF_MSG_LINK,
2125                    "Set GPIO %d (shift %d) -> output high\n",
2126                    gpio_num, gpio_shift);
2127                 /* clear FLOAT and set SET */
2128                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2129                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2130                 break;
2131
2132         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2133                 DP(NETIF_MSG_LINK,
2134                    "Set GPIO %d (shift %d) -> input\n",
2135                    gpio_num, gpio_shift);
2136                 /* set FLOAT */
2137                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2138                 break;
2139
2140         default:
2141                 break;
2142         }
2143
2144         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2145         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2146
2147         return 0;
2148 }
2149
2150 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2151 {
2152         u32 gpio_reg = 0;
2153         int rc = 0;
2154
2155         /* Any port swapping should be handled by caller. */
2156
2157         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2158         /* read GPIO and mask except the float bits */
2159         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2160         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2161         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2162         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2163
2164         switch (mode) {
2165         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2166                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2167                 /* set CLR */
2168                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2169                 break;
2170
2171         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2172                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2173                 /* set SET */
2174                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2175                 break;
2176
2177         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2178                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2179                 /* set FLOAT */
2180                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2181                 break;
2182
2183         default:
2184                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2185                 rc = -EINVAL;
2186                 break;
2187         }
2188
2189         if (rc == 0)
2190                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2191
2192         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2193
2194         return rc;
2195 }
2196
2197 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2198 {
2199         /* The GPIO should be swapped if swap register is set and active */
2200         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2201                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2202         int gpio_shift = gpio_num +
2203                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2204         u32 gpio_mask = (1 << gpio_shift);
2205         u32 gpio_reg;
2206
2207         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2208                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2209                 return -EINVAL;
2210         }
2211
2212         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2213         /* read GPIO int */
2214         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2215
2216         switch (mode) {
2217         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2218                 DP(NETIF_MSG_LINK,
2219                    "Clear GPIO INT %d (shift %d) -> output low\n",
2220                    gpio_num, gpio_shift);
2221                 /* clear SET and set CLR */
2222                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2223                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2224                 break;
2225
2226         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2227                 DP(NETIF_MSG_LINK,
2228                    "Set GPIO INT %d (shift %d) -> output high\n",
2229                    gpio_num, gpio_shift);
2230                 /* clear CLR and set SET */
2231                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2232                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2233                 break;
2234
2235         default:
2236                 break;
2237         }
2238
2239         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2240         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2241
2242         return 0;
2243 }
2244
2245 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2246 {
2247         u32 spio_reg;
2248
2249         /* Only 2 SPIOs are configurable */
2250         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2251                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2252                 return -EINVAL;
2253         }
2254
2255         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2256         /* read SPIO and mask except the float bits */
2257         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2258
2259         switch (mode) {
2260         case MISC_SPIO_OUTPUT_LOW:
2261                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2262                 /* clear FLOAT and set CLR */
2263                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2264                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2265                 break;
2266
2267         case MISC_SPIO_OUTPUT_HIGH:
2268                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2269                 /* clear FLOAT and set SET */
2270                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2271                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2272                 break;
2273
2274         case MISC_SPIO_INPUT_HI_Z:
2275                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2276                 /* set FLOAT */
2277                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2278                 break;
2279
2280         default:
2281                 break;
2282         }
2283
2284         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2285         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2286
2287         return 0;
2288 }
2289
2290 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2291 {
2292         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2293
2294         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2295                                            ADVERTISED_Pause);
2296         switch (bp->link_vars.ieee_fc &
2297                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2298         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2299                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2300                                                   ADVERTISED_Pause);
2301                 break;
2302
2303         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2304                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2305                 break;
2306
2307         default:
2308                 break;
2309         }
2310 }
2311
2312 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2313 {
2314         /* Initialize link parameters structure variables
2315          * It is recommended to turn off RX FC for jumbo frames
2316          *  for better performance
2317          */
2318         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320         else
2321                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2322 }
2323
2324 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325 {
2326         u32 pause_enabled = 0;
2327
2328         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2330                         pause_enabled = 1;
2331
2332                 REG_WR(bp, BAR_USTRORM_INTMEM +
2333                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334                        pause_enabled);
2335         }
2336
2337         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338            pause_enabled ? "enabled" : "disabled");
2339 }
2340
2341 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342 {
2343         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345
2346         if (!BP_NOMCP(bp)) {
2347                 bnx2x_set_requested_fc(bp);
2348                 bnx2x_acquire_phy_lock(bp);
2349
2350                 if (load_mode == LOAD_DIAG) {
2351                         struct link_params *lp = &bp->link_params;
2352                         lp->loopback_mode = LOOPBACK_XGXS;
2353                         /* Prefer doing PHY loopback at highest speed */
2354                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2355                                 if (lp->speed_cap_mask[cfx_idx] &
2356                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2357                                         lp->req_line_speed[cfx_idx] =
2358                                         SPEED_20000;
2359                                 else if (lp->speed_cap_mask[cfx_idx] &
2360                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2361                                                 lp->req_line_speed[cfx_idx] =
2362                                                 SPEED_10000;
2363                                 else
2364                                         lp->req_line_speed[cfx_idx] =
2365                                         SPEED_1000;
2366                         }
2367                 }
2368
2369                 if (load_mode == LOAD_LOOPBACK_EXT) {
2370                         struct link_params *lp = &bp->link_params;
2371                         lp->loopback_mode = LOOPBACK_EXT;
2372                 }
2373
2374                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2375
2376                 bnx2x_release_phy_lock(bp);
2377
2378                 bnx2x_init_dropless_fc(bp);
2379
2380                 bnx2x_calc_fc_adv(bp);
2381
2382                 if (bp->link_vars.link_up) {
2383                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2384                         bnx2x_link_report(bp);
2385                 }
2386                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2387                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2388                 return rc;
2389         }
2390         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2391         return -EINVAL;
2392 }
2393
2394 void bnx2x_link_set(struct bnx2x *bp)
2395 {
2396         if (!BP_NOMCP(bp)) {
2397                 bnx2x_acquire_phy_lock(bp);
2398                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2399                 bnx2x_release_phy_lock(bp);
2400
2401                 bnx2x_init_dropless_fc(bp);
2402
2403                 bnx2x_calc_fc_adv(bp);
2404         } else
2405                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2406 }
2407
2408 static void bnx2x__link_reset(struct bnx2x *bp)
2409 {
2410         if (!BP_NOMCP(bp)) {
2411                 bnx2x_acquire_phy_lock(bp);
2412                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2413                 bnx2x_release_phy_lock(bp);
2414         } else
2415                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2416 }
2417
2418 void bnx2x_force_link_reset(struct bnx2x *bp)
2419 {
2420         bnx2x_acquire_phy_lock(bp);
2421         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2422         bnx2x_release_phy_lock(bp);
2423 }
2424
2425 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2426 {
2427         u8 rc = 0;
2428
2429         if (!BP_NOMCP(bp)) {
2430                 bnx2x_acquire_phy_lock(bp);
2431                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2432                                      is_serdes);
2433                 bnx2x_release_phy_lock(bp);
2434         } else
2435                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2436
2437         return rc;
2438 }
2439
2440 /* Calculates the sum of vn_min_rates.
2441    It's needed for further normalizing of the min_rates.
2442    Returns:
2443      sum of vn_min_rates.
2444        or
2445      0 - if all the min_rates are 0.
2446      In the later case fairness algorithm should be deactivated.
2447      If not all min_rates are zero then those that are zeroes will be set to 1.
2448  */
2449 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2450                                       struct cmng_init_input *input)
2451 {
2452         int all_zero = 1;
2453         int vn;
2454
2455         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2456                 u32 vn_cfg = bp->mf_config[vn];
2457                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2458                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2459
2460                 /* Skip hidden vns */
2461                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2462                         vn_min_rate = 0;
2463                 /* If min rate is zero - set it to 1 */
2464                 else if (!vn_min_rate)
2465                         vn_min_rate = DEF_MIN_RATE;
2466                 else
2467                         all_zero = 0;
2468
2469                 input->vnic_min_rate[vn] = vn_min_rate;
2470         }
2471
2472         /* if ETS or all min rates are zeros - disable fairness */
2473         if (BNX2X_IS_ETS_ENABLED(bp)) {
2474                 input->flags.cmng_enables &=
2475                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2477         } else if (all_zero) {
2478                 input->flags.cmng_enables &=
2479                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2480                 DP(NETIF_MSG_IFUP,
2481                    "All MIN values are zeroes fairness will be disabled\n");
2482         } else
2483                 input->flags.cmng_enables |=
2484                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2485 }
2486
2487 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2488                                     struct cmng_init_input *input)
2489 {
2490         u16 vn_max_rate;
2491         u32 vn_cfg = bp->mf_config[vn];
2492
2493         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2494                 vn_max_rate = 0;
2495         else {
2496                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2497
2498                 if (IS_MF_PERCENT_BW(bp)) {
2499                         /* maxCfg in percents of linkspeed */
2500                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2501                 } else /* SD modes */
2502                         /* maxCfg is absolute in 100Mb units */
2503                         vn_max_rate = maxCfg * 100;
2504         }
2505
2506         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2507
2508         input->vnic_max_rate[vn] = vn_max_rate;
2509 }
2510
2511 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2512 {
2513         if (CHIP_REV_IS_SLOW(bp))
2514                 return CMNG_FNS_NONE;
2515         if (IS_MF(bp))
2516                 return CMNG_FNS_MINMAX;
2517
2518         return CMNG_FNS_NONE;
2519 }
2520
2521 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2522 {
2523         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2524
2525         if (BP_NOMCP(bp))
2526                 return; /* what should be the default value in this case */
2527
2528         /* For 2 port configuration the absolute function number formula
2529          * is:
2530          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2531          *
2532          *      and there are 4 functions per port
2533          *
2534          * For 4 port configuration it is
2535          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2536          *
2537          *      and there are 2 functions per port
2538          */
2539         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2540                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2541
2542                 if (func >= E1H_FUNC_MAX)
2543                         break;
2544
2545                 bp->mf_config[vn] =
2546                         MF_CFG_RD(bp, func_mf_config[func].config);
2547         }
2548         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2549                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2550                 bp->flags |= MF_FUNC_DIS;
2551         } else {
2552                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2553                 bp->flags &= ~MF_FUNC_DIS;
2554         }
2555 }
2556
2557 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2558 {
2559         struct cmng_init_input input;
2560         memset(&input, 0, sizeof(struct cmng_init_input));
2561
2562         input.port_rate = bp->link_vars.line_speed;
2563
2564         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2565                 int vn;
2566
2567                 /* read mf conf from shmem */
2568                 if (read_cfg)
2569                         bnx2x_read_mf_cfg(bp);
2570
2571                 /* vn_weight_sum and enable fairness if not 0 */
2572                 bnx2x_calc_vn_min(bp, &input);
2573
2574                 /* calculate and set min-max rate for each vn */
2575                 if (bp->port.pmf)
2576                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2577                                 bnx2x_calc_vn_max(bp, vn, &input);
2578
2579                 /* always enable rate shaping and fairness */
2580                 input.flags.cmng_enables |=
2581                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2582
2583                 bnx2x_init_cmng(&input, &bp->cmng);
2584                 return;
2585         }
2586
2587         /* rate shaping and fairness are disabled */
2588         DP(NETIF_MSG_IFUP,
2589            "rate shaping and fairness are disabled\n");
2590 }
2591
2592 static void storm_memset_cmng(struct bnx2x *bp,
2593                               struct cmng_init *cmng,
2594                               u8 port)
2595 {
2596         int vn;
2597         size_t size = sizeof(struct cmng_struct_per_port);
2598
2599         u32 addr = BAR_XSTRORM_INTMEM +
2600                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2601
2602         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2603
2604         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2605                 int func = func_by_vn(bp, vn);
2606
2607                 addr = BAR_XSTRORM_INTMEM +
2608                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2609                 size = sizeof(struct rate_shaping_vars_per_vn);
2610                 __storm_memset_struct(bp, addr, size,
2611                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2612
2613                 addr = BAR_XSTRORM_INTMEM +
2614                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2615                 size = sizeof(struct fairness_vars_per_vn);
2616                 __storm_memset_struct(bp, addr, size,
2617                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2618         }
2619 }
2620
2621 /* init cmng mode in HW according to local configuration */
2622 void bnx2x_set_local_cmng(struct bnx2x *bp)
2623 {
2624         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2625
2626         if (cmng_fns != CMNG_FNS_NONE) {
2627                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2628                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2629         } else {
2630                 /* rate shaping and fairness are disabled */
2631                 DP(NETIF_MSG_IFUP,
2632                    "single function mode without fairness\n");
2633         }
2634 }
2635
2636 /* This function is called upon link interrupt */
2637 static void bnx2x_link_attn(struct bnx2x *bp)
2638 {
2639         /* Make sure that we are synced with the current statistics */
2640         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2641
2642         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2643
2644         bnx2x_init_dropless_fc(bp);
2645
2646         if (bp->link_vars.link_up) {
2647
2648                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2649                         struct host_port_stats *pstats;
2650
2651                         pstats = bnx2x_sp(bp, port_stats);
2652                         /* reset old mac stats */
2653                         memset(&(pstats->mac_stx[0]), 0,
2654                                sizeof(struct mac_stx));
2655                 }
2656                 if (bp->state == BNX2X_STATE_OPEN)
2657                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2658         }
2659
2660         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2661                 bnx2x_set_local_cmng(bp);
2662
2663         __bnx2x_link_report(bp);
2664
2665         if (IS_MF(bp))
2666                 bnx2x_link_sync_notify(bp);
2667 }
2668
2669 void bnx2x__link_status_update(struct bnx2x *bp)
2670 {
2671         if (bp->state != BNX2X_STATE_OPEN)
2672                 return;
2673
2674         /* read updated dcb configuration */
2675         if (IS_PF(bp)) {
2676                 bnx2x_dcbx_pmf_update(bp);
2677                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2678                 if (bp->link_vars.link_up)
2679                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2680                 else
2681                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2682                         /* indicate link status */
2683                 bnx2x_link_report(bp);
2684
2685         } else { /* VF */
2686                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2687                                           SUPPORTED_10baseT_Full |
2688                                           SUPPORTED_100baseT_Half |
2689                                           SUPPORTED_100baseT_Full |
2690                                           SUPPORTED_1000baseT_Full |
2691                                           SUPPORTED_2500baseX_Full |
2692                                           SUPPORTED_10000baseT_Full |
2693                                           SUPPORTED_TP |
2694                                           SUPPORTED_FIBRE |
2695                                           SUPPORTED_Autoneg |
2696                                           SUPPORTED_Pause |
2697                                           SUPPORTED_Asym_Pause);
2698                 bp->port.advertising[0] = bp->port.supported[0];
2699
2700                 bp->link_params.bp = bp;
2701                 bp->link_params.port = BP_PORT(bp);
2702                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2703                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2704                 bp->link_params.req_line_speed[0] = SPEED_10000;
2705                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2706                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2707                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2708                 bp->link_vars.line_speed = SPEED_10000;
2709                 bp->link_vars.link_status =
2710                         (LINK_STATUS_LINK_UP |
2711                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2712                 bp->link_vars.link_up = 1;
2713                 bp->link_vars.duplex = DUPLEX_FULL;
2714                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2715                 __bnx2x_link_report(bp);
2716
2717                 bnx2x_sample_bulletin(bp);
2718
2719                 /* if bulletin board did not have an update for link status
2720                  * __bnx2x_link_report will report current status
2721                  * but it will NOT duplicate report in case of already reported
2722                  * during sampling bulletin board.
2723                  */
2724                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2725         }
2726 }
2727
2728 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2729                                   u16 vlan_val, u8 allowed_prio)
2730 {
2731         struct bnx2x_func_state_params func_params = {NULL};
2732         struct bnx2x_func_afex_update_params *f_update_params =
2733                 &func_params.params.afex_update;
2734
2735         func_params.f_obj = &bp->func_obj;
2736         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2737
2738         /* no need to wait for RAMROD completion, so don't
2739          * set RAMROD_COMP_WAIT flag
2740          */
2741
2742         f_update_params->vif_id = vifid;
2743         f_update_params->afex_default_vlan = vlan_val;
2744         f_update_params->allowed_priorities = allowed_prio;
2745
2746         /* if ramrod can not be sent, response to MCP immediately */
2747         if (bnx2x_func_state_change(bp, &func_params) < 0)
2748                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2749
2750         return 0;
2751 }
2752
2753 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2754                                           u16 vif_index, u8 func_bit_map)
2755 {
2756         struct bnx2x_func_state_params func_params = {NULL};
2757         struct bnx2x_func_afex_viflists_params *update_params =
2758                 &func_params.params.afex_viflists;
2759         int rc;
2760         u32 drv_msg_code;
2761
2762         /* validate only LIST_SET and LIST_GET are received from switch */
2763         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2764                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2765                           cmd_type);
2766
2767         func_params.f_obj = &bp->func_obj;
2768         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2769
2770         /* set parameters according to cmd_type */
2771         update_params->afex_vif_list_command = cmd_type;
2772         update_params->vif_list_index = vif_index;
2773         update_params->func_bit_map =
2774                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2775         update_params->func_to_clear = 0;
2776         drv_msg_code =
2777                 (cmd_type == VIF_LIST_RULE_GET) ?
2778                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2779                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2780
2781         /* if ramrod can not be sent, respond to MCP immediately for
2782          * SET and GET requests (other are not triggered from MCP)
2783          */
2784         rc = bnx2x_func_state_change(bp, &func_params);
2785         if (rc < 0)
2786                 bnx2x_fw_command(bp, drv_msg_code, 0);
2787
2788         return 0;
2789 }
2790
2791 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2792 {
2793         struct afex_stats afex_stats;
2794         u32 func = BP_ABS_FUNC(bp);
2795         u32 mf_config;
2796         u16 vlan_val;
2797         u32 vlan_prio;
2798         u16 vif_id;
2799         u8 allowed_prio;
2800         u8 vlan_mode;
2801         u32 addr_to_write, vifid, addrs, stats_type, i;
2802
2803         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2804                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2805                 DP(BNX2X_MSG_MCP,
2806                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2807                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2808         }
2809
2810         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2811                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2812                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2813                 DP(BNX2X_MSG_MCP,
2814                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2815                    vifid, addrs);
2816                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2817                                                addrs);
2818         }
2819
2820         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2821                 addr_to_write = SHMEM2_RD(bp,
2822                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2823                 stats_type = SHMEM2_RD(bp,
2824                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2825
2826                 DP(BNX2X_MSG_MCP,
2827                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2828                    addr_to_write);
2829
2830                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2831
2832                 /* write response to scratchpad, for MCP */
2833                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2834                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2835                                *(((u32 *)(&afex_stats))+i));
2836
2837                 /* send ack message to MCP */
2838                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2839         }
2840
2841         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2842                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2843                 bp->mf_config[BP_VN(bp)] = mf_config;
2844                 DP(BNX2X_MSG_MCP,
2845                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2846                    mf_config);
2847
2848                 /* if VIF_SET is "enabled" */
2849                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2850                         /* set rate limit directly to internal RAM */
2851                         struct cmng_init_input cmng_input;
2852                         struct rate_shaping_vars_per_vn m_rs_vn;
2853                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2854                         u32 addr = BAR_XSTRORM_INTMEM +
2855                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2856
2857                         bp->mf_config[BP_VN(bp)] = mf_config;
2858
2859                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2860                         m_rs_vn.vn_counter.rate =
2861                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2862                         m_rs_vn.vn_counter.quota =
2863                                 (m_rs_vn.vn_counter.rate *
2864                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2865
2866                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2867
2868                         /* read relevant values from mf_cfg struct in shmem */
2869                         vif_id =
2870                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2872                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2873                         vlan_val =
2874                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2875                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2876                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2877                         vlan_prio = (mf_config &
2878                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2879                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2880                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2881                         vlan_mode =
2882                                 (MF_CFG_RD(bp,
2883                                            func_mf_config[func].afex_config) &
2884                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2885                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2886                         allowed_prio =
2887                                 (MF_CFG_RD(bp,
2888                                            func_mf_config[func].afex_config) &
2889                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2890                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2891
2892                         /* send ramrod to FW, return in case of failure */
2893                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2894                                                    allowed_prio))
2895                                 return;
2896
2897                         bp->afex_def_vlan_tag = vlan_val;
2898                         bp->afex_vlan_mode = vlan_mode;
2899                 } else {
2900                         /* notify link down because BP->flags is disabled */
2901                         bnx2x_link_report(bp);
2902
2903                         /* send INVALID VIF ramrod to FW */
2904                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2905
2906                         /* Reset the default afex VLAN */
2907                         bp->afex_def_vlan_tag = -1;
2908                 }
2909         }
2910 }
2911
2912 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2913 {
2914         struct bnx2x_func_switch_update_params *switch_update_params;
2915         struct bnx2x_func_state_params func_params;
2916
2917         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2918         switch_update_params = &func_params.params.switch_update;
2919         func_params.f_obj = &bp->func_obj;
2920         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2921
2922         /* Prepare parameters for function state transitions */
2923         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2924         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
2925
2926         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2927                 int func = BP_ABS_FUNC(bp);
2928                 u32 val;
2929
2930                 /* Re-learn the S-tag from shmem */
2931                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2932                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2933                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2934                         bp->mf_ov = val;
2935                 } else {
2936                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2937                         goto fail;
2938                 }
2939
2940                 /* Configure new S-tag in LLH */
2941                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2942                        bp->mf_ov);
2943
2944                 /* Send Ramrod to update FW of change */
2945                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2946                           &switch_update_params->changes);
2947                 switch_update_params->vlan = bp->mf_ov;
2948
2949                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2950                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2951                                   bp->mf_ov);
2952                         goto fail;
2953                 } else {
2954                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2955                            bp->mf_ov);
2956                 }
2957         } else {
2958                 goto fail;
2959         }
2960
2961         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2962         return;
2963 fail:
2964         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2965 }
2966
2967 static void bnx2x_pmf_update(struct bnx2x *bp)
2968 {
2969         int port = BP_PORT(bp);
2970         u32 val;
2971
2972         bp->port.pmf = 1;
2973         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2974
2975         /*
2976          * We need the mb() to ensure the ordering between the writing to
2977          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2978          */
2979         smp_mb();
2980
2981         /* queue a periodic task */
2982         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2983
2984         bnx2x_dcbx_pmf_update(bp);
2985
2986         /* enable nig attention */
2987         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2988         if (bp->common.int_block == INT_BLOCK_HC) {
2989                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2990                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2991         } else if (!CHIP_IS_E1x(bp)) {
2992                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2993                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2994         }
2995
2996         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2997 }
2998
2999 /* end of Link */
3000
3001 /* slow path */
3002
3003 /*
3004  * General service functions
3005  */
3006
3007 /* send the MCP a request, block until there is a reply */
3008 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3009 {
3010         int mb_idx = BP_FW_MB_IDX(bp);
3011         u32 seq;
3012         u32 rc = 0;
3013         u32 cnt = 1;
3014         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3015
3016         mutex_lock(&bp->fw_mb_mutex);
3017         seq = ++bp->fw_seq;
3018         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3019         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3020
3021         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3022                         (command | seq), param);
3023
3024         do {
3025                 /* let the FW do it's magic ... */
3026                 msleep(delay);
3027
3028                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3029
3030                 /* Give the FW up to 5 second (500*10ms) */
3031         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3032
3033         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3034            cnt*delay, rc, seq);
3035
3036         /* is this a reply to our command? */
3037         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3038                 rc &= FW_MSG_CODE_MASK;
3039         else {
3040                 /* FW BUG! */
3041                 BNX2X_ERR("FW failed to respond!\n");
3042                 bnx2x_fw_dump(bp);
3043                 rc = 0;
3044         }
3045         mutex_unlock(&bp->fw_mb_mutex);
3046
3047         return rc;
3048 }
3049
3050 static void storm_memset_func_cfg(struct bnx2x *bp,
3051                                  struct tstorm_eth_function_common_config *tcfg,
3052                                  u16 abs_fid)
3053 {
3054         size_t size = sizeof(struct tstorm_eth_function_common_config);
3055
3056         u32 addr = BAR_TSTRORM_INTMEM +
3057                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3058
3059         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3060 }
3061
3062 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3063 {
3064         if (CHIP_IS_E1x(bp)) {
3065                 struct tstorm_eth_function_common_config tcfg = {0};
3066
3067                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3068         }
3069
3070         /* Enable the function in the FW */
3071         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3072         storm_memset_func_en(bp, p->func_id, 1);
3073
3074         /* spq */
3075         if (p->spq_active) {
3076                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3077                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3078                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3079         }
3080 }
3081
3082 /**
3083  * bnx2x_get_common_flags - Return common flags
3084  *
3085  * @bp          device handle
3086  * @fp          queue handle
3087  * @zero_stats  TRUE if statistics zeroing is needed
3088  *
3089  * Return the flags that are common for the Tx-only and not normal connections.
3090  */
3091 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3092                                             struct bnx2x_fastpath *fp,
3093                                             bool zero_stats)
3094 {
3095         unsigned long flags = 0;
3096
3097         /* PF driver will always initialize the Queue to an ACTIVE state */
3098         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3099
3100         /* tx only connections collect statistics (on the same index as the
3101          * parent connection). The statistics are zeroed when the parent
3102          * connection is initialized.
3103          */
3104
3105         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3106         if (zero_stats)
3107                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3108
3109         if (bp->flags & TX_SWITCHING)
3110                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3111
3112         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3113         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3114
3115 #ifdef BNX2X_STOP_ON_ERROR
3116         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3117 #endif
3118
3119         return flags;
3120 }
3121
3122 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3123                                        struct bnx2x_fastpath *fp,
3124                                        bool leading)
3125 {
3126         unsigned long flags = 0;
3127
3128         /* calculate other queue flags */
3129         if (IS_MF_SD(bp))
3130                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3131
3132         if (IS_FCOE_FP(fp)) {
3133                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3134                 /* For FCoE - force usage of default priority (for afex) */
3135                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3136         }
3137
3138         if (fp->mode != TPA_MODE_DISABLED) {
3139                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3140                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3141                 if (fp->mode == TPA_MODE_GRO)
3142                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3143         }
3144
3145         if (leading) {
3146                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3147                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3148         }
3149
3150         /* Always set HW VLAN stripping */
3151         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3152
3153         /* configure silent vlan removal */
3154         if (IS_MF_AFEX(bp))
3155                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3156
3157         return flags | bnx2x_get_common_flags(bp, fp, true);
3158 }
3159
3160 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3161         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3162         u8 cos)
3163 {
3164         gen_init->stat_id = bnx2x_stats_id(fp);
3165         gen_init->spcl_id = fp->cl_id;
3166
3167         /* Always use mini-jumbo MTU for FCoE L2 ring */
3168         if (IS_FCOE_FP(fp))
3169                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3170         else
3171                 gen_init->mtu = bp->dev->mtu;
3172
3173         gen_init->cos = cos;
3174
3175         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3176 }
3177
3178 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3179         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3180         struct bnx2x_rxq_setup_params *rxq_init)
3181 {
3182         u8 max_sge = 0;
3183         u16 sge_sz = 0;
3184         u16 tpa_agg_size = 0;
3185
3186         if (fp->mode != TPA_MODE_DISABLED) {
3187                 pause->sge_th_lo = SGE_TH_LO(bp);
3188                 pause->sge_th_hi = SGE_TH_HI(bp);
3189
3190                 /* validate SGE ring has enough to cross high threshold */
3191                 WARN_ON(bp->dropless_fc &&
3192                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3193                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3194
3195                 tpa_agg_size = TPA_AGG_SIZE;
3196                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3197                         SGE_PAGE_SHIFT;
3198                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3199                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3200                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3201         }
3202
3203         /* pause - not for e1 */
3204         if (!CHIP_IS_E1(bp)) {
3205                 pause->bd_th_lo = BD_TH_LO(bp);
3206                 pause->bd_th_hi = BD_TH_HI(bp);
3207
3208                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3209                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3210                 /*
3211                  * validate that rings have enough entries to cross
3212                  * high thresholds
3213                  */
3214                 WARN_ON(bp->dropless_fc &&
3215                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3216                                 bp->rx_ring_size);
3217                 WARN_ON(bp->dropless_fc &&
3218                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3219                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3220
3221                 pause->pri_map = 1;
3222         }
3223
3224         /* rxq setup */
3225         rxq_init->dscr_map = fp->rx_desc_mapping;
3226         rxq_init->sge_map = fp->rx_sge_mapping;
3227         rxq_init->rcq_map = fp->rx_comp_mapping;
3228         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3229
3230         /* This should be a maximum number of data bytes that may be
3231          * placed on the BD (not including paddings).
3232          */
3233         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3234                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3235
3236         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3237         rxq_init->tpa_agg_sz = tpa_agg_size;
3238         rxq_init->sge_buf_sz = sge_sz;
3239         rxq_init->max_sges_pkt = max_sge;
3240         rxq_init->rss_engine_id = BP_FUNC(bp);
3241         rxq_init->mcast_engine_id = BP_FUNC(bp);
3242
3243         /* Maximum number or simultaneous TPA aggregation for this Queue.
3244          *
3245          * For PF Clients it should be the maximum available number.
3246          * VF driver(s) may want to define it to a smaller value.
3247          */
3248         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3249
3250         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3251         rxq_init->fw_sb_id = fp->fw_sb_id;
3252
3253         if (IS_FCOE_FP(fp))
3254                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3255         else
3256                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3257         /* configure silent vlan removal
3258          * if multi function mode is afex, then mask default vlan
3259          */
3260         if (IS_MF_AFEX(bp)) {
3261                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3262                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3263         }
3264 }
3265
3266 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3267         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3268         u8 cos)
3269 {
3270         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3271         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3272         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3273         txq_init->fw_sb_id = fp->fw_sb_id;
3274
3275         /*
3276          * set the tss leading client id for TX classification ==
3277          * leading RSS client id
3278          */
3279         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3280
3281         if (IS_FCOE_FP(fp)) {
3282                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3283                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3284         }
3285 }
3286
3287 static void bnx2x_pf_init(struct bnx2x *bp)
3288 {
3289         struct bnx2x_func_init_params func_init = {0};
3290         struct event_ring_data eq_data = { {0} };
3291
3292         if (!CHIP_IS_E1x(bp)) {
3293                 /* reset IGU PF statistics: MSIX + ATTN */
3294                 /* PF */
3295                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3296                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3297                            (CHIP_MODE_IS_4_PORT(bp) ?
3298                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3299                 /* ATTN */
3300                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3301                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3302                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3303                            (CHIP_MODE_IS_4_PORT(bp) ?
3304                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3305         }
3306
3307         func_init.spq_active = true;
3308         func_init.pf_id = BP_FUNC(bp);
3309         func_init.func_id = BP_FUNC(bp);
3310         func_init.spq_map = bp->spq_mapping;
3311         func_init.spq_prod = bp->spq_prod_idx;
3312
3313         bnx2x_func_init(bp, &func_init);
3314
3315         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3316
3317         /*
3318          * Congestion management values depend on the link rate
3319          * There is no active link so initial link rate is set to 10 Gbps.
3320          * When the link comes up The congestion management values are
3321          * re-calculated according to the actual link rate.
3322          */
3323         bp->link_vars.line_speed = SPEED_10000;
3324         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3325
3326         /* Only the PMF sets the HW */
3327         if (bp->port.pmf)
3328                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3329
3330         /* init Event Queue - PCI bus guarantees correct endianity*/
3331         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3332         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3333         eq_data.producer = bp->eq_prod;
3334         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3335         eq_data.sb_id = DEF_SB_ID;
3336         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3337 }
3338
3339 static void bnx2x_e1h_disable(struct bnx2x *bp)
3340 {
3341         int port = BP_PORT(bp);
3342
3343         bnx2x_tx_disable(bp);
3344
3345         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3346 }
3347
3348 static void bnx2x_e1h_enable(struct bnx2x *bp)
3349 {
3350         int port = BP_PORT(bp);
3351
3352         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3353                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3354
3355         /* Tx queue should be only re-enabled */
3356         netif_tx_wake_all_queues(bp->dev);
3357
3358         /*
3359          * Should not call netif_carrier_on since it will be called if the link
3360          * is up when checking for link state
3361          */
3362 }
3363
3364 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3365
3366 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3367 {
3368         struct eth_stats_info *ether_stat =
3369                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3370         struct bnx2x_vlan_mac_obj *mac_obj =
3371                 &bp->sp_objs->mac_obj;
3372         int i;
3373
3374         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3375                 ETH_STAT_INFO_VERSION_LEN);
3376
3377         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3378          * mac_local field in ether_stat struct. The base address is offset by 2
3379          * bytes to account for the field being 8 bytes but a mac address is
3380          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3381          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3382          * allocated by the ether_stat struct, so the macs will land in their
3383          * proper positions.
3384          */
3385         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3386                 memset(ether_stat->mac_local + i, 0,
3387                        sizeof(ether_stat->mac_local[0]));
3388         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3389                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3390                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3391                                 ETH_ALEN);
3392         ether_stat->mtu_size = bp->dev->mtu;
3393         if (bp->dev->features & NETIF_F_RXCSUM)
3394                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3395         if (bp->dev->features & NETIF_F_TSO)
3396                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3397         ether_stat->feature_flags |= bp->common.boot_mode;
3398
3399         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3400
3401         ether_stat->txq_size = bp->tx_ring_size;
3402         ether_stat->rxq_size = bp->rx_ring_size;
3403
3404 #ifdef CONFIG_BNX2X_SRIOV
3405         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3406 #endif
3407 }
3408
3409 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3410 {
3411         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3412         struct fcoe_stats_info *fcoe_stat =
3413                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3414
3415         if (!CNIC_LOADED(bp))
3416                 return;
3417
3418         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3419
3420         fcoe_stat->qos_priority =
3421                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3422
3423         /* insert FCoE stats from ramrod response */
3424         if (!NO_FCOE(bp)) {
3425                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3426                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3427                         tstorm_queue_statistics;
3428
3429                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3430                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3431                         xstorm_queue_statistics;
3432
3433                 struct fcoe_statistics_params *fw_fcoe_stat =
3434                         &bp->fw_stats_data->fcoe;
3435
3436                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3437                           fcoe_stat->rx_bytes_lo,
3438                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3439
3440                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3441                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3442                           fcoe_stat->rx_bytes_lo,
3443                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3444
3445                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3446                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3447                           fcoe_stat->rx_bytes_lo,
3448                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3449
3450                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3451                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3452                           fcoe_stat->rx_bytes_lo,
3453                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3454
3455                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456                           fcoe_stat->rx_frames_lo,
3457                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3458
3459                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460                           fcoe_stat->rx_frames_lo,
3461                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3462
3463                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464                           fcoe_stat->rx_frames_lo,
3465                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3466
3467                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3468                           fcoe_stat->rx_frames_lo,
3469                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3470
3471                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3472                           fcoe_stat->tx_bytes_lo,
3473                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3474
3475                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3476                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3477                           fcoe_stat->tx_bytes_lo,
3478                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3479
3480                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3481                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3482                           fcoe_stat->tx_bytes_lo,
3483                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3484
3485                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3486                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3487                           fcoe_stat->tx_bytes_lo,
3488                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3489
3490                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491                           fcoe_stat->tx_frames_lo,
3492                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3493
3494                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495                           fcoe_stat->tx_frames_lo,
3496                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3497
3498                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499                           fcoe_stat->tx_frames_lo,
3500                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3501
3502                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3503                           fcoe_stat->tx_frames_lo,
3504                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3505         }
3506
3507         /* ask L5 driver to add data to the struct */
3508         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3509 }
3510
3511 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3512 {
3513         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3514         struct iscsi_stats_info *iscsi_stat =
3515                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3516
3517         if (!CNIC_LOADED(bp))
3518                 return;
3519
3520         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3521                ETH_ALEN);
3522
3523         iscsi_stat->qos_priority =
3524                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3525
3526         /* ask L5 driver to add data to the struct */
3527         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3528 }
3529
3530 /* called due to MCP event (on pmf):
3531  *      reread new bandwidth configuration
3532  *      configure FW
3533  *      notify others function about the change
3534  */
3535 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3536 {
3537         /* Workaround for MFW bug.
3538          * MFW is not supposed to generate BW attention in
3539          * single function mode.
3540          */
3541         if (!IS_MF(bp)) {
3542                 DP(BNX2X_MSG_MCP,
3543                    "Ignoring MF BW config in single function mode\n");
3544                 return;
3545         }
3546
3547         if (bp->link_vars.link_up) {
3548                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3549                 bnx2x_link_sync_notify(bp);
3550         }
3551         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3552 }
3553
3554 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3555 {
3556         bnx2x_config_mf_bw(bp);
3557         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3558 }
3559
3560 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3561 {
3562         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3563         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3564 }
3565
3566 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3567 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3568
3569 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3570 {
3571         enum drv_info_opcode op_code;
3572         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3573         bool release = false;
3574         int wait;
3575
3576         /* if drv_info version supported by MFW doesn't match - send NACK */
3577         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3578                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3579                 return;
3580         }
3581
3582         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3583                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3584
3585         /* Must prevent other flows from accessing drv_info_to_mcp */
3586         mutex_lock(&bp->drv_info_mutex);
3587
3588         memset(&bp->slowpath->drv_info_to_mcp, 0,
3589                sizeof(union drv_info_to_mcp));
3590
3591         switch (op_code) {
3592         case ETH_STATS_OPCODE:
3593                 bnx2x_drv_info_ether_stat(bp);
3594                 break;
3595         case FCOE_STATS_OPCODE:
3596                 bnx2x_drv_info_fcoe_stat(bp);
3597                 break;
3598         case ISCSI_STATS_OPCODE:
3599                 bnx2x_drv_info_iscsi_stat(bp);
3600                 break;
3601         default:
3602                 /* if op code isn't supported - send NACK */
3603                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3604                 goto out;
3605         }
3606
3607         /* if we got drv_info attn from MFW then these fields are defined in
3608          * shmem2 for sure
3609          */
3610         SHMEM2_WR(bp, drv_info_host_addr_lo,
3611                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3612         SHMEM2_WR(bp, drv_info_host_addr_hi,
3613                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3614
3615         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3616
3617         /* Since possible management wants both this and get_driver_version
3618          * need to wait until management notifies us it finished utilizing
3619          * the buffer.
3620          */
3621         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3622                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3623         } else if (!bp->drv_info_mng_owner) {
3624                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3625
3626                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3627                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3628
3629                         /* Management is done; need to clear indication */
3630                         if (indication & bit) {
3631                                 SHMEM2_WR(bp, mfw_drv_indication,
3632                                           indication & ~bit);
3633                                 release = true;
3634                                 break;
3635                         }
3636
3637                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3638                 }
3639         }
3640         if (!release) {
3641                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3642                 bp->drv_info_mng_owner = true;
3643         }
3644
3645 out:
3646         mutex_unlock(&bp->drv_info_mutex);
3647 }
3648
3649 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3650 {
3651         u8 vals[4];
3652         int i = 0;
3653
3654         if (bnx2x_format) {
3655                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3656                            &vals[0], &vals[1], &vals[2], &vals[3]);
3657                 if (i > 0)
3658                         vals[0] -= '0';
3659         } else {
3660                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3661                            &vals[0], &vals[1], &vals[2], &vals[3]);
3662         }
3663
3664         while (i < 4)
3665                 vals[i++] = 0;
3666
3667         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3668 }
3669
3670 void bnx2x_update_mng_version(struct bnx2x *bp)
3671 {
3672         u32 iscsiver = DRV_VER_NOT_LOADED;
3673         u32 fcoever = DRV_VER_NOT_LOADED;
3674         u32 ethver = DRV_VER_NOT_LOADED;
3675         int idx = BP_FW_MB_IDX(bp);
3676         u8 *version;
3677
3678         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3679                 return;
3680
3681         mutex_lock(&bp->drv_info_mutex);
3682         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3683         if (bp->drv_info_mng_owner)
3684                 goto out;
3685
3686         if (bp->state != BNX2X_STATE_OPEN)
3687                 goto out;
3688
3689         /* Parse ethernet driver version */
3690         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3691         if (!CNIC_LOADED(bp))
3692                 goto out;
3693
3694         /* Try getting storage driver version via cnic */
3695         memset(&bp->slowpath->drv_info_to_mcp, 0,
3696                sizeof(union drv_info_to_mcp));
3697         bnx2x_drv_info_iscsi_stat(bp);
3698         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3699         iscsiver = bnx2x_update_mng_version_utility(version, false);
3700
3701         memset(&bp->slowpath->drv_info_to_mcp, 0,
3702                sizeof(union drv_info_to_mcp));
3703         bnx2x_drv_info_fcoe_stat(bp);
3704         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3705         fcoever = bnx2x_update_mng_version_utility(version, false);
3706
3707 out:
3708         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3709         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3710         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3711
3712         mutex_unlock(&bp->drv_info_mutex);
3713
3714         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3715            ethver, iscsiver, fcoever);
3716 }
3717
3718 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3719 {
3720         u32 drv_ver;
3721         u32 valid_dump;
3722
3723         if (!SHMEM2_HAS(bp, drv_info))
3724                 return;
3725
3726         /* Update Driver load time, possibly broken in y2038 */
3727         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3728
3729         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3730         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3731
3732         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3733
3734         /* Check & notify On-Chip dump. */
3735         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3736
3737         if (valid_dump & FIRST_DUMP_VALID)
3738                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3739
3740         if (valid_dump & SECOND_DUMP_VALID)
3741                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3742 }
3743
3744 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3745 {
3746         u32 cmd_ok, cmd_fail;
3747
3748         /* sanity */
3749         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3750             event & DRV_STATUS_OEM_EVENT_MASK) {
3751                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3752                 return;
3753         }
3754
3755         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3756                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3757                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3758         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3759                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3760                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3761         }
3762
3763         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3764
3765         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3766                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3767                 /* This is the only place besides the function initialization
3768                  * where the bp->flags can change so it is done without any
3769                  * locks
3770                  */
3771                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3772                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3773                         bp->flags |= MF_FUNC_DIS;
3774
3775                         bnx2x_e1h_disable(bp);
3776                 } else {
3777                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3778                         bp->flags &= ~MF_FUNC_DIS;
3779
3780                         bnx2x_e1h_enable(bp);
3781                 }
3782                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3783                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3784         }
3785
3786         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3787                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3788                 bnx2x_config_mf_bw(bp);
3789                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3790                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3791         }
3792
3793         /* Report results to MCP */
3794         if (event)
3795                 bnx2x_fw_command(bp, cmd_fail, 0);
3796         else
3797                 bnx2x_fw_command(bp, cmd_ok, 0);
3798 }
3799
3800 /* must be called under the spq lock */
3801 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3802 {
3803         struct eth_spe *next_spe = bp->spq_prod_bd;
3804
3805         if (bp->spq_prod_bd == bp->spq_last_bd) {
3806                 bp->spq_prod_bd = bp->spq;
3807                 bp->spq_prod_idx = 0;
3808                 DP(BNX2X_MSG_SP, "end of spq\n");
3809         } else {
3810                 bp->spq_prod_bd++;
3811                 bp->spq_prod_idx++;
3812         }
3813         return next_spe;
3814 }
3815
3816 /* must be called under the spq lock */
3817 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3818 {
3819         int func = BP_FUNC(bp);
3820
3821         /*
3822          * Make sure that BD data is updated before writing the producer:
3823          * BD data is written to the memory, the producer is read from the
3824          * memory, thus we need a full memory barrier to ensure the ordering.
3825          */
3826         mb();
3827
3828         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3829                  bp->spq_prod_idx);
3830         mmiowb();
3831 }
3832
3833 /**
3834  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3835  *
3836  * @cmd:        command to check
3837  * @cmd_type:   command type
3838  */
3839 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3840 {
3841         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3842             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3843             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3844             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3845             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3846             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3847             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3848                 return true;
3849         else
3850                 return false;
3851 }
3852
3853 /**
3854  * bnx2x_sp_post - place a single command on an SP ring
3855  *
3856  * @bp:         driver handle
3857  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3858  * @cid:        SW CID the command is related to
3859  * @data_hi:    command private data address (high 32 bits)
3860  * @data_lo:    command private data address (low 32 bits)
3861  * @cmd_type:   command type (e.g. NONE, ETH)
3862  *
3863  * SP data is handled as if it's always an address pair, thus data fields are
3864  * not swapped to little endian in upper functions. Instead this function swaps
3865  * data as if it's two u32 fields.
3866  */
3867 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3868                   u32 data_hi, u32 data_lo, int cmd_type)
3869 {
3870         struct eth_spe *spe;
3871         u16 type;
3872         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3873
3874 #ifdef BNX2X_STOP_ON_ERROR
3875         if (unlikely(bp->panic)) {
3876                 BNX2X_ERR("Can't post SP when there is panic\n");
3877                 return -EIO;
3878         }
3879 #endif
3880
3881         spin_lock_bh(&bp->spq_lock);
3882
3883         if (common) {
3884                 if (!atomic_read(&bp->eq_spq_left)) {
3885                         BNX2X_ERR("BUG! EQ ring full!\n");
3886                         spin_unlock_bh(&bp->spq_lock);
3887                         bnx2x_panic();
3888                         return -EBUSY;
3889                 }
3890         } else if (!atomic_read(&bp->cq_spq_left)) {
3891                         BNX2X_ERR("BUG! SPQ ring full!\n");
3892                         spin_unlock_bh(&bp->spq_lock);
3893                         bnx2x_panic();
3894                         return -EBUSY;
3895         }
3896
3897         spe = bnx2x_sp_get_next(bp);
3898
3899         /* CID needs port number to be encoded int it */
3900         spe->hdr.conn_and_cmd_data =
3901                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3902                                     HW_CID(bp, cid));
3903
3904         /* In some cases, type may already contain the func-id
3905          * mainly in SRIOV related use cases, so we add it here only
3906          * if it's not already set.
3907          */
3908         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3909                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3910                         SPE_HDR_CONN_TYPE;
3911                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3912                          SPE_HDR_FUNCTION_ID);
3913         } else {
3914                 type = cmd_type;
3915         }
3916
3917         spe->hdr.type = cpu_to_le16(type);
3918
3919         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3920         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3921
3922         /*
3923          * It's ok if the actual decrement is issued towards the memory
3924          * somewhere between the spin_lock and spin_unlock. Thus no
3925          * more explicit memory barrier is needed.
3926          */
3927         if (common)
3928                 atomic_dec(&bp->eq_spq_left);
3929         else
3930                 atomic_dec(&bp->cq_spq_left);
3931
3932         DP(BNX2X_MSG_SP,
3933            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3934            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3935            (u32)(U64_LO(bp->spq_mapping) +
3936            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3937            HW_CID(bp, cid), data_hi, data_lo, type,
3938            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3939
3940         bnx2x_sp_prod_update(bp);
3941         spin_unlock_bh(&bp->spq_lock);
3942         return 0;
3943 }
3944
3945 /* acquire split MCP access lock register */
3946 static int bnx2x_acquire_alr(struct bnx2x *bp)
3947 {
3948         u32 j, val;
3949         int rc = 0;
3950
3951         might_sleep();
3952         for (j = 0; j < 1000; j++) {
3953                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3954                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3955                 if (val & MCPR_ACCESS_LOCK_LOCK)
3956                         break;
3957
3958                 usleep_range(5000, 10000);
3959         }
3960         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3961                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3962                 rc = -EBUSY;
3963         }
3964
3965         return rc;
3966 }
3967
3968 /* release split MCP access lock register */
3969 static void bnx2x_release_alr(struct bnx2x *bp)
3970 {
3971         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3972 }
3973
3974 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3975 #define BNX2X_DEF_SB_IDX        0x0002
3976
3977 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3978 {
3979         struct host_sp_status_block *def_sb = bp->def_status_blk;
3980         u16 rc = 0;
3981
3982         barrier(); /* status block is written to by the chip */
3983         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3984                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3985                 rc |= BNX2X_DEF_SB_ATT_IDX;
3986         }
3987
3988         if (bp->def_idx != def_sb->sp_sb.running_index) {
3989                 bp->def_idx = def_sb->sp_sb.running_index;
3990                 rc |= BNX2X_DEF_SB_IDX;
3991         }
3992
3993         /* Do not reorder: indices reading should complete before handling */
3994         barrier();
3995         return rc;
3996 }
3997
3998 /*
3999  * slow path service functions
4000  */
4001
4002 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4003 {
4004         int port = BP_PORT(bp);
4005         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4006                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
4007         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4008                                        NIG_REG_MASK_INTERRUPT_PORT0;
4009         u32 aeu_mask;
4010         u32 nig_mask = 0;
4011         u32 reg_addr;
4012
4013         if (bp->attn_state & asserted)
4014                 BNX2X_ERR("IGU ERROR\n");
4015
4016         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4017         aeu_mask = REG_RD(bp, aeu_addr);
4018
4019         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4020            aeu_mask, asserted);
4021         aeu_mask &= ~(asserted & 0x3ff);
4022         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4023
4024         REG_WR(bp, aeu_addr, aeu_mask);
4025         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4026
4027         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4028         bp->attn_state |= asserted;
4029         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4030
4031         if (asserted & ATTN_HARD_WIRED_MASK) {
4032                 if (asserted & ATTN_NIG_FOR_FUNC) {
4033
4034                         bnx2x_acquire_phy_lock(bp);
4035
4036                         /* save nig interrupt mask */
4037                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4038
4039                         /* If nig_mask is not set, no need to call the update
4040                          * function.
4041                          */
4042                         if (nig_mask) {
4043                                 REG_WR(bp, nig_int_mask_addr, 0);
4044
4045                                 bnx2x_link_attn(bp);
4046                         }
4047
4048                         /* handle unicore attn? */
4049                 }
4050                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4051                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4052
4053                 if (asserted & GPIO_2_FUNC)
4054                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4055
4056                 if (asserted & GPIO_3_FUNC)
4057                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4058
4059                 if (asserted & GPIO_4_FUNC)
4060                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4061
4062                 if (port == 0) {
4063                         if (asserted & ATTN_GENERAL_ATTN_1) {
4064                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4065                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4066                         }
4067                         if (asserted & ATTN_GENERAL_ATTN_2) {
4068                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4069                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4070                         }
4071                         if (asserted & ATTN_GENERAL_ATTN_3) {
4072                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4073                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4074                         }
4075                 } else {
4076                         if (asserted & ATTN_GENERAL_ATTN_4) {
4077                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4078                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4079                         }
4080                         if (asserted & ATTN_GENERAL_ATTN_5) {
4081                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4082                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4083                         }
4084                         if (asserted & ATTN_GENERAL_ATTN_6) {
4085                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4086                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4087                         }
4088                 }
4089
4090         } /* if hardwired */
4091
4092         if (bp->common.int_block == INT_BLOCK_HC)
4093                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4094                             COMMAND_REG_ATTN_BITS_SET);
4095         else
4096                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4097
4098         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4099            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4100         REG_WR(bp, reg_addr, asserted);
4101
4102         /* now set back the mask */
4103         if (asserted & ATTN_NIG_FOR_FUNC) {
4104                 /* Verify that IGU ack through BAR was written before restoring
4105                  * NIG mask. This loop should exit after 2-3 iterations max.
4106                  */
4107                 if (bp->common.int_block != INT_BLOCK_HC) {
4108                         u32 cnt = 0, igu_acked;
4109                         do {
4110                                 igu_acked = REG_RD(bp,
4111                                                    IGU_REG_ATTENTION_ACK_BITS);
4112                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4113                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4114                         if (!igu_acked)
4115                                 DP(NETIF_MSG_HW,
4116                                    "Failed to verify IGU ack on time\n");
4117                         barrier();
4118                 }
4119                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4120                 bnx2x_release_phy_lock(bp);
4121         }
4122 }
4123
4124 static void bnx2x_fan_failure(struct bnx2x *bp)
4125 {
4126         int port = BP_PORT(bp);
4127         u32 ext_phy_config;
4128         /* mark the failure */
4129         ext_phy_config =
4130                 SHMEM_RD(bp,
4131                          dev_info.port_hw_config[port].external_phy_config);
4132
4133         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4134         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4135         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4136                  ext_phy_config);
4137
4138         /* log the failure */
4139         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4140                             "Please contact OEM Support for assistance\n");
4141
4142         /* Schedule device reset (unload)
4143          * This is due to some boards consuming sufficient power when driver is
4144          * up to overheat if fan fails.
4145          */
4146         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4147 }
4148
4149 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4150 {
4151         int port = BP_PORT(bp);
4152         int reg_offset;
4153         u32 val;
4154
4155         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4156                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4157
4158         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4159
4160                 val = REG_RD(bp, reg_offset);
4161                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4162                 REG_WR(bp, reg_offset, val);
4163
4164                 BNX2X_ERR("SPIO5 hw attention\n");
4165
4166                 /* Fan failure attention */
4167                 bnx2x_hw_reset_phy(&bp->link_params);
4168                 bnx2x_fan_failure(bp);
4169         }
4170
4171         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4172                 bnx2x_acquire_phy_lock(bp);
4173                 bnx2x_handle_module_detect_int(&bp->link_params);
4174                 bnx2x_release_phy_lock(bp);
4175         }
4176
4177         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4178
4179                 val = REG_RD(bp, reg_offset);
4180                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4181                 REG_WR(bp, reg_offset, val);
4182
4183                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4184                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4185                 bnx2x_panic();
4186         }
4187 }
4188
4189 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4190 {
4191         u32 val;
4192
4193         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4194
4195                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4196                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4197                 /* DORQ discard attention */
4198                 if (val & 0x2)
4199                         BNX2X_ERR("FATAL error from DORQ\n");
4200         }
4201
4202         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4203
4204                 int port = BP_PORT(bp);
4205                 int reg_offset;
4206
4207                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4208                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4209
4210                 val = REG_RD(bp, reg_offset);
4211                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4212                 REG_WR(bp, reg_offset, val);
4213
4214                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4215                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4216                 bnx2x_panic();
4217         }
4218 }
4219
4220 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4221 {
4222         u32 val;
4223
4224         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4225
4226                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4227                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4228                 /* CFC error attention */
4229                 if (val & 0x2)
4230                         BNX2X_ERR("FATAL error from CFC\n");
4231         }
4232
4233         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4234                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4235                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4236                 /* RQ_USDMDP_FIFO_OVERFLOW */
4237                 if (val & 0x18000)
4238                         BNX2X_ERR("FATAL error from PXP\n");
4239
4240                 if (!CHIP_IS_E1x(bp)) {
4241                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4242                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4243                 }
4244         }
4245
4246         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4247
4248                 int port = BP_PORT(bp);
4249                 int reg_offset;
4250
4251                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4252                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4253
4254                 val = REG_RD(bp, reg_offset);
4255                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4256                 REG_WR(bp, reg_offset, val);
4257
4258                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4259                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4260                 bnx2x_panic();
4261         }
4262 }
4263
4264 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4265 {
4266         u32 val;
4267
4268         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4269
4270                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4271                         int func = BP_FUNC(bp);
4272
4273                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4274                         bnx2x_read_mf_cfg(bp);
4275                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4276                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4277                         val = SHMEM_RD(bp,
4278                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4279
4280                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4281                                    DRV_STATUS_OEM_EVENT_MASK))
4282                                 bnx2x_oem_event(bp,
4283                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4284                                                 DRV_STATUS_OEM_EVENT_MASK)));
4285
4286                         if (val & DRV_STATUS_SET_MF_BW)
4287                                 bnx2x_set_mf_bw(bp);
4288
4289                         if (val & DRV_STATUS_DRV_INFO_REQ)
4290                                 bnx2x_handle_drv_info_req(bp);
4291
4292                         if (val & DRV_STATUS_VF_DISABLED)
4293                                 bnx2x_schedule_iov_task(bp,
4294                                                         BNX2X_IOV_HANDLE_FLR);
4295
4296                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4297                                 bnx2x_pmf_update(bp);
4298
4299                         if (bp->port.pmf &&
4300                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4301                                 bp->dcbx_enabled > 0)
4302                                 /* start dcbx state machine */
4303                                 bnx2x_dcbx_set_params(bp,
4304                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4305                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4306                                 bnx2x_handle_afex_cmd(bp,
4307                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4308                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4309                                 bnx2x_handle_eee_event(bp);
4310
4311                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4312                                 bnx2x_schedule_sp_rtnl(bp,
4313                                         BNX2X_SP_RTNL_UPDATE_SVID, 0);
4314
4315                         if (bp->link_vars.periodic_flags &
4316                             PERIODIC_FLAGS_LINK_EVENT) {
4317                                 /*  sync with link */
4318                                 bnx2x_acquire_phy_lock(bp);
4319                                 bp->link_vars.periodic_flags &=
4320                                         ~PERIODIC_FLAGS_LINK_EVENT;
4321                                 bnx2x_release_phy_lock(bp);
4322                                 if (IS_MF(bp))
4323                                         bnx2x_link_sync_notify(bp);
4324                                 bnx2x_link_report(bp);
4325                         }
4326                         /* Always call it here: bnx2x_link_report() will
4327                          * prevent the link indication duplication.
4328                          */
4329                         bnx2x__link_status_update(bp);
4330                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4331
4332                         BNX2X_ERR("MC assert!\n");
4333                         bnx2x_mc_assert(bp);
4334                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4335                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4336                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4337                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4338                         bnx2x_panic();
4339
4340                 } else if (attn & BNX2X_MCP_ASSERT) {
4341
4342                         BNX2X_ERR("MCP assert!\n");
4343                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4344                         bnx2x_fw_dump(bp);
4345
4346                 } else
4347                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4348         }
4349
4350         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4351                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4352                 if (attn & BNX2X_GRC_TIMEOUT) {
4353                         val = CHIP_IS_E1(bp) ? 0 :
4354                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4355                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4356                 }
4357                 if (attn & BNX2X_GRC_RSV) {
4358                         val = CHIP_IS_E1(bp) ? 0 :
4359                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4360                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4361                 }
4362                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4363         }
4364 }
4365
4366 /*
4367  * Bits map:
4368  * 0-7   - Engine0 load counter.
4369  * 8-15  - Engine1 load counter.
4370  * 16    - Engine0 RESET_IN_PROGRESS bit.
4371  * 17    - Engine1 RESET_IN_PROGRESS bit.
4372  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4373  *         on the engine
4374  * 19    - Engine1 ONE_IS_LOADED.
4375  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4376  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4377  *         just the one belonging to its engine).
4378  *
4379  */
4380 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4381
4382 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4383 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4384 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4385 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4386 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4387 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4388 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4389
4390 /*
4391  * Set the GLOBAL_RESET bit.
4392  *
4393  * Should be run under rtnl lock
4394  */
4395 void bnx2x_set_reset_global(struct bnx2x *bp)
4396 {
4397         u32 val;
4398         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4399         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4400         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4401         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4402 }
4403
4404 /*
4405  * Clear the GLOBAL_RESET bit.
4406  *
4407  * Should be run under rtnl lock
4408  */
4409 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4410 {
4411         u32 val;
4412         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4413         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4414         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4415         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4416 }
4417
4418 /*
4419  * Checks the GLOBAL_RESET bit.
4420  *
4421  * should be run under rtnl lock
4422  */
4423 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4424 {
4425         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4426
4427         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4428         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4429 }
4430
4431 /*
4432  * Clear RESET_IN_PROGRESS bit for the current engine.
4433  *
4434  * Should be run under rtnl lock
4435  */
4436 static void bnx2x_set_reset_done(struct bnx2x *bp)
4437 {
4438         u32 val;
4439         u32 bit = BP_PATH(bp) ?
4440                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4441         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4442         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4443
4444         /* Clear the bit */
4445         val &= ~bit;
4446         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4447
4448         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4449 }
4450
4451 /*
4452  * Set RESET_IN_PROGRESS for the current engine.
4453  *
4454  * should be run under rtnl lock
4455  */
4456 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4457 {
4458         u32 val;
4459         u32 bit = BP_PATH(bp) ?
4460                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4461         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4462         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4463
4464         /* Set the bit */
4465         val |= bit;
4466         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4467         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4468 }
4469
4470 /*
4471  * Checks the RESET_IN_PROGRESS bit for the given engine.
4472  * should be run under rtnl lock
4473  */
4474 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4475 {
4476         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4477         u32 bit = engine ?
4478                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4479
4480         /* return false if bit is set */
4481         return (val & bit) ? false : true;
4482 }
4483
4484 /*
4485  * set pf load for the current pf.
4486  *
4487  * should be run under rtnl lock
4488  */
4489 void bnx2x_set_pf_load(struct bnx2x *bp)
4490 {
4491         u32 val1, val;
4492         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4493                              BNX2X_PATH0_LOAD_CNT_MASK;
4494         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4495                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4496
4497         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4498         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4499
4500         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4501
4502         /* get the current counter value */
4503         val1 = (val & mask) >> shift;
4504
4505         /* set bit of that PF */
4506         val1 |= (1 << bp->pf_num);
4507
4508         /* clear the old value */
4509         val &= ~mask;
4510
4511         /* set the new one */
4512         val |= ((val1 << shift) & mask);
4513
4514         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4515         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4516 }
4517
4518 /**
4519  * bnx2x_clear_pf_load - clear pf load mark
4520  *
4521  * @bp:         driver handle
4522  *
4523  * Should be run under rtnl lock.
4524  * Decrements the load counter for the current engine. Returns
4525  * whether other functions are still loaded
4526  */
4527 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4528 {
4529         u32 val1, val;
4530         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4531                              BNX2X_PATH0_LOAD_CNT_MASK;
4532         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4533                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4534
4535         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4536         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4537         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4538
4539         /* get the current counter value */
4540         val1 = (val & mask) >> shift;
4541
4542         /* clear bit of that PF */
4543         val1 &= ~(1 << bp->pf_num);
4544
4545         /* clear the old value */
4546         val &= ~mask;
4547
4548         /* set the new one */
4549         val |= ((val1 << shift) & mask);
4550
4551         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4552         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4553         return val1 != 0;
4554 }
4555
4556 /*
4557  * Read the load status for the current engine.
4558  *
4559  * should be run under rtnl lock
4560  */
4561 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4562 {
4563         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4564                              BNX2X_PATH0_LOAD_CNT_MASK);
4565         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4566                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4567         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4568
4569         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4570
4571         val = (val & mask) >> shift;
4572
4573         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4574            engine, val);
4575
4576         return val != 0;
4577 }
4578
4579 static void _print_parity(struct bnx2x *bp, u32 reg)
4580 {
4581         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4582 }
4583
4584 static void _print_next_block(int idx, const char *blk)
4585 {
4586         pr_cont("%s%s", idx ? ", " : "", blk);
4587 }
4588
4589 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4590                                             int *par_num, bool print)
4591 {
4592         u32 cur_bit;
4593         bool res;
4594         int i;
4595
4596         res = false;
4597
4598         for (i = 0; sig; i++) {
4599                 cur_bit = (0x1UL << i);
4600                 if (sig & cur_bit) {
4601                         res |= true; /* Each bit is real error! */
4602
4603                         if (print) {
4604                                 switch (cur_bit) {
4605                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4606                                         _print_next_block((*par_num)++, "BRB");
4607                                         _print_parity(bp,
4608                                                       BRB1_REG_BRB1_PRTY_STS);
4609                                         break;
4610                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4611                                         _print_next_block((*par_num)++,
4612                                                           "PARSER");
4613                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4614                                         break;
4615                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4616                                         _print_next_block((*par_num)++, "TSDM");
4617                                         _print_parity(bp,
4618                                                       TSDM_REG_TSDM_PRTY_STS);
4619                                         break;
4620                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4621                                         _print_next_block((*par_num)++,
4622                                                           "SEARCHER");
4623                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4624                                         break;
4625                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4626                                         _print_next_block((*par_num)++, "TCM");
4627                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4628                                         break;
4629                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4630                                         _print_next_block((*par_num)++,
4631                                                           "TSEMI");
4632                                         _print_parity(bp,
4633                                                       TSEM_REG_TSEM_PRTY_STS_0);
4634                                         _print_parity(bp,
4635                                                       TSEM_REG_TSEM_PRTY_STS_1);
4636                                         break;
4637                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4638                                         _print_next_block((*par_num)++, "XPB");
4639                                         _print_parity(bp, GRCBASE_XPB +
4640                                                           PB_REG_PB_PRTY_STS);
4641                                         break;
4642                                 }
4643                         }
4644
4645                         /* Clear the bit */
4646                         sig &= ~cur_bit;
4647                 }
4648         }
4649
4650         return res;
4651 }
4652
4653 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4654                                             int *par_num, bool *global,
4655                                             bool print)
4656 {
4657         u32 cur_bit;
4658         bool res;
4659         int i;
4660
4661         res = false;
4662
4663         for (i = 0; sig; i++) {
4664                 cur_bit = (0x1UL << i);
4665                 if (sig & cur_bit) {
4666                         res |= true; /* Each bit is real error! */
4667                         switch (cur_bit) {
4668                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4669                                 if (print) {
4670                                         _print_next_block((*par_num)++, "PBF");
4671                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4672                                 }
4673                                 break;
4674                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4675                                 if (print) {
4676                                         _print_next_block((*par_num)++, "QM");
4677                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4678                                 }
4679                                 break;
4680                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4681                                 if (print) {
4682                                         _print_next_block((*par_num)++, "TM");
4683                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4684                                 }
4685                                 break;
4686                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4687                                 if (print) {
4688                                         _print_next_block((*par_num)++, "XSDM");
4689                                         _print_parity(bp,
4690                                                       XSDM_REG_XSDM_PRTY_STS);
4691                                 }
4692                                 break;
4693                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4694                                 if (print) {
4695                                         _print_next_block((*par_num)++, "XCM");
4696                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4697                                 }
4698                                 break;
4699                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4700                                 if (print) {
4701                                         _print_next_block((*par_num)++,
4702                                                           "XSEMI");
4703                                         _print_parity(bp,
4704                                                       XSEM_REG_XSEM_PRTY_STS_0);
4705                                         _print_parity(bp,
4706                                                       XSEM_REG_XSEM_PRTY_STS_1);
4707                                 }
4708                                 break;
4709                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4710                                 if (print) {
4711                                         _print_next_block((*par_num)++,
4712                                                           "DOORBELLQ");
4713                                         _print_parity(bp,
4714                                                       DORQ_REG_DORQ_PRTY_STS);
4715                                 }
4716                                 break;
4717                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4718                                 if (print) {
4719                                         _print_next_block((*par_num)++, "NIG");
4720                                         if (CHIP_IS_E1x(bp)) {
4721                                                 _print_parity(bp,
4722                                                         NIG_REG_NIG_PRTY_STS);
4723                                         } else {
4724                                                 _print_parity(bp,
4725                                                         NIG_REG_NIG_PRTY_STS_0);
4726                                                 _print_parity(bp,
4727                                                         NIG_REG_NIG_PRTY_STS_1);
4728                                         }
4729                                 }
4730                                 break;
4731                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4732                                 if (print)
4733                                         _print_next_block((*par_num)++,
4734                                                           "VAUX PCI CORE");
4735                                 *global = true;
4736                                 break;
4737                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4738                                 if (print) {
4739                                         _print_next_block((*par_num)++,
4740                                                           "DEBUG");
4741                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4742                                 }
4743                                 break;
4744                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4745                                 if (print) {
4746                                         _print_next_block((*par_num)++, "USDM");
4747                                         _print_parity(bp,
4748                                                       USDM_REG_USDM_PRTY_STS);
4749                                 }
4750                                 break;
4751                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4752                                 if (print) {
4753                                         _print_next_block((*par_num)++, "UCM");
4754                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4755                                 }
4756                                 break;
4757                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4758                                 if (print) {
4759                                         _print_next_block((*par_num)++,
4760                                                           "USEMI");
4761                                         _print_parity(bp,
4762                                                       USEM_REG_USEM_PRTY_STS_0);
4763                                         _print_parity(bp,
4764                                                       USEM_REG_USEM_PRTY_STS_1);
4765                                 }
4766                                 break;
4767                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4768                                 if (print) {
4769                                         _print_next_block((*par_num)++, "UPB");
4770                                         _print_parity(bp, GRCBASE_UPB +
4771                                                           PB_REG_PB_PRTY_STS);
4772                                 }
4773                                 break;
4774                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4775                                 if (print) {
4776                                         _print_next_block((*par_num)++, "CSDM");
4777                                         _print_parity(bp,
4778                                                       CSDM_REG_CSDM_PRTY_STS);
4779                                 }
4780                                 break;
4781                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4782                                 if (print) {
4783                                         _print_next_block((*par_num)++, "CCM");
4784                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4785                                 }
4786                                 break;
4787                         }
4788
4789                         /* Clear the bit */
4790                         sig &= ~cur_bit;
4791                 }
4792         }
4793
4794         return res;
4795 }
4796
4797 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4798                                             int *par_num, bool print)
4799 {
4800         u32 cur_bit;
4801         bool res;
4802         int i;
4803
4804         res = false;
4805
4806         for (i = 0; sig; i++) {
4807                 cur_bit = (0x1UL << i);
4808                 if (sig & cur_bit) {
4809                         res = true; /* Each bit is real error! */
4810                         if (print) {
4811                                 switch (cur_bit) {
4812                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4813                                         _print_next_block((*par_num)++,
4814                                                           "CSEMI");
4815                                         _print_parity(bp,
4816                                                       CSEM_REG_CSEM_PRTY_STS_0);
4817                                         _print_parity(bp,
4818                                                       CSEM_REG_CSEM_PRTY_STS_1);
4819                                         break;
4820                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4821                                         _print_next_block((*par_num)++, "PXP");
4822                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4823                                         _print_parity(bp,
4824                                                       PXP2_REG_PXP2_PRTY_STS_0);
4825                                         _print_parity(bp,
4826                                                       PXP2_REG_PXP2_PRTY_STS_1);
4827                                         break;
4828                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4829                                         _print_next_block((*par_num)++,
4830                                                           "PXPPCICLOCKCLIENT");
4831                                         break;
4832                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4833                                         _print_next_block((*par_num)++, "CFC");
4834                                         _print_parity(bp,
4835                                                       CFC_REG_CFC_PRTY_STS);
4836                                         break;
4837                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4838                                         _print_next_block((*par_num)++, "CDU");
4839                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4840                                         break;
4841                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4842                                         _print_next_block((*par_num)++, "DMAE");
4843                                         _print_parity(bp,
4844                                                       DMAE_REG_DMAE_PRTY_STS);
4845                                         break;
4846                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4847                                         _print_next_block((*par_num)++, "IGU");
4848                                         if (CHIP_IS_E1x(bp))
4849                                                 _print_parity(bp,
4850                                                         HC_REG_HC_PRTY_STS);
4851                                         else
4852                                                 _print_parity(bp,
4853                                                         IGU_REG_IGU_PRTY_STS);
4854                                         break;
4855                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4856                                         _print_next_block((*par_num)++, "MISC");
4857                                         _print_parity(bp,
4858                                                       MISC_REG_MISC_PRTY_STS);
4859                                         break;
4860                                 }
4861                         }
4862
4863                         /* Clear the bit */
4864                         sig &= ~cur_bit;
4865                 }
4866         }
4867
4868         return res;
4869 }
4870
4871 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4872                                             int *par_num, bool *global,
4873                                             bool print)
4874 {
4875         bool res = false;
4876         u32 cur_bit;
4877         int i;
4878
4879         for (i = 0; sig; i++) {
4880                 cur_bit = (0x1UL << i);
4881                 if (sig & cur_bit) {
4882                         switch (cur_bit) {
4883                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4884                                 if (print)
4885                                         _print_next_block((*par_num)++,
4886                                                           "MCP ROM");
4887                                 *global = true;
4888                                 res = true;
4889                                 break;
4890                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4891                                 if (print)
4892                                         _print_next_block((*par_num)++,
4893                                                           "MCP UMP RX");
4894                                 *global = true;
4895                                 res = true;
4896                                 break;
4897                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4898                                 if (print)
4899                                         _print_next_block((*par_num)++,
4900                                                           "MCP UMP TX");
4901                                 *global = true;
4902                                 res = true;
4903                                 break;
4904                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4905                                 (*par_num)++;
4906                                 /* clear latched SCPAD PATIRY from MCP */
4907                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4908                                        1UL << 10);
4909                                 break;
4910                         }
4911
4912                         /* Clear the bit */
4913                         sig &= ~cur_bit;
4914                 }
4915         }
4916
4917         return res;
4918 }
4919
4920 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4921                                             int *par_num, bool print)
4922 {
4923         u32 cur_bit;
4924         bool res;
4925         int i;
4926
4927         res = false;
4928
4929         for (i = 0; sig; i++) {
4930                 cur_bit = (0x1UL << i);
4931                 if (sig & cur_bit) {
4932                         res = true; /* Each bit is real error! */
4933                         if (print) {
4934                                 switch (cur_bit) {
4935                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4936                                         _print_next_block((*par_num)++,
4937                                                           "PGLUE_B");
4938                                         _print_parity(bp,
4939                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4940                                         break;
4941                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4942                                         _print_next_block((*par_num)++, "ATC");
4943                                         _print_parity(bp,
4944                                                       ATC_REG_ATC_PRTY_STS);
4945                                         break;
4946                                 }
4947                         }
4948                         /* Clear the bit */
4949                         sig &= ~cur_bit;
4950                 }
4951         }
4952
4953         return res;
4954 }
4955
4956 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4957                               u32 *sig)
4958 {
4959         bool res = false;
4960
4961         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4962             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4963             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4964             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4965             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4966                 int par_num = 0;
4967
4968                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4969                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4970                           sig[0] & HW_PRTY_ASSERT_SET_0,
4971                           sig[1] & HW_PRTY_ASSERT_SET_1,
4972                           sig[2] & HW_PRTY_ASSERT_SET_2,
4973                           sig[3] & HW_PRTY_ASSERT_SET_3,
4974                           sig[4] & HW_PRTY_ASSERT_SET_4);
4975                 if (print) {
4976                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4977                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4978                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4979                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4980                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4981                                 netdev_err(bp->dev,
4982                                            "Parity errors detected in blocks: ");
4983                         } else {
4984                                 print = false;
4985                         }
4986                 }
4987                 res |= bnx2x_check_blocks_with_parity0(bp,
4988                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4989                 res |= bnx2x_check_blocks_with_parity1(bp,
4990                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4991                 res |= bnx2x_check_blocks_with_parity2(bp,
4992                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4993                 res |= bnx2x_check_blocks_with_parity3(bp,
4994                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4995                 res |= bnx2x_check_blocks_with_parity4(bp,
4996                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4997
4998                 if (print)
4999                         pr_cont("\n");
5000         }
5001
5002         return res;
5003 }
5004
5005 /**
5006  * bnx2x_chk_parity_attn - checks for parity attentions.
5007  *
5008  * @bp:         driver handle
5009  * @global:     true if there was a global attention
5010  * @print:      show parity attention in syslog
5011  */
5012 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5013 {
5014         struct attn_route attn = { {0} };
5015         int port = BP_PORT(bp);
5016
5017         attn.sig[0] = REG_RD(bp,
5018                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5019                              port*4);
5020         attn.sig[1] = REG_RD(bp,
5021                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5022                              port*4);
5023         attn.sig[2] = REG_RD(bp,
5024                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5025                              port*4);
5026         attn.sig[3] = REG_RD(bp,
5027                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5028                              port*4);
5029         /* Since MCP attentions can't be disabled inside the block, we need to
5030          * read AEU registers to see whether they're currently disabled
5031          */
5032         attn.sig[3] &= ((REG_RD(bp,
5033                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5034                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5035                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5036                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5037
5038         if (!CHIP_IS_E1x(bp))
5039                 attn.sig[4] = REG_RD(bp,
5040                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5041                                      port*4);
5042
5043         return bnx2x_parity_attn(bp, global, print, attn.sig);
5044 }
5045
5046 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5047 {
5048         u32 val;
5049         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5050
5051                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5052                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5053                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5054                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5055                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5056                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5057                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5058                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5059                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5060                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5061                 if (val &
5062                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5063                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5064                 if (val &
5065                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5066                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5067                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5068                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5069                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5070                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5071                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5072                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5073         }
5074         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5075                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5076                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5077                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5078                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5079                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5080                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5081                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5082                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5083                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5084                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5085                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5086                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5087                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5088                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5089         }
5090
5091         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5092                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5093                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5094                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5095                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5096         }
5097 }
5098
5099 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5100 {
5101         struct attn_route attn, *group_mask;
5102         int port = BP_PORT(bp);
5103         int index;
5104         u32 reg_addr;
5105         u32 val;
5106         u32 aeu_mask;
5107         bool global = false;
5108
5109         /* need to take HW lock because MCP or other port might also
5110            try to handle this event */
5111         bnx2x_acquire_alr(bp);
5112
5113         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5114 #ifndef BNX2X_STOP_ON_ERROR
5115                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5116                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5117                 /* Disable HW interrupts */
5118                 bnx2x_int_disable(bp);
5119                 /* In case of parity errors don't handle attentions so that
5120                  * other function would "see" parity errors.
5121                  */
5122 #else
5123                 bnx2x_panic();
5124 #endif
5125                 bnx2x_release_alr(bp);
5126                 return;
5127         }
5128
5129         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5130         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5131         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5132         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5133         if (!CHIP_IS_E1x(bp))
5134                 attn.sig[4] =
5135                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5136         else
5137                 attn.sig[4] = 0;
5138
5139         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5140            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5141
5142         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5143                 if (deasserted & (1 << index)) {
5144                         group_mask = &bp->attn_group[index];
5145
5146                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5147                            index,
5148                            group_mask->sig[0], group_mask->sig[1],
5149                            group_mask->sig[2], group_mask->sig[3],
5150                            group_mask->sig[4]);
5151
5152                         bnx2x_attn_int_deasserted4(bp,
5153                                         attn.sig[4] & group_mask->sig[4]);
5154                         bnx2x_attn_int_deasserted3(bp,
5155                                         attn.sig[3] & group_mask->sig[3]);
5156                         bnx2x_attn_int_deasserted1(bp,
5157                                         attn.sig[1] & group_mask->sig[1]);
5158                         bnx2x_attn_int_deasserted2(bp,
5159                                         attn.sig[2] & group_mask->sig[2]);
5160                         bnx2x_attn_int_deasserted0(bp,
5161                                         attn.sig[0] & group_mask->sig[0]);
5162                 }
5163         }
5164
5165         bnx2x_release_alr(bp);
5166
5167         if (bp->common.int_block == INT_BLOCK_HC)
5168                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5169                             COMMAND_REG_ATTN_BITS_CLR);
5170         else
5171                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5172
5173         val = ~deasserted;
5174         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5175            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5176         REG_WR(bp, reg_addr, val);
5177
5178         if (~bp->attn_state & deasserted)
5179                 BNX2X_ERR("IGU ERROR\n");
5180
5181         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5182                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5183
5184         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5185         aeu_mask = REG_RD(bp, reg_addr);
5186
5187         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5188            aeu_mask, deasserted);
5189         aeu_mask |= (deasserted & 0x3ff);
5190         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5191
5192         REG_WR(bp, reg_addr, aeu_mask);
5193         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5194
5195         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5196         bp->attn_state &= ~deasserted;
5197         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5198 }
5199
5200 static void bnx2x_attn_int(struct bnx2x *bp)
5201 {
5202         /* read local copy of bits */
5203         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5204                                                                 attn_bits);
5205         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5206                                                                 attn_bits_ack);
5207         u32 attn_state = bp->attn_state;
5208
5209         /* look for changed bits */
5210         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5211         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5212
5213         DP(NETIF_MSG_HW,
5214            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5215            attn_bits, attn_ack, asserted, deasserted);
5216
5217         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5218                 BNX2X_ERR("BAD attention state\n");
5219
5220         /* handle bits that were raised */
5221         if (asserted)
5222                 bnx2x_attn_int_asserted(bp, asserted);
5223
5224         if (deasserted)
5225                 bnx2x_attn_int_deasserted(bp, deasserted);
5226 }
5227
5228 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5229                       u16 index, u8 op, u8 update)
5230 {
5231         u32 igu_addr = bp->igu_base_addr;
5232         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5233         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5234                              igu_addr);
5235 }
5236
5237 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5238 {
5239         /* No memory barriers */
5240         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5241         mmiowb(); /* keep prod updates ordered */
5242 }
5243
5244 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5245                                       union event_ring_elem *elem)
5246 {
5247         u8 err = elem->message.error;
5248
5249         if (!bp->cnic_eth_dev.starting_cid  ||
5250             (cid < bp->cnic_eth_dev.starting_cid &&
5251             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5252                 return 1;
5253
5254         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5255
5256         if (unlikely(err)) {
5257
5258                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5259                           cid);
5260                 bnx2x_panic_dump(bp, false);
5261         }
5262         bnx2x_cnic_cfc_comp(bp, cid, err);
5263         return 0;
5264 }
5265
5266 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5267 {
5268         struct bnx2x_mcast_ramrod_params rparam;
5269         int rc;
5270
5271         memset(&rparam, 0, sizeof(rparam));
5272
5273         rparam.mcast_obj = &bp->mcast_obj;
5274
5275         netif_addr_lock_bh(bp->dev);
5276
5277         /* Clear pending state for the last command */
5278         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5279
5280         /* If there are pending mcast commands - send them */
5281         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5282                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5283                 if (rc < 0)
5284                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5285                                   rc);
5286         }
5287
5288         netif_addr_unlock_bh(bp->dev);
5289 }
5290
5291 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5292                                             union event_ring_elem *elem)
5293 {
5294         unsigned long ramrod_flags = 0;
5295         int rc = 0;
5296         u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5297         u32 cid = echo & BNX2X_SWCID_MASK;
5298         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5299
5300         /* Always push next commands out, don't wait here */
5301         __set_bit(RAMROD_CONT, &ramrod_flags);
5302
5303         switch (echo >> BNX2X_SWCID_SHIFT) {
5304         case BNX2X_FILTER_MAC_PENDING:
5305                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5306                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5307                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5308                 else
5309                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5310
5311                 break;
5312         case BNX2X_FILTER_VLAN_PENDING:
5313                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5314                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5315                 break;
5316         case BNX2X_FILTER_MCAST_PENDING:
5317                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5318                 /* This is only relevant for 57710 where multicast MACs are
5319                  * configured as unicast MACs using the same ramrod.
5320                  */
5321                 bnx2x_handle_mcast_eqe(bp);
5322                 return;
5323         default:
5324                 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
5325                 return;
5326         }
5327
5328         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5329
5330         if (rc < 0)
5331                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5332         else if (rc > 0)
5333                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5334 }
5335
5336 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5337
5338 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5339 {
5340         netif_addr_lock_bh(bp->dev);
5341
5342         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5343
5344         /* Send rx_mode command again if was requested */
5345         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5346                 bnx2x_set_storm_rx_mode(bp);
5347         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5348                                     &bp->sp_state))
5349                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5350         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5351                                     &bp->sp_state))
5352                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5353
5354         netif_addr_unlock_bh(bp->dev);
5355 }
5356
5357 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5358                                               union event_ring_elem *elem)
5359 {
5360         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5361                 DP(BNX2X_MSG_SP,
5362                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5363                    elem->message.data.vif_list_event.func_bit_map);
5364                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5365                         elem->message.data.vif_list_event.func_bit_map);
5366         } else if (elem->message.data.vif_list_event.echo ==
5367                    VIF_LIST_RULE_SET) {
5368                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5369                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5370         }
5371 }
5372
5373 /* called with rtnl_lock */
5374 static void bnx2x_after_function_update(struct bnx2x *bp)
5375 {
5376         int q, rc;
5377         struct bnx2x_fastpath *fp;
5378         struct bnx2x_queue_state_params queue_params = {NULL};
5379         struct bnx2x_queue_update_params *q_update_params =
5380                 &queue_params.params.update;
5381
5382         /* Send Q update command with afex vlan removal values for all Qs */
5383         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5384
5385         /* set silent vlan removal values according to vlan mode */
5386         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5387                   &q_update_params->update_flags);
5388         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5389                   &q_update_params->update_flags);
5390         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5391
5392         /* in access mode mark mask and value are 0 to strip all vlans */
5393         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5394                 q_update_params->silent_removal_value = 0;
5395                 q_update_params->silent_removal_mask = 0;
5396         } else {
5397                 q_update_params->silent_removal_value =
5398                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5399                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5400         }
5401
5402         for_each_eth_queue(bp, q) {
5403                 /* Set the appropriate Queue object */
5404                 fp = &bp->fp[q];
5405                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5406
5407                 /* send the ramrod */
5408                 rc = bnx2x_queue_state_change(bp, &queue_params);
5409                 if (rc < 0)
5410                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5411                                   q);
5412         }
5413
5414         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5415                 fp = &bp->fp[FCOE_IDX(bp)];
5416                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5417
5418                 /* clear pending completion bit */
5419                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5420
5421                 /* mark latest Q bit */
5422                 smp_mb__before_atomic();
5423                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5424                 smp_mb__after_atomic();
5425
5426                 /* send Q update ramrod for FCoE Q */
5427                 rc = bnx2x_queue_state_change(bp, &queue_params);
5428                 if (rc < 0)
5429                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5430                                   q);
5431         } else {
5432                 /* If no FCoE ring - ACK MCP now */
5433                 bnx2x_link_report(bp);
5434                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5435         }
5436 }
5437
5438 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5439         struct bnx2x *bp, u32 cid)
5440 {
5441         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5442
5443         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5444                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5445         else
5446                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5447 }
5448
5449 static void bnx2x_eq_int(struct bnx2x *bp)
5450 {
5451         u16 hw_cons, sw_cons, sw_prod;
5452         union event_ring_elem *elem;
5453         u8 echo;
5454         u32 cid;
5455         u8 opcode;
5456         int rc, spqe_cnt = 0;
5457         struct bnx2x_queue_sp_obj *q_obj;
5458         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5459         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5460
5461         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5462
5463         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5464          * when we get the next-page we need to adjust so the loop
5465          * condition below will be met. The next element is the size of a
5466          * regular element and hence incrementing by 1
5467          */
5468         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5469                 hw_cons++;
5470
5471         /* This function may never run in parallel with itself for a
5472          * specific bp, thus there is no need in "paired" read memory
5473          * barrier here.
5474          */
5475         sw_cons = bp->eq_cons;
5476         sw_prod = bp->eq_prod;
5477
5478         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5479                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5480
5481         for (; sw_cons != hw_cons;
5482               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5483
5484                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5485
5486                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5487                 if (!rc) {
5488                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5489                            rc);
5490                         goto next_spqe;
5491                 }
5492
5493                 opcode = elem->message.opcode;
5494
5495                 /* handle eq element */
5496                 switch (opcode) {
5497                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5498                         bnx2x_vf_mbx_schedule(bp,
5499                                               &elem->message.data.vf_pf_event);
5500                         continue;
5501
5502                 case EVENT_RING_OPCODE_STAT_QUERY:
5503                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5504                                "got statistics comp event %d\n",
5505                                bp->stats_comp++);
5506                         /* nothing to do with stats comp */
5507                         goto next_spqe;
5508
5509                 case EVENT_RING_OPCODE_CFC_DEL:
5510                         /* handle according to cid range */
5511                         /*
5512                          * we may want to verify here that the bp state is
5513                          * HALTING
5514                          */
5515
5516                         /* elem CID originates from FW; actually LE */
5517                         cid = SW_CID(elem->message.data.cfc_del_event.cid);
5518
5519                         DP(BNX2X_MSG_SP,
5520                            "got delete ramrod for MULTI[%d]\n", cid);
5521
5522                         if (CNIC_LOADED(bp) &&
5523                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5524                                 goto next_spqe;
5525
5526                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5527
5528                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5529                                 break;
5530
5531                         goto next_spqe;
5532
5533                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5534                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5535                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5536                         if (f_obj->complete_cmd(bp, f_obj,
5537                                                 BNX2X_F_CMD_TX_STOP))
5538                                 break;
5539                         goto next_spqe;
5540
5541                 case EVENT_RING_OPCODE_START_TRAFFIC:
5542                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5543                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5544                         if (f_obj->complete_cmd(bp, f_obj,
5545                                                 BNX2X_F_CMD_TX_START))
5546                                 break;
5547                         goto next_spqe;
5548
5549                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5550                         echo = elem->message.data.function_update_event.echo;
5551                         if (echo == SWITCH_UPDATE) {
5552                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5553                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5554                                 if (f_obj->complete_cmd(
5555                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5556                                         break;
5557
5558                         } else {
5559                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5560
5561                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5562                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5563                                 f_obj->complete_cmd(bp, f_obj,
5564                                                     BNX2X_F_CMD_AFEX_UPDATE);
5565
5566                                 /* We will perform the Queues update from
5567                                  * sp_rtnl task as all Queue SP operations
5568                                  * should run under rtnl_lock.
5569                                  */
5570                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5571                         }
5572
5573                         goto next_spqe;
5574
5575                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5576                         f_obj->complete_cmd(bp, f_obj,
5577                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5578                         bnx2x_after_afex_vif_lists(bp, elem);
5579                         goto next_spqe;
5580                 case EVENT_RING_OPCODE_FUNCTION_START:
5581                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5582                            "got FUNC_START ramrod\n");
5583                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5584                                 break;
5585
5586                         goto next_spqe;
5587
5588                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5589                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5590                            "got FUNC_STOP ramrod\n");
5591                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5592                                 break;
5593
5594                         goto next_spqe;
5595
5596                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5597                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5598                            "got set_timesync ramrod completion\n");
5599                         if (f_obj->complete_cmd(bp, f_obj,
5600                                                 BNX2X_F_CMD_SET_TIMESYNC))
5601                                 break;
5602                         goto next_spqe;
5603                 }
5604
5605                 switch (opcode | bp->state) {
5606                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5607                       BNX2X_STATE_OPEN):
5608                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5609                       BNX2X_STATE_OPENING_WAIT4_PORT):
5610                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5611                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5612                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5613                            SW_CID(elem->message.data.eth_event.echo));
5614                         rss_raw->clear_pending(rss_raw);
5615                         break;
5616
5617                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5618                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5619                 case (EVENT_RING_OPCODE_SET_MAC |
5620                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5621                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5622                       BNX2X_STATE_OPEN):
5623                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5624                       BNX2X_STATE_DIAG):
5625                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5626                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5627                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5628                         bnx2x_handle_classification_eqe(bp, elem);
5629                         break;
5630
5631                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5632                       BNX2X_STATE_OPEN):
5633                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5634                       BNX2X_STATE_DIAG):
5635                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5636                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5637                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5638                         bnx2x_handle_mcast_eqe(bp);
5639                         break;
5640
5641                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5642                       BNX2X_STATE_OPEN):
5643                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5644                       BNX2X_STATE_DIAG):
5645                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5646                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5647                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5648                         bnx2x_handle_rx_mode_eqe(bp);
5649                         break;
5650                 default:
5651                         /* unknown event log error and continue */
5652                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5653                                   elem->message.opcode, bp->state);
5654                 }
5655 next_spqe:
5656                 spqe_cnt++;
5657         } /* for */
5658
5659         smp_mb__before_atomic();
5660         atomic_add(spqe_cnt, &bp->eq_spq_left);
5661
5662         bp->eq_cons = sw_cons;
5663         bp->eq_prod = sw_prod;
5664         /* Make sure that above mem writes were issued towards the memory */
5665         smp_wmb();
5666
5667         /* update producer */
5668         bnx2x_update_eq_prod(bp, bp->eq_prod);
5669 }
5670
5671 static void bnx2x_sp_task(struct work_struct *work)
5672 {
5673         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5674
5675         DP(BNX2X_MSG_SP, "sp task invoked\n");
5676
5677         /* make sure the atomic interrupt_occurred has been written */
5678         smp_rmb();
5679         if (atomic_read(&bp->interrupt_occurred)) {
5680
5681                 /* what work needs to be performed? */
5682                 u16 status = bnx2x_update_dsb_idx(bp);
5683
5684                 DP(BNX2X_MSG_SP, "status %x\n", status);
5685                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5686                 atomic_set(&bp->interrupt_occurred, 0);
5687
5688                 /* HW attentions */
5689                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5690                         bnx2x_attn_int(bp);
5691                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5692                 }
5693
5694                 /* SP events: STAT_QUERY and others */
5695                 if (status & BNX2X_DEF_SB_IDX) {
5696                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5697
5698                         if (FCOE_INIT(bp) &&
5699                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5700                                 /* Prevent local bottom-halves from running as
5701                                  * we are going to change the local NAPI list.
5702                                  */
5703                                 local_bh_disable();
5704                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5705                                 local_bh_enable();
5706                         }
5707
5708                         /* Handle EQ completions */
5709                         bnx2x_eq_int(bp);
5710                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5711                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5712
5713                         status &= ~BNX2X_DEF_SB_IDX;
5714                 }
5715
5716                 /* if status is non zero then perhaps something went wrong */
5717                 if (unlikely(status))
5718                         DP(BNX2X_MSG_SP,
5719                            "got an unknown interrupt! (status 0x%x)\n", status);
5720
5721                 /* ack status block only if something was actually handled */
5722                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5723                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5724         }
5725
5726         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5727         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5728                                &bp->sp_state)) {
5729                 bnx2x_link_report(bp);
5730                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5731         }
5732 }
5733
5734 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5735 {
5736         struct net_device *dev = dev_instance;
5737         struct bnx2x *bp = netdev_priv(dev);
5738
5739         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5740                      IGU_INT_DISABLE, 0);
5741
5742 #ifdef BNX2X_STOP_ON_ERROR
5743         if (unlikely(bp->panic))
5744                 return IRQ_HANDLED;
5745 #endif
5746
5747         if (CNIC_LOADED(bp)) {
5748                 struct cnic_ops *c_ops;
5749
5750                 rcu_read_lock();
5751                 c_ops = rcu_dereference(bp->cnic_ops);
5752                 if (c_ops)
5753                         c_ops->cnic_handler(bp->cnic_data, NULL);
5754                 rcu_read_unlock();
5755         }
5756
5757         /* schedule sp task to perform default status block work, ack
5758          * attentions and enable interrupts.
5759          */
5760         bnx2x_schedule_sp_task(bp);
5761
5762         return IRQ_HANDLED;
5763 }
5764
5765 /* end of slow path */
5766
5767 void bnx2x_drv_pulse(struct bnx2x *bp)
5768 {
5769         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5770                  bp->fw_drv_pulse_wr_seq);
5771 }
5772
5773 static void bnx2x_timer(unsigned long data)
5774 {
5775         struct bnx2x *bp = (struct bnx2x *) data;
5776
5777         if (!netif_running(bp->dev))
5778                 return;
5779
5780         if (IS_PF(bp) &&
5781             !BP_NOMCP(bp)) {
5782                 int mb_idx = BP_FW_MB_IDX(bp);
5783                 u16 drv_pulse;
5784                 u16 mcp_pulse;
5785
5786                 ++bp->fw_drv_pulse_wr_seq;
5787                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5788                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5789                 bnx2x_drv_pulse(bp);
5790
5791                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5792                              MCP_PULSE_SEQ_MASK);
5793                 /* The delta between driver pulse and mcp response
5794                  * should not get too big. If the MFW is more than 5 pulses
5795                  * behind, we should worry about it enough to generate an error
5796                  * log.
5797                  */
5798                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5799                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5800                                   drv_pulse, mcp_pulse);
5801         }
5802
5803         if (bp->state == BNX2X_STATE_OPEN)
5804                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5805
5806         /* sample pf vf bulletin board for new posts from pf */
5807         if (IS_VF(bp))
5808                 bnx2x_timer_sriov(bp);
5809
5810         mod_timer(&bp->timer, jiffies + bp->current_interval);
5811 }
5812
5813 /* end of Statistics */
5814
5815 /* nic init */
5816
5817 /*
5818  * nic init service functions
5819  */
5820
5821 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5822 {
5823         u32 i;
5824         if (!(len%4) && !(addr%4))
5825                 for (i = 0; i < len; i += 4)
5826                         REG_WR(bp, addr + i, fill);
5827         else
5828                 for (i = 0; i < len; i++)
5829                         REG_WR8(bp, addr + i, fill);
5830 }
5831
5832 /* helper: writes FP SP data to FW - data_size in dwords */
5833 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5834                                 int fw_sb_id,
5835                                 u32 *sb_data_p,
5836                                 u32 data_size)
5837 {
5838         int index;
5839         for (index = 0; index < data_size; index++)
5840                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5841                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5842                         sizeof(u32)*index,
5843                         *(sb_data_p + index));
5844 }
5845
5846 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5847 {
5848         u32 *sb_data_p;
5849         u32 data_size = 0;
5850         struct hc_status_block_data_e2 sb_data_e2;
5851         struct hc_status_block_data_e1x sb_data_e1x;
5852
5853         /* disable the function first */
5854         if (!CHIP_IS_E1x(bp)) {
5855                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5856                 sb_data_e2.common.state = SB_DISABLED;
5857                 sb_data_e2.common.p_func.vf_valid = false;
5858                 sb_data_p = (u32 *)&sb_data_e2;
5859                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5860         } else {
5861                 memset(&sb_data_e1x, 0,
5862                        sizeof(struct hc_status_block_data_e1x));
5863                 sb_data_e1x.common.state = SB_DISABLED;
5864                 sb_data_e1x.common.p_func.vf_valid = false;
5865                 sb_data_p = (u32 *)&sb_data_e1x;
5866                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5867         }
5868         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5869
5870         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5871                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5872                         CSTORM_STATUS_BLOCK_SIZE);
5873         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5874                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5875                         CSTORM_SYNC_BLOCK_SIZE);
5876 }
5877
5878 /* helper:  writes SP SB data to FW */
5879 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5880                 struct hc_sp_status_block_data *sp_sb_data)
5881 {
5882         int func = BP_FUNC(bp);
5883         int i;
5884         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5885                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5886                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5887                         i*sizeof(u32),
5888                         *((u32 *)sp_sb_data + i));
5889 }
5890
5891 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5892 {
5893         int func = BP_FUNC(bp);
5894         struct hc_sp_status_block_data sp_sb_data;
5895         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5896
5897         sp_sb_data.state = SB_DISABLED;
5898         sp_sb_data.p_func.vf_valid = false;
5899
5900         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5901
5902         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5903                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5904                         CSTORM_SP_STATUS_BLOCK_SIZE);
5905         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5906                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5907                         CSTORM_SP_SYNC_BLOCK_SIZE);
5908 }
5909
5910 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5911                                            int igu_sb_id, int igu_seg_id)
5912 {
5913         hc_sm->igu_sb_id = igu_sb_id;
5914         hc_sm->igu_seg_id = igu_seg_id;
5915         hc_sm->timer_value = 0xFF;
5916         hc_sm->time_to_expire = 0xFFFFFFFF;
5917 }
5918
5919 /* allocates state machine ids. */
5920 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5921 {
5922         /* zero out state machine indices */
5923         /* rx indices */
5924         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5925
5926         /* tx indices */
5927         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5928         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5929         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5930         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5931
5932         /* map indices */
5933         /* rx indices */
5934         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5935                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5936
5937         /* tx indices */
5938         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5939                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5940         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5941                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5942         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5943                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5944         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5945                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5946 }
5947
5948 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5949                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5950 {
5951         int igu_seg_id;
5952
5953         struct hc_status_block_data_e2 sb_data_e2;
5954         struct hc_status_block_data_e1x sb_data_e1x;
5955         struct hc_status_block_sm  *hc_sm_p;
5956         int data_size;
5957         u32 *sb_data_p;
5958
5959         if (CHIP_INT_MODE_IS_BC(bp))
5960                 igu_seg_id = HC_SEG_ACCESS_NORM;
5961         else
5962                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5963
5964         bnx2x_zero_fp_sb(bp, fw_sb_id);
5965
5966         if (!CHIP_IS_E1x(bp)) {
5967                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5968                 sb_data_e2.common.state = SB_ENABLED;
5969                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5970                 sb_data_e2.common.p_func.vf_id = vfid;
5971                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5972                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5973                 sb_data_e2.common.same_igu_sb_1b = true;
5974                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5975                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5976                 hc_sm_p = sb_data_e2.common.state_machine;
5977                 sb_data_p = (u32 *)&sb_data_e2;
5978                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5979                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5980         } else {
5981                 memset(&sb_data_e1x, 0,
5982                        sizeof(struct hc_status_block_data_e1x));
5983                 sb_data_e1x.common.state = SB_ENABLED;
5984                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5985                 sb_data_e1x.common.p_func.vf_id = 0xff;
5986                 sb_data_e1x.common.p_func.vf_valid = false;
5987                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5988                 sb_data_e1x.common.same_igu_sb_1b = true;
5989                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5990                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5991                 hc_sm_p = sb_data_e1x.common.state_machine;
5992                 sb_data_p = (u32 *)&sb_data_e1x;
5993                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5994                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5995         }
5996
5997         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5998                                        igu_sb_id, igu_seg_id);
5999         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
6000                                        igu_sb_id, igu_seg_id);
6001
6002         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
6003
6004         /* write indices to HW - PCI guarantees endianity of regpairs */
6005         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
6006 }
6007
6008 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6009                                      u16 tx_usec, u16 rx_usec)
6010 {
6011         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6012                                     false, rx_usec);
6013         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6014                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6015                                        tx_usec);
6016         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6017                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6018                                        tx_usec);
6019         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6020                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6021                                        tx_usec);
6022 }
6023
6024 static void bnx2x_init_def_sb(struct bnx2x *bp)
6025 {
6026         struct host_sp_status_block *def_sb = bp->def_status_blk;
6027         dma_addr_t mapping = bp->def_status_blk_mapping;
6028         int igu_sp_sb_index;
6029         int igu_seg_id;
6030         int port = BP_PORT(bp);
6031         int func = BP_FUNC(bp);
6032         int reg_offset, reg_offset_en5;
6033         u64 section;
6034         int index;
6035         struct hc_sp_status_block_data sp_sb_data;
6036         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6037
6038         if (CHIP_INT_MODE_IS_BC(bp)) {
6039                 igu_sp_sb_index = DEF_SB_IGU_ID;
6040                 igu_seg_id = HC_SEG_ACCESS_DEF;
6041         } else {
6042                 igu_sp_sb_index = bp->igu_dsb_id;
6043                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6044         }
6045
6046         /* ATTN */
6047         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6048                                             atten_status_block);
6049         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6050
6051         bp->attn_state = 0;
6052
6053         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6054                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6055         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6056                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6057         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6058                 int sindex;
6059                 /* take care of sig[0]..sig[4] */
6060                 for (sindex = 0; sindex < 4; sindex++)
6061                         bp->attn_group[index].sig[sindex] =
6062                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6063
6064                 if (!CHIP_IS_E1x(bp))
6065                         /*
6066                          * enable5 is separate from the rest of the registers,
6067                          * and therefore the address skip is 4
6068                          * and not 16 between the different groups
6069                          */
6070                         bp->attn_group[index].sig[4] = REG_RD(bp,
6071                                         reg_offset_en5 + 0x4*index);
6072                 else
6073                         bp->attn_group[index].sig[4] = 0;
6074         }
6075
6076         if (bp->common.int_block == INT_BLOCK_HC) {
6077                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6078                                      HC_REG_ATTN_MSG0_ADDR_L);
6079
6080                 REG_WR(bp, reg_offset, U64_LO(section));
6081                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6082         } else if (!CHIP_IS_E1x(bp)) {
6083                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6084                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6085         }
6086
6087         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6088                                             sp_sb);
6089
6090         bnx2x_zero_sp_sb(bp);
6091
6092         /* PCI guarantees endianity of regpairs */
6093         sp_sb_data.state                = SB_ENABLED;
6094         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6095         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6096         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6097         sp_sb_data.igu_seg_id           = igu_seg_id;
6098         sp_sb_data.p_func.pf_id         = func;
6099         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6100         sp_sb_data.p_func.vf_id         = 0xff;
6101
6102         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6103
6104         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6105 }
6106
6107 void bnx2x_update_coalesce(struct bnx2x *bp)
6108 {
6109         int i;
6110
6111         for_each_eth_queue(bp, i)
6112                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6113                                          bp->tx_ticks, bp->rx_ticks);
6114 }
6115
6116 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6117 {
6118         spin_lock_init(&bp->spq_lock);
6119         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6120
6121         bp->spq_prod_idx = 0;
6122         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6123         bp->spq_prod_bd = bp->spq;
6124         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6125 }
6126
6127 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6128 {
6129         int i;
6130         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6131                 union event_ring_elem *elem =
6132                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6133
6134                 elem->next_page.addr.hi =
6135                         cpu_to_le32(U64_HI(bp->eq_mapping +
6136                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6137                 elem->next_page.addr.lo =
6138                         cpu_to_le32(U64_LO(bp->eq_mapping +
6139                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6140         }
6141         bp->eq_cons = 0;
6142         bp->eq_prod = NUM_EQ_DESC;
6143         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6144         /* we want a warning message before it gets wrought... */
6145         atomic_set(&bp->eq_spq_left,
6146                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6147 }
6148
6149 /* called with netif_addr_lock_bh() */
6150 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6151                                unsigned long rx_mode_flags,
6152                                unsigned long rx_accept_flags,
6153                                unsigned long tx_accept_flags,
6154                                unsigned long ramrod_flags)
6155 {
6156         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6157         int rc;
6158
6159         memset(&ramrod_param, 0, sizeof(ramrod_param));
6160
6161         /* Prepare ramrod parameters */
6162         ramrod_param.cid = 0;
6163         ramrod_param.cl_id = cl_id;
6164         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6165         ramrod_param.func_id = BP_FUNC(bp);
6166
6167         ramrod_param.pstate = &bp->sp_state;
6168         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6169
6170         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6171         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6172
6173         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6174
6175         ramrod_param.ramrod_flags = ramrod_flags;
6176         ramrod_param.rx_mode_flags = rx_mode_flags;
6177
6178         ramrod_param.rx_accept_flags = rx_accept_flags;
6179         ramrod_param.tx_accept_flags = tx_accept_flags;
6180
6181         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6182         if (rc < 0) {
6183                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6184                 return rc;
6185         }
6186
6187         return 0;
6188 }
6189
6190 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6191                                    unsigned long *rx_accept_flags,
6192                                    unsigned long *tx_accept_flags)
6193 {
6194         /* Clear the flags first */
6195         *rx_accept_flags = 0;
6196         *tx_accept_flags = 0;
6197
6198         switch (rx_mode) {
6199         case BNX2X_RX_MODE_NONE:
6200                 /*
6201                  * 'drop all' supersedes any accept flags that may have been
6202                  * passed to the function.
6203                  */
6204                 break;
6205         case BNX2X_RX_MODE_NORMAL:
6206                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6207                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6208                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6209
6210                 /* internal switching mode */
6211                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6212                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6213                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6214
6215                 if (bp->accept_any_vlan) {
6216                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6217                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6218                 }
6219
6220                 break;
6221         case BNX2X_RX_MODE_ALLMULTI:
6222                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6223                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6224                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6225
6226                 /* internal switching mode */
6227                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6228                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6229                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6230
6231                 if (bp->accept_any_vlan) {
6232                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6233                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6234                 }
6235
6236                 break;
6237         case BNX2X_RX_MODE_PROMISC:
6238                 /* According to definition of SI mode, iface in promisc mode
6239                  * should receive matched and unmatched (in resolution of port)
6240                  * unicast packets.
6241                  */
6242                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6243                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6244                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6245                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6246
6247                 /* internal switching mode */
6248                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6249                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6250
6251                 if (IS_MF_SI(bp))
6252                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6253                 else
6254                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6255
6256                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6257                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6258
6259                 break;
6260         default:
6261                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6262                 return -EINVAL;
6263         }
6264
6265         return 0;
6266 }
6267
6268 /* called with netif_addr_lock_bh() */
6269 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6270 {
6271         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6272         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6273         int rc;
6274
6275         if (!NO_FCOE(bp))
6276                 /* Configure rx_mode of FCoE Queue */
6277                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6278
6279         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6280                                      &tx_accept_flags);
6281         if (rc)
6282                 return rc;
6283
6284         __set_bit(RAMROD_RX, &ramrod_flags);
6285         __set_bit(RAMROD_TX, &ramrod_flags);
6286
6287         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6288                                    rx_accept_flags, tx_accept_flags,
6289                                    ramrod_flags);
6290 }
6291
6292 static void bnx2x_init_internal_common(struct bnx2x *bp)
6293 {
6294         int i;
6295
6296         /* Zero this manually as its initialization is
6297            currently missing in the initTool */
6298         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6299                 REG_WR(bp, BAR_USTRORM_INTMEM +
6300                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6301         if (!CHIP_IS_E1x(bp)) {
6302                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6303                         CHIP_INT_MODE_IS_BC(bp) ?
6304                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6305         }
6306 }
6307
6308 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6309 {
6310         switch (load_code) {
6311         case FW_MSG_CODE_DRV_LOAD_COMMON:
6312         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6313                 bnx2x_init_internal_common(bp);
6314                 /* no break */
6315
6316         case FW_MSG_CODE_DRV_LOAD_PORT:
6317                 /* nothing to do */
6318                 /* no break */
6319
6320         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6321                 /* internal memory per function is
6322                    initialized inside bnx2x_pf_init */
6323                 break;
6324
6325         default:
6326                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6327                 break;
6328         }
6329 }
6330
6331 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6332 {
6333         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6334 }
6335
6336 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6337 {
6338         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6339 }
6340
6341 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6342 {
6343         if (CHIP_IS_E1x(fp->bp))
6344                 return BP_L_ID(fp->bp) + fp->index;
6345         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6346                 return bnx2x_fp_igu_sb_id(fp);
6347 }
6348
6349 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6350 {
6351         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6352         u8 cos;
6353         unsigned long q_type = 0;
6354         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6355         fp->rx_queue = fp_idx;
6356         fp->cid = fp_idx;
6357         fp->cl_id = bnx2x_fp_cl_id(fp);
6358         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6359         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6360         /* qZone id equals to FW (per path) client id */
6361         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6362
6363         /* init shortcut */
6364         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6365
6366         /* Setup SB indices */
6367         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6368
6369         /* Configure Queue State object */
6370         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6371         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6372
6373         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6374
6375         /* init tx data */
6376         for_each_cos_in_tx_queue(fp, cos) {
6377                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6378                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6379                                   FP_COS_TO_TXQ(fp, cos, bp),
6380                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6381                 cids[cos] = fp->txdata_ptr[cos]->cid;
6382         }
6383
6384         /* nothing more for vf to do here */
6385         if (IS_VF(bp))
6386                 return;
6387
6388         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6389                       fp->fw_sb_id, fp->igu_sb_id);
6390         bnx2x_update_fpsb_idx(fp);
6391         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6392                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6393                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6394
6395         /**
6396          * Configure classification DBs: Always enable Tx switching
6397          */
6398         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6399
6400         DP(NETIF_MSG_IFUP,
6401            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6402            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6403            fp->igu_sb_id);
6404 }
6405
6406 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6407 {
6408         int i;
6409
6410         for (i = 1; i <= NUM_TX_RINGS; i++) {
6411                 struct eth_tx_next_bd *tx_next_bd =
6412                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6413
6414                 tx_next_bd->addr_hi =
6415                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6416                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6417                 tx_next_bd->addr_lo =
6418                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6419                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6420         }
6421
6422         *txdata->tx_cons_sb = cpu_to_le16(0);
6423
6424         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6425         txdata->tx_db.data.zero_fill1 = 0;
6426         txdata->tx_db.data.prod = 0;
6427
6428         txdata->tx_pkt_prod = 0;
6429         txdata->tx_pkt_cons = 0;
6430         txdata->tx_bd_prod = 0;
6431         txdata->tx_bd_cons = 0;
6432         txdata->tx_pkt = 0;
6433 }
6434
6435 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6436 {
6437         int i;
6438
6439         for_each_tx_queue_cnic(bp, i)
6440                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6441 }
6442
6443 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6444 {
6445         int i;
6446         u8 cos;
6447
6448         for_each_eth_queue(bp, i)
6449                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6450                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6451 }
6452
6453 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6454 {
6455         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6456         unsigned long q_type = 0;
6457
6458         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6459         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6460                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6461         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6462         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6463         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6464         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6465         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6466                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6467                           fp);
6468
6469         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6470
6471         /* qZone id equals to FW (per path) client id */
6472         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6473         /* init shortcut */
6474         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6475                 bnx2x_rx_ustorm_prods_offset(fp);
6476
6477         /* Configure Queue State object */
6478         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6479         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6480
6481         /* No multi-CoS for FCoE L2 client */
6482         BUG_ON(fp->max_cos != 1);
6483
6484         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6485                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6486                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6487
6488         DP(NETIF_MSG_IFUP,
6489            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6490            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6491            fp->igu_sb_id);
6492 }
6493
6494 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6495 {
6496         if (!NO_FCOE(bp))
6497                 bnx2x_init_fcoe_fp(bp);
6498
6499         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6500                       BNX2X_VF_ID_INVALID, false,
6501                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6502
6503         /* ensure status block indices were read */
6504         rmb();
6505         bnx2x_init_rx_rings_cnic(bp);
6506         bnx2x_init_tx_rings_cnic(bp);
6507
6508         /* flush all */
6509         mb();
6510         mmiowb();
6511 }
6512
6513 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6514 {
6515         int i;
6516
6517         /* Setup NIC internals and enable interrupts */
6518         for_each_eth_queue(bp, i)
6519                 bnx2x_init_eth_fp(bp, i);
6520
6521         /* ensure status block indices were read */
6522         rmb();
6523         bnx2x_init_rx_rings(bp);
6524         bnx2x_init_tx_rings(bp);
6525
6526         if (IS_PF(bp)) {
6527                 /* Initialize MOD_ABS interrupts */
6528                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6529                                        bp->common.shmem_base,
6530                                        bp->common.shmem2_base, BP_PORT(bp));
6531
6532                 /* initialize the default status block and sp ring */
6533                 bnx2x_init_def_sb(bp);
6534                 bnx2x_update_dsb_idx(bp);
6535                 bnx2x_init_sp_ring(bp);
6536         } else {
6537                 bnx2x_memset_stats(bp);
6538         }
6539 }
6540
6541 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6542 {
6543         bnx2x_init_eq_ring(bp);
6544         bnx2x_init_internal(bp, load_code);
6545         bnx2x_pf_init(bp);
6546         bnx2x_stats_init(bp);
6547
6548         /* flush all before enabling interrupts */
6549         mb();
6550         mmiowb();
6551
6552         bnx2x_int_enable(bp);
6553
6554         /* Check for SPIO5 */
6555         bnx2x_attn_int_deasserted0(bp,
6556                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6557                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6558 }
6559
6560 /* gzip service functions */
6561 static int bnx2x_gunzip_init(struct bnx2x *bp)
6562 {
6563         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6564                                             &bp->gunzip_mapping, GFP_KERNEL);
6565         if (bp->gunzip_buf  == NULL)
6566                 goto gunzip_nomem1;
6567
6568         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6569         if (bp->strm  == NULL)
6570                 goto gunzip_nomem2;
6571
6572         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6573         if (bp->strm->workspace == NULL)
6574                 goto gunzip_nomem3;
6575
6576         return 0;
6577
6578 gunzip_nomem3:
6579         kfree(bp->strm);
6580         bp->strm = NULL;
6581
6582 gunzip_nomem2:
6583         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6584                           bp->gunzip_mapping);
6585         bp->gunzip_buf = NULL;
6586
6587 gunzip_nomem1:
6588         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6589         return -ENOMEM;
6590 }
6591
6592 static void bnx2x_gunzip_end(struct bnx2x *bp)
6593 {
6594         if (bp->strm) {
6595                 vfree(bp->strm->workspace);
6596                 kfree(bp->strm);
6597                 bp->strm = NULL;
6598         }
6599
6600         if (bp->gunzip_buf) {
6601                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6602                                   bp->gunzip_mapping);
6603                 bp->gunzip_buf = NULL;
6604         }
6605 }
6606
6607 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6608 {
6609         int n, rc;
6610
6611         /* check gzip header */
6612         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6613                 BNX2X_ERR("Bad gzip header\n");
6614                 return -EINVAL;
6615         }
6616
6617         n = 10;
6618
6619 #define FNAME                           0x8
6620
6621         if (zbuf[3] & FNAME)
6622                 while ((zbuf[n++] != 0) && (n < len));
6623
6624         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6625         bp->strm->avail_in = len - n;
6626         bp->strm->next_out = bp->gunzip_buf;
6627         bp->strm->avail_out = FW_BUF_SIZE;
6628
6629         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6630         if (rc != Z_OK)
6631                 return rc;
6632
6633         rc = zlib_inflate(bp->strm, Z_FINISH);
6634         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6635                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6636                            bp->strm->msg);
6637
6638         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6639         if (bp->gunzip_outlen & 0x3)
6640                 netdev_err(bp->dev,
6641                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6642                                 bp->gunzip_outlen);
6643         bp->gunzip_outlen >>= 2;
6644
6645         zlib_inflateEnd(bp->strm);
6646
6647         if (rc == Z_STREAM_END)
6648                 return 0;
6649
6650         return rc;
6651 }
6652
6653 /* nic load/unload */
6654
6655 /*
6656  * General service functions
6657  */
6658
6659 /* send a NIG loopback debug packet */
6660 static void bnx2x_lb_pckt(struct bnx2x *bp)
6661 {
6662         u32 wb_write[3];
6663
6664         /* Ethernet source and destination addresses */
6665         wb_write[0] = 0x55555555;
6666         wb_write[1] = 0x55555555;
6667         wb_write[2] = 0x20;             /* SOP */
6668         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6669
6670         /* NON-IP protocol */
6671         wb_write[0] = 0x09000000;
6672         wb_write[1] = 0x55555555;
6673         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6674         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6675 }
6676
6677 /* some of the internal memories
6678  * are not directly readable from the driver
6679  * to test them we send debug packets
6680  */
6681 static int bnx2x_int_mem_test(struct bnx2x *bp)
6682 {
6683         int factor;
6684         int count, i;
6685         u32 val = 0;
6686
6687         if (CHIP_REV_IS_FPGA(bp))
6688                 factor = 120;
6689         else if (CHIP_REV_IS_EMUL(bp))
6690                 factor = 200;
6691         else
6692                 factor = 1;
6693
6694         /* Disable inputs of parser neighbor blocks */
6695         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6696         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6697         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6698         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6699
6700         /*  Write 0 to parser credits for CFC search request */
6701         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6702
6703         /* send Ethernet packet */
6704         bnx2x_lb_pckt(bp);
6705
6706         /* TODO do i reset NIG statistic? */
6707         /* Wait until NIG register shows 1 packet of size 0x10 */
6708         count = 1000 * factor;
6709         while (count) {
6710
6711                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6712                 val = *bnx2x_sp(bp, wb_data[0]);
6713                 if (val == 0x10)
6714                         break;
6715
6716                 usleep_range(10000, 20000);
6717                 count--;
6718         }
6719         if (val != 0x10) {
6720                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6721                 return -1;
6722         }
6723
6724         /* Wait until PRS register shows 1 packet */
6725         count = 1000 * factor;
6726         while (count) {
6727                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6728                 if (val == 1)
6729                         break;
6730
6731                 usleep_range(10000, 20000);
6732                 count--;
6733         }
6734         if (val != 0x1) {
6735                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6736                 return -2;
6737         }
6738
6739         /* Reset and init BRB, PRS */
6740         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6741         msleep(50);
6742         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6743         msleep(50);
6744         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6745         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6746
6747         DP(NETIF_MSG_HW, "part2\n");
6748
6749         /* Disable inputs of parser neighbor blocks */
6750         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6751         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6752         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6753         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6754
6755         /* Write 0 to parser credits for CFC search request */
6756         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6757
6758         /* send 10 Ethernet packets */
6759         for (i = 0; i < 10; i++)
6760                 bnx2x_lb_pckt(bp);
6761
6762         /* Wait until NIG register shows 10 + 1
6763            packets of size 11*0x10 = 0xb0 */
6764         count = 1000 * factor;
6765         while (count) {
6766
6767                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6768                 val = *bnx2x_sp(bp, wb_data[0]);
6769                 if (val == 0xb0)
6770                         break;
6771
6772                 usleep_range(10000, 20000);
6773                 count--;
6774         }
6775         if (val != 0xb0) {
6776                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6777                 return -3;
6778         }
6779
6780         /* Wait until PRS register shows 2 packets */
6781         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6782         if (val != 2)
6783                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6784
6785         /* Write 1 to parser credits for CFC search request */
6786         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6787
6788         /* Wait until PRS register shows 3 packets */
6789         msleep(10 * factor);
6790         /* Wait until NIG register shows 1 packet of size 0x10 */
6791         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6792         if (val != 3)
6793                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6794
6795         /* clear NIG EOP FIFO */
6796         for (i = 0; i < 11; i++)
6797                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6798         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6799         if (val != 1) {
6800                 BNX2X_ERR("clear of NIG failed\n");
6801                 return -4;
6802         }
6803
6804         /* Reset and init BRB, PRS, NIG */
6805         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6806         msleep(50);
6807         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6808         msleep(50);
6809         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6810         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6811         if (!CNIC_SUPPORT(bp))
6812                 /* set NIC mode */
6813                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6814
6815         /* Enable inputs of parser neighbor blocks */
6816         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6817         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6818         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6819         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6820
6821         DP(NETIF_MSG_HW, "done\n");
6822
6823         return 0; /* OK */
6824 }
6825
6826 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6827 {
6828         u32 val;
6829
6830         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6831         if (!CHIP_IS_E1x(bp))
6832                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6833         else
6834                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6835         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6836         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6837         /*
6838          * mask read length error interrupts in brb for parser
6839          * (parsing unit and 'checksum and crc' unit)
6840          * these errors are legal (PU reads fixed length and CAC can cause
6841          * read length error on truncated packets)
6842          */
6843         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6844         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6845         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6846         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6847         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6848         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6849 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6850 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6851         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6852         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6853         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6854 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6855 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6856         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6857         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6858         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6859         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6860 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6861 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6862
6863         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6864                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6865                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6866         if (!CHIP_IS_E1x(bp))
6867                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6868                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6869         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6870
6871         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6872         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6873         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6874 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6875
6876         if (!CHIP_IS_E1x(bp))
6877                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6878                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6879
6880         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6881         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6882 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6883         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6884 }
6885
6886 static void bnx2x_reset_common(struct bnx2x *bp)
6887 {
6888         u32 val = 0x1400;
6889
6890         /* reset_common */
6891         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6892                0xd3ffff7f);
6893
6894         if (CHIP_IS_E3(bp)) {
6895                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6896                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6897         }
6898
6899         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6900 }
6901
6902 static void bnx2x_setup_dmae(struct bnx2x *bp)
6903 {
6904         bp->dmae_ready = 0;
6905         spin_lock_init(&bp->dmae_lock);
6906 }
6907
6908 static void bnx2x_init_pxp(struct bnx2x *bp)
6909 {
6910         u16 devctl;
6911         int r_order, w_order;
6912
6913         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6914         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6915         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6916         if (bp->mrrs == -1)
6917                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6918         else {
6919                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6920                 r_order = bp->mrrs;
6921         }
6922
6923         bnx2x_init_pxp_arb(bp, r_order, w_order);
6924 }
6925
6926 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6927 {
6928         int is_required;
6929         u32 val;
6930         int port;
6931
6932         if (BP_NOMCP(bp))
6933                 return;
6934
6935         is_required = 0;
6936         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6937               SHARED_HW_CFG_FAN_FAILURE_MASK;
6938
6939         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6940                 is_required = 1;
6941
6942         /*
6943          * The fan failure mechanism is usually related to the PHY type since
6944          * the power consumption of the board is affected by the PHY. Currently,
6945          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6946          */
6947         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6948                 for (port = PORT_0; port < PORT_MAX; port++) {
6949                         is_required |=
6950                                 bnx2x_fan_failure_det_req(
6951                                         bp,
6952                                         bp->common.shmem_base,
6953                                         bp->common.shmem2_base,
6954                                         port);
6955                 }
6956
6957         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6958
6959         if (is_required == 0)
6960                 return;
6961
6962         /* Fan failure is indicated by SPIO 5 */
6963         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6964
6965         /* set to active low mode */
6966         val = REG_RD(bp, MISC_REG_SPIO_INT);
6967         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6968         REG_WR(bp, MISC_REG_SPIO_INT, val);
6969
6970         /* enable interrupt to signal the IGU */
6971         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6972         val |= MISC_SPIO_SPIO5;
6973         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6974 }
6975
6976 void bnx2x_pf_disable(struct bnx2x *bp)
6977 {
6978         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6979         val &= ~IGU_PF_CONF_FUNC_EN;
6980
6981         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6982         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6983         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6984 }
6985
6986 static void bnx2x__common_init_phy(struct bnx2x *bp)
6987 {
6988         u32 shmem_base[2], shmem2_base[2];
6989         /* Avoid common init in case MFW supports LFA */
6990         if (SHMEM2_RD(bp, size) >
6991             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6992                 return;
6993         shmem_base[0] =  bp->common.shmem_base;
6994         shmem2_base[0] = bp->common.shmem2_base;
6995         if (!CHIP_IS_E1x(bp)) {
6996                 shmem_base[1] =
6997                         SHMEM2_RD(bp, other_shmem_base_addr);
6998                 shmem2_base[1] =
6999                         SHMEM2_RD(bp, other_shmem2_base_addr);
7000         }
7001         bnx2x_acquire_phy_lock(bp);
7002         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
7003                               bp->common.chip_id);
7004         bnx2x_release_phy_lock(bp);
7005 }
7006
7007 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
7008 {
7009         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7010         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7011         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7012         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7013         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7014
7015         /* make sure this value is 0 */
7016         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7017
7018         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7019         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7020         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7021         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7022 }
7023
7024 static void bnx2x_set_endianity(struct bnx2x *bp)
7025 {
7026 #ifdef __BIG_ENDIAN
7027         bnx2x_config_endianity(bp, 1);
7028 #else
7029         bnx2x_config_endianity(bp, 0);
7030 #endif
7031 }
7032
7033 static void bnx2x_reset_endianity(struct bnx2x *bp)
7034 {
7035         bnx2x_config_endianity(bp, 0);
7036 }
7037
7038 /**
7039  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7040  *
7041  * @bp:         driver handle
7042  */
7043 static int bnx2x_init_hw_common(struct bnx2x *bp)
7044 {
7045         u32 val;
7046
7047         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7048
7049         /*
7050          * take the RESET lock to protect undi_unload flow from accessing
7051          * registers while we're resetting the chip
7052          */
7053         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7054
7055         bnx2x_reset_common(bp);
7056         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7057
7058         val = 0xfffc;
7059         if (CHIP_IS_E3(bp)) {
7060                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7061                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7062         }
7063         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7064
7065         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7066
7067         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7068
7069         if (!CHIP_IS_E1x(bp)) {
7070                 u8 abs_func_id;
7071
7072                 /**
7073                  * 4-port mode or 2-port mode we need to turn of master-enable
7074                  * for everyone, after that, turn it back on for self.
7075                  * so, we disregard multi-function or not, and always disable
7076                  * for all functions on the given path, this means 0,2,4,6 for
7077                  * path 0 and 1,3,5,7 for path 1
7078                  */
7079                 for (abs_func_id = BP_PATH(bp);
7080                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7081                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7082                                 REG_WR(bp,
7083                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7084                                     1);
7085                                 continue;
7086                         }
7087
7088                         bnx2x_pretend_func(bp, abs_func_id);
7089                         /* clear pf enable */
7090                         bnx2x_pf_disable(bp);
7091                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7092                 }
7093         }
7094
7095         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7096         if (CHIP_IS_E1(bp)) {
7097                 /* enable HW interrupt from PXP on USDM overflow
7098                    bit 16 on INT_MASK_0 */
7099                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7100         }
7101
7102         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7103         bnx2x_init_pxp(bp);
7104         bnx2x_set_endianity(bp);
7105         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7106
7107         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7108                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7109
7110         /* let the HW do it's magic ... */
7111         msleep(100);
7112         /* finish PXP init */
7113         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7114         if (val != 1) {
7115                 BNX2X_ERR("PXP2 CFG failed\n");
7116                 return -EBUSY;
7117         }
7118         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7119         if (val != 1) {
7120                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7121                 return -EBUSY;
7122         }
7123
7124         /* Timers bug workaround E2 only. We need to set the entire ILT to
7125          * have entries with value "0" and valid bit on.
7126          * This needs to be done by the first PF that is loaded in a path
7127          * (i.e. common phase)
7128          */
7129         if (!CHIP_IS_E1x(bp)) {
7130 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7131  * (i.e. vnic3) to start even if it is marked as "scan-off".
7132  * This occurs when a different function (func2,3) is being marked
7133  * as "scan-off". Real-life scenario for example: if a driver is being
7134  * load-unloaded while func6,7 are down. This will cause the timer to access
7135  * the ilt, translate to a logical address and send a request to read/write.
7136  * Since the ilt for the function that is down is not valid, this will cause
7137  * a translation error which is unrecoverable.
7138  * The Workaround is intended to make sure that when this happens nothing fatal
7139  * will occur. The workaround:
7140  *      1.  First PF driver which loads on a path will:
7141  *              a.  After taking the chip out of reset, by using pretend,
7142  *                  it will write "0" to the following registers of
7143  *                  the other vnics.
7144  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7145  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7146  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7147  *                  And for itself it will write '1' to
7148  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7149  *                  dmae-operations (writing to pram for example.)
7150  *                  note: can be done for only function 6,7 but cleaner this
7151  *                        way.
7152  *              b.  Write zero+valid to the entire ILT.
7153  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7154  *                  VNIC3 (of that port). The range allocated will be the
7155  *                  entire ILT. This is needed to prevent  ILT range error.
7156  *      2.  Any PF driver load flow:
7157  *              a.  ILT update with the physical addresses of the allocated
7158  *                  logical pages.
7159  *              b.  Wait 20msec. - note that this timeout is needed to make
7160  *                  sure there are no requests in one of the PXP internal
7161  *                  queues with "old" ILT addresses.
7162  *              c.  PF enable in the PGLC.
7163  *              d.  Clear the was_error of the PF in the PGLC. (could have
7164  *                  occurred while driver was down)
7165  *              e.  PF enable in the CFC (WEAK + STRONG)
7166  *              f.  Timers scan enable
7167  *      3.  PF driver unload flow:
7168  *              a.  Clear the Timers scan_en.
7169  *              b.  Polling for scan_on=0 for that PF.
7170  *              c.  Clear the PF enable bit in the PXP.
7171  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7172  *              e.  Write zero+valid to all ILT entries (The valid bit must
7173  *                  stay set)
7174  *              f.  If this is VNIC 3 of a port then also init
7175  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7176  *                  to the last entry in the ILT.
7177  *
7178  *      Notes:
7179  *      Currently the PF error in the PGLC is non recoverable.
7180  *      In the future the there will be a recovery routine for this error.
7181  *      Currently attention is masked.
7182  *      Having an MCP lock on the load/unload process does not guarantee that
7183  *      there is no Timer disable during Func6/7 enable. This is because the
7184  *      Timers scan is currently being cleared by the MCP on FLR.
7185  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7186  *      there is error before clearing it. But the flow above is simpler and
7187  *      more general.
7188  *      All ILT entries are written by zero+valid and not just PF6/7
7189  *      ILT entries since in the future the ILT entries allocation for
7190  *      PF-s might be dynamic.
7191  */
7192                 struct ilt_client_info ilt_cli;
7193                 struct bnx2x_ilt ilt;
7194                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7195                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7196
7197                 /* initialize dummy TM client */
7198                 ilt_cli.start = 0;
7199                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7200                 ilt_cli.client_num = ILT_CLIENT_TM;
7201
7202                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7203                  * Step 2: set the timers first/last ilt entry to point
7204                  * to the entire range to prevent ILT range error for 3rd/4th
7205                  * vnic (this code assumes existence of the vnic)
7206                  *
7207                  * both steps performed by call to bnx2x_ilt_client_init_op()
7208                  * with dummy TM client
7209                  *
7210                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7211                  * and his brother are split registers
7212                  */
7213                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7214                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7215                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7216
7217                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7218                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7219                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7220         }
7221
7222         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7223         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7224
7225         if (!CHIP_IS_E1x(bp)) {
7226                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7227                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7228                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7229
7230                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7231
7232                 /* let the HW do it's magic ... */
7233                 do {
7234                         msleep(200);
7235                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7236                 } while (factor-- && (val != 1));
7237
7238                 if (val != 1) {
7239                         BNX2X_ERR("ATC_INIT failed\n");
7240                         return -EBUSY;
7241                 }
7242         }
7243
7244         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7245
7246         bnx2x_iov_init_dmae(bp);
7247
7248         /* clean the DMAE memory */
7249         bp->dmae_ready = 1;
7250         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7251
7252         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7253
7254         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7255
7256         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7257
7258         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7259
7260         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7261         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7262         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7263         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7264
7265         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7266
7267         /* QM queues pointers table */
7268         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7269
7270         /* soft reset pulse */
7271         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7272         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7273
7274         if (CNIC_SUPPORT(bp))
7275                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7276
7277         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7278
7279         if (!CHIP_REV_IS_SLOW(bp))
7280                 /* enable hw interrupt from doorbell Q */
7281                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7282
7283         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7284
7285         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7286         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7287
7288         if (!CHIP_IS_E1(bp))
7289                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7290
7291         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7292                 if (IS_MF_AFEX(bp)) {
7293                         /* configure that VNTag and VLAN headers must be
7294                          * received in afex mode
7295                          */
7296                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7297                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7298                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7299                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7300                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7301                 } else {
7302                         /* Bit-map indicating which L2 hdrs may appear
7303                          * after the basic Ethernet header
7304                          */
7305                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7306                                bp->path_has_ovlan ? 7 : 6);
7307                 }
7308         }
7309
7310         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7311         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7312         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7313         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7314
7315         if (!CHIP_IS_E1x(bp)) {
7316                 /* reset VFC memories */
7317                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7318                            VFC_MEMORIES_RST_REG_CAM_RST |
7319                            VFC_MEMORIES_RST_REG_RAM_RST);
7320                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7321                            VFC_MEMORIES_RST_REG_CAM_RST |
7322                            VFC_MEMORIES_RST_REG_RAM_RST);
7323
7324                 msleep(20);
7325         }
7326
7327         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7328         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7329         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7330         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7331
7332         /* sync semi rtc */
7333         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7334                0x80000000);
7335         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7336                0x80000000);
7337
7338         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7339         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7340         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7341
7342         if (!CHIP_IS_E1x(bp)) {
7343                 if (IS_MF_AFEX(bp)) {
7344                         /* configure that VNTag and VLAN headers must be
7345                          * sent in afex mode
7346                          */
7347                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7348                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7349                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7350                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7351                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7352                 } else {
7353                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7354                                bp->path_has_ovlan ? 7 : 6);
7355                 }
7356         }
7357
7358         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7359
7360         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7361
7362         if (CNIC_SUPPORT(bp)) {
7363                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7364                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7365                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7366                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7367                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7368                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7369                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7370                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7371                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7372                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7373         }
7374         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7375
7376         if (sizeof(union cdu_context) != 1024)
7377                 /* we currently assume that a context is 1024 bytes */
7378                 dev_alert(&bp->pdev->dev,
7379                           "please adjust the size of cdu_context(%ld)\n",
7380                           (long)sizeof(union cdu_context));
7381
7382         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7383         val = (4 << 24) + (0 << 12) + 1024;
7384         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7385
7386         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7387         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7388         /* enable context validation interrupt from CFC */
7389         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7390
7391         /* set the thresholds to prevent CFC/CDU race */
7392         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7393
7394         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7395
7396         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7397                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7398
7399         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7400         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7401
7402         /* Reset PCIE errors for debug */
7403         REG_WR(bp, 0x2814, 0xffffffff);
7404         REG_WR(bp, 0x3820, 0xffffffff);
7405
7406         if (!CHIP_IS_E1x(bp)) {
7407                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7408                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7409                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7410                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7411                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7412                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7413                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7414                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7415                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7416                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7417                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7418         }
7419
7420         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7421         if (!CHIP_IS_E1(bp)) {
7422                 /* in E3 this done in per-port section */
7423                 if (!CHIP_IS_E3(bp))
7424                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7425         }
7426         if (CHIP_IS_E1H(bp))
7427                 /* not applicable for E2 (and above ...) */
7428                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7429
7430         if (CHIP_REV_IS_SLOW(bp))
7431                 msleep(200);
7432
7433         /* finish CFC init */
7434         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7435         if (val != 1) {
7436                 BNX2X_ERR("CFC LL_INIT failed\n");
7437                 return -EBUSY;
7438         }
7439         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7440         if (val != 1) {
7441                 BNX2X_ERR("CFC AC_INIT failed\n");
7442                 return -EBUSY;
7443         }
7444         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7445         if (val != 1) {
7446                 BNX2X_ERR("CFC CAM_INIT failed\n");
7447                 return -EBUSY;
7448         }
7449         REG_WR(bp, CFC_REG_DEBUG0, 0);
7450
7451         if (CHIP_IS_E1(bp)) {
7452                 /* read NIG statistic
7453                    to see if this is our first up since powerup */
7454                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7455                 val = *bnx2x_sp(bp, wb_data[0]);
7456
7457                 /* do internal memory self test */
7458                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7459                         BNX2X_ERR("internal mem self test failed\n");
7460                         return -EBUSY;
7461                 }
7462         }
7463
7464         bnx2x_setup_fan_failure_detection(bp);
7465
7466         /* clear PXP2 attentions */
7467         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7468
7469         bnx2x_enable_blocks_attention(bp);
7470         bnx2x_enable_blocks_parity(bp);
7471
7472         if (!BP_NOMCP(bp)) {
7473                 if (CHIP_IS_E1x(bp))
7474                         bnx2x__common_init_phy(bp);
7475         } else
7476                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7477
7478         if (SHMEM2_HAS(bp, netproc_fw_ver))
7479                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7480
7481         return 0;
7482 }
7483
7484 /**
7485  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7486  *
7487  * @bp:         driver handle
7488  */
7489 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7490 {
7491         int rc = bnx2x_init_hw_common(bp);
7492
7493         if (rc)
7494                 return rc;
7495
7496         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7497         if (!BP_NOMCP(bp))
7498                 bnx2x__common_init_phy(bp);
7499
7500         return 0;
7501 }
7502
7503 static int bnx2x_init_hw_port(struct bnx2x *bp)
7504 {
7505         int port = BP_PORT(bp);
7506         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7507         u32 low, high;
7508         u32 val, reg;
7509
7510         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7511
7512         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7513
7514         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7515         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7516         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7517
7518         /* Timers bug workaround: disables the pf_master bit in pglue at
7519          * common phase, we need to enable it here before any dmae access are
7520          * attempted. Therefore we manually added the enable-master to the
7521          * port phase (it also happens in the function phase)
7522          */
7523         if (!CHIP_IS_E1x(bp))
7524                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7525
7526         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7527         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7528         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7529         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7530
7531         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7532         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7533         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7534         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7535
7536         /* QM cid (connection) count */
7537         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7538
7539         if (CNIC_SUPPORT(bp)) {
7540                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7541                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7542                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7543         }
7544
7545         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7546
7547         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7548
7549         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7550
7551                 if (IS_MF(bp))
7552                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7553                 else if (bp->dev->mtu > 4096) {
7554                         if (bp->flags & ONE_PORT_FLAG)
7555                                 low = 160;
7556                         else {
7557                                 val = bp->dev->mtu;
7558                                 /* (24*1024 + val*4)/256 */
7559                                 low = 96 + (val/64) +
7560                                                 ((val % 64) ? 1 : 0);
7561                         }
7562                 } else
7563                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7564                 high = low + 56;        /* 14*1024/256 */
7565                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7566                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7567         }
7568
7569         if (CHIP_MODE_IS_4_PORT(bp))
7570                 REG_WR(bp, (BP_PORT(bp) ?
7571                             BRB1_REG_MAC_GUARANTIED_1 :
7572                             BRB1_REG_MAC_GUARANTIED_0), 40);
7573
7574         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7575         if (CHIP_IS_E3B0(bp)) {
7576                 if (IS_MF_AFEX(bp)) {
7577                         /* configure headers for AFEX mode */
7578                         REG_WR(bp, BP_PORT(bp) ?
7579                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7580                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7581                         REG_WR(bp, BP_PORT(bp) ?
7582                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7583                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7584                         REG_WR(bp, BP_PORT(bp) ?
7585                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7586                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7587                 } else {
7588                         /* Ovlan exists only if we are in multi-function +
7589                          * switch-dependent mode, in switch-independent there
7590                          * is no ovlan headers
7591                          */
7592                         REG_WR(bp, BP_PORT(bp) ?
7593                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7594                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7595                                (bp->path_has_ovlan ? 7 : 6));
7596                 }
7597         }
7598
7599         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7600         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7601         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7602         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7603
7604         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7605         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7606         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7607         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7608
7609         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7610         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7611
7612         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7613
7614         if (CHIP_IS_E1x(bp)) {
7615                 /* configure PBF to work without PAUSE mtu 9000 */
7616                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7617
7618                 /* update threshold */
7619                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7620                 /* update init credit */
7621                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7622
7623                 /* probe changes */
7624                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7625                 udelay(50);
7626                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7627         }
7628
7629         if (CNIC_SUPPORT(bp))
7630                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7631
7632         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7633         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7634
7635         if (CHIP_IS_E1(bp)) {
7636                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7637                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7638         }
7639         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7640
7641         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7642
7643         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7644         /* init aeu_mask_attn_func_0/1:
7645          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7646          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7647          *             bits 4-7 are used for "per vn group attention" */
7648         val = IS_MF(bp) ? 0xF7 : 0x7;
7649         /* Enable DCBX attention for all but E1 */
7650         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7651         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7652
7653         /* SCPAD_PARITY should NOT trigger close the gates */
7654         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7655         REG_WR(bp, reg,
7656                REG_RD(bp, reg) &
7657                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7658
7659         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7660         REG_WR(bp, reg,
7661                REG_RD(bp, reg) &
7662                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7663
7664         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7665
7666         if (!CHIP_IS_E1x(bp)) {
7667                 /* Bit-map indicating which L2 hdrs may appear after the
7668                  * basic Ethernet header
7669                  */
7670                 if (IS_MF_AFEX(bp))
7671                         REG_WR(bp, BP_PORT(bp) ?
7672                                NIG_REG_P1_HDRS_AFTER_BASIC :
7673                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7674                 else
7675                         REG_WR(bp, BP_PORT(bp) ?
7676                                NIG_REG_P1_HDRS_AFTER_BASIC :
7677                                NIG_REG_P0_HDRS_AFTER_BASIC,
7678                                IS_MF_SD(bp) ? 7 : 6);
7679
7680                 if (CHIP_IS_E3(bp))
7681                         REG_WR(bp, BP_PORT(bp) ?
7682                                    NIG_REG_LLH1_MF_MODE :
7683                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7684         }
7685         if (!CHIP_IS_E3(bp))
7686                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7687
7688         if (!CHIP_IS_E1(bp)) {
7689                 /* 0x2 disable mf_ov, 0x1 enable */
7690                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7691                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7692
7693                 if (!CHIP_IS_E1x(bp)) {
7694                         val = 0;
7695                         switch (bp->mf_mode) {
7696                         case MULTI_FUNCTION_SD:
7697                                 val = 1;
7698                                 break;
7699                         case MULTI_FUNCTION_SI:
7700                         case MULTI_FUNCTION_AFEX:
7701                                 val = 2;
7702                                 break;
7703                         }
7704
7705                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7706                                                   NIG_REG_LLH0_CLS_TYPE), val);
7707                 }
7708                 {
7709                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7710                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7711                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7712                 }
7713         }
7714
7715         /* If SPIO5 is set to generate interrupts, enable it for this port */
7716         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7717         if (val & MISC_SPIO_SPIO5) {
7718                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7719                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7720                 val = REG_RD(bp, reg_addr);
7721                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7722                 REG_WR(bp, reg_addr, val);
7723         }
7724
7725         return 0;
7726 }
7727
7728 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7729 {
7730         int reg;
7731         u32 wb_write[2];
7732
7733         if (CHIP_IS_E1(bp))
7734                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7735         else
7736                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7737
7738         wb_write[0] = ONCHIP_ADDR1(addr);
7739         wb_write[1] = ONCHIP_ADDR2(addr);
7740         REG_WR_DMAE(bp, reg, wb_write, 2);
7741 }
7742
7743 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7744 {
7745         u32 data, ctl, cnt = 100;
7746         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7747         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7748         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7749         u32 sb_bit =  1 << (idu_sb_id%32);
7750         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7751         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7752
7753         /* Not supported in BC mode */
7754         if (CHIP_INT_MODE_IS_BC(bp))
7755                 return;
7756
7757         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7758                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7759                 IGU_REGULAR_CLEANUP_SET                         |
7760                 IGU_REGULAR_BCLEANUP;
7761
7762         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7763               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7764               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7765
7766         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7767                          data, igu_addr_data);
7768         REG_WR(bp, igu_addr_data, data);
7769         mmiowb();
7770         barrier();
7771         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7772                           ctl, igu_addr_ctl);
7773         REG_WR(bp, igu_addr_ctl, ctl);
7774         mmiowb();
7775         barrier();
7776
7777         /* wait for clean up to finish */
7778         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7779                 msleep(20);
7780
7781         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7782                 DP(NETIF_MSG_HW,
7783                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7784                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7785         }
7786 }
7787
7788 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7789 {
7790         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7791 }
7792
7793 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7794 {
7795         u32 i, base = FUNC_ILT_BASE(func);
7796         for (i = base; i < base + ILT_PER_FUNC; i++)
7797                 bnx2x_ilt_wr(bp, i, 0);
7798 }
7799
7800 static void bnx2x_init_searcher(struct bnx2x *bp)
7801 {
7802         int port = BP_PORT(bp);
7803         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7804         /* T1 hash bits value determines the T1 number of entries */
7805         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7806 }
7807
7808 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7809 {
7810         int rc;
7811         struct bnx2x_func_state_params func_params = {NULL};
7812         struct bnx2x_func_switch_update_params *switch_update_params =
7813                 &func_params.params.switch_update;
7814
7815         /* Prepare parameters for function state transitions */
7816         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7817         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7818
7819         func_params.f_obj = &bp->func_obj;
7820         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7821
7822         /* Function parameters */
7823         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7824                   &switch_update_params->changes);
7825         if (suspend)
7826                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7827                           &switch_update_params->changes);
7828
7829         rc = bnx2x_func_state_change(bp, &func_params);
7830
7831         return rc;
7832 }
7833
7834 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7835 {
7836         int rc, i, port = BP_PORT(bp);
7837         int vlan_en = 0, mac_en[NUM_MACS];
7838
7839         /* Close input from network */
7840         if (bp->mf_mode == SINGLE_FUNCTION) {
7841                 bnx2x_set_rx_filter(&bp->link_params, 0);
7842         } else {
7843                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7844                                    NIG_REG_LLH0_FUNC_EN);
7845                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7846                           NIG_REG_LLH0_FUNC_EN, 0);
7847                 for (i = 0; i < NUM_MACS; i++) {
7848                         mac_en[i] = REG_RD(bp, port ?
7849                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7850                                               4 * i) :
7851                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7852                                               4 * i));
7853                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7854                                               4 * i) :
7855                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7856                 }
7857         }
7858
7859         /* Close BMC to host */
7860         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7861                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7862
7863         /* Suspend Tx switching to the PF. Completion of this ramrod
7864          * further guarantees that all the packets of that PF / child
7865          * VFs in BRB were processed by the Parser, so it is safe to
7866          * change the NIC_MODE register.
7867          */
7868         rc = bnx2x_func_switch_update(bp, 1);
7869         if (rc) {
7870                 BNX2X_ERR("Can't suspend tx-switching!\n");
7871                 return rc;
7872         }
7873
7874         /* Change NIC_MODE register */
7875         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7876
7877         /* Open input from network */
7878         if (bp->mf_mode == SINGLE_FUNCTION) {
7879                 bnx2x_set_rx_filter(&bp->link_params, 1);
7880         } else {
7881                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7882                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7883                 for (i = 0; i < NUM_MACS; i++) {
7884                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7885                                               4 * i) :
7886                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7887                                   mac_en[i]);
7888                 }
7889         }
7890
7891         /* Enable BMC to host */
7892         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7893                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7894
7895         /* Resume Tx switching to the PF */
7896         rc = bnx2x_func_switch_update(bp, 0);
7897         if (rc) {
7898                 BNX2X_ERR("Can't resume tx-switching!\n");
7899                 return rc;
7900         }
7901
7902         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7903         return 0;
7904 }
7905
7906 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7907 {
7908         int rc;
7909
7910         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7911
7912         if (CONFIGURE_NIC_MODE(bp)) {
7913                 /* Configure searcher as part of function hw init */
7914                 bnx2x_init_searcher(bp);
7915
7916                 /* Reset NIC mode */
7917                 rc = bnx2x_reset_nic_mode(bp);
7918                 if (rc)
7919                         BNX2X_ERR("Can't change NIC mode!\n");
7920                 return rc;
7921         }
7922
7923         return 0;
7924 }
7925
7926 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7927  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7928  * the addresses of the transaction, resulting in was-error bit set in the pci
7929  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7930  * to clear the interrupt which detected this from the pglueb and the was done
7931  * bit
7932  */
7933 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7934 {
7935         if (!CHIP_IS_E1x(bp))
7936                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7937                        1 << BP_ABS_FUNC(bp));
7938 }
7939
7940 static int bnx2x_init_hw_func(struct bnx2x *bp)
7941 {
7942         int port = BP_PORT(bp);
7943         int func = BP_FUNC(bp);
7944         int init_phase = PHASE_PF0 + func;
7945         struct bnx2x_ilt *ilt = BP_ILT(bp);
7946         u16 cdu_ilt_start;
7947         u32 addr, val;
7948         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7949         int i, main_mem_width, rc;
7950
7951         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7952
7953         /* FLR cleanup - hmmm */
7954         if (!CHIP_IS_E1x(bp)) {
7955                 rc = bnx2x_pf_flr_clnup(bp);
7956                 if (rc) {
7957                         bnx2x_fw_dump(bp);
7958                         return rc;
7959                 }
7960         }
7961
7962         /* set MSI reconfigure capability */
7963         if (bp->common.int_block == INT_BLOCK_HC) {
7964                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7965                 val = REG_RD(bp, addr);
7966                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7967                 REG_WR(bp, addr, val);
7968         }
7969
7970         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7971         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7972
7973         ilt = BP_ILT(bp);
7974         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7975
7976         if (IS_SRIOV(bp))
7977                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7978         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7979
7980         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7981          * those of the VFs, so start line should be reset
7982          */
7983         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7984         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7985                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7986                 ilt->lines[cdu_ilt_start + i].page_mapping =
7987                         bp->context[i].cxt_mapping;
7988                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7989         }
7990
7991         bnx2x_ilt_init_op(bp, INITOP_SET);
7992
7993         if (!CONFIGURE_NIC_MODE(bp)) {
7994                 bnx2x_init_searcher(bp);
7995                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7996                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7997         } else {
7998                 /* Set NIC mode */
7999                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
8000                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
8001         }
8002
8003         if (!CHIP_IS_E1x(bp)) {
8004                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
8005
8006                 /* Turn on a single ISR mode in IGU if driver is going to use
8007                  * INT#x or MSI
8008                  */
8009                 if (!(bp->flags & USING_MSIX_FLAG))
8010                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8011                 /*
8012                  * Timers workaround bug: function init part.
8013                  * Need to wait 20msec after initializing ILT,
8014                  * needed to make sure there are no requests in
8015                  * one of the PXP internal queues with "old" ILT addresses
8016                  */
8017                 msleep(20);
8018                 /*
8019                  * Master enable - Due to WB DMAE writes performed before this
8020                  * register is re-initialized as part of the regular function
8021                  * init
8022                  */
8023                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8024                 /* Enable the function in IGU */
8025                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8026         }
8027
8028         bp->dmae_ready = 1;
8029
8030         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8031
8032         bnx2x_clean_pglue_errors(bp);
8033
8034         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8035         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8036         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8037         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8038         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8039         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8040         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8041         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8042         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8043         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8044         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8045         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8046         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8047
8048         if (!CHIP_IS_E1x(bp))
8049                 REG_WR(bp, QM_REG_PF_EN, 1);
8050
8051         if (!CHIP_IS_E1x(bp)) {
8052                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8053                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8054                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8055                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8056         }
8057         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8058
8059         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8060         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8061         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8062
8063         bnx2x_iov_init_dq(bp);
8064
8065         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8066         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8067         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8068         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8069         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8070         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8071         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8072         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8073         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8074         if (!CHIP_IS_E1x(bp))
8075                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8076
8077         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8078
8079         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8080
8081         if (!CHIP_IS_E1x(bp))
8082                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8083
8084         if (IS_MF(bp)) {
8085                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8086                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8087                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8088                                bp->mf_ov);
8089                 }
8090         }
8091
8092         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8093
8094         /* HC init per function */
8095         if (bp->common.int_block == INT_BLOCK_HC) {
8096                 if (CHIP_IS_E1H(bp)) {
8097                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8098
8099                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8100                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8101                 }
8102                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8103
8104         } else {
8105                 int num_segs, sb_idx, prod_offset;
8106
8107                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8108
8109                 if (!CHIP_IS_E1x(bp)) {
8110                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8111                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8112                 }
8113
8114                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8115
8116                 if (!CHIP_IS_E1x(bp)) {
8117                         int dsb_idx = 0;
8118                         /**
8119                          * Producer memory:
8120                          * E2 mode: address 0-135 match to the mapping memory;
8121                          * 136 - PF0 default prod; 137 - PF1 default prod;
8122                          * 138 - PF2 default prod; 139 - PF3 default prod;
8123                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8124                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8125                          * 144-147 reserved.
8126                          *
8127                          * E1.5 mode - In backward compatible mode;
8128                          * for non default SB; each even line in the memory
8129                          * holds the U producer and each odd line hold
8130                          * the C producer. The first 128 producers are for
8131                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8132                          * producers are for the DSB for each PF.
8133                          * Each PF has five segments: (the order inside each
8134                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8135                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8136                          * 144-147 attn prods;
8137                          */
8138                         /* non-default-status-blocks */
8139                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8140                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8141                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8142                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8143                                         num_segs;
8144
8145                                 for (i = 0; i < num_segs; i++) {
8146                                         addr = IGU_REG_PROD_CONS_MEMORY +
8147                                                         (prod_offset + i) * 4;
8148                                         REG_WR(bp, addr, 0);
8149                                 }
8150                                 /* send consumer update with value 0 */
8151                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8152                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8153                                 bnx2x_igu_clear_sb(bp,
8154                                                    bp->igu_base_sb + sb_idx);
8155                         }
8156
8157                         /* default-status-blocks */
8158                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8159                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8160
8161                         if (CHIP_MODE_IS_4_PORT(bp))
8162                                 dsb_idx = BP_FUNC(bp);
8163                         else
8164                                 dsb_idx = BP_VN(bp);
8165
8166                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8167                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8168                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8169
8170                         /*
8171                          * igu prods come in chunks of E1HVN_MAX (4) -
8172                          * does not matters what is the current chip mode
8173                          */
8174                         for (i = 0; i < (num_segs * E1HVN_MAX);
8175                              i += E1HVN_MAX) {
8176                                 addr = IGU_REG_PROD_CONS_MEMORY +
8177                                                         (prod_offset + i)*4;
8178                                 REG_WR(bp, addr, 0);
8179                         }
8180                         /* send consumer update with 0 */
8181                         if (CHIP_INT_MODE_IS_BC(bp)) {
8182                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8183                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8184                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8185                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8186                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8187                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8188                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8189                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8190                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8191                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8192                         } else {
8193                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8194                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8195                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8196                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8197                         }
8198                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8199
8200                         /* !!! These should become driver const once
8201                            rf-tool supports split-68 const */
8202                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8203                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8204                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8205                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8206                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8207                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8208                 }
8209         }
8210
8211         /* Reset PCIE errors for debug */
8212         REG_WR(bp, 0x2114, 0xffffffff);
8213         REG_WR(bp, 0x2120, 0xffffffff);
8214
8215         if (CHIP_IS_E1x(bp)) {
8216                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8217                 main_mem_base = HC_REG_MAIN_MEMORY +
8218                                 BP_PORT(bp) * (main_mem_size * 4);
8219                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8220                 main_mem_width = 8;
8221
8222                 val = REG_RD(bp, main_mem_prty_clr);
8223                 if (val)
8224                         DP(NETIF_MSG_HW,
8225                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8226                            val);
8227
8228                 /* Clear "false" parity errors in MSI-X table */
8229                 for (i = main_mem_base;
8230                      i < main_mem_base + main_mem_size * 4;
8231                      i += main_mem_width) {
8232                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8233                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8234                                          i, main_mem_width / 4);
8235                 }
8236                 /* Clear HC parity attention */
8237                 REG_RD(bp, main_mem_prty_clr);
8238         }
8239
8240 #ifdef BNX2X_STOP_ON_ERROR
8241         /* Enable STORMs SP logging */
8242         REG_WR8(bp, BAR_USTRORM_INTMEM +
8243                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8244         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8245                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8246         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8247                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8248         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8249                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8250 #endif
8251
8252         bnx2x_phy_probe(&bp->link_params);
8253
8254         return 0;
8255 }
8256
8257 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8258 {
8259         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8260
8261         if (!CHIP_IS_E1x(bp))
8262                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8263                                sizeof(struct host_hc_status_block_e2));
8264         else
8265                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8266                                sizeof(struct host_hc_status_block_e1x));
8267
8268         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8269 }
8270
8271 void bnx2x_free_mem(struct bnx2x *bp)
8272 {
8273         int i;
8274
8275         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8276                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8277
8278         if (IS_VF(bp))
8279                 return;
8280
8281         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8282                        sizeof(struct host_sp_status_block));
8283
8284         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8285                        sizeof(struct bnx2x_slowpath));
8286
8287         for (i = 0; i < L2_ILT_LINES(bp); i++)
8288                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8289                                bp->context[i].size);
8290         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8291
8292         BNX2X_FREE(bp->ilt->lines);
8293
8294         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8295
8296         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8297                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8298
8299         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8300
8301         bnx2x_iov_free_mem(bp);
8302 }
8303
8304 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8305 {
8306         if (!CHIP_IS_E1x(bp)) {
8307                 /* size = the status block + ramrod buffers */
8308                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8309                                                     sizeof(struct host_hc_status_block_e2));
8310                 if (!bp->cnic_sb.e2_sb)
8311                         goto alloc_mem_err;
8312         } else {
8313                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8314                                                      sizeof(struct host_hc_status_block_e1x));
8315                 if (!bp->cnic_sb.e1x_sb)
8316                         goto alloc_mem_err;
8317         }
8318
8319         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8320                 /* allocate searcher T2 table, as it wasn't allocated before */
8321                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8322                 if (!bp->t2)
8323                         goto alloc_mem_err;
8324         }
8325
8326         /* write address to which L5 should insert its values */
8327         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8328                 &bp->slowpath->drv_info_to_mcp;
8329
8330         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8331                 goto alloc_mem_err;
8332
8333         return 0;
8334
8335 alloc_mem_err:
8336         bnx2x_free_mem_cnic(bp);
8337         BNX2X_ERR("Can't allocate memory\n");
8338         return -ENOMEM;
8339 }
8340
8341 int bnx2x_alloc_mem(struct bnx2x *bp)
8342 {
8343         int i, allocated, context_size;
8344
8345         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8346                 /* allocate searcher T2 table */
8347                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8348                 if (!bp->t2)
8349                         goto alloc_mem_err;
8350         }
8351
8352         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8353                                              sizeof(struct host_sp_status_block));
8354         if (!bp->def_status_blk)
8355                 goto alloc_mem_err;
8356
8357         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8358                                        sizeof(struct bnx2x_slowpath));
8359         if (!bp->slowpath)
8360                 goto alloc_mem_err;
8361
8362         /* Allocate memory for CDU context:
8363          * This memory is allocated separately and not in the generic ILT
8364          * functions because CDU differs in few aspects:
8365          * 1. There are multiple entities allocating memory for context -
8366          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8367          * its own ILT lines.
8368          * 2. Since CDU page-size is not a single 4KB page (which is the case
8369          * for the other ILT clients), to be efficient we want to support
8370          * allocation of sub-page-size in the last entry.
8371          * 3. Context pointers are used by the driver to pass to FW / update
8372          * the context (for the other ILT clients the pointers are used just to
8373          * free the memory during unload).
8374          */
8375         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8376
8377         for (i = 0, allocated = 0; allocated < context_size; i++) {
8378                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8379                                           (context_size - allocated));
8380                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8381                                                       bp->context[i].size);
8382                 if (!bp->context[i].vcxt)
8383                         goto alloc_mem_err;
8384                 allocated += bp->context[i].size;
8385         }
8386         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8387                                  GFP_KERNEL);
8388         if (!bp->ilt->lines)
8389                 goto alloc_mem_err;
8390
8391         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8392                 goto alloc_mem_err;
8393
8394         if (bnx2x_iov_alloc_mem(bp))
8395                 goto alloc_mem_err;
8396
8397         /* Slow path ring */
8398         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8399         if (!bp->spq)
8400                 goto alloc_mem_err;
8401
8402         /* EQ */
8403         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8404                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8405         if (!bp->eq_ring)
8406                 goto alloc_mem_err;
8407
8408         return 0;
8409
8410 alloc_mem_err:
8411         bnx2x_free_mem(bp);
8412         BNX2X_ERR("Can't allocate memory\n");
8413         return -ENOMEM;
8414 }
8415
8416 /*
8417  * Init service functions
8418  */
8419
8420 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8421                       struct bnx2x_vlan_mac_obj *obj, bool set,
8422                       int mac_type, unsigned long *ramrod_flags)
8423 {
8424         int rc;
8425         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8426
8427         memset(&ramrod_param, 0, sizeof(ramrod_param));
8428
8429         /* Fill general parameters */
8430         ramrod_param.vlan_mac_obj = obj;
8431         ramrod_param.ramrod_flags = *ramrod_flags;
8432
8433         /* Fill a user request section if needed */
8434         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8435                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8436
8437                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8438
8439                 /* Set the command: ADD or DEL */
8440                 if (set)
8441                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8442                 else
8443                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8444         }
8445
8446         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8447
8448         if (rc == -EEXIST) {
8449                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8450                 /* do not treat adding same MAC as error */
8451                 rc = 0;
8452         } else if (rc < 0)
8453                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8454
8455         return rc;
8456 }
8457
8458 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8459                        struct bnx2x_vlan_mac_obj *obj, bool set,
8460                        unsigned long *ramrod_flags)
8461 {
8462         int rc;
8463         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8464
8465         memset(&ramrod_param, 0, sizeof(ramrod_param));
8466
8467         /* Fill general parameters */
8468         ramrod_param.vlan_mac_obj = obj;
8469         ramrod_param.ramrod_flags = *ramrod_flags;
8470
8471         /* Fill a user request section if needed */
8472         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8473                 ramrod_param.user_req.u.vlan.vlan = vlan;
8474                 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags);
8475                 /* Set the command: ADD or DEL */
8476                 if (set)
8477                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8478                 else
8479                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8480         }
8481
8482         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8483
8484         if (rc == -EEXIST) {
8485                 /* Do not treat adding same vlan as error. */
8486                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8487                 rc = 0;
8488         } else if (rc < 0) {
8489                 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8490         }
8491
8492         return rc;
8493 }
8494
8495 void bnx2x_clear_vlan_info(struct bnx2x *bp)
8496 {
8497         struct bnx2x_vlan_entry *vlan;
8498
8499         /* Mark that hw forgot all entries */
8500         list_for_each_entry(vlan, &bp->vlan_reg, link)
8501                 vlan->hw = false;
8502
8503         bp->vlan_cnt = 0;
8504 }
8505
8506 static int bnx2x_del_all_vlans(struct bnx2x *bp)
8507 {
8508         struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj;
8509         unsigned long ramrod_flags = 0, vlan_flags = 0;
8510         int rc;
8511
8512         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8513         __set_bit(BNX2X_VLAN, &vlan_flags);
8514         rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags);
8515         if (rc)
8516                 return rc;
8517
8518         bnx2x_clear_vlan_info(bp);
8519
8520         return 0;
8521 }
8522
8523 int bnx2x_del_all_macs(struct bnx2x *bp,
8524                        struct bnx2x_vlan_mac_obj *mac_obj,
8525                        int mac_type, bool wait_for_comp)
8526 {
8527         int rc;
8528         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8529
8530         /* Wait for completion of requested */
8531         if (wait_for_comp)
8532                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8533
8534         /* Set the mac type of addresses we want to clear */
8535         __set_bit(mac_type, &vlan_mac_flags);
8536
8537         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8538         if (rc < 0)
8539                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8540
8541         return rc;
8542 }
8543
8544 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8545 {
8546         if (IS_PF(bp)) {
8547                 unsigned long ramrod_flags = 0;
8548
8549                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8550                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8551                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8552                                          &bp->sp_objs->mac_obj, set,
8553                                          BNX2X_ETH_MAC, &ramrod_flags);
8554         } else { /* vf */
8555                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8556                                              bp->fp->index, set);
8557         }
8558 }
8559
8560 int bnx2x_setup_leading(struct bnx2x *bp)
8561 {
8562         if (IS_PF(bp))
8563                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8564         else /* VF */
8565                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8566 }
8567
8568 /**
8569  * bnx2x_set_int_mode - configure interrupt mode
8570  *
8571  * @bp:         driver handle
8572  *
8573  * In case of MSI-X it will also try to enable MSI-X.
8574  */
8575 int bnx2x_set_int_mode(struct bnx2x *bp)
8576 {
8577         int rc = 0;
8578
8579         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8580                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8581                 return -EINVAL;
8582         }
8583
8584         switch (int_mode) {
8585         case BNX2X_INT_MODE_MSIX:
8586                 /* attempt to enable msix */
8587                 rc = bnx2x_enable_msix(bp);
8588
8589                 /* msix attained */
8590                 if (!rc)
8591                         return 0;
8592
8593                 /* vfs use only msix */
8594                 if (rc && IS_VF(bp))
8595                         return rc;
8596
8597                 /* failed to enable multiple MSI-X */
8598                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8599                                bp->num_queues,
8600                                1 + bp->num_cnic_queues);
8601
8602                 /* falling through... */
8603         case BNX2X_INT_MODE_MSI:
8604                 bnx2x_enable_msi(bp);
8605
8606                 /* falling through... */
8607         case BNX2X_INT_MODE_INTX:
8608                 bp->num_ethernet_queues = 1;
8609                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8610                 BNX2X_DEV_INFO("set number of queues to 1\n");
8611                 break;
8612         default:
8613                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8614                 return -EINVAL;
8615         }
8616         return 0;
8617 }
8618
8619 /* must be called prior to any HW initializations */
8620 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8621 {
8622         if (IS_SRIOV(bp))
8623                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8624         return L2_ILT_LINES(bp);
8625 }
8626
8627 void bnx2x_ilt_set_info(struct bnx2x *bp)
8628 {
8629         struct ilt_client_info *ilt_client;
8630         struct bnx2x_ilt *ilt = BP_ILT(bp);
8631         u16 line = 0;
8632
8633         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8634         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8635
8636         /* CDU */
8637         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8638         ilt_client->client_num = ILT_CLIENT_CDU;
8639         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8640         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8641         ilt_client->start = line;
8642         line += bnx2x_cid_ilt_lines(bp);
8643
8644         if (CNIC_SUPPORT(bp))
8645                 line += CNIC_ILT_LINES;
8646         ilt_client->end = line - 1;
8647
8648         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8649            ilt_client->start,
8650            ilt_client->end,
8651            ilt_client->page_size,
8652            ilt_client->flags,
8653            ilog2(ilt_client->page_size >> 12));
8654
8655         /* QM */
8656         if (QM_INIT(bp->qm_cid_count)) {
8657                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8658                 ilt_client->client_num = ILT_CLIENT_QM;
8659                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8660                 ilt_client->flags = 0;
8661                 ilt_client->start = line;
8662
8663                 /* 4 bytes for each cid */
8664                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8665                                                          QM_ILT_PAGE_SZ);
8666
8667                 ilt_client->end = line - 1;
8668
8669                 DP(NETIF_MSG_IFUP,
8670                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8671                    ilt_client->start,
8672                    ilt_client->end,
8673                    ilt_client->page_size,
8674                    ilt_client->flags,
8675                    ilog2(ilt_client->page_size >> 12));
8676         }
8677
8678         if (CNIC_SUPPORT(bp)) {
8679                 /* SRC */
8680                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8681                 ilt_client->client_num = ILT_CLIENT_SRC;
8682                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8683                 ilt_client->flags = 0;
8684                 ilt_client->start = line;
8685                 line += SRC_ILT_LINES;
8686                 ilt_client->end = line - 1;
8687
8688                 DP(NETIF_MSG_IFUP,
8689                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8690                    ilt_client->start,
8691                    ilt_client->end,
8692                    ilt_client->page_size,
8693                    ilt_client->flags,
8694                    ilog2(ilt_client->page_size >> 12));
8695
8696                 /* TM */
8697                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8698                 ilt_client->client_num = ILT_CLIENT_TM;
8699                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8700                 ilt_client->flags = 0;
8701                 ilt_client->start = line;
8702                 line += TM_ILT_LINES;
8703                 ilt_client->end = line - 1;
8704
8705                 DP(NETIF_MSG_IFUP,
8706                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8707                    ilt_client->start,
8708                    ilt_client->end,
8709                    ilt_client->page_size,
8710                    ilt_client->flags,
8711                    ilog2(ilt_client->page_size >> 12));
8712         }
8713
8714         BUG_ON(line > ILT_MAX_LINES);
8715 }
8716
8717 /**
8718  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8719  *
8720  * @bp:                 driver handle
8721  * @fp:                 pointer to fastpath
8722  * @init_params:        pointer to parameters structure
8723  *
8724  * parameters configured:
8725  *      - HC configuration
8726  *      - Queue's CDU context
8727  */
8728 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8729         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8730 {
8731         u8 cos;
8732         int cxt_index, cxt_offset;
8733
8734         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8735         if (!IS_FCOE_FP(fp)) {
8736                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8737                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8738
8739                 /* If HC is supported, enable host coalescing in the transition
8740                  * to INIT state.
8741                  */
8742                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8743                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8744
8745                 /* HC rate */
8746                 init_params->rx.hc_rate = bp->rx_ticks ?
8747                         (1000000 / bp->rx_ticks) : 0;
8748                 init_params->tx.hc_rate = bp->tx_ticks ?
8749                         (1000000 / bp->tx_ticks) : 0;
8750
8751                 /* FW SB ID */
8752                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8753                         fp->fw_sb_id;
8754
8755                 /*
8756                  * CQ index among the SB indices: FCoE clients uses the default
8757                  * SB, therefore it's different.
8758                  */
8759                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8760                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8761         }
8762
8763         /* set maximum number of COSs supported by this queue */
8764         init_params->max_cos = fp->max_cos;
8765
8766         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8767             fp->index, init_params->max_cos);
8768
8769         /* set the context pointers queue object */
8770         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8771                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8772                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8773                                 ILT_PAGE_CIDS);
8774                 init_params->cxts[cos] =
8775                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8776         }
8777 }
8778
8779 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8780                         struct bnx2x_queue_state_params *q_params,
8781                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8782                         int tx_index, bool leading)
8783 {
8784         memset(tx_only_params, 0, sizeof(*tx_only_params));
8785
8786         /* Set the command */
8787         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8788
8789         /* Set tx-only QUEUE flags: don't zero statistics */
8790         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8791
8792         /* choose the index of the cid to send the slow path on */
8793         tx_only_params->cid_index = tx_index;
8794
8795         /* Set general TX_ONLY_SETUP parameters */
8796         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8797
8798         /* Set Tx TX_ONLY_SETUP parameters */
8799         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8800
8801         DP(NETIF_MSG_IFUP,
8802            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8803            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8804            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8805            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8806
8807         /* send the ramrod */
8808         return bnx2x_queue_state_change(bp, q_params);
8809 }
8810
8811 /**
8812  * bnx2x_setup_queue - setup queue
8813  *
8814  * @bp:         driver handle
8815  * @fp:         pointer to fastpath
8816  * @leading:    is leading
8817  *
8818  * This function performs 2 steps in a Queue state machine
8819  *      actually: 1) RESET->INIT 2) INIT->SETUP
8820  */
8821
8822 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8823                        bool leading)
8824 {
8825         struct bnx2x_queue_state_params q_params = {NULL};
8826         struct bnx2x_queue_setup_params *setup_params =
8827                                                 &q_params.params.setup;
8828         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8829                                                 &q_params.params.tx_only;
8830         int rc;
8831         u8 tx_index;
8832
8833         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8834
8835         /* reset IGU state skip FCoE L2 queue */
8836         if (!IS_FCOE_FP(fp))
8837                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8838                              IGU_INT_ENABLE, 0);
8839
8840         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8841         /* We want to wait for completion in this context */
8842         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8843
8844         /* Prepare the INIT parameters */
8845         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8846
8847         /* Set the command */
8848         q_params.cmd = BNX2X_Q_CMD_INIT;
8849
8850         /* Change the state to INIT */
8851         rc = bnx2x_queue_state_change(bp, &q_params);
8852         if (rc) {
8853                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8854                 return rc;
8855         }
8856
8857         DP(NETIF_MSG_IFUP, "init complete\n");
8858
8859         /* Now move the Queue to the SETUP state... */
8860         memset(setup_params, 0, sizeof(*setup_params));
8861
8862         /* Set QUEUE flags */
8863         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8864
8865         /* Set general SETUP parameters */
8866         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8867                                 FIRST_TX_COS_INDEX);
8868
8869         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8870                             &setup_params->rxq_params);
8871
8872         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8873                            FIRST_TX_COS_INDEX);
8874
8875         /* Set the command */
8876         q_params.cmd = BNX2X_Q_CMD_SETUP;
8877
8878         if (IS_FCOE_FP(fp))
8879                 bp->fcoe_init = true;
8880
8881         /* Change the state to SETUP */
8882         rc = bnx2x_queue_state_change(bp, &q_params);
8883         if (rc) {
8884                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8885                 return rc;
8886         }
8887
8888         /* loop through the relevant tx-only indices */
8889         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8890               tx_index < fp->max_cos;
8891               tx_index++) {
8892
8893                 /* prepare and send tx-only ramrod*/
8894                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8895                                           tx_only_params, tx_index, leading);
8896                 if (rc) {
8897                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8898                                   fp->index, tx_index);
8899                         return rc;
8900                 }
8901         }
8902
8903         return rc;
8904 }
8905
8906 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8907 {
8908         struct bnx2x_fastpath *fp = &bp->fp[index];
8909         struct bnx2x_fp_txdata *txdata;
8910         struct bnx2x_queue_state_params q_params = {NULL};
8911         int rc, tx_index;
8912
8913         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8914
8915         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8916         /* We want to wait for completion in this context */
8917         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8918
8919         /* close tx-only connections */
8920         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8921              tx_index < fp->max_cos;
8922              tx_index++){
8923
8924                 /* ascertain this is a normal queue*/
8925                 txdata = fp->txdata_ptr[tx_index];
8926
8927                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8928                                                         txdata->txq_index);
8929
8930                 /* send halt terminate on tx-only connection */
8931                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8932                 memset(&q_params.params.terminate, 0,
8933                        sizeof(q_params.params.terminate));
8934                 q_params.params.terminate.cid_index = tx_index;
8935
8936                 rc = bnx2x_queue_state_change(bp, &q_params);
8937                 if (rc)
8938                         return rc;
8939
8940                 /* send halt terminate on tx-only connection */
8941                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8942                 memset(&q_params.params.cfc_del, 0,
8943                        sizeof(q_params.params.cfc_del));
8944                 q_params.params.cfc_del.cid_index = tx_index;
8945                 rc = bnx2x_queue_state_change(bp, &q_params);
8946                 if (rc)
8947                         return rc;
8948         }
8949         /* Stop the primary connection: */
8950         /* ...halt the connection */
8951         q_params.cmd = BNX2X_Q_CMD_HALT;
8952         rc = bnx2x_queue_state_change(bp, &q_params);
8953         if (rc)
8954                 return rc;
8955
8956         /* ...terminate the connection */
8957         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8958         memset(&q_params.params.terminate, 0,
8959                sizeof(q_params.params.terminate));
8960         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8961         rc = bnx2x_queue_state_change(bp, &q_params);
8962         if (rc)
8963                 return rc;
8964         /* ...delete cfc entry */
8965         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8966         memset(&q_params.params.cfc_del, 0,
8967                sizeof(q_params.params.cfc_del));
8968         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8969         return bnx2x_queue_state_change(bp, &q_params);
8970 }
8971
8972 static void bnx2x_reset_func(struct bnx2x *bp)
8973 {
8974         int port = BP_PORT(bp);
8975         int func = BP_FUNC(bp);
8976         int i;
8977
8978         /* Disable the function in the FW */
8979         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8980         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8981         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8982         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8983
8984         /* FP SBs */
8985         for_each_eth_queue(bp, i) {
8986                 struct bnx2x_fastpath *fp = &bp->fp[i];
8987                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8988                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8989                            SB_DISABLED);
8990         }
8991
8992         if (CNIC_LOADED(bp))
8993                 /* CNIC SB */
8994                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8995                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8996                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8997
8998         /* SP SB */
8999         REG_WR8(bp, BAR_CSTRORM_INTMEM +
9000                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
9001                 SB_DISABLED);
9002
9003         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
9004                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
9005                        0);
9006
9007         /* Configure IGU */
9008         if (bp->common.int_block == INT_BLOCK_HC) {
9009                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
9010                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
9011         } else {
9012                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
9013                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
9014         }
9015
9016         if (CNIC_LOADED(bp)) {
9017                 /* Disable Timer scan */
9018                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
9019                 /*
9020                  * Wait for at least 10ms and up to 2 second for the timers
9021                  * scan to complete
9022                  */
9023                 for (i = 0; i < 200; i++) {
9024                         usleep_range(10000, 20000);
9025                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
9026                                 break;
9027                 }
9028         }
9029         /* Clear ILT */
9030         bnx2x_clear_func_ilt(bp, func);
9031
9032         /* Timers workaround bug for E2: if this is vnic-3,
9033          * we need to set the entire ilt range for this timers.
9034          */
9035         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
9036                 struct ilt_client_info ilt_cli;
9037                 /* use dummy TM client */
9038                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9039                 ilt_cli.start = 0;
9040                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9041                 ilt_cli.client_num = ILT_CLIENT_TM;
9042
9043                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9044         }
9045
9046         /* this assumes that reset_port() called before reset_func()*/
9047         if (!CHIP_IS_E1x(bp))
9048                 bnx2x_pf_disable(bp);
9049
9050         bp->dmae_ready = 0;
9051 }
9052
9053 static void bnx2x_reset_port(struct bnx2x *bp)
9054 {
9055         int port = BP_PORT(bp);
9056         u32 val;
9057
9058         /* Reset physical Link */
9059         bnx2x__link_reset(bp);
9060
9061         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9062
9063         /* Do not rcv packets to BRB */
9064         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9065         /* Do not direct rcv packets that are not for MCP to the BRB */
9066         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9067                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9068
9069         /* Configure AEU */
9070         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9071
9072         msleep(100);
9073         /* Check for BRB port occupancy */
9074         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9075         if (val)
9076                 DP(NETIF_MSG_IFDOWN,
9077                    "BRB1 is not empty  %d blocks are occupied\n", val);
9078
9079         /* TODO: Close Doorbell port? */
9080 }
9081
9082 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9083 {
9084         struct bnx2x_func_state_params func_params = {NULL};
9085
9086         /* Prepare parameters for function state transitions */
9087         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9088
9089         func_params.f_obj = &bp->func_obj;
9090         func_params.cmd = BNX2X_F_CMD_HW_RESET;
9091
9092         func_params.params.hw_init.load_phase = load_code;
9093
9094         return bnx2x_func_state_change(bp, &func_params);
9095 }
9096
9097 static int bnx2x_func_stop(struct bnx2x *bp)
9098 {
9099         struct bnx2x_func_state_params func_params = {NULL};
9100         int rc;
9101
9102         /* Prepare parameters for function state transitions */
9103         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9104         func_params.f_obj = &bp->func_obj;
9105         func_params.cmd = BNX2X_F_CMD_STOP;
9106
9107         /*
9108          * Try to stop the function the 'good way'. If fails (in case
9109          * of a parity error during bnx2x_chip_cleanup()) and we are
9110          * not in a debug mode, perform a state transaction in order to
9111          * enable further HW_RESET transaction.
9112          */
9113         rc = bnx2x_func_state_change(bp, &func_params);
9114         if (rc) {
9115 #ifdef BNX2X_STOP_ON_ERROR
9116                 return rc;
9117 #else
9118                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9119                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9120                 return bnx2x_func_state_change(bp, &func_params);
9121 #endif
9122         }
9123
9124         return 0;
9125 }
9126
9127 /**
9128  * bnx2x_send_unload_req - request unload mode from the MCP.
9129  *
9130  * @bp:                 driver handle
9131  * @unload_mode:        requested function's unload mode
9132  *
9133  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9134  */
9135 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9136 {
9137         u32 reset_code = 0;
9138         int port = BP_PORT(bp);
9139
9140         /* Select the UNLOAD request mode */
9141         if (unload_mode == UNLOAD_NORMAL)
9142                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9143
9144         else if (bp->flags & NO_WOL_FLAG)
9145                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9146
9147         else if (bp->wol) {
9148                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9149                 u8 *mac_addr = bp->dev->dev_addr;
9150                 struct pci_dev *pdev = bp->pdev;
9151                 u32 val;
9152                 u16 pmc;
9153
9154                 /* The mac address is written to entries 1-4 to
9155                  * preserve entry 0 which is used by the PMF
9156                  */
9157                 u8 entry = (BP_VN(bp) + 1)*8;
9158
9159                 val = (mac_addr[0] << 8) | mac_addr[1];
9160                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9161
9162                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9163                       (mac_addr[4] << 8) | mac_addr[5];
9164                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9165
9166                 /* Enable the PME and clear the status */
9167                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9168                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9169                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9170
9171                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9172
9173         } else
9174                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9175
9176         /* Send the request to the MCP */
9177         if (!BP_NOMCP(bp))
9178                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9179         else {
9180                 int path = BP_PATH(bp);
9181
9182                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9183                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9184                    bnx2x_load_count[path][2]);
9185                 bnx2x_load_count[path][0]--;
9186                 bnx2x_load_count[path][1 + port]--;
9187                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9188                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9189                    bnx2x_load_count[path][2]);
9190                 if (bnx2x_load_count[path][0] == 0)
9191                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9192                 else if (bnx2x_load_count[path][1 + port] == 0)
9193                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9194                 else
9195                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9196         }
9197
9198         return reset_code;
9199 }
9200
9201 /**
9202  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9203  *
9204  * @bp:         driver handle
9205  * @keep_link:          true iff link should be kept up
9206  */
9207 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9208 {
9209         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9210
9211         /* Report UNLOAD_DONE to MCP */
9212         if (!BP_NOMCP(bp))
9213                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9214 }
9215
9216 static int bnx2x_func_wait_started(struct bnx2x *bp)
9217 {
9218         int tout = 50;
9219         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9220
9221         if (!bp->port.pmf)
9222                 return 0;
9223
9224         /*
9225          * (assumption: No Attention from MCP at this stage)
9226          * PMF probably in the middle of TX disable/enable transaction
9227          * 1. Sync IRS for default SB
9228          * 2. Sync SP queue - this guarantees us that attention handling started
9229          * 3. Wait, that TX disable/enable transaction completes
9230          *
9231          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9232          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9233          * received completion for the transaction the state is TX_STOPPED.
9234          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9235          * transaction.
9236          */
9237
9238         /* make sure default SB ISR is done */
9239         if (msix)
9240                 synchronize_irq(bp->msix_table[0].vector);
9241         else
9242                 synchronize_irq(bp->pdev->irq);
9243
9244         flush_workqueue(bnx2x_wq);
9245         flush_workqueue(bnx2x_iov_wq);
9246
9247         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9248                                 BNX2X_F_STATE_STARTED && tout--)
9249                 msleep(20);
9250
9251         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9252                                                 BNX2X_F_STATE_STARTED) {
9253 #ifdef BNX2X_STOP_ON_ERROR
9254                 BNX2X_ERR("Wrong function state\n");
9255                 return -EBUSY;
9256 #else
9257                 /*
9258                  * Failed to complete the transaction in a "good way"
9259                  * Force both transactions with CLR bit
9260                  */
9261                 struct bnx2x_func_state_params func_params = {NULL};
9262
9263                 DP(NETIF_MSG_IFDOWN,
9264                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9265
9266                 func_params.f_obj = &bp->func_obj;
9267                 __set_bit(RAMROD_DRV_CLR_ONLY,
9268                                         &func_params.ramrod_flags);
9269
9270                 /* STARTED-->TX_ST0PPED */
9271                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9272                 bnx2x_func_state_change(bp, &func_params);
9273
9274                 /* TX_ST0PPED-->STARTED */
9275                 func_params.cmd = BNX2X_F_CMD_TX_START;
9276                 return bnx2x_func_state_change(bp, &func_params);
9277 #endif
9278         }
9279
9280         return 0;
9281 }
9282
9283 static void bnx2x_disable_ptp(struct bnx2x *bp)
9284 {
9285         int port = BP_PORT(bp);
9286
9287         /* Disable sending PTP packets to host */
9288         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9289                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9290
9291         /* Reset PTP event detection rules */
9292         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9293                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9294         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9295                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9296         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9297                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9298         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9299                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9300
9301         /* Disable the PTP feature */
9302         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9303                NIG_REG_P0_PTP_EN, 0x0);
9304 }
9305
9306 /* Called during unload, to stop PTP-related stuff */
9307 static void bnx2x_stop_ptp(struct bnx2x *bp)
9308 {
9309         /* Cancel PTP work queue. Should be done after the Tx queues are
9310          * drained to prevent additional scheduling.
9311          */
9312         cancel_work_sync(&bp->ptp_task);
9313
9314         if (bp->ptp_tx_skb) {
9315                 dev_kfree_skb_any(bp->ptp_tx_skb);
9316                 bp->ptp_tx_skb = NULL;
9317         }
9318
9319         /* Disable PTP in HW */
9320         bnx2x_disable_ptp(bp);
9321
9322         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9323 }
9324
9325 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9326 {
9327         int port = BP_PORT(bp);
9328         int i, rc = 0;
9329         u8 cos;
9330         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9331         u32 reset_code;
9332
9333         /* Wait until tx fastpath tasks complete */
9334         for_each_tx_queue(bp, i) {
9335                 struct bnx2x_fastpath *fp = &bp->fp[i];
9336
9337                 for_each_cos_in_tx_queue(fp, cos)
9338                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9339 #ifdef BNX2X_STOP_ON_ERROR
9340                 if (rc)
9341                         return;
9342 #endif
9343         }
9344
9345         /* Give HW time to discard old tx messages */
9346         usleep_range(1000, 2000);
9347
9348         /* Clean all ETH MACs */
9349         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9350                                 false);
9351         if (rc < 0)
9352                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9353
9354         /* Clean up UC list  */
9355         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9356                                 true);
9357         if (rc < 0)
9358                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9359                           rc);
9360
9361         /* The whole *vlan_obj structure may be not initialized if VLAN
9362          * filtering offload is not supported by hardware. Currently this is
9363          * true for all hardware covered by CHIP_IS_E1x().
9364          */
9365         if (!CHIP_IS_E1x(bp)) {
9366                 /* Remove all currently configured VLANs */
9367                 rc = bnx2x_del_all_vlans(bp);
9368                 if (rc < 0)
9369                         BNX2X_ERR("Failed to delete all VLANs\n");
9370         }
9371
9372         /* Disable LLH */
9373         if (!CHIP_IS_E1(bp))
9374                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9375
9376         /* Set "drop all" (stop Rx).
9377          * We need to take a netif_addr_lock() here in order to prevent
9378          * a race between the completion code and this code.
9379          */
9380         netif_addr_lock_bh(bp->dev);
9381         /* Schedule the rx_mode command */
9382         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9383                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9384         else
9385                 bnx2x_set_storm_rx_mode(bp);
9386
9387         /* Cleanup multicast configuration */
9388         rparam.mcast_obj = &bp->mcast_obj;
9389         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9390         if (rc < 0)
9391                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9392
9393         netif_addr_unlock_bh(bp->dev);
9394
9395         bnx2x_iov_chip_cleanup(bp);
9396
9397         /*
9398          * Send the UNLOAD_REQUEST to the MCP. This will return if
9399          * this function should perform FUNC, PORT or COMMON HW
9400          * reset.
9401          */
9402         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9403
9404         /*
9405          * (assumption: No Attention from MCP at this stage)
9406          * PMF probably in the middle of TX disable/enable transaction
9407          */
9408         rc = bnx2x_func_wait_started(bp);
9409         if (rc) {
9410                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9411 #ifdef BNX2X_STOP_ON_ERROR
9412                 return;
9413 #endif
9414         }
9415
9416         /* Close multi and leading connections
9417          * Completions for ramrods are collected in a synchronous way
9418          */
9419         for_each_eth_queue(bp, i)
9420                 if (bnx2x_stop_queue(bp, i))
9421 #ifdef BNX2X_STOP_ON_ERROR
9422                         return;
9423 #else
9424                         goto unload_error;
9425 #endif
9426
9427         if (CNIC_LOADED(bp)) {
9428                 for_each_cnic_queue(bp, i)
9429                         if (bnx2x_stop_queue(bp, i))
9430 #ifdef BNX2X_STOP_ON_ERROR
9431                                 return;
9432 #else
9433                                 goto unload_error;
9434 #endif
9435         }
9436
9437         /* If SP settings didn't get completed so far - something
9438          * very wrong has happen.
9439          */
9440         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9441                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9442
9443 #ifndef BNX2X_STOP_ON_ERROR
9444 unload_error:
9445 #endif
9446         rc = bnx2x_func_stop(bp);
9447         if (rc) {
9448                 BNX2X_ERR("Function stop failed!\n");
9449 #ifdef BNX2X_STOP_ON_ERROR
9450                 return;
9451 #endif
9452         }
9453
9454         /* stop_ptp should be after the Tx queues are drained to prevent
9455          * scheduling to the cancelled PTP work queue. It should also be after
9456          * function stop ramrod is sent, since as part of this ramrod FW access
9457          * PTP registers.
9458          */
9459         if (bp->flags & PTP_SUPPORTED)
9460                 bnx2x_stop_ptp(bp);
9461
9462         /* Disable HW interrupts, NAPI */
9463         bnx2x_netif_stop(bp, 1);
9464         /* Delete all NAPI objects */
9465         bnx2x_del_all_napi(bp);
9466         if (CNIC_LOADED(bp))
9467                 bnx2x_del_all_napi_cnic(bp);
9468
9469         /* Release IRQs */
9470         bnx2x_free_irq(bp);
9471
9472         /* Reset the chip, unless PCI function is offline. If we reach this
9473          * point following a PCI error handling, it means device is really
9474          * in a bad state and we're about to remove it, so reset the chip
9475          * is not a good idea.
9476          */
9477         if (!pci_channel_offline(bp->pdev)) {
9478                 rc = bnx2x_reset_hw(bp, reset_code);
9479                 if (rc)
9480                         BNX2X_ERR("HW_RESET failed\n");
9481         }
9482
9483         /* Report UNLOAD_DONE to MCP */
9484         bnx2x_send_unload_done(bp, keep_link);
9485 }
9486
9487 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9488 {
9489         u32 val;
9490
9491         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9492
9493         if (CHIP_IS_E1(bp)) {
9494                 int port = BP_PORT(bp);
9495                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9496                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9497
9498                 val = REG_RD(bp, addr);
9499                 val &= ~(0x300);
9500                 REG_WR(bp, addr, val);
9501         } else {
9502                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9503                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9504                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9505                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9506         }
9507 }
9508
9509 /* Close gates #2, #3 and #4: */
9510 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9511 {
9512         u32 val;
9513
9514         /* Gates #2 and #4a are closed/opened for "not E1" only */
9515         if (!CHIP_IS_E1(bp)) {
9516                 /* #4 */
9517                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9518                 /* #2 */
9519                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9520         }
9521
9522         /* #3 */
9523         if (CHIP_IS_E1x(bp)) {
9524                 /* Prevent interrupts from HC on both ports */
9525                 val = REG_RD(bp, HC_REG_CONFIG_1);
9526                 REG_WR(bp, HC_REG_CONFIG_1,
9527                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9528                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9529
9530                 val = REG_RD(bp, HC_REG_CONFIG_0);
9531                 REG_WR(bp, HC_REG_CONFIG_0,
9532                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9533                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9534         } else {
9535                 /* Prevent incoming interrupts in IGU */
9536                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9537
9538                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9539                        (!close) ?
9540                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9541                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9542         }
9543
9544         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9545                 close ? "closing" : "opening");
9546         mmiowb();
9547 }
9548
9549 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9550
9551 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9552 {
9553         /* Do some magic... */
9554         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9555         *magic_val = val & SHARED_MF_CLP_MAGIC;
9556         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9557 }
9558
9559 /**
9560  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9561  *
9562  * @bp:         driver handle
9563  * @magic_val:  old value of the `magic' bit.
9564  */
9565 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9566 {
9567         /* Restore the `magic' bit value... */
9568         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9569         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9570                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9571 }
9572
9573 /**
9574  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9575  *
9576  * @bp:         driver handle
9577  * @magic_val:  old value of 'magic' bit.
9578  *
9579  * Takes care of CLP configurations.
9580  */
9581 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9582 {
9583         u32 shmem;
9584         u32 validity_offset;
9585
9586         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9587
9588         /* Set `magic' bit in order to save MF config */
9589         if (!CHIP_IS_E1(bp))
9590                 bnx2x_clp_reset_prep(bp, magic_val);
9591
9592         /* Get shmem offset */
9593         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9594         validity_offset =
9595                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9596
9597         /* Clear validity map flags */
9598         if (shmem > 0)
9599                 REG_WR(bp, shmem + validity_offset, 0);
9600 }
9601
9602 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9603 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9604
9605 /**
9606  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9607  *
9608  * @bp: driver handle
9609  */
9610 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9611 {
9612         /* special handling for emulation and FPGA,
9613            wait 10 times longer */
9614         if (CHIP_REV_IS_SLOW(bp))
9615                 msleep(MCP_ONE_TIMEOUT*10);
9616         else
9617                 msleep(MCP_ONE_TIMEOUT);
9618 }
9619
9620 /*
9621  * initializes bp->common.shmem_base and waits for validity signature to appear
9622  */
9623 static int bnx2x_init_shmem(struct bnx2x *bp)
9624 {
9625         int cnt = 0;
9626         u32 val = 0;
9627
9628         do {
9629                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9630
9631                 /* If we read all 0xFFs, means we are in PCI error state and
9632                  * should bail out to avoid crashes on adapter's FW reads.
9633                  */
9634                 if (bp->common.shmem_base == 0xFFFFFFFF) {
9635                         bp->flags |= NO_MCP_FLAG;
9636                         return -ENODEV;
9637                 }
9638
9639                 if (bp->common.shmem_base) {
9640                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9641                         if (val & SHR_MEM_VALIDITY_MB)
9642                                 return 0;
9643                 }
9644
9645                 bnx2x_mcp_wait_one(bp);
9646
9647         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9648
9649         BNX2X_ERR("BAD MCP validity signature\n");
9650
9651         return -ENODEV;
9652 }
9653
9654 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9655 {
9656         int rc = bnx2x_init_shmem(bp);
9657
9658         /* Restore the `magic' bit value */
9659         if (!CHIP_IS_E1(bp))
9660                 bnx2x_clp_reset_done(bp, magic_val);
9661
9662         return rc;
9663 }
9664
9665 static void bnx2x_pxp_prep(struct bnx2x *bp)
9666 {
9667         if (!CHIP_IS_E1(bp)) {
9668                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9669                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9670                 mmiowb();
9671         }
9672 }
9673
9674 /*
9675  * Reset the whole chip except for:
9676  *      - PCIE core
9677  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9678  *              one reset bit)
9679  *      - IGU
9680  *      - MISC (including AEU)
9681  *      - GRC
9682  *      - RBCN, RBCP
9683  */
9684 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9685 {
9686         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9687         u32 global_bits2, stay_reset2;
9688
9689         /*
9690          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9691          * (per chip) blocks.
9692          */
9693         global_bits2 =
9694                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9695                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9696
9697         /* Don't reset the following blocks.
9698          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9699          *            reset, as in 4 port device they might still be owned
9700          *            by the MCP (there is only one leader per path).
9701          */
9702         not_reset_mask1 =
9703                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9704                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9705                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9706
9707         not_reset_mask2 =
9708                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9709                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9710                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9711                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9712                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9713                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9714                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9715                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9716                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9717                 MISC_REGISTERS_RESET_REG_2_PGLC |
9718                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9719                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9720                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9721                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9722                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9723                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9724
9725         /*
9726          * Keep the following blocks in reset:
9727          *  - all xxMACs are handled by the bnx2x_link code.
9728          */
9729         stay_reset2 =
9730                 MISC_REGISTERS_RESET_REG_2_XMAC |
9731                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9732
9733         /* Full reset masks according to the chip */
9734         reset_mask1 = 0xffffffff;
9735
9736         if (CHIP_IS_E1(bp))
9737                 reset_mask2 = 0xffff;
9738         else if (CHIP_IS_E1H(bp))
9739                 reset_mask2 = 0x1ffff;
9740         else if (CHIP_IS_E2(bp))
9741                 reset_mask2 = 0xfffff;
9742         else /* CHIP_IS_E3 */
9743                 reset_mask2 = 0x3ffffff;
9744
9745         /* Don't reset global blocks unless we need to */
9746         if (!global)
9747                 reset_mask2 &= ~global_bits2;
9748
9749         /*
9750          * In case of attention in the QM, we need to reset PXP
9751          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9752          * because otherwise QM reset would release 'close the gates' shortly
9753          * before resetting the PXP, then the PSWRQ would send a write
9754          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9755          * read the payload data from PSWWR, but PSWWR would not
9756          * respond. The write queue in PGLUE would stuck, dmae commands
9757          * would not return. Therefore it's important to reset the second
9758          * reset register (containing the
9759          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9760          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9761          * bit).
9762          */
9763         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9764                reset_mask2 & (~not_reset_mask2));
9765
9766         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9767                reset_mask1 & (~not_reset_mask1));
9768
9769         barrier();
9770         mmiowb();
9771
9772         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9773                reset_mask2 & (~stay_reset2));
9774
9775         barrier();
9776         mmiowb();
9777
9778         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9779         mmiowb();
9780 }
9781
9782 /**
9783  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9784  * It should get cleared in no more than 1s.
9785  *
9786  * @bp: driver handle
9787  *
9788  * It should get cleared in no more than 1s. Returns 0 if
9789  * pending writes bit gets cleared.
9790  */
9791 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9792 {
9793         u32 cnt = 1000;
9794         u32 pend_bits = 0;
9795
9796         do {
9797                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9798
9799                 if (pend_bits == 0)
9800                         break;
9801
9802                 usleep_range(1000, 2000);
9803         } while (cnt-- > 0);
9804
9805         if (cnt <= 0) {
9806                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9807                           pend_bits);
9808                 return -EBUSY;
9809         }
9810
9811         return 0;
9812 }
9813
9814 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9815 {
9816         int cnt = 1000;
9817         u32 val = 0;
9818         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9819         u32 tags_63_32 = 0;
9820
9821         /* Empty the Tetris buffer, wait for 1s */
9822         do {
9823                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9824                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9825                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9826                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9827                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9828                 if (CHIP_IS_E3(bp))
9829                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9830
9831                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9832                     ((port_is_idle_0 & 0x1) == 0x1) &&
9833                     ((port_is_idle_1 & 0x1) == 0x1) &&
9834                     (pgl_exp_rom2 == 0xffffffff) &&
9835                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9836                         break;
9837                 usleep_range(1000, 2000);
9838         } while (cnt-- > 0);
9839
9840         if (cnt <= 0) {
9841                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9842                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9843                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9844                           pgl_exp_rom2);
9845                 return -EAGAIN;
9846         }
9847
9848         barrier();
9849
9850         /* Close gates #2, #3 and #4 */
9851         bnx2x_set_234_gates(bp, true);
9852
9853         /* Poll for IGU VQs for 57712 and newer chips */
9854         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9855                 return -EAGAIN;
9856
9857         /* TBD: Indicate that "process kill" is in progress to MCP */
9858
9859         /* Clear "unprepared" bit */
9860         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9861         barrier();
9862
9863         /* Make sure all is written to the chip before the reset */
9864         mmiowb();
9865
9866         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9867          * PSWHST, GRC and PSWRD Tetris buffer.
9868          */
9869         usleep_range(1000, 2000);
9870
9871         /* Prepare to chip reset: */
9872         /* MCP */
9873         if (global)
9874                 bnx2x_reset_mcp_prep(bp, &val);
9875
9876         /* PXP */
9877         bnx2x_pxp_prep(bp);
9878         barrier();
9879
9880         /* reset the chip */
9881         bnx2x_process_kill_chip_reset(bp, global);
9882         barrier();
9883
9884         /* clear errors in PGB */
9885         if (!CHIP_IS_E1x(bp))
9886                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9887
9888         /* Recover after reset: */
9889         /* MCP */
9890         if (global && bnx2x_reset_mcp_comp(bp, val))
9891                 return -EAGAIN;
9892
9893         /* TBD: Add resetting the NO_MCP mode DB here */
9894
9895         /* Open the gates #2, #3 and #4 */
9896         bnx2x_set_234_gates(bp, false);
9897
9898         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9899          * reset state, re-enable attentions. */
9900
9901         return 0;
9902 }
9903
9904 static int bnx2x_leader_reset(struct bnx2x *bp)
9905 {
9906         int rc = 0;
9907         bool global = bnx2x_reset_is_global(bp);
9908         u32 load_code;
9909
9910         /* if not going to reset MCP - load "fake" driver to reset HW while
9911          * driver is owner of the HW
9912          */
9913         if (!global && !BP_NOMCP(bp)) {
9914                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9915                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9916                 if (!load_code) {
9917                         BNX2X_ERR("MCP response failure, aborting\n");
9918                         rc = -EAGAIN;
9919                         goto exit_leader_reset;
9920                 }
9921                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9922                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9923                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9924                         rc = -EAGAIN;
9925                         goto exit_leader_reset2;
9926                 }
9927                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9928                 if (!load_code) {
9929                         BNX2X_ERR("MCP response failure, aborting\n");
9930                         rc = -EAGAIN;
9931                         goto exit_leader_reset2;
9932                 }
9933         }
9934
9935         /* Try to recover after the failure */
9936         if (bnx2x_process_kill(bp, global)) {
9937                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9938                           BP_PATH(bp));
9939                 rc = -EAGAIN;
9940                 goto exit_leader_reset2;
9941         }
9942
9943         /*
9944          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9945          * state.
9946          */
9947         bnx2x_set_reset_done(bp);
9948         if (global)
9949                 bnx2x_clear_reset_global(bp);
9950
9951 exit_leader_reset2:
9952         /* unload "fake driver" if it was loaded */
9953         if (!global && !BP_NOMCP(bp)) {
9954                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9955                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9956         }
9957 exit_leader_reset:
9958         bp->is_leader = 0;
9959         bnx2x_release_leader_lock(bp);
9960         smp_mb();
9961         return rc;
9962 }
9963
9964 static void bnx2x_recovery_failed(struct bnx2x *bp)
9965 {
9966         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9967
9968         /* Disconnect this device */
9969         netif_device_detach(bp->dev);
9970
9971         /*
9972          * Block ifup for all function on this engine until "process kill"
9973          * or power cycle.
9974          */
9975         bnx2x_set_reset_in_progress(bp);
9976
9977         /* Shut down the power */
9978         bnx2x_set_power_state(bp, PCI_D3hot);
9979
9980         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9981
9982         smp_mb();
9983 }
9984
9985 /*
9986  * Assumption: runs under rtnl lock. This together with the fact
9987  * that it's called only from bnx2x_sp_rtnl() ensure that it
9988  * will never be called when netif_running(bp->dev) is false.
9989  */
9990 static void bnx2x_parity_recover(struct bnx2x *bp)
9991 {
9992         u32 error_recovered, error_unrecovered;
9993         bool is_parity, global = false;
9994 #ifdef CONFIG_BNX2X_SRIOV
9995         int vf_idx;
9996
9997         for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) {
9998                 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
9999
10000                 if (vf)
10001                         vf->state = VF_LOST;
10002         }
10003 #endif
10004         DP(NETIF_MSG_HW, "Handling parity\n");
10005         while (1) {
10006                 switch (bp->recovery_state) {
10007                 case BNX2X_RECOVERY_INIT:
10008                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
10009                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
10010                         WARN_ON(!is_parity);
10011
10012                         /* Try to get a LEADER_LOCK HW lock */
10013                         if (bnx2x_trylock_leader_lock(bp)) {
10014                                 bnx2x_set_reset_in_progress(bp);
10015                                 /*
10016                                  * Check if there is a global attention and if
10017                                  * there was a global attention, set the global
10018                                  * reset bit.
10019                                  */
10020
10021                                 if (global)
10022                                         bnx2x_set_reset_global(bp);
10023
10024                                 bp->is_leader = 1;
10025                         }
10026
10027                         /* Stop the driver */
10028                         /* If interface has been removed - break */
10029                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
10030                                 return;
10031
10032                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
10033
10034                         /* Ensure "is_leader", MCP command sequence and
10035                          * "recovery_state" update values are seen on other
10036                          * CPUs.
10037                          */
10038                         smp_mb();
10039                         break;
10040
10041                 case BNX2X_RECOVERY_WAIT:
10042                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
10043                         if (bp->is_leader) {
10044                                 int other_engine = BP_PATH(bp) ? 0 : 1;
10045                                 bool other_load_status =
10046                                         bnx2x_get_load_status(bp, other_engine);
10047                                 bool load_status =
10048                                         bnx2x_get_load_status(bp, BP_PATH(bp));
10049                                 global = bnx2x_reset_is_global(bp);
10050
10051                                 /*
10052                                  * In case of a parity in a global block, let
10053                                  * the first leader that performs a
10054                                  * leader_reset() reset the global blocks in
10055                                  * order to clear global attentions. Otherwise
10056                                  * the gates will remain closed for that
10057                                  * engine.
10058                                  */
10059                                 if (load_status ||
10060                                     (global && other_load_status)) {
10061                                         /* Wait until all other functions get
10062                                          * down.
10063                                          */
10064                                         schedule_delayed_work(&bp->sp_rtnl_task,
10065                                                                 HZ/10);
10066                                         return;
10067                                 } else {
10068                                         /* If all other functions got down -
10069                                          * try to bring the chip back to
10070                                          * normal. In any case it's an exit
10071                                          * point for a leader.
10072                                          */
10073                                         if (bnx2x_leader_reset(bp)) {
10074                                                 bnx2x_recovery_failed(bp);
10075                                                 return;
10076                                         }
10077
10078                                         /* If we are here, means that the
10079                                          * leader has succeeded and doesn't
10080                                          * want to be a leader any more. Try
10081                                          * to continue as a none-leader.
10082                                          */
10083                                         break;
10084                                 }
10085                         } else { /* non-leader */
10086                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10087                                         /* Try to get a LEADER_LOCK HW lock as
10088                                          * long as a former leader may have
10089                                          * been unloaded by the user or
10090                                          * released a leadership by another
10091                                          * reason.
10092                                          */
10093                                         if (bnx2x_trylock_leader_lock(bp)) {
10094                                                 /* I'm a leader now! Restart a
10095                                                  * switch case.
10096                                                  */
10097                                                 bp->is_leader = 1;
10098                                                 break;
10099                                         }
10100
10101                                         schedule_delayed_work(&bp->sp_rtnl_task,
10102                                                                 HZ/10);
10103                                         return;
10104
10105                                 } else {
10106                                         /*
10107                                          * If there was a global attention, wait
10108                                          * for it to be cleared.
10109                                          */
10110                                         if (bnx2x_reset_is_global(bp)) {
10111                                                 schedule_delayed_work(
10112                                                         &bp->sp_rtnl_task,
10113                                                         HZ/10);
10114                                                 return;
10115                                         }
10116
10117                                         error_recovered =
10118                                           bp->eth_stats.recoverable_error;
10119                                         error_unrecovered =
10120                                           bp->eth_stats.unrecoverable_error;
10121                                         bp->recovery_state =
10122                                                 BNX2X_RECOVERY_NIC_LOADING;
10123                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10124                                                 error_unrecovered++;
10125                                                 netdev_err(bp->dev,
10126                                                            "Recovery failed. Power cycle needed\n");
10127                                                 /* Disconnect this device */
10128                                                 netif_device_detach(bp->dev);
10129                                                 /* Shut down the power */
10130                                                 bnx2x_set_power_state(
10131                                                         bp, PCI_D3hot);
10132                                                 smp_mb();
10133                                         } else {
10134                                                 bp->recovery_state =
10135                                                         BNX2X_RECOVERY_DONE;
10136                                                 error_recovered++;
10137                                                 smp_mb();
10138                                         }
10139                                         bp->eth_stats.recoverable_error =
10140                                                 error_recovered;
10141                                         bp->eth_stats.unrecoverable_error =
10142                                                 error_unrecovered;
10143
10144                                         return;
10145                                 }
10146                         }
10147                 default:
10148                         return;
10149                 }
10150         }
10151 }
10152
10153 static int bnx2x_udp_port_update(struct bnx2x *bp)
10154 {
10155         struct bnx2x_func_switch_update_params *switch_update_params;
10156         struct bnx2x_func_state_params func_params = {NULL};
10157         struct bnx2x_udp_tunnel *udp_tunnel;
10158         u16 vxlan_port = 0, geneve_port = 0;
10159         int rc;
10160
10161         switch_update_params = &func_params.params.switch_update;
10162
10163         /* Prepare parameters for function state transitions */
10164         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10165         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10166
10167         func_params.f_obj = &bp->func_obj;
10168         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10169
10170         /* Function parameters */
10171         __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10172                   &switch_update_params->changes);
10173
10174         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10175                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10176                 geneve_port = udp_tunnel->dst_port;
10177                 switch_update_params->geneve_dst_port = geneve_port;
10178         }
10179
10180         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10181                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10182                 vxlan_port = udp_tunnel->dst_port;
10183                 switch_update_params->vxlan_dst_port = vxlan_port;
10184         }
10185
10186         /* Re-enable inner-rss for the offloaded UDP tunnels */
10187         __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10188                   &switch_update_params->changes);
10189
10190         rc = bnx2x_func_state_change(bp, &func_params);
10191         if (rc)
10192                 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10193                           vxlan_port, geneve_port, rc);
10194         else
10195                 DP(BNX2X_MSG_SP,
10196                    "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10197                    vxlan_port, geneve_port);
10198
10199         return rc;
10200 }
10201
10202 static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10203                                  enum bnx2x_udp_port_type type)
10204 {
10205         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10206
10207         if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp))
10208                 return;
10209
10210         if (udp_port->count && udp_port->dst_port == port) {
10211                 udp_port->count++;
10212                 return;
10213         }
10214
10215         if (udp_port->count) {
10216                 DP(BNX2X_MSG_SP,
10217                    "UDP tunnel [%d] -  destination port limit reached\n",
10218                    type);
10219                 return;
10220         }
10221
10222         udp_port->dst_port = port;
10223         udp_port->count = 1;
10224         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10225 }
10226
10227 static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10228                                  enum bnx2x_udp_port_type type)
10229 {
10230         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10231
10232         if (!IS_PF(bp) || CHIP_IS_E1x(bp))
10233                 return;
10234
10235         if (!udp_port->count || udp_port->dst_port != port) {
10236                 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10237                    type);
10238                 return;
10239         }
10240
10241         /* Remove reference, and make certain it's no longer in use */
10242         udp_port->count--;
10243         if (udp_port->count)
10244                 return;
10245         udp_port->dst_port = 0;
10246
10247         if (netif_running(bp->dev))
10248                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10249         else
10250                 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10251                    type, port);
10252 }
10253
10254 static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10255                                  struct udp_tunnel_info *ti)
10256 {
10257         struct bnx2x *bp = netdev_priv(netdev);
10258         u16 t_port = ntohs(ti->port);
10259
10260         switch (ti->type) {
10261         case UDP_TUNNEL_TYPE_VXLAN:
10262                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10263                 break;
10264         case UDP_TUNNEL_TYPE_GENEVE:
10265                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10266                 break;
10267         default:
10268                 break;
10269         }
10270 }
10271
10272 static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10273                                  struct udp_tunnel_info *ti)
10274 {
10275         struct bnx2x *bp = netdev_priv(netdev);
10276         u16 t_port = ntohs(ti->port);
10277
10278         switch (ti->type) {
10279         case UDP_TUNNEL_TYPE_VXLAN:
10280                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10281                 break;
10282         case UDP_TUNNEL_TYPE_GENEVE:
10283                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10284                 break;
10285         default:
10286                 break;
10287         }
10288 }
10289
10290 static int bnx2x_close(struct net_device *dev);
10291
10292 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10293  * scheduled on a general queue in order to prevent a dead lock.
10294  */
10295 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10296 {
10297         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10298
10299         rtnl_lock();
10300
10301         if (!netif_running(bp->dev)) {
10302                 rtnl_unlock();
10303                 return;
10304         }
10305
10306         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10307 #ifdef BNX2X_STOP_ON_ERROR
10308                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10309                           "you will need to reboot when done\n");
10310                 goto sp_rtnl_not_reset;
10311 #endif
10312                 /*
10313                  * Clear all pending SP commands as we are going to reset the
10314                  * function anyway.
10315                  */
10316                 bp->sp_rtnl_state = 0;
10317                 smp_mb();
10318
10319                 bnx2x_parity_recover(bp);
10320
10321                 rtnl_unlock();
10322                 return;
10323         }
10324
10325         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10326 #ifdef BNX2X_STOP_ON_ERROR
10327                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10328                           "you will need to reboot when done\n");
10329                 goto sp_rtnl_not_reset;
10330 #endif
10331
10332                 /*
10333                  * Clear all pending SP commands as we are going to reset the
10334                  * function anyway.
10335                  */
10336                 bp->sp_rtnl_state = 0;
10337                 smp_mb();
10338
10339                 /* Immediately indicate link as down */
10340                 bp->link_vars.link_up = 0;
10341                 bp->force_link_down = true;
10342                 netif_carrier_off(bp->dev);
10343                 BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
10344
10345                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10346                 bnx2x_nic_load(bp, LOAD_NORMAL);
10347
10348                 rtnl_unlock();
10349                 return;
10350         }
10351 #ifdef BNX2X_STOP_ON_ERROR
10352 sp_rtnl_not_reset:
10353 #endif
10354         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10355                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10356         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10357                 bnx2x_after_function_update(bp);
10358         /*
10359          * in case of fan failure we need to reset id if the "stop on error"
10360          * debug flag is set, since we trying to prevent permanent overheating
10361          * damage
10362          */
10363         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10364                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10365                 netif_device_detach(bp->dev);
10366                 bnx2x_close(bp->dev);
10367                 rtnl_unlock();
10368                 return;
10369         }
10370
10371         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10372                 DP(BNX2X_MSG_SP,
10373                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10374                 bnx2x_vfpf_set_mcast(bp->dev);
10375         }
10376         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10377                                &bp->sp_rtnl_state)){
10378                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10379                         bnx2x_tx_disable(bp);
10380                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10381                 }
10382         }
10383
10384         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10385                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10386                 bnx2x_set_rx_mode_inner(bp);
10387         }
10388
10389         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10390                                &bp->sp_rtnl_state))
10391                 bnx2x_pf_set_vfs_vlan(bp);
10392
10393         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10394                 bnx2x_dcbx_stop_hw_tx(bp);
10395                 bnx2x_dcbx_resume_hw_tx(bp);
10396         }
10397
10398         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10399                                &bp->sp_rtnl_state))
10400                 bnx2x_update_mng_version(bp);
10401
10402         if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state))
10403                 bnx2x_handle_update_svid_cmd(bp);
10404
10405         if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
10406                                &bp->sp_rtnl_state)) {
10407                 if (bnx2x_udp_port_update(bp)) {
10408                         /* On error, forget configuration */
10409                         memset(bp->udp_tunnel_ports, 0,
10410                                sizeof(struct bnx2x_udp_tunnel) *
10411                                BNX2X_UDP_PORT_MAX);
10412                 } else {
10413                         /* Since we don't store additional port information,
10414                          * if no ports are configured for any feature ask for
10415                          * information about currently configured ports.
10416                          */
10417                         if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10418                             !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10419                                 udp_tunnel_get_rx_info(bp->dev);
10420                 }
10421         }
10422
10423         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10424          * can be called from other contexts as well)
10425          */
10426         rtnl_unlock();
10427
10428         /* enable SR-IOV if applicable */
10429         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10430                                                &bp->sp_rtnl_state)) {
10431                 bnx2x_disable_sriov(bp);
10432                 bnx2x_enable_sriov(bp);
10433         }
10434 }
10435
10436 static void bnx2x_period_task(struct work_struct *work)
10437 {
10438         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10439
10440         if (!netif_running(bp->dev))
10441                 goto period_task_exit;
10442
10443         if (CHIP_REV_IS_SLOW(bp)) {
10444                 BNX2X_ERR("period task called on emulation, ignoring\n");
10445                 goto period_task_exit;
10446         }
10447
10448         bnx2x_acquire_phy_lock(bp);
10449         /*
10450          * The barrier is needed to ensure the ordering between the writing to
10451          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10452          * the reading here.
10453          */
10454         smp_mb();
10455         if (bp->port.pmf) {
10456                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10457
10458                 /* Re-queue task in 1 sec */
10459                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10460         }
10461
10462         bnx2x_release_phy_lock(bp);
10463 period_task_exit:
10464         return;
10465 }
10466
10467 /*
10468  * Init service functions
10469  */
10470
10471 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10472 {
10473         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10474         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10475         return base + (BP_ABS_FUNC(bp)) * stride;
10476 }
10477
10478 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10479                                          u8 port, u32 reset_reg,
10480                                          struct bnx2x_mac_vals *vals)
10481 {
10482         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10483         u32 base_addr;
10484
10485         if (!(mask & reset_reg))
10486                 return false;
10487
10488         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10489         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10490         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10491         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10492         REG_WR(bp, vals->umac_addr[port], 0);
10493
10494         return true;
10495 }
10496
10497 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10498                                         struct bnx2x_mac_vals *vals)
10499 {
10500         u32 val, base_addr, offset, mask, reset_reg;
10501         bool mac_stopped = false;
10502         u8 port = BP_PORT(bp);
10503
10504         /* reset addresses as they also mark which values were changed */
10505         memset(vals, 0, sizeof(*vals));
10506
10507         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10508
10509         if (!CHIP_IS_E3(bp)) {
10510                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10511                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10512                 if ((mask & reset_reg) && val) {
10513                         u32 wb_data[2];
10514                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10515                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10516                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10517                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10518                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10519
10520                         /*
10521                          * use rd/wr since we cannot use dmae. This is safe
10522                          * since MCP won't access the bus due to the request
10523                          * to unload, and no function on the path can be
10524                          * loaded at this time.
10525                          */
10526                         wb_data[0] = REG_RD(bp, base_addr + offset);
10527                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10528                         vals->bmac_addr = base_addr + offset;
10529                         vals->bmac_val[0] = wb_data[0];
10530                         vals->bmac_val[1] = wb_data[1];
10531                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10532                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10533                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10534                 }
10535                 BNX2X_DEV_INFO("Disable emac Rx\n");
10536                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10537                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10538                 REG_WR(bp, vals->emac_addr, 0);
10539                 mac_stopped = true;
10540         } else {
10541                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10542                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10543                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10544                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10545                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10546                                val & ~(1 << 1));
10547                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10548                                val | (1 << 1));
10549                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10550                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10551                         REG_WR(bp, vals->xmac_addr, 0);
10552                         mac_stopped = true;
10553                 }
10554
10555                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10556                                                             reset_reg, vals);
10557                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10558                                                             reset_reg, vals);
10559         }
10560
10561         if (mac_stopped)
10562                 msleep(20);
10563 }
10564
10565 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10566 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10567                                         0x1848 + ((f) << 4))
10568 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10569 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10570 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10571
10572 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10573 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10574 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10575
10576 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10577 {
10578         /* UNDI marks its presence in DORQ -
10579          * it initializes CID offset for normal bell to 0x7
10580          */
10581         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10582             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10583                 return false;
10584
10585         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10586                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10587                 return true;
10588         }
10589
10590         return false;
10591 }
10592
10593 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10594 {
10595         u16 rcq, bd;
10596         u32 addr, tmp_reg;
10597
10598         if (BP_FUNC(bp) < 2)
10599                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10600         else
10601                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10602
10603         tmp_reg = REG_RD(bp, addr);
10604         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10605         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10606
10607         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10608         REG_WR(bp, addr, tmp_reg);
10609
10610         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10611                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10612 }
10613
10614 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10615 {
10616         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10617                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10618         if (!rc) {
10619                 BNX2X_ERR("MCP response failure, aborting\n");
10620                 return -EBUSY;
10621         }
10622
10623         return 0;
10624 }
10625
10626 static struct bnx2x_prev_path_list *
10627                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10628 {
10629         struct bnx2x_prev_path_list *tmp_list;
10630
10631         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10632                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10633                     bp->pdev->bus->number == tmp_list->bus &&
10634                     BP_PATH(bp) == tmp_list->path)
10635                         return tmp_list;
10636
10637         return NULL;
10638 }
10639
10640 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10641 {
10642         struct bnx2x_prev_path_list *tmp_list;
10643         int rc;
10644
10645         rc = down_interruptible(&bnx2x_prev_sem);
10646         if (rc) {
10647                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10648                 return rc;
10649         }
10650
10651         tmp_list = bnx2x_prev_path_get_entry(bp);
10652         if (tmp_list) {
10653                 tmp_list->aer = 1;
10654                 rc = 0;
10655         } else {
10656                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10657                           BP_PATH(bp));
10658         }
10659
10660         up(&bnx2x_prev_sem);
10661
10662         return rc;
10663 }
10664
10665 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10666 {
10667         struct bnx2x_prev_path_list *tmp_list;
10668         bool rc = false;
10669
10670         if (down_trylock(&bnx2x_prev_sem))
10671                 return false;
10672
10673         tmp_list = bnx2x_prev_path_get_entry(bp);
10674         if (tmp_list) {
10675                 if (tmp_list->aer) {
10676                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10677                            BP_PATH(bp));
10678                 } else {
10679                         rc = true;
10680                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10681                                        BP_PATH(bp));
10682                 }
10683         }
10684
10685         up(&bnx2x_prev_sem);
10686
10687         return rc;
10688 }
10689
10690 bool bnx2x_port_after_undi(struct bnx2x *bp)
10691 {
10692         struct bnx2x_prev_path_list *entry;
10693         bool val;
10694
10695         down(&bnx2x_prev_sem);
10696
10697         entry = bnx2x_prev_path_get_entry(bp);
10698         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10699
10700         up(&bnx2x_prev_sem);
10701
10702         return val;
10703 }
10704
10705 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10706 {
10707         struct bnx2x_prev_path_list *tmp_list;
10708         int rc;
10709
10710         rc = down_interruptible(&bnx2x_prev_sem);
10711         if (rc) {
10712                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10713                 return rc;
10714         }
10715
10716         /* Check whether the entry for this path already exists */
10717         tmp_list = bnx2x_prev_path_get_entry(bp);
10718         if (tmp_list) {
10719                 if (!tmp_list->aer) {
10720                         BNX2X_ERR("Re-Marking the path.\n");
10721                 } else {
10722                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10723                            BP_PATH(bp));
10724                         tmp_list->aer = 0;
10725                 }
10726                 up(&bnx2x_prev_sem);
10727                 return 0;
10728         }
10729         up(&bnx2x_prev_sem);
10730
10731         /* Create an entry for this path and add it */
10732         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10733         if (!tmp_list) {
10734                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10735                 return -ENOMEM;
10736         }
10737
10738         tmp_list->bus = bp->pdev->bus->number;
10739         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10740         tmp_list->path = BP_PATH(bp);
10741         tmp_list->aer = 0;
10742         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10743
10744         rc = down_interruptible(&bnx2x_prev_sem);
10745         if (rc) {
10746                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10747                 kfree(tmp_list);
10748         } else {
10749                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10750                    BP_PATH(bp));
10751                 list_add(&tmp_list->list, &bnx2x_prev_list);
10752                 up(&bnx2x_prev_sem);
10753         }
10754
10755         return rc;
10756 }
10757
10758 static int bnx2x_do_flr(struct bnx2x *bp)
10759 {
10760         struct pci_dev *dev = bp->pdev;
10761
10762         if (CHIP_IS_E1x(bp)) {
10763                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10764                 return -EINVAL;
10765         }
10766
10767         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10768         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10769                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10770                           bp->common.bc_ver);
10771                 return -EINVAL;
10772         }
10773
10774         if (!pci_wait_for_pending_transaction(dev))
10775                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10776
10777         BNX2X_DEV_INFO("Initiating FLR\n");
10778         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10779
10780         return 0;
10781 }
10782
10783 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10784 {
10785         int rc;
10786
10787         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10788
10789         /* Test if previous unload process was already finished for this path */
10790         if (bnx2x_prev_is_path_marked(bp))
10791                 return bnx2x_prev_mcp_done(bp);
10792
10793         BNX2X_DEV_INFO("Path is unmarked\n");
10794
10795         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10796         if (bnx2x_prev_is_after_undi(bp))
10797                 goto out;
10798
10799         /* If function has FLR capabilities, and existing FW version matches
10800          * the one required, then FLR will be sufficient to clean any residue
10801          * left by previous driver
10802          */
10803         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10804
10805         if (!rc) {
10806                 /* fw version is good */
10807                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10808                 rc = bnx2x_do_flr(bp);
10809         }
10810
10811         if (!rc) {
10812                 /* FLR was performed */
10813                 BNX2X_DEV_INFO("FLR successful\n");
10814                 return 0;
10815         }
10816
10817         BNX2X_DEV_INFO("Could not FLR\n");
10818
10819 out:
10820         /* Close the MCP request, return failure*/
10821         rc = bnx2x_prev_mcp_done(bp);
10822         if (!rc)
10823                 rc = BNX2X_PREV_WAIT_NEEDED;
10824
10825         return rc;
10826 }
10827
10828 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10829 {
10830         u32 reset_reg, tmp_reg = 0, rc;
10831         bool prev_undi = false;
10832         struct bnx2x_mac_vals mac_vals;
10833
10834         /* It is possible a previous function received 'common' answer,
10835          * but hasn't loaded yet, therefore creating a scenario of
10836          * multiple functions receiving 'common' on the same path.
10837          */
10838         BNX2X_DEV_INFO("Common unload Flow\n");
10839
10840         memset(&mac_vals, 0, sizeof(mac_vals));
10841
10842         if (bnx2x_prev_is_path_marked(bp))
10843                 return bnx2x_prev_mcp_done(bp);
10844
10845         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10846
10847         /* Reset should be performed after BRB is emptied */
10848         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10849                 u32 timer_count = 1000;
10850
10851                 /* Close the MAC Rx to prevent BRB from filling up */
10852                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10853
10854                 /* close LLH filters for both ports towards the BRB */
10855                 bnx2x_set_rx_filter(&bp->link_params, 0);
10856                 bp->link_params.port ^= 1;
10857                 bnx2x_set_rx_filter(&bp->link_params, 0);
10858                 bp->link_params.port ^= 1;
10859
10860                 /* Check if the UNDI driver was previously loaded */
10861                 if (bnx2x_prev_is_after_undi(bp)) {
10862                         prev_undi = true;
10863                         /* clear the UNDI indication */
10864                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10865                         /* clear possible idle check errors */
10866                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10867                 }
10868                 if (!CHIP_IS_E1x(bp))
10869                         /* block FW from writing to host */
10870                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10871
10872                 /* wait until BRB is empty */
10873                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10874                 while (timer_count) {
10875                         u32 prev_brb = tmp_reg;
10876
10877                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10878                         if (!tmp_reg)
10879                                 break;
10880
10881                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10882
10883                         /* reset timer as long as BRB actually gets emptied */
10884                         if (prev_brb > tmp_reg)
10885                                 timer_count = 1000;
10886                         else
10887                                 timer_count--;
10888
10889                         /* If UNDI resides in memory, manually increment it */
10890                         if (prev_undi)
10891                                 bnx2x_prev_unload_undi_inc(bp, 1);
10892
10893                         udelay(10);
10894                 }
10895
10896                 if (!timer_count)
10897                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10898         }
10899
10900         /* No packets are in the pipeline, path is ready for reset */
10901         bnx2x_reset_common(bp);
10902
10903         if (mac_vals.xmac_addr)
10904                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10905         if (mac_vals.umac_addr[0])
10906                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10907         if (mac_vals.umac_addr[1])
10908                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10909         if (mac_vals.emac_addr)
10910                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10911         if (mac_vals.bmac_addr) {
10912                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10913                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10914         }
10915
10916         rc = bnx2x_prev_mark_path(bp, prev_undi);
10917         if (rc) {
10918                 bnx2x_prev_mcp_done(bp);
10919                 return rc;
10920         }
10921
10922         return bnx2x_prev_mcp_done(bp);
10923 }
10924
10925 static int bnx2x_prev_unload(struct bnx2x *bp)
10926 {
10927         int time_counter = 10;
10928         u32 rc, fw, hw_lock_reg, hw_lock_val;
10929         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10930
10931         /* clear hw from errors which may have resulted from an interrupted
10932          * dmae transaction.
10933          */
10934         bnx2x_clean_pglue_errors(bp);
10935
10936         /* Release previously held locks */
10937         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10938                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10939                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10940
10941         hw_lock_val = REG_RD(bp, hw_lock_reg);
10942         if (hw_lock_val) {
10943                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10944                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10945                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10946                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10947                 }
10948
10949                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10950                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10951         } else
10952                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10953
10954         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10955                 BNX2X_DEV_INFO("Release previously held alr\n");
10956                 bnx2x_release_alr(bp);
10957         }
10958
10959         do {
10960                 int aer = 0;
10961                 /* Lock MCP using an unload request */
10962                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10963                 if (!fw) {
10964                         BNX2X_ERR("MCP response failure, aborting\n");
10965                         rc = -EBUSY;
10966                         break;
10967                 }
10968
10969                 rc = down_interruptible(&bnx2x_prev_sem);
10970                 if (rc) {
10971                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10972                                   rc);
10973                 } else {
10974                         /* If Path is marked by EEH, ignore unload status */
10975                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10976                                  bnx2x_prev_path_get_entry(bp)->aer);
10977                         up(&bnx2x_prev_sem);
10978                 }
10979
10980                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10981                         rc = bnx2x_prev_unload_common(bp);
10982                         break;
10983                 }
10984
10985                 /* non-common reply from MCP might require looping */
10986                 rc = bnx2x_prev_unload_uncommon(bp);
10987                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10988                         break;
10989
10990                 msleep(20);
10991         } while (--time_counter);
10992
10993         if (!time_counter || rc) {
10994                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10995                 rc = -EPROBE_DEFER;
10996         }
10997
10998         /* Mark function if its port was used to boot from SAN */
10999         if (bnx2x_port_after_undi(bp))
11000                 bp->link_params.feature_config_flags |=
11001                         FEATURE_CONFIG_BOOT_FROM_SAN;
11002
11003         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
11004
11005         return rc;
11006 }
11007
11008 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
11009 {
11010         u32 val, val2, val3, val4, id, boot_mode;
11011         u16 pmc;
11012
11013         /* Get the chip revision id and number. */
11014         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
11015         val = REG_RD(bp, MISC_REG_CHIP_NUM);
11016         id = ((val & 0xffff) << 16);
11017         val = REG_RD(bp, MISC_REG_CHIP_REV);
11018         id |= ((val & 0xf) << 12);
11019
11020         /* Metal is read from PCI regs, but we can't access >=0x400 from
11021          * the configuration space (so we need to reg_rd)
11022          */
11023         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
11024         id |= (((val >> 24) & 0xf) << 4);
11025         val = REG_RD(bp, MISC_REG_BOND_ID);
11026         id |= (val & 0xf);
11027         bp->common.chip_id = id;
11028
11029         /* force 57811 according to MISC register */
11030         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
11031                 if (CHIP_IS_57810(bp))
11032                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
11033                                 (bp->common.chip_id & 0x0000FFFF);
11034                 else if (CHIP_IS_57810_MF(bp))
11035                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
11036                                 (bp->common.chip_id & 0x0000FFFF);
11037                 bp->common.chip_id |= 0x1;
11038         }
11039
11040         /* Set doorbell size */
11041         bp->db_size = (1 << BNX2X_DB_SHIFT);
11042
11043         if (!CHIP_IS_E1x(bp)) {
11044                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
11045                 if ((val & 1) == 0)
11046                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
11047                 else
11048                         val = (val >> 1) & 1;
11049                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
11050                                                        "2_PORT_MODE");
11051                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
11052                                                  CHIP_2_PORT_MODE;
11053
11054                 if (CHIP_MODE_IS_4_PORT(bp))
11055                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
11056                 else
11057                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
11058         } else {
11059                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
11060                 bp->pfid = bp->pf_num;                  /* 0..7 */
11061         }
11062
11063         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
11064
11065         bp->link_params.chip_id = bp->common.chip_id;
11066         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
11067
11068         val = (REG_RD(bp, 0x2874) & 0x55);
11069         if ((bp->common.chip_id & 0x1) ||
11070             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
11071                 bp->flags |= ONE_PORT_FLAG;
11072                 BNX2X_DEV_INFO("single port device\n");
11073         }
11074
11075         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
11076         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
11077                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
11078         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11079                        bp->common.flash_size, bp->common.flash_size);
11080
11081         bnx2x_init_shmem(bp);
11082
11083         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11084                                         MISC_REG_GENERIC_CR_1 :
11085                                         MISC_REG_GENERIC_CR_0));
11086
11087         bp->link_params.shmem_base = bp->common.shmem_base;
11088         bp->link_params.shmem2_base = bp->common.shmem2_base;
11089         if (SHMEM2_RD(bp, size) >
11090             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11091                 bp->link_params.lfa_base =
11092                 REG_RD(bp, bp->common.shmem2_base +
11093                        (u32)offsetof(struct shmem2_region,
11094                                      lfa_host_addr[BP_PORT(bp)]));
11095         else
11096                 bp->link_params.lfa_base = 0;
11097         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
11098                        bp->common.shmem_base, bp->common.shmem2_base);
11099
11100         if (!bp->common.shmem_base) {
11101                 BNX2X_DEV_INFO("MCP not active\n");
11102                 bp->flags |= NO_MCP_FLAG;
11103                 return;
11104         }
11105
11106         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
11107         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
11108
11109         bp->link_params.hw_led_mode = ((bp->common.hw_config &
11110                                         SHARED_HW_CFG_LED_MODE_MASK) >>
11111                                        SHARED_HW_CFG_LED_MODE_SHIFT);
11112
11113         bp->link_params.feature_config_flags = 0;
11114         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11115         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11116                 bp->link_params.feature_config_flags |=
11117                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11118         else
11119                 bp->link_params.feature_config_flags &=
11120                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11121
11122         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11123         bp->common.bc_ver = val;
11124         BNX2X_DEV_INFO("bc_ver %X\n", val);
11125         if (val < BNX2X_BC_VER) {
11126                 /* for now only warn
11127                  * later we might need to enforce this */
11128                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11129                           BNX2X_BC_VER, val);
11130         }
11131         bp->link_params.feature_config_flags |=
11132                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11133                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11134
11135         bp->link_params.feature_config_flags |=
11136                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11137                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11138         bp->link_params.feature_config_flags |=
11139                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11140                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11141         bp->link_params.feature_config_flags |=
11142                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11143                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11144
11145         bp->link_params.feature_config_flags |=
11146                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11147                 FEATURE_CONFIG_MT_SUPPORT : 0;
11148
11149         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11150                         BC_SUPPORTS_PFC_STATS : 0;
11151
11152         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11153                         BC_SUPPORTS_FCOE_FEATURES : 0;
11154
11155         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11156                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11157
11158         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11159                         BC_SUPPORTS_RMMOD_CMD : 0;
11160
11161         boot_mode = SHMEM_RD(bp,
11162                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11163                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11164         switch (boot_mode) {
11165         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11166                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11167                 break;
11168         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11169                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11170                 break;
11171         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11172                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11173                 break;
11174         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11175                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11176                 break;
11177         }
11178
11179         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11180         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11181
11182         BNX2X_DEV_INFO("%sWoL capable\n",
11183                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
11184
11185         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11186         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11187         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11188         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11189
11190         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11191                  val, val2, val3, val4);
11192 }
11193
11194 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11195 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11196
11197 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11198 {
11199         int pfid = BP_FUNC(bp);
11200         int igu_sb_id;
11201         u32 val;
11202         u8 fid, igu_sb_cnt = 0;
11203
11204         bp->igu_base_sb = 0xff;
11205         if (CHIP_INT_MODE_IS_BC(bp)) {
11206                 int vn = BP_VN(bp);
11207                 igu_sb_cnt = bp->igu_sb_cnt;
11208                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11209                         FP_SB_MAX_E1x;
11210
11211                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
11212                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11213
11214                 return 0;
11215         }
11216
11217         /* IGU in normal mode - read CAM */
11218         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11219              igu_sb_id++) {
11220                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11221                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11222                         continue;
11223                 fid = IGU_FID(val);
11224                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11225                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11226                                 continue;
11227                         if (IGU_VEC(val) == 0)
11228                                 /* default status block */
11229                                 bp->igu_dsb_id = igu_sb_id;
11230                         else {
11231                                 if (bp->igu_base_sb == 0xff)
11232                                         bp->igu_base_sb = igu_sb_id;
11233                                 igu_sb_cnt++;
11234                         }
11235                 }
11236         }
11237
11238 #ifdef CONFIG_PCI_MSI
11239         /* Due to new PF resource allocation by MFW T7.4 and above, it's
11240          * optional that number of CAM entries will not be equal to the value
11241          * advertised in PCI.
11242          * Driver should use the minimal value of both as the actual status
11243          * block count
11244          */
11245         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11246 #endif
11247
11248         if (igu_sb_cnt == 0) {
11249                 BNX2X_ERR("CAM configuration error\n");
11250                 return -EINVAL;
11251         }
11252
11253         return 0;
11254 }
11255
11256 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11257 {
11258         int cfg_size = 0, idx, port = BP_PORT(bp);
11259
11260         /* Aggregation of supported attributes of all external phys */
11261         bp->port.supported[0] = 0;
11262         bp->port.supported[1] = 0;
11263         switch (bp->link_params.num_phys) {
11264         case 1:
11265                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11266                 cfg_size = 1;
11267                 break;
11268         case 2:
11269                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11270                 cfg_size = 1;
11271                 break;
11272         case 3:
11273                 if (bp->link_params.multi_phy_config &
11274                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11275                         bp->port.supported[1] =
11276                                 bp->link_params.phy[EXT_PHY1].supported;
11277                         bp->port.supported[0] =
11278                                 bp->link_params.phy[EXT_PHY2].supported;
11279                 } else {
11280                         bp->port.supported[0] =
11281                                 bp->link_params.phy[EXT_PHY1].supported;
11282                         bp->port.supported[1] =
11283                                 bp->link_params.phy[EXT_PHY2].supported;
11284                 }
11285                 cfg_size = 2;
11286                 break;
11287         }
11288
11289         if (!(bp->port.supported[0] || bp->port.supported[1])) {
11290                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11291                            SHMEM_RD(bp,
11292                            dev_info.port_hw_config[port].external_phy_config),
11293                            SHMEM_RD(bp,
11294                            dev_info.port_hw_config[port].external_phy_config2));
11295                         return;
11296         }
11297
11298         if (CHIP_IS_E3(bp))
11299                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11300         else {
11301                 switch (switch_cfg) {
11302                 case SWITCH_CFG_1G:
11303                         bp->port.phy_addr = REG_RD(
11304                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11305                         break;
11306                 case SWITCH_CFG_10G:
11307                         bp->port.phy_addr = REG_RD(
11308                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11309                         break;
11310                 default:
11311                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11312                                   bp->port.link_config[0]);
11313                         return;
11314                 }
11315         }
11316         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11317         /* mask what we support according to speed_cap_mask per configuration */
11318         for (idx = 0; idx < cfg_size; idx++) {
11319                 if (!(bp->link_params.speed_cap_mask[idx] &
11320                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11321                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11322
11323                 if (!(bp->link_params.speed_cap_mask[idx] &
11324                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11325                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11326
11327                 if (!(bp->link_params.speed_cap_mask[idx] &
11328                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11329                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11330
11331                 if (!(bp->link_params.speed_cap_mask[idx] &
11332                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11333                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11334
11335                 if (!(bp->link_params.speed_cap_mask[idx] &
11336                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11337                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11338                                                      SUPPORTED_1000baseT_Full);
11339
11340                 if (!(bp->link_params.speed_cap_mask[idx] &
11341                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11342                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11343
11344                 if (!(bp->link_params.speed_cap_mask[idx] &
11345                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11346                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11347
11348                 if (!(bp->link_params.speed_cap_mask[idx] &
11349                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11350                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11351         }
11352
11353         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11354                        bp->port.supported[1]);
11355 }
11356
11357 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11358 {
11359         u32 link_config, idx, cfg_size = 0;
11360         bp->port.advertising[0] = 0;
11361         bp->port.advertising[1] = 0;
11362         switch (bp->link_params.num_phys) {
11363         case 1:
11364         case 2:
11365                 cfg_size = 1;
11366                 break;
11367         case 3:
11368                 cfg_size = 2;
11369                 break;
11370         }
11371         for (idx = 0; idx < cfg_size; idx++) {
11372                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11373                 link_config = bp->port.link_config[idx];
11374                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11375                 case PORT_FEATURE_LINK_SPEED_AUTO:
11376                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11377                                 bp->link_params.req_line_speed[idx] =
11378                                         SPEED_AUTO_NEG;
11379                                 bp->port.advertising[idx] |=
11380                                         bp->port.supported[idx];
11381                                 if (bp->link_params.phy[EXT_PHY1].type ==
11382                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11383                                         bp->port.advertising[idx] |=
11384                                         (SUPPORTED_100baseT_Half |
11385                                          SUPPORTED_100baseT_Full);
11386                         } else {
11387                                 /* force 10G, no AN */
11388                                 bp->link_params.req_line_speed[idx] =
11389                                         SPEED_10000;
11390                                 bp->port.advertising[idx] |=
11391                                         (ADVERTISED_10000baseT_Full |
11392                                          ADVERTISED_FIBRE);
11393                                 continue;
11394                         }
11395                         break;
11396
11397                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11398                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11399                                 bp->link_params.req_line_speed[idx] =
11400                                         SPEED_10;
11401                                 bp->port.advertising[idx] |=
11402                                         (ADVERTISED_10baseT_Full |
11403                                          ADVERTISED_TP);
11404                         } else {
11405                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11406                                             link_config,
11407                                     bp->link_params.speed_cap_mask[idx]);
11408                                 return;
11409                         }
11410                         break;
11411
11412                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11413                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11414                                 bp->link_params.req_line_speed[idx] =
11415                                         SPEED_10;
11416                                 bp->link_params.req_duplex[idx] =
11417                                         DUPLEX_HALF;
11418                                 bp->port.advertising[idx] |=
11419                                         (ADVERTISED_10baseT_Half |
11420                                          ADVERTISED_TP);
11421                         } else {
11422                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11423                                             link_config,
11424                                           bp->link_params.speed_cap_mask[idx]);
11425                                 return;
11426                         }
11427                         break;
11428
11429                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11430                         if (bp->port.supported[idx] &
11431                             SUPPORTED_100baseT_Full) {
11432                                 bp->link_params.req_line_speed[idx] =
11433                                         SPEED_100;
11434                                 bp->port.advertising[idx] |=
11435                                         (ADVERTISED_100baseT_Full |
11436                                          ADVERTISED_TP);
11437                         } else {
11438                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11439                                             link_config,
11440                                           bp->link_params.speed_cap_mask[idx]);
11441                                 return;
11442                         }
11443                         break;
11444
11445                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11446                         if (bp->port.supported[idx] &
11447                             SUPPORTED_100baseT_Half) {
11448                                 bp->link_params.req_line_speed[idx] =
11449                                                                 SPEED_100;
11450                                 bp->link_params.req_duplex[idx] =
11451                                                                 DUPLEX_HALF;
11452                                 bp->port.advertising[idx] |=
11453                                         (ADVERTISED_100baseT_Half |
11454                                          ADVERTISED_TP);
11455                         } else {
11456                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11457                                     link_config,
11458                                     bp->link_params.speed_cap_mask[idx]);
11459                                 return;
11460                         }
11461                         break;
11462
11463                 case PORT_FEATURE_LINK_SPEED_1G:
11464                         if (bp->port.supported[idx] &
11465                             SUPPORTED_1000baseT_Full) {
11466                                 bp->link_params.req_line_speed[idx] =
11467                                         SPEED_1000;
11468                                 bp->port.advertising[idx] |=
11469                                         (ADVERTISED_1000baseT_Full |
11470                                          ADVERTISED_TP);
11471                         } else if (bp->port.supported[idx] &
11472                                    SUPPORTED_1000baseKX_Full) {
11473                                 bp->link_params.req_line_speed[idx] =
11474                                         SPEED_1000;
11475                                 bp->port.advertising[idx] |=
11476                                         ADVERTISED_1000baseKX_Full;
11477                         } else {
11478                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11479                                     link_config,
11480                                     bp->link_params.speed_cap_mask[idx]);
11481                                 return;
11482                         }
11483                         break;
11484
11485                 case PORT_FEATURE_LINK_SPEED_2_5G:
11486                         if (bp->port.supported[idx] &
11487                             SUPPORTED_2500baseX_Full) {
11488                                 bp->link_params.req_line_speed[idx] =
11489                                         SPEED_2500;
11490                                 bp->port.advertising[idx] |=
11491                                         (ADVERTISED_2500baseX_Full |
11492                                                 ADVERTISED_TP);
11493                         } else {
11494                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11495                                     link_config,
11496                                     bp->link_params.speed_cap_mask[idx]);
11497                                 return;
11498                         }
11499                         break;
11500
11501                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11502                         if (bp->port.supported[idx] &
11503                             SUPPORTED_10000baseT_Full) {
11504                                 bp->link_params.req_line_speed[idx] =
11505                                         SPEED_10000;
11506                                 bp->port.advertising[idx] |=
11507                                         (ADVERTISED_10000baseT_Full |
11508                                                 ADVERTISED_FIBRE);
11509                         } else if (bp->port.supported[idx] &
11510                                    SUPPORTED_10000baseKR_Full) {
11511                                 bp->link_params.req_line_speed[idx] =
11512                                         SPEED_10000;
11513                                 bp->port.advertising[idx] |=
11514                                         (ADVERTISED_10000baseKR_Full |
11515                                                 ADVERTISED_FIBRE);
11516                         } else {
11517                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11518                                     link_config,
11519                                     bp->link_params.speed_cap_mask[idx]);
11520                                 return;
11521                         }
11522                         break;
11523                 case PORT_FEATURE_LINK_SPEED_20G:
11524                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11525
11526                         break;
11527                 default:
11528                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11529                                   link_config);
11530                                 bp->link_params.req_line_speed[idx] =
11531                                                         SPEED_AUTO_NEG;
11532                                 bp->port.advertising[idx] =
11533                                                 bp->port.supported[idx];
11534                         break;
11535                 }
11536
11537                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11538                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11539                 if (bp->link_params.req_flow_ctrl[idx] ==
11540                     BNX2X_FLOW_CTRL_AUTO) {
11541                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11542                                 bp->link_params.req_flow_ctrl[idx] =
11543                                                         BNX2X_FLOW_CTRL_NONE;
11544                         else
11545                                 bnx2x_set_requested_fc(bp);
11546                 }
11547
11548                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11549                                bp->link_params.req_line_speed[idx],
11550                                bp->link_params.req_duplex[idx],
11551                                bp->link_params.req_flow_ctrl[idx],
11552                                bp->port.advertising[idx]);
11553         }
11554 }
11555
11556 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11557 {
11558         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11559         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11560         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11561         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11562 }
11563
11564 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11565 {
11566         int port = BP_PORT(bp);
11567         u32 config;
11568         u32 ext_phy_type, ext_phy_config, eee_mode;
11569
11570         bp->link_params.bp = bp;
11571         bp->link_params.port = port;
11572
11573         bp->link_params.lane_config =
11574                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11575
11576         bp->link_params.speed_cap_mask[0] =
11577                 SHMEM_RD(bp,
11578                          dev_info.port_hw_config[port].speed_capability_mask) &
11579                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11580         bp->link_params.speed_cap_mask[1] =
11581                 SHMEM_RD(bp,
11582                          dev_info.port_hw_config[port].speed_capability_mask2) &
11583                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11584         bp->port.link_config[0] =
11585                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11586
11587         bp->port.link_config[1] =
11588                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11589
11590         bp->link_params.multi_phy_config =
11591                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11592         /* If the device is capable of WoL, set the default state according
11593          * to the HW
11594          */
11595         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11596         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11597                    (config & PORT_FEATURE_WOL_ENABLED));
11598
11599         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11600             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11601                 bp->flags |= NO_ISCSI_FLAG;
11602         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11603             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11604                 bp->flags |= NO_FCOE_FLAG;
11605
11606         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11607                        bp->link_params.lane_config,
11608                        bp->link_params.speed_cap_mask[0],
11609                        bp->port.link_config[0]);
11610
11611         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11612                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11613         bnx2x_phy_probe(&bp->link_params);
11614         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11615
11616         bnx2x_link_settings_requested(bp);
11617
11618         /*
11619          * If connected directly, work with the internal PHY, otherwise, work
11620          * with the external PHY
11621          */
11622         ext_phy_config =
11623                 SHMEM_RD(bp,
11624                          dev_info.port_hw_config[port].external_phy_config);
11625         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11626         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11627                 bp->mdio.prtad = bp->port.phy_addr;
11628
11629         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11630                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11631                 bp->mdio.prtad =
11632                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11633
11634         /* Configure link feature according to nvram value */
11635         eee_mode = (((SHMEM_RD(bp, dev_info.
11636                       port_feature_config[port].eee_power_mode)) &
11637                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11638                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11639         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11640                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11641                                            EEE_MODE_ENABLE_LPI |
11642                                            EEE_MODE_OUTPUT_TIME;
11643         } else {
11644                 bp->link_params.eee_mode = 0;
11645         }
11646 }
11647
11648 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11649 {
11650         u32 no_flags = NO_ISCSI_FLAG;
11651         int port = BP_PORT(bp);
11652         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11653                                 drv_lic_key[port].max_iscsi_conn);
11654
11655         if (!CNIC_SUPPORT(bp)) {
11656                 bp->flags |= no_flags;
11657                 return;
11658         }
11659
11660         /* Get the number of maximum allowed iSCSI connections */
11661         bp->cnic_eth_dev.max_iscsi_conn =
11662                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11663                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11664
11665         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11666                        bp->cnic_eth_dev.max_iscsi_conn);
11667
11668         /*
11669          * If maximum allowed number of connections is zero -
11670          * disable the feature.
11671          */
11672         if (!bp->cnic_eth_dev.max_iscsi_conn)
11673                 bp->flags |= no_flags;
11674 }
11675
11676 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11677 {
11678         /* Port info */
11679         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11680                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11681         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11682                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11683
11684         /* Node info */
11685         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11686                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11687         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11688                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11689 }
11690
11691 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11692 {
11693         u8 count = 0;
11694
11695         if (IS_MF(bp)) {
11696                 u8 fid;
11697
11698                 /* iterate over absolute function ids for this path: */
11699                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11700                         if (IS_MF_SD(bp)) {
11701                                 u32 cfg = MF_CFG_RD(bp,
11702                                                     func_mf_config[fid].config);
11703
11704                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11705                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11706                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11707                                         count++;
11708                         } else {
11709                                 u32 cfg = MF_CFG_RD(bp,
11710                                                     func_ext_config[fid].
11711                                                                       func_cfg);
11712
11713                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11714                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11715                                         count++;
11716                         }
11717                 }
11718         } else { /* SF */
11719                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11720
11721                 for (port = 0; port < port_cnt; port++) {
11722                         u32 lic = SHMEM_RD(bp,
11723                                            drv_lic_key[port].max_fcoe_conn) ^
11724                                   FW_ENCODE_32BIT_PATTERN;
11725                         if (lic)
11726                                 count++;
11727                 }
11728         }
11729
11730         return count;
11731 }
11732
11733 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11734 {
11735         int port = BP_PORT(bp);
11736         int func = BP_ABS_FUNC(bp);
11737         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11738                                 drv_lic_key[port].max_fcoe_conn);
11739         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11740
11741         if (!CNIC_SUPPORT(bp)) {
11742                 bp->flags |= NO_FCOE_FLAG;
11743                 return;
11744         }
11745
11746         /* Get the number of maximum allowed FCoE connections */
11747         bp->cnic_eth_dev.max_fcoe_conn =
11748                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11749                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11750
11751         /* Calculate the number of maximum allowed FCoE tasks */
11752         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11753
11754         /* check if FCoE resources must be shared between different functions */
11755         if (num_fcoe_func)
11756                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11757
11758         /* Read the WWN: */
11759         if (!IS_MF(bp)) {
11760                 /* Port info */
11761                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11762                         SHMEM_RD(bp,
11763                                  dev_info.port_hw_config[port].
11764                                  fcoe_wwn_port_name_upper);
11765                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11766                         SHMEM_RD(bp,
11767                                  dev_info.port_hw_config[port].
11768                                  fcoe_wwn_port_name_lower);
11769
11770                 /* Node info */
11771                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11772                         SHMEM_RD(bp,
11773                                  dev_info.port_hw_config[port].
11774                                  fcoe_wwn_node_name_upper);
11775                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11776                         SHMEM_RD(bp,
11777                                  dev_info.port_hw_config[port].
11778                                  fcoe_wwn_node_name_lower);
11779         } else if (!IS_MF_SD(bp)) {
11780                 /* Read the WWN info only if the FCoE feature is enabled for
11781                  * this function.
11782                  */
11783                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11784                         bnx2x_get_ext_wwn_info(bp, func);
11785         } else {
11786                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11787                         bnx2x_get_ext_wwn_info(bp, func);
11788         }
11789
11790         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11791
11792         /*
11793          * If maximum allowed number of connections is zero -
11794          * disable the feature.
11795          */
11796         if (!bp->cnic_eth_dev.max_fcoe_conn) {
11797                 bp->flags |= NO_FCOE_FLAG;
11798                 eth_zero_addr(bp->fip_mac);
11799         }
11800 }
11801
11802 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11803 {
11804         /*
11805          * iSCSI may be dynamically disabled but reading
11806          * info here we will decrease memory usage by driver
11807          * if the feature is disabled for good
11808          */
11809         bnx2x_get_iscsi_info(bp);
11810         bnx2x_get_fcoe_info(bp);
11811 }
11812
11813 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11814 {
11815         u32 val, val2;
11816         int func = BP_ABS_FUNC(bp);
11817         int port = BP_PORT(bp);
11818         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11819         u8 *fip_mac = bp->fip_mac;
11820
11821         if (IS_MF(bp)) {
11822                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11823                  * FCoE MAC then the appropriate feature should be disabled.
11824                  * In non SD mode features configuration comes from struct
11825                  * func_ext_config.
11826                  */
11827                 if (!IS_MF_SD(bp)) {
11828                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11829                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11830                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11831                                                  iscsi_mac_addr_upper);
11832                                 val = MF_CFG_RD(bp, func_ext_config[func].
11833                                                 iscsi_mac_addr_lower);
11834                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11835                                 BNX2X_DEV_INFO
11836                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11837                         } else {
11838                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11839                         }
11840
11841                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11842                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11843                                                  fcoe_mac_addr_upper);
11844                                 val = MF_CFG_RD(bp, func_ext_config[func].
11845                                                 fcoe_mac_addr_lower);
11846                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11847                                 BNX2X_DEV_INFO
11848                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11849                         } else {
11850                                 bp->flags |= NO_FCOE_FLAG;
11851                         }
11852
11853                         bp->mf_ext_config = cfg;
11854
11855                 } else { /* SD MODE */
11856                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11857                                 /* use primary mac as iscsi mac */
11858                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11859
11860                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11861                                 BNX2X_DEV_INFO
11862                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11863                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11864                                 /* use primary mac as fip mac */
11865                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11866                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11867                                 BNX2X_DEV_INFO
11868                                         ("Read FIP MAC: %pM\n", fip_mac);
11869                         }
11870                 }
11871
11872                 /* If this is a storage-only interface, use SAN mac as
11873                  * primary MAC. Notice that for SD this is already the case,
11874                  * as the SAN mac was copied from the primary MAC.
11875                  */
11876                 if (IS_MF_FCOE_AFEX(bp))
11877                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11878         } else {
11879                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11880                                 iscsi_mac_upper);
11881                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11882                                iscsi_mac_lower);
11883                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11884
11885                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11886                                 fcoe_fip_mac_upper);
11887                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11888                                fcoe_fip_mac_lower);
11889                 bnx2x_set_mac_buf(fip_mac, val, val2);
11890         }
11891
11892         /* Disable iSCSI OOO if MAC configuration is invalid. */
11893         if (!is_valid_ether_addr(iscsi_mac)) {
11894                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11895                 eth_zero_addr(iscsi_mac);
11896         }
11897
11898         /* Disable FCoE if MAC configuration is invalid. */
11899         if (!is_valid_ether_addr(fip_mac)) {
11900                 bp->flags |= NO_FCOE_FLAG;
11901                 eth_zero_addr(bp->fip_mac);
11902         }
11903 }
11904
11905 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11906 {
11907         u32 val, val2;
11908         int func = BP_ABS_FUNC(bp);
11909         int port = BP_PORT(bp);
11910
11911         /* Zero primary MAC configuration */
11912         eth_zero_addr(bp->dev->dev_addr);
11913
11914         if (BP_NOMCP(bp)) {
11915                 BNX2X_ERROR("warning: random MAC workaround active\n");
11916                 eth_hw_addr_random(bp->dev);
11917         } else if (IS_MF(bp)) {
11918                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11919                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11920                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11921                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11922                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11923
11924                 if (CNIC_SUPPORT(bp))
11925                         bnx2x_get_cnic_mac_hwinfo(bp);
11926         } else {
11927                 /* in SF read MACs from port configuration */
11928                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11929                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11930                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11931
11932                 if (CNIC_SUPPORT(bp))
11933                         bnx2x_get_cnic_mac_hwinfo(bp);
11934         }
11935
11936         if (!BP_NOMCP(bp)) {
11937                 /* Read physical port identifier from shmem */
11938                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11939                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11940                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11941                 bp->flags |= HAS_PHYS_PORT_ID;
11942         }
11943
11944         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11945
11946         if (!is_valid_ether_addr(bp->dev->dev_addr))
11947                 dev_err(&bp->pdev->dev,
11948                         "bad Ethernet MAC address configuration: %pM\n"
11949                         "change it manually before bringing up the appropriate network interface\n",
11950                         bp->dev->dev_addr);
11951 }
11952
11953 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11954 {
11955         int tmp;
11956         u32 cfg;
11957
11958         if (IS_VF(bp))
11959                 return false;
11960
11961         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11962                 /* Take function: tmp = func */
11963                 tmp = BP_ABS_FUNC(bp);
11964                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11965                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11966         } else {
11967                 /* Take port: tmp = port */
11968                 tmp = BP_PORT(bp);
11969                 cfg = SHMEM_RD(bp,
11970                                dev_info.port_hw_config[tmp].generic_features);
11971                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11972         }
11973         return cfg;
11974 }
11975
11976 static void validate_set_si_mode(struct bnx2x *bp)
11977 {
11978         u8 func = BP_ABS_FUNC(bp);
11979         u32 val;
11980
11981         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11982
11983         /* check for legal mac (upper bytes) */
11984         if (val != 0xffff) {
11985                 bp->mf_mode = MULTI_FUNCTION_SI;
11986                 bp->mf_config[BP_VN(bp)] =
11987                         MF_CFG_RD(bp, func_mf_config[func].config);
11988         } else
11989                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11990 }
11991
11992 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11993 {
11994         int /*abs*/func = BP_ABS_FUNC(bp);
11995         int vn, mfw_vn;
11996         u32 val = 0, val2 = 0;
11997         int rc = 0;
11998
11999         /* Validate that chip access is feasible */
12000         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
12001                 dev_err(&bp->pdev->dev,
12002                         "Chip read returns all Fs. Preventing probe from continuing\n");
12003                 return -EINVAL;
12004         }
12005
12006         bnx2x_get_common_hwinfo(bp);
12007
12008         /*
12009          * initialize IGU parameters
12010          */
12011         if (CHIP_IS_E1x(bp)) {
12012                 bp->common.int_block = INT_BLOCK_HC;
12013
12014                 bp->igu_dsb_id = DEF_SB_IGU_ID;
12015                 bp->igu_base_sb = 0;
12016         } else {
12017                 bp->common.int_block = INT_BLOCK_IGU;
12018
12019                 /* do not allow device reset during IGU info processing */
12020                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12021
12022                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
12023
12024                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12025                         int tout = 5000;
12026
12027                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
12028
12029                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
12030                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
12031                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
12032
12033                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12034                                 tout--;
12035                                 usleep_range(1000, 2000);
12036                         }
12037
12038                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12039                                 dev_err(&bp->pdev->dev,
12040                                         "FORCING Normal Mode failed!!!\n");
12041                                 bnx2x_release_hw_lock(bp,
12042                                                       HW_LOCK_RESOURCE_RESET);
12043                                 return -EPERM;
12044                         }
12045                 }
12046
12047                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12048                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
12049                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
12050                 } else
12051                         BNX2X_DEV_INFO("IGU Normal Mode\n");
12052
12053                 rc = bnx2x_get_igu_cam_info(bp);
12054                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12055                 if (rc)
12056                         return rc;
12057         }
12058
12059         /*
12060          * set base FW non-default (fast path) status block id, this value is
12061          * used to initialize the fw_sb_id saved on the fp/queue structure to
12062          * determine the id used by the FW.
12063          */
12064         if (CHIP_IS_E1x(bp))
12065                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
12066         else /*
12067               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
12068               * the same queue are indicated on the same IGU SB). So we prefer
12069               * FW and IGU SBs to be the same value.
12070               */
12071                 bp->base_fw_ndsb = bp->igu_base_sb;
12072
12073         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
12074                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
12075                        bp->igu_sb_cnt, bp->base_fw_ndsb);
12076
12077         /*
12078          * Initialize MF configuration
12079          */
12080
12081         bp->mf_ov = 0;
12082         bp->mf_mode = 0;
12083         bp->mf_sub_mode = 0;
12084         vn = BP_VN(bp);
12085         mfw_vn = BP_FW_MB_IDX(bp);
12086
12087         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
12088                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12089                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
12090                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12091
12092                 if (SHMEM2_HAS(bp, mf_cfg_addr))
12093                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12094                 else
12095                         bp->common.mf_cfg_base = bp->common.shmem_base +
12096                                 offsetof(struct shmem_region, func_mb) +
12097                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
12098                 /*
12099                  * get mf configuration:
12100                  * 1. Existence of MF configuration
12101                  * 2. MAC address must be legal (check only upper bytes)
12102                  *    for  Switch-Independent mode;
12103                  *    OVLAN must be legal for Switch-Dependent mode
12104                  * 3. SF_MODE configures specific MF mode
12105                  */
12106                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12107                         /* get mf configuration */
12108                         val = SHMEM_RD(bp,
12109                                        dev_info.shared_feature_config.config);
12110                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12111
12112                         switch (val) {
12113                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
12114                                 validate_set_si_mode(bp);
12115                                 break;
12116                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12117                                 if ((!CHIP_IS_E1x(bp)) &&
12118                                     (MF_CFG_RD(bp, func_mf_config[func].
12119                                                mac_upper) != 0xffff) &&
12120                                     (SHMEM2_HAS(bp,
12121                                                 afex_driver_support))) {
12122                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
12123                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12124                                                 func_mf_config[func].config);
12125                                 } else {
12126                                         BNX2X_DEV_INFO("can not configure afex mode\n");
12127                                 }
12128                                 break;
12129                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12130                                 /* get OV configuration */
12131                                 val = MF_CFG_RD(bp,
12132                                         func_mf_config[FUNC_0].e1hov_tag);
12133                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12134
12135                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12136                                         bp->mf_mode = MULTI_FUNCTION_SD;
12137                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12138                                                 func_mf_config[func].config);
12139                                 } else
12140                                         BNX2X_DEV_INFO("illegal OV for SD\n");
12141                                 break;
12142                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12143                                 bp->mf_mode = MULTI_FUNCTION_SD;
12144                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
12145                                 bp->mf_config[vn] =
12146                                         MF_CFG_RD(bp,
12147                                                   func_mf_config[func].config);
12148
12149                                 if (SHMEM2_HAS(bp, mtu_size)) {
12150                                         int mtu_idx = BP_FW_MB_IDX(bp);
12151                                         u16 mtu_size;
12152                                         u32 mtu;
12153
12154                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12155                                         mtu_size = (u16)mtu;
12156                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12157                                            mtu_size, mtu);
12158
12159                                         /* if valid: update device mtu */
12160                                         if (((mtu_size + ETH_HLEN) >=
12161                                              ETH_MIN_PACKET_SIZE) &&
12162                                             (mtu_size <=
12163                                              ETH_MAX_JUMBO_PACKET_SIZE))
12164                                                 bp->dev->mtu = mtu_size;
12165                                 }
12166                                 break;
12167                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12168                                 bp->mf_mode = MULTI_FUNCTION_SD;
12169                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12170                                 bp->mf_config[vn] =
12171                                         MF_CFG_RD(bp,
12172                                                   func_mf_config[func].config);
12173                                 break;
12174                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12175                                 bp->mf_config[vn] = 0;
12176                                 break;
12177                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12178                                 val2 = SHMEM_RD(bp,
12179                                         dev_info.shared_hw_config.config_3);
12180                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12181                                 switch (val2) {
12182                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12183                                         validate_set_si_mode(bp);
12184                                         bp->mf_sub_mode =
12185                                                         SUB_MF_MODE_NPAR1_DOT_5;
12186                                         break;
12187                                 default:
12188                                         /* Unknown configuration */
12189                                         bp->mf_config[vn] = 0;
12190                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12191                                                        val);
12192                                 }
12193                                 break;
12194                         default:
12195                                 /* Unknown configuration: reset mf_config */
12196                                 bp->mf_config[vn] = 0;
12197                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12198                         }
12199                 }
12200
12201                 BNX2X_DEV_INFO("%s function mode\n",
12202                                IS_MF(bp) ? "multi" : "single");
12203
12204                 switch (bp->mf_mode) {
12205                 case MULTI_FUNCTION_SD:
12206                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12207                               FUNC_MF_CFG_E1HOV_TAG_MASK;
12208                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12209                                 bp->mf_ov = val;
12210                                 bp->path_has_ovlan = true;
12211
12212                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12213                                                func, bp->mf_ov, bp->mf_ov);
12214                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12215                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12216                                 dev_err(&bp->pdev->dev,
12217                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12218                                         func);
12219                                 bp->path_has_ovlan = true;
12220                         } else {
12221                                 dev_err(&bp->pdev->dev,
12222                                         "No valid MF OV for func %d, aborting\n",
12223                                         func);
12224                                 return -EPERM;
12225                         }
12226                         break;
12227                 case MULTI_FUNCTION_AFEX:
12228                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12229                         break;
12230                 case MULTI_FUNCTION_SI:
12231                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12232                                        func);
12233                         break;
12234                 default:
12235                         if (vn) {
12236                                 dev_err(&bp->pdev->dev,
12237                                         "VN %d is in a single function mode, aborting\n",
12238                                         vn);
12239                                 return -EPERM;
12240                         }
12241                         break;
12242                 }
12243
12244                 /* check if other port on the path needs ovlan:
12245                  * Since MF configuration is shared between ports
12246                  * Possible mixed modes are only
12247                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12248                  */
12249                 if (CHIP_MODE_IS_4_PORT(bp) &&
12250                     !bp->path_has_ovlan &&
12251                     !IS_MF(bp) &&
12252                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12253                         u8 other_port = !BP_PORT(bp);
12254                         u8 other_func = BP_PATH(bp) + 2*other_port;
12255                         val = MF_CFG_RD(bp,
12256                                         func_mf_config[other_func].e1hov_tag);
12257                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12258                                 bp->path_has_ovlan = true;
12259                 }
12260         }
12261
12262         /* adjust igu_sb_cnt to MF for E1H */
12263         if (CHIP_IS_E1H(bp) && IS_MF(bp))
12264                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12265
12266         /* port info */
12267         bnx2x_get_port_hwinfo(bp);
12268
12269         /* Get MAC addresses */
12270         bnx2x_get_mac_hwinfo(bp);
12271
12272         bnx2x_get_cnic_info(bp);
12273
12274         return rc;
12275 }
12276
12277 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12278 {
12279         int cnt, i, block_end, rodi;
12280         char vpd_start[BNX2X_VPD_LEN+1];
12281         char str_id_reg[VENDOR_ID_LEN+1];
12282         char str_id_cap[VENDOR_ID_LEN+1];
12283         char *vpd_data;
12284         char *vpd_extended_data = NULL;
12285         u8 len;
12286
12287         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12288         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12289
12290         if (cnt < BNX2X_VPD_LEN)
12291                 goto out_not_found;
12292
12293         /* VPD RO tag should be first tag after identifier string, hence
12294          * we should be able to find it in first BNX2X_VPD_LEN chars
12295          */
12296         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12297                              PCI_VPD_LRDT_RO_DATA);
12298         if (i < 0)
12299                 goto out_not_found;
12300
12301         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12302                     pci_vpd_lrdt_size(&vpd_start[i]);
12303
12304         i += PCI_VPD_LRDT_TAG_SIZE;
12305
12306         if (block_end > BNX2X_VPD_LEN) {
12307                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12308                 if (vpd_extended_data  == NULL)
12309                         goto out_not_found;
12310
12311                 /* read rest of vpd image into vpd_extended_data */
12312                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12313                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12314                                    block_end - BNX2X_VPD_LEN,
12315                                    vpd_extended_data + BNX2X_VPD_LEN);
12316                 if (cnt < (block_end - BNX2X_VPD_LEN))
12317                         goto out_not_found;
12318                 vpd_data = vpd_extended_data;
12319         } else
12320                 vpd_data = vpd_start;
12321
12322         /* now vpd_data holds full vpd content in both cases */
12323
12324         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12325                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12326         if (rodi < 0)
12327                 goto out_not_found;
12328
12329         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12330
12331         if (len != VENDOR_ID_LEN)
12332                 goto out_not_found;
12333
12334         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12335
12336         /* vendor specific info */
12337         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12338         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12339         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12340             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12341
12342                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12343                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12344                 if (rodi >= 0) {
12345                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12346
12347                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12348
12349                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12350                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12351                                 bp->fw_ver[len] = ' ';
12352                         }
12353                 }
12354                 kfree(vpd_extended_data);
12355                 return;
12356         }
12357 out_not_found:
12358         kfree(vpd_extended_data);
12359         return;
12360 }
12361
12362 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12363 {
12364         u32 flags = 0;
12365
12366         if (CHIP_REV_IS_FPGA(bp))
12367                 SET_FLAGS(flags, MODE_FPGA);
12368         else if (CHIP_REV_IS_EMUL(bp))
12369                 SET_FLAGS(flags, MODE_EMUL);
12370         else
12371                 SET_FLAGS(flags, MODE_ASIC);
12372
12373         if (CHIP_MODE_IS_4_PORT(bp))
12374                 SET_FLAGS(flags, MODE_PORT4);
12375         else
12376                 SET_FLAGS(flags, MODE_PORT2);
12377
12378         if (CHIP_IS_E2(bp))
12379                 SET_FLAGS(flags, MODE_E2);
12380         else if (CHIP_IS_E3(bp)) {
12381                 SET_FLAGS(flags, MODE_E3);
12382                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12383                         SET_FLAGS(flags, MODE_E3_A0);
12384                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12385                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12386         }
12387
12388         if (IS_MF(bp)) {
12389                 SET_FLAGS(flags, MODE_MF);
12390                 switch (bp->mf_mode) {
12391                 case MULTI_FUNCTION_SD:
12392                         SET_FLAGS(flags, MODE_MF_SD);
12393                         break;
12394                 case MULTI_FUNCTION_SI:
12395                         SET_FLAGS(flags, MODE_MF_SI);
12396                         break;
12397                 case MULTI_FUNCTION_AFEX:
12398                         SET_FLAGS(flags, MODE_MF_AFEX);
12399                         break;
12400                 }
12401         } else
12402                 SET_FLAGS(flags, MODE_SF);
12403
12404 #if defined(__LITTLE_ENDIAN)
12405         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12406 #else /*(__BIG_ENDIAN)*/
12407         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12408 #endif
12409         INIT_MODE_FLAGS(bp) = flags;
12410 }
12411
12412 static int bnx2x_init_bp(struct bnx2x *bp)
12413 {
12414         int func;
12415         int rc;
12416
12417         mutex_init(&bp->port.phy_mutex);
12418         mutex_init(&bp->fw_mb_mutex);
12419         mutex_init(&bp->drv_info_mutex);
12420         sema_init(&bp->stats_lock, 1);
12421         bp->drv_info_mng_owner = false;
12422         INIT_LIST_HEAD(&bp->vlan_reg);
12423
12424         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12425         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12426         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12427         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12428         if (IS_PF(bp)) {
12429                 rc = bnx2x_get_hwinfo(bp);
12430                 if (rc)
12431                         return rc;
12432         } else {
12433                 eth_zero_addr(bp->dev->dev_addr);
12434         }
12435
12436         bnx2x_set_modes_bitmap(bp);
12437
12438         rc = bnx2x_alloc_mem_bp(bp);
12439         if (rc)
12440                 return rc;
12441
12442         bnx2x_read_fwinfo(bp);
12443
12444         func = BP_FUNC(bp);
12445
12446         /* need to reset chip if undi was active */
12447         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12448                 /* init fw_seq */
12449                 bp->fw_seq =
12450                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12451                                                         DRV_MSG_SEQ_NUMBER_MASK;
12452                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12453
12454                 rc = bnx2x_prev_unload(bp);
12455                 if (rc) {
12456                         bnx2x_free_mem_bp(bp);
12457                         return rc;
12458                 }
12459         }
12460
12461         if (CHIP_REV_IS_FPGA(bp))
12462                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12463
12464         if (BP_NOMCP(bp) && (func == 0))
12465                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12466
12467         bp->disable_tpa = disable_tpa;
12468         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12469         /* Reduce memory usage in kdump environment by disabling TPA */
12470         bp->disable_tpa |= is_kdump_kernel();
12471
12472         /* Set TPA flags */
12473         if (bp->disable_tpa) {
12474                 bp->dev->hw_features &= ~NETIF_F_LRO;
12475                 bp->dev->features &= ~NETIF_F_LRO;
12476         }
12477
12478         if (CHIP_IS_E1(bp))
12479                 bp->dropless_fc = 0;
12480         else
12481                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12482
12483         bp->mrrs = mrrs;
12484
12485         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12486         if (IS_VF(bp))
12487                 bp->rx_ring_size = MAX_RX_AVAIL;
12488
12489         /* make sure that the numbers are in the right granularity */
12490         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12491         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12492
12493         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12494
12495         init_timer(&bp->timer);
12496         bp->timer.expires = jiffies + bp->current_interval;
12497         bp->timer.data = (unsigned long) bp;
12498         bp->timer.function = bnx2x_timer;
12499
12500         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12501             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12502             SHMEM2_HAS(bp, dcbx_en) &&
12503             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12504             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12505             SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
12506                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12507                 bnx2x_dcbx_init_params(bp);
12508         } else {
12509                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12510         }
12511
12512         if (CHIP_IS_E1x(bp))
12513                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12514         else
12515                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12516
12517         /* multiple tx priority */
12518         if (IS_VF(bp))
12519                 bp->max_cos = 1;
12520         else if (CHIP_IS_E1x(bp))
12521                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12522         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12523                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12524         else if (CHIP_IS_E3B0(bp))
12525                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12526         else
12527                 BNX2X_ERR("unknown chip %x revision %x\n",
12528                           CHIP_NUM(bp), CHIP_REV(bp));
12529         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12530
12531         /* We need at least one default status block for slow-path events,
12532          * second status block for the L2 queue, and a third status block for
12533          * CNIC if supported.
12534          */
12535         if (IS_VF(bp))
12536                 bp->min_msix_vec_cnt = 1;
12537         else if (CNIC_SUPPORT(bp))
12538                 bp->min_msix_vec_cnt = 3;
12539         else /* PF w/o cnic */
12540                 bp->min_msix_vec_cnt = 2;
12541         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12542
12543         bp->dump_preset_idx = 1;
12544
12545         if (CHIP_IS_E3B0(bp))
12546                 bp->flags |= PTP_SUPPORTED;
12547
12548         return rc;
12549 }
12550
12551 /****************************************************************************
12552 * General service functions
12553 ****************************************************************************/
12554
12555 /*
12556  * net_device service functions
12557  */
12558
12559 /* called with rtnl_lock */
12560 static int bnx2x_open(struct net_device *dev)
12561 {
12562         struct bnx2x *bp = netdev_priv(dev);
12563         int rc;
12564
12565         bp->stats_init = true;
12566
12567         netif_carrier_off(dev);
12568
12569         bnx2x_set_power_state(bp, PCI_D0);
12570
12571         /* If parity had happen during the unload, then attentions
12572          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12573          * want the first function loaded on the current engine to
12574          * complete the recovery.
12575          * Parity recovery is only relevant for PF driver.
12576          */
12577         if (IS_PF(bp)) {
12578                 int other_engine = BP_PATH(bp) ? 0 : 1;
12579                 bool other_load_status, load_status;
12580                 bool global = false;
12581
12582                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12583                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12584                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12585                     bnx2x_chk_parity_attn(bp, &global, true)) {
12586                         do {
12587                                 /* If there are attentions and they are in a
12588                                  * global blocks, set the GLOBAL_RESET bit
12589                                  * regardless whether it will be this function
12590                                  * that will complete the recovery or not.
12591                                  */
12592                                 if (global)
12593                                         bnx2x_set_reset_global(bp);
12594
12595                                 /* Only the first function on the current
12596                                  * engine should try to recover in open. In case
12597                                  * of attentions in global blocks only the first
12598                                  * in the chip should try to recover.
12599                                  */
12600                                 if ((!load_status &&
12601                                      (!global || !other_load_status)) &&
12602                                       bnx2x_trylock_leader_lock(bp) &&
12603                                       !bnx2x_leader_reset(bp)) {
12604                                         netdev_info(bp->dev,
12605                                                     "Recovered in open\n");
12606                                         break;
12607                                 }
12608
12609                                 /* recovery has failed... */
12610                                 bnx2x_set_power_state(bp, PCI_D3hot);
12611                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12612
12613                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12614                                           "If you still see this message after a few retries then power cycle is required.\n");
12615
12616                                 return -EAGAIN;
12617                         } while (0);
12618                 }
12619         }
12620
12621         bp->recovery_state = BNX2X_RECOVERY_DONE;
12622         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12623         if (rc)
12624                 return rc;
12625
12626         if (IS_PF(bp))
12627                 udp_tunnel_get_rx_info(dev);
12628
12629         return 0;
12630 }
12631
12632 /* called with rtnl_lock */
12633 static int bnx2x_close(struct net_device *dev)
12634 {
12635         struct bnx2x *bp = netdev_priv(dev);
12636
12637         /* Unload the driver, release IRQs */
12638         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12639
12640         return 0;
12641 }
12642
12643 struct bnx2x_mcast_list_elem_group
12644 {
12645         struct list_head mcast_group_link;
12646         struct bnx2x_mcast_list_elem mcast_elems[];
12647 };
12648
12649 #define MCAST_ELEMS_PER_PG \
12650         ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12651         sizeof(struct bnx2x_mcast_list_elem))
12652
12653 static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list)
12654 {
12655         struct bnx2x_mcast_list_elem_group *current_mcast_group;
12656
12657         while (!list_empty(mcast_group_list)) {
12658                 current_mcast_group = list_first_entry(mcast_group_list,
12659                                       struct bnx2x_mcast_list_elem_group,
12660                                       mcast_group_link);
12661                 list_del(&current_mcast_group->mcast_group_link);
12662                 free_page((unsigned long)current_mcast_group);
12663         }
12664 }
12665
12666 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12667                                       struct bnx2x_mcast_ramrod_params *p,
12668                                       struct list_head *mcast_group_list)
12669 {
12670         struct bnx2x_mcast_list_elem *mc_mac;
12671         struct netdev_hw_addr *ha;
12672         struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL;
12673         int mc_count = netdev_mc_count(bp->dev);
12674         int offset = 0;
12675
12676         INIT_LIST_HEAD(&p->mcast_list);
12677         netdev_for_each_mc_addr(ha, bp->dev) {
12678                 if (!offset) {
12679                         current_mcast_group =
12680                                 (struct bnx2x_mcast_list_elem_group *)
12681                                 __get_free_page(GFP_ATOMIC);
12682                         if (!current_mcast_group) {
12683                                 bnx2x_free_mcast_macs_list(mcast_group_list);
12684                                 BNX2X_ERR("Failed to allocate mc MAC list\n");
12685                                 return -ENOMEM;
12686                         }
12687                         list_add(&current_mcast_group->mcast_group_link,
12688                                  mcast_group_list);
12689                 }
12690                 mc_mac = &current_mcast_group->mcast_elems[offset];
12691                 mc_mac->mac = bnx2x_mc_addr(ha);
12692                 list_add_tail(&mc_mac->link, &p->mcast_list);
12693                 offset++;
12694                 if (offset == MCAST_ELEMS_PER_PG)
12695                         offset = 0;
12696         }
12697         p->mcast_list_len = mc_count;
12698         return 0;
12699 }
12700
12701 /**
12702  * bnx2x_set_uc_list - configure a new unicast MACs list.
12703  *
12704  * @bp: driver handle
12705  *
12706  * We will use zero (0) as a MAC type for these MACs.
12707  */
12708 static int bnx2x_set_uc_list(struct bnx2x *bp)
12709 {
12710         int rc;
12711         struct net_device *dev = bp->dev;
12712         struct netdev_hw_addr *ha;
12713         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12714         unsigned long ramrod_flags = 0;
12715
12716         /* First schedule a cleanup up of old configuration */
12717         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12718         if (rc < 0) {
12719                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12720                 return rc;
12721         }
12722
12723         netdev_for_each_uc_addr(ha, dev) {
12724                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12725                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12726                 if (rc == -EEXIST) {
12727                         DP(BNX2X_MSG_SP,
12728                            "Failed to schedule ADD operations: %d\n", rc);
12729                         /* do not treat adding same MAC as error */
12730                         rc = 0;
12731
12732                 } else if (rc < 0) {
12733
12734                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12735                                   rc);
12736                         return rc;
12737                 }
12738         }
12739
12740         /* Execute the pending commands */
12741         __set_bit(RAMROD_CONT, &ramrod_flags);
12742         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12743                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12744 }
12745
12746 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
12747 {
12748         LIST_HEAD(mcast_group_list);
12749         struct net_device *dev = bp->dev;
12750         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12751         int rc = 0;
12752
12753         rparam.mcast_obj = &bp->mcast_obj;
12754
12755         /* first, clear all configured multicast MACs */
12756         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12757         if (rc < 0) {
12758                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12759                 return rc;
12760         }
12761
12762         /* then, configure a new MACs list */
12763         if (netdev_mc_count(dev)) {
12764                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12765                 if (rc)
12766                         return rc;
12767
12768                 /* Now add the new MACs */
12769                 rc = bnx2x_config_mcast(bp, &rparam,
12770                                         BNX2X_MCAST_CMD_ADD);
12771                 if (rc < 0)
12772                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12773                                   rc);
12774
12775                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12776         }
12777
12778         return rc;
12779 }
12780
12781 static int bnx2x_set_mc_list(struct bnx2x *bp)
12782 {
12783         LIST_HEAD(mcast_group_list);
12784         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12785         struct net_device *dev = bp->dev;
12786         int rc = 0;
12787
12788         /* On older adapters, we need to flush and re-add filters */
12789         if (CHIP_IS_E1x(bp))
12790                 return bnx2x_set_mc_list_e1x(bp);
12791
12792         rparam.mcast_obj = &bp->mcast_obj;
12793
12794         if (netdev_mc_count(dev)) {
12795                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12796                 if (rc)
12797                         return rc;
12798
12799                 /* Override the curently configured set of mc filters */
12800                 rc = bnx2x_config_mcast(bp, &rparam,
12801                                         BNX2X_MCAST_CMD_SET);
12802                 if (rc < 0)
12803                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12804                                   rc);
12805
12806                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12807         } else {
12808                 /* If no mc addresses are required, flush the configuration */
12809                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12810                 if (rc)
12811                         BNX2X_ERR("Failed to clear multicast configuration %d\n",
12812                                   rc);
12813         }
12814
12815         return rc;
12816 }
12817
12818 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12819 static void bnx2x_set_rx_mode(struct net_device *dev)
12820 {
12821         struct bnx2x *bp = netdev_priv(dev);
12822
12823         if (bp->state != BNX2X_STATE_OPEN) {
12824                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12825                 return;
12826         } else {
12827                 /* Schedule an SP task to handle rest of change */
12828                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12829                                        NETIF_MSG_IFUP);
12830         }
12831 }
12832
12833 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12834 {
12835         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12836
12837         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12838
12839         netif_addr_lock_bh(bp->dev);
12840
12841         if (bp->dev->flags & IFF_PROMISC) {
12842                 rx_mode = BNX2X_RX_MODE_PROMISC;
12843         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12844                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12845                     CHIP_IS_E1(bp))) {
12846                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12847         } else {
12848                 if (IS_PF(bp)) {
12849                         /* some multicasts */
12850                         if (bnx2x_set_mc_list(bp) < 0)
12851                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12852
12853                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12854                         netif_addr_unlock_bh(bp->dev);
12855                         if (bnx2x_set_uc_list(bp) < 0)
12856                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12857                         netif_addr_lock_bh(bp->dev);
12858                 } else {
12859                         /* configuring mcast to a vf involves sleeping (when we
12860                          * wait for the pf's response).
12861                          */
12862                         bnx2x_schedule_sp_rtnl(bp,
12863                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12864                 }
12865         }
12866
12867         bp->rx_mode = rx_mode;
12868         /* handle ISCSI SD mode */
12869         if (IS_MF_ISCSI_ONLY(bp))
12870                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12871
12872         /* Schedule the rx_mode command */
12873         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12874                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12875                 netif_addr_unlock_bh(bp->dev);
12876                 return;
12877         }
12878
12879         if (IS_PF(bp)) {
12880                 bnx2x_set_storm_rx_mode(bp);
12881                 netif_addr_unlock_bh(bp->dev);
12882         } else {
12883                 /* VF will need to request the PF to make this change, and so
12884                  * the VF needs to release the bottom-half lock prior to the
12885                  * request (as it will likely require sleep on the VF side)
12886                  */
12887                 netif_addr_unlock_bh(bp->dev);
12888                 bnx2x_vfpf_storm_rx_mode(bp);
12889         }
12890 }
12891
12892 /* called with rtnl_lock */
12893 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12894                            int devad, u16 addr)
12895 {
12896         struct bnx2x *bp = netdev_priv(netdev);
12897         u16 value;
12898         int rc;
12899
12900         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12901            prtad, devad, addr);
12902
12903         /* The HW expects different devad if CL22 is used */
12904         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12905
12906         bnx2x_acquire_phy_lock(bp);
12907         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12908         bnx2x_release_phy_lock(bp);
12909         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12910
12911         if (!rc)
12912                 rc = value;
12913         return rc;
12914 }
12915
12916 /* called with rtnl_lock */
12917 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12918                             u16 addr, u16 value)
12919 {
12920         struct bnx2x *bp = netdev_priv(netdev);
12921         int rc;
12922
12923         DP(NETIF_MSG_LINK,
12924            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12925            prtad, devad, addr, value);
12926
12927         /* The HW expects different devad if CL22 is used */
12928         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12929
12930         bnx2x_acquire_phy_lock(bp);
12931         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12932         bnx2x_release_phy_lock(bp);
12933         return rc;
12934 }
12935
12936 /* called with rtnl_lock */
12937 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12938 {
12939         struct bnx2x *bp = netdev_priv(dev);
12940         struct mii_ioctl_data *mdio = if_mii(ifr);
12941
12942         if (!netif_running(dev))
12943                 return -EAGAIN;
12944
12945         switch (cmd) {
12946         case SIOCSHWTSTAMP:
12947                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12948         default:
12949                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12950                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12951                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12952         }
12953 }
12954
12955 #ifdef CONFIG_NET_POLL_CONTROLLER
12956 static void poll_bnx2x(struct net_device *dev)
12957 {
12958         struct bnx2x *bp = netdev_priv(dev);
12959         int i;
12960
12961         for_each_eth_queue(bp, i) {
12962                 struct bnx2x_fastpath *fp = &bp->fp[i];
12963                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12964         }
12965 }
12966 #endif
12967
12968 static int bnx2x_validate_addr(struct net_device *dev)
12969 {
12970         struct bnx2x *bp = netdev_priv(dev);
12971
12972         /* query the bulletin board for mac address configured by the PF */
12973         if (IS_VF(bp))
12974                 bnx2x_sample_bulletin(bp);
12975
12976         if (!is_valid_ether_addr(dev->dev_addr)) {
12977                 BNX2X_ERR("Non-valid Ethernet address\n");
12978                 return -EADDRNOTAVAIL;
12979         }
12980         return 0;
12981 }
12982
12983 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12984                                   struct netdev_phys_item_id *ppid)
12985 {
12986         struct bnx2x *bp = netdev_priv(netdev);
12987
12988         if (!(bp->flags & HAS_PHYS_PORT_ID))
12989                 return -EOPNOTSUPP;
12990
12991         ppid->id_len = sizeof(bp->phys_port_id);
12992         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12993
12994         return 0;
12995 }
12996
12997 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12998                                               struct net_device *dev,
12999                                               netdev_features_t features)
13000 {
13001         /*
13002          * A skb with gso_size + header length > 9700 will cause a
13003          * firmware panic. Drop GSO support.
13004          *
13005          * Eventually the upper layer should not pass these packets down.
13006          *
13007          * For speed, if the gso_size is <= 9000, assume there will
13008          * not be 700 bytes of headers and pass it through. Only do a
13009          * full (slow) validation if the gso_size is > 9000.
13010          *
13011          * (Due to the way SKB_BY_FRAGS works this will also do a full
13012          * validation in that case.)
13013          */
13014         if (unlikely(skb_is_gso(skb) &&
13015                      (skb_shinfo(skb)->gso_size > 9000) &&
13016                      !skb_gso_validate_mac_len(skb, 9700)))
13017                 features &= ~NETIF_F_GSO_MASK;
13018
13019         features = vlan_features_check(skb, features);
13020         return vxlan_features_check(skb, features);
13021 }
13022
13023 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
13024 {
13025         int rc;
13026
13027         if (IS_PF(bp)) {
13028                 unsigned long ramrod_flags = 0;
13029
13030                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13031                 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
13032                                         add, &ramrod_flags);
13033         } else {
13034                 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
13035         }
13036
13037         return rc;
13038 }
13039
13040 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
13041 {
13042         struct bnx2x_vlan_entry *vlan;
13043         int rc = 0;
13044
13045         /* Configure all non-configured entries */
13046         list_for_each_entry(vlan, &bp->vlan_reg, link) {
13047                 if (vlan->hw)
13048                         continue;
13049
13050                 if (bp->vlan_cnt >= bp->vlan_credit)
13051                         return -ENOBUFS;
13052
13053                 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
13054                 if (rc) {
13055                         BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
13056                         return rc;
13057                 }
13058
13059                 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
13060                 vlan->hw = true;
13061                 bp->vlan_cnt++;
13062         }
13063
13064         return 0;
13065 }
13066
13067 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
13068 {
13069         bool need_accept_any_vlan;
13070
13071         need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
13072
13073         if (bp->accept_any_vlan != need_accept_any_vlan) {
13074                 bp->accept_any_vlan = need_accept_any_vlan;
13075                 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
13076                    bp->accept_any_vlan ? "raised" : "cleared");
13077                 if (set_rx_mode) {
13078                         if (IS_PF(bp))
13079                                 bnx2x_set_rx_mode_inner(bp);
13080                         else
13081                                 bnx2x_vfpf_storm_rx_mode(bp);
13082                 }
13083         }
13084 }
13085
13086 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
13087 {
13088         /* Don't set rx mode here. Our caller will do it. */
13089         bnx2x_vlan_configure(bp, false);
13090
13091         return 0;
13092 }
13093
13094 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
13095 {
13096         struct bnx2x *bp = netdev_priv(dev);
13097         struct bnx2x_vlan_entry *vlan;
13098
13099         DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
13100
13101         vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
13102         if (!vlan)
13103                 return -ENOMEM;
13104
13105         vlan->vid = vid;
13106         vlan->hw = false;
13107         list_add_tail(&vlan->link, &bp->vlan_reg);
13108
13109         if (netif_running(dev))
13110                 bnx2x_vlan_configure(bp, true);
13111
13112         return 0;
13113 }
13114
13115 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
13116 {
13117         struct bnx2x *bp = netdev_priv(dev);
13118         struct bnx2x_vlan_entry *vlan;
13119         bool found = false;
13120         int rc = 0;
13121
13122         DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
13123
13124         list_for_each_entry(vlan, &bp->vlan_reg, link)
13125                 if (vlan->vid == vid) {
13126                         found = true;
13127                         break;
13128                 }
13129
13130         if (!found) {
13131                 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13132                 return -EINVAL;
13133         }
13134
13135         if (netif_running(dev) && vlan->hw) {
13136                 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
13137                 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13138                 bp->vlan_cnt--;
13139         }
13140
13141         list_del(&vlan->link);
13142         kfree(vlan);
13143
13144         if (netif_running(dev))
13145                 bnx2x_vlan_configure(bp, true);
13146
13147         DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13148
13149         return rc;
13150 }
13151
13152 static const struct net_device_ops bnx2x_netdev_ops = {
13153         .ndo_open               = bnx2x_open,
13154         .ndo_stop               = bnx2x_close,
13155         .ndo_start_xmit         = bnx2x_start_xmit,
13156         .ndo_select_queue       = bnx2x_select_queue,
13157         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
13158         .ndo_set_mac_address    = bnx2x_change_mac_addr,
13159         .ndo_validate_addr      = bnx2x_validate_addr,
13160         .ndo_do_ioctl           = bnx2x_ioctl,
13161         .ndo_change_mtu         = bnx2x_change_mtu,
13162         .ndo_fix_features       = bnx2x_fix_features,
13163         .ndo_set_features       = bnx2x_set_features,
13164         .ndo_tx_timeout         = bnx2x_tx_timeout,
13165         .ndo_vlan_rx_add_vid    = bnx2x_vlan_rx_add_vid,
13166         .ndo_vlan_rx_kill_vid   = bnx2x_vlan_rx_kill_vid,
13167 #ifdef CONFIG_NET_POLL_CONTROLLER
13168         .ndo_poll_controller    = poll_bnx2x,
13169 #endif
13170         .ndo_setup_tc           = __bnx2x_setup_tc,
13171 #ifdef CONFIG_BNX2X_SRIOV
13172         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
13173         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
13174         .ndo_get_vf_config      = bnx2x_get_vf_config,
13175 #endif
13176 #ifdef NETDEV_FCOE_WWNN
13177         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
13178 #endif
13179
13180         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
13181         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
13182         .ndo_features_check     = bnx2x_features_check,
13183         .ndo_udp_tunnel_add     = bnx2x_udp_tunnel_add,
13184         .ndo_udp_tunnel_del     = bnx2x_udp_tunnel_del,
13185 };
13186
13187 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13188 {
13189         struct device *dev = &bp->pdev->dev;
13190
13191         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13192             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13193                 dev_err(dev, "System does not support DMA, aborting\n");
13194                 return -EIO;
13195         }
13196
13197         return 0;
13198 }
13199
13200 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13201 {
13202         if (bp->flags & AER_ENABLED) {
13203                 pci_disable_pcie_error_reporting(bp->pdev);
13204                 bp->flags &= ~AER_ENABLED;
13205         }
13206 }
13207
13208 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13209                           struct net_device *dev, unsigned long board_type)
13210 {
13211         int rc;
13212         u32 pci_cfg_dword;
13213         bool chip_is_e1x = (board_type == BCM57710 ||
13214                             board_type == BCM57711 ||
13215                             board_type == BCM57711E);
13216
13217         SET_NETDEV_DEV(dev, &pdev->dev);
13218
13219         bp->dev = dev;
13220         bp->pdev = pdev;
13221
13222         rc = pci_enable_device(pdev);
13223         if (rc) {
13224                 dev_err(&bp->pdev->dev,
13225                         "Cannot enable PCI device, aborting\n");
13226                 goto err_out;
13227         }
13228
13229         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13230                 dev_err(&bp->pdev->dev,
13231                         "Cannot find PCI device base address, aborting\n");
13232                 rc = -ENODEV;
13233                 goto err_out_disable;
13234         }
13235
13236         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13237                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13238                 rc = -ENODEV;
13239                 goto err_out_disable;
13240         }
13241
13242         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13243         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13244             PCICFG_REVESION_ID_ERROR_VAL) {
13245                 pr_err("PCI device error, probably due to fan failure, aborting\n");
13246                 rc = -ENODEV;
13247                 goto err_out_disable;
13248         }
13249
13250         if (atomic_read(&pdev->enable_cnt) == 1) {
13251                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13252                 if (rc) {
13253                         dev_err(&bp->pdev->dev,
13254                                 "Cannot obtain PCI resources, aborting\n");
13255                         goto err_out_disable;
13256                 }
13257
13258                 pci_set_master(pdev);
13259                 pci_save_state(pdev);
13260         }
13261
13262         if (IS_PF(bp)) {
13263                 if (!pdev->pm_cap) {
13264                         dev_err(&bp->pdev->dev,
13265                                 "Cannot find power management capability, aborting\n");
13266                         rc = -EIO;
13267                         goto err_out_release;
13268                 }
13269         }
13270
13271         if (!pci_is_pcie(pdev)) {
13272                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13273                 rc = -EIO;
13274                 goto err_out_release;
13275         }
13276
13277         rc = bnx2x_set_coherency_mask(bp);
13278         if (rc)
13279                 goto err_out_release;
13280
13281         dev->mem_start = pci_resource_start(pdev, 0);
13282         dev->base_addr = dev->mem_start;
13283         dev->mem_end = pci_resource_end(pdev, 0);
13284
13285         dev->irq = pdev->irq;
13286
13287         bp->regview = pci_ioremap_bar(pdev, 0);
13288         if (!bp->regview) {
13289                 dev_err(&bp->pdev->dev,
13290                         "Cannot map register space, aborting\n");
13291                 rc = -ENOMEM;
13292                 goto err_out_release;
13293         }
13294
13295         /* In E1/E1H use pci device function given by kernel.
13296          * In E2/E3 read physical function from ME register since these chips
13297          * support Physical Device Assignment where kernel BDF maybe arbitrary
13298          * (depending on hypervisor).
13299          */
13300         if (chip_is_e1x) {
13301                 bp->pf_num = PCI_FUNC(pdev->devfn);
13302         } else {
13303                 /* chip is E2/3*/
13304                 pci_read_config_dword(bp->pdev,
13305                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
13306                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13307                                   ME_REG_ABS_PF_NUM_SHIFT);
13308         }
13309         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13310
13311         /* clean indirect addresses */
13312         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13313                                PCICFG_VENDOR_ID_OFFSET);
13314
13315         /* Set PCIe reset type to fundamental for EEH recovery */
13316         pdev->needs_freset = 1;
13317
13318         /* AER (Advanced Error reporting) configuration */
13319         rc = pci_enable_pcie_error_reporting(pdev);
13320         if (!rc)
13321                 bp->flags |= AER_ENABLED;
13322         else
13323                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13324
13325         /*
13326          * Clean the following indirect addresses for all functions since it
13327          * is not used by the driver.
13328          */
13329         if (IS_PF(bp)) {
13330                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13331                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13332                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13333                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13334
13335                 if (chip_is_e1x) {
13336                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13337                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13338                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13339                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13340                 }
13341
13342                 /* Enable internal target-read (in case we are probed after PF
13343                  * FLR). Must be done prior to any BAR read access. Only for
13344                  * 57712 and up
13345                  */
13346                 if (!chip_is_e1x)
13347                         REG_WR(bp,
13348                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13349         }
13350
13351         dev->watchdog_timeo = TX_TIMEOUT;
13352
13353         dev->netdev_ops = &bnx2x_netdev_ops;
13354         bnx2x_set_ethtool_ops(bp, dev);
13355
13356         dev->priv_flags |= IFF_UNICAST_FLT;
13357
13358         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13359                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13360                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13361                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13362         if (!chip_is_e1x) {
13363                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13364                                     NETIF_F_GSO_IPXIP4 |
13365                                     NETIF_F_GSO_UDP_TUNNEL |
13366                                     NETIF_F_GSO_UDP_TUNNEL_CSUM |
13367                                     NETIF_F_GSO_PARTIAL;
13368
13369                 dev->hw_enc_features =
13370                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13371                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13372                         NETIF_F_GSO_IPXIP4 |
13373                         NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13374                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13375                         NETIF_F_GSO_PARTIAL;
13376
13377                 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13378                                             NETIF_F_GSO_UDP_TUNNEL_CSUM;
13379         }
13380
13381         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13382                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13383
13384         if (IS_PF(bp)) {
13385                 if (chip_is_e1x)
13386                         bp->accept_any_vlan = true;
13387                 else
13388                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13389         }
13390         /* For VF we'll know whether to enable VLAN filtering after
13391          * getting a response to CHANNEL_TLV_ACQUIRE from PF.
13392          */
13393
13394         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13395         dev->features |= NETIF_F_HIGHDMA;
13396
13397         /* Add Loopback capability to the device */
13398         dev->hw_features |= NETIF_F_LOOPBACK;
13399
13400 #ifdef BCM_DCBNL
13401         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13402 #endif
13403
13404         /* get_port_hwinfo() will set prtad and mmds properly */
13405         bp->mdio.prtad = MDIO_PRTAD_NONE;
13406         bp->mdio.mmds = 0;
13407         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13408         bp->mdio.dev = dev;
13409         bp->mdio.mdio_read = bnx2x_mdio_read;
13410         bp->mdio.mdio_write = bnx2x_mdio_write;
13411
13412         return 0;
13413
13414 err_out_release:
13415         if (atomic_read(&pdev->enable_cnt) == 1)
13416                 pci_release_regions(pdev);
13417
13418 err_out_disable:
13419         pci_disable_device(pdev);
13420
13421 err_out:
13422         return rc;
13423 }
13424
13425 /*(DEBLOBBED)*/
13426
13427 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13428 {
13429         const __be32 *source = (const __be32 *)_source;
13430         u32 *target = (u32 *)_target;
13431         u32 i;
13432
13433         for (i = 0; i < n/4; i++)
13434                 target[i] = be32_to_cpu(source[i]);
13435 }
13436
13437 /*
13438    Ops array is stored in the following format:
13439    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13440  */
13441 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13442 {
13443         const __be32 *source = (const __be32 *)_source;
13444         struct raw_op *target = (struct raw_op *)_target;
13445         u32 i, j, tmp;
13446
13447         for (i = 0, j = 0; i < n/8; i++, j += 2) {
13448                 tmp = be32_to_cpu(source[j]);
13449                 target[i].op = (tmp >> 24) & 0xff;
13450                 target[i].offset = tmp & 0xffffff;
13451                 target[i].raw_data = be32_to_cpu(source[j + 1]);
13452         }
13453 }
13454
13455 /* IRO array is stored in the following format:
13456  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13457  */
13458 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13459 {
13460         const __be32 *source = (const __be32 *)_source;
13461         struct iro *target = (struct iro *)_target;
13462         u32 i, j, tmp;
13463
13464         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13465                 target[i].base = be32_to_cpu(source[j]);
13466                 j++;
13467                 tmp = be32_to_cpu(source[j]);
13468                 target[i].m1 = (tmp >> 16) & 0xffff;
13469                 target[i].m2 = tmp & 0xffff;
13470                 j++;
13471                 tmp = be32_to_cpu(source[j]);
13472                 target[i].m3 = (tmp >> 16) & 0xffff;
13473                 target[i].size = tmp & 0xffff;
13474                 j++;
13475         }
13476 }
13477
13478 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13479 {
13480         const __be16 *source = (const __be16 *)_source;
13481         u16 *target = (u16 *)_target;
13482         u32 i;
13483
13484         for (i = 0; i < n/2; i++)
13485                 target[i] = be16_to_cpu(source[i]);
13486 }
13487
13488 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13489 do {                                                                    \
13490         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13491         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13492         if (!bp->arr)                                                   \
13493                 goto lbl;                                               \
13494         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13495              (u8 *)bp->arr, len);                                       \
13496 } while (0)
13497
13498 static int bnx2x_init_firmware(struct bnx2x *bp)
13499 {
13500         const char *fw_file_name;
13501         struct bnx2x_fw_file_hdr *fw_hdr;
13502         int rc;
13503
13504         if (bp->firmware)
13505                 return 0;
13506
13507         if (CHIP_IS_E1(bp))
13508                 fw_file_name = FW_FILE_NAME_E1;
13509         else if (CHIP_IS_E1H(bp))
13510                 fw_file_name = FW_FILE_NAME_E1H;
13511         else if (!CHIP_IS_E1x(bp))
13512                 fw_file_name = FW_FILE_NAME_E2;
13513         else {
13514                 BNX2X_ERR("Unsupported chip revision\n");
13515                 return -EINVAL;
13516         }
13517         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13518
13519         rc = reject_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13520         if (rc) {
13521                 BNX2X_ERR("Can't load firmware file %s\n",
13522                           fw_file_name);
13523                 goto request_firmware_exit;
13524         }
13525
13526         /*(DEBLOBBED)*/
13527         if (rc) {
13528                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13529                 goto request_firmware_exit;
13530         }
13531
13532         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13533
13534         /* Initialize the pointers to the init arrays */
13535         /* Blob */
13536         rc = -ENOMEM;
13537         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13538
13539         /* Opcodes */
13540         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13541
13542         /* Offsets */
13543         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13544                             be16_to_cpu_n);
13545
13546         /* STORMs firmware */
13547         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13548                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13549         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13550                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13551         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13552                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13553         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13554                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13555         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13556                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13557         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13558                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13559         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13560                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13561         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13562                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13563         /* IRO */
13564         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13565
13566         return 0;
13567
13568 iro_alloc_err:
13569         kfree(bp->init_ops_offsets);
13570 init_offsets_alloc_err:
13571         kfree(bp->init_ops);
13572 init_ops_alloc_err:
13573         kfree(bp->init_data);
13574 request_firmware_exit:
13575         release_firmware(bp->firmware);
13576         bp->firmware = NULL;
13577
13578         return rc;
13579 }
13580
13581 static void bnx2x_release_firmware(struct bnx2x *bp)
13582 {
13583         kfree(bp->init_ops_offsets);
13584         kfree(bp->init_ops);
13585         kfree(bp->init_data);
13586         release_firmware(bp->firmware);
13587         bp->firmware = NULL;
13588 }
13589
13590 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13591         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13592         .init_hw_cmn      = bnx2x_init_hw_common,
13593         .init_hw_port     = bnx2x_init_hw_port,
13594         .init_hw_func     = bnx2x_init_hw_func,
13595
13596         .reset_hw_cmn     = bnx2x_reset_common,
13597         .reset_hw_port    = bnx2x_reset_port,
13598         .reset_hw_func    = bnx2x_reset_func,
13599
13600         .gunzip_init      = bnx2x_gunzip_init,
13601         .gunzip_end       = bnx2x_gunzip_end,
13602
13603         .init_fw          = bnx2x_init_firmware,
13604         .release_fw       = bnx2x_release_firmware,
13605 };
13606
13607 void bnx2x__init_func_obj(struct bnx2x *bp)
13608 {
13609         /* Prepare DMAE related driver resources */
13610         bnx2x_setup_dmae(bp);
13611
13612         bnx2x_init_func_obj(bp, &bp->func_obj,
13613                             bnx2x_sp(bp, func_rdata),
13614                             bnx2x_sp_mapping(bp, func_rdata),
13615                             bnx2x_sp(bp, func_afex_rdata),
13616                             bnx2x_sp_mapping(bp, func_afex_rdata),
13617                             &bnx2x_func_sp_drv);
13618 }
13619
13620 /* must be called after sriov-enable */
13621 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13622 {
13623         int cid_count = BNX2X_L2_MAX_CID(bp);
13624
13625         if (IS_SRIOV(bp))
13626                 cid_count += BNX2X_VF_CIDS;
13627
13628         if (CNIC_SUPPORT(bp))
13629                 cid_count += CNIC_CID_MAX;
13630
13631         return roundup(cid_count, QM_CID_ROUND);
13632 }
13633
13634 /**
13635  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13636  *
13637  * @dev:        pci device
13638  *
13639  */
13640 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13641 {
13642         int index;
13643         u16 control = 0;
13644
13645         /*
13646          * If MSI-X is not supported - return number of SBs needed to support
13647          * one fast path queue: one FP queue + SB for CNIC
13648          */
13649         if (!pdev->msix_cap) {
13650                 dev_info(&pdev->dev, "no msix capability found\n");
13651                 return 1 + cnic_cnt;
13652         }
13653         dev_info(&pdev->dev, "msix capability found\n");
13654
13655         /*
13656          * The value in the PCI configuration space is the index of the last
13657          * entry, namely one less than the actual size of the table, which is
13658          * exactly what we want to return from this function: number of all SBs
13659          * without the default SB.
13660          * For VFs there is no default SB, then we return (index+1).
13661          */
13662         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13663
13664         index = control & PCI_MSIX_FLAGS_QSIZE;
13665
13666         return index;
13667 }
13668
13669 static int set_max_cos_est(int chip_id)
13670 {
13671         switch (chip_id) {
13672         case BCM57710:
13673         case BCM57711:
13674         case BCM57711E:
13675                 return BNX2X_MULTI_TX_COS_E1X;
13676         case BCM57712:
13677         case BCM57712_MF:
13678                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13679         case BCM57800:
13680         case BCM57800_MF:
13681         case BCM57810:
13682         case BCM57810_MF:
13683         case BCM57840_4_10:
13684         case BCM57840_2_20:
13685         case BCM57840_O:
13686         case BCM57840_MFO:
13687         case BCM57840_MF:
13688         case BCM57811:
13689         case BCM57811_MF:
13690                 return BNX2X_MULTI_TX_COS_E3B0;
13691         case BCM57712_VF:
13692         case BCM57800_VF:
13693         case BCM57810_VF:
13694         case BCM57840_VF:
13695         case BCM57811_VF:
13696                 return 1;
13697         default:
13698                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13699                 return -ENODEV;
13700         }
13701 }
13702
13703 static int set_is_vf(int chip_id)
13704 {
13705         switch (chip_id) {
13706         case BCM57712_VF:
13707         case BCM57800_VF:
13708         case BCM57810_VF:
13709         case BCM57840_VF:
13710         case BCM57811_VF:
13711                 return true;
13712         default:
13713                 return false;
13714         }
13715 }
13716
13717 /* nig_tsgen registers relative address */
13718 #define tsgen_ctrl 0x0
13719 #define tsgen_freecount 0x10
13720 #define tsgen_synctime_t0 0x20
13721 #define tsgen_offset_t0 0x28
13722 #define tsgen_drift_t0 0x30
13723 #define tsgen_synctime_t1 0x58
13724 #define tsgen_offset_t1 0x60
13725 #define tsgen_drift_t1 0x68
13726
13727 /* FW workaround for setting drift */
13728 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13729                                           int best_val, int best_period)
13730 {
13731         struct bnx2x_func_state_params func_params = {NULL};
13732         struct bnx2x_func_set_timesync_params *set_timesync_params =
13733                 &func_params.params.set_timesync;
13734
13735         /* Prepare parameters for function state transitions */
13736         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13737         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13738
13739         func_params.f_obj = &bp->func_obj;
13740         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13741
13742         /* Function parameters */
13743         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13744         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13745         set_timesync_params->add_sub_drift_adjust_value =
13746                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13747         set_timesync_params->drift_adjust_value = best_val;
13748         set_timesync_params->drift_adjust_period = best_period;
13749
13750         return bnx2x_func_state_change(bp, &func_params);
13751 }
13752
13753 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13754 {
13755         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13756         int rc;
13757         int drift_dir = 1;
13758         int val, period, period1, period2, dif, dif1, dif2;
13759         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13760
13761         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13762
13763         if (!netif_running(bp->dev)) {
13764                 DP(BNX2X_MSG_PTP,
13765                    "PTP adjfreq called while the interface is down\n");
13766                 return -ENETDOWN;
13767         }
13768
13769         if (ppb < 0) {
13770                 ppb = -ppb;
13771                 drift_dir = 0;
13772         }
13773
13774         if (ppb == 0) {
13775                 best_val = 1;
13776                 best_period = 0x1FFFFFF;
13777         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13778                 best_val = 31;
13779                 best_period = 1;
13780         } else {
13781                 /* Changed not to allow val = 8, 16, 24 as these values
13782                  * are not supported in workaround.
13783                  */
13784                 for (val = 0; val <= 31; val++) {
13785                         if ((val & 0x7) == 0)
13786                                 continue;
13787                         period1 = val * 1000000 / ppb;
13788                         period2 = period1 + 1;
13789                         if (period1 != 0)
13790                                 dif1 = ppb - (val * 1000000 / period1);
13791                         else
13792                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13793                         if (dif1 < 0)
13794                                 dif1 = -dif1;
13795                         dif2 = ppb - (val * 1000000 / period2);
13796                         if (dif2 < 0)
13797                                 dif2 = -dif2;
13798                         dif = (dif1 < dif2) ? dif1 : dif2;
13799                         period = (dif1 < dif2) ? period1 : period2;
13800                         if (dif < best_dif) {
13801                                 best_dif = dif;
13802                                 best_val = val;
13803                                 best_period = period;
13804                         }
13805                 }
13806         }
13807
13808         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13809                                             best_period);
13810         if (rc) {
13811                 BNX2X_ERR("Failed to set drift\n");
13812                 return -EFAULT;
13813         }
13814
13815         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13816            best_period);
13817
13818         return 0;
13819 }
13820
13821 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13822 {
13823         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13824
13825         if (!netif_running(bp->dev)) {
13826                 DP(BNX2X_MSG_PTP,
13827                    "PTP adjtime called while the interface is down\n");
13828                 return -ENETDOWN;
13829         }
13830
13831         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13832
13833         timecounter_adjtime(&bp->timecounter, delta);
13834
13835         return 0;
13836 }
13837
13838 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13839 {
13840         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13841         u64 ns;
13842
13843         if (!netif_running(bp->dev)) {
13844                 DP(BNX2X_MSG_PTP,
13845                    "PTP gettime called while the interface is down\n");
13846                 return -ENETDOWN;
13847         }
13848
13849         ns = timecounter_read(&bp->timecounter);
13850
13851         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13852
13853         *ts = ns_to_timespec64(ns);
13854
13855         return 0;
13856 }
13857
13858 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13859                              const struct timespec64 *ts)
13860 {
13861         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13862         u64 ns;
13863
13864         if (!netif_running(bp->dev)) {
13865                 DP(BNX2X_MSG_PTP,
13866                    "PTP settime called while the interface is down\n");
13867                 return -ENETDOWN;
13868         }
13869
13870         ns = timespec64_to_ns(ts);
13871
13872         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13873
13874         /* Re-init the timecounter */
13875         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13876
13877         return 0;
13878 }
13879
13880 /* Enable (or disable) ancillary features of the phc subsystem */
13881 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13882                             struct ptp_clock_request *rq, int on)
13883 {
13884         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13885
13886         BNX2X_ERR("PHC ancillary features are not supported\n");
13887         return -ENOTSUPP;
13888 }
13889
13890 static void bnx2x_register_phc(struct bnx2x *bp)
13891 {
13892         /* Fill the ptp_clock_info struct and register PTP clock*/
13893         bp->ptp_clock_info.owner = THIS_MODULE;
13894         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13895         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13896         bp->ptp_clock_info.n_alarm = 0;
13897         bp->ptp_clock_info.n_ext_ts = 0;
13898         bp->ptp_clock_info.n_per_out = 0;
13899         bp->ptp_clock_info.pps = 0;
13900         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13901         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13902         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13903         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13904         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13905
13906         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13907         if (IS_ERR(bp->ptp_clock)) {
13908                 bp->ptp_clock = NULL;
13909                 BNX2X_ERR("PTP clock registeration failed\n");
13910         }
13911 }
13912
13913 static int bnx2x_init_one(struct pci_dev *pdev,
13914                                     const struct pci_device_id *ent)
13915 {
13916         struct net_device *dev = NULL;
13917         struct bnx2x *bp;
13918         enum pcie_link_width pcie_width;
13919         enum pci_bus_speed pcie_speed;
13920         int rc, max_non_def_sbs;
13921         int rx_count, tx_count, rss_count, doorbell_size;
13922         int max_cos_est;
13923         bool is_vf;
13924         int cnic_cnt;
13925
13926         /* Management FW 'remembers' living interfaces. Allow it some time
13927          * to forget previously living interfaces, allowing a proper re-load.
13928          */
13929         if (is_kdump_kernel()) {
13930                 ktime_t now = ktime_get_boottime();
13931                 ktime_t fw_ready_time = ktime_set(5, 0);
13932
13933                 if (ktime_before(now, fw_ready_time))
13934                         msleep(ktime_ms_delta(fw_ready_time, now));
13935         }
13936
13937         /* An estimated maximum supported CoS number according to the chip
13938          * version.
13939          * We will try to roughly estimate the maximum number of CoSes this chip
13940          * may support in order to minimize the memory allocated for Tx
13941          * netdev_queue's. This number will be accurately calculated during the
13942          * initialization of bp->max_cos based on the chip versions AND chip
13943          * revision in the bnx2x_init_bp().
13944          */
13945         max_cos_est = set_max_cos_est(ent->driver_data);
13946         if (max_cos_est < 0)
13947                 return max_cos_est;
13948         is_vf = set_is_vf(ent->driver_data);
13949         cnic_cnt = is_vf ? 0 : 1;
13950
13951         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13952
13953         /* add another SB for VF as it has no default SB */
13954         max_non_def_sbs += is_vf ? 1 : 0;
13955
13956         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13957         rss_count = max_non_def_sbs - cnic_cnt;
13958
13959         if (rss_count < 1)
13960                 return -EINVAL;
13961
13962         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13963         rx_count = rss_count + cnic_cnt;
13964
13965         /* Maximum number of netdev Tx queues:
13966          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13967          */
13968         tx_count = rss_count * max_cos_est + cnic_cnt;
13969
13970         /* dev zeroed in init_etherdev */
13971         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13972         if (!dev)
13973                 return -ENOMEM;
13974
13975         bp = netdev_priv(dev);
13976
13977         bp->flags = 0;
13978         if (is_vf)
13979                 bp->flags |= IS_VF_FLAG;
13980
13981         bp->igu_sb_cnt = max_non_def_sbs;
13982         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13983         bp->msg_enable = debug;
13984         bp->cnic_support = cnic_cnt;
13985         bp->cnic_probe = bnx2x_cnic_probe;
13986
13987         pci_set_drvdata(pdev, dev);
13988
13989         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13990         if (rc < 0) {
13991                 free_netdev(dev);
13992                 return rc;
13993         }
13994
13995         BNX2X_DEV_INFO("This is a %s function\n",
13996                        IS_PF(bp) ? "physical" : "virtual");
13997         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13998         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13999         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
14000                        tx_count, rx_count);
14001
14002         rc = bnx2x_init_bp(bp);
14003         if (rc)
14004                 goto init_one_exit;
14005
14006         /* Map doorbells here as we need the real value of bp->max_cos which
14007          * is initialized in bnx2x_init_bp() to determine the number of
14008          * l2 connections.
14009          */
14010         if (IS_VF(bp)) {
14011                 bp->doorbells = bnx2x_vf_doorbells(bp);
14012                 rc = bnx2x_vf_pci_alloc(bp);
14013                 if (rc)
14014                         goto init_one_freemem;
14015         } else {
14016                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
14017                 if (doorbell_size > pci_resource_len(pdev, 2)) {
14018                         dev_err(&bp->pdev->dev,
14019                                 "Cannot map doorbells, bar size too small, aborting\n");
14020                         rc = -ENOMEM;
14021                         goto init_one_freemem;
14022                 }
14023                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
14024                                                 doorbell_size);
14025         }
14026         if (!bp->doorbells) {
14027                 dev_err(&bp->pdev->dev,
14028                         "Cannot map doorbell space, aborting\n");
14029                 rc = -ENOMEM;
14030                 goto init_one_freemem;
14031         }
14032
14033         if (IS_VF(bp)) {
14034                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
14035                 if (rc)
14036                         goto init_one_freemem;
14037
14038 #ifdef CONFIG_BNX2X_SRIOV
14039                 /* VF with OLD Hypervisor or old PF do not support filtering */
14040                 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
14041                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14042                         dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14043                 }
14044 #endif
14045         }
14046
14047         /* Enable SRIOV if capability found in configuration space */
14048         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
14049         if (rc)
14050                 goto init_one_freemem;
14051
14052         /* calc qm_cid_count */
14053         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
14054         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
14055
14056         /* disable FCOE L2 queue for E1x*/
14057         if (CHIP_IS_E1x(bp))
14058                 bp->flags |= NO_FCOE_FLAG;
14059
14060         /* Set bp->num_queues for MSI-X mode*/
14061         bnx2x_set_num_queues(bp);
14062
14063         /* Configure interrupt mode: try to enable MSI-X/MSI if
14064          * needed.
14065          */
14066         rc = bnx2x_set_int_mode(bp);
14067         if (rc) {
14068                 dev_err(&pdev->dev, "Cannot set interrupts\n");
14069                 goto init_one_freemem;
14070         }
14071         BNX2X_DEV_INFO("set interrupts successfully\n");
14072
14073         /* register the net device */
14074         rc = register_netdev(dev);
14075         if (rc) {
14076                 dev_err(&pdev->dev, "Cannot register net device\n");
14077                 goto init_one_freemem;
14078         }
14079         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
14080
14081         if (!NO_FCOE(bp)) {
14082                 /* Add storage MAC address */
14083                 rtnl_lock();
14084                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14085                 rtnl_unlock();
14086         }
14087         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
14088             pcie_speed == PCI_SPEED_UNKNOWN ||
14089             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
14090                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
14091         else
14092                 BNX2X_DEV_INFO(
14093                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
14094                        board_info[ent->driver_data].name,
14095                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14096                        pcie_width,
14097                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
14098                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
14099                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
14100                        "Unknown",
14101                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
14102
14103         bnx2x_register_phc(bp);
14104
14105         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14106                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14107
14108         return 0;
14109
14110 init_one_freemem:
14111         bnx2x_free_mem_bp(bp);
14112
14113 init_one_exit:
14114         bnx2x_disable_pcie_error_reporting(bp);
14115
14116         if (bp->regview)
14117                 iounmap(bp->regview);
14118
14119         if (IS_PF(bp) && bp->doorbells)
14120                 iounmap(bp->doorbells);
14121
14122         free_netdev(dev);
14123
14124         if (atomic_read(&pdev->enable_cnt) == 1)
14125                 pci_release_regions(pdev);
14126
14127         pci_disable_device(pdev);
14128
14129         return rc;
14130 }
14131
14132 static void __bnx2x_remove(struct pci_dev *pdev,
14133                            struct net_device *dev,
14134                            struct bnx2x *bp,
14135                            bool remove_netdev)
14136 {
14137         if (bp->ptp_clock) {
14138                 ptp_clock_unregister(bp->ptp_clock);
14139                 bp->ptp_clock = NULL;
14140         }
14141
14142         /* Delete storage MAC address */
14143         if (!NO_FCOE(bp)) {
14144                 rtnl_lock();
14145                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14146                 rtnl_unlock();
14147         }
14148
14149 #ifdef BCM_DCBNL
14150         /* Delete app tlvs from dcbnl */
14151         bnx2x_dcbnl_update_applist(bp, true);
14152 #endif
14153
14154         if (IS_PF(bp) &&
14155             !BP_NOMCP(bp) &&
14156             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14157                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14158
14159         /* Close the interface - either directly or implicitly */
14160         if (remove_netdev) {
14161                 unregister_netdev(dev);
14162         } else {
14163                 rtnl_lock();
14164                 dev_close(dev);
14165                 rtnl_unlock();
14166         }
14167
14168         bnx2x_iov_remove_one(bp);
14169
14170         /* Power on: we can't let PCI layer write to us while we are in D3 */
14171         if (IS_PF(bp)) {
14172                 bnx2x_set_power_state(bp, PCI_D0);
14173                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14174
14175                 /* Set endianity registers to reset values in case next driver
14176                  * boots in different endianty environment.
14177                  */
14178                 bnx2x_reset_endianity(bp);
14179         }
14180
14181         /* Disable MSI/MSI-X */
14182         bnx2x_disable_msi(bp);
14183
14184         /* Power off */
14185         if (IS_PF(bp))
14186                 bnx2x_set_power_state(bp, PCI_D3hot);
14187
14188         /* Make sure RESET task is not scheduled before continuing */
14189         cancel_delayed_work_sync(&bp->sp_rtnl_task);
14190
14191         /* send message via vfpf channel to release the resources of this vf */
14192         if (IS_VF(bp))
14193                 bnx2x_vfpf_release(bp);
14194
14195         /* Assumes no further PCIe PM changes will occur */
14196         if (system_state == SYSTEM_POWER_OFF) {
14197                 pci_wake_from_d3(pdev, bp->wol);
14198                 pci_set_power_state(pdev, PCI_D3hot);
14199         }
14200
14201         bnx2x_disable_pcie_error_reporting(bp);
14202         if (remove_netdev) {
14203                 if (bp->regview)
14204                         iounmap(bp->regview);
14205
14206                 /* For vfs, doorbells are part of the regview and were unmapped
14207                  * along with it. FW is only loaded by PF.
14208                  */
14209                 if (IS_PF(bp)) {
14210                         if (bp->doorbells)
14211                                 iounmap(bp->doorbells);
14212
14213                         bnx2x_release_firmware(bp);
14214                 } else {
14215                         bnx2x_vf_pci_dealloc(bp);
14216                 }
14217                 bnx2x_free_mem_bp(bp);
14218
14219                 free_netdev(dev);
14220
14221                 if (atomic_read(&pdev->enable_cnt) == 1)
14222                         pci_release_regions(pdev);
14223
14224                 pci_disable_device(pdev);
14225         }
14226 }
14227
14228 static void bnx2x_remove_one(struct pci_dev *pdev)
14229 {
14230         struct net_device *dev = pci_get_drvdata(pdev);
14231         struct bnx2x *bp;
14232
14233         if (!dev) {
14234                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14235                 return;
14236         }
14237         bp = netdev_priv(dev);
14238
14239         __bnx2x_remove(pdev, dev, bp, true);
14240 }
14241
14242 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14243 {
14244         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14245
14246         bp->rx_mode = BNX2X_RX_MODE_NONE;
14247
14248         if (CNIC_LOADED(bp))
14249                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14250
14251         /* Stop Tx */
14252         bnx2x_tx_disable(bp);
14253         /* Delete all NAPI objects */
14254         bnx2x_del_all_napi(bp);
14255         if (CNIC_LOADED(bp))
14256                 bnx2x_del_all_napi_cnic(bp);
14257         netdev_reset_tc(bp->dev);
14258
14259         del_timer_sync(&bp->timer);
14260         cancel_delayed_work_sync(&bp->sp_task);
14261         cancel_delayed_work_sync(&bp->period_task);
14262
14263         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14264                 bp->stats_state = STATS_STATE_DISABLED;
14265                 up(&bp->stats_lock);
14266         }
14267
14268         bnx2x_save_statistics(bp);
14269
14270         netif_carrier_off(bp->dev);
14271
14272         return 0;
14273 }
14274
14275 /**
14276  * bnx2x_io_error_detected - called when PCI error is detected
14277  * @pdev: Pointer to PCI device
14278  * @state: The current pci connection state
14279  *
14280  * This function is called after a PCI bus error affecting
14281  * this device has been detected.
14282  */
14283 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14284                                                 pci_channel_state_t state)
14285 {
14286         struct net_device *dev = pci_get_drvdata(pdev);
14287         struct bnx2x *bp = netdev_priv(dev);
14288
14289         rtnl_lock();
14290
14291         BNX2X_ERR("IO error detected\n");
14292
14293         netif_device_detach(dev);
14294
14295         if (state == pci_channel_io_perm_failure) {
14296                 rtnl_unlock();
14297                 return PCI_ERS_RESULT_DISCONNECT;
14298         }
14299
14300         if (netif_running(dev))
14301                 bnx2x_eeh_nic_unload(bp);
14302
14303         bnx2x_prev_path_mark_eeh(bp);
14304
14305         pci_disable_device(pdev);
14306
14307         rtnl_unlock();
14308
14309         /* Request a slot reset */
14310         return PCI_ERS_RESULT_NEED_RESET;
14311 }
14312
14313 /**
14314  * bnx2x_io_slot_reset - called after the PCI bus has been reset
14315  * @pdev: Pointer to PCI device
14316  *
14317  * Restart the card from scratch, as if from a cold-boot.
14318  */
14319 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14320 {
14321         struct net_device *dev = pci_get_drvdata(pdev);
14322         struct bnx2x *bp = netdev_priv(dev);
14323         int i;
14324
14325         rtnl_lock();
14326         BNX2X_ERR("IO slot reset initializing...\n");
14327         if (pci_enable_device(pdev)) {
14328                 dev_err(&pdev->dev,
14329                         "Cannot re-enable PCI device after reset\n");
14330                 rtnl_unlock();
14331                 return PCI_ERS_RESULT_DISCONNECT;
14332         }
14333
14334         pci_set_master(pdev);
14335         pci_restore_state(pdev);
14336         pci_save_state(pdev);
14337
14338         if (netif_running(dev))
14339                 bnx2x_set_power_state(bp, PCI_D0);
14340
14341         if (netif_running(dev)) {
14342                 BNX2X_ERR("IO slot reset --> driver unload\n");
14343
14344                 /* MCP should have been reset; Need to wait for validity */
14345                 if (bnx2x_init_shmem(bp)) {
14346                         rtnl_unlock();
14347                         return PCI_ERS_RESULT_DISCONNECT;
14348                 }
14349
14350                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14351                         u32 v;
14352
14353                         v = SHMEM2_RD(bp,
14354                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14355                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14356                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14357                 }
14358                 bnx2x_drain_tx_queues(bp);
14359                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14360                 bnx2x_netif_stop(bp, 1);
14361                 bnx2x_free_irq(bp);
14362
14363                 /* Report UNLOAD_DONE to MCP */
14364                 bnx2x_send_unload_done(bp, true);
14365
14366                 bp->sp_state = 0;
14367                 bp->port.pmf = 0;
14368
14369                 bnx2x_prev_unload(bp);
14370
14371                 /* We should have reseted the engine, so It's fair to
14372                  * assume the FW will no longer write to the bnx2x driver.
14373                  */
14374                 bnx2x_squeeze_objects(bp);
14375                 bnx2x_free_skbs(bp);
14376                 for_each_rx_queue(bp, i)
14377                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14378                 bnx2x_free_fp_mem(bp);
14379                 bnx2x_free_mem(bp);
14380
14381                 bp->state = BNX2X_STATE_CLOSED;
14382         }
14383
14384         rtnl_unlock();
14385
14386         /* If AER, perform cleanup of the PCIe registers */
14387         if (bp->flags & AER_ENABLED) {
14388                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14389                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14390                 else
14391                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14392         }
14393
14394         return PCI_ERS_RESULT_RECOVERED;
14395 }
14396
14397 /**
14398  * bnx2x_io_resume - called when traffic can start flowing again
14399  * @pdev: Pointer to PCI device
14400  *
14401  * This callback is called when the error recovery driver tells us that
14402  * its OK to resume normal operation.
14403  */
14404 static void bnx2x_io_resume(struct pci_dev *pdev)
14405 {
14406         struct net_device *dev = pci_get_drvdata(pdev);
14407         struct bnx2x *bp = netdev_priv(dev);
14408
14409         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14410                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14411                 return;
14412         }
14413
14414         rtnl_lock();
14415
14416         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14417                                                         DRV_MSG_SEQ_NUMBER_MASK;
14418
14419         if (netif_running(dev))
14420                 bnx2x_nic_load(bp, LOAD_NORMAL);
14421
14422         netif_device_attach(dev);
14423
14424         rtnl_unlock();
14425 }
14426
14427 static const struct pci_error_handlers bnx2x_err_handler = {
14428         .error_detected = bnx2x_io_error_detected,
14429         .slot_reset     = bnx2x_io_slot_reset,
14430         .resume         = bnx2x_io_resume,
14431 };
14432
14433 static void bnx2x_shutdown(struct pci_dev *pdev)
14434 {
14435         struct net_device *dev = pci_get_drvdata(pdev);
14436         struct bnx2x *bp;
14437
14438         if (!dev)
14439                 return;
14440
14441         bp = netdev_priv(dev);
14442         if (!bp)
14443                 return;
14444
14445         rtnl_lock();
14446         netif_device_detach(dev);
14447         rtnl_unlock();
14448
14449         /* Don't remove the netdevice, as there are scenarios which will cause
14450          * the kernel to hang, e.g., when trying to remove bnx2i while the
14451          * rootfs is mounted from SAN.
14452          */
14453         __bnx2x_remove(pdev, dev, bp, false);
14454 }
14455
14456 static struct pci_driver bnx2x_pci_driver = {
14457         .name        = DRV_MODULE_NAME,
14458         .id_table    = bnx2x_pci_tbl,
14459         .probe       = bnx2x_init_one,
14460         .remove      = bnx2x_remove_one,
14461         .suspend     = bnx2x_suspend,
14462         .resume      = bnx2x_resume,
14463         .err_handler = &bnx2x_err_handler,
14464 #ifdef CONFIG_BNX2X_SRIOV
14465         .sriov_configure = bnx2x_sriov_configure,
14466 #endif
14467         .shutdown    = bnx2x_shutdown,
14468 };
14469
14470 static int __init bnx2x_init(void)
14471 {
14472         int ret;
14473
14474         pr_info("%s", version);
14475
14476         bnx2x_wq = create_singlethread_workqueue("bnx2x");
14477         if (bnx2x_wq == NULL) {
14478                 pr_err("Cannot create workqueue\n");
14479                 return -ENOMEM;
14480         }
14481         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14482         if (!bnx2x_iov_wq) {
14483                 pr_err("Cannot create iov workqueue\n");
14484                 destroy_workqueue(bnx2x_wq);
14485                 return -ENOMEM;
14486         }
14487
14488         ret = pci_register_driver(&bnx2x_pci_driver);
14489         if (ret) {
14490                 pr_err("Cannot register driver\n");
14491                 destroy_workqueue(bnx2x_wq);
14492                 destroy_workqueue(bnx2x_iov_wq);
14493         }
14494         return ret;
14495 }
14496
14497 static void __exit bnx2x_cleanup(void)
14498 {
14499         struct list_head *pos, *q;
14500
14501         pci_unregister_driver(&bnx2x_pci_driver);
14502
14503         destroy_workqueue(bnx2x_wq);
14504         destroy_workqueue(bnx2x_iov_wq);
14505
14506         /* Free globally allocated resources */
14507         list_for_each_safe(pos, q, &bnx2x_prev_list) {
14508                 struct bnx2x_prev_path_list *tmp =
14509                         list_entry(pos, struct bnx2x_prev_path_list, list);
14510                 list_del(pos);
14511                 kfree(tmp);
14512         }
14513 }
14514
14515 void bnx2x_notify_link_changed(struct bnx2x *bp)
14516 {
14517         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14518 }
14519
14520 module_init(bnx2x_init);
14521 module_exit(bnx2x_cleanup);
14522
14523 /**
14524  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14525  *
14526  * @bp:         driver handle
14527  * @set:        set or clear the CAM entry
14528  *
14529  * This function will wait until the ramrod completion returns.
14530  * Return 0 if success, -ENODEV if ramrod doesn't return.
14531  */
14532 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14533 {
14534         unsigned long ramrod_flags = 0;
14535
14536         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14537         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14538                                  &bp->iscsi_l2_mac_obj, true,
14539                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14540 }
14541
14542 /* count denotes the number of new completions we have seen */
14543 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14544 {
14545         struct eth_spe *spe;
14546         int cxt_index, cxt_offset;
14547
14548 #ifdef BNX2X_STOP_ON_ERROR
14549         if (unlikely(bp->panic))
14550                 return;
14551 #endif
14552
14553         spin_lock_bh(&bp->spq_lock);
14554         BUG_ON(bp->cnic_spq_pending < count);
14555         bp->cnic_spq_pending -= count;
14556
14557         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14558                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14559                                 & SPE_HDR_CONN_TYPE) >>
14560                                 SPE_HDR_CONN_TYPE_SHIFT;
14561                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14562                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14563
14564                 /* Set validation for iSCSI L2 client before sending SETUP
14565                  *  ramrod
14566                  */
14567                 if (type == ETH_CONNECTION_TYPE) {
14568                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14569                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14570                                         ILT_PAGE_CIDS;
14571                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14572                                         (cxt_index * ILT_PAGE_CIDS);
14573                                 bnx2x_set_ctx_validation(bp,
14574                                         &bp->context[cxt_index].
14575                                                          vcxt[cxt_offset].eth,
14576                                         BNX2X_ISCSI_ETH_CID(bp));
14577                         }
14578                 }
14579
14580                 /*
14581                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14582                  * and in the air. We also check that number of outstanding
14583                  * COMMON ramrods is not more than the EQ and SPQ can
14584                  * accommodate.
14585                  */
14586                 if (type == ETH_CONNECTION_TYPE) {
14587                         if (!atomic_read(&bp->cq_spq_left))
14588                                 break;
14589                         else
14590                                 atomic_dec(&bp->cq_spq_left);
14591                 } else if (type == NONE_CONNECTION_TYPE) {
14592                         if (!atomic_read(&bp->eq_spq_left))
14593                                 break;
14594                         else
14595                                 atomic_dec(&bp->eq_spq_left);
14596                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14597                            (type == FCOE_CONNECTION_TYPE)) {
14598                         if (bp->cnic_spq_pending >=
14599                             bp->cnic_eth_dev.max_kwqe_pending)
14600                                 break;
14601                         else
14602                                 bp->cnic_spq_pending++;
14603                 } else {
14604                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14605                         bnx2x_panic();
14606                         break;
14607                 }
14608
14609                 spe = bnx2x_sp_get_next(bp);
14610                 *spe = *bp->cnic_kwq_cons;
14611
14612                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14613                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14614
14615                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14616                         bp->cnic_kwq_cons = bp->cnic_kwq;
14617                 else
14618                         bp->cnic_kwq_cons++;
14619         }
14620         bnx2x_sp_prod_update(bp);
14621         spin_unlock_bh(&bp->spq_lock);
14622 }
14623
14624 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14625                                struct kwqe_16 *kwqes[], u32 count)
14626 {
14627         struct bnx2x *bp = netdev_priv(dev);
14628         int i;
14629
14630 #ifdef BNX2X_STOP_ON_ERROR
14631         if (unlikely(bp->panic)) {
14632                 BNX2X_ERR("Can't post to SP queue while panic\n");
14633                 return -EIO;
14634         }
14635 #endif
14636
14637         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14638             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14639                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14640                 return -EAGAIN;
14641         }
14642
14643         spin_lock_bh(&bp->spq_lock);
14644
14645         for (i = 0; i < count; i++) {
14646                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14647
14648                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14649                         break;
14650
14651                 *bp->cnic_kwq_prod = *spe;
14652
14653                 bp->cnic_kwq_pending++;
14654
14655                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14656                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14657                    spe->data.update_data_addr.hi,
14658                    spe->data.update_data_addr.lo,
14659                    bp->cnic_kwq_pending);
14660
14661                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14662                         bp->cnic_kwq_prod = bp->cnic_kwq;
14663                 else
14664                         bp->cnic_kwq_prod++;
14665         }
14666
14667         spin_unlock_bh(&bp->spq_lock);
14668
14669         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14670                 bnx2x_cnic_sp_post(bp, 0);
14671
14672         return i;
14673 }
14674
14675 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14676 {
14677         struct cnic_ops *c_ops;
14678         int rc = 0;
14679
14680         mutex_lock(&bp->cnic_mutex);
14681         c_ops = rcu_dereference_protected(bp->cnic_ops,
14682                                           lockdep_is_held(&bp->cnic_mutex));
14683         if (c_ops)
14684                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14685         mutex_unlock(&bp->cnic_mutex);
14686
14687         return rc;
14688 }
14689
14690 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14691 {
14692         struct cnic_ops *c_ops;
14693         int rc = 0;
14694
14695         rcu_read_lock();
14696         c_ops = rcu_dereference(bp->cnic_ops);
14697         if (c_ops)
14698                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14699         rcu_read_unlock();
14700
14701         return rc;
14702 }
14703
14704 /*
14705  * for commands that have no data
14706  */
14707 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14708 {
14709         struct cnic_ctl_info ctl = {0};
14710
14711         ctl.cmd = cmd;
14712
14713         return bnx2x_cnic_ctl_send(bp, &ctl);
14714 }
14715
14716 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14717 {
14718         struct cnic_ctl_info ctl = {0};
14719
14720         /* first we tell CNIC and only then we count this as a completion */
14721         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14722         ctl.data.comp.cid = cid;
14723         ctl.data.comp.error = err;
14724
14725         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14726         bnx2x_cnic_sp_post(bp, 0);
14727 }
14728
14729 /* Called with netif_addr_lock_bh() taken.
14730  * Sets an rx_mode config for an iSCSI ETH client.
14731  * Doesn't block.
14732  * Completion should be checked outside.
14733  */
14734 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14735 {
14736         unsigned long accept_flags = 0, ramrod_flags = 0;
14737         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14738         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14739
14740         if (start) {
14741                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14742                  * because it's the only way for UIO Queue to accept
14743                  * multicasts (in non-promiscuous mode only one Queue per
14744                  * function will receive multicast packets (leading in our
14745                  * case).
14746                  */
14747                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14748                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14749                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14750                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14751
14752                 /* Clear STOP_PENDING bit if START is requested */
14753                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14754
14755                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14756         } else
14757                 /* Clear START_PENDING bit if STOP is requested */
14758                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14759
14760         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14761                 set_bit(sched_state, &bp->sp_state);
14762         else {
14763                 __set_bit(RAMROD_RX, &ramrod_flags);
14764                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14765                                     ramrod_flags);
14766         }
14767 }
14768
14769 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14770 {
14771         struct bnx2x *bp = netdev_priv(dev);
14772         int rc = 0;
14773
14774         switch (ctl->cmd) {
14775         case DRV_CTL_CTXTBL_WR_CMD: {
14776                 u32 index = ctl->data.io.offset;
14777                 dma_addr_t addr = ctl->data.io.dma_addr;
14778
14779                 bnx2x_ilt_wr(bp, index, addr);
14780                 break;
14781         }
14782
14783         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14784                 int count = ctl->data.credit.credit_count;
14785
14786                 bnx2x_cnic_sp_post(bp, count);
14787                 break;
14788         }
14789
14790         /* rtnl_lock is held.  */
14791         case DRV_CTL_START_L2_CMD: {
14792                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14793                 unsigned long sp_bits = 0;
14794
14795                 /* Configure the iSCSI classification object */
14796                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14797                                    cp->iscsi_l2_client_id,
14798                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14799                                    bnx2x_sp(bp, mac_rdata),
14800                                    bnx2x_sp_mapping(bp, mac_rdata),
14801                                    BNX2X_FILTER_MAC_PENDING,
14802                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14803                                    &bp->macs_pool);
14804
14805                 /* Set iSCSI MAC address */
14806                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14807                 if (rc)
14808                         break;
14809
14810                 mmiowb();
14811                 barrier();
14812
14813                 /* Start accepting on iSCSI L2 ring */
14814
14815                 netif_addr_lock_bh(dev);
14816                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14817                 netif_addr_unlock_bh(dev);
14818
14819                 /* bits to wait on */
14820                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14821                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14822
14823                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14824                         BNX2X_ERR("rx_mode completion timed out!\n");
14825
14826                 break;
14827         }
14828
14829         /* rtnl_lock is held.  */
14830         case DRV_CTL_STOP_L2_CMD: {
14831                 unsigned long sp_bits = 0;
14832
14833                 /* Stop accepting on iSCSI L2 ring */
14834                 netif_addr_lock_bh(dev);
14835                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14836                 netif_addr_unlock_bh(dev);
14837
14838                 /* bits to wait on */
14839                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14840                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14841
14842                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14843                         BNX2X_ERR("rx_mode completion timed out!\n");
14844
14845                 mmiowb();
14846                 barrier();
14847
14848                 /* Unset iSCSI L2 MAC */
14849                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14850                                         BNX2X_ISCSI_ETH_MAC, true);
14851                 break;
14852         }
14853         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14854                 int count = ctl->data.credit.credit_count;
14855
14856                 smp_mb__before_atomic();
14857                 atomic_add(count, &bp->cq_spq_left);
14858                 smp_mb__after_atomic();
14859                 break;
14860         }
14861         case DRV_CTL_ULP_REGISTER_CMD: {
14862                 int ulp_type = ctl->data.register_data.ulp_type;
14863
14864                 if (CHIP_IS_E3(bp)) {
14865                         int idx = BP_FW_MB_IDX(bp);
14866                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14867                         int path = BP_PATH(bp);
14868                         int port = BP_PORT(bp);
14869                         int i;
14870                         u32 scratch_offset;
14871                         u32 *host_addr;
14872
14873                         /* first write capability to shmem2 */
14874                         if (ulp_type == CNIC_ULP_ISCSI)
14875                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14876                         else if (ulp_type == CNIC_ULP_FCOE)
14877                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14878                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14879
14880                         if ((ulp_type != CNIC_ULP_FCOE) ||
14881                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14882                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14883                                 break;
14884
14885                         /* if reached here - should write fcoe capabilities */
14886                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14887                         if (!scratch_offset)
14888                                 break;
14889                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14890                                                    fcoe_features[path][port]);
14891                         host_addr = (u32 *) &(ctl->data.register_data.
14892                                               fcoe_features);
14893                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14894                              i += 4)
14895                                 REG_WR(bp, scratch_offset + i,
14896                                        *(host_addr + i/4));
14897                 }
14898                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14899                 break;
14900         }
14901
14902         case DRV_CTL_ULP_UNREGISTER_CMD: {
14903                 int ulp_type = ctl->data.ulp_type;
14904
14905                 if (CHIP_IS_E3(bp)) {
14906                         int idx = BP_FW_MB_IDX(bp);
14907                         u32 cap;
14908
14909                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14910                         if (ulp_type == CNIC_ULP_ISCSI)
14911                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14912                         else if (ulp_type == CNIC_ULP_FCOE)
14913                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14914                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14915                 }
14916                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14917                 break;
14918         }
14919
14920         default:
14921                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14922                 rc = -EINVAL;
14923         }
14924
14925         /* For storage-only interfaces, change driver state */
14926         if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14927                 switch (ctl->drv_state) {
14928                 case DRV_NOP:
14929                         break;
14930                 case DRV_ACTIVE:
14931                         bnx2x_set_os_driver_state(bp,
14932                                                   OS_DRIVER_STATE_ACTIVE);
14933                         break;
14934                 case DRV_INACTIVE:
14935                         bnx2x_set_os_driver_state(bp,
14936                                                   OS_DRIVER_STATE_DISABLED);
14937                         break;
14938                 case DRV_UNLOADED:
14939                         bnx2x_set_os_driver_state(bp,
14940                                                   OS_DRIVER_STATE_NOT_LOADED);
14941                         break;
14942                 default:
14943                 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14944                 }
14945         }
14946
14947         return rc;
14948 }
14949
14950 static int bnx2x_get_fc_npiv(struct net_device *dev,
14951                              struct cnic_fc_npiv_tbl *cnic_tbl)
14952 {
14953         struct bnx2x *bp = netdev_priv(dev);
14954         struct bdn_fc_npiv_tbl *tbl = NULL;
14955         u32 offset, entries;
14956         int rc = -EINVAL;
14957         int i;
14958
14959         if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14960                 goto out;
14961
14962         DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14963
14964         tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14965         if (!tbl) {
14966                 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14967                 goto out;
14968         }
14969
14970         offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14971         if (!offset) {
14972                 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14973                 goto out;
14974         }
14975         DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14976
14977         /* Read the table contents from nvram */
14978         if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14979                 BNX2X_ERR("Failed to read FC-NPIV table\n");
14980                 goto out;
14981         }
14982
14983         /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14984          * the number of entries back to cpu endianness.
14985          */
14986         entries = tbl->fc_npiv_cfg.num_of_npiv;
14987         entries = (__force u32)be32_to_cpu((__force __be32)entries);
14988         tbl->fc_npiv_cfg.num_of_npiv = entries;
14989
14990         if (!tbl->fc_npiv_cfg.num_of_npiv) {
14991                 DP(BNX2X_MSG_MCP,
14992                    "No FC-NPIV table [valid, simply not present]\n");
14993                 goto out;
14994         } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14995                 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14996                           tbl->fc_npiv_cfg.num_of_npiv);
14997                 goto out;
14998         } else {
14999                 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
15000                    tbl->fc_npiv_cfg.num_of_npiv);
15001         }
15002
15003         /* Copy the data into cnic-provided struct */
15004         cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
15005         for (i = 0; i < cnic_tbl->count; i++) {
15006                 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
15007                 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
15008         }
15009
15010         rc = 0;
15011 out:
15012         kfree(tbl);
15013         return rc;
15014 }
15015
15016 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
15017 {
15018         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15019
15020         if (bp->flags & USING_MSIX_FLAG) {
15021                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
15022                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
15023                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
15024         } else {
15025                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
15026                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
15027         }
15028         if (!CHIP_IS_E1x(bp))
15029                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
15030         else
15031                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
15032
15033         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
15034         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
15035         cp->irq_arr[1].status_blk = bp->def_status_blk;
15036         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
15037         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
15038
15039         cp->num_irq = 2;
15040 }
15041
15042 void bnx2x_setup_cnic_info(struct bnx2x *bp)
15043 {
15044         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15045
15046         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15047                              bnx2x_cid_ilt_lines(bp);
15048         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15049         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15050         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15051
15052         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
15053            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
15054            cp->iscsi_l2_cid);
15055
15056         if (NO_ISCSI_OOO(bp))
15057                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15058 }
15059
15060 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
15061                                void *data)
15062 {
15063         struct bnx2x *bp = netdev_priv(dev);
15064         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15065         int rc;
15066
15067         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
15068
15069         if (ops == NULL) {
15070                 BNX2X_ERR("NULL ops received\n");
15071                 return -EINVAL;
15072         }
15073
15074         if (!CNIC_SUPPORT(bp)) {
15075                 BNX2X_ERR("Can't register CNIC when not supported\n");
15076                 return -EOPNOTSUPP;
15077         }
15078
15079         if (!CNIC_LOADED(bp)) {
15080                 rc = bnx2x_load_cnic(bp);
15081                 if (rc) {
15082                         BNX2X_ERR("CNIC-related load failed\n");
15083                         return rc;
15084                 }
15085         }
15086
15087         bp->cnic_enabled = true;
15088
15089         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
15090         if (!bp->cnic_kwq)
15091                 return -ENOMEM;
15092
15093         bp->cnic_kwq_cons = bp->cnic_kwq;
15094         bp->cnic_kwq_prod = bp->cnic_kwq;
15095         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
15096
15097         bp->cnic_spq_pending = 0;
15098         bp->cnic_kwq_pending = 0;
15099
15100         bp->cnic_data = data;
15101
15102         cp->num_irq = 0;
15103         cp->drv_state |= CNIC_DRV_STATE_REGD;
15104         cp->iro_arr = bp->iro_arr;
15105
15106         bnx2x_setup_cnic_irq_info(bp);
15107
15108         rcu_assign_pointer(bp->cnic_ops, ops);
15109
15110         /* Schedule driver to read CNIC driver versions */
15111         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15112
15113         return 0;
15114 }
15115
15116 static int bnx2x_unregister_cnic(struct net_device *dev)
15117 {
15118         struct bnx2x *bp = netdev_priv(dev);
15119         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15120
15121         mutex_lock(&bp->cnic_mutex);
15122         cp->drv_state = 0;
15123         RCU_INIT_POINTER(bp->cnic_ops, NULL);
15124         mutex_unlock(&bp->cnic_mutex);
15125         synchronize_rcu();
15126         bp->cnic_enabled = false;
15127         kfree(bp->cnic_kwq);
15128         bp->cnic_kwq = NULL;
15129
15130         return 0;
15131 }
15132
15133 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
15134 {
15135         struct bnx2x *bp = netdev_priv(dev);
15136         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15137
15138         /* If both iSCSI and FCoE are disabled - return NULL in
15139          * order to indicate CNIC that it should not try to work
15140          * with this device.
15141          */
15142         if (NO_ISCSI(bp) && NO_FCOE(bp))
15143                 return NULL;
15144
15145         cp->drv_owner = THIS_MODULE;
15146         cp->chip_id = CHIP_ID(bp);
15147         cp->pdev = bp->pdev;
15148         cp->io_base = bp->regview;
15149         cp->io_base2 = bp->doorbells;
15150         cp->max_kwqe_pending = 8;
15151         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
15152         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15153                              bnx2x_cid_ilt_lines(bp);
15154         cp->ctx_tbl_len = CNIC_ILT_LINES;
15155         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15156         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15157         cp->drv_ctl = bnx2x_drv_ctl;
15158         cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15159         cp->drv_register_cnic = bnx2x_register_cnic;
15160         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15161         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15162         cp->iscsi_l2_client_id =
15163                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15164         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15165
15166         if (NO_ISCSI_OOO(bp))
15167                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15168
15169         if (NO_ISCSI(bp))
15170                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15171
15172         if (NO_FCOE(bp))
15173                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15174
15175         BNX2X_DEV_INFO(
15176                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15177            cp->ctx_blk_size,
15178            cp->ctx_tbl_offset,
15179            cp->ctx_tbl_len,
15180            cp->starting_cid);
15181         return cp;
15182 }
15183
15184 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15185 {
15186         struct bnx2x *bp = fp->bp;
15187         u32 offset = BAR_USTRORM_INTMEM;
15188
15189         if (IS_VF(bp))
15190                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15191         else if (!CHIP_IS_E1x(bp))
15192                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15193         else
15194                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15195
15196         return offset;
15197 }
15198
15199 /* called only on E1H or E2.
15200  * When pretending to be PF, the pretend value is the function number 0...7
15201  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15202  * combination
15203  */
15204 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15205 {
15206         u32 pretend_reg;
15207
15208         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15209                 return -1;
15210
15211         /* get my own pretend register */
15212         pretend_reg = bnx2x_get_pretend_reg(bp);
15213         REG_WR(bp, pretend_reg, pretend_func_val);
15214         REG_RD(bp, pretend_reg);
15215         return 0;
15216 }
15217
15218 static void bnx2x_ptp_task(struct work_struct *work)
15219 {
15220         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15221         int port = BP_PORT(bp);
15222         u32 val_seq;
15223         u64 timestamp, ns;
15224         struct skb_shared_hwtstamps shhwtstamps;
15225         bool bail = true;
15226         int i;
15227
15228         /* FW may take a while to complete timestamping; try a bit and if it's
15229          * still not complete, may indicate an error state - bail out then.
15230          */
15231         for (i = 0; i < 10; i++) {
15232                 /* Read Tx timestamp registers */
15233                 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15234                                  NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15235                 if (val_seq & 0x10000) {
15236                         bail = false;
15237                         break;
15238                 }
15239                 msleep(1 << i);
15240         }
15241
15242         if (!bail) {
15243                 /* There is a valid timestamp value */
15244                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15245                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15246                 timestamp <<= 32;
15247                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15248                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15249                 /* Reset timestamp register to allow new timestamp */
15250                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15251                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15252                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15253
15254                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15255                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15256                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15257
15258                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15259                    timestamp, ns);
15260         } else {
15261                 DP(BNX2X_MSG_PTP,
15262                    "Tx timestamp is not recorded (register read=%u)\n",
15263                    val_seq);
15264                 bp->eth_stats.ptp_skip_tx_ts++;
15265         }
15266
15267         dev_kfree_skb_any(bp->ptp_tx_skb);
15268         bp->ptp_tx_skb = NULL;
15269 }
15270
15271 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15272 {
15273         int port = BP_PORT(bp);
15274         u64 timestamp, ns;
15275
15276         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15277                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15278         timestamp <<= 32;
15279         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15280                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15281
15282         /* Reset timestamp register to allow new timestamp */
15283         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15284                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15285
15286         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15287
15288         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15289
15290         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15291            timestamp, ns);
15292 }
15293
15294 /* Read the PHC */
15295 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15296 {
15297         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15298         int port = BP_PORT(bp);
15299         u32 wb_data[2];
15300         u64 phc_cycles;
15301
15302         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15303                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15304         phc_cycles = wb_data[1];
15305         phc_cycles = (phc_cycles << 32) + wb_data[0];
15306
15307         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15308
15309         return phc_cycles;
15310 }
15311
15312 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15313 {
15314         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15315         bp->cyclecounter.read = bnx2x_cyclecounter_read;
15316         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15317         bp->cyclecounter.shift = 0;
15318         bp->cyclecounter.mult = 1;
15319 }
15320
15321 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15322 {
15323         struct bnx2x_func_state_params func_params = {NULL};
15324         struct bnx2x_func_set_timesync_params *set_timesync_params =
15325                 &func_params.params.set_timesync;
15326
15327         /* Prepare parameters for function state transitions */
15328         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15329         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15330
15331         func_params.f_obj = &bp->func_obj;
15332         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15333
15334         /* Function parameters */
15335         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15336         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15337
15338         return bnx2x_func_state_change(bp, &func_params);
15339 }
15340
15341 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15342 {
15343         struct bnx2x_queue_state_params q_params;
15344         int rc, i;
15345
15346         /* send queue update ramrod to enable PTP packets */
15347         memset(&q_params, 0, sizeof(q_params));
15348         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15349         q_params.cmd = BNX2X_Q_CMD_UPDATE;
15350         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15351                   &q_params.params.update.update_flags);
15352         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15353                   &q_params.params.update.update_flags);
15354
15355         /* send the ramrod on all the queues of the PF */
15356         for_each_eth_queue(bp, i) {
15357                 struct bnx2x_fastpath *fp = &bp->fp[i];
15358
15359                 /* Set the appropriate Queue object */
15360                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15361
15362                 /* Update the Queue state */
15363                 rc = bnx2x_queue_state_change(bp, &q_params);
15364                 if (rc) {
15365                         BNX2X_ERR("Failed to enable PTP packets\n");
15366                         return rc;
15367                 }
15368         }
15369
15370         return 0;
15371 }
15372
15373 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15374 {
15375         int port = BP_PORT(bp);
15376         int rc;
15377
15378         if (!bp->hwtstamp_ioctl_called)
15379                 return 0;
15380
15381         switch (bp->tx_type) {
15382         case HWTSTAMP_TX_ON:
15383                 bp->flags |= TX_TIMESTAMPING_EN;
15384                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15385                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15386                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15387                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15388                 break;
15389         case HWTSTAMP_TX_ONESTEP_SYNC:
15390                 BNX2X_ERR("One-step timestamping is not supported\n");
15391                 return -ERANGE;
15392         }
15393
15394         switch (bp->rx_filter) {
15395         case HWTSTAMP_FILTER_NONE:
15396                 break;
15397         case HWTSTAMP_FILTER_ALL:
15398         case HWTSTAMP_FILTER_SOME:
15399                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15400                 break;
15401         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15402         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15403         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15404                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15405                 /* Initialize PTP detection for UDP/IPv4 events */
15406                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15407                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15408                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15409                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15410                 break;
15411         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15412         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15413         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15414                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15415                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15416                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15417                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15418                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15419                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15420                 break;
15421         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15422         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15423         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15424                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15425                 /* Initialize PTP detection L2 events */
15426                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15427                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15428                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15429                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15430
15431                 break;
15432         case HWTSTAMP_FILTER_PTP_V2_EVENT:
15433         case HWTSTAMP_FILTER_PTP_V2_SYNC:
15434         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15435                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15436                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15437                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15438                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15439                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15440                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15441                 break;
15442         }
15443
15444         /* Indicate to FW that this PF expects recorded PTP packets */
15445         rc = bnx2x_enable_ptp_packets(bp);
15446         if (rc)
15447                 return rc;
15448
15449         /* Enable sending PTP packets to host */
15450         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15451                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15452
15453         return 0;
15454 }
15455
15456 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15457 {
15458         struct hwtstamp_config config;
15459         int rc;
15460
15461         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15462
15463         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15464                 return -EFAULT;
15465
15466         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15467            config.tx_type, config.rx_filter);
15468
15469         if (config.flags) {
15470                 BNX2X_ERR("config.flags is reserved for future use\n");
15471                 return -EINVAL;
15472         }
15473
15474         bp->hwtstamp_ioctl_called = 1;
15475         bp->tx_type = config.tx_type;
15476         bp->rx_filter = config.rx_filter;
15477
15478         rc = bnx2x_configure_ptp_filters(bp);
15479         if (rc)
15480                 return rc;
15481
15482         config.rx_filter = bp->rx_filter;
15483
15484         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15485                 -EFAULT : 0;
15486 }
15487
15488 /* Configures HW for PTP */
15489 static int bnx2x_configure_ptp(struct bnx2x *bp)
15490 {
15491         int rc, port = BP_PORT(bp);
15492         u32 wb_data[2];
15493
15494         /* Reset PTP event detection rules - will be configured in the IOCTL */
15495         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15496                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15497         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15498                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15499         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15500                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15501         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15502                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15503
15504         /* Disable PTP packets to host - will be configured in the IOCTL*/
15505         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15506                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15507
15508         /* Enable the PTP feature */
15509         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15510                NIG_REG_P0_PTP_EN, 0x3F);
15511
15512         /* Enable the free-running counter */
15513         wb_data[0] = 0;
15514         wb_data[1] = 0;
15515         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15516
15517         /* Reset drift register (offset register is not reset) */
15518         rc = bnx2x_send_reset_timesync_ramrod(bp);
15519         if (rc) {
15520                 BNX2X_ERR("Failed to reset PHC drift register\n");
15521                 return -EFAULT;
15522         }
15523
15524         /* Reset possibly old timestamps */
15525         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15526                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15527         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15528                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15529
15530         return 0;
15531 }
15532
15533 /* Called during load, to initialize PTP-related stuff */
15534 void bnx2x_init_ptp(struct bnx2x *bp)
15535 {
15536         int rc;
15537
15538         /* Configure PTP in HW */
15539         rc = bnx2x_configure_ptp(bp);
15540         if (rc) {
15541                 BNX2X_ERR("Stopping PTP initialization\n");
15542                 return;
15543         }
15544
15545         /* Init work queue for Tx timestamping */
15546         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15547
15548         /* Init cyclecounter and timecounter. This is done only in the first
15549          * load. If done in every load, PTP application will fail when doing
15550          * unload / load (e.g. MTU change) while it is running.
15551          */
15552         if (!bp->timecounter_init_done) {
15553                 bnx2x_init_cyclecounter(bp);
15554                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15555                                  ktime_to_ns(ktime_get_real()));
15556                 bp->timecounter_init_done = 1;
15557         }
15558
15559         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15560 }