drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <linux/rtc.h>
  36 #include <net/ip.h>
  37 #include <net/tcp.h>
  38 #include <net/udp.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <net/udp_tunnel.h>
  42 #ifdef CONFIG_NET_RX_BUSY_POLL
  43 #include <net/busy_poll.h>
  44 #endif
  45 #include <linux/workqueue.h>
  46 #include <linux/prefetch.h>
  47 #include <linux/cache.h>
  48 #include <linux/log2.h>
  49 #include <linux/aer.h>
  50 #include <linux/bitmap.h>
  51 #include <linux/cpu_rmap.h>
  52
  53 #include "bnxt_hsi.h"
  54 #include "bnxt.h"
  55 #include "bnxt_sriov.h"
  56 #include "bnxt_ethtool.h"
  57
  58 #define BNXT_TX_TIMEOUT         (5 * HZ)
  59
  60 static const char version[] =
  61         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  62
  63 MODULE_LICENSE("GPL");
  64 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  65 MODULE_VERSION(DRV_MODULE_VERSION);
  66
  67 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  68 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  69 #define BNXT_RX_COPY_THRESH 256
  70
  71 #define BNXT_TX_PUSH_THRESH 164
  72
  73 enum board_idx {
  74         BCM57301,
  75         BCM57302,
  76         BCM57304,
  77         BCM57417_NPAR,
  78         BCM58700,
  79         BCM57311,
  80         BCM57312,
  81         BCM57402,
  82         BCM57404,
  83         BCM57406,
  84         BCM57402_NPAR,
  85         BCM57407,
  86         BCM57412,
  87         BCM57414,
  88         BCM57416,
  89         BCM57417,
  90         BCM57412_NPAR,
  91         BCM57314,
  92         BCM57417_SFP,
  93         BCM57416_SFP,
  94         BCM57404_NPAR,
  95         BCM57406_NPAR,
  96         BCM57407_SFP,
  97         BCM57407_NPAR,
  98         BCM57414_NPAR,
  99         BCM57416_NPAR,
 100         NETXTREME_E_VF,
 101         NETXTREME_C_VF,
 102 };
 103
 104 /* indexed by enum above */
 105 static const struct {
 106         char *name;
 107 } board_info[] = {
 108         { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 109         { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 110         { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 111         { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 112         { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 113         { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 114         { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 115         { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 116         { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 117         { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 118         { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 119         { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 120         { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 121         { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 122         { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 123         { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 124         { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 125         { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 126         { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 127         { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 128         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 129         { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 130         { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 131         { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 132         { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 133         { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 134         { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 135         { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 136 };
 137
 138 static const struct pci_device_id bnxt_pci_tbl[] = {
 139         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 140         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 141         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 142         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 143         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 144         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 145         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 146         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 147         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 148         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 149         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 150         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 151         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 152         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 155         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 156         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 157         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 158         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 159         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 160         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 161         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 162         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 163         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 164         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 166         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 169 #ifdef CONFIG_BNXT_SRIOV
 170         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 171         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 172         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 173         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 174         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 175         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 176 #endif
 177         { 0 }
 178 };
 179
 180 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 181
 182 static const u16 bnxt_vf_req_snif[] = {
 183         HWRM_FUNC_CFG,
 184         HWRM_PORT_PHY_QCFG,
 185         HWRM_CFA_L2_FILTER_ALLOC,
 186 };
 187
 188 static const u16 bnxt_async_events_arr[] = {
 189         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 190         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 191         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 192         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 193         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 194 };
 195
 196 static bool bnxt_vf_pciid(enum board_idx idx)
 197 {
 198         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
 199 }
 200
 201 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 202 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 203 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 204
 205 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 206                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 207
 208 #define BNXT_CP_DB(db, raw_cons)                                        \
 209                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 210
 211 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 212                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 213
 214 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 215 {
 216         /* Tell compiler to fetch tx indices from memory. */
 217         barrier();
 218
 219         return bp->tx_ring_size -
 220                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 221 }
 222
 223 static const u16 bnxt_lhint_arr[] = {
 224         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 225         TX_BD_FLAGS_LHINT_512_TO_1023,
 226         TX_BD_FLAGS_LHINT_1024_TO_2047,
 227         TX_BD_FLAGS_LHINT_1024_TO_2047,
 228         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 229         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 230         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 231         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 232         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 233         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 234         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 235         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 236         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 237         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 238         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 239         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 240         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 241         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 242         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 243 };
 244
 245 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 246 {
 247         struct bnxt *bp = netdev_priv(dev);
 248         struct tx_bd *txbd;
 249         struct tx_bd_ext *txbd1;
 250         struct netdev_queue *txq;
 251         int i;
 252         dma_addr_t mapping;
 253         unsigned int length, pad = 0;
 254         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 255         u16 prod, last_frag;
 256         struct pci_dev *pdev = bp->pdev;
 257         struct bnxt_tx_ring_info *txr;
 258         struct bnxt_sw_tx_bd *tx_buf;
 259
 260         i = skb_get_queue_mapping(skb);
 261         if (unlikely(i >= bp->tx_nr_rings)) {
 262                 dev_kfree_skb_any(skb);
 263                 return NETDEV_TX_OK;
 264         }
 265
 266         txr = &bp->tx_ring[i];
 267         txq = netdev_get_tx_queue(dev, i);
 268         prod = txr->tx_prod;
 269
 270         free_size = bnxt_tx_avail(bp, txr);
 271         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 272                 netif_tx_stop_queue(txq);
 273                 return NETDEV_TX_BUSY;
 274         }
 275
 276         length = skb->len;
 277         len = skb_headlen(skb);
 278         last_frag = skb_shinfo(skb)->nr_frags;
 279
 280         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 281
 282         txbd->tx_bd_opaque = prod;
 283
 284         tx_buf = &txr->tx_buf_ring[prod];
 285         tx_buf->skb = skb;
 286         tx_buf->nr_frags = last_frag;
 287
 288         vlan_tag_flags = 0;
 289         cfa_action = 0;
 290         if (skb_vlan_tag_present(skb)) {
 291                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 292                                  skb_vlan_tag_get(skb);
 293                 /* Currently supports 8021Q, 8021AD vlan offloads
 294                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 295                  */
 296                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 297                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 298         }
 299
 300         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 301                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 302                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 303                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 304                 void *pdata = tx_push_buf->data;
 305                 u64 *end;
 306                 int j, push_len;
 307
 308                 /* Set COAL_NOW to be ready quickly for the next push */
 309                 tx_push->tx_bd_len_flags_type =
 310                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 311                                         TX_BD_TYPE_LONG_TX_BD |
 312                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 313                                         TX_BD_FLAGS_COAL_NOW |
 314                                         TX_BD_FLAGS_PACKET_END |
 315                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 316
 317                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 318                         tx_push1->tx_bd_hsize_lflags =
 319                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 320                 else
 321                         tx_push1->tx_bd_hsize_lflags = 0;
 322
 323                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 324                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 325
 326                 end = pdata + length;
 327                 end = PTR_ALIGN(end, 8) - 1;
 328                 *end = 0;
 329
 330                 skb_copy_from_linear_data(skb, pdata, len);
 331                 pdata += len;
 332                 for (j = 0; j < last_frag; j++) {
 333                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 334                         void *fptr;
 335
 336                         fptr = skb_frag_address_safe(frag);
 337                         if (!fptr)
 338                                 goto normal_tx;
 339
 340                         memcpy(pdata, fptr, skb_frag_size(frag));
 341                         pdata += skb_frag_size(frag);
 342                 }
 343
 344                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 345                 txbd->tx_bd_haddr = txr->data_mapping;
 346                 prod = NEXT_TX(prod);
 347                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 348                 memcpy(txbd, tx_push1, sizeof(*txbd));
 349                 prod = NEXT_TX(prod);
 350                 tx_push->doorbell =
 351                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 352                 txr->tx_prod = prod;
 353
 354                 tx_buf->is_push = 1;
 355                 netdev_tx_sent_queue(txq, skb->len);
 356                 wmb();  /* Sync is_push and byte queue before pushing data */
 357
 358                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 359                 if (push_len > 16) {
 360                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 361                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 362                                          (push_len - 16) << 1);
 363                 } else {
 364                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 365                                          push_len);
 366                 }
 367
 368                 goto tx_done;
 369         }
 370
 371 normal_tx:
 372         if (length < BNXT_MIN_PKT_SIZE) {
 373                 pad = BNXT_MIN_PKT_SIZE - length;
 374                 if (skb_pad(skb, pad)) {
 375                         /* SKB already freed. */
 376                         tx_buf->skb = NULL;
 377                         return NETDEV_TX_OK;
 378                 }
 379                 length = BNXT_MIN_PKT_SIZE;
 380         }
 381
 382         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 383
 384         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 385                 dev_kfree_skb_any(skb);
 386                 tx_buf->skb = NULL;
 387                 return NETDEV_TX_OK;
 388         }
 389
 390         dma_unmap_addr_set(tx_buf, mapping, mapping);
 391         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 392                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 393
 394         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 395
 396         prod = NEXT_TX(prod);
 397         txbd1 = (struct tx_bd_ext *)
 398                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 399
 400         txbd1->tx_bd_hsize_lflags = 0;
 401         if (skb_is_gso(skb)) {
 402                 u32 hdr_len;
 403
 404                 if (skb->encapsulation)
 405                         hdr_len = skb_inner_network_offset(skb) +
 406                                 skb_inner_network_header_len(skb) +
 407                                 inner_tcp_hdrlen(skb);
 408                 else
 409                         hdr_len = skb_transport_offset(skb) +
 410                                 tcp_hdrlen(skb);
 411
 412                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 413                                         TX_BD_FLAGS_T_IPID |
 414                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 415                 length = skb_shinfo(skb)->gso_size;
 416                 txbd1->tx_bd_mss = cpu_to_le32(length);
 417                 length += hdr_len;
 418         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 419                 txbd1->tx_bd_hsize_lflags =
 420                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 421                 txbd1->tx_bd_mss = 0;
 422         }
 423
 424         length >>= 9;
 425         flags |= bnxt_lhint_arr[length];
 426         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 427
 428         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 429         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 430         for (i = 0; i < last_frag; i++) {
 431                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 432
 433                 prod = NEXT_TX(prod);
 434                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 435
 436                 len = skb_frag_size(frag);
 437                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 438                                            DMA_TO_DEVICE);
 439
 440                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 441                         goto tx_dma_error;
 442
 443                 tx_buf = &txr->tx_buf_ring[prod];
 444                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 445
 446                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 447
 448                 flags = len << TX_BD_LEN_SHIFT;
 449                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 450         }
 451
 452         flags &= ~TX_BD_LEN;
 453         txbd->tx_bd_len_flags_type =
 454                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 455                             TX_BD_FLAGS_PACKET_END);
 456
 457         netdev_tx_sent_queue(txq, skb->len);
 458
 459         /* Sync BD data before updating doorbell */
 460         wmb();
 461
 462         prod = NEXT_TX(prod);
 463         txr->tx_prod = prod;
 464
 465         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 466         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 467
 468 tx_done:
 469
 470         mmiowb();
 471
 472         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 473                 netif_tx_stop_queue(txq);
 474
 475                 /* netif_tx_stop_queue() must be done before checking
 476                  * tx index in bnxt_tx_avail() below, because in
 477                  * bnxt_tx_int(), we update tx index before checking for
 478                  * netif_tx_queue_stopped().
 479                  */
 480                 smp_mb();
 481                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 482                         netif_tx_wake_queue(txq);
 483         }
 484         return NETDEV_TX_OK;
 485
 486 tx_dma_error:
 487         last_frag = i;
 488
 489         /* start back at beginning and unmap skb */
 490         prod = txr->tx_prod;
 491         tx_buf = &txr->tx_buf_ring[prod];
 492         tx_buf->skb = NULL;
 493         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 494                          skb_headlen(skb), PCI_DMA_TODEVICE);
 495         prod = NEXT_TX(prod);
 496
 497         /* unmap remaining mapped pages */
 498         for (i = 0; i < last_frag; i++) {
 499                 prod = NEXT_TX(prod);
 500                 tx_buf = &txr->tx_buf_ring[prod];
 501                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 502                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 503                                PCI_DMA_TODEVICE);
 504         }
 505
 506         dev_kfree_skb_any(skb);
 507         return NETDEV_TX_OK;
 508 }
 509
 510 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 511 {
 512         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 513         int index = txr - &bp->tx_ring[0];
 514         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 515         u16 cons = txr->tx_cons;
 516         struct pci_dev *pdev = bp->pdev;
 517         int i;
 518         unsigned int tx_bytes = 0;
 519
 520         for (i = 0; i < nr_pkts; i++) {
 521                 struct bnxt_sw_tx_bd *tx_buf;
 522                 struct sk_buff *skb;
 523                 int j, last;
 524
 525                 tx_buf = &txr->tx_buf_ring[cons];
 526                 cons = NEXT_TX(cons);
 527                 skb = tx_buf->skb;
 528                 tx_buf->skb = NULL;
 529
 530                 if (tx_buf->is_push) {
 531                         tx_buf->is_push = 0;
 532                         goto next_tx_int;
 533                 }
 534
 535                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 536                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 537                 last = tx_buf->nr_frags;
 538
 539                 for (j = 0; j < last; j++) {
 540                         cons = NEXT_TX(cons);
 541                         tx_buf = &txr->tx_buf_ring[cons];
 542                         dma_unmap_page(
 543                                 &pdev->dev,
 544                                 dma_unmap_addr(tx_buf, mapping),
 545                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 546                                 PCI_DMA_TODEVICE);
 547                 }
 548
 549 next_tx_int:
 550                 cons = NEXT_TX(cons);
 551
 552                 tx_bytes += skb->len;
 553                 dev_kfree_skb_any(skb);
 554         }
 555
 556         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 557         txr->tx_cons = cons;
 558
 559         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 560          * before checking for netif_tx_queue_stopped().  Without the
 561          * memory barrier, there is a small possibility that bnxt_start_xmit()
 562          * will miss it and cause the queue to be stopped forever.
 563          */
 564         smp_mb();
 565
 566         if (unlikely(netif_tx_queue_stopped(txq)) &&
 567             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 568                 __netif_tx_lock(txq, smp_processor_id());
 569                 if (netif_tx_queue_stopped(txq) &&
 570                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 571                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 572                         netif_tx_wake_queue(txq);
 573                 __netif_tx_unlock(txq);
 574         }
 575 }
 576
 577 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 578                                        gfp_t gfp)
 579 {
 580         u8 *data;
 581         struct pci_dev *pdev = bp->pdev;
 582
 583         data = kmalloc(bp->rx_buf_size, gfp);
 584         if (!data)
 585                 return NULL;
 586
 587         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 588                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 589
 590         if (dma_mapping_error(&pdev->dev, *mapping)) {
 591                 kfree(data);
 592                 data = NULL;
 593         }
 594         return data;
 595 }
 596
 597 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 598                                      struct bnxt_rx_ring_info *rxr,
 599                                      u16 prod, gfp_t gfp)
 600 {
 601         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 602         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 603         u8 *data;
 604         dma_addr_t mapping;
 605
 606         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 607         if (!data)
 608                 return -ENOMEM;
 609
 610         rx_buf->data = data;
 611         dma_unmap_addr_set(rx_buf, mapping, mapping);
 612
 613         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 614
 615         return 0;
 616 }
 617
 618 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 619                                u8 *data)
 620 {
 621         u16 prod = rxr->rx_prod;
 622         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 623         struct rx_bd *cons_bd, *prod_bd;
 624
 625         prod_rx_buf = &rxr->rx_buf_ring[prod];
 626         cons_rx_buf = &rxr->rx_buf_ring[cons];
 627
 628         prod_rx_buf->data = data;
 629
 630         dma_unmap_addr_set(prod_rx_buf, mapping,
 631                            dma_unmap_addr(cons_rx_buf, mapping));
 632
 633         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 634         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 635
 636         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 637 }
 638
 639 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 640 {
 641         u16 next, max = rxr->rx_agg_bmap_size;
 642
 643         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 644         if (next >= max)
 645                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 646         return next;
 647 }
 648
 649 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 650                                      struct bnxt_rx_ring_info *rxr,
 651                                      u16 prod, gfp_t gfp)
 652 {
 653         struct rx_bd *rxbd =
 654                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 655         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 656         struct pci_dev *pdev = bp->pdev;
 657         struct page *page;
 658         dma_addr_t mapping;
 659         u16 sw_prod = rxr->rx_sw_agg_prod;
 660         unsigned int offset = 0;
 661
 662         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 663                 page = rxr->rx_page;
 664                 if (!page) {
 665                         page = alloc_page(gfp);
 666                         if (!page)
 667                                 return -ENOMEM;
 668                         rxr->rx_page = page;
 669                         rxr->rx_page_offset = 0;
 670                 }
 671                 offset = rxr->rx_page_offset;
 672                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 673                 if (rxr->rx_page_offset == PAGE_SIZE)
 674                         rxr->rx_page = NULL;
 675                 else
 676                         get_page(page);
 677         } else {
 678                 page = alloc_page(gfp);
 679                 if (!page)
 680                         return -ENOMEM;
 681         }
 682
 683         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 684                                PCI_DMA_FROMDEVICE);
 685         if (dma_mapping_error(&pdev->dev, mapping)) {
 686                 __free_page(page);
 687                 return -EIO;
 688         }
 689
 690         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 691                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 692
 693         __set_bit(sw_prod, rxr->rx_agg_bmap);
 694         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 695         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 696
 697         rx_agg_buf->page = page;
 698         rx_agg_buf->offset = offset;
 699         rx_agg_buf->mapping = mapping;
 700         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 701         rxbd->rx_bd_opaque = sw_prod;
 702         return 0;
 703 }
 704
 705 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 706                                    u32 agg_bufs)
 707 {
 708         struct bnxt *bp = bnapi->bp;
 709         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 710         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 711         u16 prod = rxr->rx_agg_prod;
 712         u16 sw_prod = rxr->rx_sw_agg_prod;
 713         u32 i;
 714
 715         for (i = 0; i < agg_bufs; i++) {
 716                 u16 cons;
 717                 struct rx_agg_cmp *agg;
 718                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 719                 struct rx_bd *prod_bd;
 720                 struct page *page;
 721
 722                 agg = (struct rx_agg_cmp *)
 723                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 724                 cons = agg->rx_agg_cmp_opaque;
 725                 __clear_bit(cons, rxr->rx_agg_bmap);
 726
 727                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 728                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 729
 730                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 731                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 732                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 733
 734                 /* It is possible for sw_prod to be equal to cons, so
 735                  * set cons_rx_buf->page to NULL first.
 736                  */
 737                 page = cons_rx_buf->page;
 738                 cons_rx_buf->page = NULL;
 739                 prod_rx_buf->page = page;
 740                 prod_rx_buf->offset = cons_rx_buf->offset;
 741
 742                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 743
 744                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 745
 746                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 747                 prod_bd->rx_bd_opaque = sw_prod;
 748
 749                 prod = NEXT_RX_AGG(prod);
 750                 sw_prod = NEXT_RX_AGG(sw_prod);
 751                 cp_cons = NEXT_CMP(cp_cons);
 752         }
 753         rxr->rx_agg_prod = prod;
 754         rxr->rx_sw_agg_prod = sw_prod;
 755 }
 756
 757 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 758                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 759                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 760                                    unsigned int len)
 761 {
 762         int err;
 763         struct sk_buff *skb;
 764
 765         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 766         if (unlikely(err)) {
 767                 bnxt_reuse_rx_data(rxr, cons, data);
 768                 return NULL;
 769         }
 770
 771         skb = build_skb(data, 0);
 772         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 773                          PCI_DMA_FROMDEVICE);
 774         if (!skb) {
 775                 kfree(data);
 776                 return NULL;
 777         }
 778
 779         skb_reserve(skb, BNXT_RX_OFFSET);
 780         skb_put(skb, len);
 781         return skb;
 782 }
 783
 784 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 785                                      struct sk_buff *skb, u16 cp_cons,
 786                                      u32 agg_bufs)
 787 {
 788         struct pci_dev *pdev = bp->pdev;
 789         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 790         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 791         u16 prod = rxr->rx_agg_prod;
 792         u32 i;
 793
 794         for (i = 0; i < agg_bufs; i++) {
 795                 u16 cons, frag_len;
 796                 struct rx_agg_cmp *agg;
 797                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 798                 struct page *page;
 799                 dma_addr_t mapping;
 800
 801                 agg = (struct rx_agg_cmp *)
 802                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 803                 cons = agg->rx_agg_cmp_opaque;
 804                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 805                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 806
 807                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 808                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 809                                    cons_rx_buf->offset, frag_len);
 810                 __clear_bit(cons, rxr->rx_agg_bmap);
 811
 812                 /* It is possible for bnxt_alloc_rx_page() to allocate
 813                  * a sw_prod index that equals the cons index, so we
 814                  * need to clear the cons entry now.
 815                  */
 816                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 817                 page = cons_rx_buf->page;
 818                 cons_rx_buf->page = NULL;
 819
 820                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 821                         struct skb_shared_info *shinfo;
 822                         unsigned int nr_frags;
 823
 824                         shinfo = skb_shinfo(skb);
 825                         nr_frags = --shinfo->nr_frags;
 826                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 827
 828                         dev_kfree_skb(skb);
 829
 830                         cons_rx_buf->page = page;
 831
 832                         /* Update prod since possibly some pages have been
 833                          * allocated already.
 834                          */
 835                         rxr->rx_agg_prod = prod;
 836                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 837                         return NULL;
 838                 }
 839
 840                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 841                                PCI_DMA_FROMDEVICE);
 842
 843                 skb->data_len += frag_len;
 844                 skb->len += frag_len;
 845                 skb->truesize += PAGE_SIZE;
 846
 847                 prod = NEXT_RX_AGG(prod);
 848                 cp_cons = NEXT_CMP(cp_cons);
 849         }
 850         rxr->rx_agg_prod = prod;
 851         return skb;
 852 }
 853
 854 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 855                                u8 agg_bufs, u32 *raw_cons)
 856 {
 857         u16 last;
 858         struct rx_agg_cmp *agg;
 859
 860         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 861         last = RING_CMP(*raw_cons);
 862         agg = (struct rx_agg_cmp *)
 863                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 864         return RX_AGG_CMP_VALID(agg, *raw_cons);
 865 }
 866
 867 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 868                                             unsigned int len,
 869                                             dma_addr_t mapping)
 870 {
 871         struct bnxt *bp = bnapi->bp;
 872         struct pci_dev *pdev = bp->pdev;
 873         struct sk_buff *skb;
 874
 875         skb = napi_alloc_skb(&bnapi->napi, len);
 876         if (!skb)
 877                 return NULL;
 878
 879         dma_sync_single_for_cpu(&pdev->dev, mapping,
 880                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 881
 882         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 883
 884         dma_sync_single_for_device(&pdev->dev, mapping,
 885                                    bp->rx_copy_thresh,
 886                                    PCI_DMA_FROMDEVICE);
 887
 888         skb_put(skb, len);
 889         return skb;
 890 }
 891
 892 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 893                            u32 *raw_cons, void *cmp)
 894 {
 895         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 896         struct rx_cmp *rxcmp = cmp;
 897         u32 tmp_raw_cons = *raw_cons;
 898         u8 cmp_type, agg_bufs = 0;
 899
 900         cmp_type = RX_CMP_TYPE(rxcmp);
 901
 902         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 903                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 904                             RX_CMP_AGG_BUFS) >>
 905                            RX_CMP_AGG_BUFS_SHIFT;
 906         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 907                 struct rx_tpa_end_cmp *tpa_end = cmp;
 908
 909                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 910                             RX_TPA_END_CMP_AGG_BUFS) >>
 911                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 912         }
 913
 914         if (agg_bufs) {
 915                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 916                         return -EBUSY;
 917         }
 918         *raw_cons = tmp_raw_cons;
 919         return 0;
 920 }
 921
 922 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 923 {
 924         if (!rxr->bnapi->in_reset) {
 925                 rxr->bnapi->in_reset = true;
 926                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
 927                 schedule_work(&bp->sp_task);
 928         }
 929         rxr->rx_next_cons = 0xffff;
 930 }
 931
 932 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 933                            struct rx_tpa_start_cmp *tpa_start,
 934                            struct rx_tpa_start_cmp_ext *tpa_start1)
 935 {
 936         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 937         u16 cons, prod;
 938         struct bnxt_tpa_info *tpa_info;
 939         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 940         struct rx_bd *prod_bd;
 941         dma_addr_t mapping;
 942
 943         cons = tpa_start->rx_tpa_start_cmp_opaque;
 944         prod = rxr->rx_prod;
 945         cons_rx_buf = &rxr->rx_buf_ring[cons];
 946         prod_rx_buf = &rxr->rx_buf_ring[prod];
 947         tpa_info = &rxr->rx_tpa[agg_id];
 948
 949         if (unlikely(cons != rxr->rx_next_cons)) {
 950                 bnxt_sched_reset(bp, rxr);
 951                 return;
 952         }
 953
 954         prod_rx_buf->data = tpa_info->data;
 955
 956         mapping = tpa_info->mapping;
 957         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 958
 959         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 960
 961         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 962
 963         tpa_info->data = cons_rx_buf->data;
 964         cons_rx_buf->data = NULL;
 965         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 966
 967         tpa_info->len =
 968                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 969                                 RX_TPA_START_CMP_LEN_SHIFT;
 970         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 971                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 972
 973                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 974                 tpa_info->gso_type = SKB_GSO_TCPV4;
 975                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 976                 if (hash_type == 3)
 977                         tpa_info->gso_type = SKB_GSO_TCPV6;
 978                 tpa_info->rss_hash =
 979                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 980         } else {
 981                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 982                 tpa_info->gso_type = 0;
 983                 if (netif_msg_rx_err(bp))
 984                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 985         }
 986         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 987         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 988         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
 989
 990         rxr->rx_prod = NEXT_RX(prod);
 991         cons = NEXT_RX(cons);
 992         rxr->rx_next_cons = NEXT_RX(cons);
 993         cons_rx_buf = &rxr->rx_buf_ring[cons];
 994
 995         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 996         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 997         cons_rx_buf->data = NULL;
 998 }
 999
1000 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1001                            u16 cp_cons, u32 agg_bufs)
1002 {
1003         if (agg_bufs)
1004                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1005 }
1006
1007 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1008                                            int payload_off, int tcp_ts,
1009                                            struct sk_buff *skb)
1010 {
1011 #ifdef CONFIG_INET
1012         struct tcphdr *th;
1013         int len, nw_off;
1014         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1015         u32 hdr_info = tpa_info->hdr_info;
1016         bool loopback = false;
1017
1018         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1019         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1020         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1021
1022         /* If the packet is an internal loopback packet, the offsets will
1023          * have an extra 4 bytes.
1024          */
1025         if (inner_mac_off == 4) {
1026                 loopback = true;
1027         } else if (inner_mac_off > 4) {
1028                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1029                                             ETH_HLEN - 2));
1030
1031                 /* We only support inner iPv4/ipv6.  If we don't see the
1032                  * correct protocol ID, it must be a loopback packet where
1033                  * the offsets are off by 4.
1034                  */
1035                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1036                         loopback = true;
1037         }
1038         if (loopback) {
1039                 /* internal loopback packet, subtract all offsets by 4 */
1040                 inner_ip_off -= 4;
1041                 inner_mac_off -= 4;
1042                 outer_ip_off -= 4;
1043         }
1044
1045         nw_off = inner_ip_off - ETH_HLEN;
1046         skb_set_network_header(skb, nw_off);
1047         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1048                 struct ipv6hdr *iph = ipv6_hdr(skb);
1049
1050                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1051                 len = skb->len - skb_transport_offset(skb);
1052                 th = tcp_hdr(skb);
1053                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1054         } else {
1055                 struct iphdr *iph = ip_hdr(skb);
1056
1057                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1058                 len = skb->len - skb_transport_offset(skb);
1059                 th = tcp_hdr(skb);
1060                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1061         }
1062
1063         if (inner_mac_off) { /* tunnel */
1064                 struct udphdr *uh = NULL;
1065                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1066                                             ETH_HLEN - 2));
1067
1068                 if (proto == htons(ETH_P_IP)) {
1069                         struct iphdr *iph = (struct iphdr *)skb->data;
1070
1071                         if (iph->protocol == IPPROTO_UDP)
1072                                 uh = (struct udphdr *)(iph + 1);
1073                 } else {
1074                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1075
1076                         if (iph->nexthdr == IPPROTO_UDP)
1077                                 uh = (struct udphdr *)(iph + 1);
1078                 }
1079                 if (uh) {
1080                         if (uh->check)
1081                                 skb_shinfo(skb)->gso_type |=
1082                                         SKB_GSO_UDP_TUNNEL_CSUM;
1083                         else
1084                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1085                 }
1086         }
1087 #endif
1088         return skb;
1089 }
1090
1091 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1092 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1093
1094 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1095                                            int payload_off, int tcp_ts,
1096                                            struct sk_buff *skb)
1097 {
1098 #ifdef CONFIG_INET
1099         struct tcphdr *th;
1100         int len, nw_off, tcp_opt_len;
1101
1102         if (tcp_ts)
1103                 tcp_opt_len = 12;
1104
1105         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1106                 struct iphdr *iph;
1107
1108                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1109                          ETH_HLEN;
1110                 skb_set_network_header(skb, nw_off);
1111                 iph = ip_hdr(skb);
1112                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1113                 len = skb->len - skb_transport_offset(skb);
1114                 th = tcp_hdr(skb);
1115                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1116         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1117                 struct ipv6hdr *iph;
1118
1119                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1120                          ETH_HLEN;
1121                 skb_set_network_header(skb, nw_off);
1122                 iph = ipv6_hdr(skb);
1123                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1124                 len = skb->len - skb_transport_offset(skb);
1125                 th = tcp_hdr(skb);
1126                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1127         } else {
1128                 dev_kfree_skb_any(skb);
1129                 return NULL;
1130         }
1131         tcp_gro_complete(skb);
1132
1133         if (nw_off) { /* tunnel */
1134                 struct udphdr *uh = NULL;
1135
1136                 if (skb->protocol == htons(ETH_P_IP)) {
1137                         struct iphdr *iph = (struct iphdr *)skb->data;
1138
1139                         if (iph->protocol == IPPROTO_UDP)
1140                                 uh = (struct udphdr *)(iph + 1);
1141                 } else {
1142                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1143
1144                         if (iph->nexthdr == IPPROTO_UDP)
1145                                 uh = (struct udphdr *)(iph + 1);
1146                 }
1147                 if (uh) {
1148                         if (uh->check)
1149                                 skb_shinfo(skb)->gso_type |=
1150                                         SKB_GSO_UDP_TUNNEL_CSUM;
1151                         else
1152                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1153                 }
1154         }
1155 #endif
1156         return skb;
1157 }
1158
1159 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1160                                            struct bnxt_tpa_info *tpa_info,
1161                                            struct rx_tpa_end_cmp *tpa_end,
1162                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1163                                            struct sk_buff *skb)
1164 {
1165 #ifdef CONFIG_INET
1166         int payload_off;
1167         u16 segs;
1168
1169         segs = TPA_END_TPA_SEGS(tpa_end);
1170         if (segs == 1)
1171                 return skb;
1172
1173         NAPI_GRO_CB(skb)->count = segs;
1174         skb_shinfo(skb)->gso_size =
1175                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1176         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1177         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1178                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1179                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1180         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1181 #endif
1182         return skb;
1183 }
1184
1185 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1186                                            struct bnxt_napi *bnapi,
1187                                            u32 *raw_cons,
1188                                            struct rx_tpa_end_cmp *tpa_end,
1189                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1190                                            bool *agg_event)
1191 {
1192         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1193         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1194         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1195         u8 *data, agg_bufs;
1196         u16 cp_cons = RING_CMP(*raw_cons);
1197         unsigned int len;
1198         struct bnxt_tpa_info *tpa_info;
1199         dma_addr_t mapping;
1200         struct sk_buff *skb;
1201
1202         if (unlikely(bnapi->in_reset)) {
1203                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1204
1205                 if (rc < 0)
1206                         return ERR_PTR(-EBUSY);
1207                 return NULL;
1208         }
1209
1210         tpa_info = &rxr->rx_tpa[agg_id];
1211         data = tpa_info->data;
1212         prefetch(data);
1213         len = tpa_info->len;
1214         mapping = tpa_info->mapping;
1215
1216         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1217                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1218
1219         if (agg_bufs) {
1220                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1221                         return ERR_PTR(-EBUSY);
1222
1223                 *agg_event = true;
1224                 cp_cons = NEXT_CMP(cp_cons);
1225         }
1226
1227         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1228                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1229                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1230                             agg_bufs, (int)MAX_SKB_FRAGS);
1231                 return NULL;
1232         }
1233
1234         if (len <= bp->rx_copy_thresh) {
1235                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1236                 if (!skb) {
1237                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1238                         return NULL;
1239                 }
1240         } else {
1241                 u8 *new_data;
1242                 dma_addr_t new_mapping;
1243
1244                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1245                 if (!new_data) {
1246                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1247                         return NULL;
1248                 }
1249
1250                 tpa_info->data = new_data;
1251                 tpa_info->mapping = new_mapping;
1252
1253                 skb = build_skb(data, 0);
1254                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1255                                  PCI_DMA_FROMDEVICE);
1256
1257                 if (!skb) {
1258                         kfree(data);
1259                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1260                         return NULL;
1261                 }
1262                 skb_reserve(skb, BNXT_RX_OFFSET);
1263                 skb_put(skb, len);
1264         }
1265
1266         if (agg_bufs) {
1267                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1268                 if (!skb) {
1269                         /* Page reuse already handled by bnxt_rx_pages(). */
1270                         return NULL;
1271                 }
1272         }
1273         skb->protocol = eth_type_trans(skb, bp->dev);
1274
1275         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1276                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1277
1278         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1279             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1280                 u16 vlan_proto = tpa_info->metadata >>
1281                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1282                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1283
1284                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1285         }
1286
1287         skb_checksum_none_assert(skb);
1288         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1289                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1290                 skb->csum_level =
1291                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1292         }
1293
1294         if (TPA_END_GRO(tpa_end))
1295                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1296
1297         return skb;
1298 }
1299
1300 /* returns the following:
1301  * 1       - 1 packet successfully received
1302  * 0       - successful TPA_START, packet not completed yet
1303  * -EBUSY  - completion ring does not have all the agg buffers yet
1304  * -ENOMEM - packet aborted due to out of memory
1305  * -EIO    - packet aborted due to hw error indicated in BD
1306  */
1307 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1308                        bool *agg_event)
1309 {
1310         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1311         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1312         struct net_device *dev = bp->dev;
1313         struct rx_cmp *rxcmp;
1314         struct rx_cmp_ext *rxcmp1;
1315         u32 tmp_raw_cons = *raw_cons;
1316         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1317         struct bnxt_sw_rx_bd *rx_buf;
1318         unsigned int len;
1319         u8 *data, agg_bufs, cmp_type;
1320         dma_addr_t dma_addr;
1321         struct sk_buff *skb;
1322         int rc = 0;
1323
1324         rxcmp = (struct rx_cmp *)
1325                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1326
1327         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1328         cp_cons = RING_CMP(tmp_raw_cons);
1329         rxcmp1 = (struct rx_cmp_ext *)
1330                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1331
1332         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1333                 return -EBUSY;
1334
1335         cmp_type = RX_CMP_TYPE(rxcmp);
1336
1337         prod = rxr->rx_prod;
1338
1339         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1340                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1341                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1342
1343                 goto next_rx_no_prod;
1344
1345         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1346                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1347                                    (struct rx_tpa_end_cmp *)rxcmp,
1348                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1349                                    agg_event);
1350
1351                 if (unlikely(IS_ERR(skb)))
1352                         return -EBUSY;
1353
1354                 rc = -ENOMEM;
1355                 if (likely(skb)) {
1356                         skb_record_rx_queue(skb, bnapi->index);
1357                         skb_mark_napi_id(skb, &bnapi->napi);
1358                         if (bnxt_busy_polling(bnapi))
1359                                 netif_receive_skb(skb);
1360                         else
1361                                 napi_gro_receive(&bnapi->napi, skb);
1362                         rc = 1;
1363                 }
1364                 goto next_rx_no_prod;
1365         }
1366
1367         cons = rxcmp->rx_cmp_opaque;
1368         rx_buf = &rxr->rx_buf_ring[cons];
1369         data = rx_buf->data;
1370         if (unlikely(cons != rxr->rx_next_cons)) {
1371                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1372
1373                 bnxt_sched_reset(bp, rxr);
1374                 return rc1;
1375         }
1376         prefetch(data);
1377
1378         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1379                                 RX_CMP_AGG_BUFS_SHIFT;
1380
1381         if (agg_bufs) {
1382                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1383                         return -EBUSY;
1384
1385                 cp_cons = NEXT_CMP(cp_cons);
1386                 *agg_event = true;
1387         }
1388
1389         rx_buf->data = NULL;
1390         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1391                 bnxt_reuse_rx_data(rxr, cons, data);
1392                 if (agg_bufs)
1393                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1394
1395                 rc = -EIO;
1396                 goto next_rx;
1397         }
1398
1399         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1400         dma_addr = dma_unmap_addr(rx_buf, mapping);
1401
1402         if (len <= bp->rx_copy_thresh) {
1403                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1404                 bnxt_reuse_rx_data(rxr, cons, data);
1405                 if (!skb) {
1406                         rc = -ENOMEM;
1407                         goto next_rx;
1408                 }
1409         } else {
1410                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1411                 if (!skb) {
1412                         rc = -ENOMEM;
1413                         goto next_rx;
1414                 }
1415         }
1416
1417         if (agg_bufs) {
1418                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1419                 if (!skb) {
1420                         rc = -ENOMEM;
1421                         goto next_rx;
1422                 }
1423         }
1424
1425         if (RX_CMP_HASH_VALID(rxcmp)) {
1426                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1427                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1428
1429                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1430                 if (hash_type != 1 && hash_type != 3)
1431                         type = PKT_HASH_TYPE_L3;
1432                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1433         }
1434
1435         skb->protocol = eth_type_trans(skb, dev);
1436
1437         if ((rxcmp1->rx_cmp_flags2 &
1438              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1439             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1440                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1441                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1442                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1443
1444                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1445         }
1446
1447         skb_checksum_none_assert(skb);
1448         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1449                 if (dev->features & NETIF_F_RXCSUM) {
1450                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1451                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1452                 }
1453         } else {
1454                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1455                         if (dev->features & NETIF_F_RXCSUM)
1456                                 cpr->rx_l4_csum_errors++;
1457                 }
1458         }
1459
1460         skb_record_rx_queue(skb, bnapi->index);
1461         skb_mark_napi_id(skb, &bnapi->napi);
1462         if (bnxt_busy_polling(bnapi))
1463                 netif_receive_skb(skb);
1464         else
1465                 napi_gro_receive(&bnapi->napi, skb);
1466         rc = 1;
1467
1468 next_rx:
1469         rxr->rx_prod = NEXT_RX(prod);
1470         rxr->rx_next_cons = NEXT_RX(cons);
1471
1472 next_rx_no_prod:
1473         *raw_cons = tmp_raw_cons;
1474
1475         return rc;
1476 }
1477
1478 #define BNXT_GET_EVENT_PORT(data)       \
1479         ((data) &                               \
1480          HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1481
1482 static int bnxt_async_event_process(struct bnxt *bp,
1483                                     struct hwrm_async_event_cmpl *cmpl)
1484 {
1485         u16 event_id = le16_to_cpu(cmpl->event_id);
1486
1487         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1488         switch (event_id) {
1489         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1490                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1491                 struct bnxt_link_info *link_info = &bp->link_info;
1492
1493                 if (BNXT_VF(bp))
1494                         goto async_event_process_exit;
1495                 if (data1 & 0x20000) {
1496                         u16 fw_speed = link_info->force_link_speed;
1497                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1498
1499                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1500                                     speed);
1501                 }
1502                 /* fall thru */
1503         }
1504         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1505                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1506                 break;
1507         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1508                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1509                 break;
1510         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1511                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1512                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1513
1514                 if (BNXT_VF(bp))
1515                         break;
1516
1517                 if (bp->pf.port_id != port_id)
1518                         break;
1519
1520                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1521                 break;
1522         }
1523         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1524                 if (BNXT_PF(bp))
1525                         goto async_event_process_exit;
1526                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1527                 break;
1528         default:
1529                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1530                            event_id);
1531                 goto async_event_process_exit;
1532         }
1533         schedule_work(&bp->sp_task);
1534 async_event_process_exit:
1535         return 0;
1536 }
1537
1538 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1539 {
1540         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1541         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1542         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1543                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1544
1545         switch (cmpl_type) {
1546         case CMPL_BASE_TYPE_HWRM_DONE:
1547                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1548                 if (seq_id == bp->hwrm_intr_seq_id)
1549                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1550                 else
1551                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1552                 break;
1553
1554         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1555                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1556
1557                 if ((vf_id < bp->pf.first_vf_id) ||
1558                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1559                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1560                                    vf_id);
1561                         return -EINVAL;
1562                 }
1563
1564                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1565                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1566                 schedule_work(&bp->sp_task);
1567                 break;
1568
1569         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1570                 bnxt_async_event_process(bp,
1571                                          (struct hwrm_async_event_cmpl *)txcmp);
1572
1573         default:
1574                 break;
1575         }
1576
1577         return 0;
1578 }
1579
1580 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1581 {
1582         struct bnxt_napi *bnapi = dev_instance;
1583         struct bnxt *bp = bnapi->bp;
1584         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1585         u32 cons = RING_CMP(cpr->cp_raw_cons);
1586
1587         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1588         napi_schedule(&bnapi->napi);
1589         return IRQ_HANDLED;
1590 }
1591
1592 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1593 {
1594         u32 raw_cons = cpr->cp_raw_cons;
1595         u16 cons = RING_CMP(raw_cons);
1596         struct tx_cmp *txcmp;
1597
1598         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1599
1600         return TX_CMP_VALID(txcmp, raw_cons);
1601 }
1602
1603 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1604 {
1605         struct bnxt_napi *bnapi = dev_instance;
1606         struct bnxt *bp = bnapi->bp;
1607         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1608         u32 cons = RING_CMP(cpr->cp_raw_cons);
1609         u32 int_status;
1610
1611         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1612
1613         if (!bnxt_has_work(bp, cpr)) {
1614                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1615                 /* return if erroneous interrupt */
1616                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1617                         return IRQ_NONE;
1618         }
1619
1620         /* disable ring IRQ */
1621         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1622
1623         /* Return here if interrupt is shared and is disabled. */
1624         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1625                 return IRQ_HANDLED;
1626
1627         napi_schedule(&bnapi->napi);
1628         return IRQ_HANDLED;
1629 }
1630
1631 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1632 {
1633         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1634         u32 raw_cons = cpr->cp_raw_cons;
1635         u32 cons;
1636         int tx_pkts = 0;
1637         int rx_pkts = 0;
1638         bool rx_event = false;
1639         bool agg_event = false;
1640         struct tx_cmp *txcmp;
1641
1642         while (1) {
1643                 int rc;
1644
1645                 cons = RING_CMP(raw_cons);
1646                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1647
1648                 if (!TX_CMP_VALID(txcmp, raw_cons))
1649                         break;
1650
1651                 /* The valid test of the entry must be done first before
1652                  * reading any further.
1653                  */
1654                 dma_rmb();
1655                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1656                         tx_pkts++;
1657                         /* return full budget so NAPI will complete. */
1658                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1659                                 rx_pkts = budget;
1660                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1661                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1662                         if (likely(rc >= 0))
1663                                 rx_pkts += rc;
1664                         else if (rc == -EBUSY)  /* partial completion */
1665                                 break;
1666                         rx_event = true;
1667                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1668                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1669                                     (TX_CMP_TYPE(txcmp) ==
1670                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1671                                     (TX_CMP_TYPE(txcmp) ==
1672                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1673                         bnxt_hwrm_handler(bp, txcmp);
1674                 }
1675                 raw_cons = NEXT_RAW_CMP(raw_cons);
1676
1677                 if (rx_pkts == budget)
1678                         break;
1679         }
1680
1681         cpr->cp_raw_cons = raw_cons;
1682         /* ACK completion ring before freeing tx ring and producing new
1683          * buffers in rx/agg rings to prevent overflowing the completion
1684          * ring.
1685          */
1686         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1687
1688         if (tx_pkts)
1689                 bnxt_tx_int(bp, bnapi, tx_pkts);
1690
1691         if (rx_event) {
1692                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1693
1694                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1695                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1696                 if (agg_event) {
1697                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1698                                rxr->rx_agg_doorbell);
1699                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1700                                rxr->rx_agg_doorbell);
1701                 }
1702         }
1703         return rx_pkts;
1704 }
1705
1706 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1707 {
1708         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1709         struct bnxt *bp = bnapi->bp;
1710         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1711         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1712         struct tx_cmp *txcmp;
1713         struct rx_cmp_ext *rxcmp1;
1714         u32 cp_cons, tmp_raw_cons;
1715         u32 raw_cons = cpr->cp_raw_cons;
1716         u32 rx_pkts = 0;
1717         bool agg_event = false;
1718
1719         while (1) {
1720                 int rc;
1721
1722                 cp_cons = RING_CMP(raw_cons);
1723                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1724
1725                 if (!TX_CMP_VALID(txcmp, raw_cons))
1726                         break;
1727
1728                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1729                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1730                         cp_cons = RING_CMP(tmp_raw_cons);
1731                         rxcmp1 = (struct rx_cmp_ext *)
1732                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1733
1734                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1735                                 break;
1736
1737                         /* force an error to recycle the buffer */
1738                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1739                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1740
1741                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1742                         if (likely(rc == -EIO))
1743                                 rx_pkts++;
1744                         else if (rc == -EBUSY)  /* partial completion */
1745                                 break;
1746                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1747                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1748                         bnxt_hwrm_handler(bp, txcmp);
1749                 } else {
1750                         netdev_err(bp->dev,
1751                                    "Invalid completion received on special ring\n");
1752                 }
1753                 raw_cons = NEXT_RAW_CMP(raw_cons);
1754
1755                 if (rx_pkts == budget)
1756                         break;
1757         }
1758
1759         cpr->cp_raw_cons = raw_cons;
1760         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1761         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1762         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1763
1764         if (agg_event) {
1765                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1766                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1767         }
1768
1769         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1770                 napi_complete(napi);
1771                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1772         }
1773         return rx_pkts;
1774 }
1775
1776 static int bnxt_poll(struct napi_struct *napi, int budget)
1777 {
1778         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1779         struct bnxt *bp = bnapi->bp;
1780         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1781         int work_done = 0;
1782
1783         if (!bnxt_lock_napi(bnapi))
1784                 return budget;
1785
1786         while (1) {
1787                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1788
1789                 if (work_done >= budget)
1790                         break;
1791
1792                 if (!bnxt_has_work(bp, cpr)) {
1793                         napi_complete(napi);
1794                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1795                         break;
1796                 }
1797         }
1798         mmiowb();
1799         bnxt_unlock_napi(bnapi);
1800         return work_done;
1801 }
1802
1803 #ifdef CONFIG_NET_RX_BUSY_POLL
1804 static int bnxt_busy_poll(struct napi_struct *napi)
1805 {
1806         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1807         struct bnxt *bp = bnapi->bp;
1808         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1809         int rx_work, budget = 4;
1810
1811         if (atomic_read(&bp->intr_sem) != 0)
1812                 return LL_FLUSH_FAILED;
1813
1814         if (!bp->link_info.link_up)
1815                 return LL_FLUSH_FAILED;
1816
1817         if (!bnxt_lock_poll(bnapi))
1818                 return LL_FLUSH_BUSY;
1819
1820         rx_work = bnxt_poll_work(bp, bnapi, budget);
1821
1822         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1823
1824         bnxt_unlock_poll(bnapi);
1825         return rx_work;
1826 }
1827 #endif
1828
1829 static void bnxt_free_tx_skbs(struct bnxt *bp)
1830 {
1831         int i, max_idx;
1832         struct pci_dev *pdev = bp->pdev;
1833
1834         if (!bp->tx_ring)
1835                 return;
1836
1837         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1838         for (i = 0; i < bp->tx_nr_rings; i++) {
1839                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1840                 int j;
1841
1842                 for (j = 0; j < max_idx;) {
1843                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1844                         struct sk_buff *skb = tx_buf->skb;
1845                         int k, last;
1846
1847                         if (!skb) {
1848                                 j++;
1849                                 continue;
1850                         }
1851
1852                         tx_buf->skb = NULL;
1853
1854                         if (tx_buf->is_push) {
1855                                 dev_kfree_skb(skb);
1856                                 j += 2;
1857                                 continue;
1858                         }
1859
1860                         dma_unmap_single(&pdev->dev,
1861                                          dma_unmap_addr(tx_buf, mapping),
1862                                          skb_headlen(skb),
1863                                          PCI_DMA_TODEVICE);
1864
1865                         last = tx_buf->nr_frags;
1866                         j += 2;
1867                         for (k = 0; k < last; k++, j++) {
1868                                 int ring_idx = j & bp->tx_ring_mask;
1869                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1870
1871                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1872                                 dma_unmap_page(
1873                                         &pdev->dev,
1874                                         dma_unmap_addr(tx_buf, mapping),
1875                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1876                         }
1877                         dev_kfree_skb(skb);
1878                 }
1879                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1880         }
1881 }
1882
1883 static void bnxt_free_rx_skbs(struct bnxt *bp)
1884 {
1885         int i, max_idx, max_agg_idx;
1886         struct pci_dev *pdev = bp->pdev;
1887
1888         if (!bp->rx_ring)
1889                 return;
1890
1891         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1892         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1893         for (i = 0; i < bp->rx_nr_rings; i++) {
1894                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1895                 int j;
1896
1897                 if (rxr->rx_tpa) {
1898                         for (j = 0; j < MAX_TPA; j++) {
1899                                 struct bnxt_tpa_info *tpa_info =
1900                                                         &rxr->rx_tpa[j];
1901                                 u8 *data = tpa_info->data;
1902
1903                                 if (!data)
1904                                         continue;
1905
1906                                 dma_unmap_single(
1907                                         &pdev->dev,
1908                                         dma_unmap_addr(tpa_info, mapping),
1909                                         bp->rx_buf_use_size,
1910                                         PCI_DMA_FROMDEVICE);
1911
1912                                 tpa_info->data = NULL;
1913
1914                                 kfree(data);
1915                         }
1916                 }
1917
1918                 for (j = 0; j < max_idx; j++) {
1919                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1920                         u8 *data = rx_buf->data;
1921
1922                         if (!data)
1923                                 continue;
1924
1925                         dma_unmap_single(&pdev->dev,
1926                                          dma_unmap_addr(rx_buf, mapping),
1927                                          bp->rx_buf_use_size,
1928                                          PCI_DMA_FROMDEVICE);
1929
1930                         rx_buf->data = NULL;
1931
1932                         kfree(data);
1933                 }
1934
1935                 for (j = 0; j < max_agg_idx; j++) {
1936                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1937                                 &rxr->rx_agg_ring[j];
1938                         struct page *page = rx_agg_buf->page;
1939
1940                         if (!page)
1941                                 continue;
1942
1943                         dma_unmap_page(&pdev->dev,
1944                                        dma_unmap_addr(rx_agg_buf, mapping),
1945                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1946
1947                         rx_agg_buf->page = NULL;
1948                         __clear_bit(j, rxr->rx_agg_bmap);
1949
1950                         __free_page(page);
1951                 }
1952                 if (rxr->rx_page) {
1953                         __free_page(rxr->rx_page);
1954                         rxr->rx_page = NULL;
1955                 }
1956         }
1957 }
1958
1959 static void bnxt_free_skbs(struct bnxt *bp)
1960 {
1961         bnxt_free_tx_skbs(bp);
1962         bnxt_free_rx_skbs(bp);
1963 }
1964
1965 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1966 {
1967         struct pci_dev *pdev = bp->pdev;
1968         int i;
1969
1970         for (i = 0; i < ring->nr_pages; i++) {
1971                 if (!ring->pg_arr[i])
1972                         continue;
1973
1974                 dma_free_coherent(&pdev->dev, ring->page_size,
1975                                   ring->pg_arr[i], ring->dma_arr[i]);
1976
1977                 ring->pg_arr[i] = NULL;
1978         }
1979         if (ring->pg_tbl) {
1980                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1981                                   ring->pg_tbl, ring->pg_tbl_map);
1982                 ring->pg_tbl = NULL;
1983         }
1984         if (ring->vmem_size && *ring->vmem) {
1985                 vfree(*ring->vmem);
1986                 *ring->vmem = NULL;
1987         }
1988 }
1989
1990 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1991 {
1992         int i;
1993         struct pci_dev *pdev = bp->pdev;
1994
1995         if (ring->nr_pages > 1) {
1996                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1997                                                   ring->nr_pages * 8,
1998                                                   &ring->pg_tbl_map,
1999                                                   GFP_KERNEL);
2000                 if (!ring->pg_tbl)
2001                         return -ENOMEM;
2002         }
2003
2004         for (i = 0; i < ring->nr_pages; i++) {
2005                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2006                                                      ring->page_size,
2007                                                      &ring->dma_arr[i],
2008                                                      GFP_KERNEL);
2009                 if (!ring->pg_arr[i])
2010                         return -ENOMEM;
2011
2012                 if (ring->nr_pages > 1)
2013                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2014         }
2015
2016         if (ring->vmem_size) {
2017                 *ring->vmem = vzalloc(ring->vmem_size);
2018                 if (!(*ring->vmem))
2019                         return -ENOMEM;
2020         }
2021         return 0;
2022 }
2023
2024 static void bnxt_free_rx_rings(struct bnxt *bp)
2025 {
2026         int i;
2027
2028         if (!bp->rx_ring)
2029                 return;
2030
2031         for (i = 0; i < bp->rx_nr_rings; i++) {
2032                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2033                 struct bnxt_ring_struct *ring;
2034
2035                 kfree(rxr->rx_tpa);
2036                 rxr->rx_tpa = NULL;
2037
2038                 kfree(rxr->rx_agg_bmap);
2039                 rxr->rx_agg_bmap = NULL;
2040
2041                 ring = &rxr->rx_ring_struct;
2042                 bnxt_free_ring(bp, ring);
2043
2044                 ring = &rxr->rx_agg_ring_struct;
2045                 bnxt_free_ring(bp, ring);
2046         }
2047 }
2048
2049 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2050 {
2051         int i, rc, agg_rings = 0, tpa_rings = 0;
2052
2053         if (!bp->rx_ring)
2054                 return -ENOMEM;
2055
2056         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2057                 agg_rings = 1;
2058
2059         if (bp->flags & BNXT_FLAG_TPA)
2060                 tpa_rings = 1;
2061
2062         for (i = 0; i < bp->rx_nr_rings; i++) {
2063                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2064                 struct bnxt_ring_struct *ring;
2065
2066                 ring = &rxr->rx_ring_struct;
2067
2068                 rc = bnxt_alloc_ring(bp, ring);
2069                 if (rc)
2070                         return rc;
2071
2072                 if (agg_rings) {
2073                         u16 mem_size;
2074
2075                         ring = &rxr->rx_agg_ring_struct;
2076                         rc = bnxt_alloc_ring(bp, ring);
2077                         if (rc)
2078                                 return rc;
2079
2080                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2081                         mem_size = rxr->rx_agg_bmap_size / 8;
2082                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2083                         if (!rxr->rx_agg_bmap)
2084                                 return -ENOMEM;
2085
2086                         if (tpa_rings) {
2087                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2088                                                 sizeof(struct bnxt_tpa_info),
2089                                                 GFP_KERNEL);
2090                                 if (!rxr->rx_tpa)
2091                                         return -ENOMEM;
2092                         }
2093                 }
2094         }
2095         return 0;
2096 }
2097
2098 static void bnxt_free_tx_rings(struct bnxt *bp)
2099 {
2100         int i;
2101         struct pci_dev *pdev = bp->pdev;
2102
2103         if (!bp->tx_ring)
2104                 return;
2105
2106         for (i = 0; i < bp->tx_nr_rings; i++) {
2107                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2108                 struct bnxt_ring_struct *ring;
2109
2110                 if (txr->tx_push) {
2111                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2112                                           txr->tx_push, txr->tx_push_mapping);
2113                         txr->tx_push = NULL;
2114                 }
2115
2116                 ring = &txr->tx_ring_struct;
2117
2118                 bnxt_free_ring(bp, ring);
2119         }
2120 }
2121
2122 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2123 {
2124         int i, j, rc;
2125         struct pci_dev *pdev = bp->pdev;
2126
2127         bp->tx_push_size = 0;
2128         if (bp->tx_push_thresh) {
2129                 int push_size;
2130
2131                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2132                                         bp->tx_push_thresh);
2133
2134                 if (push_size > 256) {
2135                         push_size = 0;
2136                         bp->tx_push_thresh = 0;
2137                 }
2138
2139                 bp->tx_push_size = push_size;
2140         }
2141
2142         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2143                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2144                 struct bnxt_ring_struct *ring;
2145
2146                 ring = &txr->tx_ring_struct;
2147
2148                 rc = bnxt_alloc_ring(bp, ring);
2149                 if (rc)
2150                         return rc;
2151
2152                 if (bp->tx_push_size) {
2153                         dma_addr_t mapping;
2154
2155                         /* One pre-allocated DMA buffer to backup
2156                          * TX push operation
2157                          */
2158                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2159                                                 bp->tx_push_size,
2160                                                 &txr->tx_push_mapping,
2161                                                 GFP_KERNEL);
2162
2163                         if (!txr->tx_push)
2164                                 return -ENOMEM;
2165
2166                         mapping = txr->tx_push_mapping +
2167                                 sizeof(struct tx_push_bd);
2168                         txr->data_mapping = cpu_to_le64(mapping);
2169
2170                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2171                 }
2172                 ring->queue_id = bp->q_info[j].queue_id;
2173                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2174                         j++;
2175         }
2176         return 0;
2177 }
2178
2179 static void bnxt_free_cp_rings(struct bnxt *bp)
2180 {
2181         int i;
2182
2183         if (!bp->bnapi)
2184                 return;
2185
2186         for (i = 0; i < bp->cp_nr_rings; i++) {
2187                 struct bnxt_napi *bnapi = bp->bnapi[i];
2188                 struct bnxt_cp_ring_info *cpr;
2189                 struct bnxt_ring_struct *ring;
2190
2191                 if (!bnapi)
2192                         continue;
2193
2194                 cpr = &bnapi->cp_ring;
2195                 ring = &cpr->cp_ring_struct;
2196
2197                 bnxt_free_ring(bp, ring);
2198         }
2199 }
2200
2201 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2202 {
2203         int i, rc;
2204
2205         for (i = 0; i < bp->cp_nr_rings; i++) {
2206                 struct bnxt_napi *bnapi = bp->bnapi[i];
2207                 struct bnxt_cp_ring_info *cpr;
2208                 struct bnxt_ring_struct *ring;
2209
2210                 if (!bnapi)
2211                         continue;
2212
2213                 cpr = &bnapi->cp_ring;
2214                 ring = &cpr->cp_ring_struct;
2215
2216                 rc = bnxt_alloc_ring(bp, ring);
2217                 if (rc)
2218                         return rc;
2219         }
2220         return 0;
2221 }
2222
2223 static void bnxt_init_ring_struct(struct bnxt *bp)
2224 {
2225         int i;
2226
2227         for (i = 0; i < bp->cp_nr_rings; i++) {
2228                 struct bnxt_napi *bnapi = bp->bnapi[i];
2229                 struct bnxt_cp_ring_info *cpr;
2230                 struct bnxt_rx_ring_info *rxr;
2231                 struct bnxt_tx_ring_info *txr;
2232                 struct bnxt_ring_struct *ring;
2233
2234                 if (!bnapi)
2235                         continue;
2236
2237                 cpr = &bnapi->cp_ring;
2238                 ring = &cpr->cp_ring_struct;
2239                 ring->nr_pages = bp->cp_nr_pages;
2240                 ring->page_size = HW_CMPD_RING_SIZE;
2241                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2242                 ring->dma_arr = cpr->cp_desc_mapping;
2243                 ring->vmem_size = 0;
2244
2245                 rxr = bnapi->rx_ring;
2246                 if (!rxr)
2247                         goto skip_rx;
2248
2249                 ring = &rxr->rx_ring_struct;
2250                 ring->nr_pages = bp->rx_nr_pages;
2251                 ring->page_size = HW_RXBD_RING_SIZE;
2252                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2253                 ring->dma_arr = rxr->rx_desc_mapping;
2254                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2255                 ring->vmem = (void **)&rxr->rx_buf_ring;
2256
2257                 ring = &rxr->rx_agg_ring_struct;
2258                 ring->nr_pages = bp->rx_agg_nr_pages;
2259                 ring->page_size = HW_RXBD_RING_SIZE;
2260                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2261                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2262                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2263                 ring->vmem = (void **)&rxr->rx_agg_ring;
2264
2265 skip_rx:
2266                 txr = bnapi->tx_ring;
2267                 if (!txr)
2268                         continue;
2269
2270                 ring = &txr->tx_ring_struct;
2271                 ring->nr_pages = bp->tx_nr_pages;
2272                 ring->page_size = HW_RXBD_RING_SIZE;
2273                 ring->pg_arr = (void **)txr->tx_desc_ring;
2274                 ring->dma_arr = txr->tx_desc_mapping;
2275                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2276                 ring->vmem = (void **)&txr->tx_buf_ring;
2277         }
2278 }
2279
2280 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2281 {
2282         int i;
2283         u32 prod;
2284         struct rx_bd **rx_buf_ring;
2285
2286         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2287         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2288                 int j;
2289                 struct rx_bd *rxbd;
2290
2291                 rxbd = rx_buf_ring[i];
2292                 if (!rxbd)
2293                         continue;
2294
2295                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2296                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2297                         rxbd->rx_bd_opaque = prod;
2298                 }
2299         }
2300 }
2301
2302 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2303 {
2304         struct net_device *dev = bp->dev;
2305         struct bnxt_rx_ring_info *rxr;
2306         struct bnxt_ring_struct *ring;
2307         u32 prod, type;
2308         int i;
2309
2310         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2311                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2312
2313         if (NET_IP_ALIGN == 2)
2314                 type |= RX_BD_FLAGS_SOP;
2315
2316         rxr = &bp->rx_ring[ring_nr];
2317         ring = &rxr->rx_ring_struct;
2318         bnxt_init_rxbd_pages(ring, type);
2319
2320         prod = rxr->rx_prod;
2321         for (i = 0; i < bp->rx_ring_size; i++) {
2322                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2323                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2324                                     ring_nr, i, bp->rx_ring_size);
2325                         break;
2326                 }
2327                 prod = NEXT_RX(prod);
2328         }
2329         rxr->rx_prod = prod;
2330         ring->fw_ring_id = INVALID_HW_RING_ID;
2331
2332         ring = &rxr->rx_agg_ring_struct;
2333         ring->fw_ring_id = INVALID_HW_RING_ID;
2334
2335         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2336                 return 0;
2337
2338         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2339                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2340
2341         bnxt_init_rxbd_pages(ring, type);
2342
2343         prod = rxr->rx_agg_prod;
2344         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2345                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2346                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2347                                     ring_nr, i, bp->rx_ring_size);
2348                         break;
2349                 }
2350                 prod = NEXT_RX_AGG(prod);
2351         }
2352         rxr->rx_agg_prod = prod;
2353
2354         if (bp->flags & BNXT_FLAG_TPA) {
2355                 if (rxr->rx_tpa) {
2356                         u8 *data;
2357                         dma_addr_t mapping;
2358
2359                         for (i = 0; i < MAX_TPA; i++) {
2360                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2361                                                             GFP_KERNEL);
2362                                 if (!data)
2363                                         return -ENOMEM;
2364
2365                                 rxr->rx_tpa[i].data = data;
2366                                 rxr->rx_tpa[i].mapping = mapping;
2367                         }
2368                 } else {
2369                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2370                         return -ENOMEM;
2371                 }
2372         }
2373
2374         return 0;
2375 }
2376
2377 static int bnxt_init_rx_rings(struct bnxt *bp)
2378 {
2379         int i, rc = 0;
2380
2381         for (i = 0; i < bp->rx_nr_rings; i++) {
2382                 rc = bnxt_init_one_rx_ring(bp, i);
2383                 if (rc)
2384                         break;
2385         }
2386
2387         return rc;
2388 }
2389
2390 static int bnxt_init_tx_rings(struct bnxt *bp)
2391 {
2392         u16 i;
2393
2394         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2395                                    MAX_SKB_FRAGS + 1);
2396
2397         for (i = 0; i < bp->tx_nr_rings; i++) {
2398                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2399                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2400
2401                 ring->fw_ring_id = INVALID_HW_RING_ID;
2402         }
2403
2404         return 0;
2405 }
2406
2407 static void bnxt_free_ring_grps(struct bnxt *bp)
2408 {
2409         kfree(bp->grp_info);
2410         bp->grp_info = NULL;
2411 }
2412
2413 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2414 {
2415         int i;
2416
2417         if (irq_re_init) {
2418                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2419                                        sizeof(struct bnxt_ring_grp_info),
2420                                        GFP_KERNEL);
2421                 if (!bp->grp_info)
2422                         return -ENOMEM;
2423         }
2424         for (i = 0; i < bp->cp_nr_rings; i++) {
2425                 if (irq_re_init)
2426                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2427                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2428                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2429                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2430                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2431         }
2432         return 0;
2433 }
2434
2435 static void bnxt_free_vnics(struct bnxt *bp)
2436 {
2437         kfree(bp->vnic_info);
2438         bp->vnic_info = NULL;
2439         bp->nr_vnics = 0;
2440 }
2441
2442 static int bnxt_alloc_vnics(struct bnxt *bp)
2443 {
2444         int num_vnics = 1;
2445
2446 #ifdef CONFIG_RFS_ACCEL
2447         if (bp->flags & BNXT_FLAG_RFS)
2448                 num_vnics += bp->rx_nr_rings;
2449 #endif
2450
2451         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2452                 num_vnics++;
2453
2454         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2455                                 GFP_KERNEL);
2456         if (!bp->vnic_info)
2457                 return -ENOMEM;
2458
2459         bp->nr_vnics = num_vnics;
2460         return 0;
2461 }
2462
2463 static void bnxt_init_vnics(struct bnxt *bp)
2464 {
2465         int i;
2466
2467         for (i = 0; i < bp->nr_vnics; i++) {
2468                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2469
2470                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2471                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2472                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2473                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2474
2475                 if (bp->vnic_info[i].rss_hash_key) {
2476                         if (i == 0)
2477                                 prandom_bytes(vnic->rss_hash_key,
2478                                               HW_HASH_KEY_SIZE);
2479                         else
2480                                 memcpy(vnic->rss_hash_key,
2481                                        bp->vnic_info[0].rss_hash_key,
2482                                        HW_HASH_KEY_SIZE);
2483                 }
2484         }
2485 }
2486
2487 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2488 {
2489         int pages;
2490
2491         pages = ring_size / desc_per_pg;
2492
2493         if (!pages)
2494                 return 1;
2495
2496         pages++;
2497
2498         while (pages & (pages - 1))
2499                 pages++;
2500
2501         return pages;
2502 }
2503
2504 static void bnxt_set_tpa_flags(struct bnxt *bp)
2505 {
2506         bp->flags &= ~BNXT_FLAG_TPA;
2507         if (bp->dev->features & NETIF_F_LRO)
2508                 bp->flags |= BNXT_FLAG_LRO;
2509         if (bp->dev->features & NETIF_F_GRO)
2510                 bp->flags |= BNXT_FLAG_GRO;
2511 }
2512
2513 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2514  * be set on entry.
2515  */
2516 void bnxt_set_ring_params(struct bnxt *bp)
2517 {
2518         u32 ring_size, rx_size, rx_space;
2519         u32 agg_factor = 0, agg_ring_size = 0;
2520
2521         /* 8 for CRC and VLAN */
2522         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2523
2524         rx_space = rx_size + NET_SKB_PAD +
2525                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2526
2527         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2528         ring_size = bp->rx_ring_size;
2529         bp->rx_agg_ring_size = 0;
2530         bp->rx_agg_nr_pages = 0;
2531
2532         if (bp->flags & BNXT_FLAG_TPA)
2533                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2534
2535         bp->flags &= ~BNXT_FLAG_JUMBO;
2536         if (rx_space > PAGE_SIZE) {
2537                 u32 jumbo_factor;
2538
2539                 bp->flags |= BNXT_FLAG_JUMBO;
2540                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2541                 if (jumbo_factor > agg_factor)
2542                         agg_factor = jumbo_factor;
2543         }
2544         agg_ring_size = ring_size * agg_factor;
2545
2546         if (agg_ring_size) {
2547                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2548                                                         RX_DESC_CNT);
2549                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2550                         u32 tmp = agg_ring_size;
2551
2552                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2553                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2554                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2555                                     tmp, agg_ring_size);
2556                 }
2557                 bp->rx_agg_ring_size = agg_ring_size;
2558                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2559                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2560                 rx_space = rx_size + NET_SKB_PAD +
2561                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2562         }
2563
2564         bp->rx_buf_use_size = rx_size;
2565         bp->rx_buf_size = rx_space;
2566
2567         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2568         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2569
2570         ring_size = bp->tx_ring_size;
2571         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2572         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2573
2574         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2575         bp->cp_ring_size = ring_size;
2576
2577         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2578         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2579                 bp->cp_nr_pages = MAX_CP_PAGES;
2580                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2581                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2582                             ring_size, bp->cp_ring_size);
2583         }
2584         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2585         bp->cp_ring_mask = bp->cp_bit - 1;
2586 }
2587
2588 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2589 {
2590         int i;
2591         struct bnxt_vnic_info *vnic;
2592         struct pci_dev *pdev = bp->pdev;
2593
2594         if (!bp->vnic_info)
2595                 return;
2596
2597         for (i = 0; i < bp->nr_vnics; i++) {
2598                 vnic = &bp->vnic_info[i];
2599
2600                 kfree(vnic->fw_grp_ids);
2601                 vnic->fw_grp_ids = NULL;
2602
2603                 kfree(vnic->uc_list);
2604                 vnic->uc_list = NULL;
2605
2606                 if (vnic->mc_list) {
2607                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2608                                           vnic->mc_list, vnic->mc_list_mapping);
2609                         vnic->mc_list = NULL;
2610                 }
2611
2612                 if (vnic->rss_table) {
2613                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2614                                           vnic->rss_table,
2615                                           vnic->rss_table_dma_addr);
2616                         vnic->rss_table = NULL;
2617                 }
2618
2619                 vnic->rss_hash_key = NULL;
2620                 vnic->flags = 0;
2621         }
2622 }
2623
2624 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2625 {
2626         int i, rc = 0, size;
2627         struct bnxt_vnic_info *vnic;
2628         struct pci_dev *pdev = bp->pdev;
2629         int max_rings;
2630
2631         for (i = 0; i < bp->nr_vnics; i++) {
2632                 vnic = &bp->vnic_info[i];
2633
2634                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2635                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2636
2637                         if (mem_size > 0) {
2638                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2639                                 if (!vnic->uc_list) {
2640                                         rc = -ENOMEM;
2641                                         goto out;
2642                                 }
2643                         }
2644                 }
2645
2646                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2647                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2648                         vnic->mc_list =
2649                                 dma_alloc_coherent(&pdev->dev,
2650                                                    vnic->mc_list_size,
2651                                                    &vnic->mc_list_mapping,
2652                                                    GFP_KERNEL);
2653                         if (!vnic->mc_list) {
2654                                 rc = -ENOMEM;
2655                                 goto out;
2656                         }
2657                 }
2658
2659                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2660                         max_rings = bp->rx_nr_rings;
2661                 else
2662                         max_rings = 1;
2663
2664                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2665                 if (!vnic->fw_grp_ids) {
2666                         rc = -ENOMEM;
2667                         goto out;
2668                 }
2669
2670                 /* Allocate rss table and hash key */
2671                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2672                                                      &vnic->rss_table_dma_addr,
2673                                                      GFP_KERNEL);
2674                 if (!vnic->rss_table) {
2675                         rc = -ENOMEM;
2676                         goto out;
2677                 }
2678
2679                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2680
2681                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2682                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2683         }
2684         return 0;
2685
2686 out:
2687         return rc;
2688 }
2689
2690 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2691 {
2692         struct pci_dev *pdev = bp->pdev;
2693
2694         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2695                           bp->hwrm_cmd_resp_dma_addr);
2696
2697         bp->hwrm_cmd_resp_addr = NULL;
2698         if (bp->hwrm_dbg_resp_addr) {
2699                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2700                                   bp->hwrm_dbg_resp_addr,
2701                                   bp->hwrm_dbg_resp_dma_addr);
2702
2703                 bp->hwrm_dbg_resp_addr = NULL;
2704         }
2705 }
2706
2707 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2708 {
2709         struct pci_dev *pdev = bp->pdev;
2710
2711         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2712                                                    &bp->hwrm_cmd_resp_dma_addr,
2713                                                    GFP_KERNEL);
2714         if (!bp->hwrm_cmd_resp_addr)
2715                 return -ENOMEM;
2716         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2717                                                     HWRM_DBG_REG_BUF_SIZE,
2718                                                     &bp->hwrm_dbg_resp_dma_addr,
2719                                                     GFP_KERNEL);
2720         if (!bp->hwrm_dbg_resp_addr)
2721                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2722
2723         return 0;
2724 }
2725
2726 static void bnxt_free_stats(struct bnxt *bp)
2727 {
2728         u32 size, i;
2729         struct pci_dev *pdev = bp->pdev;
2730
2731         if (bp->hw_rx_port_stats) {
2732                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2733                                   bp->hw_rx_port_stats,
2734                                   bp->hw_rx_port_stats_map);
2735                 bp->hw_rx_port_stats = NULL;
2736                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2737         }
2738
2739         if (!bp->bnapi)
2740                 return;
2741
2742         size = sizeof(struct ctx_hw_stats);
2743
2744         for (i = 0; i < bp->cp_nr_rings; i++) {
2745                 struct bnxt_napi *bnapi = bp->bnapi[i];
2746                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2747
2748                 if (cpr->hw_stats) {
2749                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2750                                           cpr->hw_stats_map);
2751                         cpr->hw_stats = NULL;
2752                 }
2753         }
2754 }
2755
2756 static int bnxt_alloc_stats(struct bnxt *bp)
2757 {
2758         u32 size, i;
2759         struct pci_dev *pdev = bp->pdev;
2760
2761         size = sizeof(struct ctx_hw_stats);
2762
2763         for (i = 0; i < bp->cp_nr_rings; i++) {
2764                 struct bnxt_napi *bnapi = bp->bnapi[i];
2765                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2766
2767                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2768                                                    &cpr->hw_stats_map,
2769                                                    GFP_KERNEL);
2770                 if (!cpr->hw_stats)
2771                         return -ENOMEM;
2772
2773                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2774         }
2775
2776         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2777                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2778                                          sizeof(struct tx_port_stats) + 1024;
2779
2780                 bp->hw_rx_port_stats =
2781                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2782                                            &bp->hw_rx_port_stats_map,
2783                                            GFP_KERNEL);
2784                 if (!bp->hw_rx_port_stats)
2785                         return -ENOMEM;
2786
2787                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2788                                        512;
2789                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2790                                            sizeof(struct rx_port_stats) + 512;
2791                 bp->flags |= BNXT_FLAG_PORT_STATS;
2792         }
2793         return 0;
2794 }
2795
2796 static void bnxt_clear_ring_indices(struct bnxt *bp)
2797 {
2798         int i;
2799
2800         if (!bp->bnapi)
2801                 return;
2802
2803         for (i = 0; i < bp->cp_nr_rings; i++) {
2804                 struct bnxt_napi *bnapi = bp->bnapi[i];
2805                 struct bnxt_cp_ring_info *cpr;
2806                 struct bnxt_rx_ring_info *rxr;
2807                 struct bnxt_tx_ring_info *txr;
2808
2809                 if (!bnapi)
2810                         continue;
2811
2812                 cpr = &bnapi->cp_ring;
2813                 cpr->cp_raw_cons = 0;
2814
2815                 txr = bnapi->tx_ring;
2816                 if (txr) {
2817                         txr->tx_prod = 0;
2818                         txr->tx_cons = 0;
2819                 }
2820
2821                 rxr = bnapi->rx_ring;
2822                 if (rxr) {
2823                         rxr->rx_prod = 0;
2824                         rxr->rx_agg_prod = 0;
2825                         rxr->rx_sw_agg_prod = 0;
2826                         rxr->rx_next_cons = 0;
2827                 }
2828         }
2829 }
2830
2831 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2832 {
2833 #ifdef CONFIG_RFS_ACCEL
2834         int i;
2835
2836         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2837          * safe to delete the hash table.
2838          */
2839         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2840                 struct hlist_head *head;
2841                 struct hlist_node *tmp;
2842                 struct bnxt_ntuple_filter *fltr;
2843
2844                 head = &bp->ntp_fltr_hash_tbl[i];
2845                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2846                         hlist_del(&fltr->hash);
2847                         kfree(fltr);
2848                 }
2849         }
2850         if (irq_reinit) {
2851                 kfree(bp->ntp_fltr_bmap);
2852                 bp->ntp_fltr_bmap = NULL;
2853         }
2854         bp->ntp_fltr_count = 0;
2855 #endif
2856 }
2857
2858 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2859 {
2860 #ifdef CONFIG_RFS_ACCEL
2861         int i, rc = 0;
2862
2863         if (!(bp->flags & BNXT_FLAG_RFS))
2864                 return 0;
2865
2866         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2867                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2868
2869         bp->ntp_fltr_count = 0;
2870         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2871                                     GFP_KERNEL);
2872
2873         if (!bp->ntp_fltr_bmap)
2874                 rc = -ENOMEM;
2875
2876         return rc;
2877 #else
2878         return 0;
2879 #endif
2880 }
2881
2882 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2883 {
2884         bnxt_free_vnic_attributes(bp);
2885         bnxt_free_tx_rings(bp);
2886         bnxt_free_rx_rings(bp);
2887         bnxt_free_cp_rings(bp);
2888         bnxt_free_ntp_fltrs(bp, irq_re_init);
2889         if (irq_re_init) {
2890                 bnxt_free_stats(bp);
2891                 bnxt_free_ring_grps(bp);
2892                 bnxt_free_vnics(bp);
2893                 kfree(bp->tx_ring);
2894                 bp->tx_ring = NULL;
2895                 kfree(bp->rx_ring);
2896                 bp->rx_ring = NULL;
2897                 kfree(bp->bnapi);
2898                 bp->bnapi = NULL;
2899         } else {
2900                 bnxt_clear_ring_indices(bp);
2901         }
2902 }
2903
2904 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2905 {
2906         int i, j, rc, size, arr_size;
2907         void *bnapi;
2908
2909         if (irq_re_init) {
2910                 /* Allocate bnapi mem pointer array and mem block for
2911                  * all queues
2912                  */
2913                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2914                                 bp->cp_nr_rings);
2915                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2916                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2917                 if (!bnapi)
2918                         return -ENOMEM;
2919
2920                 bp->bnapi = bnapi;
2921                 bnapi += arr_size;
2922                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2923                         bp->bnapi[i] = bnapi;
2924                         bp->bnapi[i]->index = i;
2925                         bp->bnapi[i]->bp = bp;
2926                 }
2927
2928                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2929                                       sizeof(struct bnxt_rx_ring_info),
2930                                       GFP_KERNEL);
2931                 if (!bp->rx_ring)
2932                         return -ENOMEM;
2933
2934                 for (i = 0; i < bp->rx_nr_rings; i++) {
2935                         bp->rx_ring[i].bnapi = bp->bnapi[i];
2936                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2937                 }
2938
2939                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2940                                       sizeof(struct bnxt_tx_ring_info),
2941                                       GFP_KERNEL);
2942                 if (!bp->tx_ring)
2943                         return -ENOMEM;
2944
2945                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2946                         j = 0;
2947                 else
2948                         j = bp->rx_nr_rings;
2949
2950                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2951                         bp->tx_ring[i].bnapi = bp->bnapi[j];
2952                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2953                 }
2954
2955                 rc = bnxt_alloc_stats(bp);
2956                 if (rc)
2957                         goto alloc_mem_err;
2958
2959                 rc = bnxt_alloc_ntp_fltrs(bp);
2960                 if (rc)
2961                         goto alloc_mem_err;
2962
2963                 rc = bnxt_alloc_vnics(bp);
2964                 if (rc)
2965                         goto alloc_mem_err;
2966         }
2967
2968         bnxt_init_ring_struct(bp);
2969
2970         rc = bnxt_alloc_rx_rings(bp);
2971         if (rc)
2972                 goto alloc_mem_err;
2973
2974         rc = bnxt_alloc_tx_rings(bp);
2975         if (rc)
2976                 goto alloc_mem_err;
2977
2978         rc = bnxt_alloc_cp_rings(bp);
2979         if (rc)
2980                 goto alloc_mem_err;
2981
2982         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2983                                   BNXT_VNIC_UCAST_FLAG;
2984         rc = bnxt_alloc_vnic_attributes(bp);
2985         if (rc)
2986                 goto alloc_mem_err;
2987         return 0;
2988
2989 alloc_mem_err:
2990         bnxt_free_mem(bp, true);
2991         return rc;
2992 }
2993
2994 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2995                             u16 cmpl_ring, u16 target_id)
2996 {
2997         struct input *req = request;
2998
2999         req->req_type = cpu_to_le16(req_type);
3000         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3001         req->target_id = cpu_to_le16(target_id);
3002         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3003 }
3004
3005 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3006                                  int timeout, bool silent)
3007 {
3008         int i, intr_process, rc, tmo_count;
3009         struct input *req = msg;
3010         u32 *data = msg;
3011         __le32 *resp_len, *valid;
3012         u16 cp_ring_id, len = 0;
3013         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3014
3015         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3016         memset(resp, 0, PAGE_SIZE);
3017         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3018         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3019
3020         /* Write request msg to hwrm channel */
3021         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3022
3023         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
3024                 writel(0, bp->bar0 + i);
3025
3026         /* currently supports only one outstanding message */
3027         if (intr_process)
3028                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3029
3030         /* Ring channel doorbell */
3031         writel(1, bp->bar0 + 0x100);
3032
3033         if (!timeout)
3034                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3035
3036         i = 0;
3037         tmo_count = timeout * 40;
3038         if (intr_process) {
3039                 /* Wait until hwrm response cmpl interrupt is processed */
3040                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3041                        i++ < tmo_count) {
3042                         usleep_range(25, 40);
3043                 }
3044
3045                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3046                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3047                                    le16_to_cpu(req->req_type));
3048                         return -1;
3049                 }
3050         } else {
3051                 /* Check if response len is updated */
3052                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3053                 for (i = 0; i < tmo_count; i++) {
3054                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3055                               HWRM_RESP_LEN_SFT;
3056                         if (len)
3057                                 break;
3058                         usleep_range(25, 40);
3059                 }
3060
3061                 if (i >= tmo_count) {
3062                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3063                                    timeout, le16_to_cpu(req->req_type),
3064                                    le16_to_cpu(req->seq_id), len);
3065                         return -1;
3066                 }
3067
3068                 /* Last word of resp contains valid bit */
3069                 valid = bp->hwrm_cmd_resp_addr + len - 4;
3070                 for (i = 0; i < 5; i++) {
3071                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3072                                 break;
3073                         udelay(1);
3074                 }
3075
3076                 if (i >= 5) {
3077                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3078                                    timeout, le16_to_cpu(req->req_type),
3079                                    le16_to_cpu(req->seq_id), len, *valid);
3080                         return -1;
3081                 }
3082         }
3083
3084         rc = le16_to_cpu(resp->error_code);
3085         if (rc && !silent)
3086                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3087                            le16_to_cpu(resp->req_type),
3088                            le16_to_cpu(resp->seq_id), rc);
3089         return rc;
3090 }
3091
3092 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3093 {
3094         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3095 }
3096
3097 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3098 {
3099         int rc;
3100
3101         mutex_lock(&bp->hwrm_cmd_lock);
3102         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3103         mutex_unlock(&bp->hwrm_cmd_lock);
3104         return rc;
3105 }
3106
3107 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3108                              int timeout)
3109 {
3110         int rc;
3111
3112         mutex_lock(&bp->hwrm_cmd_lock);
3113         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3114         mutex_unlock(&bp->hwrm_cmd_lock);
3115         return rc;
3116 }
3117
3118 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3119 {
3120         struct hwrm_func_drv_rgtr_input req = {0};
3121         int i;
3122         DECLARE_BITMAP(async_events_bmap, 256);
3123         u32 *events = (u32 *)async_events_bmap;
3124
3125         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3126
3127         req.enables =
3128                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3129                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
3130                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3131
3132         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3133         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3134                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3135
3136         for (i = 0; i < 8; i++)
3137                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3138
3139         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3140         req.ver_maj = DRV_VER_MAJ;
3141         req.ver_min = DRV_VER_MIN;
3142         req.ver_upd = DRV_VER_UPD;
3143
3144         if (BNXT_PF(bp)) {
3145                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3146                 u32 *data = (u32 *)vf_req_snif_bmap;
3147
3148                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3149                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3150                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3151
3152                 for (i = 0; i < 8; i++)
3153                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3154
3155                 req.enables |=
3156                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3157         }
3158
3159         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3160 }
3161
3162 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3163 {
3164         struct hwrm_func_drv_unrgtr_input req = {0};
3165
3166         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3167         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3168 }
3169
3170 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3171 {
3172         u32 rc = 0;
3173         struct hwrm_tunnel_dst_port_free_input req = {0};
3174
3175         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3176         req.tunnel_type = tunnel_type;
3177
3178         switch (tunnel_type) {
3179         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3180                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3181                 break;
3182         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3183                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3184                 break;
3185         default:
3186                 break;
3187         }
3188
3189         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3190         if (rc)
3191                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3192                            rc);
3193         return rc;
3194 }
3195
3196 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3197                                            u8 tunnel_type)
3198 {
3199         u32 rc = 0;
3200         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3201         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3202
3203         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3204
3205         req.tunnel_type = tunnel_type;
3206         req.tunnel_dst_port_val = port;
3207
3208         mutex_lock(&bp->hwrm_cmd_lock);
3209         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3210         if (rc) {
3211                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3212                            rc);
3213                 goto err_out;
3214         }
3215
3216         switch (tunnel_type) {
3217         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3218                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3219                 break;
3220         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3221                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3222                 break;
3223         default:
3224                 break;
3225         }
3226
3227 err_out:
3228         mutex_unlock(&bp->hwrm_cmd_lock);
3229         return rc;
3230 }
3231
3232 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3233 {
3234         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3235         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3236
3237         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3238         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3239
3240         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3241         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3242         req.mask = cpu_to_le32(vnic->rx_mask);
3243         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3244 }
3245
3246 #ifdef CONFIG_RFS_ACCEL
3247 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3248                                             struct bnxt_ntuple_filter *fltr)
3249 {
3250         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3251
3252         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3253         req.ntuple_filter_id = fltr->filter_id;
3254         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3255 }
3256
3257 #define BNXT_NTP_FLTR_FLAGS                                     \
3258         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3259          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3260          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3261          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3262          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3263          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3264          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3265          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3266          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3267          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3268          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3269          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3270          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3271          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3272
3273 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3274                                              struct bnxt_ntuple_filter *fltr)
3275 {
3276         int rc = 0;
3277         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3278         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3279                 bp->hwrm_cmd_resp_addr;
3280         struct flow_keys *keys = &fltr->fkeys;
3281         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3282
3283         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3284         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3285
3286         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3287
3288         req.ethertype = htons(ETH_P_IP);
3289         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3290         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3291         req.ip_protocol = keys->basic.ip_proto;
3292
3293         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3294         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3295         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3296         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3297
3298         req.src_port = keys->ports.src;
3299         req.src_port_mask = cpu_to_be16(0xffff);
3300         req.dst_port = keys->ports.dst;
3301         req.dst_port_mask = cpu_to_be16(0xffff);
3302
3303         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3304         mutex_lock(&bp->hwrm_cmd_lock);
3305         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3306         if (!rc)
3307                 fltr->filter_id = resp->ntuple_filter_id;
3308         mutex_unlock(&bp->hwrm_cmd_lock);
3309         return rc;
3310 }
3311 #endif
3312
3313 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3314                                      u8 *mac_addr)
3315 {
3316         u32 rc = 0;
3317         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3318         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3319
3320         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3321         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3322         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3323                 req.flags |=
3324                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3325         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3326         req.enables =
3327                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3328                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3329                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3330         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3331         req.l2_addr_mask[0] = 0xff;
3332         req.l2_addr_mask[1] = 0xff;
3333         req.l2_addr_mask[2] = 0xff;
3334         req.l2_addr_mask[3] = 0xff;
3335         req.l2_addr_mask[4] = 0xff;
3336         req.l2_addr_mask[5] = 0xff;
3337
3338         mutex_lock(&bp->hwrm_cmd_lock);
3339         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3340         if (!rc)
3341                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3342                                                         resp->l2_filter_id;
3343         mutex_unlock(&bp->hwrm_cmd_lock);
3344         return rc;
3345 }
3346
3347 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3348 {
3349         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3350         int rc = 0;
3351
3352         /* Any associated ntuple filters will also be cleared by firmware. */
3353         mutex_lock(&bp->hwrm_cmd_lock);
3354         for (i = 0; i < num_of_vnics; i++) {
3355                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3356
3357                 for (j = 0; j < vnic->uc_filter_count; j++) {
3358                         struct hwrm_cfa_l2_filter_free_input req = {0};
3359
3360                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3361                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3362
3363                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3364
3365                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3366                                                 HWRM_CMD_TIMEOUT);
3367                 }
3368                 vnic->uc_filter_count = 0;
3369         }
3370         mutex_unlock(&bp->hwrm_cmd_lock);
3371
3372         return rc;
3373 }
3374
3375 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3376 {
3377         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3378         struct hwrm_vnic_tpa_cfg_input req = {0};
3379
3380         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3381
3382         if (tpa_flags) {
3383                 u16 mss = bp->dev->mtu - 40;
3384                 u32 nsegs, n, segs = 0, flags;
3385
3386                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3387                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3388                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3389                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3390                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3391                 if (tpa_flags & BNXT_FLAG_GRO)
3392                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3393
3394                 req.flags = cpu_to_le32(flags);
3395
3396                 req.enables =
3397                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3398                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3399                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3400
3401                 /* Number of segs are log2 units, and first packet is not
3402                  * included as part of this units.
3403                  */
3404                 if (mss <= BNXT_RX_PAGE_SIZE) {
3405                         n = BNXT_RX_PAGE_SIZE / mss;
3406                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3407                 } else {
3408                         n = mss / BNXT_RX_PAGE_SIZE;
3409                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3410                                 n++;
3411                         nsegs = (MAX_SKB_FRAGS - n) / n;
3412                 }
3413
3414                 segs = ilog2(nsegs);
3415                 req.max_agg_segs = cpu_to_le16(segs);
3416                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3417
3418                 req.min_agg_len = cpu_to_le32(512);
3419         }
3420         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3421
3422         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3423 }
3424
3425 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3426 {
3427         u32 i, j, max_rings;
3428         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3429         struct hwrm_vnic_rss_cfg_input req = {0};
3430
3431         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3432                 return 0;
3433
3434         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3435         if (set_rss) {
3436                 vnic->hash_type = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
3437                                   VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
3438                                   VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
3439                                   VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
3440
3441                 req.hash_type = cpu_to_le32(vnic->hash_type);
3442
3443                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3444                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3445                                 max_rings = bp->rx_nr_rings - 1;
3446                         else
3447                                 max_rings = bp->rx_nr_rings;
3448                 } else {
3449                         max_rings = 1;
3450                 }
3451
3452                 /* Fill the RSS indirection table with ring group ids */
3453                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3454                         if (j == max_rings)
3455                                 j = 0;
3456                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3457                 }
3458
3459                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3460                 req.hash_key_tbl_addr =
3461                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3462         }
3463         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3464         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3465 }
3466
3467 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3468 {
3469         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3470         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3471
3472         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3473         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3474                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3475                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3476         req.enables =
3477                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3478                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3479         /* thresholds not implemented in firmware yet */
3480         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3481         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3482         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3483         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3484 }
3485
3486 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3487                                         u16 ctx_idx)
3488 {
3489         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3490
3491         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3492         req.rss_cos_lb_ctx_id =
3493                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3494
3495         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3496         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3497 }
3498
3499 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3500 {
3501         int i, j;
3502
3503         for (i = 0; i < bp->nr_vnics; i++) {
3504                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3505
3506                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3507                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3508                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3509                 }
3510         }
3511         bp->rsscos_nr_ctxs = 0;
3512 }
3513
3514 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3515 {
3516         int rc;
3517         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3518         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3519                                                 bp->hwrm_cmd_resp_addr;
3520
3521         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3522                                -1);
3523
3524         mutex_lock(&bp->hwrm_cmd_lock);
3525         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3526         if (!rc)
3527                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3528                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3529         mutex_unlock(&bp->hwrm_cmd_lock);
3530
3531         return rc;
3532 }
3533
3534 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3535 {
3536         unsigned int ring = 0, grp_idx;
3537         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3538         struct hwrm_vnic_cfg_input req = {0};
3539         u16 def_vlan = 0;
3540
3541         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3542
3543         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3544         /* Only RSS support for now TBD: COS & LB */
3545         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3546                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3547                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3548                                            VNIC_CFG_REQ_ENABLES_MRU);
3549         } else {
3550                 req.rss_rule = cpu_to_le16(0xffff);
3551         }
3552
3553         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3554             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3555                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3556                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3557         } else {
3558                 req.cos_rule = cpu_to_le16(0xffff);
3559         }
3560
3561         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3562                 ring = 0;
3563         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3564                 ring = vnic_id - 1;
3565         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3566                 ring = bp->rx_nr_rings - 1;
3567
3568         grp_idx = bp->rx_ring[ring].bnapi->index;
3569         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3570         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3571
3572         req.lb_rule = cpu_to_le16(0xffff);
3573         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3574                               VLAN_HLEN);
3575
3576 #ifdef CONFIG_BNXT_SRIOV
3577         if (BNXT_VF(bp))
3578                 def_vlan = bp->vf.vlan;
3579 #endif
3580         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3581                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3582
3583         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3584 }
3585
3586 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3587 {
3588         u32 rc = 0;
3589
3590         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3591                 struct hwrm_vnic_free_input req = {0};
3592
3593                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3594                 req.vnic_id =
3595                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3596
3597                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3598                 if (rc)
3599                         return rc;
3600                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3601         }
3602         return rc;
3603 }
3604
3605 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3606 {
3607         u16 i;
3608
3609         for (i = 0; i < bp->nr_vnics; i++)
3610                 bnxt_hwrm_vnic_free_one(bp, i);
3611 }
3612
3613 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3614                                 unsigned int start_rx_ring_idx,
3615                                 unsigned int nr_rings)
3616 {
3617         int rc = 0;
3618         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3619         struct hwrm_vnic_alloc_input req = {0};
3620         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3621
3622         /* map ring groups to this vnic */
3623         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3624                 grp_idx = bp->rx_ring[i].bnapi->index;
3625                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3626                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3627                                    j, nr_rings);
3628                         break;
3629                 }
3630                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3631                                         bp->grp_info[grp_idx].fw_grp_id;
3632         }
3633
3634         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3635         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3636         if (vnic_id == 0)
3637                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3638
3639         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3640
3641         mutex_lock(&bp->hwrm_cmd_lock);
3642         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3643         if (!rc)
3644                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3645         mutex_unlock(&bp->hwrm_cmd_lock);
3646         return rc;
3647 }
3648
3649 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3650 {
3651         u16 i;
3652         u32 rc = 0;
3653
3654         mutex_lock(&bp->hwrm_cmd_lock);
3655         for (i = 0; i < bp->rx_nr_rings; i++) {
3656                 struct hwrm_ring_grp_alloc_input req = {0};
3657                 struct hwrm_ring_grp_alloc_output *resp =
3658                                         bp->hwrm_cmd_resp_addr;
3659                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3660
3661                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3662
3663                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3664                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3665                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3666                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3667
3668                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3669                                         HWRM_CMD_TIMEOUT);
3670                 if (rc)
3671                         break;
3672
3673                 bp->grp_info[grp_idx].fw_grp_id =
3674                         le32_to_cpu(resp->ring_group_id);
3675         }
3676         mutex_unlock(&bp->hwrm_cmd_lock);
3677         return rc;
3678 }
3679
3680 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3681 {
3682         u16 i;
3683         u32 rc = 0;
3684         struct hwrm_ring_grp_free_input req = {0};
3685
3686         if (!bp->grp_info)
3687                 return 0;
3688
3689         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3690
3691         mutex_lock(&bp->hwrm_cmd_lock);
3692         for (i = 0; i < bp->cp_nr_rings; i++) {
3693                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3694                         continue;
3695                 req.ring_group_id =
3696                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3697
3698                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3699                                         HWRM_CMD_TIMEOUT);
3700                 if (rc)
3701                         break;
3702                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3703         }
3704         mutex_unlock(&bp->hwrm_cmd_lock);
3705         return rc;
3706 }
3707
3708 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3709                                     struct bnxt_ring_struct *ring,
3710                                     u32 ring_type, u32 map_index,
3711                                     u32 stats_ctx_id)
3712 {
3713         int rc = 0, err = 0;
3714         struct hwrm_ring_alloc_input req = {0};
3715         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3716         u16 ring_id;
3717
3718         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3719
3720         req.enables = 0;
3721         if (ring->nr_pages > 1) {
3722                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3723                 /* Page size is in log2 units */
3724                 req.page_size = BNXT_PAGE_SHIFT;
3725                 req.page_tbl_depth = 1;
3726         } else {
3727                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3728         }
3729         req.fbo = 0;
3730         /* Association of ring index with doorbell index and MSIX number */
3731         req.logical_id = cpu_to_le16(map_index);
3732
3733         switch (ring_type) {
3734         case HWRM_RING_ALLOC_TX:
3735                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3736                 /* Association of transmit ring with completion ring */
3737                 req.cmpl_ring_id =
3738                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3739                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3740                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3741                 req.queue_id = cpu_to_le16(ring->queue_id);
3742                 break;
3743         case HWRM_RING_ALLOC_RX:
3744                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3745                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3746                 break;
3747         case HWRM_RING_ALLOC_AGG:
3748                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3749                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3750                 break;
3751         case HWRM_RING_ALLOC_CMPL:
3752                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3753                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3754                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3755                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3756                 break;
3757         default:
3758                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3759                            ring_type);
3760                 return -1;
3761         }
3762
3763         mutex_lock(&bp->hwrm_cmd_lock);
3764         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3765         err = le16_to_cpu(resp->error_code);
3766         ring_id = le16_to_cpu(resp->ring_id);
3767         mutex_unlock(&bp->hwrm_cmd_lock);
3768
3769         if (rc || err) {
3770                 switch (ring_type) {
3771                 case RING_FREE_REQ_RING_TYPE_CMPL:
3772                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3773                                    rc, err);
3774                         return -1;
3775
3776                 case RING_FREE_REQ_RING_TYPE_RX:
3777                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3778                                    rc, err);
3779                         return -1;
3780
3781                 case RING_FREE_REQ_RING_TYPE_TX:
3782                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3783                                    rc, err);
3784                         return -1;
3785
3786                 default:
3787                         netdev_err(bp->dev, "Invalid ring\n");
3788                         return -1;
3789                 }
3790         }
3791         ring->fw_ring_id = ring_id;
3792         return rc;
3793 }
3794
3795 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3796 {
3797         int i, rc = 0;
3798
3799         for (i = 0; i < bp->cp_nr_rings; i++) {
3800                 struct bnxt_napi *bnapi = bp->bnapi[i];
3801                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3802                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3803
3804                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3805                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3806                                               INVALID_STATS_CTX_ID);
3807                 if (rc)
3808                         goto err_out;
3809                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3810                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3811         }
3812
3813         for (i = 0; i < bp->tx_nr_rings; i++) {
3814                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3815                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3816                 u32 map_idx = txr->bnapi->index;
3817                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3818
3819                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3820                                               map_idx, fw_stats_ctx);
3821                 if (rc)
3822                         goto err_out;
3823                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3824         }
3825
3826         for (i = 0; i < bp->rx_nr_rings; i++) {
3827                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3828                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3829                 u32 map_idx = rxr->bnapi->index;
3830
3831                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3832                                               map_idx, INVALID_STATS_CTX_ID);
3833                 if (rc)
3834                         goto err_out;
3835                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3836                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3837                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3838         }
3839
3840         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3841                 for (i = 0; i < bp->rx_nr_rings; i++) {
3842                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3843                         struct bnxt_ring_struct *ring =
3844                                                 &rxr->rx_agg_ring_struct;
3845                         u32 grp_idx = rxr->bnapi->index;
3846                         u32 map_idx = grp_idx + bp->rx_nr_rings;
3847
3848                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3849                                                       HWRM_RING_ALLOC_AGG,
3850                                                       map_idx,
3851                                                       INVALID_STATS_CTX_ID);
3852                         if (rc)
3853                                 goto err_out;
3854
3855                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3856                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3857                                rxr->rx_agg_doorbell);
3858                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3859                 }
3860         }
3861 err_out:
3862         return rc;
3863 }
3864
3865 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3866                                    struct bnxt_ring_struct *ring,
3867                                    u32 ring_type, int cmpl_ring_id)
3868 {
3869         int rc;
3870         struct hwrm_ring_free_input req = {0};
3871         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3872         u16 error_code;
3873
3874         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3875         req.ring_type = ring_type;
3876         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3877
3878         mutex_lock(&bp->hwrm_cmd_lock);
3879         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3880         error_code = le16_to_cpu(resp->error_code);
3881         mutex_unlock(&bp->hwrm_cmd_lock);
3882
3883         if (rc || error_code) {
3884                 switch (ring_type) {
3885                 case RING_FREE_REQ_RING_TYPE_CMPL:
3886                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3887                                    rc);
3888                         return rc;
3889                 case RING_FREE_REQ_RING_TYPE_RX:
3890                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3891                                    rc);
3892                         return rc;
3893                 case RING_FREE_REQ_RING_TYPE_TX:
3894                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3895                                    rc);
3896                         return rc;
3897                 default:
3898                         netdev_err(bp->dev, "Invalid ring\n");
3899                         return -1;
3900                 }
3901         }
3902         return 0;
3903 }
3904
3905 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3906 {
3907         int i;
3908
3909         if (!bp->bnapi)
3910                 return;
3911
3912         for (i = 0; i < bp->tx_nr_rings; i++) {
3913                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3914                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3915                 u32 grp_idx = txr->bnapi->index;
3916                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3917
3918                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3919                         hwrm_ring_free_send_msg(bp, ring,
3920                                                 RING_FREE_REQ_RING_TYPE_TX,
3921                                                 close_path ? cmpl_ring_id :
3922                                                 INVALID_HW_RING_ID);
3923                         ring->fw_ring_id = INVALID_HW_RING_ID;
3924                 }
3925         }
3926
3927         for (i = 0; i < bp->rx_nr_rings; i++) {
3928                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3929                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3930                 u32 grp_idx = rxr->bnapi->index;
3931                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3932
3933                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3934                         hwrm_ring_free_send_msg(bp, ring,
3935                                                 RING_FREE_REQ_RING_TYPE_RX,
3936                                                 close_path ? cmpl_ring_id :
3937                                                 INVALID_HW_RING_ID);
3938                         ring->fw_ring_id = INVALID_HW_RING_ID;
3939                         bp->grp_info[grp_idx].rx_fw_ring_id =
3940                                 INVALID_HW_RING_ID;
3941                 }
3942         }
3943
3944         for (i = 0; i < bp->rx_nr_rings; i++) {
3945                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3946                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3947                 u32 grp_idx = rxr->bnapi->index;
3948                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3949
3950                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3951                         hwrm_ring_free_send_msg(bp, ring,
3952                                                 RING_FREE_REQ_RING_TYPE_RX,
3953                                                 close_path ? cmpl_ring_id :
3954                                                 INVALID_HW_RING_ID);
3955                         ring->fw_ring_id = INVALID_HW_RING_ID;
3956                         bp->grp_info[grp_idx].agg_fw_ring_id =
3957                                 INVALID_HW_RING_ID;
3958                 }
3959         }
3960
3961         for (i = 0; i < bp->cp_nr_rings; i++) {
3962                 struct bnxt_napi *bnapi = bp->bnapi[i];
3963                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3964                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3965
3966                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3967                         hwrm_ring_free_send_msg(bp, ring,
3968                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3969                                                 INVALID_HW_RING_ID);
3970                         ring->fw_ring_id = INVALID_HW_RING_ID;
3971                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3972                 }
3973         }
3974 }
3975
3976 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3977         u32 buf_tmrs, u16 flags,
3978         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3979 {
3980         req->flags = cpu_to_le16(flags);
3981         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3982         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3983         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3984         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3985         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3986         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3987         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3988         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3989 }
3990
3991 int bnxt_hwrm_set_coal(struct bnxt *bp)
3992 {
3993         int i, rc = 0;
3994         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3995                                                            req_tx = {0}, *req;
3996         u16 max_buf, max_buf_irq;
3997         u16 buf_tmr, buf_tmr_irq;
3998         u32 flags;
3999
4000         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4001                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4002         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4003                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4004
4005         /* Each rx completion (2 records) should be DMAed immediately.
4006          * DMA 1/4 of the completion buffers at a time.
4007          */
4008         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4009         /* max_buf must not be zero */
4010         max_buf = clamp_t(u16, max_buf, 1, 63);
4011         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4012         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4013         /* buf timer set to 1/4 of interrupt timer */
4014         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4015         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4016         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4017
4018         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4019
4020         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
4021          * if coal_ticks is less than 25 us.
4022          */
4023         if (bp->rx_coal_ticks < 25)
4024                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4025
4026         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4027                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4028
4029         /* max_buf must not be zero */
4030         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4031         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4032         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4033         /* buf timer set to 1/4 of interrupt timer */
4034         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4035         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4036         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4037
4038         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4039         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4040                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4041
4042         mutex_lock(&bp->hwrm_cmd_lock);
4043         for (i = 0; i < bp->cp_nr_rings; i++) {
4044                 struct bnxt_napi *bnapi = bp->bnapi[i];
4045
4046                 req = &req_rx;
4047                 if (!bnapi->rx_ring)
4048                         req = &req_tx;
4049                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4050
4051                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4052                                         HWRM_CMD_TIMEOUT);
4053                 if (rc)
4054                         break;
4055         }
4056         mutex_unlock(&bp->hwrm_cmd_lock);
4057         return rc;
4058 }
4059
4060 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4061 {
4062         int rc = 0, i;
4063         struct hwrm_stat_ctx_free_input req = {0};
4064
4065         if (!bp->bnapi)
4066                 return 0;
4067
4068         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4069                 return 0;
4070
4071         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4072
4073         mutex_lock(&bp->hwrm_cmd_lock);
4074         for (i = 0; i < bp->cp_nr_rings; i++) {
4075                 struct bnxt_napi *bnapi = bp->bnapi[i];
4076                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4077
4078                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4079                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4080
4081                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4082                                                 HWRM_CMD_TIMEOUT);
4083                         if (rc)
4084                                 break;
4085
4086                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4087                 }
4088         }
4089         mutex_unlock(&bp->hwrm_cmd_lock);
4090         return rc;
4091 }
4092
4093 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4094 {
4095         int rc = 0, i;
4096         struct hwrm_stat_ctx_alloc_input req = {0};
4097         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4098
4099         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4100                 return 0;
4101
4102         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4103
4104         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4105
4106         mutex_lock(&bp->hwrm_cmd_lock);
4107         for (i = 0; i < bp->cp_nr_rings; i++) {
4108                 struct bnxt_napi *bnapi = bp->bnapi[i];
4109                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4110
4111                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4112
4113                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4114                                         HWRM_CMD_TIMEOUT);
4115                 if (rc)
4116                         break;
4117
4118                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4119
4120                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4121         }
4122         mutex_unlock(&bp->hwrm_cmd_lock);
4123         return rc;
4124 }
4125
4126 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4127 {
4128         struct hwrm_func_qcfg_input req = {0};
4129         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4130         int rc;
4131
4132         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4133         req.fid = cpu_to_le16(0xffff);
4134         mutex_lock(&bp->hwrm_cmd_lock);
4135         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4136         if (rc)
4137                 goto func_qcfg_exit;
4138
4139 #ifdef CONFIG_BNXT_SRIOV
4140         if (BNXT_VF(bp)) {
4141                 struct bnxt_vf_info *vf = &bp->vf;
4142
4143                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4144         }
4145 #endif
4146         switch (resp->port_partition_type) {
4147         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4148         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4149         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4150                 bp->port_partition_type = resp->port_partition_type;
4151                 break;
4152         }
4153
4154 func_qcfg_exit:
4155         mutex_unlock(&bp->hwrm_cmd_lock);
4156         return rc;
4157 }
4158
4159 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4160 {
4161         int rc = 0;
4162         struct hwrm_func_qcaps_input req = {0};
4163         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4164
4165         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4166         req.fid = cpu_to_le16(0xffff);
4167
4168         mutex_lock(&bp->hwrm_cmd_lock);
4169         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4170         if (rc)
4171                 goto hwrm_func_qcaps_exit;
4172
4173         bp->tx_push_thresh = 0;
4174         if (resp->flags &
4175             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4176                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4177
4178         if (BNXT_PF(bp)) {
4179                 struct bnxt_pf_info *pf = &bp->pf;
4180
4181                 pf->fw_fid = le16_to_cpu(resp->fid);
4182                 pf->port_id = le16_to_cpu(resp->port_id);
4183                 bp->dev->dev_port = pf->port_id;
4184                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4185                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4186                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4187                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4188                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4189                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4190                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4191                 if (!pf->max_hw_ring_grps)
4192                         pf->max_hw_ring_grps = pf->max_tx_rings;
4193                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4194                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4195                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4196                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4197                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4198                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4199                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4200                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4201                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4202                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4203                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4204         } else {
4205 #ifdef CONFIG_BNXT_SRIOV
4206                 struct bnxt_vf_info *vf = &bp->vf;
4207
4208                 vf->fw_fid = le16_to_cpu(resp->fid);
4209
4210                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4211                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4212                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4213                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4214                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4215                 if (!vf->max_hw_ring_grps)
4216                         vf->max_hw_ring_grps = vf->max_tx_rings;
4217                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4218                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4219                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4220
4221                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4222                 mutex_unlock(&bp->hwrm_cmd_lock);
4223
4224                 if (is_valid_ether_addr(vf->mac_addr)) {
4225                         /* overwrite netdev dev_adr with admin VF MAC */
4226                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4227                 } else {
4228                         random_ether_addr(bp->dev->dev_addr);
4229                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4230                 }
4231                 return rc;
4232 #endif
4233         }
4234
4235 hwrm_func_qcaps_exit:
4236         mutex_unlock(&bp->hwrm_cmd_lock);
4237         return rc;
4238 }
4239
4240 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4241 {
4242         struct hwrm_func_reset_input req = {0};
4243
4244         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4245         req.enables = 0;
4246
4247         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4248 }
4249
4250 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4251 {
4252         int rc = 0;
4253         struct hwrm_queue_qportcfg_input req = {0};
4254         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4255         u8 i, *qptr;
4256
4257         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4258
4259         mutex_lock(&bp->hwrm_cmd_lock);
4260         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4261         if (rc)
4262                 goto qportcfg_exit;
4263
4264         if (!resp->max_configurable_queues) {
4265                 rc = -EINVAL;
4266                 goto qportcfg_exit;
4267         }
4268         bp->max_tc = resp->max_configurable_queues;
4269         if (bp->max_tc > BNXT_MAX_QUEUE)
4270                 bp->max_tc = BNXT_MAX_QUEUE;
4271
4272         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4273                 bp->max_tc = 1;
4274
4275         qptr = &resp->queue_id0;
4276         for (i = 0; i < bp->max_tc; i++) {
4277                 bp->q_info[i].queue_id = *qptr++;
4278                 bp->q_info[i].queue_profile = *qptr++;
4279         }
4280
4281 qportcfg_exit:
4282         mutex_unlock(&bp->hwrm_cmd_lock);
4283         return rc;
4284 }
4285
4286 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4287 {
4288         int rc;
4289         struct hwrm_ver_get_input req = {0};
4290         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4291
4292         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4293         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4294         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4295         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4296         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4297         mutex_lock(&bp->hwrm_cmd_lock);
4298         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4299         if (rc)
4300                 goto hwrm_ver_get_exit;
4301
4302         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4303
4304         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4305                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4306         if (resp->hwrm_intf_maj < 1) {
4307                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4308                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4309                             resp->hwrm_intf_upd);
4310                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4311         }
4312         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4313                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4314                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4315
4316         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4317         if (!bp->hwrm_cmd_timeout)
4318                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4319
4320         if (resp->hwrm_intf_maj >= 1)
4321                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4322
4323         bp->chip_num = le16_to_cpu(resp->chip_num);
4324         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4325             !resp->chip_metal)
4326                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4327
4328 hwrm_ver_get_exit:
4329         mutex_unlock(&bp->hwrm_cmd_lock);
4330         return rc;
4331 }
4332
4333 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4334 {
4335 #if IS_ENABLED(CONFIG_RTC_LIB)
4336         struct hwrm_fw_set_time_input req = {0};
4337         struct rtc_time tm;
4338         struct timeval tv;
4339
4340         if (bp->hwrm_spec_code < 0x10400)
4341                 return -EOPNOTSUPP;
4342
4343         do_gettimeofday(&tv);
4344         rtc_time_to_tm(tv.tv_sec, &tm);
4345         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4346         req.year = cpu_to_le16(1900 + tm.tm_year);
4347         req.month = 1 + tm.tm_mon;
4348         req.day = tm.tm_mday;
4349         req.hour = tm.tm_hour;
4350         req.minute = tm.tm_min;
4351         req.second = tm.tm_sec;
4352         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4353 #else
4354         return -EOPNOTSUPP;
4355 #endif
4356 }
4357
4358 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4359 {
4360         int rc;
4361         struct bnxt_pf_info *pf = &bp->pf;
4362         struct hwrm_port_qstats_input req = {0};
4363
4364         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4365                 return 0;
4366
4367         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4368         req.port_id = cpu_to_le16(pf->port_id);
4369         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4370         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4371         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4372         return rc;
4373 }
4374
4375 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4376 {
4377         if (bp->vxlan_port_cnt) {
4378                 bnxt_hwrm_tunnel_dst_port_free(
4379                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4380         }
4381         bp->vxlan_port_cnt = 0;
4382         if (bp->nge_port_cnt) {
4383                 bnxt_hwrm_tunnel_dst_port_free(
4384                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4385         }
4386         bp->nge_port_cnt = 0;
4387 }
4388
4389 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4390 {
4391         int rc, i;
4392         u32 tpa_flags = 0;
4393
4394         if (set_tpa)
4395                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4396         for (i = 0; i < bp->nr_vnics; i++) {
4397                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4398                 if (rc) {
4399                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4400                                    rc, i);
4401                         return rc;
4402                 }
4403         }
4404         return 0;
4405 }
4406
4407 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4408 {
4409         int i;
4410
4411         for (i = 0; i < bp->nr_vnics; i++)
4412                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4413 }
4414
4415 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4416                                     bool irq_re_init)
4417 {
4418         if (bp->vnic_info) {
4419                 bnxt_hwrm_clear_vnic_filter(bp);
4420                 /* clear all RSS setting before free vnic ctx */
4421                 bnxt_hwrm_clear_vnic_rss(bp);
4422                 bnxt_hwrm_vnic_ctx_free(bp);
4423                 /* before free the vnic, undo the vnic tpa settings */
4424                 if (bp->flags & BNXT_FLAG_TPA)
4425                         bnxt_set_tpa(bp, false);
4426                 bnxt_hwrm_vnic_free(bp);
4427         }
4428         bnxt_hwrm_ring_free(bp, close_path);
4429         bnxt_hwrm_ring_grp_free(bp);
4430         if (irq_re_init) {
4431                 bnxt_hwrm_stat_ctx_free(bp);
4432                 bnxt_hwrm_free_tunnel_ports(bp);
4433         }
4434 }
4435
4436 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4437 {
4438         int rc;
4439
4440         /* allocate context for vnic */
4441         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4442         if (rc) {
4443                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4444                            vnic_id, rc);
4445                 goto vnic_setup_err;
4446         }
4447         bp->rsscos_nr_ctxs++;
4448
4449         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4450                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4451                 if (rc) {
4452                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4453                                    vnic_id, rc);
4454                         goto vnic_setup_err;
4455                 }
4456                 bp->rsscos_nr_ctxs++;
4457         }
4458
4459         /* configure default vnic, ring grp */
4460         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4461         if (rc) {
4462                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4463                            vnic_id, rc);
4464                 goto vnic_setup_err;
4465         }
4466
4467         /* Enable RSS hashing on vnic */
4468         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4469         if (rc) {
4470                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4471                            vnic_id, rc);
4472                 goto vnic_setup_err;
4473         }
4474
4475         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4476                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4477                 if (rc) {
4478                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4479                                    vnic_id, rc);
4480                 }
4481         }
4482
4483 vnic_setup_err:
4484         return rc;
4485 }
4486
4487 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4488 {
4489 #ifdef CONFIG_RFS_ACCEL
4490         int i, rc = 0;
4491
4492         for (i = 0; i < bp->rx_nr_rings; i++) {
4493                 u16 vnic_id = i + 1;
4494                 u16 ring_id = i;
4495
4496                 if (vnic_id >= bp->nr_vnics)
4497                         break;
4498
4499                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4500                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4501                 if (rc) {
4502                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4503                                    vnic_id, rc);
4504                         break;
4505                 }
4506                 rc = bnxt_setup_vnic(bp, vnic_id);
4507                 if (rc)
4508                         break;
4509         }
4510         return rc;
4511 #else
4512         return 0;
4513 #endif
4514 }
4515
4516 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4517 static bool bnxt_promisc_ok(struct bnxt *bp)
4518 {
4519 #ifdef CONFIG_BNXT_SRIOV
4520         if (BNXT_VF(bp) && !bp->vf.vlan)
4521                 return false;
4522 #endif
4523         return true;
4524 }
4525
4526 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4527 {
4528         unsigned int rc = 0;
4529
4530         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4531         if (rc) {
4532                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4533                            rc);
4534                 return rc;
4535         }
4536
4537         rc = bnxt_hwrm_vnic_cfg(bp, 1);
4538         if (rc) {
4539                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4540                            rc);
4541                 return rc;
4542         }
4543         return rc;
4544 }
4545
4546 static int bnxt_cfg_rx_mode(struct bnxt *);
4547 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4548
4549 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4550 {
4551         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4552         int rc = 0;
4553         unsigned int rx_nr_rings = bp->rx_nr_rings;
4554
4555         if (irq_re_init) {
4556                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4557                 if (rc) {
4558                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4559                                    rc);
4560                         goto err_out;
4561                 }
4562         }
4563
4564         rc = bnxt_hwrm_ring_alloc(bp);
4565         if (rc) {
4566                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4567                 goto err_out;
4568         }
4569
4570         rc = bnxt_hwrm_ring_grp_alloc(bp);
4571         if (rc) {
4572                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4573                 goto err_out;
4574         }
4575
4576         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4577                 rx_nr_rings--;
4578
4579         /* default vnic 0 */
4580         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
4581         if (rc) {
4582                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4583                 goto err_out;
4584         }
4585
4586         rc = bnxt_setup_vnic(bp, 0);
4587         if (rc)
4588                 goto err_out;
4589
4590         if (bp->flags & BNXT_FLAG_RFS) {
4591                 rc = bnxt_alloc_rfs_vnics(bp);
4592                 if (rc)
4593                         goto err_out;
4594         }
4595
4596         if (bp->flags & BNXT_FLAG_TPA) {
4597                 rc = bnxt_set_tpa(bp, true);
4598                 if (rc)
4599                         goto err_out;
4600         }
4601
4602         if (BNXT_VF(bp))
4603                 bnxt_update_vf_mac(bp);
4604
4605         /* Filter for default vnic 0 */
4606         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4607         if (rc) {
4608                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4609                 goto err_out;
4610         }
4611         vnic->uc_filter_count = 1;
4612
4613         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4614
4615         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
4616                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4617
4618         if (bp->dev->flags & IFF_ALLMULTI) {
4619                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4620                 vnic->mc_list_count = 0;
4621         } else {
4622                 u32 mask = 0;
4623
4624                 bnxt_mc_list_updated(bp, &mask);
4625                 vnic->rx_mask |= mask;
4626         }
4627
4628         rc = bnxt_cfg_rx_mode(bp);
4629         if (rc)
4630                 goto err_out;
4631
4632         rc = bnxt_hwrm_set_coal(bp);
4633         if (rc)
4634                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4635                                 rc);
4636
4637         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4638                 rc = bnxt_setup_nitroa0_vnic(bp);
4639                 if (rc)
4640                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4641                                    rc);
4642         }
4643
4644         if (BNXT_VF(bp)) {
4645                 bnxt_hwrm_func_qcfg(bp);
4646                 netdev_update_features(bp->dev);
4647         }
4648
4649         return 0;
4650
4651 err_out:
4652         bnxt_hwrm_resource_free(bp, 0, true);
4653
4654         return rc;
4655 }
4656
4657 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4658 {
4659         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4660         return 0;
4661 }
4662
4663 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4664 {
4665         bnxt_init_rx_rings(bp);
4666         bnxt_init_tx_rings(bp);
4667         bnxt_init_ring_grps(bp, irq_re_init);
4668         bnxt_init_vnics(bp);
4669
4670         return bnxt_init_chip(bp, irq_re_init);
4671 }
4672
4673 static void bnxt_disable_int(struct bnxt *bp)
4674 {
4675         int i;
4676
4677         if (!bp->bnapi)
4678                 return;
4679
4680         for (i = 0; i < bp->cp_nr_rings; i++) {
4681                 struct bnxt_napi *bnapi = bp->bnapi[i];
4682                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4683
4684                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4685         }
4686 }
4687
4688 static void bnxt_enable_int(struct bnxt *bp)
4689 {
4690         int i;
4691
4692         atomic_set(&bp->intr_sem, 0);
4693         for (i = 0; i < bp->cp_nr_rings; i++) {
4694                 struct bnxt_napi *bnapi = bp->bnapi[i];
4695                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4696
4697                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4698         }
4699 }
4700
4701 static int bnxt_set_real_num_queues(struct bnxt *bp)
4702 {
4703         int rc;
4704         struct net_device *dev = bp->dev;
4705
4706         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4707         if (rc)
4708                 return rc;
4709
4710         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4711         if (rc)
4712                 return rc;
4713
4714 #ifdef CONFIG_RFS_ACCEL
4715         if (bp->flags & BNXT_FLAG_RFS)
4716                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4717 #endif
4718
4719         return rc;
4720 }
4721
4722 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4723                            bool shared)
4724 {
4725         int _rx = *rx, _tx = *tx;
4726
4727         if (shared) {
4728                 *rx = min_t(int, _rx, max);
4729                 *tx = min_t(int, _tx, max);
4730         } else {
4731                 if (max < 2)
4732                         return -ENOMEM;
4733
4734                 while (_rx + _tx > max) {
4735                         if (_rx > _tx && _rx > 1)
4736                                 _rx--;
4737                         else if (_tx > 1)
4738                                 _tx--;
4739                 }
4740                 *rx = _rx;
4741                 *tx = _tx;
4742         }
4743         return 0;
4744 }
4745
4746 static int bnxt_setup_msix(struct bnxt *bp)
4747 {
4748         struct msix_entry *msix_ent;
4749         struct net_device *dev = bp->dev;
4750         int i, total_vecs, rc = 0, min = 1;
4751         const int len = sizeof(bp->irq_tbl[0].name);
4752
4753         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4754         total_vecs = bp->cp_nr_rings;
4755
4756         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4757         if (!msix_ent)
4758                 return -ENOMEM;
4759
4760         for (i = 0; i < total_vecs; i++) {
4761                 msix_ent[i].entry = i;
4762                 msix_ent[i].vector = 0;
4763         }
4764
4765         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4766                 min = 2;
4767
4768         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4769         if (total_vecs < 0) {
4770                 rc = -ENODEV;
4771                 goto msix_setup_exit;
4772         }
4773
4774         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4775         if (bp->irq_tbl) {
4776                 int tcs;
4777
4778                 /* Trim rings based upon num of vectors allocated */
4779                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4780                                      total_vecs, min == 1);
4781                 if (rc)
4782                         goto msix_setup_exit;
4783
4784                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4785                 tcs = netdev_get_num_tc(dev);
4786                 if (tcs > 1) {
4787                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4788                         if (bp->tx_nr_rings_per_tc == 0) {
4789                                 netdev_reset_tc(dev);
4790                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4791                         } else {
4792                                 int i, off, count;
4793
4794                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4795                                 for (i = 0; i < tcs; i++) {
4796                                         count = bp->tx_nr_rings_per_tc;
4797                                         off = i * count;
4798                                         netdev_set_tc_queue(dev, i, count, off);
4799                                 }
4800                         }
4801                 }
4802                 bp->cp_nr_rings = total_vecs;
4803
4804                 for (i = 0; i < bp->cp_nr_rings; i++) {
4805                         char *attr;
4806
4807                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4808                         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4809                                 attr = "TxRx";
4810                         else if (i < bp->rx_nr_rings)
4811                                 attr = "rx";
4812                         else
4813                                 attr = "tx";
4814
4815                         snprintf(bp->irq_tbl[i].name, len,
4816                                  "%s-%s-%d", dev->name, attr, i);
4817                         bp->irq_tbl[i].handler = bnxt_msix;
4818                 }
4819                 rc = bnxt_set_real_num_queues(bp);
4820                 if (rc)
4821                         goto msix_setup_exit;
4822         } else {
4823                 rc = -ENOMEM;
4824                 goto msix_setup_exit;
4825         }
4826         bp->flags |= BNXT_FLAG_USING_MSIX;
4827         kfree(msix_ent);
4828         return 0;
4829
4830 msix_setup_exit:
4831         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4832         pci_disable_msix(bp->pdev);
4833         kfree(msix_ent);
4834         return rc;
4835 }
4836
4837 static int bnxt_setup_inta(struct bnxt *bp)
4838 {
4839         int rc;
4840         const int len = sizeof(bp->irq_tbl[0].name);
4841
4842         if (netdev_get_num_tc(bp->dev))
4843                 netdev_reset_tc(bp->dev);
4844
4845         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4846         if (!bp->irq_tbl) {
4847                 rc = -ENOMEM;
4848                 return rc;
4849         }
4850         bp->rx_nr_rings = 1;
4851         bp->tx_nr_rings = 1;
4852         bp->cp_nr_rings = 1;
4853         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4854         bp->flags |= BNXT_FLAG_SHARED_RINGS;
4855         bp->irq_tbl[0].vector = bp->pdev->irq;
4856         snprintf(bp->irq_tbl[0].name, len,
4857                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4858         bp->irq_tbl[0].handler = bnxt_inta;
4859         rc = bnxt_set_real_num_queues(bp);
4860         return rc;
4861 }
4862
4863 static int bnxt_setup_int_mode(struct bnxt *bp)
4864 {
4865         int rc = 0;
4866
4867         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4868                 rc = bnxt_setup_msix(bp);
4869
4870         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
4871                 /* fallback to INTA */
4872                 rc = bnxt_setup_inta(bp);
4873         }
4874         return rc;
4875 }
4876
4877 static void bnxt_free_irq(struct bnxt *bp)
4878 {
4879         struct bnxt_irq *irq;
4880         int i;
4881
4882 #ifdef CONFIG_RFS_ACCEL
4883         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4884         bp->dev->rx_cpu_rmap = NULL;
4885 #endif
4886         if (!bp->irq_tbl)
4887                 return;
4888
4889         for (i = 0; i < bp->cp_nr_rings; i++) {
4890                 irq = &bp->irq_tbl[i];
4891                 if (irq->requested)
4892                         free_irq(irq->vector, bp->bnapi[i]);
4893                 irq->requested = 0;
4894         }
4895         if (bp->flags & BNXT_FLAG_USING_MSIX)
4896                 pci_disable_msix(bp->pdev);
4897         kfree(bp->irq_tbl);
4898         bp->irq_tbl = NULL;
4899 }
4900
4901 static int bnxt_request_irq(struct bnxt *bp)
4902 {
4903         int i, j, rc = 0;
4904         unsigned long flags = 0;
4905 #ifdef CONFIG_RFS_ACCEL
4906         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4907 #endif
4908
4909         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4910                 flags = IRQF_SHARED;
4911
4912         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4913                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4914 #ifdef CONFIG_RFS_ACCEL
4915                 if (rmap && bp->bnapi[i]->rx_ring) {
4916                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4917                         if (rc)
4918                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4919                                             j);
4920                         j++;
4921                 }
4922 #endif
4923                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4924                                  bp->bnapi[i]);
4925                 if (rc)
4926                         break;
4927
4928                 irq->requested = 1;
4929         }
4930         return rc;
4931 }
4932
4933 static void bnxt_del_napi(struct bnxt *bp)
4934 {
4935         int i;
4936
4937         if (!bp->bnapi)
4938                 return;
4939
4940         for (i = 0; i < bp->cp_nr_rings; i++) {
4941                 struct bnxt_napi *bnapi = bp->bnapi[i];
4942
4943                 napi_hash_del(&bnapi->napi);
4944                 netif_napi_del(&bnapi->napi);
4945         }
4946         /* We called napi_hash_del() before netif_napi_del(), we need
4947          * to respect an RCU grace period before freeing napi structures.
4948          */
4949         synchronize_net();
4950 }
4951
4952 static void bnxt_init_napi(struct bnxt *bp)
4953 {
4954         int i;
4955         unsigned int cp_nr_rings = bp->cp_nr_rings;
4956         struct bnxt_napi *bnapi;
4957
4958         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4959                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4960                         cp_nr_rings--;
4961                 for (i = 0; i < cp_nr_rings; i++) {
4962                         bnapi = bp->bnapi[i];
4963                         netif_napi_add(bp->dev, &bnapi->napi,
4964                                        bnxt_poll, 64);
4965                 }
4966                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4967                         bnapi = bp->bnapi[cp_nr_rings];
4968                         netif_napi_add(bp->dev, &bnapi->napi,
4969                                        bnxt_poll_nitroa0, 64);
4970                         napi_hash_add(&bnapi->napi);
4971                 }
4972         } else {
4973                 bnapi = bp->bnapi[0];
4974                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4975         }
4976 }
4977
4978 static void bnxt_disable_napi(struct bnxt *bp)
4979 {
4980         int i;
4981
4982         if (!bp->bnapi)
4983                 return;
4984
4985         for (i = 0; i < bp->cp_nr_rings; i++) {
4986                 napi_disable(&bp->bnapi[i]->napi);
4987                 bnxt_disable_poll(bp->bnapi[i]);
4988         }
4989 }
4990
4991 static void bnxt_enable_napi(struct bnxt *bp)
4992 {
4993         int i;
4994
4995         for (i = 0; i < bp->cp_nr_rings; i++) {
4996                 bp->bnapi[i]->in_reset = false;
4997                 bnxt_enable_poll(bp->bnapi[i]);
4998                 napi_enable(&bp->bnapi[i]->napi);
4999         }
5000 }
5001
5002 static void bnxt_tx_disable(struct bnxt *bp)
5003 {
5004         int i;
5005         struct bnxt_tx_ring_info *txr;
5006         struct netdev_queue *txq;
5007
5008         if (bp->tx_ring) {
5009                 for (i = 0; i < bp->tx_nr_rings; i++) {
5010                         txr = &bp->tx_ring[i];
5011                         txq = netdev_get_tx_queue(bp->dev, i);
5012                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
5013                 }
5014         }
5015         /* Stop all TX queues */
5016         netif_tx_disable(bp->dev);
5017         netif_carrier_off(bp->dev);
5018 }
5019
5020 static void bnxt_tx_enable(struct bnxt *bp)
5021 {
5022         int i;
5023         struct bnxt_tx_ring_info *txr;
5024         struct netdev_queue *txq;
5025
5026         for (i = 0; i < bp->tx_nr_rings; i++) {
5027                 txr = &bp->tx_ring[i];
5028                 txq = netdev_get_tx_queue(bp->dev, i);
5029                 txr->dev_state = 0;
5030         }
5031         netif_tx_wake_all_queues(bp->dev);
5032         if (bp->link_info.link_up)
5033                 netif_carrier_on(bp->dev);
5034 }
5035
5036 static void bnxt_report_link(struct bnxt *bp)
5037 {
5038         if (bp->link_info.link_up) {
5039                 const char *duplex;
5040                 const char *flow_ctrl;
5041                 u16 speed;
5042
5043                 netif_carrier_on(bp->dev);
5044                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5045                         duplex = "full";
5046                 else
5047                         duplex = "half";
5048                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5049                         flow_ctrl = "ON - receive & transmit";
5050                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5051                         flow_ctrl = "ON - transmit";
5052                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5053                         flow_ctrl = "ON - receive";
5054                 else
5055                         flow_ctrl = "none";
5056                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5057                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5058                             speed, duplex, flow_ctrl);
5059                 if (bp->flags & BNXT_FLAG_EEE_CAP)
5060                         netdev_info(bp->dev, "EEE is %s\n",
5061                                     bp->eee.eee_active ? "active" :
5062                                                          "not active");
5063         } else {
5064                 netif_carrier_off(bp->dev);
5065                 netdev_err(bp->dev, "NIC Link is Down\n");
5066         }
5067 }
5068
5069 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5070 {
5071         int rc = 0;
5072         struct hwrm_port_phy_qcaps_input req = {0};
5073         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5074         struct bnxt_link_info *link_info = &bp->link_info;
5075
5076         if (bp->hwrm_spec_code < 0x10201)
5077                 return 0;
5078
5079         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5080
5081         mutex_lock(&bp->hwrm_cmd_lock);
5082         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5083         if (rc)
5084                 goto hwrm_phy_qcaps_exit;
5085
5086         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5087                 struct ethtool_eee *eee = &bp->eee;
5088                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5089
5090                 bp->flags |= BNXT_FLAG_EEE_CAP;
5091                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5092                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5093                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5094                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5095                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5096         }
5097         link_info->support_auto_speeds =
5098                 le16_to_cpu(resp->supported_speeds_auto_mode);
5099
5100 hwrm_phy_qcaps_exit:
5101         mutex_unlock(&bp->hwrm_cmd_lock);
5102         return rc;
5103 }
5104
5105 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5106 {
5107         int rc = 0;
5108         struct bnxt_link_info *link_info = &bp->link_info;
5109         struct hwrm_port_phy_qcfg_input req = {0};
5110         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5111         u8 link_up = link_info->link_up;
5112
5113         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5114
5115         mutex_lock(&bp->hwrm_cmd_lock);
5116         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5117         if (rc) {
5118                 mutex_unlock(&bp->hwrm_cmd_lock);
5119                 return rc;
5120         }
5121
5122         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5123         link_info->phy_link_status = resp->link;
5124         link_info->duplex =  resp->duplex;
5125         link_info->pause = resp->pause;
5126         link_info->auto_mode = resp->auto_mode;
5127         link_info->auto_pause_setting = resp->auto_pause;
5128         link_info->lp_pause = resp->link_partner_adv_pause;
5129         link_info->force_pause_setting = resp->force_pause;
5130         link_info->duplex_setting = resp->duplex;
5131         if (link_info->phy_link_status == BNXT_LINK_LINK)
5132                 link_info->link_speed = le16_to_cpu(resp->link_speed);
5133         else
5134                 link_info->link_speed = 0;
5135         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5136         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5137         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5138         link_info->lp_auto_link_speeds =
5139                 le16_to_cpu(resp->link_partner_adv_speeds);
5140         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5141         link_info->phy_ver[0] = resp->phy_maj;
5142         link_info->phy_ver[1] = resp->phy_min;
5143         link_info->phy_ver[2] = resp->phy_bld;
5144         link_info->media_type = resp->media_type;
5145         link_info->phy_type = resp->phy_type;
5146         link_info->transceiver = resp->xcvr_pkg_type;
5147         link_info->phy_addr = resp->eee_config_phy_addr &
5148                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5149         link_info->module_status = resp->module_status;
5150
5151         if (bp->flags & BNXT_FLAG_EEE_CAP) {
5152                 struct ethtool_eee *eee = &bp->eee;
5153                 u16 fw_speeds;
5154
5155                 eee->eee_active = 0;
5156                 if (resp->eee_config_phy_addr &
5157                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5158                         eee->eee_active = 1;
5159                         fw_speeds = le16_to_cpu(
5160                                 resp->link_partner_adv_eee_link_speed_mask);
5161                         eee->lp_advertised =
5162                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5163                 }
5164
5165                 /* Pull initial EEE config */
5166                 if (!chng_link_state) {
5167                         if (resp->eee_config_phy_addr &
5168                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5169                                 eee->eee_enabled = 1;
5170
5171                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5172                         eee->advertised =
5173                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5174
5175                         if (resp->eee_config_phy_addr &
5176                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5177                                 __le32 tmr;
5178
5179                                 eee->tx_lpi_enabled = 1;
5180                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5181                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5182                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5183                         }
5184                 }
5185         }
5186         /* TODO: need to add more logic to report VF link */
5187         if (chng_link_state) {
5188                 if (link_info->phy_link_status == BNXT_LINK_LINK)
5189                         link_info->link_up = 1;
5190                 else
5191                         link_info->link_up = 0;
5192                 if (link_up != link_info->link_up)
5193                         bnxt_report_link(bp);
5194         } else {
5195                 /* alwasy link down if not require to update link state */
5196                 link_info->link_up = 0;
5197         }
5198         mutex_unlock(&bp->hwrm_cmd_lock);
5199         return 0;
5200 }
5201
5202 static void bnxt_get_port_module_status(struct bnxt *bp)
5203 {
5204         struct bnxt_link_info *link_info = &bp->link_info;
5205         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5206         u8 module_status;
5207
5208         if (bnxt_update_link(bp, true))
5209                 return;
5210
5211         module_status = link_info->module_status;
5212         switch (module_status) {
5213         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5214         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5215         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5216                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5217                             bp->pf.port_id);
5218                 if (bp->hwrm_spec_code >= 0x10201) {
5219                         netdev_warn(bp->dev, "Module part number %s\n",
5220                                     resp->phy_vendor_partnumber);
5221                 }
5222                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5223                         netdev_warn(bp->dev, "TX is disabled\n");
5224                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5225                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5226         }
5227 }
5228
5229 static void
5230 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5231 {
5232         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5233                 if (bp->hwrm_spec_code >= 0x10201)
5234                         req->auto_pause =
5235                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5236                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5237                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5238                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5239                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5240                 req->enables |=
5241                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5242         } else {
5243                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5244                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5245                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5246                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5247                 req->enables |=
5248                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5249                 if (bp->hwrm_spec_code >= 0x10201) {
5250                         req->auto_pause = req->force_pause;
5251                         req->enables |= cpu_to_le32(
5252                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5253                 }
5254         }
5255 }
5256
5257 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5258                                       struct hwrm_port_phy_cfg_input *req)
5259 {
5260         u8 autoneg = bp->link_info.autoneg;
5261         u16 fw_link_speed = bp->link_info.req_link_speed;
5262         u32 advertising = bp->link_info.advertising;
5263
5264         if (autoneg & BNXT_AUTONEG_SPEED) {
5265                 req->auto_mode |=
5266                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5267
5268                 req->enables |= cpu_to_le32(
5269                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5270                 req->auto_link_speed_mask = cpu_to_le16(advertising);
5271
5272                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5273                 req->flags |=
5274                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5275         } else {
5276                 req->force_link_speed = cpu_to_le16(fw_link_speed);
5277                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5278         }
5279
5280         /* tell chimp that the setting takes effect immediately */
5281         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5282 }
5283
5284 int bnxt_hwrm_set_pause(struct bnxt *bp)
5285 {
5286         struct hwrm_port_phy_cfg_input req = {0};
5287         int rc;
5288
5289         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5290         bnxt_hwrm_set_pause_common(bp, &req);
5291
5292         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5293             bp->link_info.force_link_chng)
5294                 bnxt_hwrm_set_link_common(bp, &req);
5295
5296         mutex_lock(&bp->hwrm_cmd_lock);
5297         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5298         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5299                 /* since changing of pause setting doesn't trigger any link
5300                  * change event, the driver needs to update the current pause
5301                  * result upon successfully return of the phy_cfg command
5302                  */
5303                 bp->link_info.pause =
5304                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5305                 bp->link_info.auto_pause_setting = 0;
5306                 if (!bp->link_info.force_link_chng)
5307                         bnxt_report_link(bp);
5308         }
5309         bp->link_info.force_link_chng = false;
5310         mutex_unlock(&bp->hwrm_cmd_lock);
5311         return rc;
5312 }
5313
5314 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5315                               struct hwrm_port_phy_cfg_input *req)
5316 {
5317         struct ethtool_eee *eee = &bp->eee;
5318
5319         if (eee->eee_enabled) {
5320                 u16 eee_speeds;
5321                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5322
5323                 if (eee->tx_lpi_enabled)
5324                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5325                 else
5326                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5327
5328                 req->flags |= cpu_to_le32(flags);
5329                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5330                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5331                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5332         } else {
5333                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5334         }
5335 }
5336
5337 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5338 {
5339         struct hwrm_port_phy_cfg_input req = {0};
5340
5341         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5342         if (set_pause)
5343                 bnxt_hwrm_set_pause_common(bp, &req);
5344
5345         bnxt_hwrm_set_link_common(bp, &req);
5346
5347         if (set_eee)
5348                 bnxt_hwrm_set_eee(bp, &req);
5349         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5350 }
5351
5352 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5353 {
5354         struct hwrm_port_phy_cfg_input req = {0};
5355
5356         if (!BNXT_SINGLE_PF(bp))
5357                 return 0;
5358
5359         if (pci_num_vf(bp->pdev))
5360                 return 0;
5361
5362         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5363         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
5364         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5365 }
5366
5367 static bool bnxt_eee_config_ok(struct bnxt *bp)
5368 {
5369         struct ethtool_eee *eee = &bp->eee;
5370         struct bnxt_link_info *link_info = &bp->link_info;
5371
5372         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5373                 return true;
5374
5375         if (eee->eee_enabled) {
5376                 u32 advertising =
5377                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5378
5379                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5380                         eee->eee_enabled = 0;
5381                         return false;
5382                 }
5383                 if (eee->advertised & ~advertising) {
5384                         eee->advertised = advertising & eee->supported;
5385                         return false;
5386                 }
5387         }
5388         return true;
5389 }
5390
5391 static int bnxt_update_phy_setting(struct bnxt *bp)
5392 {
5393         int rc;
5394         bool update_link = false;
5395         bool update_pause = false;
5396         bool update_eee = false;
5397         struct bnxt_link_info *link_info = &bp->link_info;
5398
5399         rc = bnxt_update_link(bp, true);
5400         if (rc) {
5401                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5402                            rc);
5403                 return rc;
5404         }
5405         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5406             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5407             link_info->req_flow_ctrl)
5408                 update_pause = true;
5409         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5410             link_info->force_pause_setting != link_info->req_flow_ctrl)
5411                 update_pause = true;
5412         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5413                 if (BNXT_AUTO_MODE(link_info->auto_mode))
5414                         update_link = true;
5415                 if (link_info->req_link_speed != link_info->force_link_speed)
5416                         update_link = true;
5417                 if (link_info->req_duplex != link_info->duplex_setting)
5418                         update_link = true;
5419         } else {
5420                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5421                         update_link = true;
5422                 if (link_info->advertising != link_info->auto_link_speeds)
5423                         update_link = true;
5424         }
5425
5426         if (!bnxt_eee_config_ok(bp))
5427                 update_eee = true;
5428
5429         if (update_link)
5430                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5431         else if (update_pause)
5432                 rc = bnxt_hwrm_set_pause(bp);
5433         if (rc) {
5434                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5435                            rc);
5436                 return rc;
5437         }
5438
5439         return rc;
5440 }
5441
5442 /* Common routine to pre-map certain register block to different GRC window.
5443  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5444  * in PF and 3 windows in VF that can be customized to map in different
5445  * register blocks.
5446  */
5447 static void bnxt_preset_reg_win(struct bnxt *bp)
5448 {
5449         if (BNXT_PF(bp)) {
5450                 /* CAG registers map to GRC window #4 */
5451                 writel(BNXT_CAG_REG_BASE,
5452                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5453         }
5454 }
5455
5456 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5457 {
5458         int rc = 0;
5459
5460         bnxt_preset_reg_win(bp);
5461         netif_carrier_off(bp->dev);
5462         if (irq_re_init) {
5463                 rc = bnxt_setup_int_mode(bp);
5464                 if (rc) {
5465                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5466                                    rc);
5467                         return rc;
5468                 }
5469         }
5470         if ((bp->flags & BNXT_FLAG_RFS) &&
5471             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5472                 /* disable RFS if falling back to INTA */
5473                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5474                 bp->flags &= ~BNXT_FLAG_RFS;
5475         }
5476
5477         rc = bnxt_alloc_mem(bp, irq_re_init);
5478         if (rc) {
5479                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5480                 goto open_err_free_mem;
5481         }
5482
5483         if (irq_re_init) {
5484                 bnxt_init_napi(bp);
5485                 rc = bnxt_request_irq(bp);
5486                 if (rc) {
5487                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5488                         goto open_err;
5489                 }
5490         }
5491
5492         bnxt_enable_napi(bp);
5493
5494         rc = bnxt_init_nic(bp, irq_re_init);
5495         if (rc) {
5496                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5497                 goto open_err;
5498         }
5499
5500         if (link_re_init) {
5501                 rc = bnxt_update_phy_setting(bp);
5502                 if (rc)
5503                         netdev_warn(bp->dev, "failed to update phy settings\n");
5504         }
5505
5506         if (irq_re_init)
5507                 udp_tunnel_get_rx_info(bp->dev);
5508
5509         set_bit(BNXT_STATE_OPEN, &bp->state);
5510         bnxt_enable_int(bp);
5511         /* Enable TX queues */
5512         bnxt_tx_enable(bp);
5513         mod_timer(&bp->timer, jiffies + bp->current_interval);
5514         /* Poll link status and check for SFP+ module status */
5515         bnxt_get_port_module_status(bp);
5516
5517         return 0;
5518
5519 open_err:
5520         bnxt_disable_napi(bp);
5521         bnxt_del_napi(bp);
5522
5523 open_err_free_mem:
5524         bnxt_free_skbs(bp);
5525         bnxt_free_irq(bp);
5526         bnxt_free_mem(bp, true);
5527         return rc;
5528 }
5529
5530 /* rtnl_lock held */
5531 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5532 {
5533         int rc = 0;
5534
5535         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5536         if (rc) {
5537                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5538                 dev_close(bp->dev);
5539         }
5540         return rc;
5541 }
5542
5543 static int bnxt_open(struct net_device *dev)
5544 {
5545         struct bnxt *bp = netdev_priv(dev);
5546         int rc = 0;
5547
5548         if (!test_bit(BNXT_STATE_FN_RST_DONE, &bp->state)) {
5549                 rc = bnxt_hwrm_func_reset(bp);
5550                 if (rc) {
5551                         netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5552                                    rc);
5553                         rc = -EBUSY;
5554                         return rc;
5555                 }
5556                 /* Do func_reset during the 1st PF open only to prevent killing
5557                  * the VFs when the PF is brought down and up.
5558                  */
5559                 if (BNXT_PF(bp))
5560                         set_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
5561         }
5562         return __bnxt_open_nic(bp, true, true);
5563 }
5564
5565 static void bnxt_disable_int_sync(struct bnxt *bp)
5566 {
5567         int i;
5568
5569         atomic_inc(&bp->intr_sem);
5570         if (!netif_running(bp->dev))
5571                 return;
5572
5573         bnxt_disable_int(bp);
5574         for (i = 0; i < bp->cp_nr_rings; i++)
5575                 synchronize_irq(bp->irq_tbl[i].vector);
5576 }
5577
5578 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5579 {
5580         int rc = 0;
5581
5582 #ifdef CONFIG_BNXT_SRIOV
5583         if (bp->sriov_cfg) {
5584                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5585                                                       !bp->sriov_cfg,
5586                                                       BNXT_SRIOV_CFG_WAIT_TMO);
5587                 if (rc)
5588                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5589         }
5590 #endif
5591         /* Change device state to avoid TX queue wake up's */
5592         bnxt_tx_disable(bp);
5593
5594         clear_bit(BNXT_STATE_OPEN, &bp->state);
5595         smp_mb__after_atomic();
5596         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5597                 msleep(20);
5598
5599         /* Flush rings before disabling interrupts */
5600         bnxt_shutdown_nic(bp, irq_re_init);
5601
5602         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5603
5604         bnxt_disable_napi(bp);
5605         bnxt_disable_int_sync(bp);
5606         del_timer_sync(&bp->timer);
5607         bnxt_free_skbs(bp);
5608
5609         if (irq_re_init) {
5610                 bnxt_free_irq(bp);
5611                 bnxt_del_napi(bp);
5612         }
5613         bnxt_free_mem(bp, irq_re_init);
5614         return rc;
5615 }
5616
5617 static int bnxt_close(struct net_device *dev)
5618 {
5619         struct bnxt *bp = netdev_priv(dev);
5620
5621         bnxt_close_nic(bp, true, true);
5622         bnxt_hwrm_shutdown_link(bp);
5623         return 0;
5624 }
5625
5626 /* rtnl_lock held */
5627 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5628 {
5629         switch (cmd) {
5630         case SIOCGMIIPHY:
5631                 /* fallthru */
5632         case SIOCGMIIREG: {
5633                 if (!netif_running(dev))
5634                         return -EAGAIN;
5635
5636                 return 0;
5637         }
5638
5639         case SIOCSMIIREG:
5640                 if (!netif_running(dev))
5641                         return -EAGAIN;
5642
5643                 return 0;
5644
5645         default:
5646                 /* do nothing */
5647                 break;
5648         }
5649         return -EOPNOTSUPP;
5650 }
5651
5652 static struct rtnl_link_stats64 *
5653 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5654 {
5655         u32 i;
5656         struct bnxt *bp = netdev_priv(dev);
5657
5658         memset(stats, 0, sizeof(struct rtnl_link_stats64));
5659
5660         if (!bp->bnapi)
5661                 return stats;
5662
5663         /* TODO check if we need to synchronize with bnxt_close path */
5664         for (i = 0; i < bp->cp_nr_rings; i++) {
5665                 struct bnxt_napi *bnapi = bp->bnapi[i];
5666                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5667                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5668
5669                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5670                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5671                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5672
5673                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5674                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5675                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5676
5677                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5678                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5679                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5680
5681                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5682                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5683                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5684
5685                 stats->rx_missed_errors +=
5686                         le64_to_cpu(hw_stats->rx_discard_pkts);
5687
5688                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5689
5690                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5691         }
5692
5693         if (bp->flags & BNXT_FLAG_PORT_STATS) {
5694                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5695                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5696
5697                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5698                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5699                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5700                                           le64_to_cpu(rx->rx_ovrsz_frames) +
5701                                           le64_to_cpu(rx->rx_runt_frames);
5702                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5703                                    le64_to_cpu(rx->rx_jbr_frames);
5704                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5705                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5706                 stats->tx_errors = le64_to_cpu(tx->tx_err);
5707         }
5708
5709         return stats;
5710 }
5711
5712 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5713 {
5714         struct net_device *dev = bp->dev;
5715         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5716         struct netdev_hw_addr *ha;
5717         u8 *haddr;
5718         int mc_count = 0;
5719         bool update = false;
5720         int off = 0;
5721
5722         netdev_for_each_mc_addr(ha, dev) {
5723                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5724                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5725                         vnic->mc_list_count = 0;
5726                         return false;
5727                 }
5728                 haddr = ha->addr;
5729                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5730                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5731                         update = true;
5732                 }
5733                 off += ETH_ALEN;
5734                 mc_count++;
5735         }
5736         if (mc_count)
5737                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5738
5739         if (mc_count != vnic->mc_list_count) {
5740                 vnic->mc_list_count = mc_count;
5741                 update = true;
5742         }
5743         return update;
5744 }
5745
5746 static bool bnxt_uc_list_updated(struct bnxt *bp)
5747 {
5748         struct net_device *dev = bp->dev;
5749         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5750         struct netdev_hw_addr *ha;
5751         int off = 0;
5752
5753         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5754                 return true;
5755
5756         netdev_for_each_uc_addr(ha, dev) {
5757                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5758                         return true;
5759
5760                 off += ETH_ALEN;
5761         }
5762         return false;
5763 }
5764
5765 static void bnxt_set_rx_mode(struct net_device *dev)
5766 {
5767         struct bnxt *bp = netdev_priv(dev);
5768         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5769         u32 mask = vnic->rx_mask;
5770         bool mc_update = false;
5771         bool uc_update;
5772
5773         if (!netif_running(dev))
5774                 return;
5775
5776         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5777                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5778                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5779
5780         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5781                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5782
5783         uc_update = bnxt_uc_list_updated(bp);
5784
5785         if (dev->flags & IFF_ALLMULTI) {
5786                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5787                 vnic->mc_list_count = 0;
5788         } else {
5789                 mc_update = bnxt_mc_list_updated(bp, &mask);
5790         }
5791
5792         if (mask != vnic->rx_mask || uc_update || mc_update) {
5793                 vnic->rx_mask = mask;
5794
5795                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5796                 schedule_work(&bp->sp_task);
5797         }
5798 }
5799
5800 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5801 {
5802         struct net_device *dev = bp->dev;
5803         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5804         struct netdev_hw_addr *ha;
5805         int i, off = 0, rc;
5806         bool uc_update;
5807
5808         netif_addr_lock_bh(dev);
5809         uc_update = bnxt_uc_list_updated(bp);
5810         netif_addr_unlock_bh(dev);
5811
5812         if (!uc_update)
5813                 goto skip_uc;
5814
5815         mutex_lock(&bp->hwrm_cmd_lock);
5816         for (i = 1; i < vnic->uc_filter_count; i++) {
5817                 struct hwrm_cfa_l2_filter_free_input req = {0};
5818
5819                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5820                                        -1);
5821
5822                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5823
5824                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5825                                         HWRM_CMD_TIMEOUT);
5826         }
5827         mutex_unlock(&bp->hwrm_cmd_lock);
5828
5829         vnic->uc_filter_count = 1;
5830
5831         netif_addr_lock_bh(dev);
5832         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5833                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5834         } else {
5835                 netdev_for_each_uc_addr(ha, dev) {
5836                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5837                         off += ETH_ALEN;
5838                         vnic->uc_filter_count++;
5839                 }
5840         }
5841         netif_addr_unlock_bh(dev);
5842
5843         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5844                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5845                 if (rc) {
5846                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5847                                    rc);
5848                         vnic->uc_filter_count = i;
5849                         return rc;
5850                 }
5851         }
5852
5853 skip_uc:
5854         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5855         if (rc)
5856                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5857                            rc);
5858
5859         return rc;
5860 }
5861
5862 static bool bnxt_rfs_capable(struct bnxt *bp)
5863 {
5864 #ifdef CONFIG_RFS_ACCEL
5865         struct bnxt_pf_info *pf = &bp->pf;
5866         int vnics;
5867
5868         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5869                 return false;
5870
5871         vnics = 1 + bp->rx_nr_rings;
5872         if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) {
5873                 netdev_warn(bp->dev,
5874                             "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
5875                             min(pf->max_rsscos_ctxs - 1, pf->max_vnics - 1));
5876                 return false;
5877         }
5878
5879         return true;
5880 #else
5881         return false;
5882 #endif
5883 }
5884
5885 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5886                                            netdev_features_t features)
5887 {
5888         struct bnxt *bp = netdev_priv(dev);
5889
5890         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
5891                 features &= ~NETIF_F_NTUPLE;
5892
5893         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5894          * turned on or off together.
5895          */
5896         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5897             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5898                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5899                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5900                                       NETIF_F_HW_VLAN_STAG_RX);
5901                 else
5902                         features |= NETIF_F_HW_VLAN_CTAG_RX |
5903                                     NETIF_F_HW_VLAN_STAG_RX;
5904         }
5905 #ifdef CONFIG_BNXT_SRIOV
5906         if (BNXT_VF(bp)) {
5907                 if (bp->vf.vlan) {
5908                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5909                                       NETIF_F_HW_VLAN_STAG_RX);
5910                 }
5911         }
5912 #endif
5913         return features;
5914 }
5915
5916 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5917 {
5918         struct bnxt *bp = netdev_priv(dev);
5919         u32 flags = bp->flags;
5920         u32 changes;
5921         int rc = 0;
5922         bool re_init = false;
5923         bool update_tpa = false;
5924
5925         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5926         if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
5927                 flags |= BNXT_FLAG_GRO;
5928         if (features & NETIF_F_LRO)
5929                 flags |= BNXT_FLAG_LRO;
5930
5931         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5932                 flags |= BNXT_FLAG_STRIP_VLAN;
5933
5934         if (features & NETIF_F_NTUPLE)
5935                 flags |= BNXT_FLAG_RFS;
5936
5937         changes = flags ^ bp->flags;
5938         if (changes & BNXT_FLAG_TPA) {
5939                 update_tpa = true;
5940                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5941                     (flags & BNXT_FLAG_TPA) == 0)
5942                         re_init = true;
5943         }
5944
5945         if (changes & ~BNXT_FLAG_TPA)
5946                 re_init = true;
5947
5948         if (flags != bp->flags) {
5949                 u32 old_flags = bp->flags;
5950
5951                 bp->flags = flags;
5952
5953                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5954                         if (update_tpa)
5955                                 bnxt_set_ring_params(bp);
5956                         return rc;
5957                 }
5958
5959                 if (re_init) {
5960                         bnxt_close_nic(bp, false, false);
5961                         if (update_tpa)
5962                                 bnxt_set_ring_params(bp);
5963
5964                         return bnxt_open_nic(bp, false, false);
5965                 }
5966                 if (update_tpa) {
5967                         rc = bnxt_set_tpa(bp,
5968                                           (flags & BNXT_FLAG_TPA) ?
5969                                           true : false);
5970                         if (rc)
5971                                 bp->flags = old_flags;
5972                 }
5973         }
5974         return rc;
5975 }
5976
5977 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5978 {
5979         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5980         int i = bnapi->index;
5981
5982         if (!txr)
5983                 return;
5984
5985         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5986                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5987                     txr->tx_cons);
5988 }
5989
5990 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5991 {
5992         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5993         int i = bnapi->index;
5994
5995         if (!rxr)
5996                 return;
5997
5998         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5999                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6000                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6001                     rxr->rx_sw_agg_prod);
6002 }
6003
6004 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6005 {
6006         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6007         int i = bnapi->index;
6008
6009         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6010                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6011 }
6012
6013 static void bnxt_dbg_dump_states(struct bnxt *bp)
6014 {
6015         int i;
6016         struct bnxt_napi *bnapi;
6017
6018         for (i = 0; i < bp->cp_nr_rings; i++) {
6019                 bnapi = bp->bnapi[i];
6020                 if (netif_msg_drv(bp)) {
6021                         bnxt_dump_tx_sw_state(bnapi);
6022                         bnxt_dump_rx_sw_state(bnapi);
6023                         bnxt_dump_cp_sw_state(bnapi);
6024                 }
6025         }
6026 }
6027
6028 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6029 {
6030         if (!silent)
6031                 bnxt_dbg_dump_states(bp);
6032         if (netif_running(bp->dev)) {
6033                 bnxt_close_nic(bp, false, false);
6034                 bnxt_open_nic(bp, false, false);
6035         }
6036 }
6037
6038 static void bnxt_tx_timeout(struct net_device *dev)
6039 {
6040         struct bnxt *bp = netdev_priv(dev);
6041
6042         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
6043         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6044         schedule_work(&bp->sp_task);
6045 }
6046
6047 #ifdef CONFIG_NET_POLL_CONTROLLER
6048 static void bnxt_poll_controller(struct net_device *dev)
6049 {
6050         struct bnxt *bp = netdev_priv(dev);
6051         int i;
6052
6053         for (i = 0; i < bp->cp_nr_rings; i++) {
6054                 struct bnxt_irq *irq = &bp->irq_tbl[i];
6055
6056                 disable_irq(irq->vector);
6057                 irq->handler(irq->vector, bp->bnapi[i]);
6058                 enable_irq(irq->vector);
6059         }
6060 }
6061 #endif
6062
6063 static void bnxt_timer(unsigned long data)
6064 {
6065         struct bnxt *bp = (struct bnxt *)data;
6066         struct net_device *dev = bp->dev;
6067
6068         if (!netif_running(dev))
6069                 return;
6070
6071         if (atomic_read(&bp->intr_sem) != 0)
6072                 goto bnxt_restart_timer;
6073
6074         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6075                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6076                 schedule_work(&bp->sp_task);
6077         }
6078 bnxt_restart_timer:
6079         mod_timer(&bp->timer, jiffies + bp->current_interval);
6080 }
6081
6082 /* Only called from bnxt_sp_task() */
6083 static void bnxt_reset(struct bnxt *bp, bool silent)
6084 {
6085         /* bnxt_reset_task() calls bnxt_close_nic() which waits
6086          * for BNXT_STATE_IN_SP_TASK to clear.
6087          * If there is a parallel dev_close(), bnxt_close() may be holding
6088          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
6089          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6090          */
6091         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6092         rtnl_lock();
6093         if (test_bit(BNXT_STATE_OPEN, &bp->state))
6094                 bnxt_reset_task(bp, silent);
6095         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6096         rtnl_unlock();
6097 }
6098
6099 static void bnxt_cfg_ntp_filters(struct bnxt *);
6100
6101 static void bnxt_sp_task(struct work_struct *work)
6102 {
6103         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6104         int rc;
6105
6106         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6107         smp_mb__after_atomic();
6108         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6109                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6110                 return;
6111         }
6112
6113         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6114                 bnxt_cfg_rx_mode(bp);
6115
6116         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6117                 bnxt_cfg_ntp_filters(bp);
6118         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6119                 rc = bnxt_update_link(bp, true);
6120                 if (rc)
6121                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6122                                    rc);
6123         }
6124         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6125                 bnxt_hwrm_exec_fwd_req(bp);
6126         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6127                 bnxt_hwrm_tunnel_dst_port_alloc(
6128                         bp, bp->vxlan_port,
6129                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6130         }
6131         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6132                 bnxt_hwrm_tunnel_dst_port_free(
6133                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6134         }
6135         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6136                 bnxt_hwrm_tunnel_dst_port_alloc(
6137                         bp, bp->nge_port,
6138                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6139         }
6140         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6141                 bnxt_hwrm_tunnel_dst_port_free(
6142                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6143         }
6144         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6145                 bnxt_reset(bp, false);
6146
6147         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6148                 bnxt_reset(bp, true);
6149
6150         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
6151                 bnxt_get_port_module_status(bp);
6152
6153         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6154                 bnxt_hwrm_port_qstats(bp);
6155
6156         smp_mb__before_atomic();
6157         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6158 }
6159
6160 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6161 {
6162         int rc;
6163         struct bnxt *bp = netdev_priv(dev);
6164
6165         SET_NETDEV_DEV(dev, &pdev->dev);
6166
6167         /* enable device (incl. PCI PM wakeup), and bus-mastering */
6168         rc = pci_enable_device(pdev);
6169         if (rc) {
6170                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6171                 goto init_err;
6172         }
6173
6174         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6175                 dev_err(&pdev->dev,
6176                         "Cannot find PCI device base address, aborting\n");
6177                 rc = -ENODEV;
6178                 goto init_err_disable;
6179         }
6180
6181         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6182         if (rc) {
6183                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6184                 goto init_err_disable;
6185         }
6186
6187         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6188             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6189                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6190                 goto init_err_disable;
6191         }
6192
6193         pci_set_master(pdev);
6194
6195         bp->dev = dev;
6196         bp->pdev = pdev;
6197
6198         bp->bar0 = pci_ioremap_bar(pdev, 0);
6199         if (!bp->bar0) {
6200                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6201                 rc = -ENOMEM;
6202                 goto init_err_release;
6203         }
6204
6205         bp->bar1 = pci_ioremap_bar(pdev, 2);
6206         if (!bp->bar1) {
6207                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6208                 rc = -ENOMEM;
6209                 goto init_err_release;
6210         }
6211
6212         bp->bar2 = pci_ioremap_bar(pdev, 4);
6213         if (!bp->bar2) {
6214                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6215                 rc = -ENOMEM;
6216                 goto init_err_release;
6217         }
6218
6219         pci_enable_pcie_error_reporting(pdev);
6220
6221         INIT_WORK(&bp->sp_task, bnxt_sp_task);
6222
6223         spin_lock_init(&bp->ntp_fltr_lock);
6224
6225         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6226         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6227
6228         /* tick values in micro seconds */
6229         bp->rx_coal_ticks = 12;
6230         bp->rx_coal_bufs = 30;
6231         bp->rx_coal_ticks_irq = 1;
6232         bp->rx_coal_bufs_irq = 2;
6233
6234         bp->tx_coal_ticks = 25;
6235         bp->tx_coal_bufs = 30;
6236         bp->tx_coal_ticks_irq = 2;
6237         bp->tx_coal_bufs_irq = 2;
6238
6239         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6240
6241         init_timer(&bp->timer);
6242         bp->timer.data = (unsigned long)bp;
6243         bp->timer.function = bnxt_timer;
6244         bp->current_interval = BNXT_TIMER_INTERVAL;
6245
6246         clear_bit(BNXT_STATE_OPEN, &bp->state);
6247
6248         return 0;
6249
6250 init_err_release:
6251         if (bp->bar2) {
6252                 pci_iounmap(pdev, bp->bar2);
6253                 bp->bar2 = NULL;
6254         }
6255
6256         if (bp->bar1) {
6257                 pci_iounmap(pdev, bp->bar1);
6258                 bp->bar1 = NULL;
6259         }
6260
6261         if (bp->bar0) {
6262                 pci_iounmap(pdev, bp->bar0);
6263                 bp->bar0 = NULL;
6264         }
6265
6266         pci_release_regions(pdev);
6267
6268 init_err_disable:
6269         pci_disable_device(pdev);
6270
6271 init_err:
6272         return rc;
6273 }
6274
6275 /* rtnl_lock held */
6276 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6277 {
6278         struct sockaddr *addr = p;
6279         struct bnxt *bp = netdev_priv(dev);
6280         int rc = 0;
6281
6282         if (!is_valid_ether_addr(addr->sa_data))
6283                 return -EADDRNOTAVAIL;
6284
6285         rc = bnxt_approve_mac(bp, addr->sa_data);
6286         if (rc)
6287                 return rc;
6288
6289         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6290                 return 0;
6291
6292         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6293         if (netif_running(dev)) {
6294                 bnxt_close_nic(bp, false, false);
6295                 rc = bnxt_open_nic(bp, false, false);
6296         }
6297
6298         return rc;
6299 }
6300
6301 /* rtnl_lock held */
6302 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6303 {
6304         struct bnxt *bp = netdev_priv(dev);
6305
6306         if (new_mtu < 60 || new_mtu > 9500)
6307                 return -EINVAL;
6308
6309         if (netif_running(dev))
6310                 bnxt_close_nic(bp, false, false);
6311
6312         dev->mtu = new_mtu;
6313         bnxt_set_ring_params(bp);
6314
6315         if (netif_running(dev))
6316                 return bnxt_open_nic(bp, false, false);
6317
6318         return 0;
6319 }
6320
6321 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6322                          struct tc_to_netdev *ntc)
6323 {
6324         struct bnxt *bp = netdev_priv(dev);
6325         bool sh = false;
6326         u8 tc;
6327
6328         if (ntc->type != TC_SETUP_MQPRIO)
6329                 return -EINVAL;
6330
6331         tc = ntc->tc;
6332
6333         if (tc > bp->max_tc) {
6334                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6335                            tc, bp->max_tc);
6336                 return -EINVAL;
6337         }
6338
6339         if (netdev_get_num_tc(dev) == tc)
6340                 return 0;
6341
6342         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6343                 sh = true;
6344
6345         if (tc) {
6346                 int max_rx_rings, max_tx_rings, rc;
6347
6348                 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6349                 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
6350                         return -ENOMEM;
6351         }
6352
6353         /* Needs to close the device and do hw resource re-allocations */
6354         if (netif_running(bp->dev))
6355                 bnxt_close_nic(bp, true, false);
6356
6357         if (tc) {
6358                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6359                 netdev_set_num_tc(dev, tc);
6360         } else {
6361                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6362                 netdev_reset_tc(dev);
6363         }
6364         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6365                                bp->tx_nr_rings + bp->rx_nr_rings;
6366         bp->num_stat_ctxs = bp->cp_nr_rings;
6367
6368         if (netif_running(bp->dev))
6369                 return bnxt_open_nic(bp, true, false);
6370
6371         return 0;
6372 }
6373
6374 #ifdef CONFIG_RFS_ACCEL
6375 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6376                             struct bnxt_ntuple_filter *f2)
6377 {
6378         struct flow_keys *keys1 = &f1->fkeys;
6379         struct flow_keys *keys2 = &f2->fkeys;
6380
6381         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6382             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6383             keys1->ports.ports == keys2->ports.ports &&
6384             keys1->basic.ip_proto == keys2->basic.ip_proto &&
6385             keys1->basic.n_proto == keys2->basic.n_proto &&
6386             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6387             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
6388                 return true;
6389
6390         return false;
6391 }
6392
6393 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6394                               u16 rxq_index, u32 flow_id)
6395 {
6396         struct bnxt *bp = netdev_priv(dev);
6397         struct bnxt_ntuple_filter *fltr, *new_fltr;
6398         struct flow_keys *fkeys;
6399         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6400         int rc = 0, idx, bit_id, l2_idx = 0;
6401         struct hlist_head *head;
6402
6403         if (skb->encapsulation)
6404                 return -EPROTONOSUPPORT;
6405
6406         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6407                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6408                 int off = 0, j;
6409
6410                 netif_addr_lock_bh(dev);
6411                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6412                         if (ether_addr_equal(eth->h_dest,
6413                                              vnic->uc_list + off)) {
6414                                 l2_idx = j + 1;
6415                                 break;
6416                         }
6417                 }
6418                 netif_addr_unlock_bh(dev);
6419                 if (!l2_idx)
6420                         return -EINVAL;
6421         }
6422         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6423         if (!new_fltr)
6424                 return -ENOMEM;
6425
6426         fkeys = &new_fltr->fkeys;
6427         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6428                 rc = -EPROTONOSUPPORT;
6429                 goto err_free;
6430         }
6431
6432         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6433             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6434              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6435                 rc = -EPROTONOSUPPORT;
6436                 goto err_free;
6437         }
6438
6439         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
6440         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6441
6442         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6443         head = &bp->ntp_fltr_hash_tbl[idx];
6444         rcu_read_lock();
6445         hlist_for_each_entry_rcu(fltr, head, hash) {
6446                 if (bnxt_fltr_match(fltr, new_fltr)) {
6447                         rcu_read_unlock();
6448                         rc = 0;
6449                         goto err_free;
6450                 }
6451         }
6452         rcu_read_unlock();
6453
6454         spin_lock_bh(&bp->ntp_fltr_lock);
6455         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6456                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
6457         if (bit_id < 0) {
6458                 spin_unlock_bh(&bp->ntp_fltr_lock);
6459                 rc = -ENOMEM;
6460                 goto err_free;
6461         }
6462
6463         new_fltr->sw_id = (u16)bit_id;
6464         new_fltr->flow_id = flow_id;
6465         new_fltr->l2_fltr_idx = l2_idx;
6466         new_fltr->rxq = rxq_index;
6467         hlist_add_head_rcu(&new_fltr->hash, head);
6468         bp->ntp_fltr_count++;
6469         spin_unlock_bh(&bp->ntp_fltr_lock);
6470
6471         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6472         schedule_work(&bp->sp_task);
6473
6474         return new_fltr->sw_id;
6475
6476 err_free:
6477         kfree(new_fltr);
6478         return rc;
6479 }
6480
6481 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6482 {
6483         int i;
6484
6485         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6486                 struct hlist_head *head;
6487                 struct hlist_node *tmp;
6488                 struct bnxt_ntuple_filter *fltr;
6489                 int rc;
6490
6491                 head = &bp->ntp_fltr_hash_tbl[i];
6492                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6493                         bool del = false;
6494
6495                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6496                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6497                                                         fltr->flow_id,
6498                                                         fltr->sw_id)) {
6499                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
6500                                                                          fltr);
6501                                         del = true;
6502                                 }
6503                         } else {
6504                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6505                                                                        fltr);
6506                                 if (rc)
6507                                         del = true;
6508                                 else
6509                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
6510                         }
6511
6512                         if (del) {
6513                                 spin_lock_bh(&bp->ntp_fltr_lock);
6514                                 hlist_del_rcu(&fltr->hash);
6515                                 bp->ntp_fltr_count--;
6516                                 spin_unlock_bh(&bp->ntp_fltr_lock);
6517                                 synchronize_rcu();
6518                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6519                                 kfree(fltr);
6520                         }
6521                 }
6522         }
6523         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6524                 netdev_info(bp->dev, "Receive PF driver unload event!");
6525 }
6526
6527 #else
6528
6529 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6530 {
6531 }
6532
6533 #endif /* CONFIG_RFS_ACCEL */
6534
6535 static void bnxt_udp_tunnel_add(struct net_device *dev,
6536                                 struct udp_tunnel_info *ti)
6537 {
6538         struct bnxt *bp = netdev_priv(dev);
6539
6540         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6541                 return;
6542
6543         if (!netif_running(dev))
6544                 return;
6545
6546         switch (ti->type) {
6547         case UDP_TUNNEL_TYPE_VXLAN:
6548                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
6549                         return;
6550
6551                 bp->vxlan_port_cnt++;
6552                 if (bp->vxlan_port_cnt == 1) {
6553                         bp->vxlan_port = ti->port;
6554                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6555                         schedule_work(&bp->sp_task);
6556                 }
6557                 break;
6558         case UDP_TUNNEL_TYPE_GENEVE:
6559                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
6560                         return;
6561
6562                 bp->nge_port_cnt++;
6563                 if (bp->nge_port_cnt == 1) {
6564                         bp->nge_port = ti->port;
6565                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
6566                 }
6567                 break;
6568         default:
6569                 return;
6570         }
6571
6572         schedule_work(&bp->sp_task);
6573 }
6574
6575 static void bnxt_udp_tunnel_del(struct net_device *dev,
6576                                 struct udp_tunnel_info *ti)
6577 {
6578         struct bnxt *bp = netdev_priv(dev);
6579
6580         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6581                 return;
6582
6583         if (!netif_running(dev))
6584                 return;
6585
6586         switch (ti->type) {
6587         case UDP_TUNNEL_TYPE_VXLAN:
6588                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
6589                         return;
6590                 bp->vxlan_port_cnt--;
6591
6592                 if (bp->vxlan_port_cnt != 0)
6593                         return;
6594
6595                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6596                 break;
6597         case UDP_TUNNEL_TYPE_GENEVE:
6598                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
6599                         return;
6600                 bp->nge_port_cnt--;
6601
6602                 if (bp->nge_port_cnt != 0)
6603                         return;
6604
6605                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
6606                 break;
6607         default:
6608                 return;
6609         }
6610
6611         schedule_work(&bp->sp_task);
6612 }
6613
6614 static const struct net_device_ops bnxt_netdev_ops = {
6615         .ndo_open               = bnxt_open,
6616         .ndo_start_xmit         = bnxt_start_xmit,
6617         .ndo_stop               = bnxt_close,
6618         .ndo_get_stats64        = bnxt_get_stats64,
6619         .ndo_set_rx_mode        = bnxt_set_rx_mode,
6620         .ndo_do_ioctl           = bnxt_ioctl,
6621         .ndo_validate_addr      = eth_validate_addr,
6622         .ndo_set_mac_address    = bnxt_change_mac_addr,
6623         .ndo_change_mtu         = bnxt_change_mtu,
6624         .ndo_fix_features       = bnxt_fix_features,
6625         .ndo_set_features       = bnxt_set_features,
6626         .ndo_tx_timeout         = bnxt_tx_timeout,
6627 #ifdef CONFIG_BNXT_SRIOV
6628         .ndo_get_vf_config      = bnxt_get_vf_config,
6629         .ndo_set_vf_mac         = bnxt_set_vf_mac,
6630         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
6631         .ndo_set_vf_rate        = bnxt_set_vf_bw,
6632         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
6633         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
6634 #endif
6635 #ifdef CONFIG_NET_POLL_CONTROLLER
6636         .ndo_poll_controller    = bnxt_poll_controller,
6637 #endif
6638         .ndo_setup_tc           = bnxt_setup_tc,
6639 #ifdef CONFIG_RFS_ACCEL
6640         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
6641 #endif
6642         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
6643         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
6644 #ifdef CONFIG_NET_RX_BUSY_POLL
6645         .ndo_busy_poll          = bnxt_busy_poll,
6646 #endif
6647 };
6648
6649 static void bnxt_remove_one(struct pci_dev *pdev)
6650 {
6651         struct net_device *dev = pci_get_drvdata(pdev);
6652         struct bnxt *bp = netdev_priv(dev);
6653
6654         if (BNXT_PF(bp))
6655                 bnxt_sriov_disable(bp);
6656
6657         pci_disable_pcie_error_reporting(pdev);
6658         unregister_netdev(dev);
6659         cancel_work_sync(&bp->sp_task);
6660         bp->sp_event = 0;
6661
6662         bnxt_hwrm_func_drv_unrgtr(bp);
6663         bnxt_free_hwrm_resources(bp);
6664         pci_iounmap(pdev, bp->bar2);
6665         pci_iounmap(pdev, bp->bar1);
6666         pci_iounmap(pdev, bp->bar0);
6667         free_netdev(dev);
6668
6669         pci_release_regions(pdev);
6670         pci_disable_device(pdev);
6671 }
6672
6673 static int bnxt_probe_phy(struct bnxt *bp)
6674 {
6675         int rc = 0;
6676         struct bnxt_link_info *link_info = &bp->link_info;
6677
6678         rc = bnxt_hwrm_phy_qcaps(bp);
6679         if (rc) {
6680                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6681                            rc);
6682                 return rc;
6683         }
6684
6685         rc = bnxt_update_link(bp, false);
6686         if (rc) {
6687                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6688                            rc);
6689                 return rc;
6690         }
6691
6692         /* Older firmware does not have supported_auto_speeds, so assume
6693          * that all supported speeds can be autonegotiated.
6694          */
6695         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
6696                 link_info->support_auto_speeds = link_info->support_speeds;
6697
6698         /*initialize the ethool setting copy with NVM settings */
6699         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
6700                 link_info->autoneg = BNXT_AUTONEG_SPEED;
6701                 if (bp->hwrm_spec_code >= 0x10201) {
6702                         if (link_info->auto_pause_setting &
6703                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6704                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6705                 } else {
6706                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6707                 }
6708                 link_info->advertising = link_info->auto_link_speeds;
6709         } else {
6710                 link_info->req_link_speed = link_info->force_link_speed;
6711                 link_info->req_duplex = link_info->duplex_setting;
6712         }
6713         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6714                 link_info->req_flow_ctrl =
6715                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6716         else
6717                 link_info->req_flow_ctrl = link_info->force_pause_setting;
6718         return rc;
6719 }
6720
6721 static int bnxt_get_max_irq(struct pci_dev *pdev)
6722 {
6723         u16 ctrl;
6724
6725         if (!pdev->msix_cap)
6726                 return 1;
6727
6728         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6729         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6730 }
6731
6732 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6733                                 int *max_cp)
6734 {
6735         int max_ring_grps = 0;
6736
6737 #ifdef CONFIG_BNXT_SRIOV
6738         if (!BNXT_PF(bp)) {
6739                 *max_tx = bp->vf.max_tx_rings;
6740                 *max_rx = bp->vf.max_rx_rings;
6741                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6742                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
6743                 max_ring_grps = bp->vf.max_hw_ring_grps;
6744         } else
6745 #endif
6746         {
6747                 *max_tx = bp->pf.max_tx_rings;
6748                 *max_rx = bp->pf.max_rx_rings;
6749                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6750                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6751                 max_ring_grps = bp->pf.max_hw_ring_grps;
6752         }
6753         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
6754                 *max_cp -= 1;
6755                 *max_rx -= 2;
6756         }
6757         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6758                 *max_rx >>= 1;
6759         *max_rx = min_t(int, *max_rx, max_ring_grps);
6760 }
6761
6762 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6763 {
6764         int rx, tx, cp;
6765
6766         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6767         if (!rx || !tx || !cp)
6768                 return -ENOMEM;
6769
6770         *max_rx = rx;
6771         *max_tx = tx;
6772         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6773 }
6774
6775 static int bnxt_set_dflt_rings(struct bnxt *bp)
6776 {
6777         int dflt_rings, max_rx_rings, max_tx_rings, rc;
6778         bool sh = true;
6779
6780         if (sh)
6781                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6782         dflt_rings = netif_get_num_default_rss_queues();
6783         rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6784         if (rc)
6785                 return rc;
6786         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6787         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6788         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6789         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6790                                bp->tx_nr_rings + bp->rx_nr_rings;
6791         bp->num_stat_ctxs = bp->cp_nr_rings;
6792         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6793                 bp->rx_nr_rings++;
6794                 bp->cp_nr_rings++;
6795         }
6796         return rc;
6797 }
6798
6799 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6800 {
6801         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6802         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6803
6804         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6805             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6806                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6807         else
6808                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6809                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6810                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6811                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6812                             "Unknown", width);
6813 }
6814
6815 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6816 {
6817         static int version_printed;
6818         struct net_device *dev;
6819         struct bnxt *bp;
6820         int rc, max_irqs;
6821
6822         if (pdev->device == 0x16cd && pci_is_bridge(pdev))
6823                 return -ENODEV;
6824
6825         if (version_printed++ == 0)
6826                 pr_info("%s", version);
6827
6828         max_irqs = bnxt_get_max_irq(pdev);
6829         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6830         if (!dev)
6831                 return -ENOMEM;
6832
6833         bp = netdev_priv(dev);
6834
6835         if (bnxt_vf_pciid(ent->driver_data))
6836                 bp->flags |= BNXT_FLAG_VF;
6837
6838         if (pdev->msix_cap)
6839                 bp->flags |= BNXT_FLAG_MSIX_CAP;
6840
6841         rc = bnxt_init_board(pdev, dev);
6842         if (rc < 0)
6843                 goto init_err_free;
6844
6845         dev->netdev_ops = &bnxt_netdev_ops;
6846         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6847         dev->ethtool_ops = &bnxt_ethtool_ops;
6848
6849         pci_set_drvdata(pdev, dev);
6850
6851         rc = bnxt_alloc_hwrm_resources(bp);
6852         if (rc)
6853                 goto init_err;
6854
6855         mutex_init(&bp->hwrm_cmd_lock);
6856         rc = bnxt_hwrm_ver_get(bp);
6857         if (rc)
6858                 goto init_err;
6859
6860         bnxt_hwrm_fw_set_time(bp);
6861
6862         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6863                            NETIF_F_TSO | NETIF_F_TSO6 |
6864                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6865                            NETIF_F_GSO_IPXIP4 |
6866                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6867                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
6868                            NETIF_F_RXCSUM | NETIF_F_GRO;
6869
6870         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
6871                 dev->hw_features |= NETIF_F_LRO;
6872
6873         dev->hw_enc_features =
6874                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6875                         NETIF_F_TSO | NETIF_F_TSO6 |
6876                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6877                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6878                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
6879         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
6880                                     NETIF_F_GSO_GRE_CSUM;
6881         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6882         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6883                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6884         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6885         dev->priv_flags |= IFF_UNICAST_FLT;
6886
6887 #ifdef CONFIG_BNXT_SRIOV
6888         init_waitqueue_head(&bp->sriov_cfg_wait);
6889 #endif
6890         bp->gro_func = bnxt_gro_func_5730x;
6891         if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
6892                 bp->gro_func = bnxt_gro_func_5731x;
6893
6894         rc = bnxt_hwrm_func_drv_rgtr(bp);
6895         if (rc)
6896                 goto init_err;
6897
6898         /* Get the MAX capabilities for this function */
6899         rc = bnxt_hwrm_func_qcaps(bp);
6900         if (rc) {
6901                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6902                            rc);
6903                 rc = -1;
6904                 goto init_err;
6905         }
6906
6907         rc = bnxt_hwrm_queue_qportcfg(bp);
6908         if (rc) {
6909                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6910                            rc);
6911                 rc = -1;
6912                 goto init_err;
6913         }
6914
6915         bnxt_hwrm_func_qcfg(bp);
6916
6917         bnxt_set_tpa_flags(bp);
6918         bnxt_set_ring_params(bp);
6919         if (BNXT_PF(bp))
6920                 bp->pf.max_irqs = max_irqs;
6921 #if defined(CONFIG_BNXT_SRIOV)
6922         else
6923                 bp->vf.max_irqs = max_irqs;
6924 #endif
6925         bnxt_set_dflt_rings(bp);
6926
6927         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6928                 dev->hw_features |= NETIF_F_NTUPLE;
6929                 if (bnxt_rfs_capable(bp)) {
6930                         bp->flags |= BNXT_FLAG_RFS;
6931                         dev->features |= NETIF_F_NTUPLE;
6932                 }
6933         }
6934
6935         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6936                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6937
6938         rc = bnxt_probe_phy(bp);
6939         if (rc)
6940                 goto init_err;
6941
6942         rc = register_netdev(dev);
6943         if (rc)
6944                 goto init_err;
6945
6946         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6947                     board_info[ent->driver_data].name,
6948                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
6949
6950         bnxt_parse_log_pcie_link(bp);
6951
6952         return 0;
6953
6954 init_err:
6955         pci_iounmap(pdev, bp->bar0);
6956         pci_release_regions(pdev);
6957         pci_disable_device(pdev);
6958
6959 init_err_free:
6960         free_netdev(dev);
6961         return rc;
6962 }
6963
6964 /**
6965  * bnxt_io_error_detected - called when PCI error is detected
6966  * @pdev: Pointer to PCI device
6967  * @state: The current pci connection state
6968  *
6969  * This function is called after a PCI bus error affecting
6970  * this device has been detected.
6971  */
6972 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6973                                                pci_channel_state_t state)
6974 {
6975         struct net_device *netdev = pci_get_drvdata(pdev);
6976         struct bnxt *bp = netdev_priv(netdev);
6977
6978         netdev_info(netdev, "PCI I/O error detected\n");
6979
6980         rtnl_lock();
6981         netif_device_detach(netdev);
6982
6983         if (state == pci_channel_io_perm_failure) {
6984                 rtnl_unlock();
6985                 return PCI_ERS_RESULT_DISCONNECT;
6986         }
6987
6988         if (netif_running(netdev))
6989                 bnxt_close(netdev);
6990
6991         /* So that func_reset will be done during slot_reset */
6992         clear_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
6993         pci_disable_device(pdev);
6994         rtnl_unlock();
6995
6996         /* Request a slot slot reset. */
6997         return PCI_ERS_RESULT_NEED_RESET;
6998 }
6999
7000 /**
7001  * bnxt_io_slot_reset - called after the pci bus has been reset.
7002  * @pdev: Pointer to PCI device
7003  *
7004  * Restart the card from scratch, as if from a cold-boot.
7005  * At this point, the card has exprienced a hard reset,
7006  * followed by fixups by BIOS, and has its config space
7007  * set up identically to what it was at cold boot.
7008  */
7009 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7010 {
7011         struct net_device *netdev = pci_get_drvdata(pdev);
7012         struct bnxt *bp = netdev_priv(netdev);
7013         int err = 0;
7014         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7015
7016         netdev_info(bp->dev, "PCI Slot Reset\n");
7017
7018         rtnl_lock();
7019
7020         if (pci_enable_device(pdev)) {
7021                 dev_err(&pdev->dev,
7022                         "Cannot re-enable PCI device after reset.\n");
7023         } else {
7024                 pci_set_master(pdev);
7025
7026                 if (netif_running(netdev))
7027                         err = bnxt_open(netdev);
7028
7029                 if (!err)
7030                         result = PCI_ERS_RESULT_RECOVERED;
7031         }
7032
7033         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7034                 dev_close(netdev);
7035
7036         rtnl_unlock();
7037
7038         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7039         if (err) {
7040                 dev_err(&pdev->dev,
7041                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7042                          err); /* non-fatal, continue */
7043         }
7044
7045         return PCI_ERS_RESULT_RECOVERED;
7046 }
7047
7048 /**
7049  * bnxt_io_resume - called when traffic can start flowing again.
7050  * @pdev: Pointer to PCI device
7051  *
7052  * This callback is called when the error recovery driver tells
7053  * us that its OK to resume normal operation.
7054  */
7055 static void bnxt_io_resume(struct pci_dev *pdev)
7056 {
7057         struct net_device *netdev = pci_get_drvdata(pdev);
7058
7059         rtnl_lock();
7060
7061         netif_device_attach(netdev);
7062
7063         rtnl_unlock();
7064 }
7065
7066 static const struct pci_error_handlers bnxt_err_handler = {
7067         .error_detected = bnxt_io_error_detected,
7068         .slot_reset     = bnxt_io_slot_reset,
7069         .resume         = bnxt_io_resume
7070 };
7071
7072 static struct pci_driver bnxt_pci_driver = {
7073         .name           = DRV_MODULE_NAME,
7074         .id_table       = bnxt_pci_tbl,
7075         .probe          = bnxt_init_one,
7076         .remove         = bnxt_remove_one,
7077         .err_handler    = &bnxt_err_handler,
7078 #if defined(CONFIG_BNXT_SRIOV)
7079         .sriov_configure = bnxt_sriov_configure,
7080 #endif
7081 };
7082
7083 module_pci_driver(bnxt_pci_driver);