drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 /* Forward declarations */
  76 static void bcmgenet_set_rx_mode(struct net_device *dev);
  77
  78 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  79 {
  80         /* MIPS chips strapped for BE will automagically configure the
  81          * peripheral registers for CPU-native byte order.
  82          */
  83         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  84                 __raw_writel(value, offset);
  85         else
  86                 writel_relaxed(value, offset);
  87 }
  88
  89 static inline u32 bcmgenet_readl(void __iomem *offset)
  90 {
  91         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  92                 return __raw_readl(offset);
  93         else
  94                 return readl_relaxed(offset);
  95 }
  96
  97 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  98                                              void __iomem *d, u32 value)
  99 {
 100         bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
 101 }
 102
 103 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
 104                                             void __iomem *d)
 105 {
 106         return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
 107 }
 108
 109 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
 110                                     void __iomem *d,
 111                                     dma_addr_t addr)
 112 {
 113         bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
 114
 115         /* Register writes to GISB bus can take couple hundred nanoseconds
 116          * and are done for each packet, save these expensive writes unless
 117          * the platform is explicitly configured for 64-bits/LPAE.
 118          */
 119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 120         if (priv->hw_params->flags & GENET_HAS_40BITS)
 121                 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 122 #endif
 123 }
 124
 125 /* Combined address + length/status setter */
 126 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 127                                void __iomem *d, dma_addr_t addr, u32 val)
 128 {
 129         dmadesc_set_addr(priv, d, addr);
 130         dmadesc_set_length_status(priv, d, val);
 131 }
 132
 133 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 134                                           void __iomem *d)
 135 {
 136         dma_addr_t addr;
 137
 138         addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
 139
 140         /* Register writes to GISB bus can take couple hundred nanoseconds
 141          * and are done for each packet, save these expensive writes unless
 142          * the platform is explicitly configured for 64-bits/LPAE.
 143          */
 144 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 145         if (priv->hw_params->flags & GENET_HAS_40BITS)
 146                 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 147 #endif
 148         return addr;
 149 }
 150
 151 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 152
 153 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 154                                 NETIF_MSG_LINK)
 155
 156 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 157 {
 158         if (GENET_IS_V1(priv))
 159                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 160         else
 161                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 162 }
 163
 164 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 165 {
 166         if (GENET_IS_V1(priv))
 167                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 168         else
 169                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 170 }
 171
 172 /* These macros are defined to deal with register map change
 173  * between GENET1.1 and GENET2. Only those currently being used
 174  * by driver are defined.
 175  */
 176 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 177 {
 178         if (GENET_IS_V1(priv))
 179                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 180         else
 181                 return bcmgenet_readl(priv->base +
 182                                       priv->hw_params->tbuf_offset + TBUF_CTRL);
 183 }
 184
 185 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 186 {
 187         if (GENET_IS_V1(priv))
 188                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 189         else
 190                 bcmgenet_writel(val, priv->base +
 191                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 192 }
 193
 194 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 195 {
 196         if (GENET_IS_V1(priv))
 197                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 198         else
 199                 return bcmgenet_readl(priv->base +
 200                                       priv->hw_params->tbuf_offset + TBUF_BP_MC);
 201 }
 202
 203 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 204 {
 205         if (GENET_IS_V1(priv))
 206                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 207         else
 208                 bcmgenet_writel(val, priv->base +
 209                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 210 }
 211
 212 /* RX/TX DMA register accessors */
 213 enum dma_reg {
 214         DMA_RING_CFG = 0,
 215         DMA_CTRL,
 216         DMA_STATUS,
 217         DMA_SCB_BURST_SIZE,
 218         DMA_ARB_CTRL,
 219         DMA_PRIORITY_0,
 220         DMA_PRIORITY_1,
 221         DMA_PRIORITY_2,
 222         DMA_INDEX2RING_0,
 223         DMA_INDEX2RING_1,
 224         DMA_INDEX2RING_2,
 225         DMA_INDEX2RING_3,
 226         DMA_INDEX2RING_4,
 227         DMA_INDEX2RING_5,
 228         DMA_INDEX2RING_6,
 229         DMA_INDEX2RING_7,
 230         DMA_RING0_TIMEOUT,
 231         DMA_RING1_TIMEOUT,
 232         DMA_RING2_TIMEOUT,
 233         DMA_RING3_TIMEOUT,
 234         DMA_RING4_TIMEOUT,
 235         DMA_RING5_TIMEOUT,
 236         DMA_RING6_TIMEOUT,
 237         DMA_RING7_TIMEOUT,
 238         DMA_RING8_TIMEOUT,
 239         DMA_RING9_TIMEOUT,
 240         DMA_RING10_TIMEOUT,
 241         DMA_RING11_TIMEOUT,
 242         DMA_RING12_TIMEOUT,
 243         DMA_RING13_TIMEOUT,
 244         DMA_RING14_TIMEOUT,
 245         DMA_RING15_TIMEOUT,
 246         DMA_RING16_TIMEOUT,
 247 };
 248
 249 static const u8 bcmgenet_dma_regs_v3plus[] = {
 250         [DMA_RING_CFG]          = 0x00,
 251         [DMA_CTRL]              = 0x04,
 252         [DMA_STATUS]            = 0x08,
 253         [DMA_SCB_BURST_SIZE]    = 0x0C,
 254         [DMA_ARB_CTRL]          = 0x2C,
 255         [DMA_PRIORITY_0]        = 0x30,
 256         [DMA_PRIORITY_1]        = 0x34,
 257         [DMA_PRIORITY_2]        = 0x38,
 258         [DMA_RING0_TIMEOUT]     = 0x2C,
 259         [DMA_RING1_TIMEOUT]     = 0x30,
 260         [DMA_RING2_TIMEOUT]     = 0x34,
 261         [DMA_RING3_TIMEOUT]     = 0x38,
 262         [DMA_RING4_TIMEOUT]     = 0x3c,
 263         [DMA_RING5_TIMEOUT]     = 0x40,
 264         [DMA_RING6_TIMEOUT]     = 0x44,
 265         [DMA_RING7_TIMEOUT]     = 0x48,
 266         [DMA_RING8_TIMEOUT]     = 0x4c,
 267         [DMA_RING9_TIMEOUT]     = 0x50,
 268         [DMA_RING10_TIMEOUT]    = 0x54,
 269         [DMA_RING11_TIMEOUT]    = 0x58,
 270         [DMA_RING12_TIMEOUT]    = 0x5c,
 271         [DMA_RING13_TIMEOUT]    = 0x60,
 272         [DMA_RING14_TIMEOUT]    = 0x64,
 273         [DMA_RING15_TIMEOUT]    = 0x68,
 274         [DMA_RING16_TIMEOUT]    = 0x6C,
 275         [DMA_INDEX2RING_0]      = 0x70,
 276         [DMA_INDEX2RING_1]      = 0x74,
 277         [DMA_INDEX2RING_2]      = 0x78,
 278         [DMA_INDEX2RING_3]      = 0x7C,
 279         [DMA_INDEX2RING_4]      = 0x80,
 280         [DMA_INDEX2RING_5]      = 0x84,
 281         [DMA_INDEX2RING_6]      = 0x88,
 282         [DMA_INDEX2RING_7]      = 0x8C,
 283 };
 284
 285 static const u8 bcmgenet_dma_regs_v2[] = {
 286         [DMA_RING_CFG]          = 0x00,
 287         [DMA_CTRL]              = 0x04,
 288         [DMA_STATUS]            = 0x08,
 289         [DMA_SCB_BURST_SIZE]    = 0x0C,
 290         [DMA_ARB_CTRL]          = 0x30,
 291         [DMA_PRIORITY_0]        = 0x34,
 292         [DMA_PRIORITY_1]        = 0x38,
 293         [DMA_PRIORITY_2]        = 0x3C,
 294         [DMA_RING0_TIMEOUT]     = 0x2C,
 295         [DMA_RING1_TIMEOUT]     = 0x30,
 296         [DMA_RING2_TIMEOUT]     = 0x34,
 297         [DMA_RING3_TIMEOUT]     = 0x38,
 298         [DMA_RING4_TIMEOUT]     = 0x3c,
 299         [DMA_RING5_TIMEOUT]     = 0x40,
 300         [DMA_RING6_TIMEOUT]     = 0x44,
 301         [DMA_RING7_TIMEOUT]     = 0x48,
 302         [DMA_RING8_TIMEOUT]     = 0x4c,
 303         [DMA_RING9_TIMEOUT]     = 0x50,
 304         [DMA_RING10_TIMEOUT]    = 0x54,
 305         [DMA_RING11_TIMEOUT]    = 0x58,
 306         [DMA_RING12_TIMEOUT]    = 0x5c,
 307         [DMA_RING13_TIMEOUT]    = 0x60,
 308         [DMA_RING14_TIMEOUT]    = 0x64,
 309         [DMA_RING15_TIMEOUT]    = 0x68,
 310         [DMA_RING16_TIMEOUT]    = 0x6C,
 311 };
 312
 313 static const u8 bcmgenet_dma_regs_v1[] = {
 314         [DMA_CTRL]              = 0x00,
 315         [DMA_STATUS]            = 0x04,
 316         [DMA_SCB_BURST_SIZE]    = 0x0C,
 317         [DMA_ARB_CTRL]          = 0x30,
 318         [DMA_PRIORITY_0]        = 0x34,
 319         [DMA_PRIORITY_1]        = 0x38,
 320         [DMA_PRIORITY_2]        = 0x3C,
 321         [DMA_RING0_TIMEOUT]     = 0x2C,
 322         [DMA_RING1_TIMEOUT]     = 0x30,
 323         [DMA_RING2_TIMEOUT]     = 0x34,
 324         [DMA_RING3_TIMEOUT]     = 0x38,
 325         [DMA_RING4_TIMEOUT]     = 0x3c,
 326         [DMA_RING5_TIMEOUT]     = 0x40,
 327         [DMA_RING6_TIMEOUT]     = 0x44,
 328         [DMA_RING7_TIMEOUT]     = 0x48,
 329         [DMA_RING8_TIMEOUT]     = 0x4c,
 330         [DMA_RING9_TIMEOUT]     = 0x50,
 331         [DMA_RING10_TIMEOUT]    = 0x54,
 332         [DMA_RING11_TIMEOUT]    = 0x58,
 333         [DMA_RING12_TIMEOUT]    = 0x5c,
 334         [DMA_RING13_TIMEOUT]    = 0x60,
 335         [DMA_RING14_TIMEOUT]    = 0x64,
 336         [DMA_RING15_TIMEOUT]    = 0x68,
 337         [DMA_RING16_TIMEOUT]    = 0x6C,
 338 };
 339
 340 /* Set at runtime once bcmgenet version is known */
 341 static const u8 *bcmgenet_dma_regs;
 342
 343 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 344 {
 345         return netdev_priv(dev_get_drvdata(dev));
 346 }
 347
 348 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 349                                       enum dma_reg r)
 350 {
 351         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 352                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 353 }
 354
 355 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 356                                         u32 val, enum dma_reg r)
 357 {
 358         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 359                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 360 }
 361
 362 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 363                                       enum dma_reg r)
 364 {
 365         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 366                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 367 }
 368
 369 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 370                                         u32 val, enum dma_reg r)
 371 {
 372         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 373                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 374 }
 375
 376 /* RDMA/TDMA ring registers and accessors
 377  * we merge the common fields and just prefix with T/D the registers
 378  * having different meaning depending on the direction
 379  */
 380 enum dma_ring_reg {
 381         TDMA_READ_PTR = 0,
 382         RDMA_WRITE_PTR = TDMA_READ_PTR,
 383         TDMA_READ_PTR_HI,
 384         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 385         TDMA_CONS_INDEX,
 386         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 387         TDMA_PROD_INDEX,
 388         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 389         DMA_RING_BUF_SIZE,
 390         DMA_START_ADDR,
 391         DMA_START_ADDR_HI,
 392         DMA_END_ADDR,
 393         DMA_END_ADDR_HI,
 394         DMA_MBUF_DONE_THRESH,
 395         TDMA_FLOW_PERIOD,
 396         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 397         TDMA_WRITE_PTR,
 398         RDMA_READ_PTR = TDMA_WRITE_PTR,
 399         TDMA_WRITE_PTR_HI,
 400         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 401 };
 402
 403 /* GENET v4 supports 40-bits pointer addressing
 404  * for obvious reasons the LO and HI word parts
 405  * are contiguous, but this offsets the other
 406  * registers.
 407  */
 408 static const u8 genet_dma_ring_regs_v4[] = {
 409         [TDMA_READ_PTR]                 = 0x00,
 410         [TDMA_READ_PTR_HI]              = 0x04,
 411         [TDMA_CONS_INDEX]               = 0x08,
 412         [TDMA_PROD_INDEX]               = 0x0C,
 413         [DMA_RING_BUF_SIZE]             = 0x10,
 414         [DMA_START_ADDR]                = 0x14,
 415         [DMA_START_ADDR_HI]             = 0x18,
 416         [DMA_END_ADDR]                  = 0x1C,
 417         [DMA_END_ADDR_HI]               = 0x20,
 418         [DMA_MBUF_DONE_THRESH]          = 0x24,
 419         [TDMA_FLOW_PERIOD]              = 0x28,
 420         [TDMA_WRITE_PTR]                = 0x2C,
 421         [TDMA_WRITE_PTR_HI]             = 0x30,
 422 };
 423
 424 static const u8 genet_dma_ring_regs_v123[] = {
 425         [TDMA_READ_PTR]                 = 0x00,
 426         [TDMA_CONS_INDEX]               = 0x04,
 427         [TDMA_PROD_INDEX]               = 0x08,
 428         [DMA_RING_BUF_SIZE]             = 0x0C,
 429         [DMA_START_ADDR]                = 0x10,
 430         [DMA_END_ADDR]                  = 0x14,
 431         [DMA_MBUF_DONE_THRESH]          = 0x18,
 432         [TDMA_FLOW_PERIOD]              = 0x1C,
 433         [TDMA_WRITE_PTR]                = 0x20,
 434 };
 435
 436 /* Set at runtime once GENET version is known */
 437 static const u8 *genet_dma_ring_regs;
 438
 439 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 440                                            unsigned int ring,
 441                                            enum dma_ring_reg r)
 442 {
 443         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 444                               (DMA_RING_SIZE * ring) +
 445                               genet_dma_ring_regs[r]);
 446 }
 447
 448 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 449                                              unsigned int ring, u32 val,
 450                                              enum dma_ring_reg r)
 451 {
 452         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 453                         (DMA_RING_SIZE * ring) +
 454                         genet_dma_ring_regs[r]);
 455 }
 456
 457 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 458                                            unsigned int ring,
 459                                            enum dma_ring_reg r)
 460 {
 461         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 462                               (DMA_RING_SIZE * ring) +
 463                               genet_dma_ring_regs[r]);
 464 }
 465
 466 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 467                                              unsigned int ring, u32 val,
 468                                              enum dma_ring_reg r)
 469 {
 470         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 471                         (DMA_RING_SIZE * ring) +
 472                         genet_dma_ring_regs[r]);
 473 }
 474
 475 static int bcmgenet_begin(struct net_device *dev)
 476 {
 477         struct bcmgenet_priv *priv = netdev_priv(dev);
 478
 479         /* Turn on the clock */
 480         return clk_prepare_enable(priv->clk);
 481 }
 482
 483 static void bcmgenet_complete(struct net_device *dev)
 484 {
 485         struct bcmgenet_priv *priv = netdev_priv(dev);
 486
 487         /* Turn off the clock */
 488         clk_disable_unprepare(priv->clk);
 489 }
 490
 491 static int bcmgenet_get_link_ksettings(struct net_device *dev,
 492                                        struct ethtool_link_ksettings *cmd)
 493 {
 494         if (!netif_running(dev))
 495                 return -EINVAL;
 496
 497         if (!dev->phydev)
 498                 return -ENODEV;
 499
 500         phy_ethtool_ksettings_get(dev->phydev, cmd);
 501
 502         return 0;
 503 }
 504
 505 static int bcmgenet_set_link_ksettings(struct net_device *dev,
 506                                        const struct ethtool_link_ksettings *cmd)
 507 {
 508         if (!netif_running(dev))
 509                 return -EINVAL;
 510
 511         if (!dev->phydev)
 512                 return -ENODEV;
 513
 514         return phy_ethtool_ksettings_set(dev->phydev, cmd);
 515 }
 516
 517 static int bcmgenet_set_rx_csum(struct net_device *dev,
 518                                 netdev_features_t wanted)
 519 {
 520         struct bcmgenet_priv *priv = netdev_priv(dev);
 521         u32 rbuf_chk_ctrl;
 522         bool rx_csum_en;
 523
 524         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 525
 526         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 527
 528         /* enable rx checksumming */
 529         if (rx_csum_en)
 530                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 531         else
 532                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 533         priv->desc_rxchk_en = rx_csum_en;
 534
 535         /* If UniMAC forwards CRC, we need to skip over it to get
 536          * a valid CHK bit to be set in the per-packet status word
 537         */
 538         if (rx_csum_en && priv->crc_fwd_en)
 539                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 540         else
 541                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 542
 543         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 544
 545         return 0;
 546 }
 547
 548 static int bcmgenet_set_tx_csum(struct net_device *dev,
 549                                 netdev_features_t wanted)
 550 {
 551         struct bcmgenet_priv *priv = netdev_priv(dev);
 552         bool desc_64b_en;
 553         u32 tbuf_ctrl, rbuf_ctrl;
 554
 555         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 556         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 557
 558         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 559
 560         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 561         if (desc_64b_en) {
 562                 tbuf_ctrl |= RBUF_64B_EN;
 563                 rbuf_ctrl |= RBUF_64B_EN;
 564         } else {
 565                 tbuf_ctrl &= ~RBUF_64B_EN;
 566                 rbuf_ctrl &= ~RBUF_64B_EN;
 567         }
 568         priv->desc_64b_en = desc_64b_en;
 569
 570         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 571         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 572
 573         return 0;
 574 }
 575
 576 static int bcmgenet_set_features(struct net_device *dev,
 577                                  netdev_features_t features)
 578 {
 579         netdev_features_t changed = features ^ dev->features;
 580         netdev_features_t wanted = dev->wanted_features;
 581         int ret = 0;
 582
 583         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 584                 ret = bcmgenet_set_tx_csum(dev, wanted);
 585         if (changed & (NETIF_F_RXCSUM))
 586                 ret = bcmgenet_set_rx_csum(dev, wanted);
 587
 588         return ret;
 589 }
 590
 591 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 592 {
 593         struct bcmgenet_priv *priv = netdev_priv(dev);
 594
 595         return priv->msg_enable;
 596 }
 597
 598 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 599 {
 600         struct bcmgenet_priv *priv = netdev_priv(dev);
 601
 602         priv->msg_enable = level;
 603 }
 604
 605 static int bcmgenet_get_coalesce(struct net_device *dev,
 606                                  struct ethtool_coalesce *ec)
 607 {
 608         struct bcmgenet_priv *priv = netdev_priv(dev);
 609         struct bcmgenet_rx_ring *ring;
 610         unsigned int i;
 611
 612         ec->tx_max_coalesced_frames =
 613                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 614                                          DMA_MBUF_DONE_THRESH);
 615         ec->rx_max_coalesced_frames =
 616                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 617                                          DMA_MBUF_DONE_THRESH);
 618         ec->rx_coalesce_usecs =
 619                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 620
 621         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 622                 ring = &priv->rx_rings[i];
 623                 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
 624         }
 625         ring = &priv->rx_rings[DESC_INDEX];
 626         ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
 627
 628         return 0;
 629 }
 630
 631 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
 632                                      u32 usecs, u32 pkts)
 633 {
 634         struct bcmgenet_priv *priv = ring->priv;
 635         unsigned int i = ring->index;
 636         u32 reg;
 637
 638         bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
 639
 640         reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 641         reg &= ~DMA_TIMEOUT_MASK;
 642         reg |= DIV_ROUND_UP(usecs * 1000, 8192);
 643         bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 644 }
 645
 646 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
 647                                           struct ethtool_coalesce *ec)
 648 {
 649         struct net_dim_cq_moder moder;
 650         u32 usecs, pkts;
 651
 652         ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
 653         ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
 654         usecs = ring->rx_coalesce_usecs;
 655         pkts = ring->rx_max_coalesced_frames;
 656
 657         if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
 658                 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
 659                 usecs = moder.usec;
 660                 pkts = moder.pkts;
 661         }
 662
 663         ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
 664         bcmgenet_set_rx_coalesce(ring, usecs, pkts);
 665 }
 666
 667 static int bcmgenet_set_coalesce(struct net_device *dev,
 668                                  struct ethtool_coalesce *ec)
 669 {
 670         struct bcmgenet_priv *priv = netdev_priv(dev);
 671         unsigned int i;
 672
 673         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 674          * divided by 1024, which yields roughly 8.192us, our maximum value
 675          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 676          */
 677         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 678             ec->tx_max_coalesced_frames == 0 ||
 679             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 680             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 681                 return -EINVAL;
 682
 683         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 684                 return -EINVAL;
 685
 686         /* GENET TDMA hardware does not support a configurable timeout, but will
 687          * always generate an interrupt either after MBDONE packets have been
 688          * transmitted, or when the ring is empty.
 689          */
 690         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 691             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low ||
 692             ec->use_adaptive_tx_coalesce)
 693                 return -EOPNOTSUPP;
 694
 695         /* Program all TX queues with the same values, as there is no
 696          * ethtool knob to do coalescing on a per-queue basis
 697          */
 698         for (i = 0; i < priv->hw_params->tx_queues; i++)
 699                 bcmgenet_tdma_ring_writel(priv, i,
 700                                           ec->tx_max_coalesced_frames,
 701                                           DMA_MBUF_DONE_THRESH);
 702         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 703                                   ec->tx_max_coalesced_frames,
 704                                   DMA_MBUF_DONE_THRESH);
 705
 706         for (i = 0; i < priv->hw_params->rx_queues; i++)
 707                 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
 708         bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
 709
 710         return 0;
 711 }
 712
 713 /* standard ethtool support functions. */
 714 enum bcmgenet_stat_type {
 715         BCMGENET_STAT_NETDEV = -1,
 716         BCMGENET_STAT_MIB_RX,
 717         BCMGENET_STAT_MIB_TX,
 718         BCMGENET_STAT_RUNT,
 719         BCMGENET_STAT_MISC,
 720         BCMGENET_STAT_SOFT,
 721 };
 722
 723 struct bcmgenet_stats {
 724         char stat_string[ETH_GSTRING_LEN];
 725         int stat_sizeof;
 726         int stat_offset;
 727         enum bcmgenet_stat_type type;
 728         /* reg offset from UMAC base for misc counters */
 729         u16 reg_offset;
 730 };
 731
 732 #define STAT_NETDEV(m) { \
 733         .stat_string = __stringify(m), \
 734         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 735         .stat_offset = offsetof(struct net_device_stats, m), \
 736         .type = BCMGENET_STAT_NETDEV, \
 737 }
 738
 739 #define STAT_GENET_MIB(str, m, _type) { \
 740         .stat_string = str, \
 741         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 742         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 743         .type = _type, \
 744 }
 745
 746 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 747 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 748 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 749 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 750
 751 #define STAT_GENET_MISC(str, m, offset) { \
 752         .stat_string = str, \
 753         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 754         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 755         .type = BCMGENET_STAT_MISC, \
 756         .reg_offset = offset, \
 757 }
 758
 759 #define STAT_GENET_Q(num) \
 760         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
 761                         tx_rings[num].packets), \
 762         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
 763                         tx_rings[num].bytes), \
 764         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
 765                         rx_rings[num].bytes),    \
 766         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
 767                         rx_rings[num].packets), \
 768         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
 769                         rx_rings[num].errors), \
 770         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
 771                         rx_rings[num].dropped)
 772
 773 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 774  * between the end of TX stats and the beginning of the RX RUNT
 775  */
 776 #define BCMGENET_STAT_OFFSET    0xc
 777
 778 /* Hardware counters must be kept in sync because the order/offset
 779  * is important here (order in structure declaration = order in hardware)
 780  */
 781 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 782         /* general stats */
 783         STAT_NETDEV(rx_packets),
 784         STAT_NETDEV(tx_packets),
 785         STAT_NETDEV(rx_bytes),
 786         STAT_NETDEV(tx_bytes),
 787         STAT_NETDEV(rx_errors),
 788         STAT_NETDEV(tx_errors),
 789         STAT_NETDEV(rx_dropped),
 790         STAT_NETDEV(tx_dropped),
 791         STAT_NETDEV(multicast),
 792         /* UniMAC RSV counters */
 793         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 794         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 795         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 796         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 797         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 798         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 799         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 800         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 801         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 802         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 803         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 804         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 805         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 806         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 807         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 808         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 809         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 810         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 811         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 812         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 813         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 814         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 815         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 816         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 817         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 818         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 819         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 820         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 821         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 822         /* UniMAC TSV counters */
 823         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 824         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 825         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 826         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 827         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 828         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 829         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 830         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 831         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 832         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 833         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 834         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 835         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 836         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 837         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 838         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 839         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 840         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 841         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 842         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 843         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 844         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 845         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 846         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 847         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 848         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 849         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 850         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 851         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 852         /* UniMAC RUNT counters */
 853         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 854         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 855         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 856         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 857         /* Misc UniMAC counters */
 858         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 859                         UMAC_RBUF_OVFL_CNT_V1),
 860         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
 861                         UMAC_RBUF_ERR_CNT_V1),
 862         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 863         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 864         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 865         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 866         /* Per TX queues */
 867         STAT_GENET_Q(0),
 868         STAT_GENET_Q(1),
 869         STAT_GENET_Q(2),
 870         STAT_GENET_Q(3),
 871         STAT_GENET_Q(16),
 872 };
 873
 874 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 875
 876 static void bcmgenet_get_drvinfo(struct net_device *dev,
 877                                  struct ethtool_drvinfo *info)
 878 {
 879         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 880         strlcpy(info->version, "v2.0", sizeof(info->version));
 881 }
 882
 883 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 884 {
 885         switch (string_set) {
 886         case ETH_SS_STATS:
 887                 return BCMGENET_STATS_LEN;
 888         default:
 889                 return -EOPNOTSUPP;
 890         }
 891 }
 892
 893 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 894                                  u8 *data)
 895 {
 896         int i;
 897
 898         switch (stringset) {
 899         case ETH_SS_STATS:
 900                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 901                         memcpy(data + i * ETH_GSTRING_LEN,
 902                                bcmgenet_gstrings_stats[i].stat_string,
 903                                ETH_GSTRING_LEN);
 904                 }
 905                 break;
 906         }
 907 }
 908
 909 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
 910 {
 911         u16 new_offset;
 912         u32 val;
 913
 914         switch (offset) {
 915         case UMAC_RBUF_OVFL_CNT_V1:
 916                 if (GENET_IS_V2(priv))
 917                         new_offset = RBUF_OVFL_CNT_V2;
 918                 else
 919                         new_offset = RBUF_OVFL_CNT_V3PLUS;
 920
 921                 val = bcmgenet_rbuf_readl(priv, new_offset);
 922                 /* clear if overflowed */
 923                 if (val == ~0)
 924                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 925                 break;
 926         case UMAC_RBUF_ERR_CNT_V1:
 927                 if (GENET_IS_V2(priv))
 928                         new_offset = RBUF_ERR_CNT_V2;
 929                 else
 930                         new_offset = RBUF_ERR_CNT_V3PLUS;
 931
 932                 val = bcmgenet_rbuf_readl(priv, new_offset);
 933                 /* clear if overflowed */
 934                 if (val == ~0)
 935                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 936                 break;
 937         default:
 938                 val = bcmgenet_umac_readl(priv, offset);
 939                 /* clear if overflowed */
 940                 if (val == ~0)
 941                         bcmgenet_umac_writel(priv, 0, offset);
 942                 break;
 943         }
 944
 945         return val;
 946 }
 947
 948 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 949 {
 950         int i, j = 0;
 951
 952         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 953                 const struct bcmgenet_stats *s;
 954                 u8 offset = 0;
 955                 u32 val = 0;
 956                 char *p;
 957
 958                 s = &bcmgenet_gstrings_stats[i];
 959                 switch (s->type) {
 960                 case BCMGENET_STAT_NETDEV:
 961                 case BCMGENET_STAT_SOFT:
 962                         continue;
 963                 case BCMGENET_STAT_RUNT:
 964                         offset += BCMGENET_STAT_OFFSET;
 965                         /* fall through */
 966                 case BCMGENET_STAT_MIB_TX:
 967                         offset += BCMGENET_STAT_OFFSET;
 968                         /* fall through */
 969                 case BCMGENET_STAT_MIB_RX:
 970                         val = bcmgenet_umac_readl(priv,
 971                                                   UMAC_MIB_START + j + offset);
 972                         offset = 0;     /* Reset Offset */
 973                         break;
 974                 case BCMGENET_STAT_MISC:
 975                         if (GENET_IS_V1(priv)) {
 976                                 val = bcmgenet_umac_readl(priv, s->reg_offset);
 977                                 /* clear if overflowed */
 978                                 if (val == ~0)
 979                                         bcmgenet_umac_writel(priv, 0,
 980                                                              s->reg_offset);
 981                         } else {
 982                                 val = bcmgenet_update_stat_misc(priv,
 983                                                                 s->reg_offset);
 984                         }
 985                         break;
 986                 }
 987
 988                 j += s->stat_sizeof;
 989                 p = (char *)priv + s->stat_offset;
 990                 *(u32 *)p = val;
 991         }
 992 }
 993
 994 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 995                                        struct ethtool_stats *stats,
 996                                        u64 *data)
 997 {
 998         struct bcmgenet_priv *priv = netdev_priv(dev);
 999         int i;
1000
1001         if (netif_running(dev))
1002                 bcmgenet_update_mib_counters(priv);
1003
1004         dev->netdev_ops->ndo_get_stats(dev);
1005
1006         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1007                 const struct bcmgenet_stats *s;
1008                 char *p;
1009
1010                 s = &bcmgenet_gstrings_stats[i];
1011                 if (s->type == BCMGENET_STAT_NETDEV)
1012                         p = (char *)&dev->stats;
1013                 else
1014                         p = (char *)priv;
1015                 p += s->stat_offset;
1016                 if (sizeof(unsigned long) != sizeof(u32) &&
1017                     s->stat_sizeof == sizeof(unsigned long))
1018                         data[i] = *(unsigned long *)p;
1019                 else
1020                         data[i] = *(u32 *)p;
1021         }
1022 }
1023
1024 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1025 {
1026         struct bcmgenet_priv *priv = netdev_priv(dev);
1027         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1028         u32 reg;
1029
1030         if (enable && !priv->clk_eee_enabled) {
1031                 clk_prepare_enable(priv->clk_eee);
1032                 priv->clk_eee_enabled = true;
1033         }
1034
1035         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1036         if (enable)
1037                 reg |= EEE_EN;
1038         else
1039                 reg &= ~EEE_EN;
1040         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1041
1042         /* Enable EEE and switch to a 27Mhz clock automatically */
1043         reg = bcmgenet_readl(priv->base + off);
1044         if (enable)
1045                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1046         else
1047                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1048         bcmgenet_writel(reg, priv->base + off);
1049
1050         /* Do the same for thing for RBUF */
1051         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1052         if (enable)
1053                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1054         else
1055                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1056         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1057
1058         if (!enable && priv->clk_eee_enabled) {
1059                 clk_disable_unprepare(priv->clk_eee);
1060                 priv->clk_eee_enabled = false;
1061         }
1062
1063         priv->eee.eee_enabled = enable;
1064         priv->eee.eee_active = enable;
1065 }
1066
1067 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1068 {
1069         struct bcmgenet_priv *priv = netdev_priv(dev);
1070         struct ethtool_eee *p = &priv->eee;
1071
1072         if (GENET_IS_V1(priv))
1073                 return -EOPNOTSUPP;
1074
1075         if (!dev->phydev)
1076                 return -ENODEV;
1077
1078         e->eee_enabled = p->eee_enabled;
1079         e->eee_active = p->eee_active;
1080         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1081
1082         return phy_ethtool_get_eee(dev->phydev, e);
1083 }
1084
1085 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1086 {
1087         struct bcmgenet_priv *priv = netdev_priv(dev);
1088         struct ethtool_eee *p = &priv->eee;
1089         int ret = 0;
1090
1091         if (GENET_IS_V1(priv))
1092                 return -EOPNOTSUPP;
1093
1094         if (!dev->phydev)
1095                 return -ENODEV;
1096
1097         p->eee_enabled = e->eee_enabled;
1098
1099         if (!p->eee_enabled) {
1100                 bcmgenet_eee_enable_set(dev, false);
1101         } else {
1102                 ret = phy_init_eee(dev->phydev, 0);
1103                 if (ret) {
1104                         netif_err(priv, hw, dev, "EEE initialization failed\n");
1105                         return ret;
1106                 }
1107
1108                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1109                 bcmgenet_eee_enable_set(dev, true);
1110         }
1111
1112         return phy_ethtool_set_eee(dev->phydev, e);
1113 }
1114
1115 /* standard ethtool support functions. */
1116 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1117         .begin                  = bcmgenet_begin,
1118         .complete               = bcmgenet_complete,
1119         .get_strings            = bcmgenet_get_strings,
1120         .get_sset_count         = bcmgenet_get_sset_count,
1121         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
1122         .get_drvinfo            = bcmgenet_get_drvinfo,
1123         .get_link               = ethtool_op_get_link,
1124         .get_msglevel           = bcmgenet_get_msglevel,
1125         .set_msglevel           = bcmgenet_set_msglevel,
1126         .get_wol                = bcmgenet_get_wol,
1127         .set_wol                = bcmgenet_set_wol,
1128         .get_eee                = bcmgenet_get_eee,
1129         .set_eee                = bcmgenet_set_eee,
1130         .nway_reset             = phy_ethtool_nway_reset,
1131         .get_coalesce           = bcmgenet_get_coalesce,
1132         .set_coalesce           = bcmgenet_set_coalesce,
1133         .get_link_ksettings     = bcmgenet_get_link_ksettings,
1134         .set_link_ksettings     = bcmgenet_set_link_ksettings,
1135 };
1136
1137 /* Power down the unimac, based on mode. */
1138 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1139                                 enum bcmgenet_power_mode mode)
1140 {
1141         int ret = 0;
1142         u32 reg;
1143
1144         switch (mode) {
1145         case GENET_POWER_CABLE_SENSE:
1146                 phy_detach(priv->dev->phydev);
1147                 break;
1148
1149         case GENET_POWER_WOL_MAGIC:
1150                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1151                 break;
1152
1153         case GENET_POWER_PASSIVE:
1154                 /* Power down LED */
1155                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1156                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1157                         if (GENET_IS_V5(priv))
1158                                 reg |= EXT_PWR_DOWN_PHY_EN |
1159                                        EXT_PWR_DOWN_PHY_RD |
1160                                        EXT_PWR_DOWN_PHY_SD |
1161                                        EXT_PWR_DOWN_PHY_RX |
1162                                        EXT_PWR_DOWN_PHY_TX |
1163                                        EXT_IDDQ_GLBL_PWR;
1164                         else
1165                                 reg |= EXT_PWR_DOWN_PHY;
1166
1167                         reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1168                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1169
1170                         bcmgenet_phy_power_set(priv->dev, false);
1171                 }
1172                 break;
1173         default:
1174                 break;
1175         }
1176
1177         return ret;
1178 }
1179
1180 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1181                               enum bcmgenet_power_mode mode)
1182 {
1183         u32 reg;
1184
1185         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1186                 return;
1187
1188         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1189
1190         switch (mode) {
1191         case GENET_POWER_PASSIVE:
1192                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1193                          EXT_ENERGY_DET_MASK);
1194                 if (GENET_IS_V5(priv)) {
1195                         reg &= ~(EXT_PWR_DOWN_PHY_EN |
1196                                  EXT_PWR_DOWN_PHY_RD |
1197                                  EXT_PWR_DOWN_PHY_SD |
1198                                  EXT_PWR_DOWN_PHY_RX |
1199                                  EXT_PWR_DOWN_PHY_TX |
1200                                  EXT_IDDQ_GLBL_PWR);
1201                         reg |=   EXT_PHY_RESET;
1202                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1203                         mdelay(1);
1204
1205                         reg &=  ~EXT_PHY_RESET;
1206                 } else {
1207                         reg &= ~EXT_PWR_DOWN_PHY;
1208                         reg |= EXT_PWR_DN_EN_LD;
1209                 }
1210                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1211                 bcmgenet_phy_power_set(priv->dev, true);
1212                 break;
1213
1214         case GENET_POWER_CABLE_SENSE:
1215                 /* enable APD */
1216                 if (!GENET_IS_V5(priv)) {
1217                         reg |= EXT_PWR_DN_EN_LD;
1218                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1219                 }
1220                 break;
1221         case GENET_POWER_WOL_MAGIC:
1222                 bcmgenet_wol_power_up_cfg(priv, mode);
1223                 return;
1224         default:
1225                 break;
1226         }
1227 }
1228
1229 /* ioctl handle special commands that are not present in ethtool. */
1230 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1231 {
1232         if (!netif_running(dev))
1233                 return -EINVAL;
1234
1235         if (!dev->phydev)
1236                 return -ENODEV;
1237
1238         return phy_mii_ioctl(dev->phydev, rq, cmd);
1239 }
1240
1241 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1242                                          struct bcmgenet_tx_ring *ring)
1243 {
1244         struct enet_cb *tx_cb_ptr;
1245
1246         tx_cb_ptr = ring->cbs;
1247         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1248
1249         /* Advancing local write pointer */
1250         if (ring->write_ptr == ring->end_ptr)
1251                 ring->write_ptr = ring->cb_ptr;
1252         else
1253                 ring->write_ptr++;
1254
1255         return tx_cb_ptr;
1256 }
1257
1258 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1259                                          struct bcmgenet_tx_ring *ring)
1260 {
1261         struct enet_cb *tx_cb_ptr;
1262
1263         tx_cb_ptr = ring->cbs;
1264         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1265
1266         /* Rewinding local write pointer */
1267         if (ring->write_ptr == ring->cb_ptr)
1268                 ring->write_ptr = ring->end_ptr;
1269         else
1270                 ring->write_ptr--;
1271
1272         return tx_cb_ptr;
1273 }
1274
1275 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1276 {
1277         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1278                                  INTRL2_CPU_MASK_SET);
1279 }
1280
1281 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1282 {
1283         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1284                                  INTRL2_CPU_MASK_CLEAR);
1285 }
1286
1287 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1288 {
1289         bcmgenet_intrl2_1_writel(ring->priv,
1290                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1291                                  INTRL2_CPU_MASK_SET);
1292 }
1293
1294 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1295 {
1296         bcmgenet_intrl2_1_writel(ring->priv,
1297                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1298                                  INTRL2_CPU_MASK_CLEAR);
1299 }
1300
1301 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1302 {
1303         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1304                                  INTRL2_CPU_MASK_SET);
1305 }
1306
1307 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1308 {
1309         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1310                                  INTRL2_CPU_MASK_CLEAR);
1311 }
1312
1313 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1314 {
1315         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1316                                  INTRL2_CPU_MASK_CLEAR);
1317 }
1318
1319 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1320 {
1321         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1322                                  INTRL2_CPU_MASK_SET);
1323 }
1324
1325 /* Simple helper to free a transmit control block's resources
1326  * Returns an skb when the last transmit control block associated with the
1327  * skb is freed.  The skb should be freed by the caller if necessary.
1328  */
1329 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1330                                            struct enet_cb *cb)
1331 {
1332         struct sk_buff *skb;
1333
1334         skb = cb->skb;
1335
1336         if (skb) {
1337                 cb->skb = NULL;
1338                 if (cb == GENET_CB(skb)->first_cb)
1339                         dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1340                                          dma_unmap_len(cb, dma_len),
1341                                          DMA_TO_DEVICE);
1342                 else
1343                         dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1344                                        dma_unmap_len(cb, dma_len),
1345                                        DMA_TO_DEVICE);
1346                 dma_unmap_addr_set(cb, dma_addr, 0);
1347
1348                 if (cb == GENET_CB(skb)->last_cb)
1349                         return skb;
1350
1351         } else if (dma_unmap_addr(cb, dma_addr)) {
1352                 dma_unmap_page(dev,
1353                                dma_unmap_addr(cb, dma_addr),
1354                                dma_unmap_len(cb, dma_len),
1355                                DMA_TO_DEVICE);
1356                 dma_unmap_addr_set(cb, dma_addr, 0);
1357         }
1358
1359         return NULL;
1360 }
1361
1362 /* Simple helper to free a receive control block's resources */
1363 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1364                                            struct enet_cb *cb)
1365 {
1366         struct sk_buff *skb;
1367
1368         skb = cb->skb;
1369         cb->skb = NULL;
1370
1371         if (dma_unmap_addr(cb, dma_addr)) {
1372                 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1373                                  dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1374                 dma_unmap_addr_set(cb, dma_addr, 0);
1375         }
1376
1377         return skb;
1378 }
1379
1380 /* Unlocked version of the reclaim routine */
1381 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1382                                           struct bcmgenet_tx_ring *ring)
1383 {
1384         struct bcmgenet_priv *priv = netdev_priv(dev);
1385         unsigned int txbds_processed = 0;
1386         unsigned int bytes_compl = 0;
1387         unsigned int pkts_compl = 0;
1388         unsigned int txbds_ready;
1389         unsigned int c_index;
1390         struct sk_buff *skb;
1391
1392         /* Clear status before servicing to reduce spurious interrupts */
1393         if (ring->index == DESC_INDEX)
1394                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1395                                          INTRL2_CPU_CLEAR);
1396         else
1397                 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1398                                          INTRL2_CPU_CLEAR);
1399
1400         /* Compute how many buffers are transmitted since last xmit call */
1401         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1402                 & DMA_C_INDEX_MASK;
1403         txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1404
1405         netif_dbg(priv, tx_done, dev,
1406                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1407                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1408
1409         /* Reclaim transmitted buffers */
1410         while (txbds_processed < txbds_ready) {
1411                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1412                                           &priv->tx_cbs[ring->clean_ptr]);
1413                 if (skb) {
1414                         pkts_compl++;
1415                         bytes_compl += GENET_CB(skb)->bytes_sent;
1416                         dev_consume_skb_any(skb);
1417                 }
1418
1419                 txbds_processed++;
1420                 if (likely(ring->clean_ptr < ring->end_ptr))
1421                         ring->clean_ptr++;
1422                 else
1423                         ring->clean_ptr = ring->cb_ptr;
1424         }
1425
1426         ring->free_bds += txbds_processed;
1427         ring->c_index = c_index;
1428
1429         ring->packets += pkts_compl;
1430         ring->bytes += bytes_compl;
1431
1432         netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1433                                   pkts_compl, bytes_compl);
1434
1435         return txbds_processed;
1436 }
1437
1438 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1439                                 struct bcmgenet_tx_ring *ring)
1440 {
1441         unsigned int released;
1442
1443         spin_lock_bh(&ring->lock);
1444         released = __bcmgenet_tx_reclaim(dev, ring);
1445         spin_unlock_bh(&ring->lock);
1446
1447         return released;
1448 }
1449
1450 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1451 {
1452         struct bcmgenet_tx_ring *ring =
1453                 container_of(napi, struct bcmgenet_tx_ring, napi);
1454         unsigned int work_done = 0;
1455         struct netdev_queue *txq;
1456
1457         spin_lock(&ring->lock);
1458         work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1459         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1460                 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1461                 netif_tx_wake_queue(txq);
1462         }
1463         spin_unlock(&ring->lock);
1464
1465         if (work_done == 0) {
1466                 napi_complete(napi);
1467                 ring->int_enable(ring);
1468
1469                 return 0;
1470         }
1471
1472         return budget;
1473 }
1474
1475 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1476 {
1477         struct bcmgenet_priv *priv = netdev_priv(dev);
1478         int i;
1479
1480         if (netif_is_multiqueue(dev)) {
1481                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1482                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1483         }
1484
1485         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1486 }
1487
1488 /* Reallocate the SKB to put enough headroom in front of it and insert
1489  * the transmit checksum offsets in the descriptors
1490  */
1491 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1492                                             struct sk_buff *skb)
1493 {
1494         struct status_64 *status = NULL;
1495         struct sk_buff *new_skb;
1496         u16 offset;
1497         u8 ip_proto;
1498         __be16 ip_ver;
1499         u32 tx_csum_info;
1500
1501         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1502                 /* If 64 byte status block enabled, must make sure skb has
1503                  * enough headroom for us to insert 64B status block.
1504                  */
1505                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1506                 dev_kfree_skb(skb);
1507                 if (!new_skb) {
1508                         dev->stats.tx_dropped++;
1509                         return NULL;
1510                 }
1511                 skb = new_skb;
1512         }
1513
1514         skb_push(skb, sizeof(*status));
1515         status = (struct status_64 *)skb->data;
1516
1517         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1518                 ip_ver = skb->protocol;
1519                 switch (ip_ver) {
1520                 case htons(ETH_P_IP):
1521                         ip_proto = ip_hdr(skb)->protocol;
1522                         break;
1523                 case htons(ETH_P_IPV6):
1524                         ip_proto = ipv6_hdr(skb)->nexthdr;
1525                         break;
1526                 default:
1527                         return skb;
1528                 }
1529
1530                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1531                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1532                                 (offset + skb->csum_offset);
1533
1534                 /* Set the length valid bit for TCP and UDP and just set
1535                  * the special UDP flag for IPv4, else just set to 0.
1536                  */
1537                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1538                         tx_csum_info |= STATUS_TX_CSUM_LV;
1539                         if (ip_proto == IPPROTO_UDP &&
1540                             ip_ver == htons(ETH_P_IP))
1541                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1542                 } else {
1543                         tx_csum_info = 0;
1544                 }
1545
1546                 status->tx_csum_info = tx_csum_info;
1547         }
1548
1549         return skb;
1550 }
1551
1552 static void bcmgenet_hide_tsb(struct sk_buff *skb)
1553 {
1554         __skb_pull(skb, sizeof(struct status_64));
1555 }
1556
1557 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1558 {
1559         struct bcmgenet_priv *priv = netdev_priv(dev);
1560         struct device *kdev = &priv->pdev->dev;
1561         struct bcmgenet_tx_ring *ring = NULL;
1562         struct enet_cb *tx_cb_ptr;
1563         struct netdev_queue *txq;
1564         int nr_frags, index;
1565         dma_addr_t mapping;
1566         unsigned int size;
1567         skb_frag_t *frag;
1568         u32 len_stat;
1569         int ret;
1570         int i;
1571
1572         index = skb_get_queue_mapping(skb);
1573         /* Mapping strategy:
1574          * queue_mapping = 0, unclassified, packet xmited through ring16
1575          * queue_mapping = 1, goes to ring 0. (highest priority queue
1576          * queue_mapping = 2, goes to ring 1.
1577          * queue_mapping = 3, goes to ring 2.
1578          * queue_mapping = 4, goes to ring 3.
1579          */
1580         if (index == 0)
1581                 index = DESC_INDEX;
1582         else
1583                 index -= 1;
1584
1585         ring = &priv->tx_rings[index];
1586         txq = netdev_get_tx_queue(dev, ring->queue);
1587
1588         nr_frags = skb_shinfo(skb)->nr_frags;
1589
1590         spin_lock(&ring->lock);
1591         if (ring->free_bds <= (nr_frags + 1)) {
1592                 if (!netif_tx_queue_stopped(txq)) {
1593                         netif_tx_stop_queue(txq);
1594                         netdev_err(dev,
1595                                    "%s: tx ring %d full when queue %d awake\n",
1596                                    __func__, index, ring->queue);
1597                 }
1598                 ret = NETDEV_TX_BUSY;
1599                 goto out;
1600         }
1601
1602         /* Retain how many bytes will be sent on the wire, without TSB inserted
1603          * by transmit checksum offload
1604          */
1605         GENET_CB(skb)->bytes_sent = skb->len;
1606
1607         /* set the SKB transmit checksum */
1608         if (priv->desc_64b_en) {
1609                 skb = bcmgenet_put_tx_csum(dev, skb);
1610                 if (!skb) {
1611                         ret = NETDEV_TX_OK;
1612                         goto out;
1613                 }
1614         }
1615
1616         for (i = 0; i <= nr_frags; i++) {
1617                 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1618
1619                 BUG_ON(!tx_cb_ptr);
1620
1621                 if (!i) {
1622                         /* Transmit single SKB or head of fragment list */
1623                         GENET_CB(skb)->first_cb = tx_cb_ptr;
1624                         size = skb_headlen(skb);
1625                         mapping = dma_map_single(kdev, skb->data, size,
1626                                                  DMA_TO_DEVICE);
1627                 } else {
1628                         /* xmit fragment */
1629                         frag = &skb_shinfo(skb)->frags[i - 1];
1630                         size = skb_frag_size(frag);
1631                         mapping = skb_frag_dma_map(kdev, frag, 0, size,
1632                                                    DMA_TO_DEVICE);
1633                 }
1634
1635                 ret = dma_mapping_error(kdev, mapping);
1636                 if (ret) {
1637                         priv->mib.tx_dma_failed++;
1638                         netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1639                         ret = NETDEV_TX_OK;
1640                         goto out_unmap_frags;
1641                 }
1642                 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1643                 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1644
1645                 tx_cb_ptr->skb = skb;
1646
1647                 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1648                            (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1649
1650                 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
1651                  * will need to restore software padding of "runt" packets
1652                  */
1653                 if (!i) {
1654                         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1655                         if (skb->ip_summed == CHECKSUM_PARTIAL)
1656                                 len_stat |= DMA_TX_DO_CSUM;
1657                 }
1658                 if (i == nr_frags)
1659                         len_stat |= DMA_EOP;
1660
1661                 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1662         }
1663
1664         GENET_CB(skb)->last_cb = tx_cb_ptr;
1665
1666         bcmgenet_hide_tsb(skb);
1667         skb_tx_timestamp(skb);
1668
1669         /* Decrement total BD count and advance our write pointer */
1670         ring->free_bds -= nr_frags + 1;
1671         ring->prod_index += nr_frags + 1;
1672         ring->prod_index &= DMA_P_INDEX_MASK;
1673
1674         netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1675
1676         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1677                 netif_tx_stop_queue(txq);
1678
1679         if (!skb->xmit_more || netif_xmit_stopped(txq))
1680                 /* Packets are ready, update producer index */
1681                 bcmgenet_tdma_ring_writel(priv, ring->index,
1682                                           ring->prod_index, TDMA_PROD_INDEX);
1683 out:
1684         spin_unlock(&ring->lock);
1685
1686         return ret;
1687
1688 out_unmap_frags:
1689         /* Back up for failed control block mapping */
1690         bcmgenet_put_txcb(priv, ring);
1691
1692         /* Unmap successfully mapped control blocks */
1693         while (i-- > 0) {
1694                 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1695                 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1696         }
1697
1698         dev_kfree_skb(skb);
1699         goto out;
1700 }
1701
1702 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1703                                           struct enet_cb *cb)
1704 {
1705         struct device *kdev = &priv->pdev->dev;
1706         struct sk_buff *skb;
1707         struct sk_buff *rx_skb;
1708         dma_addr_t mapping;
1709
1710         /* Allocate a new Rx skb */
1711         skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
1712                                  GFP_ATOMIC | __GFP_NOWARN);
1713         if (!skb) {
1714                 priv->mib.alloc_rx_buff_failed++;
1715                 netif_err(priv, rx_err, priv->dev,
1716                           "%s: Rx skb allocation failed\n", __func__);
1717                 return NULL;
1718         }
1719
1720         /* DMA-map the new Rx skb */
1721         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1722                                  DMA_FROM_DEVICE);
1723         if (dma_mapping_error(kdev, mapping)) {
1724                 priv->mib.rx_dma_failed++;
1725                 dev_kfree_skb_any(skb);
1726                 netif_err(priv, rx_err, priv->dev,
1727                           "%s: Rx skb DMA mapping failed\n", __func__);
1728                 return NULL;
1729         }
1730
1731         /* Grab the current Rx skb from the ring and DMA-unmap it */
1732         rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1733
1734         /* Put the new Rx skb on the ring */
1735         cb->skb = skb;
1736         dma_unmap_addr_set(cb, dma_addr, mapping);
1737         dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1738         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1739
1740         /* Return the current Rx skb to caller */
1741         return rx_skb;
1742 }
1743
1744 /* bcmgenet_desc_rx - descriptor based rx process.
1745  * this could be called from bottom half, or from NAPI polling method.
1746  */
1747 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1748                                      unsigned int budget)
1749 {
1750         struct bcmgenet_priv *priv = ring->priv;
1751         struct net_device *dev = priv->dev;
1752         struct enet_cb *cb;
1753         struct sk_buff *skb;
1754         u32 dma_length_status;
1755         unsigned long dma_flag;
1756         int len;
1757         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1758         unsigned int bytes_processed = 0;
1759         unsigned int p_index, mask;
1760         unsigned int discards;
1761         unsigned int chksum_ok = 0;
1762
1763         /* Clear status before servicing to reduce spurious interrupts */
1764         if (ring->index == DESC_INDEX) {
1765                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1766                                          INTRL2_CPU_CLEAR);
1767         } else {
1768                 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1769                 bcmgenet_intrl2_1_writel(priv,
1770                                          mask,
1771                                          INTRL2_CPU_CLEAR);
1772         }
1773
1774         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1775
1776         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1777                    DMA_P_INDEX_DISCARD_CNT_MASK;
1778         if (discards > ring->old_discards) {
1779                 discards = discards - ring->old_discards;
1780                 ring->errors += discards;
1781                 ring->old_discards += discards;
1782
1783                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1784                 if (ring->old_discards >= 0xC000) {
1785                         ring->old_discards = 0;
1786                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1787                                                   RDMA_PROD_INDEX);
1788                 }
1789         }
1790
1791         p_index &= DMA_P_INDEX_MASK;
1792         rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1793
1794         netif_dbg(priv, rx_status, dev,
1795                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1796
1797         while ((rxpktprocessed < rxpkttoprocess) &&
1798                (rxpktprocessed < budget)) {
1799                 cb = &priv->rx_cbs[ring->read_ptr];
1800                 skb = bcmgenet_rx_refill(priv, cb);
1801
1802                 if (unlikely(!skb)) {
1803                         ring->dropped++;
1804                         goto next;
1805                 }
1806
1807                 if (!priv->desc_64b_en) {
1808                         dma_length_status =
1809                                 dmadesc_get_length_status(priv, cb->bd_addr);
1810                 } else {
1811                         struct status_64 *status;
1812
1813                         status = (struct status_64 *)skb->data;
1814                         dma_length_status = status->length_status;
1815                 }
1816
1817                 /* DMA flags and length are still valid no matter how
1818                  * we got the Receive Status Vector (64B RSB or register)
1819                  */
1820                 dma_flag = dma_length_status & 0xffff;
1821                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1822
1823                 netif_dbg(priv, rx_status, dev,
1824                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1825                           __func__, p_index, ring->c_index,
1826                           ring->read_ptr, dma_length_status);
1827
1828                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1829                         netif_err(priv, rx_status, dev,
1830                                   "dropping fragmented packet!\n");
1831                         ring->errors++;
1832                         dev_kfree_skb_any(skb);
1833                         goto next;
1834                 }
1835
1836                 /* report errors */
1837                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1838                                                 DMA_RX_OV |
1839                                                 DMA_RX_NO |
1840                                                 DMA_RX_LG |
1841                                                 DMA_RX_RXER))) {
1842                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1843                                   (unsigned int)dma_flag);
1844                         if (dma_flag & DMA_RX_CRC_ERROR)
1845                                 dev->stats.rx_crc_errors++;
1846                         if (dma_flag & DMA_RX_OV)
1847                                 dev->stats.rx_over_errors++;
1848                         if (dma_flag & DMA_RX_NO)
1849                                 dev->stats.rx_frame_errors++;
1850                         if (dma_flag & DMA_RX_LG)
1851                                 dev->stats.rx_length_errors++;
1852                         dev->stats.rx_errors++;
1853                         dev_kfree_skb_any(skb);
1854                         goto next;
1855                 } /* error packet */
1856
1857                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1858                              priv->desc_rxchk_en;
1859
1860                 skb_put(skb, len);
1861                 if (priv->desc_64b_en) {
1862                         skb_pull(skb, 64);
1863                         len -= 64;
1864                 }
1865
1866                 if (likely(chksum_ok))
1867                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1868
1869                 /* remove hardware 2bytes added for IP alignment */
1870                 skb_pull(skb, 2);
1871                 len -= 2;
1872
1873                 if (priv->crc_fwd_en) {
1874                         skb_trim(skb, len - ETH_FCS_LEN);
1875                         len -= ETH_FCS_LEN;
1876                 }
1877
1878                 bytes_processed += len;
1879
1880                 /*Finish setting up the received SKB and send it to the kernel*/
1881                 skb->protocol = eth_type_trans(skb, priv->dev);
1882                 ring->packets++;
1883                 ring->bytes += len;
1884                 if (dma_flag & DMA_RX_MULT)
1885                         dev->stats.multicast++;
1886
1887                 /* Notify kernel */
1888                 napi_gro_receive(&ring->napi, skb);
1889                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1890
1891 next:
1892                 rxpktprocessed++;
1893                 if (likely(ring->read_ptr < ring->end_ptr))
1894                         ring->read_ptr++;
1895                 else
1896                         ring->read_ptr = ring->cb_ptr;
1897
1898                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1899                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1900         }
1901
1902         ring->dim.bytes = bytes_processed;
1903         ring->dim.packets = rxpktprocessed;
1904
1905         return rxpktprocessed;
1906 }
1907
1908 /* Rx NAPI polling method */
1909 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1910 {
1911         struct bcmgenet_rx_ring *ring = container_of(napi,
1912                         struct bcmgenet_rx_ring, napi);
1913         struct net_dim_sample dim_sample;
1914         unsigned int work_done;
1915
1916         work_done = bcmgenet_desc_rx(ring, budget);
1917
1918         if (work_done < budget) {
1919                 napi_complete_done(napi, work_done);
1920                 ring->int_enable(ring);
1921         }
1922
1923         if (ring->dim.use_dim) {
1924                 net_dim_sample(ring->dim.event_ctr, ring->dim.packets,
1925                                ring->dim.bytes, &dim_sample);
1926                 net_dim(&ring->dim.dim, dim_sample);
1927         }
1928
1929         return work_done;
1930 }
1931
1932 static void bcmgenet_dim_work(struct work_struct *work)
1933 {
1934         struct net_dim *dim = container_of(work, struct net_dim, work);
1935         struct bcmgenet_net_dim *ndim =
1936                         container_of(dim, struct bcmgenet_net_dim, dim);
1937         struct bcmgenet_rx_ring *ring =
1938                         container_of(ndim, struct bcmgenet_rx_ring, dim);
1939         struct net_dim_cq_moder cur_profile =
1940                         net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1941
1942         bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
1943         dim->state = NET_DIM_START_MEASURE;
1944 }
1945
1946 /* Assign skb to RX DMA descriptor. */
1947 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1948                                      struct bcmgenet_rx_ring *ring)
1949 {
1950         struct enet_cb *cb;
1951         struct sk_buff *skb;
1952         int i;
1953
1954         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1955
1956         /* loop here for each buffer needing assign */
1957         for (i = 0; i < ring->size; i++) {
1958                 cb = ring->cbs + i;
1959                 skb = bcmgenet_rx_refill(priv, cb);
1960                 if (skb)
1961                         dev_consume_skb_any(skb);
1962                 if (!cb->skb)
1963                         return -ENOMEM;
1964         }
1965
1966         return 0;
1967 }
1968
1969 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1970 {
1971         struct sk_buff *skb;
1972         struct enet_cb *cb;
1973         int i;
1974
1975         for (i = 0; i < priv->num_rx_bds; i++) {
1976                 cb = &priv->rx_cbs[i];
1977
1978                 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1979                 if (skb)
1980                         dev_consume_skb_any(skb);
1981         }
1982 }
1983
1984 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1985 {
1986         u32 reg;
1987
1988         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1989         if (enable)
1990                 reg |= mask;
1991         else
1992                 reg &= ~mask;
1993         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1994
1995         /* UniMAC stops on a packet boundary, wait for a full-size packet
1996          * to be processed
1997          */
1998         if (enable == 0)
1999                 usleep_range(1000, 2000);
2000 }
2001
2002 static void reset_umac(struct bcmgenet_priv *priv)
2003 {
2004         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2005         bcmgenet_rbuf_ctrl_set(priv, 0);
2006         udelay(10);
2007
2008         /* disable MAC while updating its registers */
2009         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2010
2011         /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
2012         bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
2013 }
2014
2015 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2016 {
2017         /* Mask all interrupts.*/
2018         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2019         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2020         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2021         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2022 }
2023
2024 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2025 {
2026         u32 int0_enable = 0;
2027
2028         /* Monitor cable plug/unplugged event for internal PHY, external PHY
2029          * and MoCA PHY
2030          */
2031         if (priv->internal_phy) {
2032                 int0_enable |= UMAC_IRQ_LINK_EVENT;
2033                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2034                         int0_enable |= UMAC_IRQ_PHY_DET_R;
2035         } else if (priv->ext_phy) {
2036                 int0_enable |= UMAC_IRQ_LINK_EVENT;
2037         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2038                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2039                         int0_enable |= UMAC_IRQ_LINK_EVENT;
2040         }
2041         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2042 }
2043
2044 static void init_umac(struct bcmgenet_priv *priv)
2045 {
2046         struct device *kdev = &priv->pdev->dev;
2047         u32 reg;
2048         u32 int0_enable = 0;
2049
2050         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2051
2052         reset_umac(priv);
2053
2054         /* clear tx/rx counter */
2055         bcmgenet_umac_writel(priv,
2056                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2057                              UMAC_MIB_CTRL);
2058         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2059
2060         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2061
2062         /* init rx registers, enable ip header optimization */
2063         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2064         reg |= RBUF_ALIGN_2B;
2065         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2066
2067         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2068                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2069
2070         bcmgenet_intr_disable(priv);
2071
2072         /* Configure backpressure vectors for MoCA */
2073         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2074                 reg = bcmgenet_bp_mc_get(priv);
2075                 reg |= BIT(priv->hw_params->bp_in_en_shift);
2076
2077                 /* bp_mask: back pressure mask */
2078                 if (netif_is_multiqueue(priv->dev))
2079                         reg |= priv->hw_params->bp_in_mask;
2080                 else
2081                         reg &= ~priv->hw_params->bp_in_mask;
2082                 bcmgenet_bp_mc_set(priv, reg);
2083         }
2084
2085         /* Enable MDIO interrupts on GENET v3+ */
2086         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2087                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2088
2089         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2090
2091         dev_dbg(kdev, "done init umac\n");
2092 }
2093
2094 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2095                               void (*cb)(struct work_struct *work))
2096 {
2097         struct bcmgenet_net_dim *dim = &ring->dim;
2098
2099         INIT_WORK(&dim->dim.work, cb);
2100         dim->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2101         dim->event_ctr = 0;
2102         dim->packets = 0;
2103         dim->bytes = 0;
2104 }
2105
2106 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2107 {
2108         struct bcmgenet_net_dim *dim = &ring->dim;
2109         struct net_dim_cq_moder moder;
2110         u32 usecs, pkts;
2111
2112         usecs = ring->rx_coalesce_usecs;
2113         pkts = ring->rx_max_coalesced_frames;
2114
2115         /* If DIM was enabled, re-apply default parameters */
2116         if (dim->use_dim) {
2117                 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2118                 usecs = moder.usec;
2119                 pkts = moder.pkts;
2120         }
2121
2122         bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2123 }
2124
2125 /* Initialize a Tx ring along with corresponding hardware registers */
2126 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2127                                   unsigned int index, unsigned int size,
2128                                   unsigned int start_ptr, unsigned int end_ptr)
2129 {
2130         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2131         u32 words_per_bd = WORDS_PER_BD(priv);
2132         u32 flow_period_val = 0;
2133
2134         spin_lock_init(&ring->lock);
2135         ring->priv = priv;
2136         ring->index = index;
2137         if (index == DESC_INDEX) {
2138                 ring->queue = 0;
2139                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2140                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2141         } else {
2142                 ring->queue = index + 1;
2143                 ring->int_enable = bcmgenet_tx_ring_int_enable;
2144                 ring->int_disable = bcmgenet_tx_ring_int_disable;
2145         }
2146         ring->cbs = priv->tx_cbs + start_ptr;
2147         ring->size = size;
2148         ring->clean_ptr = start_ptr;
2149         ring->c_index = 0;
2150         ring->free_bds = size;
2151         ring->write_ptr = start_ptr;
2152         ring->cb_ptr = start_ptr;
2153         ring->end_ptr = end_ptr - 1;
2154         ring->prod_index = 0;
2155
2156         /* Set flow period for ring != 16 */
2157         if (index != DESC_INDEX)
2158                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2159
2160         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2161         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2162         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2163         /* Disable rate control for now */
2164         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2165                                   TDMA_FLOW_PERIOD);
2166         bcmgenet_tdma_ring_writel(priv, index,
2167                                   ((size << DMA_RING_SIZE_SHIFT) |
2168                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2169
2170         /* Set start and end address, read and write pointers */
2171         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2172                                   DMA_START_ADDR);
2173         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2174                                   TDMA_READ_PTR);
2175         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2176                                   TDMA_WRITE_PTR);
2177         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2178                                   DMA_END_ADDR);
2179
2180         /* Initialize Tx NAPI */
2181         netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2182                           NAPI_POLL_WEIGHT);
2183 }
2184
2185 /* Initialize a RDMA ring */
2186 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2187                                  unsigned int index, unsigned int size,
2188                                  unsigned int start_ptr, unsigned int end_ptr)
2189 {
2190         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2191         u32 words_per_bd = WORDS_PER_BD(priv);
2192         int ret;
2193
2194         ring->priv = priv;
2195         ring->index = index;
2196         if (index == DESC_INDEX) {
2197                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2198                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2199         } else {
2200                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2201                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2202         }
2203         ring->cbs = priv->rx_cbs + start_ptr;
2204         ring->size = size;
2205         ring->c_index = 0;
2206         ring->read_ptr = start_ptr;
2207         ring->cb_ptr = start_ptr;
2208         ring->end_ptr = end_ptr - 1;
2209
2210         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2211         if (ret)
2212                 return ret;
2213
2214         bcmgenet_init_dim(ring, bcmgenet_dim_work);
2215         bcmgenet_init_rx_coalesce(ring);
2216
2217         /* Initialize Rx NAPI */
2218         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2219                        NAPI_POLL_WEIGHT);
2220
2221         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2222         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2223         bcmgenet_rdma_ring_writel(priv, index,
2224                                   ((size << DMA_RING_SIZE_SHIFT) |
2225                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2226         bcmgenet_rdma_ring_writel(priv, index,
2227                                   (DMA_FC_THRESH_LO <<
2228                                    DMA_XOFF_THRESHOLD_SHIFT) |
2229                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2230
2231         /* Set start and end address, read and write pointers */
2232         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2233                                   DMA_START_ADDR);
2234         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2235                                   RDMA_READ_PTR);
2236         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2237                                   RDMA_WRITE_PTR);
2238         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2239                                   DMA_END_ADDR);
2240
2241         return ret;
2242 }
2243
2244 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2245 {
2246         unsigned int i;
2247         struct bcmgenet_tx_ring *ring;
2248
2249         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2250                 ring = &priv->tx_rings[i];
2251                 napi_enable(&ring->napi);
2252                 ring->int_enable(ring);
2253         }
2254
2255         ring = &priv->tx_rings[DESC_INDEX];
2256         napi_enable(&ring->napi);
2257         ring->int_enable(ring);
2258 }
2259
2260 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2261 {
2262         unsigned int i;
2263         struct bcmgenet_tx_ring *ring;
2264
2265         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2266                 ring = &priv->tx_rings[i];
2267                 napi_disable(&ring->napi);
2268         }
2269
2270         ring = &priv->tx_rings[DESC_INDEX];
2271         napi_disable(&ring->napi);
2272 }
2273
2274 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2275 {
2276         unsigned int i;
2277         struct bcmgenet_tx_ring *ring;
2278
2279         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2280                 ring = &priv->tx_rings[i];
2281                 netif_napi_del(&ring->napi);
2282         }
2283
2284         ring = &priv->tx_rings[DESC_INDEX];
2285         netif_napi_del(&ring->napi);
2286 }
2287
2288 /* Initialize Tx queues
2289  *
2290  * Queues 0-3 are priority-based, each one has 32 descriptors,
2291  * with queue 0 being the highest priority queue.
2292  *
2293  * Queue 16 is the default Tx queue with
2294  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2295  *
2296  * The transmit control block pool is then partitioned as follows:
2297  * - Tx queue 0 uses tx_cbs[0..31]
2298  * - Tx queue 1 uses tx_cbs[32..63]
2299  * - Tx queue 2 uses tx_cbs[64..95]
2300  * - Tx queue 3 uses tx_cbs[96..127]
2301  * - Tx queue 16 uses tx_cbs[128..255]
2302  */
2303 static void bcmgenet_init_tx_queues(struct net_device *dev)
2304 {
2305         struct bcmgenet_priv *priv = netdev_priv(dev);
2306         u32 i, dma_enable;
2307         u32 dma_ctrl, ring_cfg;
2308         u32 dma_priority[3] = {0, 0, 0};
2309
2310         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2311         dma_enable = dma_ctrl & DMA_EN;
2312         dma_ctrl &= ~DMA_EN;
2313         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2314
2315         dma_ctrl = 0;
2316         ring_cfg = 0;
2317
2318         /* Enable strict priority arbiter mode */
2319         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2320
2321         /* Initialize Tx priority queues */
2322         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2323                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2324                                       i * priv->hw_params->tx_bds_per_q,
2325                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2326                 ring_cfg |= (1 << i);
2327                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2328                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2329                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2330         }
2331
2332         /* Initialize Tx default queue 16 */
2333         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2334                               priv->hw_params->tx_queues *
2335                               priv->hw_params->tx_bds_per_q,
2336                               TOTAL_DESC);
2337         ring_cfg |= (1 << DESC_INDEX);
2338         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2339         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2340                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2341                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2342
2343         /* Set Tx queue priorities */
2344         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2345         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2346         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2347
2348         /* Enable Tx queues */
2349         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2350
2351         /* Enable Tx DMA */
2352         if (dma_enable)
2353                 dma_ctrl |= DMA_EN;
2354         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2355 }
2356
2357 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2358 {
2359         unsigned int i;
2360         struct bcmgenet_rx_ring *ring;
2361
2362         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2363                 ring = &priv->rx_rings[i];
2364                 napi_enable(&ring->napi);
2365                 ring->int_enable(ring);
2366         }
2367
2368         ring = &priv->rx_rings[DESC_INDEX];
2369         napi_enable(&ring->napi);
2370         ring->int_enable(ring);
2371 }
2372
2373 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2374 {
2375         unsigned int i;
2376         struct bcmgenet_rx_ring *ring;
2377
2378         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2379                 ring = &priv->rx_rings[i];
2380                 napi_disable(&ring->napi);
2381                 cancel_work_sync(&ring->dim.dim.work);
2382         }
2383
2384         ring = &priv->rx_rings[DESC_INDEX];
2385         napi_disable(&ring->napi);
2386         cancel_work_sync(&ring->dim.dim.work);
2387 }
2388
2389 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2390 {
2391         unsigned int i;
2392         struct bcmgenet_rx_ring *ring;
2393
2394         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2395                 ring = &priv->rx_rings[i];
2396                 netif_napi_del(&ring->napi);
2397         }
2398
2399         ring = &priv->rx_rings[DESC_INDEX];
2400         netif_napi_del(&ring->napi);
2401 }
2402
2403 /* Initialize Rx queues
2404  *
2405  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2406  * used to direct traffic to these queues.
2407  *
2408  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2409  */
2410 static int bcmgenet_init_rx_queues(struct net_device *dev)
2411 {
2412         struct bcmgenet_priv *priv = netdev_priv(dev);
2413         u32 i;
2414         u32 dma_enable;
2415         u32 dma_ctrl;
2416         u32 ring_cfg;
2417         int ret;
2418
2419         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2420         dma_enable = dma_ctrl & DMA_EN;
2421         dma_ctrl &= ~DMA_EN;
2422         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2423
2424         dma_ctrl = 0;
2425         ring_cfg = 0;
2426
2427         /* Initialize Rx priority queues */
2428         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2429                 ret = bcmgenet_init_rx_ring(priv, i,
2430                                             priv->hw_params->rx_bds_per_q,
2431                                             i * priv->hw_params->rx_bds_per_q,
2432                                             (i + 1) *
2433                                             priv->hw_params->rx_bds_per_q);
2434                 if (ret)
2435                         return ret;
2436
2437                 ring_cfg |= (1 << i);
2438                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2439         }
2440
2441         /* Initialize Rx default queue 16 */
2442         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2443                                     priv->hw_params->rx_queues *
2444                                     priv->hw_params->rx_bds_per_q,
2445                                     TOTAL_DESC);
2446         if (ret)
2447                 return ret;
2448
2449         ring_cfg |= (1 << DESC_INDEX);
2450         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2451
2452         /* Enable rings */
2453         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2454
2455         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2456         if (dma_enable)
2457                 dma_ctrl |= DMA_EN;
2458         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2459
2460         return 0;
2461 }
2462
2463 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2464 {
2465         int ret = 0;
2466         int timeout = 0;
2467         u32 reg;
2468         u32 dma_ctrl;
2469         int i;
2470
2471         /* Disable TDMA to stop add more frames in TX DMA */
2472         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2473         reg &= ~DMA_EN;
2474         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2475
2476         /* Check TDMA status register to confirm TDMA is disabled */
2477         while (timeout++ < DMA_TIMEOUT_VAL) {
2478                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2479                 if (reg & DMA_DISABLED)
2480                         break;
2481
2482                 udelay(1);
2483         }
2484
2485         if (timeout == DMA_TIMEOUT_VAL) {
2486                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2487                 ret = -ETIMEDOUT;
2488         }
2489
2490         /* Wait 10ms for packet drain in both tx and rx dma */
2491         usleep_range(10000, 20000);
2492
2493         /* Disable RDMA */
2494         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2495         reg &= ~DMA_EN;
2496         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2497
2498         timeout = 0;
2499         /* Check RDMA status register to confirm RDMA is disabled */
2500         while (timeout++ < DMA_TIMEOUT_VAL) {
2501                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2502                 if (reg & DMA_DISABLED)
2503                         break;
2504
2505                 udelay(1);
2506         }
2507
2508         if (timeout == DMA_TIMEOUT_VAL) {
2509                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2510                 ret = -ETIMEDOUT;
2511         }
2512
2513         dma_ctrl = 0;
2514         for (i = 0; i < priv->hw_params->rx_queues; i++)
2515                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2516         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2517         reg &= ~dma_ctrl;
2518         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2519
2520         dma_ctrl = 0;
2521         for (i = 0; i < priv->hw_params->tx_queues; i++)
2522                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2523         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2524         reg &= ~dma_ctrl;
2525         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2526
2527         return ret;
2528 }
2529
2530 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2531 {
2532         struct netdev_queue *txq;
2533         struct sk_buff *skb;
2534         struct enet_cb *cb;
2535         int i;
2536
2537         bcmgenet_fini_rx_napi(priv);
2538         bcmgenet_fini_tx_napi(priv);
2539
2540         for (i = 0; i < priv->num_tx_bds; i++) {
2541                 cb = priv->tx_cbs + i;
2542                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2543                 if (skb)
2544                         dev_kfree_skb(skb);
2545         }
2546
2547         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2548                 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2549                 netdev_tx_reset_queue(txq);
2550         }
2551
2552         txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2553         netdev_tx_reset_queue(txq);
2554
2555         bcmgenet_free_rx_buffers(priv);
2556         kfree(priv->rx_cbs);
2557         kfree(priv->tx_cbs);
2558 }
2559
2560 /* init_edma: Initialize DMA control register */
2561 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2562 {
2563         int ret;
2564         unsigned int i;
2565         struct enet_cb *cb;
2566
2567         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2568
2569         /* Initialize common Rx ring structures */
2570         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2571         priv->num_rx_bds = TOTAL_DESC;
2572         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2573                                GFP_KERNEL);
2574         if (!priv->rx_cbs)
2575                 return -ENOMEM;
2576
2577         for (i = 0; i < priv->num_rx_bds; i++) {
2578                 cb = priv->rx_cbs + i;
2579                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2580         }
2581
2582         /* Initialize common TX ring structures */
2583         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2584         priv->num_tx_bds = TOTAL_DESC;
2585         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2586                                GFP_KERNEL);
2587         if (!priv->tx_cbs) {
2588                 kfree(priv->rx_cbs);
2589                 return -ENOMEM;
2590         }
2591
2592         for (i = 0; i < priv->num_tx_bds; i++) {
2593                 cb = priv->tx_cbs + i;
2594                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2595         }
2596
2597         /* Init rDma */
2598         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2599
2600         /* Initialize Rx queues */
2601         ret = bcmgenet_init_rx_queues(priv->dev);
2602         if (ret) {
2603                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2604                 bcmgenet_free_rx_buffers(priv);
2605                 kfree(priv->rx_cbs);
2606                 kfree(priv->tx_cbs);
2607                 return ret;
2608         }
2609
2610         /* Init tDma */
2611         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2612
2613         /* Initialize Tx queues */
2614         bcmgenet_init_tx_queues(priv->dev);
2615
2616         return 0;
2617 }
2618
2619 /* Interrupt bottom half */
2620 static void bcmgenet_irq_task(struct work_struct *work)
2621 {
2622         unsigned int status;
2623         struct bcmgenet_priv *priv = container_of(
2624                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2625
2626         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2627
2628         spin_lock_irq(&priv->lock);
2629         status = priv->irq0_stat;
2630         priv->irq0_stat = 0;
2631         spin_unlock_irq(&priv->lock);
2632
2633         if (status & UMAC_IRQ_PHY_DET_R &&
2634             priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2635                 phy_init_hw(priv->dev->phydev);
2636                 genphy_config_aneg(priv->dev->phydev);
2637         }
2638
2639         /* Link UP/DOWN event */
2640         if (status & UMAC_IRQ_LINK_EVENT)
2641                 phy_mac_interrupt(priv->dev->phydev);
2642
2643 }
2644
2645 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2646 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2647 {
2648         struct bcmgenet_priv *priv = dev_id;
2649         struct bcmgenet_rx_ring *rx_ring;
2650         struct bcmgenet_tx_ring *tx_ring;
2651         unsigned int index, status;
2652
2653         /* Read irq status */
2654         status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2655                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2656
2657         /* clear interrupts */
2658         bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2659
2660         netif_dbg(priv, intr, priv->dev,
2661                   "%s: IRQ=0x%x\n", __func__, status);
2662
2663         /* Check Rx priority queue interrupts */
2664         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2665                 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2666                         continue;
2667
2668                 rx_ring = &priv->rx_rings[index];
2669                 rx_ring->dim.event_ctr++;
2670
2671                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2672                         rx_ring->int_disable(rx_ring);
2673                         __napi_schedule_irqoff(&rx_ring->napi);
2674                 }
2675         }
2676
2677         /* Check Tx priority queue interrupts */
2678         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2679                 if (!(status & BIT(index)))
2680                         continue;
2681
2682                 tx_ring = &priv->tx_rings[index];
2683
2684                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2685                         tx_ring->int_disable(tx_ring);
2686                         __napi_schedule_irqoff(&tx_ring->napi);
2687                 }
2688         }
2689
2690         return IRQ_HANDLED;
2691 }
2692
2693 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2694 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2695 {
2696         struct bcmgenet_priv *priv = dev_id;
2697         struct bcmgenet_rx_ring *rx_ring;
2698         struct bcmgenet_tx_ring *tx_ring;
2699         unsigned int status;
2700         unsigned long flags;
2701
2702         /* Read irq status */
2703         status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2704                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2705
2706         /* clear interrupts */
2707         bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2708
2709         netif_dbg(priv, intr, priv->dev,
2710                   "IRQ=0x%x\n", status);
2711
2712         if (status & UMAC_IRQ_RXDMA_DONE) {
2713                 rx_ring = &priv->rx_rings[DESC_INDEX];
2714                 rx_ring->dim.event_ctr++;
2715
2716                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2717                         rx_ring->int_disable(rx_ring);
2718                         __napi_schedule_irqoff(&rx_ring->napi);
2719                 }
2720         }
2721
2722         if (status & UMAC_IRQ_TXDMA_DONE) {
2723                 tx_ring = &priv->tx_rings[DESC_INDEX];
2724
2725                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2726                         tx_ring->int_disable(tx_ring);
2727                         __napi_schedule_irqoff(&tx_ring->napi);
2728                 }
2729         }
2730
2731         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2732                 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2733                 wake_up(&priv->wq);
2734         }
2735
2736         /* all other interested interrupts handled in bottom half */
2737         status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
2738         if (status) {
2739                 /* Save irq status for bottom-half processing. */
2740                 spin_lock_irqsave(&priv->lock, flags);
2741                 priv->irq0_stat |= status;
2742                 spin_unlock_irqrestore(&priv->lock, flags);
2743
2744                 schedule_work(&priv->bcmgenet_irq_work);
2745         }
2746
2747         return IRQ_HANDLED;
2748 }
2749
2750 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2751 {
2752         struct bcmgenet_priv *priv = dev_id;
2753
2754         pm_wakeup_event(&priv->pdev->dev, 0);
2755
2756         return IRQ_HANDLED;
2757 }
2758
2759 #ifdef CONFIG_NET_POLL_CONTROLLER
2760 static void bcmgenet_poll_controller(struct net_device *dev)
2761 {
2762         struct bcmgenet_priv *priv = netdev_priv(dev);
2763
2764         /* Invoke the main RX/TX interrupt handler */
2765         disable_irq(priv->irq0);
2766         bcmgenet_isr0(priv->irq0, priv);
2767         enable_irq(priv->irq0);
2768
2769         /* And the interrupt handler for RX/TX priority queues */
2770         disable_irq(priv->irq1);
2771         bcmgenet_isr1(priv->irq1, priv);
2772         enable_irq(priv->irq1);
2773 }
2774 #endif
2775
2776 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2777 {
2778         u32 reg;
2779
2780         reg = bcmgenet_rbuf_ctrl_get(priv);
2781         reg |= BIT(1);
2782         bcmgenet_rbuf_ctrl_set(priv, reg);
2783         udelay(10);
2784
2785         reg &= ~BIT(1);
2786         bcmgenet_rbuf_ctrl_set(priv, reg);
2787         udelay(10);
2788 }
2789
2790 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2791                                  unsigned char *addr)
2792 {
2793         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2794                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2795         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2796 }
2797
2798 /* Returns a reusable dma control register value */
2799 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2800 {
2801         unsigned int i;
2802         u32 reg;
2803         u32 dma_ctrl;
2804
2805         /* disable DMA */
2806         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2807         for (i = 0; i < priv->hw_params->tx_queues; i++)
2808                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2809         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2810         reg &= ~dma_ctrl;
2811         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2812
2813         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2814         for (i = 0; i < priv->hw_params->rx_queues; i++)
2815                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2816         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2817         reg &= ~dma_ctrl;
2818         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2819
2820         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2821         udelay(10);
2822         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2823
2824         return dma_ctrl;
2825 }
2826
2827 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2828 {
2829         u32 reg;
2830
2831         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2832         reg |= dma_ctrl;
2833         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2834
2835         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2836         reg |= dma_ctrl;
2837         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2838 }
2839
2840 /* bcmgenet_hfb_clear
2841  *
2842  * Clear Hardware Filter Block and disable all filtering.
2843  */
2844 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2845 {
2846         u32 i;
2847
2848         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2849         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2850         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2851
2852         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2853                 bcmgenet_rdma_writel(priv, 0x0, i);
2854
2855         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2856                 bcmgenet_hfb_reg_writel(priv, 0x0,
2857                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2858
2859         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2860                         priv->hw_params->hfb_filter_size; i++)
2861                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2862 }
2863
2864 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2865 {
2866         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2867                 return;
2868
2869         bcmgenet_hfb_clear(priv);
2870 }
2871
2872 static void bcmgenet_netif_start(struct net_device *dev)
2873 {
2874         struct bcmgenet_priv *priv = netdev_priv(dev);
2875
2876         /* Start the network engine */
2877         bcmgenet_set_rx_mode(dev);
2878         bcmgenet_enable_rx_napi(priv);
2879
2880         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2881
2882         bcmgenet_enable_tx_napi(priv);
2883
2884         /* Monitor link interrupts now */
2885         bcmgenet_link_intr_enable(priv);
2886
2887         phy_start(dev->phydev);
2888 }
2889
2890 static int bcmgenet_open(struct net_device *dev)
2891 {
2892         struct bcmgenet_priv *priv = netdev_priv(dev);
2893         unsigned long dma_ctrl;
2894         u32 reg;
2895         int ret;
2896
2897         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2898
2899         /* Turn on the clock */
2900         clk_prepare_enable(priv->clk);
2901
2902         /* If this is an internal GPHY, power it back on now, before UniMAC is
2903          * brought out of reset as absolutely no UniMAC activity is allowed
2904          */
2905         if (priv->internal_phy)
2906                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2907
2908         /* take MAC out of reset */
2909         bcmgenet_umac_reset(priv);
2910
2911         init_umac(priv);
2912
2913         /* Make sure we reflect the value of CRC_CMD_FWD */
2914         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2915         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2916
2917         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2918
2919         /* Disable RX/TX DMA and flush TX queues */
2920         dma_ctrl = bcmgenet_dma_disable(priv);
2921
2922         /* Reinitialize TDMA and RDMA and SW housekeeping */
2923         ret = bcmgenet_init_dma(priv);
2924         if (ret) {
2925                 netdev_err(dev, "failed to initialize DMA\n");
2926                 goto err_clk_disable;
2927         }
2928
2929         /* Always enable ring 16 - descriptor ring */
2930         bcmgenet_enable_dma(priv, dma_ctrl);
2931
2932         /* HFB init */
2933         bcmgenet_hfb_init(priv);
2934
2935         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2936                           dev->name, priv);
2937         if (ret < 0) {
2938                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2939                 goto err_fini_dma;
2940         }
2941
2942         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2943                           dev->name, priv);
2944         if (ret < 0) {
2945                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2946                 goto err_irq0;
2947         }
2948
2949         ret = bcmgenet_mii_probe(dev);
2950         if (ret) {
2951                 netdev_err(dev, "failed to connect to PHY\n");
2952                 goto err_irq1;
2953         }
2954
2955         bcmgenet_netif_start(dev);
2956
2957         netif_tx_start_all_queues(dev);
2958
2959         return 0;
2960
2961 err_irq1:
2962         free_irq(priv->irq1, priv);
2963 err_irq0:
2964         free_irq(priv->irq0, priv);
2965 err_fini_dma:
2966         bcmgenet_dma_teardown(priv);
2967         bcmgenet_fini_dma(priv);
2968 err_clk_disable:
2969         if (priv->internal_phy)
2970                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2971         clk_disable_unprepare(priv->clk);
2972         return ret;
2973 }
2974
2975 static void bcmgenet_netif_stop(struct net_device *dev)
2976 {
2977         struct bcmgenet_priv *priv = netdev_priv(dev);
2978
2979         bcmgenet_disable_tx_napi(priv);
2980         netif_tx_disable(dev);
2981
2982         /* Disable MAC receive */
2983         umac_enable_set(priv, CMD_RX_EN, false);
2984
2985         bcmgenet_dma_teardown(priv);
2986
2987         /* Disable MAC transmit. TX DMA disabled must be done before this */
2988         umac_enable_set(priv, CMD_TX_EN, false);
2989
2990         phy_stop(dev->phydev);
2991         bcmgenet_disable_rx_napi(priv);
2992         bcmgenet_intr_disable(priv);
2993
2994         /* Wait for pending work items to complete. Since interrupts are
2995          * disabled no new work will be scheduled.
2996          */
2997         cancel_work_sync(&priv->bcmgenet_irq_work);
2998
2999         priv->old_link = -1;
3000         priv->old_speed = -1;
3001         priv->old_duplex = -1;
3002         priv->old_pause = -1;
3003
3004         /* tx reclaim */
3005         bcmgenet_tx_reclaim_all(dev);
3006         bcmgenet_fini_dma(priv);
3007 }
3008
3009 static int bcmgenet_close(struct net_device *dev)
3010 {
3011         struct bcmgenet_priv *priv = netdev_priv(dev);
3012         int ret = 0;
3013
3014         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3015
3016         bcmgenet_netif_stop(dev);
3017
3018         /* Really kill the PHY state machine and disconnect from it */
3019         phy_disconnect(dev->phydev);
3020
3021         free_irq(priv->irq0, priv);
3022         free_irq(priv->irq1, priv);
3023
3024         if (priv->internal_phy)
3025                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3026
3027         clk_disable_unprepare(priv->clk);
3028
3029         return ret;
3030 }
3031
3032 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3033 {
3034         struct bcmgenet_priv *priv = ring->priv;
3035         u32 p_index, c_index, intsts, intmsk;
3036         struct netdev_queue *txq;
3037         unsigned int free_bds;
3038         bool txq_stopped;
3039
3040         if (!netif_msg_tx_err(priv))
3041                 return;
3042
3043         txq = netdev_get_tx_queue(priv->dev, ring->queue);
3044
3045         spin_lock(&ring->lock);
3046         if (ring->index == DESC_INDEX) {
3047                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3048                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3049         } else {
3050                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3051                 intmsk = 1 << ring->index;
3052         }
3053         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3054         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3055         txq_stopped = netif_tx_queue_stopped(txq);
3056         free_bds = ring->free_bds;
3057         spin_unlock(&ring->lock);
3058
3059         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3060                   "TX queue status: %s, interrupts: %s\n"
3061                   "(sw)free_bds: %d (sw)size: %d\n"
3062                   "(sw)p_index: %d (hw)p_index: %d\n"
3063                   "(sw)c_index: %d (hw)c_index: %d\n"
3064                   "(sw)clean_p: %d (sw)write_p: %d\n"
3065                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3066                   ring->index, ring->queue,
3067                   txq_stopped ? "stopped" : "active",
3068                   intsts & intmsk ? "enabled" : "disabled",
3069                   free_bds, ring->size,
3070                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
3071                   ring->c_index, c_index & DMA_C_INDEX_MASK,
3072                   ring->clean_ptr, ring->write_ptr,
3073                   ring->cb_ptr, ring->end_ptr);
3074 }
3075
3076 static void bcmgenet_timeout(struct net_device *dev)
3077 {
3078         struct bcmgenet_priv *priv = netdev_priv(dev);
3079         u32 int0_enable = 0;
3080         u32 int1_enable = 0;
3081         unsigned int q;
3082
3083         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3084
3085         for (q = 0; q < priv->hw_params->tx_queues; q++)
3086                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3087         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3088
3089         bcmgenet_tx_reclaim_all(dev);
3090
3091         for (q = 0; q < priv->hw_params->tx_queues; q++)
3092                 int1_enable |= (1 << q);
3093
3094         int0_enable = UMAC_IRQ_TXDMA_DONE;
3095
3096         /* Re-enable TX interrupts if disabled */
3097         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3098         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3099
3100         netif_trans_update(dev);
3101
3102         dev->stats.tx_errors++;
3103
3104         netif_tx_wake_all_queues(dev);
3105 }
3106
3107 #define MAX_MDF_FILTER  17
3108
3109 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3110                                          unsigned char *addr,
3111                                          int *i)
3112 {
3113         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3114                              UMAC_MDF_ADDR + (*i * 4));
3115         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3116                              addr[4] << 8 | addr[5],
3117                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3118         *i += 2;
3119 }
3120
3121 static void bcmgenet_set_rx_mode(struct net_device *dev)
3122 {
3123         struct bcmgenet_priv *priv = netdev_priv(dev);
3124         struct netdev_hw_addr *ha;
3125         int i, nfilter;
3126         u32 reg;
3127
3128         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3129
3130         /* Number of filters needed */
3131         nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3132
3133         /*
3134          * Turn on promicuous mode for three scenarios
3135          * 1. IFF_PROMISC flag is set
3136          * 2. IFF_ALLMULTI flag is set
3137          * 3. The number of filters needed exceeds the number filters
3138          *    supported by the hardware.
3139         */
3140         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3141         if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3142             (nfilter > MAX_MDF_FILTER)) {
3143                 reg |= CMD_PROMISC;
3144                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3145                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3146                 return;
3147         } else {
3148                 reg &= ~CMD_PROMISC;
3149                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3150         }
3151
3152         /* update MDF filter */
3153         i = 0;
3154         /* Broadcast */
3155         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3156         /* my own address.*/
3157         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3158
3159         /* Unicast */
3160         netdev_for_each_uc_addr(ha, dev)
3161                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3162
3163         /* Multicast */
3164         netdev_for_each_mc_addr(ha, dev)
3165                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3166
3167         /* Enable filters */
3168         reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3169         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3170 }
3171
3172 /* Set the hardware MAC address. */
3173 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3174 {
3175         struct sockaddr *addr = p;
3176
3177         /* Setting the MAC address at the hardware level is not possible
3178          * without disabling the UniMAC RX/TX enable bits.
3179          */
3180         if (netif_running(dev))
3181                 return -EBUSY;
3182
3183         ether_addr_copy(dev->dev_addr, addr->sa_data);
3184
3185         return 0;
3186 }
3187
3188 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3189 {
3190         struct bcmgenet_priv *priv = netdev_priv(dev);
3191         unsigned long tx_bytes = 0, tx_packets = 0;
3192         unsigned long rx_bytes = 0, rx_packets = 0;
3193         unsigned long rx_errors = 0, rx_dropped = 0;
3194         struct bcmgenet_tx_ring *tx_ring;
3195         struct bcmgenet_rx_ring *rx_ring;
3196         unsigned int q;
3197
3198         for (q = 0; q < priv->hw_params->tx_queues; q++) {
3199                 tx_ring = &priv->tx_rings[q];
3200                 tx_bytes += tx_ring->bytes;
3201                 tx_packets += tx_ring->packets;
3202         }
3203         tx_ring = &priv->tx_rings[DESC_INDEX];
3204         tx_bytes += tx_ring->bytes;
3205         tx_packets += tx_ring->packets;
3206
3207         for (q = 0; q < priv->hw_params->rx_queues; q++) {
3208                 rx_ring = &priv->rx_rings[q];
3209
3210                 rx_bytes += rx_ring->bytes;
3211                 rx_packets += rx_ring->packets;
3212                 rx_errors += rx_ring->errors;
3213                 rx_dropped += rx_ring->dropped;
3214         }
3215         rx_ring = &priv->rx_rings[DESC_INDEX];
3216         rx_bytes += rx_ring->bytes;
3217         rx_packets += rx_ring->packets;
3218         rx_errors += rx_ring->errors;
3219         rx_dropped += rx_ring->dropped;
3220
3221         dev->stats.tx_bytes = tx_bytes;
3222         dev->stats.tx_packets = tx_packets;
3223         dev->stats.rx_bytes = rx_bytes;
3224         dev->stats.rx_packets = rx_packets;
3225         dev->stats.rx_errors = rx_errors;
3226         dev->stats.rx_missed_errors = rx_errors;
3227         dev->stats.rx_dropped = rx_dropped;
3228         return &dev->stats;
3229 }
3230
3231 static const struct net_device_ops bcmgenet_netdev_ops = {
3232         .ndo_open               = bcmgenet_open,
3233         .ndo_stop               = bcmgenet_close,
3234         .ndo_start_xmit         = bcmgenet_xmit,
3235         .ndo_tx_timeout         = bcmgenet_timeout,
3236         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3237         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3238         .ndo_do_ioctl           = bcmgenet_ioctl,
3239         .ndo_set_features       = bcmgenet_set_features,
3240 #ifdef CONFIG_NET_POLL_CONTROLLER
3241         .ndo_poll_controller    = bcmgenet_poll_controller,
3242 #endif
3243         .ndo_get_stats          = bcmgenet_get_stats,
3244 };
3245
3246 /* Array of GENET hardware parameters/characteristics */
3247 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3248         [GENET_V1] = {
3249                 .tx_queues = 0,
3250                 .tx_bds_per_q = 0,
3251                 .rx_queues = 0,
3252                 .rx_bds_per_q = 0,
3253                 .bp_in_en_shift = 16,
3254                 .bp_in_mask = 0xffff,
3255                 .hfb_filter_cnt = 16,
3256                 .qtag_mask = 0x1F,
3257                 .hfb_offset = 0x1000,
3258                 .rdma_offset = 0x2000,
3259                 .tdma_offset = 0x3000,
3260                 .words_per_bd = 2,
3261         },
3262         [GENET_V2] = {
3263                 .tx_queues = 4,
3264                 .tx_bds_per_q = 32,
3265                 .rx_queues = 0,
3266                 .rx_bds_per_q = 0,
3267                 .bp_in_en_shift = 16,
3268                 .bp_in_mask = 0xffff,
3269                 .hfb_filter_cnt = 16,
3270                 .qtag_mask = 0x1F,
3271                 .tbuf_offset = 0x0600,
3272                 .hfb_offset = 0x1000,
3273                 .hfb_reg_offset = 0x2000,
3274                 .rdma_offset = 0x3000,
3275                 .tdma_offset = 0x4000,
3276                 .words_per_bd = 2,
3277                 .flags = GENET_HAS_EXT,
3278         },
3279         [GENET_V3] = {
3280                 .tx_queues = 4,
3281                 .tx_bds_per_q = 32,
3282                 .rx_queues = 0,
3283                 .rx_bds_per_q = 0,
3284                 .bp_in_en_shift = 17,
3285                 .bp_in_mask = 0x1ffff,
3286                 .hfb_filter_cnt = 48,
3287                 .hfb_filter_size = 128,
3288                 .qtag_mask = 0x3F,
3289                 .tbuf_offset = 0x0600,
3290                 .hfb_offset = 0x8000,
3291                 .hfb_reg_offset = 0xfc00,
3292                 .rdma_offset = 0x10000,
3293                 .tdma_offset = 0x11000,
3294                 .words_per_bd = 2,
3295                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3296                          GENET_HAS_MOCA_LINK_DET,
3297         },
3298         [GENET_V4] = {
3299                 .tx_queues = 4,
3300                 .tx_bds_per_q = 32,
3301                 .rx_queues = 0,
3302                 .rx_bds_per_q = 0,
3303                 .bp_in_en_shift = 17,
3304                 .bp_in_mask = 0x1ffff,
3305                 .hfb_filter_cnt = 48,
3306                 .hfb_filter_size = 128,
3307                 .qtag_mask = 0x3F,
3308                 .tbuf_offset = 0x0600,
3309                 .hfb_offset = 0x8000,
3310                 .hfb_reg_offset = 0xfc00,
3311                 .rdma_offset = 0x2000,
3312                 .tdma_offset = 0x4000,
3313                 .words_per_bd = 3,
3314                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3315                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3316         },
3317         [GENET_V5] = {
3318                 .tx_queues = 4,
3319                 .tx_bds_per_q = 32,
3320                 .rx_queues = 0,
3321                 .rx_bds_per_q = 0,
3322                 .bp_in_en_shift = 17,
3323                 .bp_in_mask = 0x1ffff,
3324                 .hfb_filter_cnt = 48,
3325                 .hfb_filter_size = 128,
3326                 .qtag_mask = 0x3F,
3327                 .tbuf_offset = 0x0600,
3328                 .hfb_offset = 0x8000,
3329                 .hfb_reg_offset = 0xfc00,
3330                 .rdma_offset = 0x2000,
3331                 .tdma_offset = 0x4000,
3332                 .words_per_bd = 3,
3333                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3334                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3335         },
3336 };
3337
3338 /* Infer hardware parameters from the detected GENET version */
3339 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3340 {
3341         struct bcmgenet_hw_params *params;
3342         u32 reg;
3343         u8 major;
3344         u16 gphy_rev;
3345
3346         if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3347                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3348                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3349                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3350         } else if (GENET_IS_V3(priv)) {
3351                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3352                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3353                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3354         } else if (GENET_IS_V2(priv)) {
3355                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3356                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3357                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3358         } else if (GENET_IS_V1(priv)) {
3359                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3360                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3361                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3362         }
3363
3364         /* enum genet_version starts at 1 */
3365         priv->hw_params = &bcmgenet_hw_params[priv->version];
3366         params = priv->hw_params;
3367
3368         /* Read GENET HW version */
3369         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3370         major = (reg >> 24 & 0x0f);
3371         if (major == 6)
3372                 major = 5;
3373         else if (major == 5)
3374                 major = 4;
3375         else if (major == 0)
3376                 major = 1;
3377         if (major != priv->version) {
3378                 dev_err(&priv->pdev->dev,
3379                         "GENET version mismatch, got: %d, configured for: %d\n",
3380                         major, priv->version);
3381         }
3382
3383         /* Print the GENET core version */
3384         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3385                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3386
3387         /* Store the integrated PHY revision for the MDIO probing function
3388          * to pass this information to the PHY driver. The PHY driver expects
3389          * to find the PHY major revision in bits 15:8 while the GENET register
3390          * stores that information in bits 7:0, account for that.
3391          *
3392          * On newer chips, starting with PHY revision G0, a new scheme is
3393          * deployed similar to the Starfighter 2 switch with GPHY major
3394          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3395          * is reserved as well as special value 0x01ff, we have a small
3396          * heuristic to check for the new GPHY revision and re-arrange things
3397          * so the GPHY driver is happy.
3398          */
3399         gphy_rev = reg & 0xffff;
3400
3401         if (GENET_IS_V5(priv)) {
3402                 /* The EPHY revision should come from the MDIO registers of
3403                  * the PHY not from GENET.
3404                  */
3405                 if (gphy_rev != 0) {
3406                         pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3407                                 gphy_rev);
3408                 }
3409         /* This is reserved so should require special treatment */
3410         } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3411                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3412                 return;
3413         /* This is the good old scheme, just GPHY major, no minor nor patch */
3414         } else if ((gphy_rev & 0xf0) != 0) {
3415                 priv->gphy_rev = gphy_rev << 8;
3416         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3417         } else if ((gphy_rev & 0xff00) != 0) {
3418                 priv->gphy_rev = gphy_rev;
3419         }
3420
3421 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3422         if (!(params->flags & GENET_HAS_40BITS))
3423                 pr_warn("GENET does not support 40-bits PA\n");
3424 #endif
3425
3426         pr_debug("Configuration for version: %d\n"
3427                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3428                 "BP << en: %2d, BP msk: 0x%05x\n"
3429                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3430                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3431                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3432                 "Words/BD: %d\n",
3433                 priv->version,
3434                 params->tx_queues, params->tx_bds_per_q,
3435                 params->rx_queues, params->rx_bds_per_q,
3436                 params->bp_in_en_shift, params->bp_in_mask,
3437                 params->hfb_filter_cnt, params->qtag_mask,
3438                 params->tbuf_offset, params->hfb_offset,
3439                 params->hfb_reg_offset,
3440                 params->rdma_offset, params->tdma_offset,
3441                 params->words_per_bd);
3442 }
3443
3444 static const struct of_device_id bcmgenet_match[] = {
3445         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3446         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3447         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3448         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3449         { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3450         { },
3451 };
3452 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3453
3454 static int bcmgenet_probe(struct platform_device *pdev)
3455 {
3456         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3457         struct device_node *dn = pdev->dev.of_node;
3458         const struct of_device_id *of_id = NULL;
3459         struct bcmgenet_priv *priv;
3460         struct net_device *dev;
3461         const void *macaddr;
3462         struct resource *r;
3463         unsigned int i;
3464         int err = -EIO;
3465         const char *phy_mode_str;
3466
3467         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3468         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3469                                  GENET_MAX_MQ_CNT + 1);
3470         if (!dev) {
3471                 dev_err(&pdev->dev, "can't allocate net device\n");
3472                 return -ENOMEM;
3473         }
3474
3475         if (dn) {
3476                 of_id = of_match_node(bcmgenet_match, dn);
3477                 if (!of_id)
3478                         return -EINVAL;
3479         }
3480
3481         priv = netdev_priv(dev);
3482         priv->irq0 = platform_get_irq(pdev, 0);
3483         priv->irq1 = platform_get_irq(pdev, 1);
3484         priv->wol_irq = platform_get_irq(pdev, 2);
3485         if (!priv->irq0 || !priv->irq1) {
3486                 dev_err(&pdev->dev, "can't find IRQs\n");
3487                 err = -EINVAL;
3488                 goto err;
3489         }
3490
3491         if (dn) {
3492                 macaddr = of_get_mac_address(dn);
3493                 if (!macaddr) {
3494                         dev_err(&pdev->dev, "can't find MAC address\n");
3495                         err = -EINVAL;
3496                         goto err;
3497                 }
3498         } else {
3499                 macaddr = pd->mac_address;
3500         }
3501
3502         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3503         priv->base = devm_ioremap_resource(&pdev->dev, r);
3504         if (IS_ERR(priv->base)) {
3505                 err = PTR_ERR(priv->base);
3506                 goto err;
3507         }
3508
3509         spin_lock_init(&priv->lock);
3510
3511         SET_NETDEV_DEV(dev, &pdev->dev);
3512         dev_set_drvdata(&pdev->dev, dev);
3513         ether_addr_copy(dev->dev_addr, macaddr);
3514         dev->watchdog_timeo = 2 * HZ;
3515         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3516         dev->netdev_ops = &bcmgenet_netdev_ops;
3517
3518         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3519
3520         /* Set hardware features */
3521         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3522                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3523
3524         /* Request the WOL interrupt and advertise suspend if available */
3525         priv->wol_irq_disabled = true;
3526         if (priv->wol_irq > 0) {
3527                 err = devm_request_irq(&pdev->dev, priv->wol_irq,
3528                                        bcmgenet_wol_isr, 0, dev->name, priv);
3529                 if (!err)
3530                         device_set_wakeup_capable(&pdev->dev, 1);
3531         }
3532
3533         /* Set the needed headroom to account for any possible
3534          * features enabling/disabling at runtime
3535          */
3536         dev->needed_headroom += 64;
3537
3538         netdev_boot_setup_check(dev);
3539
3540         priv->dev = dev;
3541         priv->pdev = pdev;
3542         if (of_id)
3543                 priv->version = (enum bcmgenet_version)of_id->data;
3544         else
3545                 priv->version = pd->genet_version;
3546
3547         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3548         if (IS_ERR(priv->clk)) {
3549                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3550                 priv->clk = NULL;
3551         }
3552
3553         clk_prepare_enable(priv->clk);
3554
3555         bcmgenet_set_hw_params(priv);
3556
3557         /* Mii wait queue */
3558         init_waitqueue_head(&priv->wq);
3559         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3560         priv->rx_buf_len = RX_BUF_LENGTH;
3561         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3562
3563         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3564         if (IS_ERR(priv->clk_wol)) {
3565                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3566                 priv->clk_wol = NULL;
3567         }
3568
3569         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3570         if (IS_ERR(priv->clk_eee)) {
3571                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3572                 priv->clk_eee = NULL;
3573         }
3574
3575         /* If this is an internal GPHY, power it on now, before UniMAC is
3576          * brought out of reset as absolutely no UniMAC activity is allowed
3577          */
3578         if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3579             !strcasecmp(phy_mode_str, "internal"))
3580                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3581
3582         reset_umac(priv);
3583
3584         err = bcmgenet_mii_init(dev);
3585         if (err)
3586                 goto err_clk_disable;
3587
3588         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3589          * just the ring 16 descriptor based TX
3590          */
3591         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3592         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3593
3594         /* Set default coalescing parameters */
3595         for (i = 0; i < priv->hw_params->rx_queues; i++)
3596                 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3597         priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3598
3599         /* libphy will determine the link state */
3600         netif_carrier_off(dev);
3601
3602         /* Turn off the main clock, WOL clock is handled separately */
3603         clk_disable_unprepare(priv->clk);
3604
3605         err = register_netdev(dev);
3606         if (err) {
3607                 bcmgenet_mii_exit(dev);
3608                 goto err;
3609         }
3610
3611         return err;
3612
3613 err_clk_disable:
3614         clk_disable_unprepare(priv->clk);
3615 err:
3616         free_netdev(dev);
3617         return err;
3618 }
3619
3620 static int bcmgenet_remove(struct platform_device *pdev)
3621 {
3622         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3623
3624         dev_set_drvdata(&pdev->dev, NULL);
3625         unregister_netdev(priv->dev);
3626         bcmgenet_mii_exit(priv->dev);
3627         free_netdev(priv->dev);
3628
3629         return 0;
3630 }
3631
3632 #ifdef CONFIG_PM_SLEEP
3633 static int bcmgenet_resume(struct device *d)
3634 {
3635         struct net_device *dev = dev_get_drvdata(d);
3636         struct bcmgenet_priv *priv = netdev_priv(dev);
3637         unsigned long dma_ctrl;
3638         int ret;
3639
3640         if (!netif_running(dev))
3641                 return 0;
3642
3643         /* Turn on the clock */
3644         ret = clk_prepare_enable(priv->clk);
3645         if (ret)
3646                 return ret;
3647
3648         /* If this is an internal GPHY, power it back on now, before UniMAC is
3649          * brought out of reset as absolutely no UniMAC activity is allowed
3650          */
3651         if (priv->internal_phy)
3652                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3653
3654         bcmgenet_umac_reset(priv);
3655
3656         init_umac(priv);
3657
3658         /* From WOL-enabled suspend, switch to regular clock */
3659         if (priv->wolopts)
3660                 clk_disable_unprepare(priv->clk_wol);
3661
3662         phy_init_hw(dev->phydev);
3663
3664         /* Speed settings must be restored */
3665         genphy_config_aneg(dev->phydev);
3666         bcmgenet_mii_config(priv->dev, false);
3667
3668         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3669
3670         if (priv->wolopts)
3671                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3672
3673         /* Disable RX/TX DMA and flush TX queues */
3674         dma_ctrl = bcmgenet_dma_disable(priv);
3675
3676         /* Reinitialize TDMA and RDMA and SW housekeeping */
3677         ret = bcmgenet_init_dma(priv);
3678         if (ret) {
3679                 netdev_err(dev, "failed to initialize DMA\n");
3680                 goto out_clk_disable;
3681         }
3682
3683         /* Always enable ring 16 - descriptor ring */
3684         bcmgenet_enable_dma(priv, dma_ctrl);
3685
3686         if (!device_may_wakeup(d))
3687                 phy_resume(dev->phydev);
3688
3689         if (priv->eee.eee_enabled)
3690                 bcmgenet_eee_enable_set(dev, true);
3691
3692         bcmgenet_netif_start(dev);
3693
3694         netif_device_attach(dev);
3695
3696         return 0;
3697
3698 out_clk_disable:
3699         if (priv->internal_phy)
3700                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3701         clk_disable_unprepare(priv->clk);
3702         return ret;
3703 }
3704
3705 static int bcmgenet_suspend(struct device *d)
3706 {
3707         struct net_device *dev = dev_get_drvdata(d);
3708         struct bcmgenet_priv *priv = netdev_priv(dev);
3709         int ret = 0;
3710
3711         if (!netif_running(dev))
3712                 return 0;
3713
3714         netif_device_detach(dev);
3715
3716         bcmgenet_netif_stop(dev);
3717
3718         if (!device_may_wakeup(d))
3719                 phy_suspend(dev->phydev);
3720
3721         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3722         if (device_may_wakeup(d) && priv->wolopts) {
3723                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3724                 clk_prepare_enable(priv->clk_wol);
3725         } else if (priv->internal_phy) {
3726                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3727         }
3728
3729         /* Turn off the clocks */
3730         clk_disable_unprepare(priv->clk);
3731
3732         if (ret)
3733                 bcmgenet_resume(d);
3734
3735         return ret;
3736 }
3737 #endif /* CONFIG_PM_SLEEP */
3738
3739 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3740
3741 static struct platform_driver bcmgenet_driver = {
3742         .probe  = bcmgenet_probe,
3743         .remove = bcmgenet_remove,
3744         .driver = {
3745                 .name   = "bcmgenet",
3746                 .of_match_table = bcmgenet_match,
3747                 .pm     = &bcmgenet_pm_ops,
3748         },
3749 };
3750 module_platform_driver(bcmgenet_driver);
3751
3752 MODULE_AUTHOR("Broadcom Corporation");
3753 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3754 MODULE_ALIAS("platform:bcmgenet");
3755 MODULE_LICENSE("GPL");
3756 MODULE_SOFTDEP("pre: mdio-bcm-unimac");