drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <linux/platform_data/bcmgenet.h>
  27 #include <linux/platform_data/mdio-bcm-unimac.h>
  28
  29 #include "bcmgenet.h"
  30
  31 /* setup netdev link state when PHY link status change and
  32  * update UMAC and RGMII block when link up
  33  */
  34 void bcmgenet_mii_setup(struct net_device *dev)
  35 {
  36         struct bcmgenet_priv *priv = netdev_priv(dev);
  37         struct phy_device *phydev = priv->phydev;
  38         u32 reg, cmd_bits = 0;
  39         bool status_changed = false;
  40
  41         if (priv->old_link != phydev->link) {
  42                 status_changed = true;
  43                 priv->old_link = phydev->link;
  44         }
  45
  46         if (phydev->link) {
  47                 /* check speed/duplex/pause changes */
  48                 if (priv->old_speed != phydev->speed) {
  49                         status_changed = true;
  50                         priv->old_speed = phydev->speed;
  51                 }
  52
  53                 if (priv->old_duplex != phydev->duplex) {
  54                         status_changed = true;
  55                         priv->old_duplex = phydev->duplex;
  56                 }
  57
  58                 if (priv->old_pause != phydev->pause) {
  59                         status_changed = true;
  60                         priv->old_pause = phydev->pause;
  61                 }
  62
  63                 /* done if nothing has changed */
  64                 if (!status_changed)
  65                         return;
  66
  67                 /* speed */
  68                 if (phydev->speed == SPEED_1000)
  69                         cmd_bits = UMAC_SPEED_1000;
  70                 else if (phydev->speed == SPEED_100)
  71                         cmd_bits = UMAC_SPEED_100;
  72                 else
  73                         cmd_bits = UMAC_SPEED_10;
  74                 cmd_bits <<= CMD_SPEED_SHIFT;
  75
  76                 /* duplex */
  77                 if (phydev->duplex != DUPLEX_FULL)
  78                         cmd_bits |= CMD_HD_EN;
  79
  80                 /* pause capability */
  81                 if (!phydev->pause)
  82                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
  83
  84                 /*
  85                  * Program UMAC and RGMII block based on established
  86                  * link speed, duplex, and pause. The speed set in
  87                  * umac->cmd tell RGMII block which clock to use for
  88                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
  89                  * Receive clock is provided by the PHY.
  90                  */
  91                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
  92                 reg &= ~OOB_DISABLE;
  93                 reg |= RGMII_LINK;
  94                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
  95
  96                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
  97                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
  98                                CMD_HD_EN |
  99                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 100                 reg |= cmd_bits;
 101                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 102         } else {
 103                 /* done if nothing has changed */
 104                 if (!status_changed)
 105                         return;
 106
 107                 /* needed for MoCA fixed PHY to reflect correct link status */
 108                 netif_carrier_off(dev);
 109         }
 110
 111         phy_print_status(phydev);
 112 }
 113
 114
 115 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 116                                           struct fixed_phy_status *status)
 117 {
 118         struct bcmgenet_priv *priv;
 119         u32 reg;
 120
 121         if (dev && dev->phydev && status) {
 122                 priv = netdev_priv(dev);
 123                 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
 124                 status->link = !!(reg & MODE_LINK_STATUS);
 125         }
 126
 127         return 0;
 128 }
 129
 130 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about
 131  * not doing it and will start corrupting packets
 132  */
 133 void bcmgenet_mii_reset(struct net_device *dev)
 134 {
 135         struct bcmgenet_priv *priv = netdev_priv(dev);
 136
 137         if (GENET_IS_V4(priv))
 138                 return;
 139
 140         if (priv->phydev) {
 141                 phy_init_hw(priv->phydev);
 142                 phy_start_aneg(priv->phydev);
 143         }
 144 }
 145
 146 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 147 {
 148         struct bcmgenet_priv *priv = netdev_priv(dev);
 149         u32 reg = 0;
 150
 151         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 152         if (GENET_IS_V4(priv)) {
 153                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 154                 if (enable) {
 155                         reg &= ~EXT_CK25_DIS;
 156                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 157                         mdelay(1);
 158
 159                         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 160                         reg |= EXT_GPHY_RESET;
 161                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 162                         mdelay(1);
 163
 164                         reg &= ~EXT_GPHY_RESET;
 165                 } else {
 166                         reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
 167                                EXT_GPHY_RESET;
 168                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 169                         mdelay(1);
 170                         reg |= EXT_CK25_DIS;
 171                 }
 172                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 173                 udelay(60);
 174         } else {
 175                 mdelay(1);
 176         }
 177 }
 178
 179 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 180 {
 181         u32 reg;
 182
 183         if (!GENET_IS_V5(priv)) {
 184                 /* Speed settings are set in bcmgenet_mii_setup() */
 185                 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 186                 reg |= LED_ACT_SOURCE_MAC;
 187                 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 188         }
 189
 190         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 191                 fixed_phy_set_link_update(priv->phydev,
 192                                           bcmgenet_fixed_phy_link_update);
 193 }
 194
 195 int bcmgenet_mii_config(struct net_device *dev, bool init)
 196 {
 197         struct bcmgenet_priv *priv = netdev_priv(dev);
 198         struct phy_device *phydev = priv->phydev;
 199         struct device *kdev = &priv->pdev->dev;
 200         const char *phy_name = NULL;
 201         u32 id_mode_dis = 0;
 202         u32 port_ctrl;
 203         u32 reg;
 204
 205         priv->ext_phy = !priv->internal_phy &&
 206                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 207
 208         switch (priv->phy_interface) {
 209         case PHY_INTERFACE_MODE_INTERNAL:
 210         case PHY_INTERFACE_MODE_MOCA:
 211                 /* Irrespective of the actually configured PHY speed (100 or
 212                  * 1000) GENETv4 only has an internal GPHY so we will just end
 213                  * up masking the Gigabit features from what we support, not
 214                  * switching to the EPHY
 215                  */
 216                 if (GENET_IS_V4(priv))
 217                         port_ctrl = PORT_MODE_INT_GPHY;
 218                 else
 219                         port_ctrl = PORT_MODE_INT_EPHY;
 220
 221                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 222
 223                 if (priv->internal_phy) {
 224                         phy_name = "internal PHY";
 225                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 226                         phy_name = "MoCA";
 227                         bcmgenet_moca_phy_setup(priv);
 228                 }
 229                 break;
 230
 231         case PHY_INTERFACE_MODE_MII:
 232                 phy_name = "external MII";
 233                 phydev->supported &= PHY_BASIC_FEATURES;
 234                 bcmgenet_sys_writel(priv,
 235                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 236                 break;
 237
 238         case PHY_INTERFACE_MODE_REVMII:
 239                 phy_name = "external RvMII";
 240                 /* of_mdiobus_register took care of reading the 'max-speed'
 241                  * PHY property for us, effectively limiting the PHY supported
 242                  * capabilities, use that knowledge to also configure the
 243                  * Reverse MII interface correctly.
 244                  */
 245                 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
 246                                 PHY_BASIC_FEATURES)
 247                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 248                 else
 249                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 250                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 251                 break;
 252
 253         case PHY_INTERFACE_MODE_RGMII:
 254                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 255                  *              (requires PCB or receiver-side delay)
 256                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 257                  *
 258                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 259                  */
 260                 id_mode_dis = BIT(16);
 261                 /* fall through */
 262         case PHY_INTERFACE_MODE_RGMII_TXID:
 263                 if (id_mode_dis)
 264                         phy_name = "external RGMII (no delay)";
 265                 else
 266                         phy_name = "external RGMII (TX delay)";
 267                 bcmgenet_sys_writel(priv,
 268                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 269                 break;
 270         default:
 271                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 272                 return -EINVAL;
 273         }
 274
 275         /* This is an external PHY (xMII), so we need to enable the RGMII
 276          * block for the interface to work
 277          */
 278         if (priv->ext_phy) {
 279                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 280                 reg |= id_mode_dis;
 281                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
 282                         reg |= RGMII_MODE_EN_V123;
 283                 else
 284                         reg |= RGMII_MODE_EN;
 285                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 286         }
 287
 288         if (init)
 289                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 290
 291         return 0;
 292 }
 293
 294 int bcmgenet_mii_probe(struct net_device *dev)
 295 {
 296         struct bcmgenet_priv *priv = netdev_priv(dev);
 297         struct device_node *dn = priv->pdev->dev.of_node;
 298         struct phy_device *phydev;
 299         u32 phy_flags = 0;
 300         int ret;
 301
 302         /* Communicate the integrated PHY revision */
 303         if (priv->internal_phy)
 304                 phy_flags = priv->gphy_rev;
 305
 306         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 307         priv->old_link = -1;
 308         priv->old_speed = -1;
 309         priv->old_duplex = -1;
 310         priv->old_pause = -1;
 311
 312         if (dn) {
 313                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 314                                         phy_flags, priv->phy_interface);
 315                 if (!phydev) {
 316                         pr_err("could not attach to PHY\n");
 317                         return -ENODEV;
 318                 }
 319         } else {
 320                 phydev = priv->phydev;
 321                 phydev->dev_flags = phy_flags;
 322
 323                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 324                                          priv->phy_interface);
 325                 if (ret) {
 326                         pr_err("could not attach to PHY\n");
 327                         return -ENODEV;
 328                 }
 329         }
 330
 331         priv->phydev = phydev;
 332
 333         /* Configure port multiplexer based on what the probed PHY device since
 334          * reading the 'max-speed' property determines the maximum supported
 335          * PHY speed which is needed for bcmgenet_mii_config() to configure
 336          * things appropriately.
 337          */
 338         ret = bcmgenet_mii_config(dev, true);
 339         if (ret) {
 340                 phy_disconnect(priv->phydev);
 341                 return ret;
 342         }
 343
 344         phydev->advertising = phydev->supported;
 345
 346         /* The internal PHY has its link interrupts routed to the
 347          * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
 348          * that prevents the signaling of link UP interrupts when
 349          * the link operates at 10Mbps, so fallback to polling for
 350          * those versions of GENET.
 351          */
 352         if (priv->internal_phy && !GENET_IS_V5(priv))
 353                 priv->phydev->irq = PHY_IGNORE_INTERRUPT;
 354
 355         return 0;
 356 }
 357
 358 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
 359 {
 360         struct device_node *dn = priv->pdev->dev.of_node;
 361         struct device *kdev = &priv->pdev->dev;
 362         char *compat;
 363
 364         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 365         if (!compat)
 366                 return NULL;
 367
 368         priv->mdio_dn = of_get_compatible_child(dn, compat);
 369         kfree(compat);
 370         if (!priv->mdio_dn) {
 371                 dev_err(kdev, "unable to find MDIO bus node\n");
 372                 return NULL;
 373         }
 374
 375         return priv->mdio_dn;
 376 }
 377
 378 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
 379                                     struct unimac_mdio_pdata *ppd)
 380 {
 381         struct device *kdev = &priv->pdev->dev;
 382         struct bcmgenet_platform_data *pd = kdev->platform_data;
 383
 384         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 385                 /*
 386                  * Internal or external PHY with MDIO access
 387                  */
 388                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 389                         ppd->phy_mask = 1 << pd->phy_address;
 390                 else
 391                         ppd->phy_mask = 0;
 392         }
 393 }
 394
 395 static int bcmgenet_mii_wait(void *wait_func_data)
 396 {
 397         struct bcmgenet_priv *priv = wait_func_data;
 398
 399         wait_event_timeout(priv->wq,
 400                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
 401                            & MDIO_START_BUSY),
 402                            HZ / 100);
 403         return 0;
 404 }
 405
 406 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
 407 {
 408         struct platform_device *pdev = priv->pdev;
 409         struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
 410         struct device_node *dn = pdev->dev.of_node;
 411         struct unimac_mdio_pdata ppd;
 412         struct platform_device *ppdev;
 413         struct resource *pres, res;
 414         int id, ret;
 415
 416         pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 417         if (!pres) {
 418                 dev_err(&pdev->dev, "Invalid resource\n");
 419                 return -EINVAL;
 420         }
 421         memset(&res, 0, sizeof(res));
 422         memset(&ppd, 0, sizeof(ppd));
 423
 424         ppd.wait_func = bcmgenet_mii_wait;
 425         ppd.wait_func_data = priv;
 426         ppd.bus_name = "bcmgenet MII bus";
 427
 428         /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
 429          * and is 2 * 32-bits word long, 8 bytes total.
 430          */
 431         res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
 432         res.end = res.start + 8;
 433         res.flags = IORESOURCE_MEM;
 434
 435         if (dn)
 436                 id = of_alias_get_id(dn, "eth");
 437         else
 438                 id = pdev->id;
 439
 440         ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
 441         if (!ppdev)
 442                 return -ENOMEM;
 443
 444         /* Retain this platform_device pointer for later cleanup */
 445         priv->mii_pdev = ppdev;
 446         ppdev->dev.parent = &pdev->dev;
 447         ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
 448         if (pdata)
 449                 bcmgenet_mii_pdata_init(priv, &ppd);
 450
 451         ret = platform_device_add_resources(ppdev, &res, 1);
 452         if (ret)
 453                 goto out;
 454
 455         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
 456         if (ret)
 457                 goto out;
 458
 459         ret = platform_device_add(ppdev);
 460         if (ret)
 461                 goto out;
 462
 463         return 0;
 464 out:
 465         platform_device_put(ppdev);
 466         return ret;
 467 }
 468
 469 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 470 {
 471         struct device_node *dn = priv->pdev->dev.of_node;
 472         struct device *kdev = &priv->pdev->dev;
 473         struct phy_device *phydev;
 474         int phy_mode;
 475         int ret;
 476
 477         /* Fetch the PHY phandle */
 478         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 479
 480         /* In the case of a fixed PHY, the DT node associated
 481          * to the PHY is the Ethernet MAC DT node.
 482          */
 483         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 484                 ret = of_phy_register_fixed_link(dn);
 485                 if (ret)
 486                         return ret;
 487
 488                 priv->phy_dn = of_node_get(dn);
 489         }
 490
 491         /* Get the link mode */
 492         phy_mode = of_get_phy_mode(dn);
 493         if (phy_mode < 0) {
 494                 dev_err(kdev, "invalid PHY mode property\n");
 495                 return phy_mode;
 496         }
 497
 498         priv->phy_interface = phy_mode;
 499
 500         /* We need to specifically look up whether this PHY interface is internal
 501          * or not *before* we even try to probe the PHY driver over MDIO as we
 502          * may have shut down the internal PHY for power saving purposes.
 503          */
 504         if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
 505                 priv->internal_phy = true;
 506
 507         /* Make sure we initialize MoCA PHYs with a link down */
 508         if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
 509                 phydev = of_phy_find_device(dn);
 510                 if (phydev) {
 511                         phydev->link = 0;
 512                         put_device(&phydev->mdio.dev);
 513                 }
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 520 {
 521         struct device *kdev = &priv->pdev->dev;
 522         struct bcmgenet_platform_data *pd = kdev->platform_data;
 523         char phy_name[MII_BUS_ID_SIZE + 3];
 524         char mdio_bus_id[MII_BUS_ID_SIZE];
 525         struct phy_device *phydev;
 526
 527         snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
 528                  UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
 529
 530         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 531                 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
 532                          mdio_bus_id, pd->phy_address);
 533
 534                 /*
 535                  * Internal or external PHY with MDIO access
 536                  */
 537                 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
 538                 if (!phydev) {
 539                         dev_err(kdev, "failed to register PHY device\n");
 540                         return -ENODEV;
 541                 }
 542         } else {
 543                 /*
 544                  * MoCA port or no MDIO access.
 545                  * Use fixed PHY to represent the link layer.
 546                  */
 547                 struct fixed_phy_status fphy_status = {
 548                         .link = 1,
 549                         .speed = pd->phy_speed,
 550                         .duplex = pd->phy_duplex,
 551                         .pause = 0,
 552                         .asym_pause = 0,
 553                 };
 554
 555                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
 556                 if (!phydev || IS_ERR(phydev)) {
 557                         dev_err(kdev, "failed to register fixed PHY device\n");
 558                         return -ENODEV;
 559                 }
 560
 561                 /* Make sure we initialize MoCA PHYs with a link down */
 562                 phydev->link = 0;
 563
 564         }
 565
 566         priv->phydev = phydev;
 567         priv->phy_interface = pd->phy_interface;
 568
 569         return 0;
 570 }
 571
 572 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 573 {
 574         struct device_node *dn = priv->pdev->dev.of_node;
 575
 576         if (dn)
 577                 return bcmgenet_mii_of_init(priv);
 578         else
 579                 return bcmgenet_mii_pd_init(priv);
 580 }
 581
 582 int bcmgenet_mii_init(struct net_device *dev)
 583 {
 584         struct bcmgenet_priv *priv = netdev_priv(dev);
 585         int ret;
 586
 587         ret = bcmgenet_mii_register(priv);
 588         if (ret)
 589                 return ret;
 590
 591         ret = bcmgenet_mii_bus_init(priv);
 592         if (ret)
 593                 goto out;
 594
 595         return 0;
 596
 597 out:
 598         bcmgenet_mii_exit(dev);
 599         return ret;
 600 }
 601
 602 void bcmgenet_mii_exit(struct net_device *dev)
 603 {
 604         struct bcmgenet_priv *priv = netdev_priv(dev);
 605         struct device_node *dn = priv->pdev->dev.of_node;
 606
 607         if (of_phy_is_fixed_link(dn))
 608                 of_phy_deregister_fixed_link(dn);
 609         of_node_put(priv->phy_dn);
 610         platform_device_unregister(priv->mii_pdev);
 611         platform_device_put(priv->mii_pdev);
 612 }