drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <net/addrconf.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/crash_dump.h>
  68
  69 #include "cxgb4.h"
  70 #include "cxgb4_filter.h"
  71 #include "t4_regs.h"
  72 #include "t4_values.h"
  73 #include "t4_msg.h"
  74 #include "t4fw_api.h"
  75 #include "t4fw_version.h"
  76 #include "cxgb4_dcb.h"
  77 #include "cxgb4_debugfs.h"
  78 #include "clip_tbl.h"
  79 #include "l2t.h"
  80 #include "sched.h"
  81 #include "cxgb4_tc_u32.h"
  82 #include "cxgb4_ptp.h"
  83
  84 char cxgb4_driver_name[] = KBUILD_MODNAME;
  85
  86 #ifdef DRV_VERSION
  87 #undef DRV_VERSION
  88 #endif
  89 #define DRV_VERSION "2.0.0-ko"
  90 const char cxgb4_driver_version[] = DRV_VERSION;
  91 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
  92
  93 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  94                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
  95                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
  96
  97 /* Macros needed to support the PCI Device ID Table ...
  98  */
  99 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
 100         static const struct pci_device_id cxgb4_pci_tbl[] = {
 101 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
 102
 103 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 104  * called for both.
 105  */
 106 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 107
 108 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 109                 {PCI_VDEVICE(CHELSIO, (devid)), 4}
 110
 111 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 112                 { 0, } \
 113         }
 114
 115 #include "t4_pci_id_tbl.h"
 116
 117 #define FW4_FNAME "/*(DEBLOBBED)*/"
 118 #define FW5_FNAME "/*(DEBLOBBED)*/"
 119 #define FW6_FNAME "/*(DEBLOBBED)*/"
 120 #define FW4_CFNAME "cxgb4/t4-config.txt"
 121 #define FW5_CFNAME "cxgb4/t5-config.txt"
 122 #define FW6_CFNAME "cxgb4/t6-config.txt"
 123 #define PHY_AQ1202_FIRMWARE "/*(DEBLOBBED)*/"
 124 #define PHY_BCM84834_FIRMWARE "/*(DEBLOBBED)*/"
 125 #define PHY_AQ1202_DEVICEID 0x4409
 126 #define PHY_BCM84834_DEVICEID 0x4486
 127
 128 MODULE_DESCRIPTION(DRV_DESC);
 129 MODULE_AUTHOR("Chelsio Communications");
 130 MODULE_LICENSE("Dual BSD/GPL");
 131 MODULE_VERSION(DRV_VERSION);
 132 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 133 /*(DEBLOBBED)*/
 134
 135 /*
 136  * The driver uses the best interrupt scheme available on a platform in the
 137  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 138  * of these schemes the driver may consider as follows:
 139  *
 140  * msi = 2: choose from among all three options
 141  * msi = 1: only consider MSI and INTx interrupts
 142  * msi = 0: force INTx interrupts
 143  */
 144 static int msi = 2;
 145
 146 module_param(msi, int, 0644);
 147 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 148
 149 /*
 150  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 151  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 152  * boundaries.  This is a requirement for many architectures which will throw
 153  * a machine check fault if an attempt is made to access one of the 4-byte IP
 154  * header fields on a non-4-byte boundary.  And it's a major performance issue
 155  * even on some architectures which allow it like some implementations of the
 156  * x86 ISA.  However, some architectures don't mind this and for some very
 157  * edge-case performance sensitive applications (like forwarding large volumes
 158  * of small packets), setting this DMA offset to 0 will decrease the number of
 159  * PCI-E Bus transfers enough to measurably affect performance.
 160  */
 161 static int rx_dma_offset = 2;
 162
 163 /* TX Queue select used to determine what algorithm to use for selecting TX
 164  * queue. Select between the kernel provided function (select_queue=0) or user
 165  * cxgb_select_queue function (select_queue=1)
 166  *
 167  * Default: select_queue=0
 168  */
 169 static int select_queue;
 170 module_param(select_queue, int, 0644);
 171 MODULE_PARM_DESC(select_queue,
 172                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 173
 174 static struct dentry *cxgb4_debugfs_root;
 175
 176 LIST_HEAD(adapter_list);
 177 DEFINE_MUTEX(uld_mutex);
 178
 179 static void link_report(struct net_device *dev)
 180 {
 181         if (!netif_carrier_ok(dev))
 182                 netdev_info(dev, "link down\n");
 183         else {
 184                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 185
 186                 const char *s;
 187                 const struct port_info *p = netdev_priv(dev);
 188
 189                 switch (p->link_cfg.speed) {
 190                 case 100:
 191                         s = "100Mbps";
 192                         break;
 193                 case 1000:
 194                         s = "1Gbps";
 195                         break;
 196                 case 10000:
 197                         s = "10Gbps";
 198                         break;
 199                 case 25000:
 200                         s = "25Gbps";
 201                         break;
 202                 case 40000:
 203                         s = "40Gbps";
 204                         break;
 205                 case 100000:
 206                         s = "100Gbps";
 207                         break;
 208                 default:
 209                         pr_info("%s: unsupported speed: %d\n",
 210                                 dev->name, p->link_cfg.speed);
 211                         return;
 212                 }
 213
 214                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 215                             fc[p->link_cfg.fc]);
 216         }
 217 }
 218
 219 #ifdef CONFIG_CHELSIO_T4_DCB
 220 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 221 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 222 {
 223         struct port_info *pi = netdev_priv(dev);
 224         struct adapter *adap = pi->adapter;
 225         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 226         int i;
 227
 228         /* We use a simple mapping of Port TX Queue Index to DCB
 229          * Priority when we're enabling DCB.
 230          */
 231         for (i = 0; i < pi->nqsets; i++, txq++) {
 232                 u32 name, value;
 233                 int err;
 234
 235                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 236                         FW_PARAMS_PARAM_X_V(
 237                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 238                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 239                 value = enable ? i : 0xffffffff;
 240
 241                 /* Since we can be called while atomic (from "interrupt
 242                  * level") we need to issue the Set Parameters Commannd
 243                  * without sleeping (timeout < 0).
 244                  */
 245                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
 246                                             &name, &value,
 247                                             -FW_CMD_MAX_TIMEOUT);
 248
 249                 if (err)
 250                         dev_err(adap->pdev_dev,
 251                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 252                                 enable ? "set" : "unset", pi->port_id, i, -err);
 253                 else
 254                         txq->dcb_prio = enable ? value : 0;
 255         }
 256 }
 257
 258 static int cxgb4_dcb_enabled(const struct net_device *dev)
 259 {
 260         struct port_info *pi = netdev_priv(dev);
 261
 262         if (!pi->dcb.enabled)
 263                 return 0;
 264
 265         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 266                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 267 }
 268 #endif /* CONFIG_CHELSIO_T4_DCB */
 269
 270 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 271 {
 272         struct net_device *dev = adapter->port[port_id];
 273
 274         /* Skip changes from disabled ports. */
 275         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 276                 if (link_stat)
 277                         netif_carrier_on(dev);
 278                 else {
 279 #ifdef CONFIG_CHELSIO_T4_DCB
 280                         if (cxgb4_dcb_enabled(dev)) {
 281                                 cxgb4_dcb_state_init(dev);
 282                                 dcb_tx_queue_prio_enable(dev, false);
 283                         }
 284 #endif /* CONFIG_CHELSIO_T4_DCB */
 285                         netif_carrier_off(dev);
 286                 }
 287
 288                 link_report(dev);
 289         }
 290 }
 291
 292 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 293 {
 294         static const char *mod_str[] = {
 295                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 296         };
 297
 298         const struct net_device *dev = adap->port[port_id];
 299         const struct port_info *pi = netdev_priv(dev);
 300
 301         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 302                 netdev_info(dev, "port module unplugged\n");
 303         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 304                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 305         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 306                 netdev_info(dev, "%s: unsupported port module inserted\n",
 307                             dev->name);
 308         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 309                 netdev_info(dev, "%s: unknown port module inserted\n",
 310                             dev->name);
 311         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 312                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
 313         else
 314                 netdev_info(dev, "%s: unknown module type %d inserted\n",
 315                             dev->name, pi->mod_type);
 316 }
 317
 318 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 319 module_param(dbfifo_int_thresh, int, 0644);
 320 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 321
 322 /*
 323  * usecs to sleep while draining the dbfifo
 324  */
 325 static int dbfifo_drain_delay = 1000;
 326 module_param(dbfifo_drain_delay, int, 0644);
 327 MODULE_PARM_DESC(dbfifo_drain_delay,
 328                  "usecs to sleep while draining the dbfifo");
 329
 330 static inline int cxgb4_set_addr_hash(struct port_info *pi)
 331 {
 332         struct adapter *adap = pi->adapter;
 333         u64 vec = 0;
 334         bool ucast = false;
 335         struct hash_mac_addr *entry;
 336
 337         /* Calculate the hash vector for the updated list and program it */
 338         list_for_each_entry(entry, &adap->mac_hlist, list) {
 339                 ucast |= is_unicast_ether_addr(entry->addr);
 340                 vec |= (1ULL << hash_mac_addr(entry->addr));
 341         }
 342         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
 343                                 vec, false);
 344 }
 345
 346 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
 347 {
 348         struct port_info *pi = netdev_priv(netdev);
 349         struct adapter *adap = pi->adapter;
 350         int ret;
 351         u64 mhash = 0;
 352         u64 uhash = 0;
 353         bool free = false;
 354         bool ucast = is_unicast_ether_addr(mac_addr);
 355         const u8 *maclist[1] = {mac_addr};
 356         struct hash_mac_addr *new_entry;
 357
 358         ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
 359                                 NULL, ucast ? &uhash : &mhash, false);
 360         if (ret < 0)
 361                 goto out;
 362         /* if hash != 0, then add the addr to hash addr list
 363          * so on the end we will calculate the hash for the
 364          * list and program it
 365          */
 366         if (uhash || mhash) {
 367                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
 368                 if (!new_entry)
 369                         return -ENOMEM;
 370                 ether_addr_copy(new_entry->addr, mac_addr);
 371                 list_add_tail(&new_entry->list, &adap->mac_hlist);
 372                 ret = cxgb4_set_addr_hash(pi);
 373         }
 374 out:
 375         return ret < 0 ? ret : 0;
 376 }
 377
 378 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
 379 {
 380         struct port_info *pi = netdev_priv(netdev);
 381         struct adapter *adap = pi->adapter;
 382         int ret;
 383         const u8 *maclist[1] = {mac_addr};
 384         struct hash_mac_addr *entry, *tmp;
 385
 386         /* If the MAC address to be removed is in the hash addr
 387          * list, delete it from the list and update hash vector
 388          */
 389         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
 390                 if (ether_addr_equal(entry->addr, mac_addr)) {
 391                         list_del(&entry->list);
 392                         kfree(entry);
 393                         return cxgb4_set_addr_hash(pi);
 394                 }
 395         }
 396
 397         ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
 398         return ret < 0 ? -EINVAL : 0;
 399 }
 400
 401 /*
 402  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 403  * If @mtu is -1 it is left unchanged.
 404  */
 405 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 406 {
 407         struct port_info *pi = netdev_priv(dev);
 408         struct adapter *adapter = pi->adapter;
 409
 410         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 411         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 412
 413         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
 414                              (dev->flags & IFF_PROMISC) ? 1 : 0,
 415                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 416                              sleep_ok);
 417 }
 418
 419 /**
 420  *      link_start - enable a port
 421  *      @dev: the port to enable
 422  *
 423  *      Performs the MAC and PHY actions needed to enable a port.
 424  */
 425 static int link_start(struct net_device *dev)
 426 {
 427         int ret;
 428         struct port_info *pi = netdev_priv(dev);
 429         unsigned int mb = pi->adapter->pf;
 430
 431         /*
 432          * We do not set address filters and promiscuity here, the stack does
 433          * that step explicitly.
 434          */
 435         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 436                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 437         if (ret == 0) {
 438                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 439                                     pi->xact_addr_filt, dev->dev_addr, true,
 440                                     true);
 441                 if (ret >= 0) {
 442                         pi->xact_addr_filt = ret;
 443                         ret = 0;
 444                 }
 445         }
 446         if (ret == 0)
 447                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
 448                                     &pi->link_cfg);
 449         if (ret == 0) {
 450                 local_bh_disable();
 451                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 452                                           true, CXGB4_DCB_ENABLED);
 453                 local_bh_enable();
 454         }
 455
 456         return ret;
 457 }
 458
 459 #ifdef CONFIG_CHELSIO_T4_DCB
 460 /* Handle a Data Center Bridging update message from the firmware. */
 461 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 462 {
 463         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 464         struct net_device *dev = adap->port[adap->chan_map[port]];
 465         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 466         int new_dcb_enabled;
 467
 468         cxgb4_dcb_handle_fw_update(adap, pcmd);
 469         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 470
 471         /* If the DCB has become enabled or disabled on the port then we're
 472          * going to need to set up/tear down DCB Priority parameters for the
 473          * TX Queues associated with the port.
 474          */
 475         if (new_dcb_enabled != old_dcb_enabled)
 476                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 477 }
 478 #endif /* CONFIG_CHELSIO_T4_DCB */
 479
 480 /* Response queue handler for the FW event queue.
 481  */
 482 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 483                           const struct pkt_gl *gl)
 484 {
 485         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 486
 487         rsp++;                                          /* skip RSS header */
 488
 489         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 490          */
 491         if (unlikely(opcode == CPL_FW4_MSG &&
 492            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 493                 rsp++;
 494                 opcode = ((const struct rss_header *)rsp)->opcode;
 495                 rsp++;
 496                 if (opcode != CPL_SGE_EGR_UPDATE) {
 497                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 498                                 , opcode);
 499                         goto out;
 500                 }
 501         }
 502
 503         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 504                 const struct cpl_sge_egr_update *p = (void *)rsp;
 505                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
 506                 struct sge_txq *txq;
 507
 508                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 509                 txq->restarts++;
 510                 if (txq->q_type == CXGB4_TXQ_ETH) {
 511                         struct sge_eth_txq *eq;
 512
 513                         eq = container_of(txq, struct sge_eth_txq, q);
 514                         netif_tx_wake_queue(eq->txq);
 515                 } else {
 516                         struct sge_uld_txq *oq;
 517
 518                         oq = container_of(txq, struct sge_uld_txq, q);
 519                         tasklet_schedule(&oq->qresume_tsk);
 520                 }
 521         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 522                 const struct cpl_fw6_msg *p = (void *)rsp;
 523
 524 #ifdef CONFIG_CHELSIO_T4_DCB
 525                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 526                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 527                 unsigned int action =
 528                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 529
 530                 if (cmd == FW_PORT_CMD &&
 531                     (action == FW_PORT_ACTION_GET_PORT_INFO ||
 532                      action == FW_PORT_ACTION_GET_PORT_INFO32)) {
 533                         int port = FW_PORT_CMD_PORTID_G(
 534                                         be32_to_cpu(pcmd->op_to_portid));
 535                         struct net_device *dev;
 536                         int dcbxdis, state_input;
 537
 538                         dev = q->adap->port[q->adap->chan_map[port]];
 539                         dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
 540                                    ? !!(pcmd->u.info.dcbxdis_pkd &
 541                                         FW_PORT_CMD_DCBXDIS_F)
 542                                    : !!(pcmd->u.info32.lstatus32_to_cbllen32 &
 543                                         FW_PORT_CMD_DCBXDIS32_F));
 544                         state_input = (dcbxdis
 545                                        ? CXGB4_DCB_INPUT_FW_DISABLED
 546                                        : CXGB4_DCB_INPUT_FW_ENABLED);
 547
 548                         cxgb4_dcb_state_fsm(dev, state_input);
 549                 }
 550
 551                 if (cmd == FW_PORT_CMD &&
 552                     action == FW_PORT_ACTION_L2_DCB_CFG)
 553                         dcb_rpl(q->adap, pcmd);
 554                 else
 555 #endif
 556                         if (p->type == 0)
 557                                 t4_handle_fw_rpl(q->adap, p->data);
 558         } else if (opcode == CPL_L2T_WRITE_RPL) {
 559                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 560
 561                 do_l2t_write_rpl(q->adap, p);
 562         } else if (opcode == CPL_SET_TCB_RPL) {
 563                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 564
 565                 filter_rpl(q->adap, p);
 566         } else
 567                 dev_err(q->adap->pdev_dev,
 568                         "unexpected CPL %#x on FW event queue\n", opcode);
 569 out:
 570         return 0;
 571 }
 572
 573 static void disable_msi(struct adapter *adapter)
 574 {
 575         if (adapter->flags & USING_MSIX) {
 576                 pci_disable_msix(adapter->pdev);
 577                 adapter->flags &= ~USING_MSIX;
 578         } else if (adapter->flags & USING_MSI) {
 579                 pci_disable_msi(adapter->pdev);
 580                 adapter->flags &= ~USING_MSI;
 581         }
 582 }
 583
 584 /*
 585  * Interrupt handler for non-data events used with MSI-X.
 586  */
 587 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 588 {
 589         struct adapter *adap = cookie;
 590         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
 591
 592         if (v & PFSW_F) {
 593                 adap->swintr = 1;
 594                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
 595         }
 596         if (adap->flags & MASTER_PF)
 597                 t4_slow_intr_handler(adap);
 598         return IRQ_HANDLED;
 599 }
 600
 601 /*
 602  * Name the MSI-X interrupts.
 603  */
 604 static void name_msix_vecs(struct adapter *adap)
 605 {
 606         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 607
 608         /* non-data interrupts */
 609         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 610
 611         /* FW events */
 612         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 613                  adap->port[0]->name);
 614
 615         /* Ethernet queues */
 616         for_each_port(adap, j) {
 617                 struct net_device *d = adap->port[j];
 618                 const struct port_info *pi = netdev_priv(d);
 619
 620                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 621                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 622                                  d->name, i);
 623         }
 624 }
 625
 626 static int request_msix_queue_irqs(struct adapter *adap)
 627 {
 628         struct sge *s = &adap->sge;
 629         int err, ethqidx;
 630         int msi_index = 2;
 631
 632         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 633                           adap->msix_info[1].desc, &s->fw_evtq);
 634         if (err)
 635                 return err;
 636
 637         for_each_ethrxq(s, ethqidx) {
 638                 err = request_irq(adap->msix_info[msi_index].vec,
 639                                   t4_sge_intr_msix, 0,
 640                                   adap->msix_info[msi_index].desc,
 641                                   &s->ethrxq[ethqidx].rspq);
 642                 if (err)
 643                         goto unwind;
 644                 msi_index++;
 645         }
 646         return 0;
 647
 648 unwind:
 649         while (--ethqidx >= 0)
 650                 free_irq(adap->msix_info[--msi_index].vec,
 651                          &s->ethrxq[ethqidx].rspq);
 652         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 653         return err;
 654 }
 655
 656 static void free_msix_queue_irqs(struct adapter *adap)
 657 {
 658         int i, msi_index = 2;
 659         struct sge *s = &adap->sge;
 660
 661         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 662         for_each_ethrxq(s, i)
 663                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
 664 }
 665
 666 /**
 667  *      cxgb4_write_rss - write the RSS table for a given port
 668  *      @pi: the port
 669  *      @queues: array of queue indices for RSS
 670  *
 671  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 672  *      packets to the Rx queues in @queues.
 673  *      Should never be called before setting up sge eth rx queues
 674  */
 675 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 676 {
 677         u16 *rss;
 678         int i, err;
 679         struct adapter *adapter = pi->adapter;
 680         const struct sge_eth_rxq *rxq;
 681
 682         rxq = &adapter->sge.ethrxq[pi->first_qset];
 683         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
 684         if (!rss)
 685                 return -ENOMEM;
 686
 687         /* map the queue indices to queue ids */
 688         for (i = 0; i < pi->rss_size; i++, queues++)
 689                 rss[i] = rxq[*queues].rspq.abs_id;
 690
 691         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 692                                   pi->rss_size, rss, pi->rss_size);
 693         /* If Tunnel All Lookup isn't specified in the global RSS
 694          * Configuration, then we need to specify a default Ingress
 695          * Queue for any ingress packets which aren't hashed.  We'll
 696          * use our first ingress queue ...
 697          */
 698         if (!err)
 699                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 700                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
 701                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
 702                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
 703                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
 704                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
 705                                        rss[0]);
 706         kfree(rss);
 707         return err;
 708 }
 709
 710 /**
 711  *      setup_rss - configure RSS
 712  *      @adap: the adapter
 713  *
 714  *      Sets up RSS for each port.
 715  */
 716 static int setup_rss(struct adapter *adap)
 717 {
 718         int i, j, err;
 719
 720         for_each_port(adap, i) {
 721                 const struct port_info *pi = adap2pinfo(adap, i);
 722
 723                 /* Fill default values with equal distribution */
 724                 for (j = 0; j < pi->rss_size; j++)
 725                         pi->rss[j] = j % pi->nqsets;
 726
 727                 err = cxgb4_write_rss(pi, pi->rss);
 728                 if (err)
 729                         return err;
 730         }
 731         return 0;
 732 }
 733
 734 /*
 735  * Return the channel of the ingress queue with the given qid.
 736  */
 737 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 738 {
 739         qid -= p->ingr_start;
 740         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 741 }
 742
 743 /*
 744  * Wait until all NAPI handlers are descheduled.
 745  */
 746 static void quiesce_rx(struct adapter *adap)
 747 {
 748         int i;
 749
 750         for (i = 0; i < adap->sge.ingr_sz; i++) {
 751                 struct sge_rspq *q = adap->sge.ingr_map[i];
 752
 753                 if (q && q->handler)
 754                         napi_disable(&q->napi);
 755         }
 756 }
 757
 758 /* Disable interrupt and napi handler */
 759 static void disable_interrupts(struct adapter *adap)
 760 {
 761         if (adap->flags & FULL_INIT_DONE) {
 762                 t4_intr_disable(adap);
 763                 if (adap->flags & USING_MSIX) {
 764                         free_msix_queue_irqs(adap);
 765                         free_irq(adap->msix_info[0].vec, adap);
 766                 } else {
 767                         free_irq(adap->pdev->irq, adap);
 768                 }
 769                 quiesce_rx(adap);
 770         }
 771 }
 772
 773 /*
 774  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 775  */
 776 static void enable_rx(struct adapter *adap)
 777 {
 778         int i;
 779
 780         for (i = 0; i < adap->sge.ingr_sz; i++) {
 781                 struct sge_rspq *q = adap->sge.ingr_map[i];
 782
 783                 if (!q)
 784                         continue;
 785                 if (q->handler)
 786                         napi_enable(&q->napi);
 787
 788                 /* 0-increment GTS to start the timer and enable interrupts */
 789                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 790                              SEINTARM_V(q->intr_params) |
 791                              INGRESSQID_V(q->cntxt_id));
 792         }
 793 }
 794
 795
 796 static int setup_fw_sge_queues(struct adapter *adap)
 797 {
 798         struct sge *s = &adap->sge;
 799         int err = 0;
 800
 801         bitmap_zero(s->starving_fl, s->egr_sz);
 802         bitmap_zero(s->txq_maperr, s->egr_sz);
 803
 804         if (adap->flags & USING_MSIX)
 805                 adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
 806         else {
 807                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
 808                                        NULL, NULL, NULL, -1);
 809                 if (err)
 810                         return err;
 811                 adap->msi_idx = -((int)s->intrq.abs_id + 1);
 812         }
 813
 814         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
 815                                adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
 816         return err;
 817 }
 818
 819 /**
 820  *      setup_sge_queues - configure SGE Tx/Rx/response queues
 821  *      @adap: the adapter
 822  *
 823  *      Determines how many sets of SGE queues to use and initializes them.
 824  *      We support multiple queue sets per port if we have MSI-X, otherwise
 825  *      just one queue set per port.
 826  */
 827 static int setup_sge_queues(struct adapter *adap)
 828 {
 829         int err, i, j;
 830         struct sge *s = &adap->sge;
 831         struct sge_uld_rxq_info *rxq_info = NULL;
 832         unsigned int cmplqid = 0;
 833
 834         if (is_uld(adap))
 835                 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
 836
 837         for_each_port(adap, i) {
 838                 struct net_device *dev = adap->port[i];
 839                 struct port_info *pi = netdev_priv(dev);
 840                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
 841                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
 842
 843                 for (j = 0; j < pi->nqsets; j++, q++) {
 844                         if (adap->msi_idx > 0)
 845                                 adap->msi_idx++;
 846                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
 847                                                adap->msi_idx, &q->fl,
 848                                                t4_ethrx_handler,
 849                                                NULL,
 850                                                t4_get_tp_ch_map(adap,
 851                                                                 pi->tx_chan));
 852                         if (err)
 853                                 goto freeout;
 854                         q->rspq.idx = j;
 855                         memset(&q->stats, 0, sizeof(q->stats));
 856                 }
 857                 for (j = 0; j < pi->nqsets; j++, t++) {
 858                         err = t4_sge_alloc_eth_txq(adap, t, dev,
 859                                         netdev_get_tx_queue(dev, j),
 860                                         s->fw_evtq.cntxt_id);
 861                         if (err)
 862                                 goto freeout;
 863                 }
 864         }
 865
 866         for_each_port(adap, i) {
 867                 /* Note that cmplqid below is 0 if we don't
 868                  * have RDMA queues, and that's the right value.
 869                  */
 870                 if (rxq_info)
 871                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
 872
 873                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
 874                                             s->fw_evtq.cntxt_id, cmplqid);
 875                 if (err)
 876                         goto freeout;
 877         }
 878
 879         if (!is_t4(adap->params.chip)) {
 880                 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
 881                                            netdev_get_tx_queue(adap->port[0], 0)
 882                                            , s->fw_evtq.cntxt_id);
 883                 if (err)
 884                         goto freeout;
 885         }
 886
 887         t4_write_reg(adap, is_t4(adap->params.chip) ?
 888                                 MPS_TRC_RSS_CONTROL_A :
 889                                 MPS_T5_TRC_RSS_CONTROL_A,
 890                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
 891                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
 892         return 0;
 893 freeout:
 894         t4_free_sge_resources(adap);
 895         return err;
 896 }
 897
 898 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
 899                              void *accel_priv, select_queue_fallback_t fallback)
 900 {
 901         int txq;
 902
 903 #ifdef CONFIG_CHELSIO_T4_DCB
 904         /* If a Data Center Bridging has been successfully negotiated on this
 905          * link then we'll use the skb's priority to map it to a TX Queue.
 906          * The skb's priority is determined via the VLAN Tag Priority Code
 907          * Point field.
 908          */
 909         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
 910                 u16 vlan_tci;
 911                 int err;
 912
 913                 err = vlan_get_tag(skb, &vlan_tci);
 914                 if (unlikely(err)) {
 915                         if (net_ratelimit())
 916                                 netdev_warn(dev,
 917                                             "TX Packet without VLAN Tag on DCB Link\n");
 918                         txq = 0;
 919                 } else {
 920                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
 921 #ifdef CONFIG_CHELSIO_T4_FCOE
 922                         if (skb->protocol == htons(ETH_P_FCOE))
 923                                 txq = skb->priority & 0x7;
 924 #endif /* CONFIG_CHELSIO_T4_FCOE */
 925                 }
 926                 return txq;
 927         }
 928 #endif /* CONFIG_CHELSIO_T4_DCB */
 929
 930         if (select_queue) {
 931                 txq = (skb_rx_queue_recorded(skb)
 932                         ? skb_get_rx_queue(skb)
 933                         : smp_processor_id());
 934
 935                 while (unlikely(txq >= dev->real_num_tx_queues))
 936                         txq -= dev->real_num_tx_queues;
 937
 938                 return txq;
 939         }
 940
 941         return fallback(dev, skb) % dev->real_num_tx_queues;
 942 }
 943
 944 static int closest_timer(const struct sge *s, int time)
 945 {
 946         int i, delta, match = 0, min_delta = INT_MAX;
 947
 948         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 949                 delta = time - s->timer_val[i];
 950                 if (delta < 0)
 951                         delta = -delta;
 952                 if (delta < min_delta) {
 953                         min_delta = delta;
 954                         match = i;
 955                 }
 956         }
 957         return match;
 958 }
 959
 960 static int closest_thres(const struct sge *s, int thres)
 961 {
 962         int i, delta, match = 0, min_delta = INT_MAX;
 963
 964         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 965                 delta = thres - s->counter_val[i];
 966                 if (delta < 0)
 967                         delta = -delta;
 968                 if (delta < min_delta) {
 969                         min_delta = delta;
 970                         match = i;
 971                 }
 972         }
 973         return match;
 974 }
 975
 976 /**
 977  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 978  *      @q: the Rx queue
 979  *      @us: the hold-off time in us, or 0 to disable timer
 980  *      @cnt: the hold-off packet count, or 0 to disable counter
 981  *
 982  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
 983  *      one of the two needs to be enabled for the queue to generate interrupts.
 984  */
 985 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
 986                                unsigned int us, unsigned int cnt)
 987 {
 988         struct adapter *adap = q->adap;
 989
 990         if ((us | cnt) == 0)
 991                 cnt = 1;
 992
 993         if (cnt) {
 994                 int err;
 995                 u32 v, new_idx;
 996
 997                 new_idx = closest_thres(&adap->sge, cnt);
 998                 if (q->desc && q->pktcnt_idx != new_idx) {
 999                         /* the queue has already been created, update it */
1000                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1001                             FW_PARAMS_PARAM_X_V(
1002                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1003                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1004                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1005                                             &v, &new_idx);
1006                         if (err)
1007                                 return err;
1008                 }
1009                 q->pktcnt_idx = new_idx;
1010         }
1011
1012         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1013         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1014         return 0;
1015 }
1016
1017 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1018 {
1019         const struct port_info *pi = netdev_priv(dev);
1020         netdev_features_t changed = dev->features ^ features;
1021         int err;
1022
1023         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1024                 return 0;
1025
1026         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1027                             -1, -1, -1,
1028                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1029         if (unlikely(err))
1030                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1031         return err;
1032 }
1033
1034 static int setup_debugfs(struct adapter *adap)
1035 {
1036         if (IS_ERR_OR_NULL(adap->debugfs_root))
1037                 return -1;
1038
1039 #ifdef CONFIG_DEBUG_FS
1040         t4_setup_debugfs(adap);
1041 #endif
1042         return 0;
1043 }
1044
1045 /*
1046  * upper-layer driver support
1047  */
1048
1049 /*
1050  * Allocate an active-open TID and set it to the supplied value.
1051  */
1052 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1053 {
1054         int atid = -1;
1055
1056         spin_lock_bh(&t->atid_lock);
1057         if (t->afree) {
1058                 union aopen_entry *p = t->afree;
1059
1060                 atid = (p - t->atid_tab) + t->atid_base;
1061                 t->afree = p->next;
1062                 p->data = data;
1063                 t->atids_in_use++;
1064         }
1065         spin_unlock_bh(&t->atid_lock);
1066         return atid;
1067 }
1068 EXPORT_SYMBOL(cxgb4_alloc_atid);
1069
1070 /*
1071  * Release an active-open TID.
1072  */
1073 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1074 {
1075         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1076
1077         spin_lock_bh(&t->atid_lock);
1078         p->next = t->afree;
1079         t->afree = p;
1080         t->atids_in_use--;
1081         spin_unlock_bh(&t->atid_lock);
1082 }
1083 EXPORT_SYMBOL(cxgb4_free_atid);
1084
1085 /*
1086  * Allocate a server TID and set it to the supplied value.
1087  */
1088 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1089 {
1090         int stid;
1091
1092         spin_lock_bh(&t->stid_lock);
1093         if (family == PF_INET) {
1094                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1095                 if (stid < t->nstids)
1096                         __set_bit(stid, t->stid_bmap);
1097                 else
1098                         stid = -1;
1099         } else {
1100                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1101                 if (stid < 0)
1102                         stid = -1;
1103         }
1104         if (stid >= 0) {
1105                 t->stid_tab[stid].data = data;
1106                 stid += t->stid_base;
1107                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1108                  * This is equivalent to 4 TIDs. With CLIP enabled it
1109                  * needs 2 TIDs.
1110                  */
1111                 if (family == PF_INET6) {
1112                         t->stids_in_use += 2;
1113                         t->v6_stids_in_use += 2;
1114                 } else {
1115                         t->stids_in_use++;
1116                 }
1117         }
1118         spin_unlock_bh(&t->stid_lock);
1119         return stid;
1120 }
1121 EXPORT_SYMBOL(cxgb4_alloc_stid);
1122
1123 /* Allocate a server filter TID and set it to the supplied value.
1124  */
1125 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1126 {
1127         int stid;
1128
1129         spin_lock_bh(&t->stid_lock);
1130         if (family == PF_INET) {
1131                 stid = find_next_zero_bit(t->stid_bmap,
1132                                 t->nstids + t->nsftids, t->nstids);
1133                 if (stid < (t->nstids + t->nsftids))
1134                         __set_bit(stid, t->stid_bmap);
1135                 else
1136                         stid = -1;
1137         } else {
1138                 stid = -1;
1139         }
1140         if (stid >= 0) {
1141                 t->stid_tab[stid].data = data;
1142                 stid -= t->nstids;
1143                 stid += t->sftid_base;
1144                 t->sftids_in_use++;
1145         }
1146         spin_unlock_bh(&t->stid_lock);
1147         return stid;
1148 }
1149 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1150
1151 /* Release a server TID.
1152  */
1153 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1154 {
1155         /* Is it a server filter TID? */
1156         if (t->nsftids && (stid >= t->sftid_base)) {
1157                 stid -= t->sftid_base;
1158                 stid += t->nstids;
1159         } else {
1160                 stid -= t->stid_base;
1161         }
1162
1163         spin_lock_bh(&t->stid_lock);
1164         if (family == PF_INET)
1165                 __clear_bit(stid, t->stid_bmap);
1166         else
1167                 bitmap_release_region(t->stid_bmap, stid, 1);
1168         t->stid_tab[stid].data = NULL;
1169         if (stid < t->nstids) {
1170                 if (family == PF_INET6) {
1171                         t->stids_in_use -= 2;
1172                         t->v6_stids_in_use -= 2;
1173                 } else {
1174                         t->stids_in_use--;
1175                 }
1176         } else {
1177                 t->sftids_in_use--;
1178         }
1179
1180         spin_unlock_bh(&t->stid_lock);
1181 }
1182 EXPORT_SYMBOL(cxgb4_free_stid);
1183
1184 /*
1185  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1186  */
1187 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1188                            unsigned int tid)
1189 {
1190         struct cpl_tid_release *req;
1191
1192         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1193         req = __skb_put(skb, sizeof(*req));
1194         INIT_TP_WR(req, tid);
1195         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1196 }
1197
1198 /*
1199  * Queue a TID release request and if necessary schedule a work queue to
1200  * process it.
1201  */
1202 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1203                                     unsigned int tid)
1204 {
1205         void **p = &t->tid_tab[tid];
1206         struct adapter *adap = container_of(t, struct adapter, tids);
1207
1208         spin_lock_bh(&adap->tid_release_lock);
1209         *p = adap->tid_release_head;
1210         /* Low 2 bits encode the Tx channel number */
1211         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1212         if (!adap->tid_release_task_busy) {
1213                 adap->tid_release_task_busy = true;
1214                 queue_work(adap->workq, &adap->tid_release_task);
1215         }
1216         spin_unlock_bh(&adap->tid_release_lock);
1217 }
1218
1219 /*
1220  * Process the list of pending TID release requests.
1221  */
1222 static void process_tid_release_list(struct work_struct *work)
1223 {
1224         struct sk_buff *skb;
1225         struct adapter *adap;
1226
1227         adap = container_of(work, struct adapter, tid_release_task);
1228
1229         spin_lock_bh(&adap->tid_release_lock);
1230         while (adap->tid_release_head) {
1231                 void **p = adap->tid_release_head;
1232                 unsigned int chan = (uintptr_t)p & 3;
1233                 p = (void *)p - chan;
1234
1235                 adap->tid_release_head = *p;
1236                 *p = NULL;
1237                 spin_unlock_bh(&adap->tid_release_lock);
1238
1239                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1240                                          GFP_KERNEL)))
1241                         schedule_timeout_uninterruptible(1);
1242
1243                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1244                 t4_ofld_send(adap, skb);
1245                 spin_lock_bh(&adap->tid_release_lock);
1246         }
1247         adap->tid_release_task_busy = false;
1248         spin_unlock_bh(&adap->tid_release_lock);
1249 }
1250
1251 /*
1252  * Release a TID and inform HW.  If we are unable to allocate the release
1253  * message we defer to a work queue.
1254  */
1255 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1256                       unsigned short family)
1257 {
1258         struct sk_buff *skb;
1259         struct adapter *adap = container_of(t, struct adapter, tids);
1260
1261         WARN_ON(tid >= t->ntids);
1262
1263         if (t->tid_tab[tid]) {
1264                 t->tid_tab[tid] = NULL;
1265                 atomic_dec(&t->conns_in_use);
1266                 if (t->hash_base && (tid >= t->hash_base)) {
1267                         if (family == AF_INET6)
1268                                 atomic_sub(2, &t->hash_tids_in_use);
1269                         else
1270                                 atomic_dec(&t->hash_tids_in_use);
1271                 } else {
1272                         if (family == AF_INET6)
1273                                 atomic_sub(2, &t->tids_in_use);
1274                         else
1275                                 atomic_dec(&t->tids_in_use);
1276                 }
1277         }
1278
1279         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1280         if (likely(skb)) {
1281                 mk_tid_release(skb, chan, tid);
1282                 t4_ofld_send(adap, skb);
1283         } else
1284                 cxgb4_queue_tid_release(t, chan, tid);
1285 }
1286 EXPORT_SYMBOL(cxgb4_remove_tid);
1287
1288 /*
1289  * Allocate and initialize the TID tables.  Returns 0 on success.
1290  */
1291 static int tid_init(struct tid_info *t)
1292 {
1293         struct adapter *adap = container_of(t, struct adapter, tids);
1294         unsigned int max_ftids = t->nftids + t->nsftids;
1295         unsigned int natids = t->natids;
1296         unsigned int stid_bmap_size;
1297         unsigned int ftid_bmap_size;
1298         size_t size;
1299
1300         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1301         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1302         size = t->ntids * sizeof(*t->tid_tab) +
1303                natids * sizeof(*t->atid_tab) +
1304                t->nstids * sizeof(*t->stid_tab) +
1305                t->nsftids * sizeof(*t->stid_tab) +
1306                stid_bmap_size * sizeof(long) +
1307                max_ftids * sizeof(*t->ftid_tab) +
1308                ftid_bmap_size * sizeof(long);
1309
1310         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1311         if (!t->tid_tab)
1312                 return -ENOMEM;
1313
1314         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1315         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1316         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1317         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1318         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1319         spin_lock_init(&t->stid_lock);
1320         spin_lock_init(&t->atid_lock);
1321         spin_lock_init(&t->ftid_lock);
1322
1323         t->stids_in_use = 0;
1324         t->v6_stids_in_use = 0;
1325         t->sftids_in_use = 0;
1326         t->afree = NULL;
1327         t->atids_in_use = 0;
1328         atomic_set(&t->tids_in_use, 0);
1329         atomic_set(&t->conns_in_use, 0);
1330         atomic_set(&t->hash_tids_in_use, 0);
1331
1332         /* Setup the free list for atid_tab and clear the stid bitmap. */
1333         if (natids) {
1334                 while (--natids)
1335                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1336                 t->afree = t->atid_tab;
1337         }
1338
1339         if (is_offload(adap)) {
1340                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1341                 /* Reserve stid 0 for T4/T5 adapters */
1342                 if (!t->stid_base &&
1343                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1344                         __set_bit(0, t->stid_bmap);
1345         }
1346
1347         bitmap_zero(t->ftid_bmap, t->nftids);
1348         return 0;
1349 }
1350
1351 /**
1352  *      cxgb4_create_server - create an IP server
1353  *      @dev: the device
1354  *      @stid: the server TID
1355  *      @sip: local IP address to bind server to
1356  *      @sport: the server's TCP port
1357  *      @queue: queue to direct messages from this server to
1358  *
1359  *      Create an IP server for the given port and address.
1360  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1361  */
1362 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1363                         __be32 sip, __be16 sport, __be16 vlan,
1364                         unsigned int queue)
1365 {
1366         unsigned int chan;
1367         struct sk_buff *skb;
1368         struct adapter *adap;
1369         struct cpl_pass_open_req *req;
1370         int ret;
1371
1372         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1373         if (!skb)
1374                 return -ENOMEM;
1375
1376         adap = netdev2adap(dev);
1377         req = __skb_put(skb, sizeof(*req));
1378         INIT_TP_WR(req, 0);
1379         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1380         req->local_port = sport;
1381         req->peer_port = htons(0);
1382         req->local_ip = sip;
1383         req->peer_ip = htonl(0);
1384         chan = rxq_to_chan(&adap->sge, queue);
1385         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1386         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1387                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1388         ret = t4_mgmt_tx(adap, skb);
1389         return net_xmit_eval(ret);
1390 }
1391 EXPORT_SYMBOL(cxgb4_create_server);
1392
1393 /*      cxgb4_create_server6 - create an IPv6 server
1394  *      @dev: the device
1395  *      @stid: the server TID
1396  *      @sip: local IPv6 address to bind server to
1397  *      @sport: the server's TCP port
1398  *      @queue: queue to direct messages from this server to
1399  *
1400  *      Create an IPv6 server for the given port and address.
1401  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1402  */
1403 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1404                          const struct in6_addr *sip, __be16 sport,
1405                          unsigned int queue)
1406 {
1407         unsigned int chan;
1408         struct sk_buff *skb;
1409         struct adapter *adap;
1410         struct cpl_pass_open_req6 *req;
1411         int ret;
1412
1413         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1414         if (!skb)
1415                 return -ENOMEM;
1416
1417         adap = netdev2adap(dev);
1418         req = __skb_put(skb, sizeof(*req));
1419         INIT_TP_WR(req, 0);
1420         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1421         req->local_port = sport;
1422         req->peer_port = htons(0);
1423         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1424         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1425         req->peer_ip_hi = cpu_to_be64(0);
1426         req->peer_ip_lo = cpu_to_be64(0);
1427         chan = rxq_to_chan(&adap->sge, queue);
1428         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1429         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1430                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1431         ret = t4_mgmt_tx(adap, skb);
1432         return net_xmit_eval(ret);
1433 }
1434 EXPORT_SYMBOL(cxgb4_create_server6);
1435
1436 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1437                         unsigned int queue, bool ipv6)
1438 {
1439         struct sk_buff *skb;
1440         struct adapter *adap;
1441         struct cpl_close_listsvr_req *req;
1442         int ret;
1443
1444         adap = netdev2adap(dev);
1445
1446         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1447         if (!skb)
1448                 return -ENOMEM;
1449
1450         req = __skb_put(skb, sizeof(*req));
1451         INIT_TP_WR(req, 0);
1452         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1453         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1454                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1455         ret = t4_mgmt_tx(adap, skb);
1456         return net_xmit_eval(ret);
1457 }
1458 EXPORT_SYMBOL(cxgb4_remove_server);
1459
1460 /**
1461  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1462  *      @mtus: the HW MTU table
1463  *      @mtu: the target MTU
1464  *      @idx: index of selected entry in the MTU table
1465  *
1466  *      Returns the index and the value in the HW MTU table that is closest to
1467  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1468  *      table, in which case that smallest available value is selected.
1469  */
1470 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1471                             unsigned int *idx)
1472 {
1473         unsigned int i = 0;
1474
1475         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1476                 ++i;
1477         if (idx)
1478                 *idx = i;
1479         return mtus[i];
1480 }
1481 EXPORT_SYMBOL(cxgb4_best_mtu);
1482
1483 /**
1484  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1485  *     @mtus: the HW MTU table
1486  *     @header_size: Header Size
1487  *     @data_size_max: maximum Data Segment Size
1488  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1489  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1490  *
1491  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1492  *     MTU Table based solely on a Maximum MTU parameter, we break that
1493  *     parameter up into a Header Size and Maximum Data Segment Size, and
1494  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1495  *     the Hardware MTU Table which will result in a Data Segment Size with
1496  *     the requested alignment _and_ that MTU isn't "too far" from the
1497  *     closest MTU, then we'll return that rather than the closest MTU.
1498  */
1499 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1500                                     unsigned short header_size,
1501                                     unsigned short data_size_max,
1502                                     unsigned short data_size_align,
1503                                     unsigned int *mtu_idxp)
1504 {
1505         unsigned short max_mtu = header_size + data_size_max;
1506         unsigned short data_size_align_mask = data_size_align - 1;
1507         int mtu_idx, aligned_mtu_idx;
1508
1509         /* Scan the MTU Table till we find an MTU which is larger than our
1510          * Maximum MTU or we reach the end of the table.  Along the way,
1511          * record the last MTU found, if any, which will result in a Data
1512          * Segment Length matching the requested alignment.
1513          */
1514         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1515                 unsigned short data_size = mtus[mtu_idx] - header_size;
1516
1517                 /* If this MTU minus the Header Size would result in a
1518                  * Data Segment Size of the desired alignment, remember it.
1519                  */
1520                 if ((data_size & data_size_align_mask) == 0)
1521                         aligned_mtu_idx = mtu_idx;
1522
1523                 /* If we're not at the end of the Hardware MTU Table and the
1524                  * next element is larger than our Maximum MTU, drop out of
1525                  * the loop.
1526                  */
1527                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1528                         break;
1529         }
1530
1531         /* If we fell out of the loop because we ran to the end of the table,
1532          * then we just have to use the last [largest] entry.
1533          */
1534         if (mtu_idx == NMTUS)
1535                 mtu_idx--;
1536
1537         /* If we found an MTU which resulted in the requested Data Segment
1538          * Length alignment and that's "not far" from the largest MTU which is
1539          * less than or equal to the maximum MTU, then use that.
1540          */
1541         if (aligned_mtu_idx >= 0 &&
1542             mtu_idx - aligned_mtu_idx <= 1)
1543                 mtu_idx = aligned_mtu_idx;
1544
1545         /* If the caller has passed in an MTU Index pointer, pass the
1546          * MTU Index back.  Return the MTU value.
1547          */
1548         if (mtu_idxp)
1549                 *mtu_idxp = mtu_idx;
1550         return mtus[mtu_idx];
1551 }
1552 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1553
1554 /**
1555  *      cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1556  *      @chip: chip type
1557  *      @viid: VI id of the given port
1558  *
1559  *      Return the SMT index for this VI.
1560  */
1561 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1562 {
1563         /* In T4/T5, SMT contains 256 SMAC entries organized in
1564          * 128 rows of 2 entries each.
1565          * In T6, SMT contains 256 SMAC entries in 256 rows.
1566          * TODO: The below code needs to be updated when we add support
1567          * for 256 VFs.
1568          */
1569         if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1570                 return ((viid & 0x7f) << 1);
1571         else
1572                 return (viid & 0x7f);
1573 }
1574 EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1575
1576 /**
1577  *      cxgb4_port_chan - get the HW channel of a port
1578  *      @dev: the net device for the port
1579  *
1580  *      Return the HW Tx channel of the given port.
1581  */
1582 unsigned int cxgb4_port_chan(const struct net_device *dev)
1583 {
1584         return netdev2pinfo(dev)->tx_chan;
1585 }
1586 EXPORT_SYMBOL(cxgb4_port_chan);
1587
1588 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1589 {
1590         struct adapter *adap = netdev2adap(dev);
1591         u32 v1, v2, lp_count, hp_count;
1592
1593         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1594         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1595         if (is_t4(adap->params.chip)) {
1596                 lp_count = LP_COUNT_G(v1);
1597                 hp_count = HP_COUNT_G(v1);
1598         } else {
1599                 lp_count = LP_COUNT_T5_G(v1);
1600                 hp_count = HP_COUNT_T5_G(v2);
1601         }
1602         return lpfifo ? lp_count : hp_count;
1603 }
1604 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1605
1606 /**
1607  *      cxgb4_port_viid - get the VI id of a port
1608  *      @dev: the net device for the port
1609  *
1610  *      Return the VI id of the given port.
1611  */
1612 unsigned int cxgb4_port_viid(const struct net_device *dev)
1613 {
1614         return netdev2pinfo(dev)->viid;
1615 }
1616 EXPORT_SYMBOL(cxgb4_port_viid);
1617
1618 /**
1619  *      cxgb4_port_idx - get the index of a port
1620  *      @dev: the net device for the port
1621  *
1622  *      Return the index of the given port.
1623  */
1624 unsigned int cxgb4_port_idx(const struct net_device *dev)
1625 {
1626         return netdev2pinfo(dev)->port_id;
1627 }
1628 EXPORT_SYMBOL(cxgb4_port_idx);
1629
1630 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1631                          struct tp_tcp_stats *v6)
1632 {
1633         struct adapter *adap = pci_get_drvdata(pdev);
1634
1635         spin_lock(&adap->stats_lock);
1636         t4_tp_get_tcp_stats(adap, v4, v6);
1637         spin_unlock(&adap->stats_lock);
1638 }
1639 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1640
1641 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1642                       const unsigned int *pgsz_order)
1643 {
1644         struct adapter *adap = netdev2adap(dev);
1645
1646         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1647         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1648                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1649                      HPZ3_V(pgsz_order[3]));
1650 }
1651 EXPORT_SYMBOL(cxgb4_iscsi_init);
1652
1653 int cxgb4_flush_eq_cache(struct net_device *dev)
1654 {
1655         struct adapter *adap = netdev2adap(dev);
1656
1657         return t4_sge_ctxt_flush(adap, adap->mbox);
1658 }
1659 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1660
1661 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1662 {
1663         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1664         __be64 indices;
1665         int ret;
1666
1667         spin_lock(&adap->win0_lock);
1668         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1669                            sizeof(indices), (__be32 *)&indices,
1670                            T4_MEMORY_READ);
1671         spin_unlock(&adap->win0_lock);
1672         if (!ret) {
1673                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1674                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1675         }
1676         return ret;
1677 }
1678
1679 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1680                         u16 size)
1681 {
1682         struct adapter *adap = netdev2adap(dev);
1683         u16 hw_pidx, hw_cidx;
1684         int ret;
1685
1686         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1687         if (ret)
1688                 goto out;
1689
1690         if (pidx != hw_pidx) {
1691                 u16 delta;
1692                 u32 val;
1693
1694                 if (pidx >= hw_pidx)
1695                         delta = pidx - hw_pidx;
1696                 else
1697                         delta = size - hw_pidx + pidx;
1698
1699                 if (is_t4(adap->params.chip))
1700                         val = PIDX_V(delta);
1701                 else
1702                         val = PIDX_T5_V(delta);
1703                 wmb();
1704                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1705                              QID_V(qid) | val);
1706         }
1707 out:
1708         return ret;
1709 }
1710 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1711
1712 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1713 {
1714         struct adapter *adap;
1715         u32 offset, memtype, memaddr;
1716         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1717         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1718         int ret;
1719
1720         adap = netdev2adap(dev);
1721
1722         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1723
1724         /* Figure out where the offset lands in the Memory Type/Address scheme.
1725          * This code assumes that the memory is laid out starting at offset 0
1726          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1727          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1728          * MC0, and some have both MC0 and MC1.
1729          */
1730         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1731         edc0_size = EDRAM0_SIZE_G(size) << 20;
1732         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1733         edc1_size = EDRAM1_SIZE_G(size) << 20;
1734         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1735         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1736
1737         edc0_end = edc0_size;
1738         edc1_end = edc0_end + edc1_size;
1739         mc0_end = edc1_end + mc0_size;
1740
1741         if (offset < edc0_end) {
1742                 memtype = MEM_EDC0;
1743                 memaddr = offset;
1744         } else if (offset < edc1_end) {
1745                 memtype = MEM_EDC1;
1746                 memaddr = offset - edc0_end;
1747         } else {
1748                 if (offset < mc0_end) {
1749                         memtype = MEM_MC0;
1750                         memaddr = offset - edc1_end;
1751                 } else if (is_t5(adap->params.chip)) {
1752                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1753                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1754                         mc1_end = mc0_end + mc1_size;
1755                         if (offset < mc1_end) {
1756                                 memtype = MEM_MC1;
1757                                 memaddr = offset - mc0_end;
1758                         } else {
1759                                 /* offset beyond the end of any memory */
1760                                 goto err;
1761                         }
1762                 } else {
1763                         /* T4/T6 only has a single memory channel */
1764                         goto err;
1765                 }
1766         }
1767
1768         spin_lock(&adap->win0_lock);
1769         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1770         spin_unlock(&adap->win0_lock);
1771         return ret;
1772
1773 err:
1774         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1775                 stag, offset);
1776         return -EINVAL;
1777 }
1778 EXPORT_SYMBOL(cxgb4_read_tpte);
1779
1780 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1781 {
1782         u32 hi, lo;
1783         struct adapter *adap;
1784
1785         adap = netdev2adap(dev);
1786         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1787         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1788
1789         return ((u64)hi << 32) | (u64)lo;
1790 }
1791 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1792
1793 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1794                          unsigned int qid,
1795                          enum cxgb4_bar2_qtype qtype,
1796                          int user,
1797                          u64 *pbar2_qoffset,
1798                          unsigned int *pbar2_qid)
1799 {
1800         return t4_bar2_sge_qregs(netdev2adap(dev),
1801                                  qid,
1802                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
1803                                   ? T4_BAR2_QTYPE_EGRESS
1804                                   : T4_BAR2_QTYPE_INGRESS),
1805                                  user,
1806                                  pbar2_qoffset,
1807                                  pbar2_qid);
1808 }
1809 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1810
1811 static struct pci_driver cxgb4_driver;
1812
1813 static void check_neigh_update(struct neighbour *neigh)
1814 {
1815         const struct device *parent;
1816         const struct net_device *netdev = neigh->dev;
1817
1818         if (is_vlan_dev(netdev))
1819                 netdev = vlan_dev_real_dev(netdev);
1820         parent = netdev->dev.parent;
1821         if (parent && parent->driver == &cxgb4_driver.driver)
1822                 t4_l2t_update(dev_get_drvdata(parent), neigh);
1823 }
1824
1825 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1826                        void *data)
1827 {
1828         switch (event) {
1829         case NETEVENT_NEIGH_UPDATE:
1830                 check_neigh_update(data);
1831                 break;
1832         case NETEVENT_REDIRECT:
1833         default:
1834                 break;
1835         }
1836         return 0;
1837 }
1838
1839 static bool netevent_registered;
1840 static struct notifier_block cxgb4_netevent_nb = {
1841         .notifier_call = netevent_cb
1842 };
1843
1844 static void drain_db_fifo(struct adapter *adap, int usecs)
1845 {
1846         u32 v1, v2, lp_count, hp_count;
1847
1848         do {
1849                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1850                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1851                 if (is_t4(adap->params.chip)) {
1852                         lp_count = LP_COUNT_G(v1);
1853                         hp_count = HP_COUNT_G(v1);
1854                 } else {
1855                         lp_count = LP_COUNT_T5_G(v1);
1856                         hp_count = HP_COUNT_T5_G(v2);
1857                 }
1858
1859                 if (lp_count == 0 && hp_count == 0)
1860                         break;
1861                 set_current_state(TASK_UNINTERRUPTIBLE);
1862                 schedule_timeout(usecs_to_jiffies(usecs));
1863         } while (1);
1864 }
1865
1866 static void disable_txq_db(struct sge_txq *q)
1867 {
1868         unsigned long flags;
1869
1870         spin_lock_irqsave(&q->db_lock, flags);
1871         q->db_disabled = 1;
1872         spin_unlock_irqrestore(&q->db_lock, flags);
1873 }
1874
1875 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1876 {
1877         spin_lock_irq(&q->db_lock);
1878         if (q->db_pidx_inc) {
1879                 /* Make sure that all writes to the TX descriptors
1880                  * are committed before we tell HW about them.
1881                  */
1882                 wmb();
1883                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1884                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1885                 q->db_pidx_inc = 0;
1886         }
1887         q->db_disabled = 0;
1888         spin_unlock_irq(&q->db_lock);
1889 }
1890
1891 static void disable_dbs(struct adapter *adap)
1892 {
1893         int i;
1894
1895         for_each_ethrxq(&adap->sge, i)
1896                 disable_txq_db(&adap->sge.ethtxq[i].q);
1897         if (is_offload(adap)) {
1898                 struct sge_uld_txq_info *txq_info =
1899                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1900
1901                 if (txq_info) {
1902                         for_each_ofldtxq(&adap->sge, i) {
1903                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1904
1905                                 disable_txq_db(&txq->q);
1906                         }
1907                 }
1908         }
1909         for_each_port(adap, i)
1910                 disable_txq_db(&adap->sge.ctrlq[i].q);
1911 }
1912
1913 static void enable_dbs(struct adapter *adap)
1914 {
1915         int i;
1916
1917         for_each_ethrxq(&adap->sge, i)
1918                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1919         if (is_offload(adap)) {
1920                 struct sge_uld_txq_info *txq_info =
1921                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1922
1923                 if (txq_info) {
1924                         for_each_ofldtxq(&adap->sge, i) {
1925                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1926
1927                                 enable_txq_db(adap, &txq->q);
1928                         }
1929                 }
1930         }
1931         for_each_port(adap, i)
1932                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
1933 }
1934
1935 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
1936 {
1937         enum cxgb4_uld type = CXGB4_ULD_RDMA;
1938
1939         if (adap->uld && adap->uld[type].handle)
1940                 adap->uld[type].control(adap->uld[type].handle, cmd);
1941 }
1942
1943 static void process_db_full(struct work_struct *work)
1944 {
1945         struct adapter *adap;
1946
1947         adap = container_of(work, struct adapter, db_full_task);
1948
1949         drain_db_fifo(adap, dbfifo_drain_delay);
1950         enable_dbs(adap);
1951         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
1952         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1953                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1954                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
1955                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
1956         else
1957                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1958                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
1959 }
1960
1961 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
1962 {
1963         u16 hw_pidx, hw_cidx;
1964         int ret;
1965
1966         spin_lock_irq(&q->db_lock);
1967         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
1968         if (ret)
1969                 goto out;
1970         if (q->db_pidx != hw_pidx) {
1971                 u16 delta;
1972                 u32 val;
1973
1974                 if (q->db_pidx >= hw_pidx)
1975                         delta = q->db_pidx - hw_pidx;
1976                 else
1977                         delta = q->size - hw_pidx + q->db_pidx;
1978
1979                 if (is_t4(adap->params.chip))
1980                         val = PIDX_V(delta);
1981                 else
1982                         val = PIDX_T5_V(delta);
1983                 wmb();
1984                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1985                              QID_V(q->cntxt_id) | val);
1986         }
1987 out:
1988         q->db_disabled = 0;
1989         q->db_pidx_inc = 0;
1990         spin_unlock_irq(&q->db_lock);
1991         if (ret)
1992                 CH_WARN(adap, "DB drop recovery failed.\n");
1993 }
1994
1995 static void recover_all_queues(struct adapter *adap)
1996 {
1997         int i;
1998
1999         for_each_ethrxq(&adap->sge, i)
2000                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2001         if (is_offload(adap)) {
2002                 struct sge_uld_txq_info *txq_info =
2003                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2004                 if (txq_info) {
2005                         for_each_ofldtxq(&adap->sge, i) {
2006                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2007
2008                                 sync_txq_pidx(adap, &txq->q);
2009                         }
2010                 }
2011         }
2012         for_each_port(adap, i)
2013                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2014 }
2015
2016 static void process_db_drop(struct work_struct *work)
2017 {
2018         struct adapter *adap;
2019
2020         adap = container_of(work, struct adapter, db_drop_task);
2021
2022         if (is_t4(adap->params.chip)) {
2023                 drain_db_fifo(adap, dbfifo_drain_delay);
2024                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2025                 drain_db_fifo(adap, dbfifo_drain_delay);
2026                 recover_all_queues(adap);
2027                 drain_db_fifo(adap, dbfifo_drain_delay);
2028                 enable_dbs(adap);
2029                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2030         } else if (is_t5(adap->params.chip)) {
2031                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2032                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2033                 u16 pidx_inc = dropped_db & 0x1fff;
2034                 u64 bar2_qoffset;
2035                 unsigned int bar2_qid;
2036                 int ret;
2037
2038                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2039                                         0, &bar2_qoffset, &bar2_qid);
2040                 if (ret)
2041                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2042                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2043                 else
2044                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2045                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2046
2047                 /* Re-enable BAR2 WC */
2048                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2049         }
2050
2051         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2052                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2053 }
2054
2055 void t4_db_full(struct adapter *adap)
2056 {
2057         if (is_t4(adap->params.chip)) {
2058                 disable_dbs(adap);
2059                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2060                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2061                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2062                 queue_work(adap->workq, &adap->db_full_task);
2063         }
2064 }
2065
2066 void t4_db_dropped(struct adapter *adap)
2067 {
2068         if (is_t4(adap->params.chip)) {
2069                 disable_dbs(adap);
2070                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2071         }
2072         queue_work(adap->workq, &adap->db_drop_task);
2073 }
2074
2075 void t4_register_netevent_notifier(void)
2076 {
2077         if (!netevent_registered) {
2078                 register_netevent_notifier(&cxgb4_netevent_nb);
2079                 netevent_registered = true;
2080         }
2081 }
2082
2083 static void detach_ulds(struct adapter *adap)
2084 {
2085         unsigned int i;
2086
2087         mutex_lock(&uld_mutex);
2088         list_del(&adap->list_node);
2089
2090         for (i = 0; i < CXGB4_ULD_MAX; i++)
2091                 if (adap->uld && adap->uld[i].handle)
2092                         adap->uld[i].state_change(adap->uld[i].handle,
2093                                              CXGB4_STATE_DETACH);
2094
2095         if (netevent_registered && list_empty(&adapter_list)) {
2096                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2097                 netevent_registered = false;
2098         }
2099         mutex_unlock(&uld_mutex);
2100 }
2101
2102 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2103 {
2104         unsigned int i;
2105
2106         mutex_lock(&uld_mutex);
2107         for (i = 0; i < CXGB4_ULD_MAX; i++)
2108                 if (adap->uld && adap->uld[i].handle)
2109                         adap->uld[i].state_change(adap->uld[i].handle,
2110                                                   new_state);
2111         mutex_unlock(&uld_mutex);
2112 }
2113
2114 #if IS_ENABLED(CONFIG_IPV6)
2115 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2116                                    unsigned long event, void *data)
2117 {
2118         struct inet6_ifaddr *ifa = data;
2119         struct net_device *event_dev = ifa->idev->dev;
2120         const struct device *parent = NULL;
2121 #if IS_ENABLED(CONFIG_BONDING)
2122         struct adapter *adap;
2123 #endif
2124         if (is_vlan_dev(event_dev))
2125                 event_dev = vlan_dev_real_dev(event_dev);
2126 #if IS_ENABLED(CONFIG_BONDING)
2127         if (event_dev->flags & IFF_MASTER) {
2128                 list_for_each_entry(adap, &adapter_list, list_node) {
2129                         switch (event) {
2130                         case NETDEV_UP:
2131                                 cxgb4_clip_get(adap->port[0],
2132                                                (const u32 *)ifa, 1);
2133                                 break;
2134                         case NETDEV_DOWN:
2135                                 cxgb4_clip_release(adap->port[0],
2136                                                    (const u32 *)ifa, 1);
2137                                 break;
2138                         default:
2139                                 break;
2140                         }
2141                 }
2142                 return NOTIFY_OK;
2143         }
2144 #endif
2145
2146         if (event_dev)
2147                 parent = event_dev->dev.parent;
2148
2149         if (parent && parent->driver == &cxgb4_driver.driver) {
2150                 switch (event) {
2151                 case NETDEV_UP:
2152                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2153                         break;
2154                 case NETDEV_DOWN:
2155                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2156                         break;
2157                 default:
2158                         break;
2159                 }
2160         }
2161         return NOTIFY_OK;
2162 }
2163
2164 static bool inet6addr_registered;
2165 static struct notifier_block cxgb4_inet6addr_notifier = {
2166         .notifier_call = cxgb4_inet6addr_handler
2167 };
2168
2169 static void update_clip(const struct adapter *adap)
2170 {
2171         int i;
2172         struct net_device *dev;
2173         int ret;
2174
2175         rcu_read_lock();
2176
2177         for (i = 0; i < MAX_NPORTS; i++) {
2178                 dev = adap->port[i];
2179                 ret = 0;
2180
2181                 if (dev)
2182                         ret = cxgb4_update_root_dev_clip(dev);
2183
2184                 if (ret < 0)
2185                         break;
2186         }
2187         rcu_read_unlock();
2188 }
2189 #endif /* IS_ENABLED(CONFIG_IPV6) */
2190
2191 /**
2192  *      cxgb_up - enable the adapter
2193  *      @adap: adapter being enabled
2194  *
2195  *      Called when the first port is enabled, this function performs the
2196  *      actions necessary to make an adapter operational, such as completing
2197  *      the initialization of HW modules, and enabling interrupts.
2198  *
2199  *      Must be called with the rtnl lock held.
2200  */
2201 static int cxgb_up(struct adapter *adap)
2202 {
2203         int err;
2204
2205         mutex_lock(&uld_mutex);
2206         err = setup_sge_queues(adap);
2207         if (err)
2208                 goto rel_lock;
2209         err = setup_rss(adap);
2210         if (err)
2211                 goto freeq;
2212
2213         if (adap->flags & USING_MSIX) {
2214                 name_msix_vecs(adap);
2215                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2216                                   adap->msix_info[0].desc, adap);
2217                 if (err)
2218                         goto irq_err;
2219                 err = request_msix_queue_irqs(adap);
2220                 if (err) {
2221                         free_irq(adap->msix_info[0].vec, adap);
2222                         goto irq_err;
2223                 }
2224         } else {
2225                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2226                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2227                                   adap->port[0]->name, adap);
2228                 if (err)
2229                         goto irq_err;
2230         }
2231
2232         enable_rx(adap);
2233         t4_sge_start(adap);
2234         t4_intr_enable(adap);
2235         adap->flags |= FULL_INIT_DONE;
2236         mutex_unlock(&uld_mutex);
2237
2238         notify_ulds(adap, CXGB4_STATE_UP);
2239 #if IS_ENABLED(CONFIG_IPV6)
2240         update_clip(adap);
2241 #endif
2242         return err;
2243
2244  irq_err:
2245         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2246  freeq:
2247         t4_free_sge_resources(adap);
2248  rel_lock:
2249         mutex_unlock(&uld_mutex);
2250         return err;
2251 }
2252
2253 static void cxgb_down(struct adapter *adapter)
2254 {
2255         cancel_work_sync(&adapter->tid_release_task);
2256         cancel_work_sync(&adapter->db_full_task);
2257         cancel_work_sync(&adapter->db_drop_task);
2258         adapter->tid_release_task_busy = false;
2259         adapter->tid_release_head = NULL;
2260
2261         t4_sge_stop(adapter);
2262         t4_free_sge_resources(adapter);
2263
2264         adapter->flags &= ~FULL_INIT_DONE;
2265 }
2266
2267 /*
2268  * net_device operations
2269  */
2270 static int cxgb_open(struct net_device *dev)
2271 {
2272         int err;
2273         struct port_info *pi = netdev_priv(dev);
2274         struct adapter *adapter = pi->adapter;
2275
2276         netif_carrier_off(dev);
2277
2278         if (!(adapter->flags & FULL_INIT_DONE)) {
2279                 err = cxgb_up(adapter);
2280                 if (err < 0)
2281                         return err;
2282         }
2283
2284         /* It's possible that the basic port information could have
2285          * changed since we first read it.
2286          */
2287         err = t4_update_port_info(pi);
2288         if (err < 0)
2289                 return err;
2290
2291         err = link_start(dev);
2292         if (!err)
2293                 netif_tx_start_all_queues(dev);
2294         return err;
2295 }
2296
2297 static int cxgb_close(struct net_device *dev)
2298 {
2299         struct port_info *pi = netdev_priv(dev);
2300         struct adapter *adapter = pi->adapter;
2301
2302         netif_tx_stop_all_queues(dev);
2303         netif_carrier_off(dev);
2304         return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2305 }
2306
2307 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2308                 __be32 sip, __be16 sport, __be16 vlan,
2309                 unsigned int queue, unsigned char port, unsigned char mask)
2310 {
2311         int ret;
2312         struct filter_entry *f;
2313         struct adapter *adap;
2314         int i;
2315         u8 *val;
2316
2317         adap = netdev2adap(dev);
2318
2319         /* Adjust stid to correct filter index */
2320         stid -= adap->tids.sftid_base;
2321         stid += adap->tids.nftids;
2322
2323         /* Check to make sure the filter requested is writable ...
2324          */
2325         f = &adap->tids.ftid_tab[stid];
2326         ret = writable_filter(f);
2327         if (ret)
2328                 return ret;
2329
2330         /* Clear out any old resources being used by the filter before
2331          * we start constructing the new filter.
2332          */
2333         if (f->valid)
2334                 clear_filter(adap, f);
2335
2336         /* Clear out filter specifications */
2337         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2338         f->fs.val.lport = cpu_to_be16(sport);
2339         f->fs.mask.lport  = ~0;
2340         val = (u8 *)&sip;
2341         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2342                 for (i = 0; i < 4; i++) {
2343                         f->fs.val.lip[i] = val[i];
2344                         f->fs.mask.lip[i] = ~0;
2345                 }
2346                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2347                         f->fs.val.iport = port;
2348                         f->fs.mask.iport = mask;
2349                 }
2350         }
2351
2352         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2353                 f->fs.val.proto = IPPROTO_TCP;
2354                 f->fs.mask.proto = ~0;
2355         }
2356
2357         f->fs.dirsteer = 1;
2358         f->fs.iq = queue;
2359         /* Mark filter as locked */
2360         f->locked = 1;
2361         f->fs.rpttid = 1;
2362
2363         /* Save the actual tid. We need this to get the corresponding
2364          * filter entry structure in filter_rpl.
2365          */
2366         f->tid = stid + adap->tids.ftid_base;
2367         ret = set_filter_wr(adap, stid);
2368         if (ret) {
2369                 clear_filter(adap, f);
2370                 return ret;
2371         }
2372
2373         return 0;
2374 }
2375 EXPORT_SYMBOL(cxgb4_create_server_filter);
2376
2377 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2378                 unsigned int queue, bool ipv6)
2379 {
2380         struct filter_entry *f;
2381         struct adapter *adap;
2382
2383         adap = netdev2adap(dev);
2384
2385         /* Adjust stid to correct filter index */
2386         stid -= adap->tids.sftid_base;
2387         stid += adap->tids.nftids;
2388
2389         f = &adap->tids.ftid_tab[stid];
2390         /* Unlock the filter */
2391         f->locked = 0;
2392
2393         return delete_filter(adap, stid);
2394 }
2395 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2396
2397 static void cxgb_get_stats(struct net_device *dev,
2398                            struct rtnl_link_stats64 *ns)
2399 {
2400         struct port_stats stats;
2401         struct port_info *p = netdev_priv(dev);
2402         struct adapter *adapter = p->adapter;
2403
2404         /* Block retrieving statistics during EEH error
2405          * recovery. Otherwise, the recovery might fail
2406          * and the PCI device will be removed permanently
2407          */
2408         spin_lock(&adapter->stats_lock);
2409         if (!netif_device_present(dev)) {
2410                 spin_unlock(&adapter->stats_lock);
2411                 return;
2412         }
2413         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2414                                  &p->stats_base);
2415         spin_unlock(&adapter->stats_lock);
2416
2417         ns->tx_bytes   = stats.tx_octets;
2418         ns->tx_packets = stats.tx_frames;
2419         ns->rx_bytes   = stats.rx_octets;
2420         ns->rx_packets = stats.rx_frames;
2421         ns->multicast  = stats.rx_mcast_frames;
2422
2423         /* detailed rx_errors */
2424         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2425                                stats.rx_runt;
2426         ns->rx_over_errors   = 0;
2427         ns->rx_crc_errors    = stats.rx_fcs_err;
2428         ns->rx_frame_errors  = stats.rx_symbol_err;
2429         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2430                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2431                                stats.rx_trunc0 + stats.rx_trunc1 +
2432                                stats.rx_trunc2 + stats.rx_trunc3;
2433         ns->rx_missed_errors = 0;
2434
2435         /* detailed tx_errors */
2436         ns->tx_aborted_errors   = 0;
2437         ns->tx_carrier_errors   = 0;
2438         ns->tx_fifo_errors      = 0;
2439         ns->tx_heartbeat_errors = 0;
2440         ns->tx_window_errors    = 0;
2441
2442         ns->tx_errors = stats.tx_error_frames;
2443         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2444                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2445 }
2446
2447 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2448 {
2449         unsigned int mbox;
2450         int ret = 0, prtad, devad;
2451         struct port_info *pi = netdev_priv(dev);
2452         struct adapter *adapter = pi->adapter;
2453         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2454
2455         switch (cmd) {
2456         case SIOCGMIIPHY:
2457                 if (pi->mdio_addr < 0)
2458                         return -EOPNOTSUPP;
2459                 data->phy_id = pi->mdio_addr;
2460                 break;
2461         case SIOCGMIIREG:
2462         case SIOCSMIIREG:
2463                 if (mdio_phy_id_is_c45(data->phy_id)) {
2464                         prtad = mdio_phy_id_prtad(data->phy_id);
2465                         devad = mdio_phy_id_devad(data->phy_id);
2466                 } else if (data->phy_id < 32) {
2467                         prtad = data->phy_id;
2468                         devad = 0;
2469                         data->reg_num &= 0x1f;
2470                 } else
2471                         return -EINVAL;
2472
2473                 mbox = pi->adapter->pf;
2474                 if (cmd == SIOCGMIIREG)
2475                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2476                                          data->reg_num, &data->val_out);
2477                 else
2478                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2479                                          data->reg_num, data->val_in);
2480                 break;
2481         case SIOCGHWTSTAMP:
2482                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2483                                     sizeof(pi->tstamp_config)) ?
2484                         -EFAULT : 0;
2485         case SIOCSHWTSTAMP:
2486                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2487                                    sizeof(pi->tstamp_config)))
2488                         return -EFAULT;
2489
2490                 if (!is_t4(adapter->params.chip)) {
2491                         switch (pi->tstamp_config.tx_type) {
2492                         case HWTSTAMP_TX_OFF:
2493                         case HWTSTAMP_TX_ON:
2494                                 break;
2495                         default:
2496                                 return -ERANGE;
2497                         }
2498
2499                         switch (pi->tstamp_config.rx_filter) {
2500                         case HWTSTAMP_FILTER_NONE:
2501                                 pi->rxtstamp = false;
2502                                 break;
2503                         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2504                         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2505                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2506                                                          PTP_TS_L4);
2507                                 break;
2508                         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2509                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2510                                                          PTP_TS_L2_L4);
2511                                 break;
2512                         case HWTSTAMP_FILTER_ALL:
2513                         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2514                         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2515                         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2516                         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2517                                 pi->rxtstamp = true;
2518                                 break;
2519                         default:
2520                                 pi->tstamp_config.rx_filter =
2521                                         HWTSTAMP_FILTER_NONE;
2522                                 return -ERANGE;
2523                         }
2524
2525                         if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2526                             (pi->tstamp_config.rx_filter ==
2527                                 HWTSTAMP_FILTER_NONE)) {
2528                                 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2529                                         pi->ptp_enable = false;
2530                         }
2531
2532                         if (pi->tstamp_config.rx_filter !=
2533                                 HWTSTAMP_FILTER_NONE) {
2534                                 if (cxgb4_ptp_redirect_rx_packet(adapter,
2535                                                                  pi) >= 0)
2536                                         pi->ptp_enable = true;
2537                         }
2538                 } else {
2539                         /* For T4 Adapters */
2540                         switch (pi->tstamp_config.rx_filter) {
2541                         case HWTSTAMP_FILTER_NONE:
2542                         pi->rxtstamp = false;
2543                         break;
2544                         case HWTSTAMP_FILTER_ALL:
2545                         pi->rxtstamp = true;
2546                         break;
2547                         default:
2548                         pi->tstamp_config.rx_filter =
2549                         HWTSTAMP_FILTER_NONE;
2550                         return -ERANGE;
2551                         }
2552                 }
2553                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2554                                     sizeof(pi->tstamp_config)) ?
2555                         -EFAULT : 0;
2556         default:
2557                 return -EOPNOTSUPP;
2558         }
2559         return ret;
2560 }
2561
2562 static void cxgb_set_rxmode(struct net_device *dev)
2563 {
2564         /* unfortunately we can't return errors to the stack */
2565         set_rxmode(dev, -1, false);
2566 }
2567
2568 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2569 {
2570         int ret;
2571         struct port_info *pi = netdev_priv(dev);
2572
2573         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2574                             -1, -1, -1, true);
2575         if (!ret)
2576                 dev->mtu = new_mtu;
2577         return ret;
2578 }
2579
2580 #ifdef CONFIG_PCI_IOV
2581 static int dummy_open(struct net_device *dev)
2582 {
2583         /* Turn carrier off since we don't have to transmit anything on this
2584          * interface.
2585          */
2586         netif_carrier_off(dev);
2587         return 0;
2588 }
2589
2590 /* Fill MAC address that will be assigned by the FW */
2591 static void fill_vf_station_mac_addr(struct adapter *adap)
2592 {
2593         unsigned int i;
2594         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2595         int err;
2596         u8 *na;
2597         u16 a, b;
2598
2599         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2600         if (!err) {
2601                 na = adap->params.vpd.na;
2602                 for (i = 0; i < ETH_ALEN; i++)
2603                         hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2604                                       hex2val(na[2 * i + 1]));
2605                 a = (hw_addr[0] << 8) | hw_addr[1];
2606                 b = (hw_addr[1] << 8) | hw_addr[2];
2607                 a ^= b;
2608                 a |= 0x0200;    /* locally assigned Ethernet MAC address */
2609                 a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2610                 macaddr[0] = a >> 8;
2611                 macaddr[1] = a & 0xff;
2612
2613                 for (i = 2; i < 5; i++)
2614                         macaddr[i] = hw_addr[i + 1];
2615
2616                 for (i = 0; i < adap->num_vfs; i++) {
2617                         macaddr[5] = adap->pf * 16 + i;
2618                         ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr);
2619                 }
2620         }
2621 }
2622
2623 static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2624 {
2625         struct port_info *pi = netdev_priv(dev);
2626         struct adapter *adap = pi->adapter;
2627         int ret;
2628
2629         /* verify MAC addr is valid */
2630         if (!is_valid_ether_addr(mac)) {
2631                 dev_err(pi->adapter->pdev_dev,
2632                         "Invalid Ethernet address %pM for VF %d\n",
2633                         mac, vf);
2634                 return -EINVAL;
2635         }
2636
2637         dev_info(pi->adapter->pdev_dev,
2638                  "Setting MAC %pM on VF %d\n", mac, vf);
2639         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2640         if (!ret)
2641                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2642         return ret;
2643 }
2644
2645 static int cxgb_get_vf_config(struct net_device *dev,
2646                               int vf, struct ifla_vf_info *ivi)
2647 {
2648         struct port_info *pi = netdev_priv(dev);
2649         struct adapter *adap = pi->adapter;
2650
2651         if (vf >= adap->num_vfs)
2652                 return -EINVAL;
2653         ivi->vf = vf;
2654         ivi->max_tx_rate = adap->vfinfo[vf].tx_rate;
2655         ivi->min_tx_rate = 0;
2656         ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr);
2657         return 0;
2658 }
2659
2660 static int cxgb_get_phys_port_id(struct net_device *dev,
2661                                  struct netdev_phys_item_id *ppid)
2662 {
2663         struct port_info *pi = netdev_priv(dev);
2664         unsigned int phy_port_id;
2665
2666         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2667         ppid->id_len = sizeof(phy_port_id);
2668         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2669         return 0;
2670 }
2671
2672 static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2673                             int max_tx_rate)
2674 {
2675         struct port_info *pi = netdev_priv(dev);
2676         struct adapter *adap = pi->adapter;
2677         unsigned int link_ok, speed, mtu;
2678         u32 fw_pfvf, fw_class;
2679         int class_id = vf;
2680         int ret;
2681         u16 pktsize;
2682
2683         if (vf >= adap->num_vfs)
2684                 return -EINVAL;
2685
2686         if (min_tx_rate) {
2687                 dev_err(adap->pdev_dev,
2688                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2689                         min_tx_rate, vf);
2690                 return -EINVAL;
2691         }
2692
2693         ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2694         if (ret != FW_SUCCESS) {
2695                 dev_err(adap->pdev_dev,
2696                         "Failed to get link information for VF %d\n", vf);
2697                 return -EINVAL;
2698         }
2699
2700         if (!link_ok) {
2701                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2702                 return -EINVAL;
2703         }
2704
2705         if (max_tx_rate > speed) {
2706                 dev_err(adap->pdev_dev,
2707                         "Max tx rate %d for VF %d can't be > link-speed %u",
2708                         max_tx_rate, vf, speed);
2709                 return -EINVAL;
2710         }
2711
2712         pktsize = mtu;
2713         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2714         pktsize = pktsize - sizeof(struct ethhdr) - 4;
2715         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2716         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2717         /* configure Traffic Class for rate-limiting */
2718         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2719                               SCHED_CLASS_LEVEL_CL_RL,
2720                               SCHED_CLASS_MODE_CLASS,
2721                               SCHED_CLASS_RATEUNIT_BITS,
2722                               SCHED_CLASS_RATEMODE_ABS,
2723                               pi->tx_chan, class_id, 0,
2724                               max_tx_rate * 1000, 0, pktsize);
2725         if (ret) {
2726                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2727                         ret);
2728                 return -EINVAL;
2729         }
2730         dev_info(adap->pdev_dev,
2731                  "Class %d with MSS %u configured with rate %u\n",
2732                  class_id, pktsize, max_tx_rate);
2733
2734         /* bind VF to configured Traffic Class */
2735         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2736                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2737         fw_class = class_id;
2738         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2739                             &fw_class);
2740         if (ret) {
2741                 dev_err(adap->pdev_dev,
2742                         "Err %d in binding VF %d to Traffic Class %d\n",
2743                         ret, vf, class_id);
2744                 return -EINVAL;
2745         }
2746         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2747                  adap->pf, vf, class_id);
2748         adap->vfinfo[vf].tx_rate = max_tx_rate;
2749         return 0;
2750 }
2751
2752 #endif
2753
2754 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2755 {
2756         int ret;
2757         struct sockaddr *addr = p;
2758         struct port_info *pi = netdev_priv(dev);
2759
2760         if (!is_valid_ether_addr(addr->sa_data))
2761                 return -EADDRNOTAVAIL;
2762
2763         ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
2764                             pi->xact_addr_filt, addr->sa_data, true, true);
2765         if (ret < 0)
2766                 return ret;
2767
2768         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2769         pi->xact_addr_filt = ret;
2770         return 0;
2771 }
2772
2773 #ifdef CONFIG_NET_POLL_CONTROLLER
2774 static void cxgb_netpoll(struct net_device *dev)
2775 {
2776         struct port_info *pi = netdev_priv(dev);
2777         struct adapter *adap = pi->adapter;
2778
2779         if (adap->flags & USING_MSIX) {
2780                 int i;
2781                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2782
2783                 for (i = pi->nqsets; i; i--, rx++)
2784                         t4_sge_intr_msix(0, &rx->rspq);
2785         } else
2786                 t4_intr_handler(adap)(0, adap);
2787 }
2788 #endif
2789
2790 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2791 {
2792         struct port_info *pi = netdev_priv(dev);
2793         struct adapter *adap = pi->adapter;
2794         struct sched_class *e;
2795         struct ch_sched_params p;
2796         struct ch_sched_queue qe;
2797         u32 req_rate;
2798         int err = 0;
2799
2800         if (!can_sched(dev))
2801                 return -ENOTSUPP;
2802
2803         if (index < 0 || index > pi->nqsets - 1)
2804                 return -EINVAL;
2805
2806         if (!(adap->flags & FULL_INIT_DONE)) {
2807                 dev_err(adap->pdev_dev,
2808                         "Failed to rate limit on queue %d. Link Down?\n",
2809                         index);
2810                 return -EINVAL;
2811         }
2812
2813         /* Convert from Mbps to Kbps */
2814         req_rate = rate << 10;
2815
2816         /* Max rate is 10 Gbps */
2817         if (req_rate >= SCHED_MAX_RATE_KBPS) {
2818                 dev_err(adap->pdev_dev,
2819                         "Invalid rate %u Mbps, Max rate is %u Gbps\n",
2820                         rate, SCHED_MAX_RATE_KBPS);
2821                 return -ERANGE;
2822         }
2823
2824         /* First unbind the queue from any existing class */
2825         memset(&qe, 0, sizeof(qe));
2826         qe.queue = index;
2827         qe.class = SCHED_CLS_NONE;
2828
2829         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
2830         if (err) {
2831                 dev_err(adap->pdev_dev,
2832                         "Unbinding Queue %d on port %d fail. Err: %d\n",
2833                         index, pi->port_id, err);
2834                 return err;
2835         }
2836
2837         /* Queue already unbound */
2838         if (!req_rate)
2839                 return 0;
2840
2841         /* Fetch any available unused or matching scheduling class */
2842         memset(&p, 0, sizeof(p));
2843         p.type = SCHED_CLASS_TYPE_PACKET;
2844         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
2845         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
2846         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
2847         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
2848         p.u.params.channel  = pi->tx_chan;
2849         p.u.params.class    = SCHED_CLS_NONE;
2850         p.u.params.minrate  = 0;
2851         p.u.params.maxrate  = req_rate;
2852         p.u.params.weight   = 0;
2853         p.u.params.pktsize  = dev->mtu;
2854
2855         e = cxgb4_sched_class_alloc(dev, &p);
2856         if (!e)
2857                 return -ENOMEM;
2858
2859         /* Bind the queue to a scheduling class */
2860         memset(&qe, 0, sizeof(qe));
2861         qe.queue = index;
2862         qe.class = e->idx;
2863
2864         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
2865         if (err)
2866                 dev_err(adap->pdev_dev,
2867                         "Queue rate limiting failed. Err: %d\n", err);
2868         return err;
2869 }
2870
2871 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
2872                                  struct tc_cls_u32_offload *cls_u32)
2873 {
2874         if (!is_classid_clsact_ingress(cls_u32->common.classid) ||
2875             cls_u32->common.chain_index)
2876                 return -EOPNOTSUPP;
2877
2878         switch (cls_u32->command) {
2879         case TC_CLSU32_NEW_KNODE:
2880         case TC_CLSU32_REPLACE_KNODE:
2881                 return cxgb4_config_knode(dev, cls_u32);
2882         case TC_CLSU32_DELETE_KNODE:
2883                 return cxgb4_delete_knode(dev, cls_u32);
2884         default:
2885                 return -EOPNOTSUPP;
2886         }
2887 }
2888
2889 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2890                          void *type_data)
2891 {
2892         struct port_info *pi = netdev2pinfo(dev);
2893         struct adapter *adap = netdev2adap(dev);
2894
2895         if (!(adap->flags & FULL_INIT_DONE)) {
2896                 dev_err(adap->pdev_dev,
2897                         "Failed to setup tc on port %d. Link Down?\n",
2898                         pi->port_id);
2899                 return -EINVAL;
2900         }
2901
2902         switch (type) {
2903         case TC_SETUP_CLSU32:
2904                 return cxgb_setup_tc_cls_u32(dev, type_data);
2905         default:
2906                 return -EOPNOTSUPP;
2907         }
2908 }
2909
2910 static netdev_features_t cxgb_fix_features(struct net_device *dev,
2911                                            netdev_features_t features)
2912 {
2913         /* Disable GRO, if RX_CSUM is disabled */
2914         if (!(features & NETIF_F_RXCSUM))
2915                 features &= ~NETIF_F_GRO;
2916
2917         return features;
2918 }
2919
2920 static const struct net_device_ops cxgb4_netdev_ops = {
2921         .ndo_open             = cxgb_open,
2922         .ndo_stop             = cxgb_close,
2923         .ndo_start_xmit       = t4_eth_xmit,
2924         .ndo_select_queue     = cxgb_select_queue,
2925         .ndo_get_stats64      = cxgb_get_stats,
2926         .ndo_set_rx_mode      = cxgb_set_rxmode,
2927         .ndo_set_mac_address  = cxgb_set_mac_addr,
2928         .ndo_set_features     = cxgb_set_features,
2929         .ndo_validate_addr    = eth_validate_addr,
2930         .ndo_do_ioctl         = cxgb_ioctl,
2931         .ndo_change_mtu       = cxgb_change_mtu,
2932 #ifdef CONFIG_NET_POLL_CONTROLLER
2933         .ndo_poll_controller  = cxgb_netpoll,
2934 #endif
2935 #ifdef CONFIG_CHELSIO_T4_FCOE
2936         .ndo_fcoe_enable      = cxgb_fcoe_enable,
2937         .ndo_fcoe_disable     = cxgb_fcoe_disable,
2938 #endif /* CONFIG_CHELSIO_T4_FCOE */
2939         .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
2940         .ndo_setup_tc         = cxgb_setup_tc,
2941         .ndo_fix_features     = cxgb_fix_features,
2942 };
2943
2944 #ifdef CONFIG_PCI_IOV
2945 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
2946         .ndo_open             = dummy_open,
2947         .ndo_set_vf_mac       = cxgb_set_vf_mac,
2948         .ndo_get_vf_config    = cxgb_get_vf_config,
2949         .ndo_set_vf_rate      = cxgb_set_vf_rate,
2950         .ndo_get_phys_port_id = cxgb_get_phys_port_id,
2951 };
2952 #endif
2953
2954 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2955 {
2956         struct adapter *adapter = netdev2adap(dev);
2957
2958         strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
2959         strlcpy(info->version, cxgb4_driver_version,
2960                 sizeof(info->version));
2961         strlcpy(info->bus_info, pci_name(adapter->pdev),
2962                 sizeof(info->bus_info));
2963 }
2964
2965 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
2966         .get_drvinfo       = get_drvinfo,
2967 };
2968
2969 void t4_fatal_err(struct adapter *adap)
2970 {
2971         int port;
2972
2973         if (pci_channel_offline(adap->pdev))
2974                 return;
2975
2976         /* Disable the SGE since ULDs are going to free resources that
2977          * could be exposed to the adapter.  RDMA MWs for example...
2978          */
2979         t4_shutdown_adapter(adap);
2980         for_each_port(adap, port) {
2981                 struct net_device *dev = adap->port[port];
2982
2983                 /* If we get here in very early initialization the network
2984                  * devices may not have been set up yet.
2985                  */
2986                 if (!dev)
2987                         continue;
2988
2989                 netif_tx_stop_all_queues(dev);
2990                 netif_carrier_off(dev);
2991         }
2992         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
2993 }
2994
2995 static void setup_memwin(struct adapter *adap)
2996 {
2997         u32 nic_win_base = t4_get_util_window(adap);
2998
2999         t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3000 }
3001
3002 static void setup_memwin_rdma(struct adapter *adap)
3003 {
3004         if (adap->vres.ocq.size) {
3005                 u32 start;
3006                 unsigned int sz_kb;
3007
3008                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3009                 start &= PCI_BASE_ADDRESS_MEM_MASK;
3010                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3011                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3012                 t4_write_reg(adap,
3013                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3014                              start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3015                 t4_write_reg(adap,
3016                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3017                              adap->vres.ocq.start);
3018                 t4_read_reg(adap,
3019                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3020         }
3021 }
3022
3023 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3024 {
3025         u32 v;
3026         int ret;
3027
3028         /* get device capabilities */
3029         memset(c, 0, sizeof(*c));
3030         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3031                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
3032         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3033         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3034         if (ret < 0)
3035                 return ret;
3036
3037         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3038                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3039         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3040         if (ret < 0)
3041                 return ret;
3042
3043         ret = t4_config_glbl_rss(adap, adap->pf,
3044                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3045                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3046                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3047         if (ret < 0)
3048                 return ret;
3049
3050         ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3051                           MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3052                           FW_CMD_CAP_PF);
3053         if (ret < 0)
3054                 return ret;
3055
3056         t4_sge_init(adap);
3057
3058         /* tweak some settings */
3059         t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3060         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3061         t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3062         v = t4_read_reg(adap, TP_PIO_DATA_A);
3063         t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3064
3065         /* first 4 Tx modulation queues point to consecutive Tx channels */
3066         adap->params.tp.tx_modq_map = 0xE4;
3067         t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3068                      TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3069
3070         /* associate each Tx modulation queue with consecutive Tx channels */
3071         v = 0x84218421;
3072         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3073                           &v, 1, TP_TX_SCHED_HDR_A);
3074         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3075                           &v, 1, TP_TX_SCHED_FIFO_A);
3076         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3077                           &v, 1, TP_TX_SCHED_PCMD_A);
3078
3079 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3080         if (is_offload(adap)) {
3081                 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3082                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3083                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3084                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3085                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3086                 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3087                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3088                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3089                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3090                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3091         }
3092
3093         /* get basic stuff going */
3094         return t4_early_init(adap, adap->pf);
3095 }
3096
3097 /*
3098  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
3099  */
3100 #define MAX_ATIDS 8192U
3101
3102 /*
3103  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3104  *
3105  * If the firmware we're dealing with has Configuration File support, then
3106  * we use that to perform all configuration
3107  */
3108
3109 /*
3110  * Tweak configuration based on module parameters, etc.  Most of these have
3111  * defaults assigned to them by Firmware Configuration Files (if we're using
3112  * them) but need to be explicitly set if we're using hard-coded
3113  * initialization.  But even in the case of using Firmware Configuration
3114  * Files, we'd like to expose the ability to change these via module
3115  * parameters so these are essentially common tweaks/settings for
3116  * Configuration Files and hard-coded initialization ...
3117  */
3118 static int adap_init0_tweaks(struct adapter *adapter)
3119 {
3120         /*
3121          * Fix up various Host-Dependent Parameters like Page Size, Cache
3122          * Line Size, etc.  The firmware default is for a 4KB Page Size and
3123          * 64B Cache Line Size ...
3124          */
3125         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3126
3127         /*
3128          * Process module parameters which affect early initialization.
3129          */
3130         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3131                 dev_err(&adapter->pdev->dev,
3132                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
3133                         rx_dma_offset);
3134                 rx_dma_offset = 2;
3135         }
3136         t4_set_reg_field(adapter, SGE_CONTROL_A,
3137                          PKTSHIFT_V(PKTSHIFT_M),
3138                          PKTSHIFT_V(rx_dma_offset));
3139
3140         /*
3141          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3142          * adds the pseudo header itself.
3143          */
3144         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3145                                CSUM_HAS_PSEUDO_HDR_F, 0);
3146
3147         return 0;
3148 }
3149
3150 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3151  * unto themselves and they contain their own firmware to perform their
3152  * tasks ...
3153  */
3154 static int phy_aq1202_version(const u8 *phy_fw_data,
3155                               size_t phy_fw_size)
3156 {
3157         int offset;
3158
3159         /* At offset 0x8 you're looking for the primary image's
3160          * starting offset which is 3 Bytes wide
3161          *
3162          * At offset 0xa of the primary image, you look for the offset
3163          * of the DRAM segment which is 3 Bytes wide.
3164          *
3165          * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3166          * wide
3167          */
3168         #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3169         #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3170         #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3171
3172         offset = le24(phy_fw_data + 0x8) << 12;
3173         offset = le24(phy_fw_data + offset + 0xa);
3174         return be16(phy_fw_data + offset + 0x27e);
3175
3176         #undef be16
3177         #undef le16
3178         #undef le24
3179 }
3180
3181 static struct info_10gbt_phy_fw {
3182         unsigned int phy_fw_id;         /* PCI Device ID */
3183         char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
3184         int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3185         int phy_flash;                  /* Has FLASH for PHY Firmware */
3186 } phy_info_array[] = {
3187         {
3188                 PHY_AQ1202_DEVICEID,
3189                 PHY_AQ1202_FIRMWARE,
3190                 phy_aq1202_version,
3191                 1,
3192         },
3193         {
3194                 PHY_BCM84834_DEVICEID,
3195                 PHY_BCM84834_FIRMWARE,
3196                 NULL,
3197                 0,
3198         },
3199         { 0, NULL, NULL },
3200 };
3201
3202 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3203 {
3204         int i;
3205
3206         for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3207                 if (phy_info_array[i].phy_fw_id == devid)
3208                         return &phy_info_array[i];
3209         }
3210         return NULL;
3211 }
3212
3213 /* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
3214  * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD.  On error
3215  * we return a negative error number.  If we transfer new firmware we return 1
3216  * (from t4_load_phy_fw()).  If we don't do anything we return 0.
3217  */
3218 static int adap_init0_phy(struct adapter *adap)
3219 {
3220         const struct firmware *phyf;
3221         int ret;
3222         struct info_10gbt_phy_fw *phy_info;
3223
3224         /* Use the device ID to determine which PHY file to flash.
3225          */
3226         phy_info = find_phy_info(adap->pdev->device);
3227         if (!phy_info) {
3228                 dev_warn(adap->pdev_dev,
3229                          "No PHY Firmware file found for this PHY\n");
3230                 return -EOPNOTSUPP;
3231         }
3232
3233         /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3234          * use that. The adapter firmware provides us with a memory buffer
3235          * where we can load a PHY firmware file from the host if we want to
3236          * override the PHY firmware File in flash.
3237          */
3238         ret = reject_firmware_direct(&phyf, phy_info->phy_fw_file,
3239                                       adap->pdev_dev);
3240         if (ret < 0) {
3241                 /* For adapters without FLASH attached to PHY for their
3242                  * firmware, it's obviously a fatal error if we can't get the
3243                  * firmware to the adapter.  For adapters with PHY firmware
3244                  * FLASH storage, it's worth a warning if we can't find the
3245                  * PHY Firmware but we'll neuter the error ...
3246                  */
3247                 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3248                         "/lib/firmware/%s, error %d\n",
3249                         phy_info->phy_fw_file, -ret);
3250                 if (phy_info->phy_flash) {
3251                         int cur_phy_fw_ver = 0;
3252
3253                         t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3254                         dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3255                                  "FLASH copy, version %#x\n", cur_phy_fw_ver);
3256                         ret = 0;
3257                 }
3258
3259                 return ret;
3260         }
3261
3262         /* Load PHY Firmware onto adapter.
3263          */
3264         ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3265                              phy_info->phy_fw_version,
3266                              (u8 *)phyf->data, phyf->size);
3267         if (ret < 0)
3268                 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3269                         -ret);
3270         else if (ret > 0) {
3271                 int new_phy_fw_ver = 0;
3272
3273                 if (phy_info->phy_fw_version)
3274                         new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3275                                                                   phyf->size);
3276                 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3277                          "Firmware /lib/firmware/%s, version %#x\n",
3278                          phy_info->phy_fw_file, new_phy_fw_ver);
3279         }
3280
3281         release_firmware(phyf);
3282
3283         return ret;
3284 }
3285
3286 /*
3287  * Attempt to initialize the adapter via a Firmware Configuration File.
3288  */
3289 static int adap_init0_config(struct adapter *adapter, int reset)
3290 {
3291         struct fw_caps_config_cmd caps_cmd;
3292         const struct firmware *cf;
3293         unsigned long mtype = 0, maddr = 0;
3294         u32 finiver, finicsum, cfcsum;
3295         int ret;
3296         int config_issued = 0;
3297         char *fw_config_file, fw_config_file_path[256];
3298         char *config_name = NULL;
3299
3300         /*
3301          * Reset device if necessary.
3302          */
3303         if (reset) {
3304                 ret = t4_fw_reset(adapter, adapter->mbox,
3305                                   PIORSTMODE_F | PIORST_F);
3306                 if (ret < 0)
3307                         goto bye;
3308         }
3309
3310         /* If this is a 10Gb/s-BT adapter make sure the chip-external
3311          * 10Gb/s-BT PHYs have up-to-date firmware.  Note that this step needs
3312          * to be performed after any global adapter RESET above since some
3313          * PHYs only have local RAM copies of the PHY firmware.
3314          */
3315         if (is_10gbt_device(adapter->pdev->device)) {
3316                 ret = adap_init0_phy(adapter);
3317                 if (ret < 0)
3318                         goto bye;
3319         }
3320         /*
3321          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3322          * then use that.  Otherwise, use the configuration file stored
3323          * in the adapter flash ...
3324          */
3325         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3326         case CHELSIO_T4:
3327                 fw_config_file = FW4_CFNAME;
3328                 break;
3329         case CHELSIO_T5:
3330                 fw_config_file = FW5_CFNAME;
3331                 break;
3332         case CHELSIO_T6:
3333                 fw_config_file = FW6_CFNAME;
3334                 break;
3335         default:
3336                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3337                        adapter->pdev->device);
3338                 ret = -EINVAL;
3339                 goto bye;
3340         }
3341
3342         ret = reject_firmware(&cf, fw_config_file, adapter->pdev_dev);
3343         if (ret < 0) {
3344                 config_name = "On FLASH";
3345                 mtype = FW_MEMTYPE_CF_FLASH;
3346                 maddr = t4_flash_cfg_addr(adapter);
3347         } else {
3348                 u32 params[7], val[7];
3349
3350                 sprintf(fw_config_file_path,
3351                         "/lib/firmware/%s", fw_config_file);
3352                 config_name = fw_config_file_path;
3353
3354                 if (cf->size >= FLASH_CFG_MAX_SIZE)
3355                         ret = -ENOMEM;
3356                 else {
3357                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3358                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3359                         ret = t4_query_params(adapter, adapter->mbox,
3360                                               adapter->pf, 0, 1, params, val);
3361                         if (ret == 0) {
3362                                 /*
3363                                  * For t4_memory_rw() below addresses and
3364                                  * sizes have to be in terms of multiples of 4
3365                                  * bytes.  So, if the Configuration File isn't
3366                                  * a multiple of 4 bytes in length we'll have
3367                                  * to write that out separately since we can't
3368                                  * guarantee that the bytes following the
3369                                  * residual byte in the buffer returned by
3370                                  * reject_firmware() are zeroed out ...
3371                                  */
3372                                 size_t resid = cf->size & 0x3;
3373                                 size_t size = cf->size & ~0x3;
3374                                 __be32 *data = (__be32 *)cf->data;
3375
3376                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3377                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3378
3379                                 spin_lock(&adapter->win0_lock);
3380                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3381                                                    size, data, T4_MEMORY_WRITE);
3382                                 if (ret == 0 && resid != 0) {
3383                                         union {
3384                                                 __be32 word;
3385                                                 char buf[4];
3386                                         } last;
3387                                         int i;
3388
3389                                         last.word = data[size >> 2];
3390                                         for (i = resid; i < 4; i++)
3391                                                 last.buf[i] = 0;
3392                                         ret = t4_memory_rw(adapter, 0, mtype,
3393                                                            maddr + size,
3394                                                            4, &last.word,
3395                                                            T4_MEMORY_WRITE);
3396                                 }
3397                                 spin_unlock(&adapter->win0_lock);
3398                         }
3399                 }
3400
3401                 release_firmware(cf);
3402                 if (ret)
3403                         goto bye;
3404         }
3405
3406         /*
3407          * Issue a Capability Configuration command to the firmware to get it
3408          * to parse the Configuration File.  We don't use t4_fw_config_file()
3409          * because we want the ability to modify various features after we've
3410          * processed the configuration file ...
3411          */
3412         memset(&caps_cmd, 0, sizeof(caps_cmd));
3413         caps_cmd.op_to_write =
3414                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3415                       FW_CMD_REQUEST_F |
3416                       FW_CMD_READ_F);
3417         caps_cmd.cfvalid_to_len16 =
3418                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3419                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3420                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3421                       FW_LEN16(caps_cmd));
3422         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3423                          &caps_cmd);
3424
3425         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3426          * Configuration File in FLASH), our last gasp effort is to use the
3427          * Firmware Configuration File which is embedded in the firmware.  A
3428          * very few early versions of the firmware didn't have one embedded
3429          * but we can ignore those.
3430          */
3431         if (ret == -ENOENT) {
3432                 memset(&caps_cmd, 0, sizeof(caps_cmd));
3433                 caps_cmd.op_to_write =
3434                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3435                                         FW_CMD_REQUEST_F |
3436                                         FW_CMD_READ_F);
3437                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3438                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3439                                 sizeof(caps_cmd), &caps_cmd);
3440                 config_name = "Firmware Default";
3441         }
3442
3443         config_issued = 1;
3444         if (ret < 0)
3445                 goto bye;
3446
3447         finiver = ntohl(caps_cmd.finiver);
3448         finicsum = ntohl(caps_cmd.finicsum);
3449         cfcsum = ntohl(caps_cmd.cfcsum);
3450         if (finicsum != cfcsum)
3451                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3452                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3453                          finicsum, cfcsum);
3454
3455         /*
3456          * And now tell the firmware to use the configuration we just loaded.
3457          */
3458         caps_cmd.op_to_write =
3459                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3460                       FW_CMD_REQUEST_F |
3461                       FW_CMD_WRITE_F);
3462         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3463         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3464                          NULL);
3465         if (ret < 0)
3466                 goto bye;
3467
3468         /*
3469          * Tweak configuration based on system architecture, module
3470          * parameters, etc.
3471          */
3472         ret = adap_init0_tweaks(adapter);
3473         if (ret < 0)
3474                 goto bye;
3475
3476         /*
3477          * And finally tell the firmware to initialize itself using the
3478          * parameters from the Configuration File.
3479          */
3480         ret = t4_fw_initialize(adapter, adapter->mbox);
3481         if (ret < 0)
3482                 goto bye;
3483
3484         /* Emit Firmware Configuration File information and return
3485          * successfully.
3486          */
3487         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3488                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3489                  config_name, finiver, cfcsum);
3490         return 0;
3491
3492         /*
3493          * Something bad happened.  Return the error ...  (If the "error"
3494          * is that there's no Configuration File on the adapter we don't
3495          * want to issue a warning since this is fairly common.)
3496          */
3497 bye:
3498         if (config_issued && ret != -ENOENT)
3499                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3500                          config_name, -ret);
3501         return ret;
3502 }
3503
3504 static struct fw_info fw_info_array[] = {
3505         {
3506                 .chip = CHELSIO_T4,
3507                 .fs_name = FW4_CFNAME,
3508                 .fw_mod_name = FW4_FNAME,
3509                 .fw_hdr = {
3510                         .chip = FW_HDR_CHIP_T4,
3511                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3512                         .intfver_nic = FW_INTFVER(T4, NIC),
3513                         .intfver_vnic = FW_INTFVER(T4, VNIC),
3514                         .intfver_ri = FW_INTFVER(T4, RI),
3515                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3516                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
3517                 },
3518         }, {
3519                 .chip = CHELSIO_T5,
3520                 .fs_name = FW5_CFNAME,
3521                 .fw_mod_name = FW5_FNAME,
3522                 .fw_hdr = {
3523                         .chip = FW_HDR_CHIP_T5,
3524                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3525                         .intfver_nic = FW_INTFVER(T5, NIC),
3526                         .intfver_vnic = FW_INTFVER(T5, VNIC),
3527                         .intfver_ri = FW_INTFVER(T5, RI),
3528                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3529                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
3530                 },
3531         }, {
3532                 .chip = CHELSIO_T6,
3533                 .fs_name = FW6_CFNAME,
3534                 .fw_mod_name = FW6_FNAME,
3535                 .fw_hdr = {
3536                         .chip = FW_HDR_CHIP_T6,
3537                         .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3538                         .intfver_nic = FW_INTFVER(T6, NIC),
3539                         .intfver_vnic = FW_INTFVER(T6, VNIC),
3540                         .intfver_ofld = FW_INTFVER(T6, OFLD),
3541                         .intfver_ri = FW_INTFVER(T6, RI),
3542                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3543                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3544                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3545                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
3546                 },
3547         }
3548
3549 };
3550
3551 static struct fw_info *find_fw_info(int chip)
3552 {
3553         int i;
3554
3555         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3556                 if (fw_info_array[i].chip == chip)
3557                         return &fw_info_array[i];
3558         }
3559         return NULL;
3560 }
3561
3562 /*
3563  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3564  */
3565 static int adap_init0(struct adapter *adap)
3566 {
3567         int ret;
3568         u32 v, port_vec;
3569         enum dev_state state;
3570         u32 params[7], val[7];
3571         struct fw_caps_config_cmd caps_cmd;
3572         int reset = 1;
3573
3574         /* Grab Firmware Device Log parameters as early as possible so we have
3575          * access to it for debugging, etc.
3576          */
3577         ret = t4_init_devlog_params(adap);
3578         if (ret < 0)
3579                 return ret;
3580
3581         /* Contact FW, advertising Master capability */
3582         ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
3583                           is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
3584         if (ret < 0) {
3585                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3586                         ret);
3587                 return ret;
3588         }
3589         if (ret == adap->mbox)
3590                 adap->flags |= MASTER_PF;
3591
3592         /*
3593          * If we're the Master PF Driver and the device is uninitialized,
3594          * then let's consider upgrading the firmware ...  (We always want
3595          * to check the firmware version number in order to A. get it for
3596          * later reporting and B. to warn if the currently loaded firmware
3597          * is excessively mismatched relative to the driver.)
3598          */
3599
3600         t4_get_version_info(adap);
3601         ret = t4_check_fw_version(adap);
3602         /* If firmware is too old (not supported by driver) force an update. */
3603         if (ret)
3604                 state = DEV_STATE_UNINIT;
3605         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3606                 struct fw_info *fw_info;
3607                 struct fw_hdr *card_fw;
3608                 const struct firmware *fw;
3609                 const u8 *fw_data = NULL;
3610                 unsigned int fw_size = 0;
3611
3612                 /* This is the firmware whose headers the driver was compiled
3613                  * against
3614                  */
3615                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3616                 if (fw_info == NULL) {
3617                         dev_err(adap->pdev_dev,
3618                                 "unable to get firmware info for chip %d.\n",
3619                                 CHELSIO_CHIP_VERSION(adap->params.chip));
3620                         return -EINVAL;
3621                 }
3622
3623                 /* allocate memory to read the header of the firmware on the
3624                  * card
3625                  */
3626                 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
3627
3628                 /* Get FW from from /lib/firmware/ */
3629                 ret = reject_firmware(&fw, fw_info->fw_mod_name,
3630                                        adap->pdev_dev);
3631                 if (ret < 0) {
3632                         dev_err(adap->pdev_dev,
3633                                 "unable to load firmware image %s, error %d\n",
3634                                 fw_info->fw_mod_name, ret);
3635                 } else {
3636                         fw_data = fw->data;
3637                         fw_size = fw->size;
3638                 }
3639
3640                 /* upgrade FW logic */
3641                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3642                                  state, &reset);
3643
3644                 /* Cleaning up */
3645                 release_firmware(fw);
3646                 kvfree(card_fw);
3647
3648                 if (ret < 0)
3649                         goto bye;
3650         }
3651
3652         /*
3653          * Grab VPD parameters.  This should be done after we establish a
3654          * connection to the firmware since some of the VPD parameters
3655          * (notably the Core Clock frequency) are retrieved via requests to
3656          * the firmware.  On the other hand, we need these fairly early on
3657          * so we do this right after getting ahold of the firmware.
3658          */
3659         ret = t4_get_vpd_params(adap, &adap->params.vpd);
3660         if (ret < 0)
3661                 goto bye;
3662
3663         /*
3664          * Find out what ports are available to us.  Note that we need to do
3665          * this before calling adap_init0_no_config() since it needs nports
3666          * and portvec ...
3667          */
3668         v =
3669             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3670             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3671         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3672         if (ret < 0)
3673                 goto bye;
3674
3675         adap->params.nports = hweight32(port_vec);
3676         adap->params.portvec = port_vec;
3677
3678         /* If the firmware is initialized already, emit a simply note to that
3679          * effect. Otherwise, it's time to try initializing the adapter.
3680          */
3681         if (state == DEV_STATE_INIT) {
3682                 dev_info(adap->pdev_dev, "Coming up as %s: "\
3683                          "Adapter already initialized\n",
3684                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3685         } else {
3686                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3687                          "Initializing adapter\n");
3688
3689                 /* Find out whether we're dealing with a version of the
3690                  * firmware which has configuration file support.
3691                  */
3692                 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3693                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3694                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3695                                       params, val);
3696
3697                 /* If the firmware doesn't support Configuration Files,
3698                  * return an error.
3699                  */
3700                 if (ret < 0) {
3701                         dev_err(adap->pdev_dev, "firmware doesn't support "
3702                                 "Firmware Configuration Files\n");
3703                         goto bye;
3704                 }
3705
3706                 /* The firmware provides us with a memory buffer where we can
3707                  * load a Configuration File from the host if we want to
3708                  * override the Configuration File in flash.
3709                  */
3710                 ret = adap_init0_config(adap, reset);
3711                 if (ret == -ENOENT) {
3712                         dev_err(adap->pdev_dev, "no Configuration File "
3713                                 "present on adapter.\n");
3714                         goto bye;
3715                 }
3716                 if (ret < 0) {
3717                         dev_err(adap->pdev_dev, "could not initialize "
3718                                 "adapter, error %d\n", -ret);
3719                         goto bye;
3720                 }
3721         }
3722
3723         /* Give the SGE code a chance to pull in anything that it needs ...
3724          * Note that this must be called after we retrieve our VPD parameters
3725          * in order to know how to convert core ticks to seconds, etc.
3726          */
3727         ret = t4_sge_init(adap);
3728         if (ret < 0)
3729                 goto bye;
3730
3731         if (is_bypass_device(adap->pdev->device))
3732                 adap->params.bypass = 1;
3733
3734         /*
3735          * Grab some of our basic fundamental operating parameters.
3736          */
3737 #define FW_PARAM_DEV(param) \
3738         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3739         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3740
3741 #define FW_PARAM_PFVF(param) \
3742         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3743         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
3744         FW_PARAMS_PARAM_Y_V(0) | \
3745         FW_PARAMS_PARAM_Z_V(0)
3746
3747         params[0] = FW_PARAM_PFVF(EQ_START);
3748         params[1] = FW_PARAM_PFVF(L2T_START);
3749         params[2] = FW_PARAM_PFVF(L2T_END);
3750         params[3] = FW_PARAM_PFVF(FILTER_START);
3751         params[4] = FW_PARAM_PFVF(FILTER_END);
3752         params[5] = FW_PARAM_PFVF(IQFLINT_START);
3753         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3754         if (ret < 0)
3755                 goto bye;
3756         adap->sge.egr_start = val[0];
3757         adap->l2t_start = val[1];
3758         adap->l2t_end = val[2];
3759         adap->tids.ftid_base = val[3];
3760         adap->tids.nftids = val[4] - val[3] + 1;
3761         adap->sge.ingr_start = val[5];
3762
3763         /* qids (ingress/egress) returned from firmware can be anywhere
3764          * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3765          * Hence driver needs to allocate memory for this range to
3766          * store the queue info. Get the highest IQFLINT/EQ index returned
3767          * in FW_EQ_*_CMD.alloc command.
3768          */
3769         params[0] = FW_PARAM_PFVF(EQ_END);
3770         params[1] = FW_PARAM_PFVF(IQFLINT_END);
3771         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3772         if (ret < 0)
3773                 goto bye;
3774         adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3775         adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3776
3777         adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3778                                     sizeof(*adap->sge.egr_map), GFP_KERNEL);
3779         if (!adap->sge.egr_map) {
3780                 ret = -ENOMEM;
3781                 goto bye;
3782         }
3783
3784         adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3785                                      sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3786         if (!adap->sge.ingr_map) {
3787                 ret = -ENOMEM;
3788                 goto bye;
3789         }
3790
3791         /* Allocate the memory for the vaious egress queue bitmaps
3792          * ie starving_fl, txq_maperr and blocked_fl.
3793          */
3794         adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3795                                         sizeof(long), GFP_KERNEL);
3796         if (!adap->sge.starving_fl) {
3797                 ret = -ENOMEM;
3798                 goto bye;
3799         }
3800
3801         adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3802                                        sizeof(long), GFP_KERNEL);
3803         if (!adap->sge.txq_maperr) {
3804                 ret = -ENOMEM;
3805                 goto bye;
3806         }
3807
3808 #ifdef CONFIG_DEBUG_FS
3809         adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3810                                        sizeof(long), GFP_KERNEL);
3811         if (!adap->sge.blocked_fl) {
3812                 ret = -ENOMEM;
3813                 goto bye;
3814         }
3815 #endif
3816
3817         params[0] = FW_PARAM_PFVF(CLIP_START);
3818         params[1] = FW_PARAM_PFVF(CLIP_END);
3819         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3820         if (ret < 0)
3821                 goto bye;
3822         adap->clipt_start = val[0];
3823         adap->clipt_end = val[1];
3824
3825         /* We don't yet have a PARAMs calls to retrieve the number of Traffic
3826          * Classes supported by the hardware/firmware so we hard code it here
3827          * for now.
3828          */
3829         adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
3830
3831         /* query params related to active filter region */
3832         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3833         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3834         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3835         /* If Active filter size is set we enable establishing
3836          * offload connection through firmware work request
3837          */
3838         if ((val[0] != val[1]) && (ret >= 0)) {
3839                 adap->flags |= FW_OFLD_CONN;
3840                 adap->tids.aftid_base = val[0];
3841                 adap->tids.aftid_end = val[1];
3842         }
3843
3844         /* If we're running on newer firmware, let it know that we're
3845          * prepared to deal with encapsulated CPL messages.  Older
3846          * firmware won't understand this and we'll just get
3847          * unencapsulated messages ...
3848          */
3849         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3850         val[0] = 1;
3851         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3852
3853         /*
3854          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3855          * capability.  Earlier versions of the firmware didn't have the
3856          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3857          * permission to use ULPTX MEMWRITE DSGL.
3858          */
3859         if (is_t4(adap->params.chip)) {
3860                 adap->params.ulptx_memwrite_dsgl = false;
3861         } else {
3862                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3863                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3864                                       1, params, val);
3865                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3866         }
3867
3868         /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
3869         params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
3870         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3871                               1, params, val);
3872         adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
3873
3874         /*
3875          * Get device capabilities so we can determine what resources we need
3876          * to manage.
3877          */
3878         memset(&caps_cmd, 0, sizeof(caps_cmd));
3879         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3880                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
3881         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3882         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3883                          &caps_cmd);
3884         if (ret < 0)
3885                 goto bye;
3886
3887         if (caps_cmd.ofldcaps) {
3888                 /* query offload-related parameters */
3889                 params[0] = FW_PARAM_DEV(NTID);
3890                 params[1] = FW_PARAM_PFVF(SERVER_START);
3891                 params[2] = FW_PARAM_PFVF(SERVER_END);
3892                 params[3] = FW_PARAM_PFVF(TDDP_START);
3893                 params[4] = FW_PARAM_PFVF(TDDP_END);
3894                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3895                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3896                                       params, val);
3897                 if (ret < 0)
3898                         goto bye;
3899                 adap->tids.ntids = val[0];
3900                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3901                 adap->tids.stid_base = val[1];
3902                 adap->tids.nstids = val[2] - val[1] + 1;
3903                 /*
3904                  * Setup server filter region. Divide the available filter
3905                  * region into two parts. Regular filters get 1/3rd and server
3906                  * filters get 2/3rd part. This is only enabled if workarond
3907                  * path is enabled.
3908                  * 1. For regular filters.
3909                  * 2. Server filter: This are special filters which are used
3910                  * to redirect SYN packets to offload queue.
3911                  */
3912                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3913                         adap->tids.sftid_base = adap->tids.ftid_base +
3914                                         DIV_ROUND_UP(adap->tids.nftids, 3);
3915                         adap->tids.nsftids = adap->tids.nftids -
3916                                          DIV_ROUND_UP(adap->tids.nftids, 3);
3917                         adap->tids.nftids = adap->tids.sftid_base -
3918                                                 adap->tids.ftid_base;
3919                 }
3920                 adap->vres.ddp.start = val[3];
3921                 adap->vres.ddp.size = val[4] - val[3] + 1;
3922                 adap->params.ofldq_wr_cred = val[5];
3923
3924                 adap->params.offload = 1;
3925                 adap->num_ofld_uld += 1;
3926         }
3927         if (caps_cmd.rdmacaps) {
3928                 params[0] = FW_PARAM_PFVF(STAG_START);
3929                 params[1] = FW_PARAM_PFVF(STAG_END);
3930                 params[2] = FW_PARAM_PFVF(RQ_START);
3931                 params[3] = FW_PARAM_PFVF(RQ_END);
3932                 params[4] = FW_PARAM_PFVF(PBL_START);
3933                 params[5] = FW_PARAM_PFVF(PBL_END);
3934                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3935                                       params, val);
3936                 if (ret < 0)
3937                         goto bye;
3938                 adap->vres.stag.start = val[0];
3939                 adap->vres.stag.size = val[1] - val[0] + 1;
3940                 adap->vres.rq.start = val[2];
3941                 adap->vres.rq.size = val[3] - val[2] + 1;
3942                 adap->vres.pbl.start = val[4];
3943                 adap->vres.pbl.size = val[5] - val[4] + 1;
3944
3945                 params[0] = FW_PARAM_PFVF(SQRQ_START);
3946                 params[1] = FW_PARAM_PFVF(SQRQ_END);
3947                 params[2] = FW_PARAM_PFVF(CQ_START);
3948                 params[3] = FW_PARAM_PFVF(CQ_END);
3949                 params[4] = FW_PARAM_PFVF(OCQ_START);
3950                 params[5] = FW_PARAM_PFVF(OCQ_END);
3951                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
3952                                       val);
3953                 if (ret < 0)
3954                         goto bye;
3955                 adap->vres.qp.start = val[0];
3956                 adap->vres.qp.size = val[1] - val[0] + 1;
3957                 adap->vres.cq.start = val[2];
3958                 adap->vres.cq.size = val[3] - val[2] + 1;
3959                 adap->vres.ocq.start = val[4];
3960                 adap->vres.ocq.size = val[5] - val[4] + 1;
3961
3962                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3963                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3964                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
3965                                       val);
3966                 if (ret < 0) {
3967                         adap->params.max_ordird_qp = 8;
3968                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
3969                         ret = 0;
3970                 } else {
3971                         adap->params.max_ordird_qp = val[0];
3972                         adap->params.max_ird_adapter = val[1];
3973                 }
3974                 dev_info(adap->pdev_dev,
3975                          "max_ordird_qp %d max_ird_adapter %d\n",
3976                          adap->params.max_ordird_qp,
3977                          adap->params.max_ird_adapter);
3978                 adap->num_ofld_uld += 2;
3979         }
3980         if (caps_cmd.iscsicaps) {
3981                 params[0] = FW_PARAM_PFVF(ISCSI_START);
3982                 params[1] = FW_PARAM_PFVF(ISCSI_END);
3983                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
3984                                       params, val);
3985                 if (ret < 0)
3986                         goto bye;
3987                 adap->vres.iscsi.start = val[0];
3988                 adap->vres.iscsi.size = val[1] - val[0] + 1;
3989                 /* LIO target and cxgb4i initiaitor */
3990                 adap->num_ofld_uld += 2;
3991         }
3992         if (caps_cmd.cryptocaps) {
3993                 /* Should query params here...TODO */
3994                 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
3995                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
3996                                       params, val);
3997                 if (ret < 0) {
3998                         if (ret != -EINVAL)
3999                                 goto bye;
4000                 } else {
4001                         adap->vres.ncrypto_fc = val[0];
4002                 }
4003                 adap->params.crypto |= ULP_CRYPTO_LOOKASIDE;
4004                 adap->num_uld += 1;
4005         }
4006 #undef FW_PARAM_PFVF
4007 #undef FW_PARAM_DEV
4008
4009         /* The MTU/MSS Table is initialized by now, so load their values.  If
4010          * we're initializing the adapter, then we'll make any modifications
4011          * we want to the MTU/MSS Table and also initialize the congestion
4012          * parameters.
4013          */
4014         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4015         if (state != DEV_STATE_INIT) {
4016                 int i;
4017
4018                 /* The default MTU Table contains values 1492 and 1500.
4019                  * However, for TCP, it's better to have two values which are
4020                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4021                  * This allows us to have a TCP Data Payload which is a
4022                  * multiple of 8 regardless of what combination of TCP Options
4023                  * are in use (always a multiple of 4 bytes) which is
4024                  * important for performance reasons.  For instance, if no
4025                  * options are in use, then we have a 20-byte IP header and a
4026                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
4027                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4028                  * which is not a multiple of 8.  So using an MSS of 1488 in
4029                  * this case results in a TCP Data Payload of 1448 bytes which
4030                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
4031                  * Stamps have been negotiated, then an MTU of 1500 bytes
4032                  * results in a TCP Data Payload of 1448 bytes which, as
4033                  * above, is a multiple of 8 bytes ...
4034                  */
4035                 for (i = 0; i < NMTUS; i++)
4036                         if (adap->params.mtus[i] == 1492) {
4037                                 adap->params.mtus[i] = 1488;
4038                                 break;
4039                         }
4040
4041                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4042                              adap->params.b_wnd);
4043         }
4044         t4_init_sge_params(adap);
4045         adap->flags |= FW_OK;
4046         t4_init_tp_params(adap);
4047         return 0;
4048
4049         /*
4050          * Something bad happened.  If a command timed out or failed with EIO
4051          * FW does not operate within its spec or something catastrophic
4052          * happened to HW/FW, stop issuing commands.
4053          */
4054 bye:
4055         kfree(adap->sge.egr_map);
4056         kfree(adap->sge.ingr_map);
4057         kfree(adap->sge.starving_fl);
4058         kfree(adap->sge.txq_maperr);
4059 #ifdef CONFIG_DEBUG_FS
4060         kfree(adap->sge.blocked_fl);
4061 #endif
4062         if (ret != -ETIMEDOUT && ret != -EIO)
4063                 t4_fw_bye(adap, adap->mbox);
4064         return ret;
4065 }
4066
4067 /* EEH callbacks */
4068
4069 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4070                                          pci_channel_state_t state)
4071 {
4072         int i;
4073         struct adapter *adap = pci_get_drvdata(pdev);
4074
4075         if (!adap)
4076                 goto out;
4077
4078         rtnl_lock();
4079         adap->flags &= ~FW_OK;
4080         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4081         spin_lock(&adap->stats_lock);
4082         for_each_port(adap, i) {
4083                 struct net_device *dev = adap->port[i];
4084                 if (dev) {
4085                         netif_device_detach(dev);
4086                         netif_carrier_off(dev);
4087                 }
4088         }
4089         spin_unlock(&adap->stats_lock);
4090         disable_interrupts(adap);
4091         if (adap->flags & FULL_INIT_DONE)
4092                 cxgb_down(adap);
4093         rtnl_unlock();
4094         if ((adap->flags & DEV_ENABLED)) {
4095                 pci_disable_device(pdev);
4096                 adap->flags &= ~DEV_ENABLED;
4097         }
4098 out:    return state == pci_channel_io_perm_failure ?
4099                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4100 }
4101
4102 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4103 {
4104         int i, ret;
4105         struct fw_caps_config_cmd c;
4106         struct adapter *adap = pci_get_drvdata(pdev);
4107
4108         if (!adap) {
4109                 pci_restore_state(pdev);
4110                 pci_save_state(pdev);
4111                 return PCI_ERS_RESULT_RECOVERED;
4112         }
4113
4114         if (!(adap->flags & DEV_ENABLED)) {
4115                 if (pci_enable_device(pdev)) {
4116                         dev_err(&pdev->dev, "Cannot reenable PCI "
4117                                             "device after reset\n");
4118                         return PCI_ERS_RESULT_DISCONNECT;
4119                 }
4120                 adap->flags |= DEV_ENABLED;
4121         }
4122
4123         pci_set_master(pdev);
4124         pci_restore_state(pdev);
4125         pci_save_state(pdev);
4126         pci_cleanup_aer_uncorrect_error_status(pdev);
4127
4128         if (t4_wait_dev_ready(adap->regs) < 0)
4129                 return PCI_ERS_RESULT_DISCONNECT;
4130         if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4131                 return PCI_ERS_RESULT_DISCONNECT;
4132         adap->flags |= FW_OK;
4133         if (adap_init1(adap, &c))
4134                 return PCI_ERS_RESULT_DISCONNECT;
4135
4136         for_each_port(adap, i) {
4137                 struct port_info *p = adap2pinfo(adap, i);
4138
4139                 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4140                                   NULL, NULL);
4141                 if (ret < 0)
4142                         return PCI_ERS_RESULT_DISCONNECT;
4143                 p->viid = ret;
4144                 p->xact_addr_filt = -1;
4145         }
4146
4147         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4148                      adap->params.b_wnd);
4149         setup_memwin(adap);
4150         if (cxgb_up(adap))
4151                 return PCI_ERS_RESULT_DISCONNECT;
4152         return PCI_ERS_RESULT_RECOVERED;
4153 }
4154
4155 static void eeh_resume(struct pci_dev *pdev)
4156 {
4157         int i;
4158         struct adapter *adap = pci_get_drvdata(pdev);
4159
4160         if (!adap)
4161                 return;
4162
4163         rtnl_lock();
4164         for_each_port(adap, i) {
4165                 struct net_device *dev = adap->port[i];
4166                 if (dev) {
4167                         if (netif_running(dev)) {
4168                                 link_start(dev);
4169                                 cxgb_set_rxmode(dev);
4170                         }
4171                         netif_device_attach(dev);
4172                 }
4173         }
4174         rtnl_unlock();
4175 }
4176
4177 static const struct pci_error_handlers cxgb4_eeh = {
4178         .error_detected = eeh_err_detected,
4179         .slot_reset     = eeh_slot_reset,
4180         .resume         = eeh_resume,
4181 };
4182
4183 /* Return true if the Link Configuration supports "High Speeds" (those greater
4184  * than 1Gb/s).
4185  */
4186 static inline bool is_x_10g_port(const struct link_config *lc)
4187 {
4188         unsigned int speeds, high_speeds;
4189
4190         speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
4191         high_speeds = speeds &
4192                         ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
4193
4194         return high_speeds != 0;
4195 }
4196
4197 /*
4198  * Perform default configuration of DMA queues depending on the number and type
4199  * of ports we found and the number of available CPUs.  Most settings can be
4200  * modified by the admin prior to actual use.
4201  */
4202 static void cfg_queues(struct adapter *adap)
4203 {
4204         struct sge *s = &adap->sge;
4205         int i = 0, n10g = 0, qidx = 0;
4206 #ifndef CONFIG_CHELSIO_T4_DCB
4207         int q10g = 0;
4208 #endif
4209
4210         /* Reduce memory usage in kdump environment, disable all offload.
4211          */
4212         if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
4213                 adap->params.offload = 0;
4214                 adap->params.crypto = 0;
4215         }
4216
4217         n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4218 #ifdef CONFIG_CHELSIO_T4_DCB
4219         /* For Data Center Bridging support we need to be able to support up
4220          * to 8 Traffic Priorities; each of which will be assigned to its
4221          * own TX Queue in order to prevent Head-Of-Line Blocking.
4222          */
4223         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4224                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4225                         MAX_ETH_QSETS, adap->params.nports * 8);
4226                 BUG_ON(1);
4227         }
4228
4229         for_each_port(adap, i) {
4230                 struct port_info *pi = adap2pinfo(adap, i);
4231
4232                 pi->first_qset = qidx;
4233                 pi->nqsets = is_kdump_kernel() ? 1 : 8;
4234                 qidx += pi->nqsets;
4235         }
4236 #else /* !CONFIG_CHELSIO_T4_DCB */
4237         /*
4238          * We default to 1 queue per non-10G port and up to # of cores queues
4239          * per 10G port.
4240          */
4241         if (n10g)
4242                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4243         if (q10g > netif_get_num_default_rss_queues())
4244                 q10g = netif_get_num_default_rss_queues();
4245
4246         if (is_kdump_kernel())
4247                 q10g = 1;
4248
4249         for_each_port(adap, i) {
4250                 struct port_info *pi = adap2pinfo(adap, i);
4251
4252                 pi->first_qset = qidx;
4253                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4254                 qidx += pi->nqsets;
4255         }
4256 #endif /* !CONFIG_CHELSIO_T4_DCB */
4257
4258         s->ethqsets = qidx;
4259         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
4260
4261         if (is_uld(adap)) {
4262                 /*
4263                  * For offload we use 1 queue/channel if all ports are up to 1G,
4264                  * otherwise we divide all available queues amongst the channels
4265                  * capped by the number of available cores.
4266                  */
4267                 if (n10g) {
4268                         i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
4269                         s->ofldqsets = roundup(i, adap->params.nports);
4270                 } else {
4271                         s->ofldqsets = adap->params.nports;
4272                 }
4273         }
4274
4275         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4276                 struct sge_eth_rxq *r = &s->ethrxq[i];
4277
4278                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4279                 r->fl.size = 72;
4280         }
4281
4282         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4283                 s->ethtxq[i].q.size = 1024;
4284
4285         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4286                 s->ctrlq[i].q.size = 512;
4287
4288         if (!is_t4(adap->params.chip))
4289                 s->ptptxq.q.size = 8;
4290
4291         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4292         init_rspq(adap, &s->intrq, 0, 1, 512, 64);
4293 }
4294
4295 /*
4296  * Reduce the number of Ethernet queues across all ports to at most n.
4297  * n provides at least one queue per port.
4298  */
4299 static void reduce_ethqs(struct adapter *adap, int n)
4300 {
4301         int i;
4302         struct port_info *pi;
4303
4304         while (n < adap->sge.ethqsets)
4305                 for_each_port(adap, i) {
4306                         pi = adap2pinfo(adap, i);
4307                         if (pi->nqsets > 1) {
4308                                 pi->nqsets--;
4309                                 adap->sge.ethqsets--;
4310                                 if (adap->sge.ethqsets <= n)
4311                                         break;
4312                         }
4313                 }
4314
4315         n = 0;
4316         for_each_port(adap, i) {
4317                 pi = adap2pinfo(adap, i);
4318                 pi->first_qset = n;
4319                 n += pi->nqsets;
4320         }
4321 }
4322
4323 static int get_msix_info(struct adapter *adap)
4324 {
4325         struct uld_msix_info *msix_info;
4326         unsigned int max_ingq = 0;
4327
4328         if (is_offload(adap))
4329                 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
4330         if (is_pci_uld(adap))
4331                 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
4332
4333         if (!max_ingq)
4334                 goto out;
4335
4336         msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
4337         if (!msix_info)
4338                 return -ENOMEM;
4339
4340         adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
4341                                                  sizeof(long), GFP_KERNEL);
4342         if (!adap->msix_bmap_ulds.msix_bmap) {
4343                 kfree(msix_info);
4344                 return -ENOMEM;
4345         }
4346         spin_lock_init(&adap->msix_bmap_ulds.lock);
4347         adap->msix_info_ulds = msix_info;
4348 out:
4349         return 0;
4350 }
4351
4352 static void free_msix_info(struct adapter *adap)
4353 {
4354         if (!(adap->num_uld && adap->num_ofld_uld))
4355                 return;
4356
4357         kfree(adap->msix_info_ulds);
4358         kfree(adap->msix_bmap_ulds.msix_bmap);
4359 }
4360
4361 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4362 #define EXTRA_VECS 2
4363
4364 static int enable_msix(struct adapter *adap)
4365 {
4366         int ofld_need = 0, uld_need = 0;
4367         int i, j, want, need, allocated;
4368         struct sge *s = &adap->sge;
4369         unsigned int nchan = adap->params.nports;
4370         struct msix_entry *entries;
4371         int max_ingq = MAX_INGQ;
4372
4373         if (is_pci_uld(adap))
4374                 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
4375         if (is_offload(adap))
4376                 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
4377         entries = kmalloc(sizeof(*entries) * (max_ingq + 1),
4378                           GFP_KERNEL);
4379         if (!entries)
4380                 return -ENOMEM;
4381
4382         /* map for msix */
4383         if (get_msix_info(adap)) {
4384                 adap->params.offload = 0;
4385                 adap->params.crypto = 0;
4386         }
4387
4388         for (i = 0; i < max_ingq + 1; ++i)
4389                 entries[i].entry = i;
4390
4391         want = s->max_ethqsets + EXTRA_VECS;
4392         if (is_offload(adap)) {
4393                 want += adap->num_ofld_uld * s->ofldqsets;
4394                 ofld_need = adap->num_ofld_uld * nchan;
4395         }
4396         if (is_pci_uld(adap)) {
4397                 want += adap->num_uld * s->ofldqsets;
4398                 uld_need = adap->num_uld * nchan;
4399         }
4400 #ifdef CONFIG_CHELSIO_T4_DCB
4401         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4402          * each port.
4403          */
4404         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
4405 #else
4406         need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
4407 #endif
4408         allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4409         if (allocated < 0) {
4410                 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4411                          " not using MSI-X\n");
4412                 kfree(entries);
4413                 return allocated;
4414         }
4415
4416         /* Distribute available vectors to the various queue groups.
4417          * Every group gets its minimum requirement and NIC gets top
4418          * priority for leftovers.
4419          */
4420         i = allocated - EXTRA_VECS - ofld_need - uld_need;
4421         if (i < s->max_ethqsets) {
4422                 s->max_ethqsets = i;
4423                 if (i < s->ethqsets)
4424                         reduce_ethqs(adap, i);
4425         }
4426         if (is_uld(adap)) {
4427                 if (allocated < want)
4428                         s->nqs_per_uld = nchan;
4429                 else
4430                         s->nqs_per_uld = s->ofldqsets;
4431         }
4432
4433         for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
4434                 adap->msix_info[i].vec = entries[i].vector;
4435         if (is_uld(adap)) {
4436                 for (j = 0 ; i < allocated; ++i, j++) {
4437                         adap->msix_info_ulds[j].vec = entries[i].vector;
4438                         adap->msix_info_ulds[j].idx = i;
4439                 }
4440                 adap->msix_bmap_ulds.mapsize = j;
4441         }
4442         dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4443                  "nic %d per uld %d\n",
4444                  allocated, s->max_ethqsets, s->nqs_per_uld);
4445
4446         kfree(entries);
4447         return 0;
4448 }
4449
4450 #undef EXTRA_VECS
4451
4452 static int init_rss(struct adapter *adap)
4453 {
4454         unsigned int i;
4455         int err;
4456
4457         err = t4_init_rss_mode(adap, adap->mbox);
4458         if (err)
4459                 return err;
4460
4461         for_each_port(adap, i) {
4462                 struct port_info *pi = adap2pinfo(adap, i);
4463
4464                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4465                 if (!pi->rss)
4466                         return -ENOMEM;
4467         }
4468         return 0;
4469 }
4470
4471 static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4472                                         enum pci_bus_speed *speed,
4473                                         enum pcie_link_width *width)
4474 {
4475         u32 lnkcap1, lnkcap2;
4476         int err1, err2;
4477
4478 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
4479
4480         *speed = PCI_SPEED_UNKNOWN;
4481         *width = PCIE_LNK_WIDTH_UNKNOWN;
4482
4483         err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4484                                           &lnkcap1);
4485         err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4486                                           &lnkcap2);
4487         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
4488                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4489                         *speed = PCIE_SPEED_8_0GT;
4490                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4491                         *speed = PCIE_SPEED_5_0GT;
4492                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4493                         *speed = PCIE_SPEED_2_5GT;
4494         }
4495         if (!err1) {
4496                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4497                 if (!lnkcap2) { /* pre-r3.0 */
4498                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4499                                 *speed = PCIE_SPEED_5_0GT;
4500                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4501                                 *speed = PCIE_SPEED_2_5GT;
4502                 }
4503         }
4504
4505         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4506                 return err1 ? err1 : err2 ? err2 : -EINVAL;
4507         return 0;
4508 }
4509
4510 static void cxgb4_check_pcie_caps(struct adapter *adap)
4511 {
4512         enum pcie_link_width width, width_cap;
4513         enum pci_bus_speed speed, speed_cap;
4514
4515 #define PCIE_SPEED_STR(speed) \
4516         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4517          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4518          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4519          "Unknown")
4520
4521         if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4522                 dev_warn(adap->pdev_dev,
4523                          "Unable to determine PCIe device BW capabilities\n");
4524                 return;
4525         }
4526
4527         if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4528             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4529                 dev_warn(adap->pdev_dev,
4530                          "Unable to determine PCI Express bandwidth.\n");
4531                 return;
4532         }
4533
4534         dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4535                  PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4536         dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4537                  width, width_cap);
4538         if (speed < speed_cap || width < width_cap)
4539                 dev_info(adap->pdev_dev,
4540                          "A slot with more lanes and/or higher speed is "
4541                          "suggested for optimal performance.\n");
4542 }
4543
4544 /* Dump basic information about the adapter */
4545 static void print_adapter_info(struct adapter *adapter)
4546 {
4547         /* Hardware/Firmware/etc. Version/Revision IDs */
4548         t4_dump_version_info(adapter);
4549
4550         /* Software/Hardware configuration */
4551         dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
4552                  is_offload(adapter) ? "R" : "",
4553                  ((adapter->flags & USING_MSIX) ? "MSI-X" :
4554                   (adapter->flags & USING_MSI) ? "MSI" : ""),
4555                  is_offload(adapter) ? "Offload" : "non-Offload");
4556 }
4557
4558 static void print_port_info(const struct net_device *dev)
4559 {
4560         char buf[80];
4561         char *bufp = buf;
4562         const char *spd = "";
4563         const struct port_info *pi = netdev_priv(dev);
4564         const struct adapter *adap = pi->adapter;
4565
4566         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4567                 spd = " 2.5 GT/s";
4568         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4569                 spd = " 5 GT/s";
4570         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4571                 spd = " 8 GT/s";
4572
4573         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
4574                 bufp += sprintf(bufp, "100M/");
4575         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
4576                 bufp += sprintf(bufp, "1G/");
4577         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
4578                 bufp += sprintf(bufp, "10G/");
4579         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
4580                 bufp += sprintf(bufp, "25G/");
4581         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
4582                 bufp += sprintf(bufp, "40G/");
4583         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
4584                 bufp += sprintf(bufp, "50G/");
4585         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
4586                 bufp += sprintf(bufp, "100G/");
4587         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
4588                 bufp += sprintf(bufp, "200G/");
4589         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
4590                 bufp += sprintf(bufp, "400G/");
4591         if (bufp != buf)
4592                 --bufp;
4593         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4594
4595         netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
4596                     dev->name, adap->params.vpd.id, adap->name, buf);
4597 }
4598
4599 /*
4600  * Free the following resources:
4601  * - memory used for tables
4602  * - MSI/MSI-X
4603  * - net devices
4604  * - resources FW is holding for us
4605  */
4606 static void free_some_resources(struct adapter *adapter)
4607 {
4608         unsigned int i;
4609
4610         kvfree(adapter->l2t);
4611         t4_cleanup_sched(adapter);
4612         kvfree(adapter->tids.tid_tab);
4613         cxgb4_cleanup_tc_u32(adapter);
4614         kfree(adapter->sge.egr_map);
4615         kfree(adapter->sge.ingr_map);
4616         kfree(adapter->sge.starving_fl);
4617         kfree(adapter->sge.txq_maperr);
4618 #ifdef CONFIG_DEBUG_FS
4619         kfree(adapter->sge.blocked_fl);
4620 #endif
4621         disable_msi(adapter);
4622
4623         for_each_port(adapter, i)
4624                 if (adapter->port[i]) {
4625                         struct port_info *pi = adap2pinfo(adapter, i);
4626
4627                         if (pi->viid != 0)
4628                                 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4629                                            0, pi->viid);
4630                         kfree(adap2pinfo(adapter, i)->rss);
4631                         free_netdev(adapter->port[i]);
4632                 }
4633         if (adapter->flags & FW_OK)
4634                 t4_fw_bye(adapter, adapter->pf);
4635 }
4636
4637 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4638 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4639                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4640 #define SEGMENT_SIZE 128
4641
4642 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4643 {
4644         u16 device_id;
4645
4646         /* Retrieve adapter's device ID */
4647         pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4648
4649         switch (device_id >> 12) {
4650         case CHELSIO_T4:
4651                 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4652         case CHELSIO_T5:
4653                 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4654         case CHELSIO_T6:
4655                 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4656         default:
4657                 dev_err(&pdev->dev, "Device %d is not supported\n",
4658                         device_id);
4659         }
4660         return -EINVAL;
4661 }
4662
4663 #ifdef CONFIG_PCI_IOV
4664 static void dummy_setup(struct net_device *dev)
4665 {
4666         dev->type = ARPHRD_NONE;
4667         dev->mtu = 0;
4668         dev->hard_header_len = 0;
4669         dev->addr_len = 0;
4670         dev->tx_queue_len = 0;
4671         dev->flags |= IFF_NOARP;
4672         dev->priv_flags |= IFF_NO_QUEUE;
4673
4674         /* Initialize the device structure. */
4675         dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
4676         dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
4677 }
4678
4679 static int config_mgmt_dev(struct pci_dev *pdev)
4680 {
4681         struct adapter *adap = pci_get_drvdata(pdev);
4682         struct net_device *netdev;
4683         struct port_info *pi;
4684         char name[IFNAMSIZ];
4685         int err;
4686
4687         snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf);
4688         netdev = alloc_netdev(sizeof(struct port_info), name, NET_NAME_UNKNOWN,
4689                               dummy_setup);
4690         if (!netdev)
4691                 return -ENOMEM;
4692
4693         pi = netdev_priv(netdev);
4694         pi->adapter = adap;
4695         pi->tx_chan = adap->pf % adap->params.nports;
4696         SET_NETDEV_DEV(netdev, &pdev->dev);
4697
4698         adap->port[0] = netdev;
4699         pi->port_id = 0;
4700
4701         err = register_netdev(adap->port[0]);
4702         if (err) {
4703                 pr_info("Unable to register VF mgmt netdev %s\n", name);
4704                 free_netdev(adap->port[0]);
4705                 adap->port[0] = NULL;
4706                 return err;
4707         }
4708         return 0;
4709 }
4710
4711 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
4712 {
4713         struct adapter *adap = pci_get_drvdata(pdev);
4714         int err = 0;
4715         int current_vfs = pci_num_vf(pdev);
4716         u32 pcie_fw;
4717
4718         pcie_fw = readl(adap->regs + PCIE_FW_A);
4719         /* Check if cxgb4 is the MASTER and fw is initialized */
4720         if (!(pcie_fw & PCIE_FW_INIT_F) ||
4721             !(pcie_fw & PCIE_FW_MASTER_VLD_F) ||
4722             PCIE_FW_MASTER_G(pcie_fw) != 4) {
4723                 dev_warn(&pdev->dev,
4724                          "cxgb4 driver needs to be MASTER to support SRIOV\n");
4725                 return -EOPNOTSUPP;
4726         }
4727
4728         /* If any of the VF's is already assigned to Guest OS, then
4729          * SRIOV for the same cannot be modified
4730          */
4731         if (current_vfs && pci_vfs_assigned(pdev)) {
4732                 dev_err(&pdev->dev,
4733                         "Cannot modify SR-IOV while VFs are assigned\n");
4734                 num_vfs = current_vfs;
4735                 return num_vfs;
4736         }
4737
4738         /* Disable SRIOV when zero is passed.
4739          * One needs to disable SRIOV before modifying it, else
4740          * stack throws the below warning:
4741          * " 'n' VFs already enabled. Disable before enabling 'm' VFs."
4742          */
4743         if (!num_vfs) {
4744                 pci_disable_sriov(pdev);
4745                 if (adap->port[0]) {
4746                         unregister_netdev(adap->port[0]);
4747                         adap->port[0] = NULL;
4748                 }
4749                 /* free VF resources */
4750                 kfree(adap->vfinfo);
4751                 adap->vfinfo = NULL;
4752                 adap->num_vfs = 0;
4753                 return num_vfs;
4754         }
4755
4756         if (num_vfs != current_vfs) {
4757                 err = pci_enable_sriov(pdev, num_vfs);
4758                 if (err)
4759                         return err;
4760
4761                 adap->num_vfs = num_vfs;
4762                 err = config_mgmt_dev(pdev);
4763                 if (err)
4764                         return err;
4765         }
4766
4767         adap->vfinfo = kcalloc(adap->num_vfs,
4768                                sizeof(struct vf_info), GFP_KERNEL);
4769         if (adap->vfinfo)
4770                 fill_vf_station_mac_addr(adap);
4771         return num_vfs;
4772 }
4773 #endif
4774
4775 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4776 {
4777         int func, i, err, s_qpp, qpp, num_seg;
4778         struct port_info *pi;
4779         bool highdma = false;
4780         struct adapter *adapter = NULL;
4781         struct net_device *netdev;
4782         void __iomem *regs;
4783         u32 whoami, pl_rev;
4784         enum chip_type chip;
4785         static int adap_idx = 1;
4786 #ifdef CONFIG_PCI_IOV
4787         u32 v, port_vec;
4788 #endif
4789
4790         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4791
4792         err = pci_request_regions(pdev, KBUILD_MODNAME);
4793         if (err) {
4794                 /* Just info, some other driver may have claimed the device. */
4795                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4796                 return err;
4797         }
4798
4799         err = pci_enable_device(pdev);
4800         if (err) {
4801                 dev_err(&pdev->dev, "cannot enable PCI device\n");
4802                 goto out_release_regions;
4803         }
4804
4805         regs = pci_ioremap_bar(pdev, 0);
4806         if (!regs) {
4807                 dev_err(&pdev->dev, "cannot map device registers\n");
4808                 err = -ENOMEM;
4809                 goto out_disable_device;
4810         }
4811
4812         err = t4_wait_dev_ready(regs);
4813         if (err < 0)
4814                 goto out_unmap_bar0;
4815
4816         /* We control everything through one PF */
4817         whoami = readl(regs + PL_WHOAMI_A);
4818         pl_rev = REV_G(readl(regs + PL_REV_A));
4819         chip = get_chip_type(pdev, pl_rev);
4820         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4821                 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4822         if (func != ent->driver_data) {
4823 #ifndef CONFIG_PCI_IOV
4824                 iounmap(regs);
4825 #endif
4826                 pci_disable_device(pdev);
4827                 pci_save_state(pdev);        /* to restore SR-IOV later */
4828                 goto sriov;
4829         }
4830
4831         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4832                 highdma = true;
4833                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4834                 if (err) {
4835                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4836                                 "coherent allocations\n");
4837                         goto out_unmap_bar0;
4838                 }
4839         } else {
4840                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4841                 if (err) {
4842                         dev_err(&pdev->dev, "no usable DMA configuration\n");
4843                         goto out_unmap_bar0;
4844                 }
4845         }
4846
4847         pci_enable_pcie_error_reporting(pdev);
4848         pci_set_master(pdev);
4849         pci_save_state(pdev);
4850
4851         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4852         if (!adapter) {
4853                 err = -ENOMEM;
4854                 goto out_unmap_bar0;
4855         }
4856         adap_idx++;
4857
4858         adapter->workq = create_singlethread_workqueue("cxgb4");
4859         if (!adapter->workq) {
4860                 err = -ENOMEM;
4861                 goto out_free_adapter;
4862         }
4863
4864         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
4865                                     (sizeof(struct mbox_cmd) *
4866                                      T4_OS_LOG_MBOX_CMDS),
4867                                     GFP_KERNEL);
4868         if (!adapter->mbox_log) {
4869                 err = -ENOMEM;
4870                 goto out_free_adapter;
4871         }
4872         adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
4873
4874         /* PCI device has been enabled */
4875         adapter->flags |= DEV_ENABLED;
4876
4877         adapter->regs = regs;
4878         adapter->pdev = pdev;
4879         adapter->pdev_dev = &pdev->dev;
4880         adapter->name = pci_name(pdev);
4881         adapter->mbox = func;
4882         adapter->pf = func;
4883         adapter->msg_enable = DFLT_MSG_ENABLE;
4884         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4885
4886         /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
4887          * Ingress Packet Data to Free List Buffers in order to allow for
4888          * chipset performance optimizations between the Root Complex and
4889          * Memory Controllers.  (Messages to the associated Ingress Queue
4890          * notifying new Packet Placement in the Free Lists Buffers will be
4891          * send without the Relaxed Ordering Attribute thus guaranteeing that
4892          * all preceding PCIe Transaction Layer Packets will be processed
4893          * first.)  But some Root Complexes have various issues with Upstream
4894          * Transaction Layer Packets with the Relaxed Ordering Attribute set.
4895          * The PCIe devices which under the Root Complexes will be cleared the
4896          * Relaxed Ordering bit in the configuration space, So we check our
4897          * PCIe configuration space to see if it's flagged with advice against
4898          * using Relaxed Ordering.
4899          */
4900         if (!pcie_relaxed_ordering_enabled(pdev))
4901                 adapter->flags |= ROOT_NO_RELAXED_ORDERING;
4902
4903         spin_lock_init(&adapter->stats_lock);
4904         spin_lock_init(&adapter->tid_release_lock);
4905         spin_lock_init(&adapter->win0_lock);
4906         spin_lock_init(&adapter->mbox_lock);
4907
4908         INIT_LIST_HEAD(&adapter->mlist.list);
4909
4910         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4911         INIT_WORK(&adapter->db_full_task, process_db_full);
4912         INIT_WORK(&adapter->db_drop_task, process_db_drop);
4913
4914         err = t4_prep_adapter(adapter);
4915         if (err)
4916                 goto out_free_adapter;
4917
4918
4919         if (!is_t4(adapter->params.chip)) {
4920                 s_qpp = (QUEUESPERPAGEPF0_S +
4921                         (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4922                         adapter->pf);
4923                 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4924                       SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4925                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4926
4927                 /* Each segment size is 128B. Write coalescing is enabled only
4928                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4929                  * queue is less no of segments that can be accommodated in
4930                  * a page size.
4931                  */
4932                 if (qpp > num_seg) {
4933                         dev_err(&pdev->dev,
4934                                 "Incorrect number of egress queues per page\n");
4935                         err = -EINVAL;
4936                         goto out_free_adapter;
4937                 }
4938                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4939                 pci_resource_len(pdev, 2));
4940                 if (!adapter->bar2) {
4941                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
4942                         err = -ENOMEM;
4943                         goto out_free_adapter;
4944                 }
4945         }
4946
4947         setup_memwin(adapter);
4948         err = adap_init0(adapter);
4949 #ifdef CONFIG_DEBUG_FS
4950         bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4951 #endif
4952         setup_memwin_rdma(adapter);
4953         if (err)
4954                 goto out_unmap_bar;
4955
4956         /* configure SGE_STAT_CFG_A to read WC stats */
4957         if (!is_t4(adapter->params.chip))
4958                 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
4959                              (is_t5(adapter->params.chip) ? STATMODE_V(0) :
4960                               T6_STATMODE_V(0)));
4961
4962         /* Initialize hash mac addr list */
4963         INIT_LIST_HEAD(&adapter->mac_hlist);
4964
4965         for_each_port(adapter, i) {
4966                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4967                                            MAX_ETH_QSETS);
4968                 if (!netdev) {
4969                         err = -ENOMEM;
4970                         goto out_free_dev;
4971                 }
4972
4973                 SET_NETDEV_DEV(netdev, &pdev->dev);
4974
4975                 adapter->port[i] = netdev;
4976                 pi = netdev_priv(netdev);
4977                 pi->adapter = adapter;
4978                 pi->xact_addr_filt = -1;
4979                 pi->port_id = i;
4980                 netdev->irq = pdev->irq;
4981
4982                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4983                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4984                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
4985                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
4986                         NETIF_F_HW_TC;
4987                 if (highdma)
4988                         netdev->hw_features |= NETIF_F_HIGHDMA;
4989                 netdev->features |= netdev->hw_features;
4990                 netdev->vlan_features = netdev->features & VLAN_FEAT;
4991
4992                 netdev->priv_flags |= IFF_UNICAST_FLT;
4993
4994                 /* MTU range: 81 - 9600 */
4995                 netdev->min_mtu = 81;
4996                 netdev->max_mtu = MAX_MTU;
4997
4998                 netdev->netdev_ops = &cxgb4_netdev_ops;
4999 #ifdef CONFIG_CHELSIO_T4_DCB
5000                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5001                 cxgb4_dcb_state_init(netdev);
5002 #endif
5003                 cxgb4_set_ethtool_ops(netdev);
5004         }
5005
5006         pci_set_drvdata(pdev, adapter);
5007
5008         if (adapter->flags & FW_OK) {
5009                 err = t4_port_init(adapter, func, func, 0);
5010                 if (err)
5011                         goto out_free_dev;
5012         } else if (adapter->params.nports == 1) {
5013                 /* If we don't have a connection to the firmware -- possibly
5014                  * because of an error -- grab the raw VPD parameters so we
5015                  * can set the proper MAC Address on the debug network
5016                  * interface that we've created.
5017                  */
5018                 u8 hw_addr[ETH_ALEN];
5019                 u8 *na = adapter->params.vpd.na;
5020
5021                 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5022                 if (!err) {
5023                         for (i = 0; i < ETH_ALEN; i++)
5024                                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5025                                               hex2val(na[2 * i + 1]));
5026                         t4_set_hw_addr(adapter, 0, hw_addr);
5027                 }
5028         }
5029
5030         /* Configure queues and allocate tables now, they can be needed as
5031          * soon as the first register_netdev completes.
5032          */
5033         cfg_queues(adapter);
5034
5035         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
5036         if (!adapter->l2t) {
5037                 /* We tolerate a lack of L2T, giving up some functionality */
5038                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5039                 adapter->params.offload = 0;
5040         }
5041
5042 #if IS_ENABLED(CONFIG_IPV6)
5043         if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
5044             (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5045                 /* CLIP functionality is not present in hardware,
5046                  * hence disable all offload features
5047                  */
5048                 dev_warn(&pdev->dev,
5049                          "CLIP not enabled in hardware, continuing\n");
5050                 adapter->params.offload = 0;
5051         } else {
5052                 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5053                                                   adapter->clipt_end);
5054                 if (!adapter->clipt) {
5055                         /* We tolerate a lack of clip_table, giving up
5056                          * some functionality
5057                          */
5058                         dev_warn(&pdev->dev,
5059                                  "could not allocate Clip table, continuing\n");
5060                         adapter->params.offload = 0;
5061                 }
5062         }
5063 #endif
5064
5065         for_each_port(adapter, i) {
5066                 pi = adap2pinfo(adapter, i);
5067                 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5068                 if (!pi->sched_tbl)
5069                         dev_warn(&pdev->dev,
5070                                  "could not activate scheduling on port %d\n",
5071                                  i);
5072         }
5073
5074         if (tid_init(&adapter->tids) < 0) {
5075                 dev_warn(&pdev->dev, "could not allocate TID table, "
5076                          "continuing\n");
5077                 adapter->params.offload = 0;
5078         } else {
5079                 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
5080                 if (!adapter->tc_u32)
5081                         dev_warn(&pdev->dev,
5082                                  "could not offload tc u32, continuing\n");
5083         }
5084
5085         if (is_offload(adapter)) {
5086                 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5087                         u32 hash_base, hash_reg;
5088
5089                         if (chip <= CHELSIO_T5) {
5090                                 hash_reg = LE_DB_TID_HASHBASE_A;
5091                                 hash_base = t4_read_reg(adapter, hash_reg);
5092                                 adapter->tids.hash_base = hash_base / 4;
5093                         } else {
5094                                 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5095                                 hash_base = t4_read_reg(adapter, hash_reg);
5096                                 adapter->tids.hash_base = hash_base;
5097                         }
5098                 }
5099         }
5100
5101         /* See what interrupts we'll be using */
5102         if (msi > 1 && enable_msix(adapter) == 0)
5103                 adapter->flags |= USING_MSIX;
5104         else if (msi > 0 && pci_enable_msi(pdev) == 0) {
5105                 adapter->flags |= USING_MSI;
5106                 if (msi > 1)
5107                         free_msix_info(adapter);
5108         }
5109
5110         /* check for PCI Express bandwidth capabiltites */
5111         cxgb4_check_pcie_caps(adapter);
5112
5113         err = init_rss(adapter);
5114         if (err)
5115                 goto out_free_dev;
5116
5117         err = setup_fw_sge_queues(adapter);
5118         if (err) {
5119                 dev_err(adapter->pdev_dev,
5120                         "FW sge queue allocation failed, err %d", err);
5121                 goto out_free_dev;
5122         }
5123
5124         /*
5125          * The card is now ready to go.  If any errors occur during device
5126          * registration we do not fail the whole card but rather proceed only
5127          * with the ports we manage to register successfully.  However we must
5128          * register at least one net device.
5129          */
5130         for_each_port(adapter, i) {
5131                 pi = adap2pinfo(adapter, i);
5132                 adapter->port[i]->dev_port = pi->lport;
5133                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5134                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5135
5136                 netif_carrier_off(adapter->port[i]);
5137
5138                 err = register_netdev(adapter->port[i]);
5139                 if (err)
5140                         break;
5141                 adapter->chan_map[pi->tx_chan] = i;
5142                 print_port_info(adapter->port[i]);
5143         }
5144         if (i == 0) {
5145                 dev_err(&pdev->dev, "could not register any net devices\n");
5146                 goto out_free_dev;
5147         }
5148         if (err) {
5149                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5150                 err = 0;
5151         }
5152
5153         if (cxgb4_debugfs_root) {
5154                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5155                                                            cxgb4_debugfs_root);
5156                 setup_debugfs(adapter);
5157         }
5158
5159         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5160         pdev->needs_freset = 1;
5161
5162         if (is_uld(adapter)) {
5163                 mutex_lock(&uld_mutex);
5164                 list_add_tail(&adapter->list_node, &adapter_list);
5165                 mutex_unlock(&uld_mutex);
5166         }
5167
5168         if (!is_t4(adapter->params.chip))
5169                 cxgb4_ptp_init(adapter);
5170
5171         print_adapter_info(adapter);
5172         return 0;
5173
5174 sriov:
5175 #ifdef CONFIG_PCI_IOV
5176         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5177         if (!adapter) {
5178                 err = -ENOMEM;
5179                 goto free_pci_region;
5180         }
5181
5182         adapter->pdev = pdev;
5183         adapter->pdev_dev = &pdev->dev;
5184         adapter->name = pci_name(pdev);
5185         adapter->mbox = func;
5186         adapter->pf = func;
5187         adapter->regs = regs;
5188         adapter->adap_idx = adap_idx;
5189         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5190                                     (sizeof(struct mbox_cmd) *
5191                                      T4_OS_LOG_MBOX_CMDS),
5192                                     GFP_KERNEL);
5193         if (!adapter->mbox_log) {
5194                 err = -ENOMEM;
5195                 goto free_adapter;
5196         }
5197         spin_lock_init(&adapter->mbox_lock);
5198         INIT_LIST_HEAD(&adapter->mlist.list);
5199
5200         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5201             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
5202         err = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1,
5203                               &v, &port_vec);
5204         if (err < 0) {
5205                 dev_err(adapter->pdev_dev, "Could not fetch port params\n");
5206                 goto free_mbox_log;
5207         }
5208
5209         adapter->params.nports = hweight32(port_vec);
5210         pci_set_drvdata(pdev, adapter);
5211         return 0;
5212
5213 free_mbox_log:
5214         kfree(adapter->mbox_log);
5215  free_adapter:
5216         kfree(adapter);
5217  free_pci_region:
5218         iounmap(regs);
5219         pci_disable_sriov(pdev);
5220         pci_release_regions(pdev);
5221         return err;
5222 #else
5223         return 0;
5224 #endif
5225
5226  out_free_dev:
5227         t4_free_sge_resources(adapter);
5228         free_some_resources(adapter);
5229         if (adapter->flags & USING_MSIX)
5230                 free_msix_info(adapter);
5231         if (adapter->num_uld || adapter->num_ofld_uld)
5232                 t4_uld_mem_free(adapter);
5233  out_unmap_bar:
5234         if (!is_t4(adapter->params.chip))
5235                 iounmap(adapter->bar2);
5236  out_free_adapter:
5237         if (adapter->workq)
5238                 destroy_workqueue(adapter->workq);
5239
5240         kfree(adapter->mbox_log);
5241         kfree(adapter);
5242  out_unmap_bar0:
5243         iounmap(regs);
5244  out_disable_device:
5245         pci_disable_pcie_error_reporting(pdev);
5246         pci_disable_device(pdev);
5247  out_release_regions:
5248         pci_release_regions(pdev);
5249         return err;
5250 }
5251
5252 static void remove_one(struct pci_dev *pdev)
5253 {
5254         struct adapter *adapter = pci_get_drvdata(pdev);
5255         struct hash_mac_addr *entry, *tmp;
5256
5257         if (!adapter) {
5258                 pci_release_regions(pdev);
5259                 return;
5260         }
5261
5262         if (adapter->pf == 4) {
5263                 int i;
5264
5265                 /* Tear down per-adapter Work Queue first since it can contain
5266                  * references to our adapter data structure.
5267                  */
5268                 destroy_workqueue(adapter->workq);
5269
5270                 if (is_uld(adapter)) {
5271                         detach_ulds(adapter);
5272                         t4_uld_clean_up(adapter);
5273                 }
5274
5275                 disable_interrupts(adapter);
5276
5277                 for_each_port(adapter, i)
5278                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5279                                 unregister_netdev(adapter->port[i]);
5280
5281                 debugfs_remove_recursive(adapter->debugfs_root);
5282
5283                 if (!is_t4(adapter->params.chip))
5284                         cxgb4_ptp_stop(adapter);
5285
5286                 /* If we allocated filters, free up state associated with any
5287                  * valid filters ...
5288                  */
5289                 clear_all_filters(adapter);
5290
5291                 if (adapter->flags & FULL_INIT_DONE)
5292                         cxgb_down(adapter);
5293
5294                 if (adapter->flags & USING_MSIX)
5295                         free_msix_info(adapter);
5296                 if (adapter->num_uld || adapter->num_ofld_uld)
5297                         t4_uld_mem_free(adapter);
5298                 free_some_resources(adapter);
5299                 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
5300                                          list) {
5301                         list_del(&entry->list);
5302                         kfree(entry);
5303                 }
5304
5305 #if IS_ENABLED(CONFIG_IPV6)
5306                 t4_cleanup_clip_tbl(adapter);
5307 #endif
5308                 iounmap(adapter->regs);
5309                 if (!is_t4(adapter->params.chip))
5310                         iounmap(adapter->bar2);
5311                 pci_disable_pcie_error_reporting(pdev);
5312                 if ((adapter->flags & DEV_ENABLED)) {
5313                         pci_disable_device(pdev);
5314                         adapter->flags &= ~DEV_ENABLED;
5315                 }
5316                 pci_release_regions(pdev);
5317                 kfree(adapter->mbox_log);
5318                 synchronize_rcu();
5319                 kfree(adapter);
5320         }
5321 #ifdef CONFIG_PCI_IOV
5322         else {
5323                 if (adapter->port[0])
5324                         unregister_netdev(adapter->port[0]);
5325                 iounmap(adapter->regs);
5326                 kfree(adapter->vfinfo);
5327                 kfree(adapter->mbox_log);
5328                 kfree(adapter);
5329                 pci_disable_sriov(pdev);
5330                 pci_release_regions(pdev);
5331         }
5332 #endif
5333 }
5334
5335 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
5336  * delivery.  This is essentially a stripped down version of the PCI remove()
5337  * function where we do the minimal amount of work necessary to shutdown any
5338  * further activity.
5339  */
5340 static void shutdown_one(struct pci_dev *pdev)
5341 {
5342         struct adapter *adapter = pci_get_drvdata(pdev);
5343
5344         /* As with remove_one() above (see extended comment), we only want do
5345          * do cleanup on PCI Devices which went all the way through init_one()
5346          * ...
5347          */
5348         if (!adapter) {
5349                 pci_release_regions(pdev);
5350                 return;
5351         }
5352
5353         if (adapter->pf == 4) {
5354                 int i;
5355
5356                 for_each_port(adapter, i)
5357                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5358                                 cxgb_close(adapter->port[i]);
5359
5360                 if (is_uld(adapter)) {
5361                         detach_ulds(adapter);
5362                         t4_uld_clean_up(adapter);
5363                 }
5364
5365                 disable_interrupts(adapter);
5366                 disable_msi(adapter);
5367
5368                 t4_sge_stop(adapter);
5369                 if (adapter->flags & FW_OK)
5370                         t4_fw_bye(adapter, adapter->mbox);
5371         }
5372 #ifdef CONFIG_PCI_IOV
5373         else {
5374                 if (adapter->port[0])
5375                         unregister_netdev(adapter->port[0]);
5376                 iounmap(adapter->regs);
5377                 kfree(adapter->vfinfo);
5378                 kfree(adapter->mbox_log);
5379                 kfree(adapter);
5380                 pci_disable_sriov(pdev);
5381                 pci_release_regions(pdev);
5382         }
5383 #endif
5384 }
5385
5386 static struct pci_driver cxgb4_driver = {
5387         .name     = KBUILD_MODNAME,
5388         .id_table = cxgb4_pci_tbl,
5389         .probe    = init_one,
5390         .remove   = remove_one,
5391         .shutdown = shutdown_one,
5392 #ifdef CONFIG_PCI_IOV
5393         .sriov_configure = cxgb4_iov_configure,
5394 #endif
5395         .err_handler = &cxgb4_eeh,
5396 };
5397
5398 static int __init cxgb4_init_module(void)
5399 {
5400         int ret;
5401
5402         /* Debugfs support is optional, just warn if this fails */
5403         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5404         if (!cxgb4_debugfs_root)
5405                 pr_warn("could not create debugfs entry, continuing\n");
5406
5407         ret = pci_register_driver(&cxgb4_driver);
5408         if (ret < 0)
5409                 goto err_pci;
5410
5411 #if IS_ENABLED(CONFIG_IPV6)
5412         if (!inet6addr_registered) {
5413                 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5414                 if (ret)
5415                         pci_unregister_driver(&cxgb4_driver);
5416                 else
5417                         inet6addr_registered = true;
5418         }
5419 #endif
5420
5421         if (ret == 0)
5422                 return ret;
5423
5424 err_pci:
5425         debugfs_remove(cxgb4_debugfs_root);
5426
5427         return ret;
5428 }
5429
5430 static void __exit cxgb4_cleanup_module(void)
5431 {
5432 #if IS_ENABLED(CONFIG_IPV6)
5433         if (inet6addr_registered) {
5434                 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5435                 inet6addr_registered = false;
5436         }
5437 #endif
5438         pci_unregister_driver(&cxgb4_driver);
5439         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
5440 }
5441
5442 module_init(cxgb4_init_module);
5443 module_exit(cxgb4_cleanup_module);