drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F) {
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201                 adap->flags &= ~FW_OK;
 202         }
 203 }
 204
 205 /*
 206  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 207  */
 208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 209                          u32 mbox_addr)
 210 {
 211         for ( ; nflit; nflit--, mbox_addr += 8)
 212                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 213 }
 214
 215 /*
 216  * Handle a FW assertion reported in a mailbox.
 217  */
 218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 219 {
 220         struct fw_debug_cmd asrt;
 221
 222         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 223         dev_alert(adap->pdev_dev,
 224                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 225                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 226                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 227 }
 228
 229 /**
 230  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 231  *      @adapter: the adapter
 232  *      @cmd: the Firmware Mailbox Command or Reply
 233  *      @size: command length in bytes
 234  *      @access: the time (ms) needed to access the Firmware Mailbox
 235  *      @execute: the time (ms) the command spent being executed
 236  */
 237 static void t4_record_mbox(struct adapter *adapter,
 238                            const __be64 *cmd, unsigned int size,
 239                            int access, int execute)
 240 {
 241         struct mbox_cmd_log *log = adapter->mbox_log;
 242         struct mbox_cmd *entry;
 243         int i;
 244
 245         entry = mbox_cmd_log_entry(log, log->cursor++);
 246         if (log->cursor == log->size)
 247                 log->cursor = 0;
 248
 249         for (i = 0; i < size / 8; i++)
 250                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 251         while (i < MBOX_LEN / 8)
 252                 entry->cmd[i++] = 0;
 253         entry->timestamp = jiffies;
 254         entry->seqno = log->seqno++;
 255         entry->access = access;
 256         entry->execute = execute;
 257 }
 258
 259 /**
 260  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 261  *      @adap: the adapter
 262  *      @mbox: index of the mailbox to use
 263  *      @cmd: the command to write
 264  *      @size: command length in bytes
 265  *      @rpl: where to optionally store the reply
 266  *      @sleep_ok: if true we may sleep while awaiting command completion
 267  *      @timeout: time to wait for command to finish before timing out
 268  *
 269  *      Sends the given command to FW through the selected mailbox and waits
 270  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 271  *      store the FW's reply to the command.  The command and its optional
 272  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 273  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 274  *      the response.  If sleeping is allowed we use progressive backoff
 275  *      otherwise we spin.
 276  *
 277  *      The return value is 0 on success or a negative errno on failure.  A
 278  *      failure can happen either because we are not able to execute the
 279  *      command or FW executes it but signals an error.  In the latter case
 280  *      the return value is the error code indicated by FW (negated).
 281  */
 282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 283                             int size, void *rpl, bool sleep_ok, int timeout)
 284 {
 285         static const int delay[] = {
 286                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 287         };
 288
 289         struct mbox_list entry;
 290         u16 access = 0;
 291         u16 execute = 0;
 292         u32 v;
 293         u64 res;
 294         int i, ms, delay_idx, ret;
 295         const __be64 *p = cmd;
 296         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 297         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 298         __be64 cmd_rpl[MBOX_LEN / 8];
 299         u32 pcie_fw;
 300
 301         if ((size & 15) || size > MBOX_LEN)
 302                 return -EINVAL;
 303
 304         /*
 305          * If the device is off-line, as in EEH, commands will time out.
 306          * Fail them early so we don't waste time waiting.
 307          */
 308         if (adap->pdev->error_state != pci_channel_io_normal)
 309                 return -EIO;
 310
 311         /* If we have a negative timeout, that implies that we can't sleep. */
 312         if (timeout < 0) {
 313                 sleep_ok = false;
 314                 timeout = -timeout;
 315         }
 316
 317         /* Queue ourselves onto the mailbox access list.  When our entry is at
 318          * the front of the list, we have rights to access the mailbox.  So we
 319          * wait [for a while] till we're at the front [or bail out with an
 320          * EBUSY] ...
 321          */
 322         spin_lock_bh(&adap->mbox_lock);
 323         list_add_tail(&entry.list, &adap->mlist.list);
 324         spin_unlock_bh(&adap->mbox_lock);
 325
 326         delay_idx = 0;
 327         ms = delay[0];
 328
 329         for (i = 0; ; i += ms) {
 330                 /* If we've waited too long, return a busy indication.  This
 331                  * really ought to be based on our initial position in the
 332                  * mailbox access list but this is a start.  We very rearely
 333                  * contend on access to the mailbox ...
 334                  */
 335                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 336                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 337                         spin_lock_bh(&adap->mbox_lock);
 338                         list_del(&entry.list);
 339                         spin_unlock_bh(&adap->mbox_lock);
 340                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 341                         t4_record_mbox(adap, cmd, size, access, ret);
 342                         return ret;
 343                 }
 344
 345                 /* If we're at the head, break out and start the mailbox
 346                  * protocol.
 347                  */
 348                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 349                                      list) == &entry)
 350                         break;
 351
 352                 /* Delay for a bit before checking again ... */
 353                 if (sleep_ok) {
 354                         ms = delay[delay_idx];  /* last element may repeat */
 355                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 356                                 delay_idx++;
 357                         msleep(ms);
 358                 } else {
 359                         mdelay(ms);
 360                 }
 361         }
 362
 363         /* Loop trying to get ownership of the mailbox.  Return an error
 364          * if we can't gain ownership.
 365          */
 366         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 368                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 369         if (v != MBOX_OWNER_DRV) {
 370                 spin_lock_bh(&adap->mbox_lock);
 371                 list_del(&entry.list);
 372                 spin_unlock_bh(&adap->mbox_lock);
 373                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 374                 t4_record_mbox(adap, cmd, size, access, ret);
 375                 return ret;
 376         }
 377
 378         /* Copy in the new mailbox command and send it on its way ... */
 379         t4_record_mbox(adap, cmd, size, access, 0);
 380         for (i = 0; i < size; i += 8)
 381                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 382
 383         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 384         t4_read_reg(adap, ctl_reg);          /* flush write */
 385
 386         delay_idx = 0;
 387         ms = delay[0];
 388
 389         for (i = 0;
 390              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 391              i < timeout;
 392              i += ms) {
 393                 if (sleep_ok) {
 394                         ms = delay[delay_idx];  /* last element may repeat */
 395                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 396                                 delay_idx++;
 397                         msleep(ms);
 398                 } else
 399                         mdelay(ms);
 400
 401                 v = t4_read_reg(adap, ctl_reg);
 402                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 403                         if (!(v & MBMSGVALID_F)) {
 404                                 t4_write_reg(adap, ctl_reg, 0);
 405                                 continue;
 406                         }
 407
 408                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 409                         res = be64_to_cpu(cmd_rpl[0]);
 410
 411                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 412                                 fw_asrt(adap, data_reg);
 413                                 res = FW_CMD_RETVAL_V(EIO);
 414                         } else if (rpl) {
 415                                 memcpy(rpl, cmd_rpl, size);
 416                         }
 417
 418                         t4_write_reg(adap, ctl_reg, 0);
 419
 420                         execute = i + ms;
 421                         t4_record_mbox(adap, cmd_rpl,
 422                                        MBOX_LEN, access, execute);
 423                         spin_lock_bh(&adap->mbox_lock);
 424                         list_del(&entry.list);
 425                         spin_unlock_bh(&adap->mbox_lock);
 426                         return -FW_CMD_RETVAL_G((int)res);
 427                 }
 428         }
 429
 430         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 431         t4_record_mbox(adap, cmd, size, access, ret);
 432         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 433                 *(const u8 *)cmd, mbox);
 434         t4_report_fw_error(adap);
 435         spin_lock_bh(&adap->mbox_lock);
 436         list_del(&entry.list);
 437         spin_unlock_bh(&adap->mbox_lock);
 438         t4_fatal_err(adap);
 439         return ret;
 440 }
 441
 442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 443                     void *rpl, bool sleep_ok)
 444 {
 445         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 446                                        FW_CMD_MAX_TIMEOUT);
 447 }
 448
 449 static int t4_edc_err_read(struct adapter *adap, int idx)
 450 {
 451         u32 edc_ecc_err_addr_reg;
 452         u32 rdata_reg;
 453
 454         if (is_t4(adap->params.chip)) {
 455                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 456                 return 0;
 457         }
 458         if (idx != 0 && idx != 1) {
 459                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 460                 return 0;
 461         }
 462
 463         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 464         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 465
 466         CH_WARN(adap,
 467                 "edc%d err addr 0x%x: 0x%x.\n",
 468                 idx, edc_ecc_err_addr_reg,
 469                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 470         CH_WARN(adap,
 471                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 472                 rdata_reg,
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 480                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 481                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * t4_memory_rw_init - Get memory window relative offset, base, and size.
 488  * @adap: the adapter
 489  * @win: PCI-E Memory Window to use
 490  * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
 491  * @mem_off: memory relative offset with respect to @mtype.
 492  * @mem_base: configured memory base address.
 493  * @mem_aperture: configured memory window aperture.
 494  *
 495  * Get the configured memory window's relative offset, base, and size.
 496  */
 497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
 498                       u32 *mem_base, u32 *mem_aperture)
 499 {
 500         u32 edc_size, mc_size, mem_reg;
 501
 502         /* Offset into the region of memory which is being accessed
 503          * MEM_EDC0 = 0
 504          * MEM_EDC1 = 1
 505          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 506          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 507          * MEM_HMA  = 4
 508          */
 509         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 510         if (mtype == MEM_HMA) {
 511                 *mem_off = 2 * (edc_size * 1024 * 1024);
 512         } else if (mtype != MEM_MC1) {
 513                 *mem_off = (mtype * (edc_size * 1024 * 1024));
 514         } else {
 515                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 516                                                       MA_EXT_MEMORY0_BAR_A));
 517                 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 518         }
 519
 520         /* Each PCI-E Memory Window is programmed with a window size -- or
 521          * "aperture" -- which controls the granularity of its mapping onto
 522          * adapter memory.  We need to grab that aperture in order to know
 523          * how to use the specified window.  The window is also programmed
 524          * with the base address of the Memory Window in BAR0's address
 525          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 526          * the address is relative to BAR0.
 527          */
 528         mem_reg = t4_read_reg(adap,
 529                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 530                                                   win));
 531         /* a dead adapter will return 0xffffffff for PIO reads */
 532         if (mem_reg == 0xffffffff)
 533                 return -ENXIO;
 534
 535         *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 536         *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 537         if (is_t4(adap->params.chip))
 538                 *mem_base -= adap->t4_bar0;
 539
 540         return 0;
 541 }
 542
 543 /**
 544  * t4_memory_update_win - Move memory window to specified address.
 545  * @adap: the adapter
 546  * @win: PCI-E Memory Window to use
 547  * @addr: location to move.
 548  *
 549  * Move memory window to specified address.
 550  */
 551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
 552 {
 553         t4_write_reg(adap,
 554                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 555                      addr);
 556         /* Read it back to ensure that changes propagate before we
 557          * attempt to use the new value.
 558          */
 559         t4_read_reg(adap,
 560                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 561 }
 562
 563 /**
 564  * t4_memory_rw_residual - Read/Write residual data.
 565  * @adap: the adapter
 566  * @off: relative offset within residual to start read/write.
 567  * @addr: address within indicated memory type.
 568  * @buf: host memory buffer
 569  * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 570  *
 571  * Read/Write residual data less than 32-bits.
 572  */
 573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
 574                            int dir)
 575 {
 576         union {
 577                 u32 word;
 578                 char byte[4];
 579         } last;
 580         unsigned char *bp;
 581         int i;
 582
 583         if (dir == T4_MEMORY_READ) {
 584                 last.word = le32_to_cpu((__force __le32)
 585                                         t4_read_reg(adap, addr));
 586                 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
 587                         bp[i] = last.byte[i];
 588         } else {
 589                 last.word = *buf;
 590                 for (i = off; i < 4; i++)
 591                         last.byte[i] = 0;
 592                 t4_write_reg(adap, addr,
 593                              (__force u32)cpu_to_le32(last.word));
 594         }
 595 }
 596
 597 /**
 598  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 599  *      @adap: the adapter
 600  *      @win: PCI-E Memory Window to use
 601  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 602  *      @addr: address within indicated memory type
 603  *      @len: amount of memory to transfer
 604  *      @hbuf: host memory buffer
 605  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 606  *
 607  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 608  *      firmware memory address and host buffer must be aligned on 32-bit
 609  *      boudaries; the length may be arbitrary.  The memory is transferred as
 610  *      a raw byte sequence from/to the firmware's memory.  If this memory
 611  *      contains data structures which contain multi-byte integers, it's the
 612  *      caller's responsibility to perform appropriate byte order conversions.
 613  */
 614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 615                  u32 len, void *hbuf, int dir)
 616 {
 617         u32 pos, offset, resid, memoffset;
 618         u32 win_pf, mem_aperture, mem_base;
 619         u32 *buf;
 620         int ret;
 621
 622         /* Argument sanity checks ...
 623          */
 624         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 625                 return -EINVAL;
 626         buf = (u32 *)hbuf;
 627
 628         /* It's convenient to be able to handle lengths which aren't a
 629          * multiple of 32-bits because we often end up transferring files to
 630          * the firmware.  So we'll handle that by normalizing the length here
 631          * and then handling any residual transfer at the end.
 632          */
 633         resid = len & 0x3;
 634         len -= resid;
 635
 636         ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
 637                                 &mem_aperture);
 638         if (ret)
 639                 return ret;
 640
 641         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 642         addr = addr + memoffset;
 643
 644         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 645
 646         /* Calculate our initial PCI-E Memory Window Position and Offset into
 647          * that Window.
 648          */
 649         pos = addr & ~(mem_aperture - 1);
 650         offset = addr - pos;
 651
 652         /* Set up initial PCI-E Memory Window to cover the start of our
 653          * transfer.
 654          */
 655         t4_memory_update_win(adap, win, pos | win_pf);
 656
 657         /* Transfer data to/from the adapter as long as there's an integral
 658          * number of 32-bit transfers to complete.
 659          *
 660          * A note on Endianness issues:
 661          *
 662          * The "register" reads and writes below from/to the PCI-E Memory
 663          * Window invoke the standard adapter Big-Endian to PCI-E Link
 664          * Little-Endian "swizzel."  As a result, if we have the following
 665          * data in adapter memory:
 666          *
 667          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 668          *     Address:      i+0  i+1  i+2  i+3
 669          *
 670          * Then a read of the adapter memory via the PCI-E Memory Window
 671          * will yield:
 672          *
 673          *     x = readl(i)
 674          *         31                  0
 675          *         [ b3 | b2 | b1 | b0 ]
 676          *
 677          * If this value is stored into local memory on a Little-Endian system
 678          * it will show up correctly in local memory as:
 679          *
 680          *     ( ..., b0, b1, b2, b3, ... )
 681          *
 682          * But on a Big-Endian system, the store will show up in memory
 683          * incorrectly swizzled as:
 684          *
 685          *     ( ..., b3, b2, b1, b0, ... )
 686          *
 687          * So we need to account for this in the reads and writes to the
 688          * PCI-E Memory Window below by undoing the register read/write
 689          * swizzels.
 690          */
 691         while (len > 0) {
 692                 if (dir == T4_MEMORY_READ)
 693                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 694                                                 mem_base + offset));
 695                 else
 696                         t4_write_reg(adap, mem_base + offset,
 697                                      (__force u32)cpu_to_le32(*buf++));
 698                 offset += sizeof(__be32);
 699                 len -= sizeof(__be32);
 700
 701                 /* If we've reached the end of our current window aperture,
 702                  * move the PCI-E Memory Window on to the next.  Note that
 703                  * doing this here after "len" may be 0 allows us to set up
 704                  * the PCI-E Memory Window for a possible final residual
 705                  * transfer below ...
 706                  */
 707                 if (offset == mem_aperture) {
 708                         pos += mem_aperture;
 709                         offset = 0;
 710                         t4_memory_update_win(adap, win, pos | win_pf);
 711                 }
 712         }
 713
 714         /* If the original transfer had a length which wasn't a multiple of
 715          * 32-bits, now's where we need to finish off the transfer of the
 716          * residual amount.  The PCI-E Memory Window has already been moved
 717          * above (if necessary) to cover this final transfer.
 718          */
 719         if (resid)
 720                 t4_memory_rw_residual(adap, resid, mem_base + offset,
 721                                       (u8 *)buf, dir);
 722
 723         return 0;
 724 }
 725
 726 /* Return the specified PCI-E Configuration Space register from our Physical
 727  * Function.  We try first via a Firmware LDST Command since we prefer to let
 728  * the firmware own all of these registers, but if that fails we go for it
 729  * directly ourselves.
 730  */
 731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 732 {
 733         u32 val, ldst_addrspace;
 734
 735         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 736          * retrieve the specified PCI-E Configuration Space register.
 737          */
 738         struct fw_ldst_cmd ldst_cmd;
 739         int ret;
 740
 741         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 742         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 743         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 744                                                FW_CMD_REQUEST_F |
 745                                                FW_CMD_READ_F |
 746                                                ldst_addrspace);
 747         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 748         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 749         ldst_cmd.u.pcie.ctrl_to_fn =
 750                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 751         ldst_cmd.u.pcie.r = reg;
 752
 753         /* If the LDST Command succeeds, return the result, otherwise
 754          * fall through to reading it directly ourselves ...
 755          */
 756         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 757                          &ldst_cmd);
 758         if (ret == 0)
 759                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 760         else
 761                 /* Read the desired Configuration Space register via the PCI-E
 762                  * Backdoor mechanism.
 763                  */
 764                 t4_hw_pci_read_cfg4(adap, reg, &val);
 765         return val;
 766 }
 767
 768 /* Get the window based on base passed to it.
 769  * Window aperture is currently unhandled, but there is no use case for it
 770  * right now
 771  */
 772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 773                          u32 memwin_base)
 774 {
 775         u32 ret;
 776
 777         if (is_t4(adap->params.chip)) {
 778                 u32 bar0;
 779
 780                 /* Truncation intentional: we only read the bottom 32-bits of
 781                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 782                  * mechanism to read BAR0 instead of using
 783                  * pci_resource_start() because we could be operating from
 784                  * within a Virtual Machine which is trapping our accesses to
 785                  * our Configuration Space and we need to set up the PCI-E
 786                  * Memory Window decoders with the actual addresses which will
 787                  * be coming across the PCI-E link.
 788                  */
 789                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 790                 bar0 &= pci_mask;
 791                 adap->t4_bar0 = bar0;
 792
 793                 ret = bar0 + memwin_base;
 794         } else {
 795                 /* For T5, only relative offset inside the PCIe BAR is passed */
 796                 ret = memwin_base;
 797         }
 798         return ret;
 799 }
 800
 801 /* Get the default utility window (win0) used by everyone */
 802 u32 t4_get_util_window(struct adapter *adap)
 803 {
 804         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 805                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 806 }
 807
 808 /* Set up memory window for accessing adapter memory ranges.  (Read
 809  * back MA register to ensure that changes propagate before we attempt
 810  * to use the new values.)
 811  */
 812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 813 {
 814         t4_write_reg(adap,
 815                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 816                      memwin_base | BIR_V(0) |
 817                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 818         t4_read_reg(adap,
 819                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 820 }
 821
 822 /**
 823  *      t4_get_regs_len - return the size of the chips register set
 824  *      @adapter: the adapter
 825  *
 826  *      Returns the size of the chip's BAR0 register space.
 827  */
 828 unsigned int t4_get_regs_len(struct adapter *adapter)
 829 {
 830         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 831
 832         switch (chip_version) {
 833         case CHELSIO_T4:
 834                 return T4_REGMAP_SIZE;
 835
 836         case CHELSIO_T5:
 837         case CHELSIO_T6:
 838                 return T5_REGMAP_SIZE;
 839         }
 840
 841         dev_err(adapter->pdev_dev,
 842                 "Unsupported chip version %d\n", chip_version);
 843         return 0;
 844 }
 845
 846 /**
 847  *      t4_get_regs - read chip registers into provided buffer
 848  *      @adap: the adapter
 849  *      @buf: register buffer
 850  *      @buf_size: size (in bytes) of register buffer
 851  *
 852  *      If the provided register buffer isn't large enough for the chip's
 853  *      full register range, the register dump will be truncated to the
 854  *      register buffer's size.
 855  */
 856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 857 {
 858         static const unsigned int t4_reg_ranges[] = {
 859                 0x1008, 0x1108,
 860                 0x1180, 0x1184,
 861                 0x1190, 0x1194,
 862                 0x11a0, 0x11a4,
 863                 0x11b0, 0x11b4,
 864                 0x11fc, 0x123c,
 865                 0x1300, 0x173c,
 866                 0x1800, 0x18fc,
 867                 0x3000, 0x30d8,
 868                 0x30e0, 0x30e4,
 869                 0x30ec, 0x5910,
 870                 0x5920, 0x5924,
 871                 0x5960, 0x5960,
 872                 0x5968, 0x5968,
 873                 0x5970, 0x5970,
 874                 0x5978, 0x5978,
 875                 0x5980, 0x5980,
 876                 0x5988, 0x5988,
 877                 0x5990, 0x5990,
 878                 0x5998, 0x5998,
 879                 0x59a0, 0x59d4,
 880                 0x5a00, 0x5ae0,
 881                 0x5ae8, 0x5ae8,
 882                 0x5af0, 0x5af0,
 883                 0x5af8, 0x5af8,
 884                 0x6000, 0x6098,
 885                 0x6100, 0x6150,
 886                 0x6200, 0x6208,
 887                 0x6240, 0x6248,
 888                 0x6280, 0x62b0,
 889                 0x62c0, 0x6338,
 890                 0x6370, 0x638c,
 891                 0x6400, 0x643c,
 892                 0x6500, 0x6524,
 893                 0x6a00, 0x6a04,
 894                 0x6a14, 0x6a38,
 895                 0x6a60, 0x6a70,
 896                 0x6a78, 0x6a78,
 897                 0x6b00, 0x6b0c,
 898                 0x6b1c, 0x6b84,
 899                 0x6bf0, 0x6bf8,
 900                 0x6c00, 0x6c0c,
 901                 0x6c1c, 0x6c84,
 902                 0x6cf0, 0x6cf8,
 903                 0x6d00, 0x6d0c,
 904                 0x6d1c, 0x6d84,
 905                 0x6df0, 0x6df8,
 906                 0x6e00, 0x6e0c,
 907                 0x6e1c, 0x6e84,
 908                 0x6ef0, 0x6ef8,
 909                 0x6f00, 0x6f0c,
 910                 0x6f1c, 0x6f84,
 911                 0x6ff0, 0x6ff8,
 912                 0x7000, 0x700c,
 913                 0x701c, 0x7084,
 914                 0x70f0, 0x70f8,
 915                 0x7100, 0x710c,
 916                 0x711c, 0x7184,
 917                 0x71f0, 0x71f8,
 918                 0x7200, 0x720c,
 919                 0x721c, 0x7284,
 920                 0x72f0, 0x72f8,
 921                 0x7300, 0x730c,
 922                 0x731c, 0x7384,
 923                 0x73f0, 0x73f8,
 924                 0x7400, 0x7450,
 925                 0x7500, 0x7530,
 926                 0x7600, 0x760c,
 927                 0x7614, 0x761c,
 928                 0x7680, 0x76cc,
 929                 0x7700, 0x7798,
 930                 0x77c0, 0x77fc,
 931                 0x7900, 0x79fc,
 932                 0x7b00, 0x7b58,
 933                 0x7b60, 0x7b84,
 934                 0x7b8c, 0x7c38,
 935                 0x7d00, 0x7d38,
 936                 0x7d40, 0x7d80,
 937                 0x7d8c, 0x7ddc,
 938                 0x7de4, 0x7e04,
 939                 0x7e10, 0x7e1c,
 940                 0x7e24, 0x7e38,
 941                 0x7e40, 0x7e44,
 942                 0x7e4c, 0x7e78,
 943                 0x7e80, 0x7ea4,
 944                 0x7eac, 0x7edc,
 945                 0x7ee8, 0x7efc,
 946                 0x8dc0, 0x8e04,
 947                 0x8e10, 0x8e1c,
 948                 0x8e30, 0x8e78,
 949                 0x8ea0, 0x8eb8,
 950                 0x8ec0, 0x8f6c,
 951                 0x8fc0, 0x9008,
 952                 0x9010, 0x9058,
 953                 0x9060, 0x9060,
 954                 0x9068, 0x9074,
 955                 0x90fc, 0x90fc,
 956                 0x9400, 0x9408,
 957                 0x9410, 0x9458,
 958                 0x9600, 0x9600,
 959                 0x9608, 0x9638,
 960                 0x9640, 0x96bc,
 961                 0x9800, 0x9808,
 962                 0x9820, 0x983c,
 963                 0x9850, 0x9864,
 964                 0x9c00, 0x9c6c,
 965                 0x9c80, 0x9cec,
 966                 0x9d00, 0x9d6c,
 967                 0x9d80, 0x9dec,
 968                 0x9e00, 0x9e6c,
 969                 0x9e80, 0x9eec,
 970                 0x9f00, 0x9f6c,
 971                 0x9f80, 0x9fec,
 972                 0xd004, 0xd004,
 973                 0xd010, 0xd03c,
 974                 0xdfc0, 0xdfe0,
 975                 0xe000, 0xea7c,
 976                 0xf000, 0x11110,
 977                 0x11118, 0x11190,
 978                 0x19040, 0x1906c,
 979                 0x19078, 0x19080,
 980                 0x1908c, 0x190e4,
 981                 0x190f0, 0x190f8,
 982                 0x19100, 0x19110,
 983                 0x19120, 0x19124,
 984                 0x19150, 0x19194,
 985                 0x1919c, 0x191b0,
 986                 0x191d0, 0x191e8,
 987                 0x19238, 0x1924c,
 988                 0x193f8, 0x1943c,
 989                 0x1944c, 0x19474,
 990                 0x19490, 0x194e0,
 991                 0x194f0, 0x194f8,
 992                 0x19800, 0x19c08,
 993                 0x19c10, 0x19c90,
 994                 0x19ca0, 0x19ce4,
 995                 0x19cf0, 0x19d40,
 996                 0x19d50, 0x19d94,
 997                 0x19da0, 0x19de8,
 998                 0x19df0, 0x19e40,
 999                 0x19e50, 0x19e90,
1000                 0x19ea0, 0x19f4c,
1001                 0x1a000, 0x1a004,
1002                 0x1a010, 0x1a06c,
1003                 0x1a0b0, 0x1a0e4,
1004                 0x1a0ec, 0x1a0f4,
1005                 0x1a100, 0x1a108,
1006                 0x1a114, 0x1a120,
1007                 0x1a128, 0x1a130,
1008                 0x1a138, 0x1a138,
1009                 0x1a190, 0x1a1c4,
1010                 0x1a1fc, 0x1a1fc,
1011                 0x1e040, 0x1e04c,
1012                 0x1e284, 0x1e28c,
1013                 0x1e2c0, 0x1e2c0,
1014                 0x1e2e0, 0x1e2e0,
1015                 0x1e300, 0x1e384,
1016                 0x1e3c0, 0x1e3c8,
1017                 0x1e440, 0x1e44c,
1018                 0x1e684, 0x1e68c,
1019                 0x1e6c0, 0x1e6c0,
1020                 0x1e6e0, 0x1e6e0,
1021                 0x1e700, 0x1e784,
1022                 0x1e7c0, 0x1e7c8,
1023                 0x1e840, 0x1e84c,
1024                 0x1ea84, 0x1ea8c,
1025                 0x1eac0, 0x1eac0,
1026                 0x1eae0, 0x1eae0,
1027                 0x1eb00, 0x1eb84,
1028                 0x1ebc0, 0x1ebc8,
1029                 0x1ec40, 0x1ec4c,
1030                 0x1ee84, 0x1ee8c,
1031                 0x1eec0, 0x1eec0,
1032                 0x1eee0, 0x1eee0,
1033                 0x1ef00, 0x1ef84,
1034                 0x1efc0, 0x1efc8,
1035                 0x1f040, 0x1f04c,
1036                 0x1f284, 0x1f28c,
1037                 0x1f2c0, 0x1f2c0,
1038                 0x1f2e0, 0x1f2e0,
1039                 0x1f300, 0x1f384,
1040                 0x1f3c0, 0x1f3c8,
1041                 0x1f440, 0x1f44c,
1042                 0x1f684, 0x1f68c,
1043                 0x1f6c0, 0x1f6c0,
1044                 0x1f6e0, 0x1f6e0,
1045                 0x1f700, 0x1f784,
1046                 0x1f7c0, 0x1f7c8,
1047                 0x1f840, 0x1f84c,
1048                 0x1fa84, 0x1fa8c,
1049                 0x1fac0, 0x1fac0,
1050                 0x1fae0, 0x1fae0,
1051                 0x1fb00, 0x1fb84,
1052                 0x1fbc0, 0x1fbc8,
1053                 0x1fc40, 0x1fc4c,
1054                 0x1fe84, 0x1fe8c,
1055                 0x1fec0, 0x1fec0,
1056                 0x1fee0, 0x1fee0,
1057                 0x1ff00, 0x1ff84,
1058                 0x1ffc0, 0x1ffc8,
1059                 0x20000, 0x2002c,
1060                 0x20100, 0x2013c,
1061                 0x20190, 0x201a0,
1062                 0x201a8, 0x201b8,
1063                 0x201c4, 0x201c8,
1064                 0x20200, 0x20318,
1065                 0x20400, 0x204b4,
1066                 0x204c0, 0x20528,
1067                 0x20540, 0x20614,
1068                 0x21000, 0x21040,
1069                 0x2104c, 0x21060,
1070                 0x210c0, 0x210ec,
1071                 0x21200, 0x21268,
1072                 0x21270, 0x21284,
1073                 0x212fc, 0x21388,
1074                 0x21400, 0x21404,
1075                 0x21500, 0x21500,
1076                 0x21510, 0x21518,
1077                 0x2152c, 0x21530,
1078                 0x2153c, 0x2153c,
1079                 0x21550, 0x21554,
1080                 0x21600, 0x21600,
1081                 0x21608, 0x2161c,
1082                 0x21624, 0x21628,
1083                 0x21630, 0x21634,
1084                 0x2163c, 0x2163c,
1085                 0x21700, 0x2171c,
1086                 0x21780, 0x2178c,
1087                 0x21800, 0x21818,
1088                 0x21820, 0x21828,
1089                 0x21830, 0x21848,
1090                 0x21850, 0x21854,
1091                 0x21860, 0x21868,
1092                 0x21870, 0x21870,
1093                 0x21878, 0x21898,
1094                 0x218a0, 0x218a8,
1095                 0x218b0, 0x218c8,
1096                 0x218d0, 0x218d4,
1097                 0x218e0, 0x218e8,
1098                 0x218f0, 0x218f0,
1099                 0x218f8, 0x21a18,
1100                 0x21a20, 0x21a28,
1101                 0x21a30, 0x21a48,
1102                 0x21a50, 0x21a54,
1103                 0x21a60, 0x21a68,
1104                 0x21a70, 0x21a70,
1105                 0x21a78, 0x21a98,
1106                 0x21aa0, 0x21aa8,
1107                 0x21ab0, 0x21ac8,
1108                 0x21ad0, 0x21ad4,
1109                 0x21ae0, 0x21ae8,
1110                 0x21af0, 0x21af0,
1111                 0x21af8, 0x21c18,
1112                 0x21c20, 0x21c20,
1113                 0x21c28, 0x21c30,
1114                 0x21c38, 0x21c38,
1115                 0x21c80, 0x21c98,
1116                 0x21ca0, 0x21ca8,
1117                 0x21cb0, 0x21cc8,
1118                 0x21cd0, 0x21cd4,
1119                 0x21ce0, 0x21ce8,
1120                 0x21cf0, 0x21cf0,
1121                 0x21cf8, 0x21d7c,
1122                 0x21e00, 0x21e04,
1123                 0x22000, 0x2202c,
1124                 0x22100, 0x2213c,
1125                 0x22190, 0x221a0,
1126                 0x221a8, 0x221b8,
1127                 0x221c4, 0x221c8,
1128                 0x22200, 0x22318,
1129                 0x22400, 0x224b4,
1130                 0x224c0, 0x22528,
1131                 0x22540, 0x22614,
1132                 0x23000, 0x23040,
1133                 0x2304c, 0x23060,
1134                 0x230c0, 0x230ec,
1135                 0x23200, 0x23268,
1136                 0x23270, 0x23284,
1137                 0x232fc, 0x23388,
1138                 0x23400, 0x23404,
1139                 0x23500, 0x23500,
1140                 0x23510, 0x23518,
1141                 0x2352c, 0x23530,
1142                 0x2353c, 0x2353c,
1143                 0x23550, 0x23554,
1144                 0x23600, 0x23600,
1145                 0x23608, 0x2361c,
1146                 0x23624, 0x23628,
1147                 0x23630, 0x23634,
1148                 0x2363c, 0x2363c,
1149                 0x23700, 0x2371c,
1150                 0x23780, 0x2378c,
1151                 0x23800, 0x23818,
1152                 0x23820, 0x23828,
1153                 0x23830, 0x23848,
1154                 0x23850, 0x23854,
1155                 0x23860, 0x23868,
1156                 0x23870, 0x23870,
1157                 0x23878, 0x23898,
1158                 0x238a0, 0x238a8,
1159                 0x238b0, 0x238c8,
1160                 0x238d0, 0x238d4,
1161                 0x238e0, 0x238e8,
1162                 0x238f0, 0x238f0,
1163                 0x238f8, 0x23a18,
1164                 0x23a20, 0x23a28,
1165                 0x23a30, 0x23a48,
1166                 0x23a50, 0x23a54,
1167                 0x23a60, 0x23a68,
1168                 0x23a70, 0x23a70,
1169                 0x23a78, 0x23a98,
1170                 0x23aa0, 0x23aa8,
1171                 0x23ab0, 0x23ac8,
1172                 0x23ad0, 0x23ad4,
1173                 0x23ae0, 0x23ae8,
1174                 0x23af0, 0x23af0,
1175                 0x23af8, 0x23c18,
1176                 0x23c20, 0x23c20,
1177                 0x23c28, 0x23c30,
1178                 0x23c38, 0x23c38,
1179                 0x23c80, 0x23c98,
1180                 0x23ca0, 0x23ca8,
1181                 0x23cb0, 0x23cc8,
1182                 0x23cd0, 0x23cd4,
1183                 0x23ce0, 0x23ce8,
1184                 0x23cf0, 0x23cf0,
1185                 0x23cf8, 0x23d7c,
1186                 0x23e00, 0x23e04,
1187                 0x24000, 0x2402c,
1188                 0x24100, 0x2413c,
1189                 0x24190, 0x241a0,
1190                 0x241a8, 0x241b8,
1191                 0x241c4, 0x241c8,
1192                 0x24200, 0x24318,
1193                 0x24400, 0x244b4,
1194                 0x244c0, 0x24528,
1195                 0x24540, 0x24614,
1196                 0x25000, 0x25040,
1197                 0x2504c, 0x25060,
1198                 0x250c0, 0x250ec,
1199                 0x25200, 0x25268,
1200                 0x25270, 0x25284,
1201                 0x252fc, 0x25388,
1202                 0x25400, 0x25404,
1203                 0x25500, 0x25500,
1204                 0x25510, 0x25518,
1205                 0x2552c, 0x25530,
1206                 0x2553c, 0x2553c,
1207                 0x25550, 0x25554,
1208                 0x25600, 0x25600,
1209                 0x25608, 0x2561c,
1210                 0x25624, 0x25628,
1211                 0x25630, 0x25634,
1212                 0x2563c, 0x2563c,
1213                 0x25700, 0x2571c,
1214                 0x25780, 0x2578c,
1215                 0x25800, 0x25818,
1216                 0x25820, 0x25828,
1217                 0x25830, 0x25848,
1218                 0x25850, 0x25854,
1219                 0x25860, 0x25868,
1220                 0x25870, 0x25870,
1221                 0x25878, 0x25898,
1222                 0x258a0, 0x258a8,
1223                 0x258b0, 0x258c8,
1224                 0x258d0, 0x258d4,
1225                 0x258e0, 0x258e8,
1226                 0x258f0, 0x258f0,
1227                 0x258f8, 0x25a18,
1228                 0x25a20, 0x25a28,
1229                 0x25a30, 0x25a48,
1230                 0x25a50, 0x25a54,
1231                 0x25a60, 0x25a68,
1232                 0x25a70, 0x25a70,
1233                 0x25a78, 0x25a98,
1234                 0x25aa0, 0x25aa8,
1235                 0x25ab0, 0x25ac8,
1236                 0x25ad0, 0x25ad4,
1237                 0x25ae0, 0x25ae8,
1238                 0x25af0, 0x25af0,
1239                 0x25af8, 0x25c18,
1240                 0x25c20, 0x25c20,
1241                 0x25c28, 0x25c30,
1242                 0x25c38, 0x25c38,
1243                 0x25c80, 0x25c98,
1244                 0x25ca0, 0x25ca8,
1245                 0x25cb0, 0x25cc8,
1246                 0x25cd0, 0x25cd4,
1247                 0x25ce0, 0x25ce8,
1248                 0x25cf0, 0x25cf0,
1249                 0x25cf8, 0x25d7c,
1250                 0x25e00, 0x25e04,
1251                 0x26000, 0x2602c,
1252                 0x26100, 0x2613c,
1253                 0x26190, 0x261a0,
1254                 0x261a8, 0x261b8,
1255                 0x261c4, 0x261c8,
1256                 0x26200, 0x26318,
1257                 0x26400, 0x264b4,
1258                 0x264c0, 0x26528,
1259                 0x26540, 0x26614,
1260                 0x27000, 0x27040,
1261                 0x2704c, 0x27060,
1262                 0x270c0, 0x270ec,
1263                 0x27200, 0x27268,
1264                 0x27270, 0x27284,
1265                 0x272fc, 0x27388,
1266                 0x27400, 0x27404,
1267                 0x27500, 0x27500,
1268                 0x27510, 0x27518,
1269                 0x2752c, 0x27530,
1270                 0x2753c, 0x2753c,
1271                 0x27550, 0x27554,
1272                 0x27600, 0x27600,
1273                 0x27608, 0x2761c,
1274                 0x27624, 0x27628,
1275                 0x27630, 0x27634,
1276                 0x2763c, 0x2763c,
1277                 0x27700, 0x2771c,
1278                 0x27780, 0x2778c,
1279                 0x27800, 0x27818,
1280                 0x27820, 0x27828,
1281                 0x27830, 0x27848,
1282                 0x27850, 0x27854,
1283                 0x27860, 0x27868,
1284                 0x27870, 0x27870,
1285                 0x27878, 0x27898,
1286                 0x278a0, 0x278a8,
1287                 0x278b0, 0x278c8,
1288                 0x278d0, 0x278d4,
1289                 0x278e0, 0x278e8,
1290                 0x278f0, 0x278f0,
1291                 0x278f8, 0x27a18,
1292                 0x27a20, 0x27a28,
1293                 0x27a30, 0x27a48,
1294                 0x27a50, 0x27a54,
1295                 0x27a60, 0x27a68,
1296                 0x27a70, 0x27a70,
1297                 0x27a78, 0x27a98,
1298                 0x27aa0, 0x27aa8,
1299                 0x27ab0, 0x27ac8,
1300                 0x27ad0, 0x27ad4,
1301                 0x27ae0, 0x27ae8,
1302                 0x27af0, 0x27af0,
1303                 0x27af8, 0x27c18,
1304                 0x27c20, 0x27c20,
1305                 0x27c28, 0x27c30,
1306                 0x27c38, 0x27c38,
1307                 0x27c80, 0x27c98,
1308                 0x27ca0, 0x27ca8,
1309                 0x27cb0, 0x27cc8,
1310                 0x27cd0, 0x27cd4,
1311                 0x27ce0, 0x27ce8,
1312                 0x27cf0, 0x27cf0,
1313                 0x27cf8, 0x27d7c,
1314                 0x27e00, 0x27e04,
1315         };
1316
1317         static const unsigned int t5_reg_ranges[] = {
1318                 0x1008, 0x10c0,
1319                 0x10cc, 0x10f8,
1320                 0x1100, 0x1100,
1321                 0x110c, 0x1148,
1322                 0x1180, 0x1184,
1323                 0x1190, 0x1194,
1324                 0x11a0, 0x11a4,
1325                 0x11b0, 0x11b4,
1326                 0x11fc, 0x123c,
1327                 0x1280, 0x173c,
1328                 0x1800, 0x18fc,
1329                 0x3000, 0x3028,
1330                 0x3060, 0x30b0,
1331                 0x30b8, 0x30d8,
1332                 0x30e0, 0x30fc,
1333                 0x3140, 0x357c,
1334                 0x35a8, 0x35cc,
1335                 0x35ec, 0x35ec,
1336                 0x3600, 0x5624,
1337                 0x56cc, 0x56ec,
1338                 0x56f4, 0x5720,
1339                 0x5728, 0x575c,
1340                 0x580c, 0x5814,
1341                 0x5890, 0x589c,
1342                 0x58a4, 0x58ac,
1343                 0x58b8, 0x58bc,
1344                 0x5940, 0x59c8,
1345                 0x59d0, 0x59dc,
1346                 0x59fc, 0x5a18,
1347                 0x5a60, 0x5a70,
1348                 0x5a80, 0x5a9c,
1349                 0x5b94, 0x5bfc,
1350                 0x6000, 0x6020,
1351                 0x6028, 0x6040,
1352                 0x6058, 0x609c,
1353                 0x60a8, 0x614c,
1354                 0x7700, 0x7798,
1355                 0x77c0, 0x78fc,
1356                 0x7b00, 0x7b58,
1357                 0x7b60, 0x7b84,
1358                 0x7b8c, 0x7c54,
1359                 0x7d00, 0x7d38,
1360                 0x7d40, 0x7d80,
1361                 0x7d8c, 0x7ddc,
1362                 0x7de4, 0x7e04,
1363                 0x7e10, 0x7e1c,
1364                 0x7e24, 0x7e38,
1365                 0x7e40, 0x7e44,
1366                 0x7e4c, 0x7e78,
1367                 0x7e80, 0x7edc,
1368                 0x7ee8, 0x7efc,
1369                 0x8dc0, 0x8de0,
1370                 0x8df8, 0x8e04,
1371                 0x8e10, 0x8e84,
1372                 0x8ea0, 0x8f84,
1373                 0x8fc0, 0x9058,
1374                 0x9060, 0x9060,
1375                 0x9068, 0x90f8,
1376                 0x9400, 0x9408,
1377                 0x9410, 0x9470,
1378                 0x9600, 0x9600,
1379                 0x9608, 0x9638,
1380                 0x9640, 0x96f4,
1381                 0x9800, 0x9808,
1382                 0x9820, 0x983c,
1383                 0x9850, 0x9864,
1384                 0x9c00, 0x9c6c,
1385                 0x9c80, 0x9cec,
1386                 0x9d00, 0x9d6c,
1387                 0x9d80, 0x9dec,
1388                 0x9e00, 0x9e6c,
1389                 0x9e80, 0x9eec,
1390                 0x9f00, 0x9f6c,
1391                 0x9f80, 0xa020,
1392                 0xd004, 0xd004,
1393                 0xd010, 0xd03c,
1394                 0xdfc0, 0xdfe0,
1395                 0xe000, 0x1106c,
1396                 0x11074, 0x11088,
1397                 0x1109c, 0x1117c,
1398                 0x11190, 0x11204,
1399                 0x19040, 0x1906c,
1400                 0x19078, 0x19080,
1401                 0x1908c, 0x190e8,
1402                 0x190f0, 0x190f8,
1403                 0x19100, 0x19110,
1404                 0x19120, 0x19124,
1405                 0x19150, 0x19194,
1406                 0x1919c, 0x191b0,
1407                 0x191d0, 0x191e8,
1408                 0x19238, 0x19290,
1409                 0x193f8, 0x19428,
1410                 0x19430, 0x19444,
1411                 0x1944c, 0x1946c,
1412                 0x19474, 0x19474,
1413                 0x19490, 0x194cc,
1414                 0x194f0, 0x194f8,
1415                 0x19c00, 0x19c08,
1416                 0x19c10, 0x19c60,
1417                 0x19c94, 0x19ce4,
1418                 0x19cf0, 0x19d40,
1419                 0x19d50, 0x19d94,
1420                 0x19da0, 0x19de8,
1421                 0x19df0, 0x19e10,
1422                 0x19e50, 0x19e90,
1423                 0x19ea0, 0x19f24,
1424                 0x19f34, 0x19f34,
1425                 0x19f40, 0x19f50,
1426                 0x19f90, 0x19fb4,
1427                 0x19fc4, 0x19fe4,
1428                 0x1a000, 0x1a004,
1429                 0x1a010, 0x1a06c,
1430                 0x1a0b0, 0x1a0e4,
1431                 0x1a0ec, 0x1a0f8,
1432                 0x1a100, 0x1a108,
1433                 0x1a114, 0x1a120,
1434                 0x1a128, 0x1a130,
1435                 0x1a138, 0x1a138,
1436                 0x1a190, 0x1a1c4,
1437                 0x1a1fc, 0x1a1fc,
1438                 0x1e008, 0x1e00c,
1439                 0x1e040, 0x1e044,
1440                 0x1e04c, 0x1e04c,
1441                 0x1e284, 0x1e290,
1442                 0x1e2c0, 0x1e2c0,
1443                 0x1e2e0, 0x1e2e0,
1444                 0x1e300, 0x1e384,
1445                 0x1e3c0, 0x1e3c8,
1446                 0x1e408, 0x1e40c,
1447                 0x1e440, 0x1e444,
1448                 0x1e44c, 0x1e44c,
1449                 0x1e684, 0x1e690,
1450                 0x1e6c0, 0x1e6c0,
1451                 0x1e6e0, 0x1e6e0,
1452                 0x1e700, 0x1e784,
1453                 0x1e7c0, 0x1e7c8,
1454                 0x1e808, 0x1e80c,
1455                 0x1e840, 0x1e844,
1456                 0x1e84c, 0x1e84c,
1457                 0x1ea84, 0x1ea90,
1458                 0x1eac0, 0x1eac0,
1459                 0x1eae0, 0x1eae0,
1460                 0x1eb00, 0x1eb84,
1461                 0x1ebc0, 0x1ebc8,
1462                 0x1ec08, 0x1ec0c,
1463                 0x1ec40, 0x1ec44,
1464                 0x1ec4c, 0x1ec4c,
1465                 0x1ee84, 0x1ee90,
1466                 0x1eec0, 0x1eec0,
1467                 0x1eee0, 0x1eee0,
1468                 0x1ef00, 0x1ef84,
1469                 0x1efc0, 0x1efc8,
1470                 0x1f008, 0x1f00c,
1471                 0x1f040, 0x1f044,
1472                 0x1f04c, 0x1f04c,
1473                 0x1f284, 0x1f290,
1474                 0x1f2c0, 0x1f2c0,
1475                 0x1f2e0, 0x1f2e0,
1476                 0x1f300, 0x1f384,
1477                 0x1f3c0, 0x1f3c8,
1478                 0x1f408, 0x1f40c,
1479                 0x1f440, 0x1f444,
1480                 0x1f44c, 0x1f44c,
1481                 0x1f684, 0x1f690,
1482                 0x1f6c0, 0x1f6c0,
1483                 0x1f6e0, 0x1f6e0,
1484                 0x1f700, 0x1f784,
1485                 0x1f7c0, 0x1f7c8,
1486                 0x1f808, 0x1f80c,
1487                 0x1f840, 0x1f844,
1488                 0x1f84c, 0x1f84c,
1489                 0x1fa84, 0x1fa90,
1490                 0x1fac0, 0x1fac0,
1491                 0x1fae0, 0x1fae0,
1492                 0x1fb00, 0x1fb84,
1493                 0x1fbc0, 0x1fbc8,
1494                 0x1fc08, 0x1fc0c,
1495                 0x1fc40, 0x1fc44,
1496                 0x1fc4c, 0x1fc4c,
1497                 0x1fe84, 0x1fe90,
1498                 0x1fec0, 0x1fec0,
1499                 0x1fee0, 0x1fee0,
1500                 0x1ff00, 0x1ff84,
1501                 0x1ffc0, 0x1ffc8,
1502                 0x30000, 0x30030,
1503                 0x30100, 0x30144,
1504                 0x30190, 0x301a0,
1505                 0x301a8, 0x301b8,
1506                 0x301c4, 0x301c8,
1507                 0x301d0, 0x301d0,
1508                 0x30200, 0x30318,
1509                 0x30400, 0x304b4,
1510                 0x304c0, 0x3052c,
1511                 0x30540, 0x3061c,
1512                 0x30800, 0x30828,
1513                 0x30834, 0x30834,
1514                 0x308c0, 0x30908,
1515                 0x30910, 0x309ac,
1516                 0x30a00, 0x30a14,
1517                 0x30a1c, 0x30a2c,
1518                 0x30a44, 0x30a50,
1519                 0x30a74, 0x30a74,
1520                 0x30a7c, 0x30afc,
1521                 0x30b08, 0x30c24,
1522                 0x30d00, 0x30d00,
1523                 0x30d08, 0x30d14,
1524                 0x30d1c, 0x30d20,
1525                 0x30d3c, 0x30d3c,
1526                 0x30d48, 0x30d50,
1527                 0x31200, 0x3120c,
1528                 0x31220, 0x31220,
1529                 0x31240, 0x31240,
1530                 0x31600, 0x3160c,
1531                 0x31a00, 0x31a1c,
1532                 0x31e00, 0x31e20,
1533                 0x31e38, 0x31e3c,
1534                 0x31e80, 0x31e80,
1535                 0x31e88, 0x31ea8,
1536                 0x31eb0, 0x31eb4,
1537                 0x31ec8, 0x31ed4,
1538                 0x31fb8, 0x32004,
1539                 0x32200, 0x32200,
1540                 0x32208, 0x32240,
1541                 0x32248, 0x32280,
1542                 0x32288, 0x322c0,
1543                 0x322c8, 0x322fc,
1544                 0x32600, 0x32630,
1545                 0x32a00, 0x32abc,
1546                 0x32b00, 0x32b10,
1547                 0x32b20, 0x32b30,
1548                 0x32b40, 0x32b50,
1549                 0x32b60, 0x32b70,
1550                 0x33000, 0x33028,
1551                 0x33030, 0x33048,
1552                 0x33060, 0x33068,
1553                 0x33070, 0x3309c,
1554                 0x330f0, 0x33128,
1555                 0x33130, 0x33148,
1556                 0x33160, 0x33168,
1557                 0x33170, 0x3319c,
1558                 0x331f0, 0x33238,
1559                 0x33240, 0x33240,
1560                 0x33248, 0x33250,
1561                 0x3325c, 0x33264,
1562                 0x33270, 0x332b8,
1563                 0x332c0, 0x332e4,
1564                 0x332f8, 0x33338,
1565                 0x33340, 0x33340,
1566                 0x33348, 0x33350,
1567                 0x3335c, 0x33364,
1568                 0x33370, 0x333b8,
1569                 0x333c0, 0x333e4,
1570                 0x333f8, 0x33428,
1571                 0x33430, 0x33448,
1572                 0x33460, 0x33468,
1573                 0x33470, 0x3349c,
1574                 0x334f0, 0x33528,
1575                 0x33530, 0x33548,
1576                 0x33560, 0x33568,
1577                 0x33570, 0x3359c,
1578                 0x335f0, 0x33638,
1579                 0x33640, 0x33640,
1580                 0x33648, 0x33650,
1581                 0x3365c, 0x33664,
1582                 0x33670, 0x336b8,
1583                 0x336c0, 0x336e4,
1584                 0x336f8, 0x33738,
1585                 0x33740, 0x33740,
1586                 0x33748, 0x33750,
1587                 0x3375c, 0x33764,
1588                 0x33770, 0x337b8,
1589                 0x337c0, 0x337e4,
1590                 0x337f8, 0x337fc,
1591                 0x33814, 0x33814,
1592                 0x3382c, 0x3382c,
1593                 0x33880, 0x3388c,
1594                 0x338e8, 0x338ec,
1595                 0x33900, 0x33928,
1596                 0x33930, 0x33948,
1597                 0x33960, 0x33968,
1598                 0x33970, 0x3399c,
1599                 0x339f0, 0x33a38,
1600                 0x33a40, 0x33a40,
1601                 0x33a48, 0x33a50,
1602                 0x33a5c, 0x33a64,
1603                 0x33a70, 0x33ab8,
1604                 0x33ac0, 0x33ae4,
1605                 0x33af8, 0x33b10,
1606                 0x33b28, 0x33b28,
1607                 0x33b3c, 0x33b50,
1608                 0x33bf0, 0x33c10,
1609                 0x33c28, 0x33c28,
1610                 0x33c3c, 0x33c50,
1611                 0x33cf0, 0x33cfc,
1612                 0x34000, 0x34030,
1613                 0x34100, 0x34144,
1614                 0x34190, 0x341a0,
1615                 0x341a8, 0x341b8,
1616                 0x341c4, 0x341c8,
1617                 0x341d0, 0x341d0,
1618                 0x34200, 0x34318,
1619                 0x34400, 0x344b4,
1620                 0x344c0, 0x3452c,
1621                 0x34540, 0x3461c,
1622                 0x34800, 0x34828,
1623                 0x34834, 0x34834,
1624                 0x348c0, 0x34908,
1625                 0x34910, 0x349ac,
1626                 0x34a00, 0x34a14,
1627                 0x34a1c, 0x34a2c,
1628                 0x34a44, 0x34a50,
1629                 0x34a74, 0x34a74,
1630                 0x34a7c, 0x34afc,
1631                 0x34b08, 0x34c24,
1632                 0x34d00, 0x34d00,
1633                 0x34d08, 0x34d14,
1634                 0x34d1c, 0x34d20,
1635                 0x34d3c, 0x34d3c,
1636                 0x34d48, 0x34d50,
1637                 0x35200, 0x3520c,
1638                 0x35220, 0x35220,
1639                 0x35240, 0x35240,
1640                 0x35600, 0x3560c,
1641                 0x35a00, 0x35a1c,
1642                 0x35e00, 0x35e20,
1643                 0x35e38, 0x35e3c,
1644                 0x35e80, 0x35e80,
1645                 0x35e88, 0x35ea8,
1646                 0x35eb0, 0x35eb4,
1647                 0x35ec8, 0x35ed4,
1648                 0x35fb8, 0x36004,
1649                 0x36200, 0x36200,
1650                 0x36208, 0x36240,
1651                 0x36248, 0x36280,
1652                 0x36288, 0x362c0,
1653                 0x362c8, 0x362fc,
1654                 0x36600, 0x36630,
1655                 0x36a00, 0x36abc,
1656                 0x36b00, 0x36b10,
1657                 0x36b20, 0x36b30,
1658                 0x36b40, 0x36b50,
1659                 0x36b60, 0x36b70,
1660                 0x37000, 0x37028,
1661                 0x37030, 0x37048,
1662                 0x37060, 0x37068,
1663                 0x37070, 0x3709c,
1664                 0x370f0, 0x37128,
1665                 0x37130, 0x37148,
1666                 0x37160, 0x37168,
1667                 0x37170, 0x3719c,
1668                 0x371f0, 0x37238,
1669                 0x37240, 0x37240,
1670                 0x37248, 0x37250,
1671                 0x3725c, 0x37264,
1672                 0x37270, 0x372b8,
1673                 0x372c0, 0x372e4,
1674                 0x372f8, 0x37338,
1675                 0x37340, 0x37340,
1676                 0x37348, 0x37350,
1677                 0x3735c, 0x37364,
1678                 0x37370, 0x373b8,
1679                 0x373c0, 0x373e4,
1680                 0x373f8, 0x37428,
1681                 0x37430, 0x37448,
1682                 0x37460, 0x37468,
1683                 0x37470, 0x3749c,
1684                 0x374f0, 0x37528,
1685                 0x37530, 0x37548,
1686                 0x37560, 0x37568,
1687                 0x37570, 0x3759c,
1688                 0x375f0, 0x37638,
1689                 0x37640, 0x37640,
1690                 0x37648, 0x37650,
1691                 0x3765c, 0x37664,
1692                 0x37670, 0x376b8,
1693                 0x376c0, 0x376e4,
1694                 0x376f8, 0x37738,
1695                 0x37740, 0x37740,
1696                 0x37748, 0x37750,
1697                 0x3775c, 0x37764,
1698                 0x37770, 0x377b8,
1699                 0x377c0, 0x377e4,
1700                 0x377f8, 0x377fc,
1701                 0x37814, 0x37814,
1702                 0x3782c, 0x3782c,
1703                 0x37880, 0x3788c,
1704                 0x378e8, 0x378ec,
1705                 0x37900, 0x37928,
1706                 0x37930, 0x37948,
1707                 0x37960, 0x37968,
1708                 0x37970, 0x3799c,
1709                 0x379f0, 0x37a38,
1710                 0x37a40, 0x37a40,
1711                 0x37a48, 0x37a50,
1712                 0x37a5c, 0x37a64,
1713                 0x37a70, 0x37ab8,
1714                 0x37ac0, 0x37ae4,
1715                 0x37af8, 0x37b10,
1716                 0x37b28, 0x37b28,
1717                 0x37b3c, 0x37b50,
1718                 0x37bf0, 0x37c10,
1719                 0x37c28, 0x37c28,
1720                 0x37c3c, 0x37c50,
1721                 0x37cf0, 0x37cfc,
1722                 0x38000, 0x38030,
1723                 0x38100, 0x38144,
1724                 0x38190, 0x381a0,
1725                 0x381a8, 0x381b8,
1726                 0x381c4, 0x381c8,
1727                 0x381d0, 0x381d0,
1728                 0x38200, 0x38318,
1729                 0x38400, 0x384b4,
1730                 0x384c0, 0x3852c,
1731                 0x38540, 0x3861c,
1732                 0x38800, 0x38828,
1733                 0x38834, 0x38834,
1734                 0x388c0, 0x38908,
1735                 0x38910, 0x389ac,
1736                 0x38a00, 0x38a14,
1737                 0x38a1c, 0x38a2c,
1738                 0x38a44, 0x38a50,
1739                 0x38a74, 0x38a74,
1740                 0x38a7c, 0x38afc,
1741                 0x38b08, 0x38c24,
1742                 0x38d00, 0x38d00,
1743                 0x38d08, 0x38d14,
1744                 0x38d1c, 0x38d20,
1745                 0x38d3c, 0x38d3c,
1746                 0x38d48, 0x38d50,
1747                 0x39200, 0x3920c,
1748                 0x39220, 0x39220,
1749                 0x39240, 0x39240,
1750                 0x39600, 0x3960c,
1751                 0x39a00, 0x39a1c,
1752                 0x39e00, 0x39e20,
1753                 0x39e38, 0x39e3c,
1754                 0x39e80, 0x39e80,
1755                 0x39e88, 0x39ea8,
1756                 0x39eb0, 0x39eb4,
1757                 0x39ec8, 0x39ed4,
1758                 0x39fb8, 0x3a004,
1759                 0x3a200, 0x3a200,
1760                 0x3a208, 0x3a240,
1761                 0x3a248, 0x3a280,
1762                 0x3a288, 0x3a2c0,
1763                 0x3a2c8, 0x3a2fc,
1764                 0x3a600, 0x3a630,
1765                 0x3aa00, 0x3aabc,
1766                 0x3ab00, 0x3ab10,
1767                 0x3ab20, 0x3ab30,
1768                 0x3ab40, 0x3ab50,
1769                 0x3ab60, 0x3ab70,
1770                 0x3b000, 0x3b028,
1771                 0x3b030, 0x3b048,
1772                 0x3b060, 0x3b068,
1773                 0x3b070, 0x3b09c,
1774                 0x3b0f0, 0x3b128,
1775                 0x3b130, 0x3b148,
1776                 0x3b160, 0x3b168,
1777                 0x3b170, 0x3b19c,
1778                 0x3b1f0, 0x3b238,
1779                 0x3b240, 0x3b240,
1780                 0x3b248, 0x3b250,
1781                 0x3b25c, 0x3b264,
1782                 0x3b270, 0x3b2b8,
1783                 0x3b2c0, 0x3b2e4,
1784                 0x3b2f8, 0x3b338,
1785                 0x3b340, 0x3b340,
1786                 0x3b348, 0x3b350,
1787                 0x3b35c, 0x3b364,
1788                 0x3b370, 0x3b3b8,
1789                 0x3b3c0, 0x3b3e4,
1790                 0x3b3f8, 0x3b428,
1791                 0x3b430, 0x3b448,
1792                 0x3b460, 0x3b468,
1793                 0x3b470, 0x3b49c,
1794                 0x3b4f0, 0x3b528,
1795                 0x3b530, 0x3b548,
1796                 0x3b560, 0x3b568,
1797                 0x3b570, 0x3b59c,
1798                 0x3b5f0, 0x3b638,
1799                 0x3b640, 0x3b640,
1800                 0x3b648, 0x3b650,
1801                 0x3b65c, 0x3b664,
1802                 0x3b670, 0x3b6b8,
1803                 0x3b6c0, 0x3b6e4,
1804                 0x3b6f8, 0x3b738,
1805                 0x3b740, 0x3b740,
1806                 0x3b748, 0x3b750,
1807                 0x3b75c, 0x3b764,
1808                 0x3b770, 0x3b7b8,
1809                 0x3b7c0, 0x3b7e4,
1810                 0x3b7f8, 0x3b7fc,
1811                 0x3b814, 0x3b814,
1812                 0x3b82c, 0x3b82c,
1813                 0x3b880, 0x3b88c,
1814                 0x3b8e8, 0x3b8ec,
1815                 0x3b900, 0x3b928,
1816                 0x3b930, 0x3b948,
1817                 0x3b960, 0x3b968,
1818                 0x3b970, 0x3b99c,
1819                 0x3b9f0, 0x3ba38,
1820                 0x3ba40, 0x3ba40,
1821                 0x3ba48, 0x3ba50,
1822                 0x3ba5c, 0x3ba64,
1823                 0x3ba70, 0x3bab8,
1824                 0x3bac0, 0x3bae4,
1825                 0x3baf8, 0x3bb10,
1826                 0x3bb28, 0x3bb28,
1827                 0x3bb3c, 0x3bb50,
1828                 0x3bbf0, 0x3bc10,
1829                 0x3bc28, 0x3bc28,
1830                 0x3bc3c, 0x3bc50,
1831                 0x3bcf0, 0x3bcfc,
1832                 0x3c000, 0x3c030,
1833                 0x3c100, 0x3c144,
1834                 0x3c190, 0x3c1a0,
1835                 0x3c1a8, 0x3c1b8,
1836                 0x3c1c4, 0x3c1c8,
1837                 0x3c1d0, 0x3c1d0,
1838                 0x3c200, 0x3c318,
1839                 0x3c400, 0x3c4b4,
1840                 0x3c4c0, 0x3c52c,
1841                 0x3c540, 0x3c61c,
1842                 0x3c800, 0x3c828,
1843                 0x3c834, 0x3c834,
1844                 0x3c8c0, 0x3c908,
1845                 0x3c910, 0x3c9ac,
1846                 0x3ca00, 0x3ca14,
1847                 0x3ca1c, 0x3ca2c,
1848                 0x3ca44, 0x3ca50,
1849                 0x3ca74, 0x3ca74,
1850                 0x3ca7c, 0x3cafc,
1851                 0x3cb08, 0x3cc24,
1852                 0x3cd00, 0x3cd00,
1853                 0x3cd08, 0x3cd14,
1854                 0x3cd1c, 0x3cd20,
1855                 0x3cd3c, 0x3cd3c,
1856                 0x3cd48, 0x3cd50,
1857                 0x3d200, 0x3d20c,
1858                 0x3d220, 0x3d220,
1859                 0x3d240, 0x3d240,
1860                 0x3d600, 0x3d60c,
1861                 0x3da00, 0x3da1c,
1862                 0x3de00, 0x3de20,
1863                 0x3de38, 0x3de3c,
1864                 0x3de80, 0x3de80,
1865                 0x3de88, 0x3dea8,
1866                 0x3deb0, 0x3deb4,
1867                 0x3dec8, 0x3ded4,
1868                 0x3dfb8, 0x3e004,
1869                 0x3e200, 0x3e200,
1870                 0x3e208, 0x3e240,
1871                 0x3e248, 0x3e280,
1872                 0x3e288, 0x3e2c0,
1873                 0x3e2c8, 0x3e2fc,
1874                 0x3e600, 0x3e630,
1875                 0x3ea00, 0x3eabc,
1876                 0x3eb00, 0x3eb10,
1877                 0x3eb20, 0x3eb30,
1878                 0x3eb40, 0x3eb50,
1879                 0x3eb60, 0x3eb70,
1880                 0x3f000, 0x3f028,
1881                 0x3f030, 0x3f048,
1882                 0x3f060, 0x3f068,
1883                 0x3f070, 0x3f09c,
1884                 0x3f0f0, 0x3f128,
1885                 0x3f130, 0x3f148,
1886                 0x3f160, 0x3f168,
1887                 0x3f170, 0x3f19c,
1888                 0x3f1f0, 0x3f238,
1889                 0x3f240, 0x3f240,
1890                 0x3f248, 0x3f250,
1891                 0x3f25c, 0x3f264,
1892                 0x3f270, 0x3f2b8,
1893                 0x3f2c0, 0x3f2e4,
1894                 0x3f2f8, 0x3f338,
1895                 0x3f340, 0x3f340,
1896                 0x3f348, 0x3f350,
1897                 0x3f35c, 0x3f364,
1898                 0x3f370, 0x3f3b8,
1899                 0x3f3c0, 0x3f3e4,
1900                 0x3f3f8, 0x3f428,
1901                 0x3f430, 0x3f448,
1902                 0x3f460, 0x3f468,
1903                 0x3f470, 0x3f49c,
1904                 0x3f4f0, 0x3f528,
1905                 0x3f530, 0x3f548,
1906                 0x3f560, 0x3f568,
1907                 0x3f570, 0x3f59c,
1908                 0x3f5f0, 0x3f638,
1909                 0x3f640, 0x3f640,
1910                 0x3f648, 0x3f650,
1911                 0x3f65c, 0x3f664,
1912                 0x3f670, 0x3f6b8,
1913                 0x3f6c0, 0x3f6e4,
1914                 0x3f6f8, 0x3f738,
1915                 0x3f740, 0x3f740,
1916                 0x3f748, 0x3f750,
1917                 0x3f75c, 0x3f764,
1918                 0x3f770, 0x3f7b8,
1919                 0x3f7c0, 0x3f7e4,
1920                 0x3f7f8, 0x3f7fc,
1921                 0x3f814, 0x3f814,
1922                 0x3f82c, 0x3f82c,
1923                 0x3f880, 0x3f88c,
1924                 0x3f8e8, 0x3f8ec,
1925                 0x3f900, 0x3f928,
1926                 0x3f930, 0x3f948,
1927                 0x3f960, 0x3f968,
1928                 0x3f970, 0x3f99c,
1929                 0x3f9f0, 0x3fa38,
1930                 0x3fa40, 0x3fa40,
1931                 0x3fa48, 0x3fa50,
1932                 0x3fa5c, 0x3fa64,
1933                 0x3fa70, 0x3fab8,
1934                 0x3fac0, 0x3fae4,
1935                 0x3faf8, 0x3fb10,
1936                 0x3fb28, 0x3fb28,
1937                 0x3fb3c, 0x3fb50,
1938                 0x3fbf0, 0x3fc10,
1939                 0x3fc28, 0x3fc28,
1940                 0x3fc3c, 0x3fc50,
1941                 0x3fcf0, 0x3fcfc,
1942                 0x40000, 0x4000c,
1943                 0x40040, 0x40050,
1944                 0x40060, 0x40068,
1945                 0x4007c, 0x4008c,
1946                 0x40094, 0x400b0,
1947                 0x400c0, 0x40144,
1948                 0x40180, 0x4018c,
1949                 0x40200, 0x40254,
1950                 0x40260, 0x40264,
1951                 0x40270, 0x40288,
1952                 0x40290, 0x40298,
1953                 0x402ac, 0x402c8,
1954                 0x402d0, 0x402e0,
1955                 0x402f0, 0x402f0,
1956                 0x40300, 0x4033c,
1957                 0x403f8, 0x403fc,
1958                 0x41304, 0x413c4,
1959                 0x41400, 0x4140c,
1960                 0x41414, 0x4141c,
1961                 0x41480, 0x414d0,
1962                 0x44000, 0x44054,
1963                 0x4405c, 0x44078,
1964                 0x440c0, 0x44174,
1965                 0x44180, 0x441ac,
1966                 0x441b4, 0x441b8,
1967                 0x441c0, 0x44254,
1968                 0x4425c, 0x44278,
1969                 0x442c0, 0x44374,
1970                 0x44380, 0x443ac,
1971                 0x443b4, 0x443b8,
1972                 0x443c0, 0x44454,
1973                 0x4445c, 0x44478,
1974                 0x444c0, 0x44574,
1975                 0x44580, 0x445ac,
1976                 0x445b4, 0x445b8,
1977                 0x445c0, 0x44654,
1978                 0x4465c, 0x44678,
1979                 0x446c0, 0x44774,
1980                 0x44780, 0x447ac,
1981                 0x447b4, 0x447b8,
1982                 0x447c0, 0x44854,
1983                 0x4485c, 0x44878,
1984                 0x448c0, 0x44974,
1985                 0x44980, 0x449ac,
1986                 0x449b4, 0x449b8,
1987                 0x449c0, 0x449fc,
1988                 0x45000, 0x45004,
1989                 0x45010, 0x45030,
1990                 0x45040, 0x45060,
1991                 0x45068, 0x45068,
1992                 0x45080, 0x45084,
1993                 0x450a0, 0x450b0,
1994                 0x45200, 0x45204,
1995                 0x45210, 0x45230,
1996                 0x45240, 0x45260,
1997                 0x45268, 0x45268,
1998                 0x45280, 0x45284,
1999                 0x452a0, 0x452b0,
2000                 0x460c0, 0x460e4,
2001                 0x47000, 0x4703c,
2002                 0x47044, 0x4708c,
2003                 0x47200, 0x47250,
2004                 0x47400, 0x47408,
2005                 0x47414, 0x47420,
2006                 0x47600, 0x47618,
2007                 0x47800, 0x47814,
2008                 0x48000, 0x4800c,
2009                 0x48040, 0x48050,
2010                 0x48060, 0x48068,
2011                 0x4807c, 0x4808c,
2012                 0x48094, 0x480b0,
2013                 0x480c0, 0x48144,
2014                 0x48180, 0x4818c,
2015                 0x48200, 0x48254,
2016                 0x48260, 0x48264,
2017                 0x48270, 0x48288,
2018                 0x48290, 0x48298,
2019                 0x482ac, 0x482c8,
2020                 0x482d0, 0x482e0,
2021                 0x482f0, 0x482f0,
2022                 0x48300, 0x4833c,
2023                 0x483f8, 0x483fc,
2024                 0x49304, 0x493c4,
2025                 0x49400, 0x4940c,
2026                 0x49414, 0x4941c,
2027                 0x49480, 0x494d0,
2028                 0x4c000, 0x4c054,
2029                 0x4c05c, 0x4c078,
2030                 0x4c0c0, 0x4c174,
2031                 0x4c180, 0x4c1ac,
2032                 0x4c1b4, 0x4c1b8,
2033                 0x4c1c0, 0x4c254,
2034                 0x4c25c, 0x4c278,
2035                 0x4c2c0, 0x4c374,
2036                 0x4c380, 0x4c3ac,
2037                 0x4c3b4, 0x4c3b8,
2038                 0x4c3c0, 0x4c454,
2039                 0x4c45c, 0x4c478,
2040                 0x4c4c0, 0x4c574,
2041                 0x4c580, 0x4c5ac,
2042                 0x4c5b4, 0x4c5b8,
2043                 0x4c5c0, 0x4c654,
2044                 0x4c65c, 0x4c678,
2045                 0x4c6c0, 0x4c774,
2046                 0x4c780, 0x4c7ac,
2047                 0x4c7b4, 0x4c7b8,
2048                 0x4c7c0, 0x4c854,
2049                 0x4c85c, 0x4c878,
2050                 0x4c8c0, 0x4c974,
2051                 0x4c980, 0x4c9ac,
2052                 0x4c9b4, 0x4c9b8,
2053                 0x4c9c0, 0x4c9fc,
2054                 0x4d000, 0x4d004,
2055                 0x4d010, 0x4d030,
2056                 0x4d040, 0x4d060,
2057                 0x4d068, 0x4d068,
2058                 0x4d080, 0x4d084,
2059                 0x4d0a0, 0x4d0b0,
2060                 0x4d200, 0x4d204,
2061                 0x4d210, 0x4d230,
2062                 0x4d240, 0x4d260,
2063                 0x4d268, 0x4d268,
2064                 0x4d280, 0x4d284,
2065                 0x4d2a0, 0x4d2b0,
2066                 0x4e0c0, 0x4e0e4,
2067                 0x4f000, 0x4f03c,
2068                 0x4f044, 0x4f08c,
2069                 0x4f200, 0x4f250,
2070                 0x4f400, 0x4f408,
2071                 0x4f414, 0x4f420,
2072                 0x4f600, 0x4f618,
2073                 0x4f800, 0x4f814,
2074                 0x50000, 0x50084,
2075                 0x50090, 0x500cc,
2076                 0x50400, 0x50400,
2077                 0x50800, 0x50884,
2078                 0x50890, 0x508cc,
2079                 0x50c00, 0x50c00,
2080                 0x51000, 0x5101c,
2081                 0x51300, 0x51308,
2082         };
2083
2084         static const unsigned int t6_reg_ranges[] = {
2085                 0x1008, 0x101c,
2086                 0x1024, 0x10a8,
2087                 0x10b4, 0x10f8,
2088                 0x1100, 0x1114,
2089                 0x111c, 0x112c,
2090                 0x1138, 0x113c,
2091                 0x1144, 0x114c,
2092                 0x1180, 0x1184,
2093                 0x1190, 0x1194,
2094                 0x11a0, 0x11a4,
2095                 0x11b0, 0x11b4,
2096                 0x11fc, 0x123c,
2097                 0x1254, 0x1274,
2098                 0x1280, 0x133c,
2099                 0x1800, 0x18fc,
2100                 0x3000, 0x302c,
2101                 0x3060, 0x30b0,
2102                 0x30b8, 0x30d8,
2103                 0x30e0, 0x30fc,
2104                 0x3140, 0x357c,
2105                 0x35a8, 0x35cc,
2106                 0x35ec, 0x35ec,
2107                 0x3600, 0x5624,
2108                 0x56cc, 0x56ec,
2109                 0x56f4, 0x5720,
2110                 0x5728, 0x575c,
2111                 0x580c, 0x5814,
2112                 0x5890, 0x589c,
2113                 0x58a4, 0x58ac,
2114                 0x58b8, 0x58bc,
2115                 0x5940, 0x595c,
2116                 0x5980, 0x598c,
2117                 0x59b0, 0x59c8,
2118                 0x59d0, 0x59dc,
2119                 0x59fc, 0x5a18,
2120                 0x5a60, 0x5a6c,
2121                 0x5a80, 0x5a8c,
2122                 0x5a94, 0x5a9c,
2123                 0x5b94, 0x5bfc,
2124                 0x5c10, 0x5e48,
2125                 0x5e50, 0x5e94,
2126                 0x5ea0, 0x5eb0,
2127                 0x5ec0, 0x5ec0,
2128                 0x5ec8, 0x5ed0,
2129                 0x5ee0, 0x5ee0,
2130                 0x5ef0, 0x5ef0,
2131                 0x5f00, 0x5f00,
2132                 0x6000, 0x6020,
2133                 0x6028, 0x6040,
2134                 0x6058, 0x609c,
2135                 0x60a8, 0x619c,
2136                 0x7700, 0x7798,
2137                 0x77c0, 0x7880,
2138                 0x78cc, 0x78fc,
2139                 0x7b00, 0x7b58,
2140                 0x7b60, 0x7b84,
2141                 0x7b8c, 0x7c54,
2142                 0x7d00, 0x7d38,
2143                 0x7d40, 0x7d84,
2144                 0x7d8c, 0x7ddc,
2145                 0x7de4, 0x7e04,
2146                 0x7e10, 0x7e1c,
2147                 0x7e24, 0x7e38,
2148                 0x7e40, 0x7e44,
2149                 0x7e4c, 0x7e78,
2150                 0x7e80, 0x7edc,
2151                 0x7ee8, 0x7efc,
2152                 0x8dc0, 0x8de4,
2153                 0x8df8, 0x8e04,
2154                 0x8e10, 0x8e84,
2155                 0x8ea0, 0x8f88,
2156                 0x8fb8, 0x9058,
2157                 0x9060, 0x9060,
2158                 0x9068, 0x90f8,
2159                 0x9100, 0x9124,
2160                 0x9400, 0x9470,
2161                 0x9600, 0x9600,
2162                 0x9608, 0x9638,
2163                 0x9640, 0x9704,
2164                 0x9710, 0x971c,
2165                 0x9800, 0x9808,
2166                 0x9820, 0x983c,
2167                 0x9850, 0x9864,
2168                 0x9c00, 0x9c6c,
2169                 0x9c80, 0x9cec,
2170                 0x9d00, 0x9d6c,
2171                 0x9d80, 0x9dec,
2172                 0x9e00, 0x9e6c,
2173                 0x9e80, 0x9eec,
2174                 0x9f00, 0x9f6c,
2175                 0x9f80, 0xa020,
2176                 0xd004, 0xd03c,
2177                 0xd100, 0xd118,
2178                 0xd200, 0xd214,
2179                 0xd220, 0xd234,
2180                 0xd240, 0xd254,
2181                 0xd260, 0xd274,
2182                 0xd280, 0xd294,
2183                 0xd2a0, 0xd2b4,
2184                 0xd2c0, 0xd2d4,
2185                 0xd2e0, 0xd2f4,
2186                 0xd300, 0xd31c,
2187                 0xdfc0, 0xdfe0,
2188                 0xe000, 0xf008,
2189                 0xf010, 0xf018,
2190                 0xf020, 0xf028,
2191                 0x11000, 0x11014,
2192                 0x11048, 0x1106c,
2193                 0x11074, 0x11088,
2194                 0x11098, 0x11120,
2195                 0x1112c, 0x1117c,
2196                 0x11190, 0x112e0,
2197                 0x11300, 0x1130c,
2198                 0x12000, 0x1206c,
2199                 0x19040, 0x1906c,
2200                 0x19078, 0x19080,
2201                 0x1908c, 0x190e8,
2202                 0x190f0, 0x190f8,
2203                 0x19100, 0x19110,
2204                 0x19120, 0x19124,
2205                 0x19150, 0x19194,
2206                 0x1919c, 0x191b0,
2207                 0x191d0, 0x191e8,
2208                 0x19238, 0x19290,
2209                 0x192a4, 0x192b0,
2210                 0x192bc, 0x192bc,
2211                 0x19348, 0x1934c,
2212                 0x193f8, 0x19418,
2213                 0x19420, 0x19428,
2214                 0x19430, 0x19444,
2215                 0x1944c, 0x1946c,
2216                 0x19474, 0x19474,
2217                 0x19490, 0x194cc,
2218                 0x194f0, 0x194f8,
2219                 0x19c00, 0x19c48,
2220                 0x19c50, 0x19c80,
2221                 0x19c94, 0x19c98,
2222                 0x19ca0, 0x19cbc,
2223                 0x19ce4, 0x19ce4,
2224                 0x19cf0, 0x19cf8,
2225                 0x19d00, 0x19d28,
2226                 0x19d50, 0x19d78,
2227                 0x19d94, 0x19d98,
2228                 0x19da0, 0x19dc8,
2229                 0x19df0, 0x19e10,
2230                 0x19e50, 0x19e6c,
2231                 0x19ea0, 0x19ebc,
2232                 0x19ec4, 0x19ef4,
2233                 0x19f04, 0x19f2c,
2234                 0x19f34, 0x19f34,
2235                 0x19f40, 0x19f50,
2236                 0x19f90, 0x19fac,
2237                 0x19fc4, 0x19fc8,
2238                 0x19fd0, 0x19fe4,
2239                 0x1a000, 0x1a004,
2240                 0x1a010, 0x1a06c,
2241                 0x1a0b0, 0x1a0e4,
2242                 0x1a0ec, 0x1a0f8,
2243                 0x1a100, 0x1a108,
2244                 0x1a114, 0x1a120,
2245                 0x1a128, 0x1a130,
2246                 0x1a138, 0x1a138,
2247                 0x1a190, 0x1a1c4,
2248                 0x1a1fc, 0x1a1fc,
2249                 0x1e008, 0x1e00c,
2250                 0x1e040, 0x1e044,
2251                 0x1e04c, 0x1e04c,
2252                 0x1e284, 0x1e290,
2253                 0x1e2c0, 0x1e2c0,
2254                 0x1e2e0, 0x1e2e0,
2255                 0x1e300, 0x1e384,
2256                 0x1e3c0, 0x1e3c8,
2257                 0x1e408, 0x1e40c,
2258                 0x1e440, 0x1e444,
2259                 0x1e44c, 0x1e44c,
2260                 0x1e684, 0x1e690,
2261                 0x1e6c0, 0x1e6c0,
2262                 0x1e6e0, 0x1e6e0,
2263                 0x1e700, 0x1e784,
2264                 0x1e7c0, 0x1e7c8,
2265                 0x1e808, 0x1e80c,
2266                 0x1e840, 0x1e844,
2267                 0x1e84c, 0x1e84c,
2268                 0x1ea84, 0x1ea90,
2269                 0x1eac0, 0x1eac0,
2270                 0x1eae0, 0x1eae0,
2271                 0x1eb00, 0x1eb84,
2272                 0x1ebc0, 0x1ebc8,
2273                 0x1ec08, 0x1ec0c,
2274                 0x1ec40, 0x1ec44,
2275                 0x1ec4c, 0x1ec4c,
2276                 0x1ee84, 0x1ee90,
2277                 0x1eec0, 0x1eec0,
2278                 0x1eee0, 0x1eee0,
2279                 0x1ef00, 0x1ef84,
2280                 0x1efc0, 0x1efc8,
2281                 0x1f008, 0x1f00c,
2282                 0x1f040, 0x1f044,
2283                 0x1f04c, 0x1f04c,
2284                 0x1f284, 0x1f290,
2285                 0x1f2c0, 0x1f2c0,
2286                 0x1f2e0, 0x1f2e0,
2287                 0x1f300, 0x1f384,
2288                 0x1f3c0, 0x1f3c8,
2289                 0x1f408, 0x1f40c,
2290                 0x1f440, 0x1f444,
2291                 0x1f44c, 0x1f44c,
2292                 0x1f684, 0x1f690,
2293                 0x1f6c0, 0x1f6c0,
2294                 0x1f6e0, 0x1f6e0,
2295                 0x1f700, 0x1f784,
2296                 0x1f7c0, 0x1f7c8,
2297                 0x1f808, 0x1f80c,
2298                 0x1f840, 0x1f844,
2299                 0x1f84c, 0x1f84c,
2300                 0x1fa84, 0x1fa90,
2301                 0x1fac0, 0x1fac0,
2302                 0x1fae0, 0x1fae0,
2303                 0x1fb00, 0x1fb84,
2304                 0x1fbc0, 0x1fbc8,
2305                 0x1fc08, 0x1fc0c,
2306                 0x1fc40, 0x1fc44,
2307                 0x1fc4c, 0x1fc4c,
2308                 0x1fe84, 0x1fe90,
2309                 0x1fec0, 0x1fec0,
2310                 0x1fee0, 0x1fee0,
2311                 0x1ff00, 0x1ff84,
2312                 0x1ffc0, 0x1ffc8,
2313                 0x30000, 0x30030,
2314                 0x30100, 0x30168,
2315                 0x30190, 0x301a0,
2316                 0x301a8, 0x301b8,
2317                 0x301c4, 0x301c8,
2318                 0x301d0, 0x301d0,
2319                 0x30200, 0x30320,
2320                 0x30400, 0x304b4,
2321                 0x304c0, 0x3052c,
2322                 0x30540, 0x3061c,
2323                 0x30800, 0x308a0,
2324                 0x308c0, 0x30908,
2325                 0x30910, 0x309b8,
2326                 0x30a00, 0x30a04,
2327                 0x30a0c, 0x30a14,
2328                 0x30a1c, 0x30a2c,
2329                 0x30a44, 0x30a50,
2330                 0x30a74, 0x30a74,
2331                 0x30a7c, 0x30afc,
2332                 0x30b08, 0x30c24,
2333                 0x30d00, 0x30d14,
2334                 0x30d1c, 0x30d3c,
2335                 0x30d44, 0x30d4c,
2336                 0x30d54, 0x30d74,
2337                 0x30d7c, 0x30d7c,
2338                 0x30de0, 0x30de0,
2339                 0x30e00, 0x30ed4,
2340                 0x30f00, 0x30fa4,
2341                 0x30fc0, 0x30fc4,
2342                 0x31000, 0x31004,
2343                 0x31080, 0x310fc,
2344                 0x31208, 0x31220,
2345                 0x3123c, 0x31254,
2346                 0x31300, 0x31300,
2347                 0x31308, 0x3131c,
2348                 0x31338, 0x3133c,
2349                 0x31380, 0x31380,
2350                 0x31388, 0x313a8,
2351                 0x313b4, 0x313b4,
2352                 0x31400, 0x31420,
2353                 0x31438, 0x3143c,
2354                 0x31480, 0x31480,
2355                 0x314a8, 0x314a8,
2356                 0x314b0, 0x314b4,
2357                 0x314c8, 0x314d4,
2358                 0x31a40, 0x31a4c,
2359                 0x31af0, 0x31b20,
2360                 0x31b38, 0x31b3c,
2361                 0x31b80, 0x31b80,
2362                 0x31ba8, 0x31ba8,
2363                 0x31bb0, 0x31bb4,
2364                 0x31bc8, 0x31bd4,
2365                 0x32140, 0x3218c,
2366                 0x321f0, 0x321f4,
2367                 0x32200, 0x32200,
2368                 0x32218, 0x32218,
2369                 0x32400, 0x32400,
2370                 0x32408, 0x3241c,
2371                 0x32618, 0x32620,
2372                 0x32664, 0x32664,
2373                 0x326a8, 0x326a8,
2374                 0x326ec, 0x326ec,
2375                 0x32a00, 0x32abc,
2376                 0x32b00, 0x32b18,
2377                 0x32b20, 0x32b38,
2378                 0x32b40, 0x32b58,
2379                 0x32b60, 0x32b78,
2380                 0x32c00, 0x32c00,
2381                 0x32c08, 0x32c3c,
2382                 0x33000, 0x3302c,
2383                 0x33034, 0x33050,
2384                 0x33058, 0x33058,
2385                 0x33060, 0x3308c,
2386                 0x3309c, 0x330ac,
2387                 0x330c0, 0x330c0,
2388                 0x330c8, 0x330d0,
2389                 0x330d8, 0x330e0,
2390                 0x330ec, 0x3312c,
2391                 0x33134, 0x33150,
2392                 0x33158, 0x33158,
2393                 0x33160, 0x3318c,
2394                 0x3319c, 0x331ac,
2395                 0x331c0, 0x331c0,
2396                 0x331c8, 0x331d0,
2397                 0x331d8, 0x331e0,
2398                 0x331ec, 0x33290,
2399                 0x33298, 0x332c4,
2400                 0x332e4, 0x33390,
2401                 0x33398, 0x333c4,
2402                 0x333e4, 0x3342c,
2403                 0x33434, 0x33450,
2404                 0x33458, 0x33458,
2405                 0x33460, 0x3348c,
2406                 0x3349c, 0x334ac,
2407                 0x334c0, 0x334c0,
2408                 0x334c8, 0x334d0,
2409                 0x334d8, 0x334e0,
2410                 0x334ec, 0x3352c,
2411                 0x33534, 0x33550,
2412                 0x33558, 0x33558,
2413                 0x33560, 0x3358c,
2414                 0x3359c, 0x335ac,
2415                 0x335c0, 0x335c0,
2416                 0x335c8, 0x335d0,
2417                 0x335d8, 0x335e0,
2418                 0x335ec, 0x33690,
2419                 0x33698, 0x336c4,
2420                 0x336e4, 0x33790,
2421                 0x33798, 0x337c4,
2422                 0x337e4, 0x337fc,
2423                 0x33814, 0x33814,
2424                 0x33854, 0x33868,
2425                 0x33880, 0x3388c,
2426                 0x338c0, 0x338d0,
2427                 0x338e8, 0x338ec,
2428                 0x33900, 0x3392c,
2429                 0x33934, 0x33950,
2430                 0x33958, 0x33958,
2431                 0x33960, 0x3398c,
2432                 0x3399c, 0x339ac,
2433                 0x339c0, 0x339c0,
2434                 0x339c8, 0x339d0,
2435                 0x339d8, 0x339e0,
2436                 0x339ec, 0x33a90,
2437                 0x33a98, 0x33ac4,
2438                 0x33ae4, 0x33b10,
2439                 0x33b24, 0x33b28,
2440                 0x33b38, 0x33b50,
2441                 0x33bf0, 0x33c10,
2442                 0x33c24, 0x33c28,
2443                 0x33c38, 0x33c50,
2444                 0x33cf0, 0x33cfc,
2445                 0x34000, 0x34030,
2446                 0x34100, 0x34168,
2447                 0x34190, 0x341a0,
2448                 0x341a8, 0x341b8,
2449                 0x341c4, 0x341c8,
2450                 0x341d0, 0x341d0,
2451                 0x34200, 0x34320,
2452                 0x34400, 0x344b4,
2453                 0x344c0, 0x3452c,
2454                 0x34540, 0x3461c,
2455                 0x34800, 0x348a0,
2456                 0x348c0, 0x34908,
2457                 0x34910, 0x349b8,
2458                 0x34a00, 0x34a04,
2459                 0x34a0c, 0x34a14,
2460                 0x34a1c, 0x34a2c,
2461                 0x34a44, 0x34a50,
2462                 0x34a74, 0x34a74,
2463                 0x34a7c, 0x34afc,
2464                 0x34b08, 0x34c24,
2465                 0x34d00, 0x34d14,
2466                 0x34d1c, 0x34d3c,
2467                 0x34d44, 0x34d4c,
2468                 0x34d54, 0x34d74,
2469                 0x34d7c, 0x34d7c,
2470                 0x34de0, 0x34de0,
2471                 0x34e00, 0x34ed4,
2472                 0x34f00, 0x34fa4,
2473                 0x34fc0, 0x34fc4,
2474                 0x35000, 0x35004,
2475                 0x35080, 0x350fc,
2476                 0x35208, 0x35220,
2477                 0x3523c, 0x35254,
2478                 0x35300, 0x35300,
2479                 0x35308, 0x3531c,
2480                 0x35338, 0x3533c,
2481                 0x35380, 0x35380,
2482                 0x35388, 0x353a8,
2483                 0x353b4, 0x353b4,
2484                 0x35400, 0x35420,
2485                 0x35438, 0x3543c,
2486                 0x35480, 0x35480,
2487                 0x354a8, 0x354a8,
2488                 0x354b0, 0x354b4,
2489                 0x354c8, 0x354d4,
2490                 0x35a40, 0x35a4c,
2491                 0x35af0, 0x35b20,
2492                 0x35b38, 0x35b3c,
2493                 0x35b80, 0x35b80,
2494                 0x35ba8, 0x35ba8,
2495                 0x35bb0, 0x35bb4,
2496                 0x35bc8, 0x35bd4,
2497                 0x36140, 0x3618c,
2498                 0x361f0, 0x361f4,
2499                 0x36200, 0x36200,
2500                 0x36218, 0x36218,
2501                 0x36400, 0x36400,
2502                 0x36408, 0x3641c,
2503                 0x36618, 0x36620,
2504                 0x36664, 0x36664,
2505                 0x366a8, 0x366a8,
2506                 0x366ec, 0x366ec,
2507                 0x36a00, 0x36abc,
2508                 0x36b00, 0x36b18,
2509                 0x36b20, 0x36b38,
2510                 0x36b40, 0x36b58,
2511                 0x36b60, 0x36b78,
2512                 0x36c00, 0x36c00,
2513                 0x36c08, 0x36c3c,
2514                 0x37000, 0x3702c,
2515                 0x37034, 0x37050,
2516                 0x37058, 0x37058,
2517                 0x37060, 0x3708c,
2518                 0x3709c, 0x370ac,
2519                 0x370c0, 0x370c0,
2520                 0x370c8, 0x370d0,
2521                 0x370d8, 0x370e0,
2522                 0x370ec, 0x3712c,
2523                 0x37134, 0x37150,
2524                 0x37158, 0x37158,
2525                 0x37160, 0x3718c,
2526                 0x3719c, 0x371ac,
2527                 0x371c0, 0x371c0,
2528                 0x371c8, 0x371d0,
2529                 0x371d8, 0x371e0,
2530                 0x371ec, 0x37290,
2531                 0x37298, 0x372c4,
2532                 0x372e4, 0x37390,
2533                 0x37398, 0x373c4,
2534                 0x373e4, 0x3742c,
2535                 0x37434, 0x37450,
2536                 0x37458, 0x37458,
2537                 0x37460, 0x3748c,
2538                 0x3749c, 0x374ac,
2539                 0x374c0, 0x374c0,
2540                 0x374c8, 0x374d0,
2541                 0x374d8, 0x374e0,
2542                 0x374ec, 0x3752c,
2543                 0x37534, 0x37550,
2544                 0x37558, 0x37558,
2545                 0x37560, 0x3758c,
2546                 0x3759c, 0x375ac,
2547                 0x375c0, 0x375c0,
2548                 0x375c8, 0x375d0,
2549                 0x375d8, 0x375e0,
2550                 0x375ec, 0x37690,
2551                 0x37698, 0x376c4,
2552                 0x376e4, 0x37790,
2553                 0x37798, 0x377c4,
2554                 0x377e4, 0x377fc,
2555                 0x37814, 0x37814,
2556                 0x37854, 0x37868,
2557                 0x37880, 0x3788c,
2558                 0x378c0, 0x378d0,
2559                 0x378e8, 0x378ec,
2560                 0x37900, 0x3792c,
2561                 0x37934, 0x37950,
2562                 0x37958, 0x37958,
2563                 0x37960, 0x3798c,
2564                 0x3799c, 0x379ac,
2565                 0x379c0, 0x379c0,
2566                 0x379c8, 0x379d0,
2567                 0x379d8, 0x379e0,
2568                 0x379ec, 0x37a90,
2569                 0x37a98, 0x37ac4,
2570                 0x37ae4, 0x37b10,
2571                 0x37b24, 0x37b28,
2572                 0x37b38, 0x37b50,
2573                 0x37bf0, 0x37c10,
2574                 0x37c24, 0x37c28,
2575                 0x37c38, 0x37c50,
2576                 0x37cf0, 0x37cfc,
2577                 0x40040, 0x40040,
2578                 0x40080, 0x40084,
2579                 0x40100, 0x40100,
2580                 0x40140, 0x401bc,
2581                 0x40200, 0x40214,
2582                 0x40228, 0x40228,
2583                 0x40240, 0x40258,
2584                 0x40280, 0x40280,
2585                 0x40304, 0x40304,
2586                 0x40330, 0x4033c,
2587                 0x41304, 0x413c8,
2588                 0x413d0, 0x413dc,
2589                 0x413f0, 0x413f0,
2590                 0x41400, 0x4140c,
2591                 0x41414, 0x4141c,
2592                 0x41480, 0x414d0,
2593                 0x44000, 0x4407c,
2594                 0x440c0, 0x441ac,
2595                 0x441b4, 0x4427c,
2596                 0x442c0, 0x443ac,
2597                 0x443b4, 0x4447c,
2598                 0x444c0, 0x445ac,
2599                 0x445b4, 0x4467c,
2600                 0x446c0, 0x447ac,
2601                 0x447b4, 0x4487c,
2602                 0x448c0, 0x449ac,
2603                 0x449b4, 0x44a7c,
2604                 0x44ac0, 0x44bac,
2605                 0x44bb4, 0x44c7c,
2606                 0x44cc0, 0x44dac,
2607                 0x44db4, 0x44e7c,
2608                 0x44ec0, 0x44fac,
2609                 0x44fb4, 0x4507c,
2610                 0x450c0, 0x451ac,
2611                 0x451b4, 0x451fc,
2612                 0x45800, 0x45804,
2613                 0x45810, 0x45830,
2614                 0x45840, 0x45860,
2615                 0x45868, 0x45868,
2616                 0x45880, 0x45884,
2617                 0x458a0, 0x458b0,
2618                 0x45a00, 0x45a04,
2619                 0x45a10, 0x45a30,
2620                 0x45a40, 0x45a60,
2621                 0x45a68, 0x45a68,
2622                 0x45a80, 0x45a84,
2623                 0x45aa0, 0x45ab0,
2624                 0x460c0, 0x460e4,
2625                 0x47000, 0x4703c,
2626                 0x47044, 0x4708c,
2627                 0x47200, 0x47250,
2628                 0x47400, 0x47408,
2629                 0x47414, 0x47420,
2630                 0x47600, 0x47618,
2631                 0x47800, 0x47814,
2632                 0x47820, 0x4782c,
2633                 0x50000, 0x50084,
2634                 0x50090, 0x500cc,
2635                 0x50300, 0x50384,
2636                 0x50400, 0x50400,
2637                 0x50800, 0x50884,
2638                 0x50890, 0x508cc,
2639                 0x50b00, 0x50b84,
2640                 0x50c00, 0x50c00,
2641                 0x51000, 0x51020,
2642                 0x51028, 0x510b0,
2643                 0x51300, 0x51324,
2644         };
2645
2646         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2647         const unsigned int *reg_ranges;
2648         int reg_ranges_size, range;
2649         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2650
2651         /* Select the right set of register ranges to dump depending on the
2652          * adapter chip type.
2653          */
2654         switch (chip_version) {
2655         case CHELSIO_T4:
2656                 reg_ranges = t4_reg_ranges;
2657                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2658                 break;
2659
2660         case CHELSIO_T5:
2661                 reg_ranges = t5_reg_ranges;
2662                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2663                 break;
2664
2665         case CHELSIO_T6:
2666                 reg_ranges = t6_reg_ranges;
2667                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2668                 break;
2669
2670         default:
2671                 dev_err(adap->pdev_dev,
2672                         "Unsupported chip version %d\n", chip_version);
2673                 return;
2674         }
2675
2676         /* Clear the register buffer and insert the appropriate register
2677          * values selected by the above register ranges.
2678          */
2679         memset(buf, 0, buf_size);
2680         for (range = 0; range < reg_ranges_size; range += 2) {
2681                 unsigned int reg = reg_ranges[range];
2682                 unsigned int last_reg = reg_ranges[range + 1];
2683                 u32 *bufp = (u32 *)((char *)buf + reg);
2684
2685                 /* Iterate across the register range filling in the register
2686                  * buffer but don't write past the end of the register buffer.
2687                  */
2688                 while (reg <= last_reg && bufp < buf_end) {
2689                         *bufp++ = t4_read_reg(adap, reg);
2690                         reg += sizeof(u32);
2691                 }
2692         }
2693 }
2694
2695 #define EEPROM_STAT_ADDR   0x7bfc
2696 #define VPD_BASE           0x400
2697 #define VPD_BASE_OLD       0
2698 #define VPD_LEN            1024
2699 #define CHELSIO_VPD_UNIQUE_ID 0x82
2700
2701 /**
2702  * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2703  * @phys_addr: the physical EEPROM address
2704  * @fn: the PCI function number
2705  * @sz: size of function-specific area
2706  *
2707  * Translate a physical EEPROM address to virtual.  The first 1K is
2708  * accessed through virtual addresses starting at 31K, the rest is
2709  * accessed through virtual addresses starting at 0.
2710  *
2711  * The mapping is as follows:
2712  * [0..1K) -> [31K..32K)
2713  * [1K..1K+A) -> [31K-A..31K)
2714  * [1K+A..ES) -> [0..ES-A-1K)
2715  *
2716  * where A = @fn * @sz, and ES = EEPROM size.
2717  */
2718 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2719 {
2720         fn *= sz;
2721         if (phys_addr < 1024)
2722                 return phys_addr + (31 << 10);
2723         if (phys_addr < 1024 + fn)
2724                 return 31744 - fn + phys_addr - 1024;
2725         if (phys_addr < EEPROMSIZE)
2726                 return phys_addr - 1024 - fn;
2727         return -EINVAL;
2728 }
2729
2730 /**
2731  *      t4_seeprom_wp - enable/disable EEPROM write protection
2732  *      @adapter: the adapter
2733  *      @enable: whether to enable or disable write protection
2734  *
2735  *      Enables or disables write protection on the serial EEPROM.
2736  */
2737 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2738 {
2739         unsigned int v = enable ? 0xc : 0;
2740         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2741         return ret < 0 ? ret : 0;
2742 }
2743
2744 /**
2745  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2746  *      @adapter: adapter to read
2747  *      @p: where to store the parameters
2748  *
2749  *      Reads card parameters stored in VPD EEPROM.
2750  */
2751 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2752 {
2753         int i, ret = 0, addr;
2754         int ec, sn, pn, na;
2755         u8 *vpd, csum;
2756         unsigned int vpdr_len, kw_offset, id_len;
2757
2758         vpd = vmalloc(VPD_LEN);
2759         if (!vpd)
2760                 return -ENOMEM;
2761
2762         /* Card information normally starts at VPD_BASE but early cards had
2763          * it at 0.
2764          */
2765         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2766         if (ret < 0)
2767                 goto out;
2768
2769         /* The VPD shall have a unique identifier specified by the PCI SIG.
2770          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2771          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2772          * is expected to automatically put this entry at the
2773          * beginning of the VPD.
2774          */
2775         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2776
2777         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2778         if (ret < 0)
2779                 goto out;
2780
2781         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2782                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2783                 ret = -EINVAL;
2784                 goto out;
2785         }
2786
2787         id_len = pci_vpd_lrdt_size(vpd);
2788         if (id_len > ID_LEN)
2789                 id_len = ID_LEN;
2790
2791         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2792         if (i < 0) {
2793                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2794                 ret = -EINVAL;
2795                 goto out;
2796         }
2797
2798         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2799         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2800         if (vpdr_len + kw_offset > VPD_LEN) {
2801                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2802                 ret = -EINVAL;
2803                 goto out;
2804         }
2805
2806 #define FIND_VPD_KW(var, name) do { \
2807         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2808         if (var < 0) { \
2809                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2810                 ret = -EINVAL; \
2811                 goto out; \
2812         } \
2813         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2814 } while (0)
2815
2816         FIND_VPD_KW(i, "RV");
2817         for (csum = 0; i >= 0; i--)
2818                 csum += vpd[i];
2819
2820         if (csum) {
2821                 dev_err(adapter->pdev_dev,
2822                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2823                 ret = -EINVAL;
2824                 goto out;
2825         }
2826
2827         FIND_VPD_KW(ec, "EC");
2828         FIND_VPD_KW(sn, "SN");
2829         FIND_VPD_KW(pn, "PN");
2830         FIND_VPD_KW(na, "NA");
2831 #undef FIND_VPD_KW
2832
2833         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2834         strim(p->id);
2835         memcpy(p->ec, vpd + ec, EC_LEN);
2836         strim(p->ec);
2837         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2838         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2839         strim(p->sn);
2840         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2841         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2842         strim(p->pn);
2843         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2844         strim((char *)p->na);
2845
2846 out:
2847         vfree(vpd);
2848         return ret < 0 ? ret : 0;
2849 }
2850
2851 /**
2852  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2853  *      @adapter: adapter to read
2854  *      @p: where to store the parameters
2855  *
2856  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2857  *      Clock.  This can only be called after a connection to the firmware
2858  *      is established.
2859  */
2860 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2861 {
2862         u32 cclk_param, cclk_val;
2863         int ret;
2864
2865         /* Grab the raw VPD parameters.
2866          */
2867         ret = t4_get_raw_vpd_params(adapter, p);
2868         if (ret)
2869                 return ret;
2870
2871         /* Ask firmware for the Core Clock since it knows how to translate the
2872          * Reference Clock ('V2') VPD field into a Core Clock value ...
2873          */
2874         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2875                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2876         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2877                               1, &cclk_param, &cclk_val);
2878
2879         if (ret)
2880                 return ret;
2881         p->cclk = cclk_val;
2882
2883         return 0;
2884 }
2885
2886 /**
2887  *      t4_get_pfres - retrieve VF resource limits
2888  *      @adapter: the adapter
2889  *
2890  *      Retrieves configured resource limits and capabilities for a physical
2891  *      function.  The results are stored in @adapter->pfres.
2892  */
2893 int t4_get_pfres(struct adapter *adapter)
2894 {
2895         struct pf_resources *pfres = &adapter->params.pfres;
2896         struct fw_pfvf_cmd cmd, rpl;
2897         int v;
2898         u32 word;
2899
2900         /* Execute PFVF Read command to get VF resource limits; bail out early
2901          * with error on command failure.
2902          */
2903         memset(&cmd, 0, sizeof(cmd));
2904         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2905                                     FW_CMD_REQUEST_F |
2906                                     FW_CMD_READ_F |
2907                                     FW_PFVF_CMD_PFN_V(adapter->pf) |
2908                                     FW_PFVF_CMD_VFN_V(0));
2909         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2910         v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2911         if (v != FW_SUCCESS)
2912                 return v;
2913
2914         /* Extract PF resource limits and return success.
2915          */
2916         word = be32_to_cpu(rpl.niqflint_niq);
2917         pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2918         pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2919
2920         word = be32_to_cpu(rpl.type_to_neq);
2921         pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2922         pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2923
2924         word = be32_to_cpu(rpl.tc_to_nexactf);
2925         pfres->tc = FW_PFVF_CMD_TC_G(word);
2926         pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2927         pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2928
2929         word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2930         pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2931         pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2932         pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2933
2934         return 0;
2935 }
2936
2937 /* serial flash and firmware constants */
2938 enum {
2939         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2940
2941         /* flash command opcodes */
2942         SF_PROG_PAGE    = 2,          /* program page */
2943         SF_WR_DISABLE   = 4,          /* disable writes */
2944         SF_RD_STATUS    = 5,          /* read status register */
2945         SF_WR_ENABLE    = 6,          /* enable writes */
2946         SF_RD_DATA_FAST = 0xb,        /* read flash */
2947         SF_RD_ID        = 0x9f,       /* read ID */
2948         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2949 };
2950
2951 /**
2952  *      sf1_read - read data from the serial flash
2953  *      @adapter: the adapter
2954  *      @byte_cnt: number of bytes to read
2955  *      @cont: whether another operation will be chained
2956  *      @lock: whether to lock SF for PL access only
2957  *      @valp: where to store the read data
2958  *
2959  *      Reads up to 4 bytes of data from the serial flash.  The location of
2960  *      the read needs to be specified prior to calling this by issuing the
2961  *      appropriate commands to the serial flash.
2962  */
2963 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2964                     int lock, u32 *valp)
2965 {
2966         int ret;
2967
2968         if (!byte_cnt || byte_cnt > 4)
2969                 return -EINVAL;
2970         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2971                 return -EBUSY;
2972         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2973                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2974         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2975         if (!ret)
2976                 *valp = t4_read_reg(adapter, SF_DATA_A);
2977         return ret;
2978 }
2979
2980 /**
2981  *      sf1_write - write data to the serial flash
2982  *      @adapter: the adapter
2983  *      @byte_cnt: number of bytes to write
2984  *      @cont: whether another operation will be chained
2985  *      @lock: whether to lock SF for PL access only
2986  *      @val: value to write
2987  *
2988  *      Writes up to 4 bytes of data to the serial flash.  The location of
2989  *      the write needs to be specified prior to calling this by issuing the
2990  *      appropriate commands to the serial flash.
2991  */
2992 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2993                      int lock, u32 val)
2994 {
2995         if (!byte_cnt || byte_cnt > 4)
2996                 return -EINVAL;
2997         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2998                 return -EBUSY;
2999         t4_write_reg(adapter, SF_DATA_A, val);
3000         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
3001                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
3002         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
3003 }
3004
3005 /**
3006  *      flash_wait_op - wait for a flash operation to complete
3007  *      @adapter: the adapter
3008  *      @attempts: max number of polls of the status register
3009  *      @delay: delay between polls in ms
3010  *
3011  *      Wait for a flash operation to complete by polling the status register.
3012  */
3013 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3014 {
3015         int ret;
3016         u32 status;
3017
3018         while (1) {
3019                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3020                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3021                         return ret;
3022                 if (!(status & 1))
3023                         return 0;
3024                 if (--attempts == 0)
3025                         return -EAGAIN;
3026                 if (delay)
3027                         msleep(delay);
3028         }
3029 }
3030
3031 /**
3032  *      t4_read_flash - read words from serial flash
3033  *      @adapter: the adapter
3034  *      @addr: the start address for the read
3035  *      @nwords: how many 32-bit words to read
3036  *      @data: where to store the read data
3037  *      @byte_oriented: whether to store data as bytes or as words
3038  *
3039  *      Read the specified number of 32-bit words from the serial flash.
3040  *      If @byte_oriented is set the read data is stored as a byte array
3041  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
3042  *      natural endianness.
3043  */
3044 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3045                   unsigned int nwords, u32 *data, int byte_oriented)
3046 {
3047         int ret;
3048
3049         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3050                 return -EINVAL;
3051
3052         addr = swab32(addr) | SF_RD_DATA_FAST;
3053
3054         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3055             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3056                 return ret;
3057
3058         for ( ; nwords; nwords--, data++) {
3059                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3060                 if (nwords == 1)
3061                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3062                 if (ret)
3063                         return ret;
3064                 if (byte_oriented)
3065                         *data = (__force __u32)(cpu_to_be32(*data));
3066         }
3067         return 0;
3068 }
3069
3070 /**
3071  *      t4_write_flash - write up to a page of data to the serial flash
3072  *      @adapter: the adapter
3073  *      @addr: the start address to write
3074  *      @n: length of data to write in bytes
3075  *      @data: the data to write
3076  *
3077  *      Writes up to a page of data (256 bytes) to the serial flash starting
3078  *      at the given address.  All the data must be written to the same page.
3079  */
3080 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3081                           unsigned int n, const u8 *data)
3082 {
3083         int ret;
3084         u32 buf[64];
3085         unsigned int i, c, left, val, offset = addr & 0xff;
3086
3087         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3088                 return -EINVAL;
3089
3090         val = swab32(addr) | SF_PROG_PAGE;
3091
3092         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3093             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3094                 goto unlock;
3095
3096         for (left = n; left; left -= c) {
3097                 c = min(left, 4U);
3098                 for (val = 0, i = 0; i < c; ++i)
3099                         val = (val << 8) + *data++;
3100
3101                 ret = sf1_write(adapter, c, c != left, 1, val);
3102                 if (ret)
3103                         goto unlock;
3104         }
3105         ret = flash_wait_op(adapter, 8, 1);
3106         if (ret)
3107                 goto unlock;
3108
3109         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3110
3111         /* Read the page to verify the write succeeded */
3112         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3113         if (ret)
3114                 return ret;
3115
3116         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3117                 dev_err(adapter->pdev_dev,
3118                         "failed to correctly write the flash page at %#x\n",
3119                         addr);
3120                 return -EIO;
3121         }
3122         return 0;
3123
3124 unlock:
3125         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3126         return ret;
3127 }
3128
3129 /**
3130  *      t4_get_fw_version - read the firmware version
3131  *      @adapter: the adapter
3132  *      @vers: where to place the version
3133  *
3134  *      Reads the FW version from flash.
3135  */
3136 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3137 {
3138         return t4_read_flash(adapter, FLASH_FW_START +
3139                              offsetof(struct fw_hdr, fw_ver), 1,
3140                              vers, 0);
3141 }
3142
3143 /**
3144  *      t4_get_bs_version - read the firmware bootstrap version
3145  *      @adapter: the adapter
3146  *      @vers: where to place the version
3147  *
3148  *      Reads the FW Bootstrap version from flash.
3149  */
3150 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3151 {
3152         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3153                              offsetof(struct fw_hdr, fw_ver), 1,
3154                              vers, 0);
3155 }
3156
3157 /**
3158  *      t4_get_tp_version - read the TP microcode version
3159  *      @adapter: the adapter
3160  *      @vers: where to place the version
3161  *
3162  *      Reads the TP microcode version from flash.
3163  */
3164 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3165 {
3166         return t4_read_flash(adapter, FLASH_FW_START +
3167                              offsetof(struct fw_hdr, tp_microcode_ver),
3168                              1, vers, 0);
3169 }
3170
3171 /**
3172  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3173  *      @adapter: the adapter
3174  *      @vers: where to place the version
3175  *
3176  *      Reads the Expansion ROM header from FLASH and returns the version
3177  *      number (if present) through the @vers return value pointer.  We return
3178  *      this in the Firmware Version Format since it's convenient.  Return
3179  *      0 on success, -ENOENT if no Expansion ROM is present.
3180  */
3181 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3182 {
3183         struct exprom_header {
3184                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3185                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3186         } *hdr;
3187         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3188                                            sizeof(u32))];
3189         int ret;
3190
3191         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3192                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3193                             0);
3194         if (ret)
3195                 return ret;
3196
3197         hdr = (struct exprom_header *)exprom_header_buf;
3198         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3199                 return -ENOENT;
3200
3201         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3202                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3203                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3204                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3205         return 0;
3206 }
3207
3208 /**
3209  *      t4_get_vpd_version - return the VPD version
3210  *      @adapter: the adapter
3211  *      @vers: where to place the version
3212  *
3213  *      Reads the VPD via the Firmware interface (thus this can only be called
3214  *      once we're ready to issue Firmware commands).  The format of the
3215  *      VPD version is adapter specific.  Returns 0 on success, an error on
3216  *      failure.
3217  *
3218  *      Note that early versions of the Firmware didn't include the ability
3219  *      to retrieve the VPD version, so we zero-out the return-value parameter
3220  *      in that case to avoid leaving it with garbage in it.
3221  *
3222  *      Also note that the Firmware will return its cached copy of the VPD
3223  *      Revision ID, not the actual Revision ID as written in the Serial
3224  *      EEPROM.  This is only an issue if a new VPD has been written and the
3225  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3226  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3227  *      if the Host Driver will be performing a full adapter initialization.
3228  */
3229 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3230 {
3231         u32 vpdrev_param;
3232         int ret;
3233
3234         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3235                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3236         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3237                               1, &vpdrev_param, vers);
3238         if (ret)
3239                 *vers = 0;
3240         return ret;
3241 }
3242
3243 /**
3244  *      t4_get_scfg_version - return the Serial Configuration version
3245  *      @adapter: the adapter
3246  *      @vers: where to place the version
3247  *
3248  *      Reads the Serial Configuration Version via the Firmware interface
3249  *      (thus this can only be called once we're ready to issue Firmware
3250  *      commands).  The format of the Serial Configuration version is
3251  *      adapter specific.  Returns 0 on success, an error on failure.
3252  *
3253  *      Note that early versions of the Firmware didn't include the ability
3254  *      to retrieve the Serial Configuration version, so we zero-out the
3255  *      return-value parameter in that case to avoid leaving it with
3256  *      garbage in it.
3257  *
3258  *      Also note that the Firmware will return its cached copy of the Serial
3259  *      Initialization Revision ID, not the actual Revision ID as written in
3260  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3261  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3262  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3263  *      been issued if the Host Driver will be performing a full adapter
3264  *      initialization.
3265  */
3266 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3267 {
3268         u32 scfgrev_param;
3269         int ret;
3270
3271         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3272                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3273         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3274                               1, &scfgrev_param, vers);
3275         if (ret)
3276                 *vers = 0;
3277         return ret;
3278 }
3279
3280 /**
3281  *      t4_get_version_info - extract various chip/firmware version information
3282  *      @adapter: the adapter
3283  *
3284  *      Reads various chip/firmware version numbers and stores them into the
3285  *      adapter Adapter Parameters structure.  If any of the efforts fails
3286  *      the first failure will be returned, but all of the version numbers
3287  *      will be read.
3288  */
3289 int t4_get_version_info(struct adapter *adapter)
3290 {
3291         int ret = 0;
3292
3293         #define FIRST_RET(__getvinfo) \
3294         do { \
3295                 int __ret = __getvinfo; \
3296                 if (__ret && !ret) \
3297                         ret = __ret; \
3298         } while (0)
3299
3300         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3301         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3302         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3303         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3304         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3305         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3306
3307         #undef FIRST_RET
3308         return ret;
3309 }
3310
3311 /**
3312  *      t4_dump_version_info - dump all of the adapter configuration IDs
3313  *      @adapter: the adapter
3314  *
3315  *      Dumps all of the various bits of adapter configuration version/revision
3316  *      IDs information.  This is typically called at some point after
3317  *      t4_get_version_info() has been called.
3318  */
3319 void t4_dump_version_info(struct adapter *adapter)
3320 {
3321         /* Device information */
3322         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3323                  adapter->params.vpd.id,
3324                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3325         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3326                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3327
3328         /* Firmware Version */
3329         if (!adapter->params.fw_vers)
3330                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3331         else
3332                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3333                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3334                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3335                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3336                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3337
3338         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3339          * Firmware, so dev_info() is more appropriate here.)
3340          */
3341         if (!adapter->params.bs_vers)
3342                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3343         else
3344                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3345                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3346                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3347                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3348                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3349
3350         /* TP Microcode Version */
3351         if (!adapter->params.tp_vers)
3352                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3353         else
3354                 dev_info(adapter->pdev_dev,
3355                          "TP Microcode version: %u.%u.%u.%u\n",
3356                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3357                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3358                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3359                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3360
3361         /* Expansion ROM version */
3362         if (!adapter->params.er_vers)
3363                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3364         else
3365                 dev_info(adapter->pdev_dev,
3366                          "Expansion ROM version: %u.%u.%u.%u\n",
3367                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3368                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3369                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3370                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3371
3372         /* Serial Configuration version */
3373         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3374                  adapter->params.scfg_vers);
3375
3376         /* VPD Version */
3377         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3378                  adapter->params.vpd_vers);
3379 }
3380
3381 /**
3382  *      t4_check_fw_version - check if the FW is supported with this driver
3383  *      @adap: the adapter
3384  *
3385  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3386  *      if there's exact match, a negative error if the version could not be
3387  *      read or there's a major version mismatch
3388  */
3389 int t4_check_fw_version(struct adapter *adap)
3390 {
3391         int i, ret, major, minor, micro;
3392         int exp_major, exp_minor, exp_micro;
3393         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3394
3395         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3396         /* Try multiple times before returning error */
3397         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3398                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3399
3400         if (ret)
3401                 return ret;
3402
3403         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3404         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3405         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3406
3407         switch (chip_version) {
3408         case CHELSIO_T4:
3409                 exp_major = T4FW_MIN_VERSION_MAJOR;
3410                 exp_minor = T4FW_MIN_VERSION_MINOR;
3411                 exp_micro = T4FW_MIN_VERSION_MICRO;
3412                 break;
3413         case CHELSIO_T5:
3414                 exp_major = T5FW_MIN_VERSION_MAJOR;
3415                 exp_minor = T5FW_MIN_VERSION_MINOR;
3416                 exp_micro = T5FW_MIN_VERSION_MICRO;
3417                 break;
3418         case CHELSIO_T6:
3419                 exp_major = T6FW_MIN_VERSION_MAJOR;
3420                 exp_minor = T6FW_MIN_VERSION_MINOR;
3421                 exp_micro = T6FW_MIN_VERSION_MICRO;
3422                 break;
3423         default:
3424                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3425                         adap->chip);
3426                 return -EINVAL;
3427         }
3428
3429         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3430             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3431                 dev_err(adap->pdev_dev,
3432                         "Card has firmware version %u.%u.%u, minimum "
3433                         "supported firmware is %u.%u.%u.\n", major, minor,
3434                         micro, exp_major, exp_minor, exp_micro);
3435                 return -EFAULT;
3436         }
3437         return 0;
3438 }
3439
3440 /* Is the given firmware API compatible with the one the driver was compiled
3441  * with?
3442  */
3443 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3444 {
3445
3446         /* short circuit if it's the exact same firmware version */
3447         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3448                 return 1;
3449
3450 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3451         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3452             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3453                 return 1;
3454 #undef SAME_INTF
3455
3456         return 0;
3457 }
3458
3459 /* The firmware in the filesystem is usable, but should it be installed?
3460  * This routine explains itself in detail if it indicates the filesystem
3461  * firmware should be installed.
3462  */
3463 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3464                                 int k, int c)
3465 {
3466         const char *reason;
3467
3468         if (!card_fw_usable) {
3469                 reason = "incompatible or unusable";
3470                 goto install;
3471         }
3472
3473         if (k > c) {
3474                 reason = "older than the version supported with this driver";
3475                 goto install;
3476         }
3477
3478         return 0;
3479
3480 install:
3481         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3482                 "installing firmware %u.%u.%u.%u on card.\n",
3483                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3484                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3485                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3486                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3487
3488         return 1;
3489 }
3490
3491 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3492                const u8 *fw_data, unsigned int fw_size,
3493                struct fw_hdr *card_fw, enum dev_state state,
3494                int *reset)
3495 {
3496         int ret, card_fw_usable, fs_fw_usable;
3497         const struct fw_hdr *fs_fw;
3498         const struct fw_hdr *drv_fw;
3499
3500         drv_fw = &fw_info->fw_hdr;
3501
3502         /* Read the header of the firmware on the card */
3503         ret = t4_read_flash(adap, FLASH_FW_START,
3504                             sizeof(*card_fw) / sizeof(uint32_t),
3505                             (uint32_t *)card_fw, 1);
3506         if (ret == 0) {
3507                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3508         } else {
3509                 dev_err(adap->pdev_dev,
3510                         "Unable to read card's firmware header: %d\n", ret);
3511                 card_fw_usable = 0;
3512         }
3513
3514         if (fw_data != NULL) {
3515                 fs_fw = (const void *)fw_data;
3516                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3517         } else {
3518                 fs_fw = NULL;
3519                 fs_fw_usable = 0;
3520         }
3521
3522         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3523             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3524                 /* Common case: the firmware on the card is an exact match and
3525                  * the filesystem one is an exact match too, or the filesystem
3526                  * one is absent/incompatible.
3527                  */
3528         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3529                    should_install_fs_fw(adap, card_fw_usable,
3530                                         be32_to_cpu(fs_fw->fw_ver),
3531                                         be32_to_cpu(card_fw->fw_ver))) {
3532                 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3533                                     fw_size, 0);
3534                 if (ret != 0) {
3535                         dev_err(adap->pdev_dev,
3536                                 "failed to install firmware: %d\n", ret);
3537                         goto bye;
3538                 }
3539
3540                 /* Installed successfully, update the cached header too. */
3541                 *card_fw = *fs_fw;
3542                 card_fw_usable = 1;
3543                 *reset = 0;     /* already reset as part of load_fw */
3544         }
3545
3546         if (!card_fw_usable) {
3547                 uint32_t d, c, k;
3548
3549                 d = be32_to_cpu(drv_fw->fw_ver);
3550                 c = be32_to_cpu(card_fw->fw_ver);
3551                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3552
3553                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3554                         "chip state %d, "
3555                         "driver compiled with %d.%d.%d.%d, "
3556                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3557                         state,
3558                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3559                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3560                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3561                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3562                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3563                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3564                 ret = -EINVAL;
3565                 goto bye;
3566         }
3567
3568         /* We're using whatever's on the card and it's known to be good. */
3569         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3570         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3571
3572 bye:
3573         return ret;
3574 }
3575
3576 /**
3577  *      t4_flash_erase_sectors - erase a range of flash sectors
3578  *      @adapter: the adapter
3579  *      @start: the first sector to erase
3580  *      @end: the last sector to erase
3581  *
3582  *      Erases the sectors in the given inclusive range.
3583  */
3584 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3585 {
3586         int ret = 0;
3587
3588         if (end >= adapter->params.sf_nsec)
3589                 return -EINVAL;
3590
3591         while (start <= end) {
3592                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3593                     (ret = sf1_write(adapter, 4, 0, 1,
3594                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3595                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3596                         dev_err(adapter->pdev_dev,
3597                                 "erase of flash sector %d failed, error %d\n",
3598                                 start, ret);
3599                         break;
3600                 }
3601                 start++;
3602         }
3603         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3604         return ret;
3605 }
3606
3607 /**
3608  *      t4_flash_cfg_addr - return the address of the flash configuration file
3609  *      @adapter: the adapter
3610  *
3611  *      Return the address within the flash where the Firmware Configuration
3612  *      File is stored.
3613  */
3614 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3615 {
3616         if (adapter->params.sf_size == 0x100000)
3617                 return FLASH_FPGA_CFG_START;
3618         else
3619                 return FLASH_CFG_START;
3620 }
3621
3622 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3623  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3624  * and emit an error message for mismatched firmware to save our caller the
3625  * effort ...
3626  */
3627 static bool t4_fw_matches_chip(const struct adapter *adap,
3628                                const struct fw_hdr *hdr)
3629 {
3630         /* The expression below will return FALSE for any unsupported adapter
3631          * which will keep us "honest" in the future ...
3632          */
3633         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3634             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3635             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3636                 return true;
3637
3638         dev_err(adap->pdev_dev,
3639                 "FW image (%d) is not suitable for this adapter (%d)\n",
3640                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3641         return false;
3642 }
3643
3644 /**
3645  *      t4_load_fw - download firmware
3646  *      @adap: the adapter
3647  *      @fw_data: the firmware image to write
3648  *      @size: image size
3649  *
3650  *      Write the supplied firmware image to the card's serial flash.
3651  */
3652 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3653 {
3654         u32 csum;
3655         int ret, addr;
3656         unsigned int i;
3657         u8 first_page[SF_PAGE_SIZE];
3658         const __be32 *p = (const __be32 *)fw_data;
3659         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3660         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3661         unsigned int fw_start_sec = FLASH_FW_START_SEC;
3662         unsigned int fw_size = FLASH_FW_MAX_SIZE;
3663         unsigned int fw_start = FLASH_FW_START;
3664
3665         if (!size) {
3666                 dev_err(adap->pdev_dev, "FW image has no data\n");
3667                 return -EINVAL;
3668         }
3669         if (size & 511) {
3670                 dev_err(adap->pdev_dev,
3671                         "FW image size not multiple of 512 bytes\n");
3672                 return -EINVAL;
3673         }
3674         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3675                 dev_err(adap->pdev_dev,
3676                         "FW image size differs from size in FW header\n");
3677                 return -EINVAL;
3678         }
3679         if (size > fw_size) {
3680                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3681                         fw_size);
3682                 return -EFBIG;
3683         }
3684         if (!t4_fw_matches_chip(adap, hdr))
3685                 return -EINVAL;
3686
3687         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3688                 csum += be32_to_cpu(p[i]);
3689
3690         if (csum != 0xffffffff) {
3691                 dev_err(adap->pdev_dev,
3692                         "corrupted firmware image, checksum %#x\n", csum);
3693                 return -EINVAL;
3694         }
3695
3696         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3697         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3698         if (ret)
3699                 goto out;
3700
3701         /*
3702          * We write the correct version at the end so the driver can see a bad
3703          * version if the FW write fails.  Start by writing a copy of the
3704          * first page with a bad version.
3705          */
3706         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3707         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3708         ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3709         if (ret)
3710                 goto out;
3711
3712         addr = fw_start;
3713         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3714                 addr += SF_PAGE_SIZE;
3715                 fw_data += SF_PAGE_SIZE;
3716                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3717                 if (ret)
3718                         goto out;
3719         }
3720
3721         ret = t4_write_flash(adap,
3722                              fw_start + offsetof(struct fw_hdr, fw_ver),
3723                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3724 out:
3725         if (ret)
3726                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3727                         ret);
3728         else
3729                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3730         return ret;
3731 }
3732
3733 /**
3734  *      t4_phy_fw_ver - return current PHY firmware version
3735  *      @adap: the adapter
3736  *      @phy_fw_ver: return value buffer for PHY firmware version
3737  *
3738  *      Returns the current version of external PHY firmware on the
3739  *      adapter.
3740  */
3741 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3742 {
3743         u32 param, val;
3744         int ret;
3745
3746         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3747                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3748                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3749                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3750         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3751                               &param, &val);
3752         if (ret)
3753                 return ret;
3754         *phy_fw_ver = val;
3755         return 0;
3756 }
3757
3758 /**
3759  *      t4_load_phy_fw - download port PHY firmware
3760  *      @adap: the adapter
3761  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3762  *      @win_lock: the lock to use to guard the memory copy
3763  *      @phy_fw_version: function to check PHY firmware versions
3764  *      @phy_fw_data: the PHY firmware image to write
3765  *      @phy_fw_size: image size
3766  *
3767  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3768  *      @phy_fw_version is supplied, then it will be used to determine if
3769  *      it's necessary to perform the transfer by comparing the version
3770  *      of any existing adapter PHY firmware with that of the passed in
3771  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3772  *      around the call to t4_memory_rw() which transfers the PHY firmware
3773  *      to the adapter.
3774  *
3775  *      A negative error number will be returned if an error occurs.  If
3776  *      version number support is available and there's no need to upgrade
3777  *      the firmware, 0 will be returned.  If firmware is successfully
3778  *      transferred to the adapter, 1 will be retured.
3779  *
3780  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3781  *      a result, a RESET of the adapter would cause that RAM to lose its
3782  *      contents.  Thus, loading PHY firmware on such adapters must happen
3783  *      after any FW_RESET_CMDs ...
3784  */
3785 int t4_load_phy_fw(struct adapter *adap,
3786                    int win, spinlock_t *win_lock,
3787                    int (*phy_fw_version)(const u8 *, size_t),
3788                    const u8 *phy_fw_data, size_t phy_fw_size)
3789 {
3790         unsigned long mtype = 0, maddr = 0;
3791         u32 param, val;
3792         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3793         int ret;
3794
3795         /* If we have version number support, then check to see if the adapter
3796          * already has up-to-date PHY firmware loaded.
3797          */
3798          if (phy_fw_version) {
3799                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3800                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3801                 if (ret < 0)
3802                         return ret;
3803
3804                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3805                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3806                                 "version %#x\n", cur_phy_fw_ver);
3807                         return 0;
3808                 }
3809         }
3810
3811         /* Ask the firmware where it wants us to copy the PHY firmware image.
3812          * The size of the file requires a special version of the READ coommand
3813          * which will pass the file size via the values field in PARAMS_CMD and
3814          * retrieve the return value from firmware and place it in the same
3815          * buffer values
3816          */
3817         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3818                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3819                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3820                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3821         val = phy_fw_size;
3822         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3823                                  &param, &val, 1, true);
3824         if (ret < 0)
3825                 return ret;
3826         mtype = val >> 8;
3827         maddr = (val & 0xff) << 16;
3828
3829         /* Copy the supplied PHY Firmware image to the adapter memory location
3830          * allocated by the adapter firmware.
3831          */
3832         if (win_lock)
3833                 spin_lock_bh(win_lock);
3834         ret = t4_memory_rw(adap, win, mtype, maddr,
3835                            phy_fw_size, (__be32 *)phy_fw_data,
3836                            T4_MEMORY_WRITE);
3837         if (win_lock)
3838                 spin_unlock_bh(win_lock);
3839         if (ret)
3840                 return ret;
3841
3842         /* Tell the firmware that the PHY firmware image has been written to
3843          * RAM and it can now start copying it over to the PHYs.  The chip
3844          * firmware will RESET the affected PHYs as part of this operation
3845          * leaving them running the new PHY firmware image.
3846          */
3847         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3848                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3849                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3850                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3851         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3852                                     &param, &val, 30000);
3853
3854         /* If we have version number support, then check to see that the new
3855          * firmware got loaded properly.
3856          */
3857         if (phy_fw_version) {
3858                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3859                 if (ret < 0)
3860                         return ret;
3861
3862                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3863                         CH_WARN(adap, "PHY Firmware did not update: "
3864                                 "version on adapter %#x, "
3865                                 "version flashed %#x\n",
3866                                 cur_phy_fw_ver, new_phy_fw_vers);
3867                         return -ENXIO;
3868                 }
3869         }
3870
3871         return 1;
3872 }
3873
3874 /**
3875  *      t4_fwcache - firmware cache operation
3876  *      @adap: the adapter
3877  *      @op  : the operation (flush or flush and invalidate)
3878  */
3879 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3880 {
3881         struct fw_params_cmd c;
3882
3883         memset(&c, 0, sizeof(c));
3884         c.op_to_vfn =
3885                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3886                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3887                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3888                             FW_PARAMS_CMD_VFN_V(0));
3889         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3890         c.param[0].mnem =
3891                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3892                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3893         c.param[0].val = cpu_to_be32(op);
3894
3895         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3896 }
3897
3898 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3899                         unsigned int *pif_req_wrptr,
3900                         unsigned int *pif_rsp_wrptr)
3901 {
3902         int i, j;
3903         u32 cfg, val, req, rsp;
3904
3905         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3906         if (cfg & LADBGEN_F)
3907                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3908
3909         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3910         req = POLADBGWRPTR_G(val);
3911         rsp = PILADBGWRPTR_G(val);
3912         if (pif_req_wrptr)
3913                 *pif_req_wrptr = req;
3914         if (pif_rsp_wrptr)
3915                 *pif_rsp_wrptr = rsp;
3916
3917         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3918                 for (j = 0; j < 6; j++) {
3919                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3920                                      PILADBGRDPTR_V(rsp));
3921                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3922                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3923                         req++;
3924                         rsp++;
3925                 }
3926                 req = (req + 2) & POLADBGRDPTR_M;
3927                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3928         }
3929         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3930 }
3931
3932 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3933 {
3934         u32 cfg;
3935         int i, j, idx;
3936
3937         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3938         if (cfg & LADBGEN_F)
3939                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3940
3941         for (i = 0; i < CIM_MALA_SIZE; i++) {
3942                 for (j = 0; j < 5; j++) {
3943                         idx = 8 * i + j;
3944                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3945                                      PILADBGRDPTR_V(idx));
3946                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3947                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3948                 }
3949         }
3950         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3951 }
3952
3953 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3954 {
3955         unsigned int i, j;
3956
3957         for (i = 0; i < 8; i++) {
3958                 u32 *p = la_buf + i;
3959
3960                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3961                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3962                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3963                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3964                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3965         }
3966 }
3967
3968 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3969                      FW_PORT_CAP32_ANEG)
3970
3971 /**
3972  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3973  *      @caps16: a 16-bit Port Capabilities value
3974  *
3975  *      Returns the equivalent 32-bit Port Capabilities value.
3976  */
3977 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3978 {
3979         fw_port_cap32_t caps32 = 0;
3980
3981         #define CAP16_TO_CAP32(__cap) \
3982                 do { \
3983                         if (caps16 & FW_PORT_CAP_##__cap) \
3984                                 caps32 |= FW_PORT_CAP32_##__cap; \
3985                 } while (0)
3986
3987         CAP16_TO_CAP32(SPEED_100M);
3988         CAP16_TO_CAP32(SPEED_1G);
3989         CAP16_TO_CAP32(SPEED_25G);
3990         CAP16_TO_CAP32(SPEED_10G);
3991         CAP16_TO_CAP32(SPEED_40G);
3992         CAP16_TO_CAP32(SPEED_100G);
3993         CAP16_TO_CAP32(FC_RX);
3994         CAP16_TO_CAP32(FC_TX);
3995         CAP16_TO_CAP32(ANEG);
3996         CAP16_TO_CAP32(FORCE_PAUSE);
3997         CAP16_TO_CAP32(MDIAUTO);
3998         CAP16_TO_CAP32(MDISTRAIGHT);
3999         CAP16_TO_CAP32(FEC_RS);
4000         CAP16_TO_CAP32(FEC_BASER_RS);
4001         CAP16_TO_CAP32(802_3_PAUSE);
4002         CAP16_TO_CAP32(802_3_ASM_DIR);
4003
4004         #undef CAP16_TO_CAP32
4005
4006         return caps32;
4007 }
4008
4009 /**
4010  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4011  *      @caps32: a 32-bit Port Capabilities value
4012  *
4013  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
4014  *      not all 32-bit Port Capabilities can be represented in the 16-bit
4015  *      Port Capabilities and some fields/values may not make it.
4016  */
4017 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4018 {
4019         fw_port_cap16_t caps16 = 0;
4020
4021         #define CAP32_TO_CAP16(__cap) \
4022                 do { \
4023                         if (caps32 & FW_PORT_CAP32_##__cap) \
4024                                 caps16 |= FW_PORT_CAP_##__cap; \
4025                 } while (0)
4026
4027         CAP32_TO_CAP16(SPEED_100M);
4028         CAP32_TO_CAP16(SPEED_1G);
4029         CAP32_TO_CAP16(SPEED_10G);
4030         CAP32_TO_CAP16(SPEED_25G);
4031         CAP32_TO_CAP16(SPEED_40G);
4032         CAP32_TO_CAP16(SPEED_100G);
4033         CAP32_TO_CAP16(FC_RX);
4034         CAP32_TO_CAP16(FC_TX);
4035         CAP32_TO_CAP16(802_3_PAUSE);
4036         CAP32_TO_CAP16(802_3_ASM_DIR);
4037         CAP32_TO_CAP16(ANEG);
4038         CAP32_TO_CAP16(FORCE_PAUSE);
4039         CAP32_TO_CAP16(MDIAUTO);
4040         CAP32_TO_CAP16(MDISTRAIGHT);
4041         CAP32_TO_CAP16(FEC_RS);
4042         CAP32_TO_CAP16(FEC_BASER_RS);
4043
4044         #undef CAP32_TO_CAP16
4045
4046         return caps16;
4047 }
4048
4049 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4050 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4051 {
4052         enum cc_pause cc_pause = 0;
4053
4054         if (fw_pause & FW_PORT_CAP32_FC_RX)
4055                 cc_pause |= PAUSE_RX;
4056         if (fw_pause & FW_PORT_CAP32_FC_TX)
4057                 cc_pause |= PAUSE_TX;
4058
4059         return cc_pause;
4060 }
4061
4062 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4063 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4064 {
4065         fw_port_cap32_t fw_pause = 0;
4066
4067         if (cc_pause & PAUSE_RX)
4068                 fw_pause |= FW_PORT_CAP32_FC_RX;
4069         if (cc_pause & PAUSE_TX)
4070                 fw_pause |= FW_PORT_CAP32_FC_TX;
4071         if (!(cc_pause & PAUSE_AUTONEG))
4072                 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4073
4074         return fw_pause;
4075 }
4076
4077 /* Translate Firmware Forward Error Correction specification to Common Code */
4078 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4079 {
4080         enum cc_fec cc_fec = 0;
4081
4082         if (fw_fec & FW_PORT_CAP32_FEC_RS)
4083                 cc_fec |= FEC_RS;
4084         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4085                 cc_fec |= FEC_BASER_RS;
4086
4087         return cc_fec;
4088 }
4089
4090 /* Translate Common Code Forward Error Correction specification to Firmware */
4091 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4092 {
4093         fw_port_cap32_t fw_fec = 0;
4094
4095         if (cc_fec & FEC_RS)
4096                 fw_fec |= FW_PORT_CAP32_FEC_RS;
4097         if (cc_fec & FEC_BASER_RS)
4098                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4099
4100         return fw_fec;
4101 }
4102
4103 /**
4104  *      t4_link_l1cfg - apply link configuration to MAC/PHY
4105  *      @adapter: the adapter
4106  *      @mbox: the Firmware Mailbox to use
4107  *      @port: the Port ID
4108  *      @lc: the Port's Link Configuration
4109  *
4110  *      Set up a port's MAC and PHY according to a desired link configuration.
4111  *      - If the PHY can auto-negotiate first decide what to advertise, then
4112  *        enable/disable auto-negotiation as desired, and reset.
4113  *      - If the PHY does not auto-negotiate just reset it.
4114  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4115  *        otherwise do it later based on the outcome of auto-negotiation.
4116  */
4117 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4118                        unsigned int port, struct link_config *lc,
4119                        bool sleep_ok, int timeout)
4120 {
4121         unsigned int fw_caps = adapter->params.fw_caps_support;
4122         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
4123         struct fw_port_cmd cmd;
4124         unsigned int fw_mdi;
4125         int ret;
4126
4127         fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4128         /* Convert driver coding of Pause Frame Flow Control settings into the
4129          * Firmware's API.
4130          */
4131         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4132
4133         /* Convert Common Code Forward Error Control settings into the
4134          * Firmware's API.  If the current Requested FEC has "Automatic"
4135          * (IEEE 802.3) specified, then we use whatever the Firmware
4136          * sent us as part of it's IEEE 802.3-based interpratation of
4137          * the Transceiver Module EPROM FEC parameters.  Otherwise we
4138          * use whatever is in the current Requested FEC settings.
4139          */
4140         if (lc->requested_fec & FEC_AUTO)
4141                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4142         else
4143                 cc_fec = lc->requested_fec;
4144         fw_fec = cc_to_fwcap_fec(cc_fec);
4145
4146         /* Figure out what our Requested Port Capabilities are going to be.
4147          */
4148         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4149                 rcap = lc->acaps | fw_fc | fw_fec;
4150                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4151                 lc->fec = cc_fec;
4152         } else if (lc->autoneg == AUTONEG_DISABLE) {
4153                 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4154                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4155                 lc->fec = cc_fec;
4156         } else {
4157                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4158         }
4159
4160         /* Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4161          * we need to exclude this from this check in order to maintain
4162          * compatibility ...
4163          */
4164         if ((rcap & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4165                 dev_err(adapter->pdev_dev,
4166                         "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4167                         rcap, lc->pcaps);
4168                 return -EINVAL;
4169         }
4170
4171         /* And send that on to the Firmware ...
4172          */
4173         memset(&cmd, 0, sizeof(cmd));
4174         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4175                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4176                                        FW_PORT_CMD_PORTID_V(port));
4177         cmd.action_to_len16 =
4178                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4179                                                  ? FW_PORT_ACTION_L1_CFG
4180                                                  : FW_PORT_ACTION_L1_CFG32) |
4181                                                  FW_LEN16(cmd));
4182         if (fw_caps == FW_CAPS16)
4183                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4184         else
4185                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4186
4187         ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4188                                       sleep_ok, timeout);
4189         if (ret) {
4190                 dev_err(adapter->pdev_dev,
4191                         "Requested Port Capabilities %#x rejected, error %d\n",
4192                         rcap, -ret);
4193                 return ret;
4194         }
4195         return ret;
4196 }
4197
4198 /**
4199  *      t4_restart_aneg - restart autonegotiation
4200  *      @adap: the adapter
4201  *      @mbox: mbox to use for the FW command
4202  *      @port: the port id
4203  *
4204  *      Restarts autonegotiation for the selected port.
4205  */
4206 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4207 {
4208         struct fw_port_cmd c;
4209
4210         memset(&c, 0, sizeof(c));
4211         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4212                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4213                                      FW_PORT_CMD_PORTID_V(port));
4214         c.action_to_len16 =
4215                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4216                             FW_LEN16(c));
4217         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4218         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4219 }
4220
4221 typedef void (*int_handler_t)(struct adapter *adap);
4222
4223 struct intr_info {
4224         unsigned int mask;       /* bits to check in interrupt status */
4225         const char *msg;         /* message to print or NULL */
4226         short stat_idx;          /* stat counter to increment or -1 */
4227         unsigned short fatal;    /* whether the condition reported is fatal */
4228         int_handler_t int_handler; /* platform-specific int handler */
4229 };
4230
4231 /**
4232  *      t4_handle_intr_status - table driven interrupt handler
4233  *      @adapter: the adapter that generated the interrupt
4234  *      @reg: the interrupt status register to process
4235  *      @acts: table of interrupt actions
4236  *
4237  *      A table driven interrupt handler that applies a set of masks to an
4238  *      interrupt status word and performs the corresponding actions if the
4239  *      interrupts described by the mask have occurred.  The actions include
4240  *      optionally emitting a warning or alert message.  The table is terminated
4241  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4242  *      conditions.
4243  */
4244 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4245                                  const struct intr_info *acts)
4246 {
4247         int fatal = 0;
4248         unsigned int mask = 0;
4249         unsigned int status = t4_read_reg(adapter, reg);
4250
4251         for ( ; acts->mask; ++acts) {
4252                 if (!(status & acts->mask))
4253                         continue;
4254                 if (acts->fatal) {
4255                         fatal++;
4256                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4257                                   status & acts->mask);
4258                 } else if (acts->msg && printk_ratelimit())
4259                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4260                                  status & acts->mask);
4261                 if (acts->int_handler)
4262                         acts->int_handler(adapter);
4263                 mask |= acts->mask;
4264         }
4265         status &= mask;
4266         if (status)                           /* clear processed interrupts */
4267                 t4_write_reg(adapter, reg, status);
4268         return fatal;
4269 }
4270
4271 /*
4272  * Interrupt handler for the PCIE module.
4273  */
4274 static void pcie_intr_handler(struct adapter *adapter)
4275 {
4276         static const struct intr_info sysbus_intr_info[] = {
4277                 { RNPP_F, "RXNP array parity error", -1, 1 },
4278                 { RPCP_F, "RXPC array parity error", -1, 1 },
4279                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4280                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4281                 { RFTP_F, "RXFT array parity error", -1, 1 },
4282                 { 0 }
4283         };
4284         static const struct intr_info pcie_port_intr_info[] = {
4285                 { TPCP_F, "TXPC array parity error", -1, 1 },
4286                 { TNPP_F, "TXNP array parity error", -1, 1 },
4287                 { TFTP_F, "TXFT array parity error", -1, 1 },
4288                 { TCAP_F, "TXCA array parity error", -1, 1 },
4289                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4290                 { RCAP_F, "RXCA array parity error", -1, 1 },
4291                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4292                 { RDPE_F, "Rx data parity error", -1, 1 },
4293                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4294                 { 0 }
4295         };
4296         static const struct intr_info pcie_intr_info[] = {
4297                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4298                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4299                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4300                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4301                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4302                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4303                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4304                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4305                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4306                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4307                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4308                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4309                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4310                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4311                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4312                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4313                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4314                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4315                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4316                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4317                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4318                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4319                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4320                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4321                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4322                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4323                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4324                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4325                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4326                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4327                   -1, 0 },
4328                 { 0 }
4329         };
4330
4331         static struct intr_info t5_pcie_intr_info[] = {
4332                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4333                   -1, 1 },
4334                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4335                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4336                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4337                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4338                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4339                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4340                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4341                   -1, 1 },
4342                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4343                   -1, 1 },
4344                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4345                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4346                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4347                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4348                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4349                   -1, 1 },
4350                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4351                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4352                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4353                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4354                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4355                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4356                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4357                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4358                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4359                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4360                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4361                   -1, 1 },
4362                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4363                   -1, 1 },
4364                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4365                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4366                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4367                 { READRSPERR_F, "Outbound read error", -1, 0 },
4368                 { 0 }
4369         };
4370
4371         int fat;
4372
4373         if (is_t4(adapter->params.chip))
4374                 fat = t4_handle_intr_status(adapter,
4375                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4376                                 sysbus_intr_info) +
4377                         t4_handle_intr_status(adapter,
4378                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4379                                         pcie_port_intr_info) +
4380                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4381                                               pcie_intr_info);
4382         else
4383                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4384                                             t5_pcie_intr_info);
4385
4386         if (fat)
4387                 t4_fatal_err(adapter);
4388 }
4389
4390 /*
4391  * TP interrupt handler.
4392  */
4393 static void tp_intr_handler(struct adapter *adapter)
4394 {
4395         static const struct intr_info tp_intr_info[] = {
4396                 { 0x3fffffff, "TP parity error", -1, 1 },
4397                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4398                 { 0 }
4399         };
4400
4401         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4402                 t4_fatal_err(adapter);
4403 }
4404
4405 /*
4406  * SGE interrupt handler.
4407  */
4408 static void sge_intr_handler(struct adapter *adapter)
4409 {
4410         u64 v;
4411         u32 err;
4412
4413         static const struct intr_info sge_intr_info[] = {
4414                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4415                   "SGE received CPL exceeding IQE size", -1, 1 },
4416                 { ERR_INVALID_CIDX_INC_F,
4417                   "SGE GTS CIDX increment too large", -1, 0 },
4418                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4419                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4420                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4421                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4422                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4423                   0 },
4424                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4425                   0 },
4426                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4427                   0 },
4428                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4429                   0 },
4430                 { ERR_ING_CTXT_PRIO_F,
4431                   "SGE too many priority ingress contexts", -1, 0 },
4432                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4433                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4434                 { 0 }
4435         };
4436
4437         static struct intr_info t4t5_sge_intr_info[] = {
4438                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4439                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4440                 { ERR_EGR_CTXT_PRIO_F,
4441                   "SGE too many priority egress contexts", -1, 0 },
4442                 { 0 }
4443         };
4444
4445         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4446                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4447         if (v) {
4448                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4449                                 (unsigned long long)v);
4450                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4451                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4452         }
4453
4454         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4455         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4456                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4457                                            t4t5_sge_intr_info);
4458
4459         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4460         if (err & ERROR_QID_VALID_F) {
4461                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4462                         ERROR_QID_G(err));
4463                 if (err & UNCAPTURED_ERROR_F)
4464                         dev_err(adapter->pdev_dev,
4465                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4466                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4467                              UNCAPTURED_ERROR_F);
4468         }
4469
4470         if (v != 0)
4471                 t4_fatal_err(adapter);
4472 }
4473
4474 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4475                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4476 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4477                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4478
4479 /*
4480  * CIM interrupt handler.
4481  */
4482 static void cim_intr_handler(struct adapter *adapter)
4483 {
4484         static const struct intr_info cim_intr_info[] = {
4485                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4486                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4487                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4488                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4489                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4490                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4491                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4492                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4493                 { 0 }
4494         };
4495         static const struct intr_info cim_upintr_info[] = {
4496                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4497                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4498                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4499                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4500                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4501                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4502                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4503                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4504                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4505                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4506                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4507                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4508                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4509                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4510                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4511                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4512                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4513                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4514                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4515                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4516                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4517                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4518                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4519                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4520                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4521                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4522                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4523                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4524                 { 0 }
4525         };
4526
4527         u32 val, fw_err;
4528         int fat;
4529
4530         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4531         if (fw_err & PCIE_FW_ERR_F)
4532                 t4_report_fw_error(adapter);
4533
4534         /* When the Firmware detects an internal error which normally
4535          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4536          * in order to make sure the Host sees the Firmware Crash.  So
4537          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4538          * ignore the Timer0 interrupt.
4539          */
4540
4541         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4542         if (val & TIMER0INT_F)
4543                 if (!(fw_err & PCIE_FW_ERR_F) ||
4544                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4545                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4546                                      TIMER0INT_F);
4547
4548         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4549                                     cim_intr_info) +
4550               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4551                                     cim_upintr_info);
4552         if (fat)
4553                 t4_fatal_err(adapter);
4554 }
4555
4556 /*
4557  * ULP RX interrupt handler.
4558  */
4559 static void ulprx_intr_handler(struct adapter *adapter)
4560 {
4561         static const struct intr_info ulprx_intr_info[] = {
4562                 { 0x1800000, "ULPRX context error", -1, 1 },
4563                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4564                 { 0 }
4565         };
4566
4567         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4568                 t4_fatal_err(adapter);
4569 }
4570
4571 /*
4572  * ULP TX interrupt handler.
4573  */
4574 static void ulptx_intr_handler(struct adapter *adapter)
4575 {
4576         static const struct intr_info ulptx_intr_info[] = {
4577                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4578                   0 },
4579                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4580                   0 },
4581                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4582                   0 },
4583                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4584                   0 },
4585                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4586                 { 0 }
4587         };
4588
4589         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4590                 t4_fatal_err(adapter);
4591 }
4592
4593 /*
4594  * PM TX interrupt handler.
4595  */
4596 static void pmtx_intr_handler(struct adapter *adapter)
4597 {
4598         static const struct intr_info pmtx_intr_info[] = {
4599                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4600                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4601                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4602                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4603                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4604                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4605                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4606                   -1, 1 },
4607                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4608                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4609                 { 0 }
4610         };
4611
4612         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4613                 t4_fatal_err(adapter);
4614 }
4615
4616 /*
4617  * PM RX interrupt handler.
4618  */
4619 static void pmrx_intr_handler(struct adapter *adapter)
4620 {
4621         static const struct intr_info pmrx_intr_info[] = {
4622                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4623                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4624                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4625                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4626                   -1, 1 },
4627                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4628                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4629                 { 0 }
4630         };
4631
4632         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4633                 t4_fatal_err(adapter);
4634 }
4635
4636 /*
4637  * CPL switch interrupt handler.
4638  */
4639 static void cplsw_intr_handler(struct adapter *adapter)
4640 {
4641         static const struct intr_info cplsw_intr_info[] = {
4642                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4643                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4644                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4645                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4646                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4647                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4648                 { 0 }
4649         };
4650
4651         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4652                 t4_fatal_err(adapter);
4653 }
4654
4655 /*
4656  * LE interrupt handler.
4657  */
4658 static void le_intr_handler(struct adapter *adap)
4659 {
4660         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4661         static const struct intr_info le_intr_info[] = {
4662                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4663                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4664                 { PARITYERR_F, "LE parity error", -1, 1 },
4665                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4666                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4667                 { 0 }
4668         };
4669
4670         static struct intr_info t6_le_intr_info[] = {
4671                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4672                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4673                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4674                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4675                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4676                 { 0 }
4677         };
4678
4679         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4680                                   (chip <= CHELSIO_T5) ?
4681                                   le_intr_info : t6_le_intr_info))
4682                 t4_fatal_err(adap);
4683 }
4684
4685 /*
4686  * MPS interrupt handler.
4687  */
4688 static void mps_intr_handler(struct adapter *adapter)
4689 {
4690         static const struct intr_info mps_rx_intr_info[] = {
4691                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4692                 { 0 }
4693         };
4694         static const struct intr_info mps_tx_intr_info[] = {
4695                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4696                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4697                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4698                   -1, 1 },
4699                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4700                   -1, 1 },
4701                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4702                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4703                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4704                 { 0 }
4705         };
4706         static const struct intr_info t6_mps_tx_intr_info[] = {
4707                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4708                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4709                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4710                   -1, 1 },
4711                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4712                   -1, 1 },
4713                 /* MPS Tx Bubble is normal for T6 */
4714                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4715                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4716                 { 0 }
4717         };
4718         static const struct intr_info mps_trc_intr_info[] = {
4719                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4720                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4721                   -1, 1 },
4722                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4723                 { 0 }
4724         };
4725         static const struct intr_info mps_stat_sram_intr_info[] = {
4726                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4727                 { 0 }
4728         };
4729         static const struct intr_info mps_stat_tx_intr_info[] = {
4730                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4731                 { 0 }
4732         };
4733         static const struct intr_info mps_stat_rx_intr_info[] = {
4734                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4735                 { 0 }
4736         };
4737         static const struct intr_info mps_cls_intr_info[] = {
4738                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4739                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4740                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4741                 { 0 }
4742         };
4743
4744         int fat;
4745
4746         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4747                                     mps_rx_intr_info) +
4748               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4749                                     is_t6(adapter->params.chip)
4750                                     ? t6_mps_tx_intr_info
4751                                     : mps_tx_intr_info) +
4752               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4753                                     mps_trc_intr_info) +
4754               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4755                                     mps_stat_sram_intr_info) +
4756               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4757                                     mps_stat_tx_intr_info) +
4758               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4759                                     mps_stat_rx_intr_info) +
4760               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4761                                     mps_cls_intr_info);
4762
4763         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4764         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4765         if (fat)
4766                 t4_fatal_err(adapter);
4767 }
4768
4769 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4770                       ECC_UE_INT_CAUSE_F)
4771
4772 /*
4773  * EDC/MC interrupt handler.
4774  */
4775 static void mem_intr_handler(struct adapter *adapter, int idx)
4776 {
4777         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4778
4779         unsigned int addr, cnt_addr, v;
4780
4781         if (idx <= MEM_EDC1) {
4782                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4783                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4784         } else if (idx == MEM_MC) {
4785                 if (is_t4(adapter->params.chip)) {
4786                         addr = MC_INT_CAUSE_A;
4787                         cnt_addr = MC_ECC_STATUS_A;
4788                 } else {
4789                         addr = MC_P_INT_CAUSE_A;
4790                         cnt_addr = MC_P_ECC_STATUS_A;
4791                 }
4792         } else {
4793                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4794                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4795         }
4796
4797         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4798         if (v & PERR_INT_CAUSE_F)
4799                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4800                           name[idx]);
4801         if (v & ECC_CE_INT_CAUSE_F) {
4802                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4803
4804                 t4_edc_err_read(adapter, idx);
4805
4806                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4807                 if (printk_ratelimit())
4808                         dev_warn(adapter->pdev_dev,
4809                                  "%u %s correctable ECC data error%s\n",
4810                                  cnt, name[idx], cnt > 1 ? "s" : "");
4811         }
4812         if (v & ECC_UE_INT_CAUSE_F)
4813                 dev_alert(adapter->pdev_dev,
4814                           "%s uncorrectable ECC data error\n", name[idx]);
4815
4816         t4_write_reg(adapter, addr, v);
4817         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4818                 t4_fatal_err(adapter);
4819 }
4820
4821 /*
4822  * MA interrupt handler.
4823  */
4824 static void ma_intr_handler(struct adapter *adap)
4825 {
4826         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4827
4828         if (status & MEM_PERR_INT_CAUSE_F) {
4829                 dev_alert(adap->pdev_dev,
4830                           "MA parity error, parity status %#x\n",
4831                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4832                 if (is_t5(adap->params.chip))
4833                         dev_alert(adap->pdev_dev,
4834                                   "MA parity error, parity status %#x\n",
4835                                   t4_read_reg(adap,
4836                                               MA_PARITY_ERROR_STATUS2_A));
4837         }
4838         if (status & MEM_WRAP_INT_CAUSE_F) {
4839                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4840                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4841                           "client %u to address %#x\n",
4842                           MEM_WRAP_CLIENT_NUM_G(v),
4843                           MEM_WRAP_ADDRESS_G(v) << 4);
4844         }
4845         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4846         t4_fatal_err(adap);
4847 }
4848
4849 /*
4850  * SMB interrupt handler.
4851  */
4852 static void smb_intr_handler(struct adapter *adap)
4853 {
4854         static const struct intr_info smb_intr_info[] = {
4855                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4856                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4857                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4858                 { 0 }
4859         };
4860
4861         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4862                 t4_fatal_err(adap);
4863 }
4864
4865 /*
4866  * NC-SI interrupt handler.
4867  */
4868 static void ncsi_intr_handler(struct adapter *adap)
4869 {
4870         static const struct intr_info ncsi_intr_info[] = {
4871                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4872                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4873                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4874                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4875                 { 0 }
4876         };
4877
4878         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4879                 t4_fatal_err(adap);
4880 }
4881
4882 /*
4883  * XGMAC interrupt handler.
4884  */
4885 static void xgmac_intr_handler(struct adapter *adap, int port)
4886 {
4887         u32 v, int_cause_reg;
4888
4889         if (is_t4(adap->params.chip))
4890                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4891         else
4892                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4893
4894         v = t4_read_reg(adap, int_cause_reg);
4895
4896         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4897         if (!v)
4898                 return;
4899
4900         if (v & TXFIFO_PRTY_ERR_F)
4901                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4902                           port);
4903         if (v & RXFIFO_PRTY_ERR_F)
4904                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4905                           port);
4906         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4907         t4_fatal_err(adap);
4908 }
4909
4910 /*
4911  * PL interrupt handler.
4912  */
4913 static void pl_intr_handler(struct adapter *adap)
4914 {
4915         static const struct intr_info pl_intr_info[] = {
4916                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4917                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4918                 { 0 }
4919         };
4920
4921         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4922                 t4_fatal_err(adap);
4923 }
4924
4925 #define PF_INTR_MASK (PFSW_F)
4926 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4927                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4928                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4929
4930 /**
4931  *      t4_slow_intr_handler - control path interrupt handler
4932  *      @adapter: the adapter
4933  *
4934  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4935  *      The designation 'slow' is because it involves register reads, while
4936  *      data interrupts typically don't involve any MMIOs.
4937  */
4938 int t4_slow_intr_handler(struct adapter *adapter)
4939 {
4940         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4941
4942         if (!(cause & GLBL_INTR_MASK))
4943                 return 0;
4944         if (cause & CIM_F)
4945                 cim_intr_handler(adapter);
4946         if (cause & MPS_F)
4947                 mps_intr_handler(adapter);
4948         if (cause & NCSI_F)
4949                 ncsi_intr_handler(adapter);
4950         if (cause & PL_F)
4951                 pl_intr_handler(adapter);
4952         if (cause & SMB_F)
4953                 smb_intr_handler(adapter);
4954         if (cause & XGMAC0_F)
4955                 xgmac_intr_handler(adapter, 0);
4956         if (cause & XGMAC1_F)
4957                 xgmac_intr_handler(adapter, 1);
4958         if (cause & XGMAC_KR0_F)
4959                 xgmac_intr_handler(adapter, 2);
4960         if (cause & XGMAC_KR1_F)
4961                 xgmac_intr_handler(adapter, 3);
4962         if (cause & PCIE_F)
4963                 pcie_intr_handler(adapter);
4964         if (cause & MC_F)
4965                 mem_intr_handler(adapter, MEM_MC);
4966         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4967                 mem_intr_handler(adapter, MEM_MC1);
4968         if (cause & EDC0_F)
4969                 mem_intr_handler(adapter, MEM_EDC0);
4970         if (cause & EDC1_F)
4971                 mem_intr_handler(adapter, MEM_EDC1);
4972         if (cause & LE_F)
4973                 le_intr_handler(adapter);
4974         if (cause & TP_F)
4975                 tp_intr_handler(adapter);
4976         if (cause & MA_F)
4977                 ma_intr_handler(adapter);
4978         if (cause & PM_TX_F)
4979                 pmtx_intr_handler(adapter);
4980         if (cause & PM_RX_F)
4981                 pmrx_intr_handler(adapter);
4982         if (cause & ULP_RX_F)
4983                 ulprx_intr_handler(adapter);
4984         if (cause & CPL_SWITCH_F)
4985                 cplsw_intr_handler(adapter);
4986         if (cause & SGE_F)
4987                 sge_intr_handler(adapter);
4988         if (cause & ULP_TX_F)
4989                 ulptx_intr_handler(adapter);
4990
4991         /* Clear the interrupts just processed for which we are the master. */
4992         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4993         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4994         return 1;
4995 }
4996
4997 /**
4998  *      t4_intr_enable - enable interrupts
4999  *      @adapter: the adapter whose interrupts should be enabled
5000  *
5001  *      Enable PF-specific interrupts for the calling function and the top-level
5002  *      interrupt concentrator for global interrupts.  Interrupts are already
5003  *      enabled at each module, here we just enable the roots of the interrupt
5004  *      hierarchies.
5005  *
5006  *      Note: this function should be called only when the driver manages
5007  *      non PF-specific interrupts from the various HW modules.  Only one PCI
5008  *      function at a time should be doing this.
5009  */
5010 void t4_intr_enable(struct adapter *adapter)
5011 {
5012         u32 val = 0;
5013         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5014         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5015                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5016
5017         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5018                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5019         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5020                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5021                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5022                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5023                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5024                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5025                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5026         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5027         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5028 }
5029
5030 /**
5031  *      t4_intr_disable - disable interrupts
5032  *      @adapter: the adapter whose interrupts should be disabled
5033  *
5034  *      Disable interrupts.  We only disable the top-level interrupt
5035  *      concentrators.  The caller must be a PCI function managing global
5036  *      interrupts.
5037  */
5038 void t4_intr_disable(struct adapter *adapter)
5039 {
5040         u32 whoami, pf;
5041
5042         if (pci_channel_offline(adapter->pdev))
5043                 return;
5044
5045         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5046         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5047                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5048
5049         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5050         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5051 }
5052
5053 unsigned int t4_chip_rss_size(struct adapter *adap)
5054 {
5055         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5056                 return RSS_NENTRIES;
5057         else
5058                 return T6_RSS_NENTRIES;
5059 }
5060
5061 /**
5062  *      t4_config_rss_range - configure a portion of the RSS mapping table
5063  *      @adapter: the adapter
5064  *      @mbox: mbox to use for the FW command
5065  *      @viid: virtual interface whose RSS subtable is to be written
5066  *      @start: start entry in the table to write
5067  *      @n: how many table entries to write
5068  *      @rspq: values for the response queue lookup table
5069  *      @nrspq: number of values in @rspq
5070  *
5071  *      Programs the selected part of the VI's RSS mapping table with the
5072  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
5073  *      until the full table range is populated.
5074  *
5075  *      The caller must ensure the values in @rspq are in the range allowed for
5076  *      @viid.
5077  */
5078 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5079                         int start, int n, const u16 *rspq, unsigned int nrspq)
5080 {
5081         int ret;
5082         const u16 *rsp = rspq;
5083         const u16 *rsp_end = rspq + nrspq;
5084         struct fw_rss_ind_tbl_cmd cmd;
5085
5086         memset(&cmd, 0, sizeof(cmd));
5087         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5088                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5089                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
5090         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5091
5092         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5093         while (n > 0) {
5094                 int nq = min(n, 32);
5095                 __be32 *qp = &cmd.iq0_to_iq2;
5096
5097                 cmd.niqid = cpu_to_be16(nq);
5098                 cmd.startidx = cpu_to_be16(start);
5099
5100                 start += nq;
5101                 n -= nq;
5102
5103                 while (nq > 0) {
5104                         unsigned int v;
5105
5106                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5107                         if (++rsp >= rsp_end)
5108                                 rsp = rspq;
5109                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5110                         if (++rsp >= rsp_end)
5111                                 rsp = rspq;
5112                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5113                         if (++rsp >= rsp_end)
5114                                 rsp = rspq;
5115
5116                         *qp++ = cpu_to_be32(v);
5117                         nq -= 3;
5118                 }
5119
5120                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5121                 if (ret)
5122                         return ret;
5123         }
5124         return 0;
5125 }
5126
5127 /**
5128  *      t4_config_glbl_rss - configure the global RSS mode
5129  *      @adapter: the adapter
5130  *      @mbox: mbox to use for the FW command
5131  *      @mode: global RSS mode
5132  *      @flags: mode-specific flags
5133  *
5134  *      Sets the global RSS mode.
5135  */
5136 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5137                        unsigned int flags)
5138 {
5139         struct fw_rss_glb_config_cmd c;
5140
5141         memset(&c, 0, sizeof(c));
5142         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5143                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5144         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5145         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5146                 c.u.manual.mode_pkd =
5147                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5148         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5149                 c.u.basicvirtual.mode_pkd =
5150                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5151                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5152         } else
5153                 return -EINVAL;
5154         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5155 }
5156
5157 /**
5158  *      t4_config_vi_rss - configure per VI RSS settings
5159  *      @adapter: the adapter
5160  *      @mbox: mbox to use for the FW command
5161  *      @viid: the VI id
5162  *      @flags: RSS flags
5163  *      @defq: id of the default RSS queue for the VI.
5164  *
5165  *      Configures VI-specific RSS properties.
5166  */
5167 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5168                      unsigned int flags, unsigned int defq)
5169 {
5170         struct fw_rss_vi_config_cmd c;
5171
5172         memset(&c, 0, sizeof(c));
5173         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5174                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5175                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5176         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5177         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5178                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5179         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5180 }
5181
5182 /* Read an RSS table row */
5183 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5184 {
5185         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5186         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5187                                    5, 0, val);
5188 }
5189
5190 /**
5191  *      t4_read_rss - read the contents of the RSS mapping table
5192  *      @adapter: the adapter
5193  *      @map: holds the contents of the RSS mapping table
5194  *
5195  *      Reads the contents of the RSS hash->queue mapping table.
5196  */
5197 int t4_read_rss(struct adapter *adapter, u16 *map)
5198 {
5199         int i, ret, nentries;
5200         u32 val;
5201
5202         nentries = t4_chip_rss_size(adapter);
5203         for (i = 0; i < nentries / 2; ++i) {
5204                 ret = rd_rss_row(adapter, i, &val);
5205                 if (ret)
5206                         return ret;
5207                 *map++ = LKPTBLQUEUE0_G(val);
5208                 *map++ = LKPTBLQUEUE1_G(val);
5209         }
5210         return 0;
5211 }
5212
5213 static unsigned int t4_use_ldst(struct adapter *adap)
5214 {
5215         return (adap->flags & FW_OK) && !adap->use_bd;
5216 }
5217
5218 /**
5219  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5220  * @adap: the adapter
5221  * @cmd: TP fw ldst address space type
5222  * @vals: where the indirect register values are stored/written
5223  * @nregs: how many indirect registers to read/write
5224  * @start_idx: index of first indirect register to read/write
5225  * @rw: Read (1) or Write (0)
5226  * @sleep_ok: if true we may sleep while awaiting command completion
5227  *
5228  * Access TP indirect registers through LDST
5229  */
5230 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5231                             unsigned int nregs, unsigned int start_index,
5232                             unsigned int rw, bool sleep_ok)
5233 {
5234         int ret = 0;
5235         unsigned int i;
5236         struct fw_ldst_cmd c;
5237
5238         for (i = 0; i < nregs; i++) {
5239                 memset(&c, 0, sizeof(c));
5240                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5241                                                 FW_CMD_REQUEST_F |
5242                                                 (rw ? FW_CMD_READ_F :
5243                                                       FW_CMD_WRITE_F) |
5244                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5245                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5246
5247                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5248                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5249                 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5250                                       sleep_ok);
5251                 if (ret)
5252                         return ret;
5253
5254                 if (rw)
5255                         vals[i] = be32_to_cpu(c.u.addrval.val);
5256         }
5257         return 0;
5258 }
5259
5260 /**
5261  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5262  * @adap: the adapter
5263  * @reg_addr: Address Register
5264  * @reg_data: Data register
5265  * @buff: where the indirect register values are stored/written
5266  * @nregs: how many indirect registers to read/write
5267  * @start_index: index of first indirect register to read/write
5268  * @rw: READ(1) or WRITE(0)
5269  * @sleep_ok: if true we may sleep while awaiting command completion
5270  *
5271  * Read/Write TP indirect registers through LDST if possible.
5272  * Else, use backdoor access
5273  **/
5274 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5275                               u32 *buff, u32 nregs, u32 start_index, int rw,
5276                               bool sleep_ok)
5277 {
5278         int rc = -EINVAL;
5279         int cmd;
5280
5281         switch (reg_addr) {
5282         case TP_PIO_ADDR_A:
5283                 cmd = FW_LDST_ADDRSPC_TP_PIO;
5284                 break;
5285         case TP_TM_PIO_ADDR_A:
5286                 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5287                 break;
5288         case TP_MIB_INDEX_A:
5289                 cmd = FW_LDST_ADDRSPC_TP_MIB;
5290                 break;
5291         default:
5292                 goto indirect_access;
5293         }
5294
5295         if (t4_use_ldst(adap))
5296                 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5297                                       sleep_ok);
5298
5299 indirect_access:
5300
5301         if (rc) {
5302                 if (rw)
5303                         t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5304                                          start_index);
5305                 else
5306                         t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5307                                           start_index);
5308         }
5309 }
5310
5311 /**
5312  * t4_tp_pio_read - Read TP PIO registers
5313  * @adap: the adapter
5314  * @buff: where the indirect register values are written
5315  * @nregs: how many indirect registers to read
5316  * @start_index: index of first indirect register to read
5317  * @sleep_ok: if true we may sleep while awaiting command completion
5318  *
5319  * Read TP PIO Registers
5320  **/
5321 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5322                     u32 start_index, bool sleep_ok)
5323 {
5324         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5325                           start_index, 1, sleep_ok);
5326 }
5327
5328 /**
5329  * t4_tp_pio_write - Write TP PIO registers
5330  * @adap: the adapter
5331  * @buff: where the indirect register values are stored
5332  * @nregs: how many indirect registers to write
5333  * @start_index: index of first indirect register to write
5334  * @sleep_ok: if true we may sleep while awaiting command completion
5335  *
5336  * Write TP PIO Registers
5337  **/
5338 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5339                             u32 start_index, bool sleep_ok)
5340 {
5341         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5342                           start_index, 0, sleep_ok);
5343 }
5344
5345 /**
5346  * t4_tp_tm_pio_read - Read TP TM PIO registers
5347  * @adap: the adapter
5348  * @buff: where the indirect register values are written
5349  * @nregs: how many indirect registers to read
5350  * @start_index: index of first indirect register to read
5351  * @sleep_ok: if true we may sleep while awaiting command completion
5352  *
5353  * Read TP TM PIO Registers
5354  **/
5355 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5356                        u32 start_index, bool sleep_ok)
5357 {
5358         t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5359                           nregs, start_index, 1, sleep_ok);
5360 }
5361
5362 /**
5363  * t4_tp_mib_read - Read TP MIB registers
5364  * @adap: the adapter
5365  * @buff: where the indirect register values are written
5366  * @nregs: how many indirect registers to read
5367  * @start_index: index of first indirect register to read
5368  * @sleep_ok: if true we may sleep while awaiting command completion
5369  *
5370  * Read TP MIB Registers
5371  **/
5372 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5373                     bool sleep_ok)
5374 {
5375         t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5376                           start_index, 1, sleep_ok);
5377 }
5378
5379 /**
5380  *      t4_read_rss_key - read the global RSS key
5381  *      @adap: the adapter
5382  *      @key: 10-entry array holding the 320-bit RSS key
5383  *      @sleep_ok: if true we may sleep while awaiting command completion
5384  *
5385  *      Reads the global 320-bit RSS key.
5386  */
5387 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5388 {
5389         t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5390 }
5391
5392 /**
5393  *      t4_write_rss_key - program one of the RSS keys
5394  *      @adap: the adapter
5395  *      @key: 10-entry array holding the 320-bit RSS key
5396  *      @idx: which RSS key to write
5397  *      @sleep_ok: if true we may sleep while awaiting command completion
5398  *
5399  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5400  *      0..15 the corresponding entry in the RSS key table is written,
5401  *      otherwise the global RSS key is written.
5402  */
5403 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5404                       bool sleep_ok)
5405 {
5406         u8 rss_key_addr_cnt = 16;
5407         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5408
5409         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5410          * allows access to key addresses 16-63 by using KeyWrAddrX
5411          * as index[5:4](upper 2) into key table
5412          */
5413         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5414             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5415                 rss_key_addr_cnt = 32;
5416
5417         t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5418
5419         if (idx >= 0 && idx < rss_key_addr_cnt) {
5420                 if (rss_key_addr_cnt > 16)
5421                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5422                                      KEYWRADDRX_V(idx >> 4) |
5423                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5424                 else
5425                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5426                                      KEYWRADDR_V(idx) | KEYWREN_F);
5427         }
5428 }
5429
5430 /**
5431  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5432  *      @adapter: the adapter
5433  *      @index: the entry in the PF RSS table to read
5434  *      @valp: where to store the returned value
5435  *      @sleep_ok: if true we may sleep while awaiting command completion
5436  *
5437  *      Reads the PF RSS Configuration Table at the specified index and returns
5438  *      the value found there.
5439  */
5440 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5441                            u32 *valp, bool sleep_ok)
5442 {
5443         t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5444 }
5445
5446 /**
5447  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5448  *      @adapter: the adapter
5449  *      @index: the entry in the VF RSS table to read
5450  *      @vfl: where to store the returned VFL
5451  *      @vfh: where to store the returned VFH
5452  *      @sleep_ok: if true we may sleep while awaiting command completion
5453  *
5454  *      Reads the VF RSS Configuration Table at the specified index and returns
5455  *      the (VFL, VFH) values found there.
5456  */
5457 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5458                            u32 *vfl, u32 *vfh, bool sleep_ok)
5459 {
5460         u32 vrt, mask, data;
5461
5462         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5463                 mask = VFWRADDR_V(VFWRADDR_M);
5464                 data = VFWRADDR_V(index);
5465         } else {
5466                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5467                  data = T6_VFWRADDR_V(index);
5468         }
5469
5470         /* Request that the index'th VF Table values be read into VFL/VFH.
5471          */
5472         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5473         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5474         vrt |= data | VFRDEN_F;
5475         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5476
5477         /* Grab the VFL/VFH values ...
5478          */
5479         t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5480         t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5481 }
5482
5483 /**
5484  *      t4_read_rss_pf_map - read PF RSS Map
5485  *      @adapter: the adapter
5486  *      @sleep_ok: if true we may sleep while awaiting command completion
5487  *
5488  *      Reads the PF RSS Map register and returns its value.
5489  */
5490 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5491 {
5492         u32 pfmap;
5493
5494         t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5495         return pfmap;
5496 }
5497
5498 /**
5499  *      t4_read_rss_pf_mask - read PF RSS Mask
5500  *      @adapter: the adapter
5501  *      @sleep_ok: if true we may sleep while awaiting command completion
5502  *
5503  *      Reads the PF RSS Mask register and returns its value.
5504  */
5505 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5506 {
5507         u32 pfmask;
5508
5509         t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5510         return pfmask;
5511 }
5512
5513 /**
5514  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5515  *      @adap: the adapter
5516  *      @v4: holds the TCP/IP counter values
5517  *      @v6: holds the TCP/IPv6 counter values
5518  *      @sleep_ok: if true we may sleep while awaiting command completion
5519  *
5520  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5521  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5522  */
5523 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5524                          struct tp_tcp_stats *v6, bool sleep_ok)
5525 {
5526         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5527
5528 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5529 #define STAT(x)     val[STAT_IDX(x)]
5530 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5531
5532         if (v4) {
5533                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5534                                TP_MIB_TCP_OUT_RST_A, sleep_ok);
5535                 v4->tcp_out_rsts = STAT(OUT_RST);
5536                 v4->tcp_in_segs  = STAT64(IN_SEG);
5537                 v4->tcp_out_segs = STAT64(OUT_SEG);
5538                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5539         }
5540         if (v6) {
5541                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5542                                TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5543                 v6->tcp_out_rsts = STAT(OUT_RST);
5544                 v6->tcp_in_segs  = STAT64(IN_SEG);
5545                 v6->tcp_out_segs = STAT64(OUT_SEG);
5546                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5547         }
5548 #undef STAT64
5549 #undef STAT
5550 #undef STAT_IDX
5551 }
5552
5553 /**
5554  *      t4_tp_get_err_stats - read TP's error MIB counters
5555  *      @adap: the adapter
5556  *      @st: holds the counter values
5557  *      @sleep_ok: if true we may sleep while awaiting command completion
5558  *
5559  *      Returns the values of TP's error counters.
5560  */
5561 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5562                          bool sleep_ok)
5563 {
5564         int nchan = adap->params.arch.nchan;
5565
5566         t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5567                        sleep_ok);
5568         t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5569                        sleep_ok);
5570         t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5571                        sleep_ok);
5572         t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5573                        TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5574         t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5575                        TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5576         t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5577                        sleep_ok);
5578         t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5579                        TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5580         t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5581                        TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5582         t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5583                        sleep_ok);
5584 }
5585
5586 /**
5587  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5588  *      @adap: the adapter
5589  *      @st: holds the counter values
5590  *      @sleep_ok: if true we may sleep while awaiting command completion
5591  *
5592  *      Returns the values of TP's CPL counters.
5593  */
5594 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5595                          bool sleep_ok)
5596 {
5597         int nchan = adap->params.arch.nchan;
5598
5599         t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5600
5601         t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5602 }
5603
5604 /**
5605  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5606  *      @adap: the adapter
5607  *      @st: holds the counter values
5608  *      @sleep_ok: if true we may sleep while awaiting command completion
5609  *
5610  *      Returns the values of TP's RDMA counters.
5611  */
5612 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5613                           bool sleep_ok)
5614 {
5615         t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5616                        sleep_ok);
5617 }
5618
5619 /**
5620  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5621  *      @adap: the adapter
5622  *      @idx: the port index
5623  *      @st: holds the counter values
5624  *      @sleep_ok: if true we may sleep while awaiting command completion
5625  *
5626  *      Returns the values of TP's FCoE counters for the selected port.
5627  */
5628 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5629                        struct tp_fcoe_stats *st, bool sleep_ok)
5630 {
5631         u32 val[2];
5632
5633         t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5634                        sleep_ok);
5635
5636         t4_tp_mib_read(adap, &st->frames_drop, 1,
5637                        TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5638
5639         t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5640                        sleep_ok);
5641
5642         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5643 }
5644
5645 /**
5646  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5647  *      @adap: the adapter
5648  *      @st: holds the counter values
5649  *      @sleep_ok: if true we may sleep while awaiting command completion
5650  *
5651  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5652  */
5653 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5654                       bool sleep_ok)
5655 {
5656         u32 val[4];
5657
5658         t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5659         st->frames = val[0];
5660         st->drops = val[1];
5661         st->octets = ((u64)val[2] << 32) | val[3];
5662 }
5663
5664 /**
5665  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5666  *      @adap: the adapter
5667  *      @mtus: where to store the MTU values
5668  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5669  *
5670  *      Reads the HW path MTU table.
5671  */
5672 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5673 {
5674         u32 v;
5675         int i;
5676
5677         for (i = 0; i < NMTUS; ++i) {
5678                 t4_write_reg(adap, TP_MTU_TABLE_A,
5679                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5680                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5681                 mtus[i] = MTUVALUE_G(v);
5682                 if (mtu_log)
5683                         mtu_log[i] = MTUWIDTH_G(v);
5684         }
5685 }
5686
5687 /**
5688  *      t4_read_cong_tbl - reads the congestion control table
5689  *      @adap: the adapter
5690  *      @incr: where to store the alpha values
5691  *
5692  *      Reads the additive increments programmed into the HW congestion
5693  *      control table.
5694  */
5695 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5696 {
5697         unsigned int mtu, w;
5698
5699         for (mtu = 0; mtu < NMTUS; ++mtu)
5700                 for (w = 0; w < NCCTRL_WIN; ++w) {
5701                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5702                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5703                         incr[mtu][w] = (u16)t4_read_reg(adap,
5704                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5705                 }
5706 }
5707
5708 /**
5709  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5710  *      @adap: the adapter
5711  *      @addr: the indirect TP register address
5712  *      @mask: specifies the field within the register to modify
5713  *      @val: new value for the field
5714  *
5715  *      Sets a field of an indirect TP register to the given value.
5716  */
5717 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5718                             unsigned int mask, unsigned int val)
5719 {
5720         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5721         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5722         t4_write_reg(adap, TP_PIO_DATA_A, val);
5723 }
5724
5725 /**
5726  *      init_cong_ctrl - initialize congestion control parameters
5727  *      @a: the alpha values for congestion control
5728  *      @b: the beta values for congestion control
5729  *
5730  *      Initialize the congestion control parameters.
5731  */
5732 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5733 {
5734         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5735         a[9] = 2;
5736         a[10] = 3;
5737         a[11] = 4;
5738         a[12] = 5;
5739         a[13] = 6;
5740         a[14] = 7;
5741         a[15] = 8;
5742         a[16] = 9;
5743         a[17] = 10;
5744         a[18] = 14;
5745         a[19] = 17;
5746         a[20] = 21;
5747         a[21] = 25;
5748         a[22] = 30;
5749         a[23] = 35;
5750         a[24] = 45;
5751         a[25] = 60;
5752         a[26] = 80;
5753         a[27] = 100;
5754         a[28] = 200;
5755         a[29] = 300;
5756         a[30] = 400;
5757         a[31] = 500;
5758
5759         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5760         b[9] = b[10] = 1;
5761         b[11] = b[12] = 2;
5762         b[13] = b[14] = b[15] = b[16] = 3;
5763         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5764         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5765         b[28] = b[29] = 6;
5766         b[30] = b[31] = 7;
5767 }
5768
5769 /* The minimum additive increment value for the congestion control table */
5770 #define CC_MIN_INCR 2U
5771
5772 /**
5773  *      t4_load_mtus - write the MTU and congestion control HW tables
5774  *      @adap: the adapter
5775  *      @mtus: the values for the MTU table
5776  *      @alpha: the values for the congestion control alpha parameter
5777  *      @beta: the values for the congestion control beta parameter
5778  *
5779  *      Write the HW MTU table with the supplied MTUs and the high-speed
5780  *      congestion control table with the supplied alpha, beta, and MTUs.
5781  *      We write the two tables together because the additive increments
5782  *      depend on the MTUs.
5783  */
5784 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5785                   const unsigned short *alpha, const unsigned short *beta)
5786 {
5787         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5788                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5789                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5790                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5791         };
5792
5793         unsigned int i, w;
5794
5795         for (i = 0; i < NMTUS; ++i) {
5796                 unsigned int mtu = mtus[i];
5797                 unsigned int log2 = fls(mtu);
5798
5799                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5800                         log2--;
5801                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5802                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5803
5804                 for (w = 0; w < NCCTRL_WIN; ++w) {
5805                         unsigned int inc;
5806
5807                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5808                                   CC_MIN_INCR);
5809
5810                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5811                                      (w << 16) | (beta[w] << 13) | inc);
5812                 }
5813         }
5814 }
5815
5816 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5817  * clocks.  The formula is
5818  *
5819  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5820  *
5821  * which is equivalent to
5822  *
5823  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5824  */
5825 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5826 {
5827         u64 v = bytes256 * adap->params.vpd.cclk;
5828
5829         return v * 62 + v / 2;
5830 }
5831
5832 /**
5833  *      t4_get_chan_txrate - get the current per channel Tx rates
5834  *      @adap: the adapter
5835  *      @nic_rate: rates for NIC traffic
5836  *      @ofld_rate: rates for offloaded traffic
5837  *
5838  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5839  *      for each channel.
5840  */
5841 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5842 {
5843         u32 v;
5844
5845         v = t4_read_reg(adap, TP_TX_TRATE_A);
5846         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5847         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5848         if (adap->params.arch.nchan == NCHAN) {
5849                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5850                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5851         }
5852
5853         v = t4_read_reg(adap, TP_TX_ORATE_A);
5854         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5855         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5856         if (adap->params.arch.nchan == NCHAN) {
5857                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5858                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5859         }
5860 }
5861
5862 /**
5863  *      t4_set_trace_filter - configure one of the tracing filters
5864  *      @adap: the adapter
5865  *      @tp: the desired trace filter parameters
5866  *      @idx: which filter to configure
5867  *      @enable: whether to enable or disable the filter
5868  *
5869  *      Configures one of the tracing filters available in HW.  If @enable is
5870  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5871  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5872  */
5873 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5874                         int idx, int enable)
5875 {
5876         int i, ofst = idx * 4;
5877         u32 data_reg, mask_reg, cfg;
5878         u32 multitrc = TRCMULTIFILTER_F;
5879
5880         if (!enable) {
5881                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5882                 return 0;
5883         }
5884
5885         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5886         if (cfg & TRCMULTIFILTER_F) {
5887                 /* If multiple tracers are enabled, then maximum
5888                  * capture size is 2.5KB (FIFO size of a single channel)
5889                  * minus 2 flits for CPL_TRACE_PKT header.
5890                  */
5891                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5892                         return -EINVAL;
5893         } else {
5894                 /* If multiple tracers are disabled, to avoid deadlocks
5895                  * maximum packet capture size of 9600 bytes is recommended.
5896                  * Also in this mode, only trace0 can be enabled and running.
5897                  */
5898                 multitrc = 0;
5899                 if (tp->snap_len > 9600 || idx)
5900                         return -EINVAL;
5901         }
5902
5903         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5904             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5905             tp->min_len > TFMINPKTSIZE_M)
5906                 return -EINVAL;
5907
5908         /* stop the tracer we'll be changing */
5909         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5910
5911         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5912         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5913         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5914
5915         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5916                 t4_write_reg(adap, data_reg, tp->data[i]);
5917                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5918         }
5919         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5920                      TFCAPTUREMAX_V(tp->snap_len) |
5921                      TFMINPKTSIZE_V(tp->min_len));
5922         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5923                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5924                      (is_t4(adap->params.chip) ?
5925                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5926                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5927                      T5_TFINVERTMATCH_V(tp->invert)));
5928
5929         return 0;
5930 }
5931
5932 /**
5933  *      t4_get_trace_filter - query one of the tracing filters
5934  *      @adap: the adapter
5935  *      @tp: the current trace filter parameters
5936  *      @idx: which trace filter to query
5937  *      @enabled: non-zero if the filter is enabled
5938  *
5939  *      Returns the current settings of one of the HW tracing filters.
5940  */
5941 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5942                          int *enabled)
5943 {
5944         u32 ctla, ctlb;
5945         int i, ofst = idx * 4;
5946         u32 data_reg, mask_reg;
5947
5948         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5949         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5950
5951         if (is_t4(adap->params.chip)) {
5952                 *enabled = !!(ctla & TFEN_F);
5953                 tp->port =  TFPORT_G(ctla);
5954                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5955         } else {
5956                 *enabled = !!(ctla & T5_TFEN_F);
5957                 tp->port = T5_TFPORT_G(ctla);
5958                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5959         }
5960         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5961         tp->min_len = TFMINPKTSIZE_G(ctlb);
5962         tp->skip_ofst = TFOFFSET_G(ctla);
5963         tp->skip_len = TFLENGTH_G(ctla);
5964
5965         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5966         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5967         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5968
5969         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5970                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5971                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5972         }
5973 }
5974
5975 /**
5976  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5977  *      @adap: the adapter
5978  *      @cnt: where to store the count statistics
5979  *      @cycles: where to store the cycle statistics
5980  *
5981  *      Returns performance statistics from PMTX.
5982  */
5983 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5984 {
5985         int i;
5986         u32 data[2];
5987
5988         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5989                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5990                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5991                 if (is_t4(adap->params.chip)) {
5992                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5993                 } else {
5994                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5995                                          PM_TX_DBG_DATA_A, data, 2,
5996                                          PM_TX_DBG_STAT_MSB_A);
5997                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5998                 }
5999         }
6000 }
6001
6002 /**
6003  *      t4_pmrx_get_stats - returns the HW stats from PMRX
6004  *      @adap: the adapter
6005  *      @cnt: where to store the count statistics
6006  *      @cycles: where to store the cycle statistics
6007  *
6008  *      Returns performance statistics from PMRX.
6009  */
6010 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6011 {
6012         int i;
6013         u32 data[2];
6014
6015         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6016                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6017                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6018                 if (is_t4(adap->params.chip)) {
6019                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6020                 } else {
6021                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6022                                          PM_RX_DBG_DATA_A, data, 2,
6023                                          PM_RX_DBG_STAT_MSB_A);
6024                         cycles[i] = (((u64)data[0] << 32) | data[1]);
6025                 }
6026         }
6027 }
6028
6029 /**
6030  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6031  *      @adap: the adapter
6032  *      @pidx: the port index
6033  *
6034  *      Computes and returns a bitmap indicating which MPS buffer groups are
6035  *      associated with the given Port.  Bit i is set if buffer group i is
6036  *      used by the Port.
6037  */
6038 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6039                                               int pidx)
6040 {
6041         unsigned int chip_version, nports;
6042
6043         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6044         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6045
6046         switch (chip_version) {
6047         case CHELSIO_T4:
6048         case CHELSIO_T5:
6049                 switch (nports) {
6050                 case 1: return 0xf;
6051                 case 2: return 3 << (2 * pidx);
6052                 case 4: return 1 << pidx;
6053                 }
6054                 break;
6055
6056         case CHELSIO_T6:
6057                 switch (nports) {
6058                 case 2: return 1 << (2 * pidx);
6059                 }
6060                 break;
6061         }
6062
6063         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6064                 chip_version, nports);
6065
6066         return 0;
6067 }
6068
6069 /**
6070  *      t4_get_mps_bg_map - return the buffer groups associated with a port
6071  *      @adapter: the adapter
6072  *      @pidx: the port index
6073  *
6074  *      Returns a bitmap indicating which MPS buffer groups are associated
6075  *      with the given Port.  Bit i is set if buffer group i is used by the
6076  *      Port.
6077  */
6078 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6079 {
6080         u8 *mps_bg_map;
6081         unsigned int nports;
6082
6083         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6084         if (pidx >= nports) {
6085                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6086                         pidx, nports);
6087                 return 0;
6088         }
6089
6090         /* If we've already retrieved/computed this, just return the result.
6091          */
6092         mps_bg_map = adapter->params.mps_bg_map;
6093         if (mps_bg_map[pidx])
6094                 return mps_bg_map[pidx];
6095
6096         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6097          * If we're talking to such Firmware, let it tell us.  If the new
6098          * API isn't supported, revert back to old hardcoded way.  The value
6099          * obtained from Firmware is encoded in below format:
6100          *
6101          * val = (( MPSBGMAP[Port 3] << 24 ) |
6102          *        ( MPSBGMAP[Port 2] << 16 ) |
6103          *        ( MPSBGMAP[Port 1] <<  8 ) |
6104          *        ( MPSBGMAP[Port 0] <<  0 ))
6105          */
6106         if (adapter->flags & FW_OK) {
6107                 u32 param, val;
6108                 int ret;
6109
6110                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6111                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6112                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6113                                          0, 1, &param, &val);
6114                 if (!ret) {
6115                         int p;
6116
6117                         /* Store the BG Map for all of the Ports in order to
6118                          * avoid more calls to the Firmware in the future.
6119                          */
6120                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6121                                 mps_bg_map[p] = val & 0xff;
6122
6123                         return mps_bg_map[pidx];
6124                 }
6125         }
6126
6127         /* Either we're not talking to the Firmware or we're dealing with
6128          * older Firmware which doesn't support the new API to get the MPS
6129          * Buffer Group Map.  Fall back to computing it ourselves.
6130          */
6131         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6132         return mps_bg_map[pidx];
6133 }
6134
6135 /**
6136  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
6137  *      @adapter: the adapter
6138  *      @pidx: the port index
6139  *
6140  *      Returns a bitmap indicating which TP Ingress Channels are associated
6141  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
6142  *      the Port.
6143  */
6144 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6145 {
6146         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6147         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6148
6149         if (pidx >= nports) {
6150                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6151                          pidx, nports);
6152                 return 0;
6153         }
6154
6155         switch (chip_version) {
6156         case CHELSIO_T4:
6157         case CHELSIO_T5:
6158                 /* Note that this happens to be the same values as the MPS
6159                  * Buffer Group Map for these Chips.  But we replicate the code
6160                  * here because they're really separate concepts.
6161                  */
6162                 switch (nports) {
6163                 case 1: return 0xf;
6164                 case 2: return 3 << (2 * pidx);
6165                 case 4: return 1 << pidx;
6166                 }
6167                 break;
6168
6169         case CHELSIO_T6:
6170                 switch (nports) {
6171                 case 1:
6172                 case 2: return 1 << pidx;
6173                 }
6174                 break;
6175         }
6176
6177         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6178                 chip_version, nports);
6179         return 0;
6180 }
6181
6182 /**
6183  *      t4_get_port_type_description - return Port Type string description
6184  *      @port_type: firmware Port Type enumeration
6185  */
6186 const char *t4_get_port_type_description(enum fw_port_type port_type)
6187 {
6188         static const char *const port_type_description[] = {
6189                 "Fiber_XFI",
6190                 "Fiber_XAUI",
6191                 "BT_SGMII",
6192                 "BT_XFI",
6193                 "BT_XAUI",
6194                 "KX4",
6195                 "CX4",
6196                 "KX",
6197                 "KR",
6198                 "SFP",
6199                 "BP_AP",
6200                 "BP4_AP",
6201                 "QSFP_10G",
6202                 "QSA",
6203                 "QSFP",
6204                 "BP40_BA",
6205                 "KR4_100G",
6206                 "CR4_QSFP",
6207                 "CR_QSFP",
6208                 "CR2_QSFP",
6209                 "SFP28",
6210                 "KR_SFP28",
6211                 "KR_XLAUI"
6212         };
6213
6214         if (port_type < ARRAY_SIZE(port_type_description))
6215                 return port_type_description[port_type];
6216         return "UNKNOWN";
6217 }
6218
6219 /**
6220  *      t4_get_port_stats_offset - collect port stats relative to a previous
6221  *                                 snapshot
6222  *      @adap: The adapter
6223  *      @idx: The port
6224  *      @stats: Current stats to fill
6225  *      @offset: Previous stats snapshot
6226  */
6227 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6228                               struct port_stats *stats,
6229                               struct port_stats *offset)
6230 {
6231         u64 *s, *o;
6232         int i;
6233
6234         t4_get_port_stats(adap, idx, stats);
6235         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6236                         i < (sizeof(struct port_stats) / sizeof(u64));
6237                         i++, s++, o++)
6238                 *s -= *o;
6239 }
6240
6241 /**
6242  *      t4_get_port_stats - collect port statistics
6243  *      @adap: the adapter
6244  *      @idx: the port index
6245  *      @p: the stats structure to fill
6246  *
6247  *      Collect statistics related to the given port from HW.
6248  */
6249 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6250 {
6251         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6252         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6253
6254 #define GET_STAT(name) \
6255         t4_read_reg64(adap, \
6256         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6257         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6258 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6259
6260         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
6261         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
6262         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
6263         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
6264         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
6265         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
6266         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
6267         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
6268         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
6269         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
6270         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
6271         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6272         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
6273         p->tx_drop             = GET_STAT(TX_PORT_DROP);
6274         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
6275         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
6276         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
6277         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
6278         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
6279         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
6280         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6281         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6282         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6283
6284         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6285                 if (stat_ctl & COUNTPAUSESTATTX_F)
6286                         p->tx_frames_64 -= p->tx_pause;
6287                 if (stat_ctl & COUNTPAUSEMCTX_F)
6288                         p->tx_mcast_frames -= p->tx_pause;
6289         }
6290         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6291         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6292         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6293         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6294         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6295         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6296         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6297         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6298         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6299         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6300         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6301         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6302         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6303         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6304         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6305         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6306         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6307         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6308         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6309         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6310         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6311         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6312         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6313         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6314         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6315         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6316         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6317
6318         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6319                 if (stat_ctl & COUNTPAUSESTATRX_F)
6320                         p->rx_frames_64 -= p->rx_pause;
6321                 if (stat_ctl & COUNTPAUSEMCRX_F)
6322                         p->rx_mcast_frames -= p->rx_pause;
6323         }
6324
6325         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6326         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6327         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6328         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6329         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6330         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6331         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6332         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6333
6334 #undef GET_STAT
6335 #undef GET_STAT_COM
6336 }
6337
6338 /**
6339  *      t4_get_lb_stats - collect loopback port statistics
6340  *      @adap: the adapter
6341  *      @idx: the loopback port index
6342  *      @p: the stats structure to fill
6343  *
6344  *      Return HW statistics for the given loopback port.
6345  */
6346 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6347 {
6348         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6349
6350 #define GET_STAT(name) \
6351         t4_read_reg64(adap, \
6352         (is_t4(adap->params.chip) ? \
6353         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6354         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6355 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6356
6357         p->octets           = GET_STAT(BYTES);
6358         p->frames           = GET_STAT(FRAMES);
6359         p->bcast_frames     = GET_STAT(BCAST);
6360         p->mcast_frames     = GET_STAT(MCAST);
6361         p->ucast_frames     = GET_STAT(UCAST);
6362         p->error_frames     = GET_STAT(ERROR);
6363
6364         p->frames_64        = GET_STAT(64B);
6365         p->frames_65_127    = GET_STAT(65B_127B);
6366         p->frames_128_255   = GET_STAT(128B_255B);
6367         p->frames_256_511   = GET_STAT(256B_511B);
6368         p->frames_512_1023  = GET_STAT(512B_1023B);
6369         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6370         p->frames_1519_max  = GET_STAT(1519B_MAX);
6371         p->drop             = GET_STAT(DROP_FRAMES);
6372
6373         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6374         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6375         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6376         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6377         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6378         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6379         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6380         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6381
6382 #undef GET_STAT
6383 #undef GET_STAT_COM
6384 }
6385
6386 /*     t4_mk_filtdelwr - create a delete filter WR
6387  *     @ftid: the filter ID
6388  *     @wr: the filter work request to populate
6389  *     @qid: ingress queue to receive the delete notification
6390  *
6391  *     Creates a filter work request to delete the supplied filter.  If @qid is
6392  *     negative the delete notification is suppressed.
6393  */
6394 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6395 {
6396         memset(wr, 0, sizeof(*wr));
6397         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6398         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6399         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6400                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6401         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6402         if (qid >= 0)
6403                 wr->rx_chan_rx_rpl_iq =
6404                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6405 }
6406
6407 #define INIT_CMD(var, cmd, rd_wr) do { \
6408         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6409                                         FW_CMD_REQUEST_F | \
6410                                         FW_CMD_##rd_wr##_F); \
6411         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6412 } while (0)
6413
6414 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6415                           u32 addr, u32 val)
6416 {
6417         u32 ldst_addrspace;
6418         struct fw_ldst_cmd c;
6419
6420         memset(&c, 0, sizeof(c));
6421         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6422         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6423                                         FW_CMD_REQUEST_F |
6424                                         FW_CMD_WRITE_F |
6425                                         ldst_addrspace);
6426         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6427         c.u.addrval.addr = cpu_to_be32(addr);
6428         c.u.addrval.val = cpu_to_be32(val);
6429
6430         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6431 }
6432
6433 /**
6434  *      t4_mdio_rd - read a PHY register through MDIO
6435  *      @adap: the adapter
6436  *      @mbox: mailbox to use for the FW command
6437  *      @phy_addr: the PHY address
6438  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6439  *      @reg: the register to read
6440  *      @valp: where to store the value
6441  *
6442  *      Issues a FW command through the given mailbox to read a PHY register.
6443  */
6444 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6445                unsigned int mmd, unsigned int reg, u16 *valp)
6446 {
6447         int ret;
6448         u32 ldst_addrspace;
6449         struct fw_ldst_cmd c;
6450
6451         memset(&c, 0, sizeof(c));
6452         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6453         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6454                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6455                                         ldst_addrspace);
6456         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6457         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6458                                          FW_LDST_CMD_MMD_V(mmd));
6459         c.u.mdio.raddr = cpu_to_be16(reg);
6460
6461         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6462         if (ret == 0)
6463                 *valp = be16_to_cpu(c.u.mdio.rval);
6464         return ret;
6465 }
6466
6467 /**
6468  *      t4_mdio_wr - write a PHY register through MDIO
6469  *      @adap: the adapter
6470  *      @mbox: mailbox to use for the FW command
6471  *      @phy_addr: the PHY address
6472  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6473  *      @reg: the register to write
6474  *      @valp: value to write
6475  *
6476  *      Issues a FW command through the given mailbox to write a PHY register.
6477  */
6478 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6479                unsigned int mmd, unsigned int reg, u16 val)
6480 {
6481         u32 ldst_addrspace;
6482         struct fw_ldst_cmd c;
6483
6484         memset(&c, 0, sizeof(c));
6485         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6486         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6487                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6488                                         ldst_addrspace);
6489         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6490         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6491                                          FW_LDST_CMD_MMD_V(mmd));
6492         c.u.mdio.raddr = cpu_to_be16(reg);
6493         c.u.mdio.rval = cpu_to_be16(val);
6494
6495         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6496 }
6497
6498 /**
6499  *      t4_sge_decode_idma_state - decode the idma state
6500  *      @adap: the adapter
6501  *      @state: the state idma is stuck in
6502  */
6503 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6504 {
6505         static const char * const t4_decode[] = {
6506                 "IDMA_IDLE",
6507                 "IDMA_PUSH_MORE_CPL_FIFO",
6508                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6509                 "Not used",
6510                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6511                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6512                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6513                 "IDMA_SEND_FIFO_TO_IMSG",
6514                 "IDMA_FL_REQ_DATA_FL_PREP",
6515                 "IDMA_FL_REQ_DATA_FL",
6516                 "IDMA_FL_DROP",
6517                 "IDMA_FL_H_REQ_HEADER_FL",
6518                 "IDMA_FL_H_SEND_PCIEHDR",
6519                 "IDMA_FL_H_PUSH_CPL_FIFO",
6520                 "IDMA_FL_H_SEND_CPL",
6521                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6522                 "IDMA_FL_H_SEND_IP_HDR",
6523                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6524                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6525                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6526                 "IDMA_FL_D_SEND_PCIEHDR",
6527                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6528                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6529                 "IDMA_FL_SEND_PCIEHDR",
6530                 "IDMA_FL_PUSH_CPL_FIFO",
6531                 "IDMA_FL_SEND_CPL",
6532                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6533                 "IDMA_FL_SEND_PAYLOAD",
6534                 "IDMA_FL_REQ_NEXT_DATA_FL",
6535                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6536                 "IDMA_FL_SEND_PADDING",
6537                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6538                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6539                 "IDMA_FL_REQ_DATAFL_DONE",
6540                 "IDMA_FL_REQ_HEADERFL_DONE",
6541         };
6542         static const char * const t5_decode[] = {
6543                 "IDMA_IDLE",
6544                 "IDMA_ALMOST_IDLE",
6545                 "IDMA_PUSH_MORE_CPL_FIFO",
6546                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6547                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6548                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6549                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6550                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6551                 "IDMA_SEND_FIFO_TO_IMSG",
6552                 "IDMA_FL_REQ_DATA_FL",
6553                 "IDMA_FL_DROP",
6554                 "IDMA_FL_DROP_SEND_INC",
6555                 "IDMA_FL_H_REQ_HEADER_FL",
6556                 "IDMA_FL_H_SEND_PCIEHDR",
6557                 "IDMA_FL_H_PUSH_CPL_FIFO",
6558                 "IDMA_FL_H_SEND_CPL",
6559                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6560                 "IDMA_FL_H_SEND_IP_HDR",
6561                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6562                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6563                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6564                 "IDMA_FL_D_SEND_PCIEHDR",
6565                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6566                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6567                 "IDMA_FL_SEND_PCIEHDR",
6568                 "IDMA_FL_PUSH_CPL_FIFO",
6569                 "IDMA_FL_SEND_CPL",
6570                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6571                 "IDMA_FL_SEND_PAYLOAD",
6572                 "IDMA_FL_REQ_NEXT_DATA_FL",
6573                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6574                 "IDMA_FL_SEND_PADDING",
6575                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6576         };
6577         static const char * const t6_decode[] = {
6578                 "IDMA_IDLE",
6579                 "IDMA_PUSH_MORE_CPL_FIFO",
6580                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6581                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6582                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6583                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6584                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6585                 "IDMA_FL_REQ_DATA_FL",
6586                 "IDMA_FL_DROP",
6587                 "IDMA_FL_DROP_SEND_INC",
6588                 "IDMA_FL_H_REQ_HEADER_FL",
6589                 "IDMA_FL_H_SEND_PCIEHDR",
6590                 "IDMA_FL_H_PUSH_CPL_FIFO",
6591                 "IDMA_FL_H_SEND_CPL",
6592                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6593                 "IDMA_FL_H_SEND_IP_HDR",
6594                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6595                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6596                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6597                 "IDMA_FL_D_SEND_PCIEHDR",
6598                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6599                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6600                 "IDMA_FL_SEND_PCIEHDR",
6601                 "IDMA_FL_PUSH_CPL_FIFO",
6602                 "IDMA_FL_SEND_CPL",
6603                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6604                 "IDMA_FL_SEND_PAYLOAD",
6605                 "IDMA_FL_REQ_NEXT_DATA_FL",
6606                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6607                 "IDMA_FL_SEND_PADDING",
6608                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6609         };
6610         static const u32 sge_regs[] = {
6611                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6612                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6613                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6614         };
6615         const char **sge_idma_decode;
6616         int sge_idma_decode_nstates;
6617         int i;
6618         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6619
6620         /* Select the right set of decode strings to dump depending on the
6621          * adapter chip type.
6622          */
6623         switch (chip_version) {
6624         case CHELSIO_T4:
6625                 sge_idma_decode = (const char **)t4_decode;
6626                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6627                 break;
6628
6629         case CHELSIO_T5:
6630                 sge_idma_decode = (const char **)t5_decode;
6631                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6632                 break;
6633
6634         case CHELSIO_T6:
6635                 sge_idma_decode = (const char **)t6_decode;
6636                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6637                 break;
6638
6639         default:
6640                 dev_err(adapter->pdev_dev,
6641                         "Unsupported chip version %d\n", chip_version);
6642                 return;
6643         }
6644
6645         if (is_t4(adapter->params.chip)) {
6646                 sge_idma_decode = (const char **)t4_decode;
6647                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6648         } else {
6649                 sge_idma_decode = (const char **)t5_decode;
6650                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6651         }
6652
6653         if (state < sge_idma_decode_nstates)
6654                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6655         else
6656                 CH_WARN(adapter, "idma state %d unknown\n", state);
6657
6658         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6659                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6660                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6661 }
6662
6663 /**
6664  *      t4_sge_ctxt_flush - flush the SGE context cache
6665  *      @adap: the adapter
6666  *      @mbox: mailbox to use for the FW command
6667  *      @ctx_type: Egress or Ingress
6668  *
6669  *      Issues a FW command through the given mailbox to flush the
6670  *      SGE context cache.
6671  */
6672 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6673 {
6674         int ret;
6675         u32 ldst_addrspace;
6676         struct fw_ldst_cmd c;
6677
6678         memset(&c, 0, sizeof(c));
6679         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6680                                                  FW_LDST_ADDRSPC_SGE_EGRC :
6681                                                  FW_LDST_ADDRSPC_SGE_INGC);
6682         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6683                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6684                                         ldst_addrspace);
6685         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6686         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6687
6688         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6689         return ret;
6690 }
6691
6692 /**
6693  *      t4_fw_hello - establish communication with FW
6694  *      @adap: the adapter
6695  *      @mbox: mailbox to use for the FW command
6696  *      @evt_mbox: mailbox to receive async FW events
6697  *      @master: specifies the caller's willingness to be the device master
6698  *      @state: returns the current device state (if non-NULL)
6699  *
6700  *      Issues a command to establish communication with FW.  Returns either
6701  *      an error (negative integer) or the mailbox of the Master PF.
6702  */
6703 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6704                 enum dev_master master, enum dev_state *state)
6705 {
6706         int ret;
6707         struct fw_hello_cmd c;
6708         u32 v;
6709         unsigned int master_mbox;
6710         int retries = FW_CMD_HELLO_RETRIES;
6711
6712 retry:
6713         memset(&c, 0, sizeof(c));
6714         INIT_CMD(c, HELLO, WRITE);
6715         c.err_to_clearinit = cpu_to_be32(
6716                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6717                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6718                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6719                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6720                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6721                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6722                 FW_HELLO_CMD_CLEARINIT_F);
6723
6724         /*
6725          * Issue the HELLO command to the firmware.  If it's not successful
6726          * but indicates that we got a "busy" or "timeout" condition, retry
6727          * the HELLO until we exhaust our retry limit.  If we do exceed our
6728          * retry limit, check to see if the firmware left us any error
6729          * information and report that if so.
6730          */
6731         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6732         if (ret < 0) {
6733                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6734                         goto retry;
6735                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6736                         t4_report_fw_error(adap);
6737                 return ret;
6738         }
6739
6740         v = be32_to_cpu(c.err_to_clearinit);
6741         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6742         if (state) {
6743                 if (v & FW_HELLO_CMD_ERR_F)
6744                         *state = DEV_STATE_ERR;
6745                 else if (v & FW_HELLO_CMD_INIT_F)
6746                         *state = DEV_STATE_INIT;
6747                 else
6748                         *state = DEV_STATE_UNINIT;
6749         }
6750
6751         /*
6752          * If we're not the Master PF then we need to wait around for the
6753          * Master PF Driver to finish setting up the adapter.
6754          *
6755          * Note that we also do this wait if we're a non-Master-capable PF and
6756          * there is no current Master PF; a Master PF may show up momentarily
6757          * and we wouldn't want to fail pointlessly.  (This can happen when an
6758          * OS loads lots of different drivers rapidly at the same time).  In
6759          * this case, the Master PF returned by the firmware will be
6760          * PCIE_FW_MASTER_M so the test below will work ...
6761          */
6762         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6763             master_mbox != mbox) {
6764                 int waiting = FW_CMD_HELLO_TIMEOUT;
6765
6766                 /*
6767                  * Wait for the firmware to either indicate an error or
6768                  * initialized state.  If we see either of these we bail out
6769                  * and report the issue to the caller.  If we exhaust the
6770                  * "hello timeout" and we haven't exhausted our retries, try
6771                  * again.  Otherwise bail with a timeout error.
6772                  */
6773                 for (;;) {
6774                         u32 pcie_fw;
6775
6776                         msleep(50);
6777                         waiting -= 50;
6778
6779                         /*
6780                          * If neither Error nor Initialialized are indicated
6781                          * by the firmware keep waiting till we exaust our
6782                          * timeout ... and then retry if we haven't exhausted
6783                          * our retries ...
6784                          */
6785                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6786                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6787                                 if (waiting <= 0) {
6788                                         if (retries-- > 0)
6789                                                 goto retry;
6790
6791                                         return -ETIMEDOUT;
6792                                 }
6793                                 continue;
6794                         }
6795
6796                         /*
6797                          * We either have an Error or Initialized condition
6798                          * report errors preferentially.
6799                          */
6800                         if (state) {
6801                                 if (pcie_fw & PCIE_FW_ERR_F)
6802                                         *state = DEV_STATE_ERR;
6803                                 else if (pcie_fw & PCIE_FW_INIT_F)
6804                                         *state = DEV_STATE_INIT;
6805                         }
6806
6807                         /*
6808                          * If we arrived before a Master PF was selected and
6809                          * there's not a valid Master PF, grab its identity
6810                          * for our caller.
6811                          */
6812                         if (master_mbox == PCIE_FW_MASTER_M &&
6813                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6814                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6815                         break;
6816                 }
6817         }
6818
6819         return master_mbox;
6820 }
6821
6822 /**
6823  *      t4_fw_bye - end communication with FW
6824  *      @adap: the adapter
6825  *      @mbox: mailbox to use for the FW command
6826  *
6827  *      Issues a command to terminate communication with FW.
6828  */
6829 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6830 {
6831         struct fw_bye_cmd c;
6832
6833         memset(&c, 0, sizeof(c));
6834         INIT_CMD(c, BYE, WRITE);
6835         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6836 }
6837
6838 /**
6839  *      t4_init_cmd - ask FW to initialize the device
6840  *      @adap: the adapter
6841  *      @mbox: mailbox to use for the FW command
6842  *
6843  *      Issues a command to FW to partially initialize the device.  This
6844  *      performs initialization that generally doesn't depend on user input.
6845  */
6846 int t4_early_init(struct adapter *adap, unsigned int mbox)
6847 {
6848         struct fw_initialize_cmd c;
6849
6850         memset(&c, 0, sizeof(c));
6851         INIT_CMD(c, INITIALIZE, WRITE);
6852         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6853 }
6854
6855 /**
6856  *      t4_fw_reset - issue a reset to FW
6857  *      @adap: the adapter
6858  *      @mbox: mailbox to use for the FW command
6859  *      @reset: specifies the type of reset to perform
6860  *
6861  *      Issues a reset command of the specified type to FW.
6862  */
6863 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6864 {
6865         struct fw_reset_cmd c;
6866
6867         memset(&c, 0, sizeof(c));
6868         INIT_CMD(c, RESET, WRITE);
6869         c.val = cpu_to_be32(reset);
6870         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6871 }
6872
6873 /**
6874  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6875  *      @adap: the adapter
6876  *      @mbox: mailbox to use for the FW RESET command (if desired)
6877  *      @force: force uP into RESET even if FW RESET command fails
6878  *
6879  *      Issues a RESET command to firmware (if desired) with a HALT indication
6880  *      and then puts the microprocessor into RESET state.  The RESET command
6881  *      will only be issued if a legitimate mailbox is provided (mbox <=
6882  *      PCIE_FW_MASTER_M).
6883  *
6884  *      This is generally used in order for the host to safely manipulate the
6885  *      adapter without fear of conflicting with whatever the firmware might
6886  *      be doing.  The only way out of this state is to RESTART the firmware
6887  *      ...
6888  */
6889 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6890 {
6891         int ret = 0;
6892
6893         /*
6894          * If a legitimate mailbox is provided, issue a RESET command
6895          * with a HALT indication.
6896          */
6897         if (mbox <= PCIE_FW_MASTER_M) {
6898                 struct fw_reset_cmd c;
6899
6900                 memset(&c, 0, sizeof(c));
6901                 INIT_CMD(c, RESET, WRITE);
6902                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6903                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6904                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6905         }
6906
6907         /*
6908          * Normally we won't complete the operation if the firmware RESET
6909          * command fails but if our caller insists we'll go ahead and put the
6910          * uP into RESET.  This can be useful if the firmware is hung or even
6911          * missing ...  We'll have to take the risk of putting the uP into
6912          * RESET without the cooperation of firmware in that case.
6913          *
6914          * We also force the firmware's HALT flag to be on in case we bypassed
6915          * the firmware RESET command above or we're dealing with old firmware
6916          * which doesn't have the HALT capability.  This will serve as a flag
6917          * for the incoming firmware to know that it's coming out of a HALT
6918          * rather than a RESET ... if it's new enough to understand that ...
6919          */
6920         if (ret == 0 || force) {
6921                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6922                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6923                                  PCIE_FW_HALT_F);
6924         }
6925
6926         /*
6927          * And we always return the result of the firmware RESET command
6928          * even when we force the uP into RESET ...
6929          */
6930         return ret;
6931 }
6932
6933 /**
6934  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6935  *      @adap: the adapter
6936  *      @reset: if we want to do a RESET to restart things
6937  *
6938  *      Restart firmware previously halted by t4_fw_halt().  On successful
6939  *      return the previous PF Master remains as the new PF Master and there
6940  *      is no need to issue a new HELLO command, etc.
6941  *
6942  *      We do this in two ways:
6943  *
6944  *       1. If we're dealing with newer firmware we'll simply want to take
6945  *          the chip's microprocessor out of RESET.  This will cause the
6946  *          firmware to start up from its start vector.  And then we'll loop
6947  *          until the firmware indicates it's started again (PCIE_FW.HALT
6948  *          reset to 0) or we timeout.
6949  *
6950  *       2. If we're dealing with older firmware then we'll need to RESET
6951  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6952  *          flag and automatically RESET itself on startup.
6953  */
6954 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6955 {
6956         if (reset) {
6957                 /*
6958                  * Since we're directing the RESET instead of the firmware
6959                  * doing it automatically, we need to clear the PCIE_FW.HALT
6960                  * bit.
6961                  */
6962                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6963
6964                 /*
6965                  * If we've been given a valid mailbox, first try to get the
6966                  * firmware to do the RESET.  If that works, great and we can
6967                  * return success.  Otherwise, if we haven't been given a
6968                  * valid mailbox or the RESET command failed, fall back to
6969                  * hitting the chip with a hammer.
6970                  */
6971                 if (mbox <= PCIE_FW_MASTER_M) {
6972                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6973                         msleep(100);
6974                         if (t4_fw_reset(adap, mbox,
6975                                         PIORST_F | PIORSTMODE_F) == 0)
6976                                 return 0;
6977                 }
6978
6979                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6980                 msleep(2000);
6981         } else {
6982                 int ms;
6983
6984                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6985                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6986                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6987                                 return 0;
6988                         msleep(100);
6989                         ms += 100;
6990                 }
6991                 return -ETIMEDOUT;
6992         }
6993         return 0;
6994 }
6995
6996 /**
6997  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6998  *      @adap: the adapter
6999  *      @mbox: mailbox to use for the FW RESET command (if desired)
7000  *      @fw_data: the firmware image to write
7001  *      @size: image size
7002  *      @force: force upgrade even if firmware doesn't cooperate
7003  *
7004  *      Perform all of the steps necessary for upgrading an adapter's
7005  *      firmware image.  Normally this requires the cooperation of the
7006  *      existing firmware in order to halt all existing activities
7007  *      but if an invalid mailbox token is passed in we skip that step
7008  *      (though we'll still put the adapter microprocessor into RESET in
7009  *      that case).
7010  *
7011  *      On successful return the new firmware will have been loaded and
7012  *      the adapter will have been fully RESET losing all previous setup
7013  *      state.  On unsuccessful return the adapter may be completely hosed ...
7014  *      positive errno indicates that the adapter is ~probably~ intact, a
7015  *      negative errno indicates that things are looking bad ...
7016  */
7017 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7018                   const u8 *fw_data, unsigned int size, int force)
7019 {
7020         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7021         int reset, ret;
7022
7023         if (!t4_fw_matches_chip(adap, fw_hdr))
7024                 return -EINVAL;
7025
7026         /* Disable FW_OK flag so that mbox commands with FW_OK flag set
7027          * wont be sent when we are flashing FW.
7028          */
7029         adap->flags &= ~FW_OK;
7030
7031         ret = t4_fw_halt(adap, mbox, force);
7032         if (ret < 0 && !force)
7033                 goto out;
7034
7035         ret = t4_load_fw(adap, fw_data, size);
7036         if (ret < 0)
7037                 goto out;
7038
7039         /*
7040          * If there was a Firmware Configuration File stored in FLASH,
7041          * there's a good chance that it won't be compatible with the new
7042          * Firmware.  In order to prevent difficult to diagnose adapter
7043          * initialization issues, we clear out the Firmware Configuration File
7044          * portion of the FLASH .  The user will need to re-FLASH a new
7045          * Firmware Configuration File which is compatible with the new
7046          * Firmware if that's desired.
7047          */
7048         (void)t4_load_cfg(adap, NULL, 0);
7049
7050         /*
7051          * Older versions of the firmware don't understand the new
7052          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7053          * restart.  So for newly loaded older firmware we'll have to do the
7054          * RESET for it so it starts up on a clean slate.  We can tell if
7055          * the newly loaded firmware will handle this right by checking
7056          * its header flags to see if it advertises the capability.
7057          */
7058         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7059         ret = t4_fw_restart(adap, mbox, reset);
7060
7061         /* Grab potentially new Firmware Device Log parameters so we can see
7062          * how healthy the new Firmware is.  It's okay to contact the new
7063          * Firmware for these parameters even though, as far as it's
7064          * concerned, we've never said "HELLO" to it ...
7065          */
7066         (void)t4_init_devlog_params(adap);
7067 out:
7068         adap->flags |= FW_OK;
7069         return ret;
7070 }
7071
7072 /**
7073  *      t4_fl_pkt_align - return the fl packet alignment
7074  *      @adap: the adapter
7075  *
7076  *      T4 has a single field to specify the packing and padding boundary.
7077  *      T5 onwards has separate fields for this and hence the alignment for
7078  *      next packet offset is maximum of these two.
7079  *
7080  */
7081 int t4_fl_pkt_align(struct adapter *adap)
7082 {
7083         u32 sge_control, sge_control2;
7084         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7085
7086         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7087
7088         /* T4 uses a single control field to specify both the PCIe Padding and
7089          * Packing Boundary.  T5 introduced the ability to specify these
7090          * separately.  The actual Ingress Packet Data alignment boundary
7091          * within Packed Buffer Mode is the maximum of these two
7092          * specifications.  (Note that it makes no real practical sense to
7093          * have the Pading Boudary be larger than the Packing Boundary but you
7094          * could set the chip up that way and, in fact, legacy T4 code would
7095          * end doing this because it would initialize the Padding Boundary and
7096          * leave the Packing Boundary initialized to 0 (16 bytes).)
7097          * Padding Boundary values in T6 starts from 8B,
7098          * where as it is 32B for T4 and T5.
7099          */
7100         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7101                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7102         else
7103                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7104
7105         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7106
7107         fl_align = ingpadboundary;
7108         if (!is_t4(adap->params.chip)) {
7109                 /* T5 has a weird interpretation of one of the PCIe Packing
7110                  * Boundary values.  No idea why ...
7111                  */
7112                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7113                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7114                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7115                         ingpackboundary = 16;
7116                 else
7117                         ingpackboundary = 1 << (ingpackboundary +
7118                                                 INGPACKBOUNDARY_SHIFT_X);
7119
7120                 fl_align = max(ingpadboundary, ingpackboundary);
7121         }
7122         return fl_align;
7123 }
7124
7125 /**
7126  *      t4_fixup_host_params - fix up host-dependent parameters
7127  *      @adap: the adapter
7128  *      @page_size: the host's Base Page Size
7129  *      @cache_line_size: the host's Cache Line Size
7130  *
7131  *      Various registers in T4 contain values which are dependent on the
7132  *      host's Base Page and Cache Line Sizes.  This function will fix all of
7133  *      those registers with the appropriate values as passed in ...
7134  */
7135 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7136                          unsigned int cache_line_size)
7137 {
7138         unsigned int page_shift = fls(page_size) - 1;
7139         unsigned int sge_hps = page_shift - 10;
7140         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7141         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7142         unsigned int fl_align_log = fls(fl_align) - 1;
7143
7144         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7145                      HOSTPAGESIZEPF0_V(sge_hps) |
7146                      HOSTPAGESIZEPF1_V(sge_hps) |
7147                      HOSTPAGESIZEPF2_V(sge_hps) |
7148                      HOSTPAGESIZEPF3_V(sge_hps) |
7149                      HOSTPAGESIZEPF4_V(sge_hps) |
7150                      HOSTPAGESIZEPF5_V(sge_hps) |
7151                      HOSTPAGESIZEPF6_V(sge_hps) |
7152                      HOSTPAGESIZEPF7_V(sge_hps));
7153
7154         if (is_t4(adap->params.chip)) {
7155                 t4_set_reg_field(adap, SGE_CONTROL_A,
7156                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7157                                  EGRSTATUSPAGESIZE_F,
7158                                  INGPADBOUNDARY_V(fl_align_log -
7159                                                   INGPADBOUNDARY_SHIFT_X) |
7160                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7161         } else {
7162                 unsigned int pack_align;
7163                 unsigned int ingpad, ingpack;
7164                 unsigned int pcie_cap;
7165
7166                 /* T5 introduced the separation of the Free List Padding and
7167                  * Packing Boundaries.  Thus, we can select a smaller Padding
7168                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
7169                  * Bandwidth, and use a Packing Boundary which is large enough
7170                  * to avoid false sharing between CPUs, etc.
7171                  *
7172                  * For the PCI Link, the smaller the Padding Boundary the
7173                  * better.  For the Memory Controller, a smaller Padding
7174                  * Boundary is better until we cross under the Memory Line
7175                  * Size (the minimum unit of transfer to/from Memory).  If we
7176                  * have a Padding Boundary which is smaller than the Memory
7177                  * Line Size, that'll involve a Read-Modify-Write cycle on the
7178                  * Memory Controller which is never good.
7179                  */
7180
7181                 /* We want the Packing Boundary to be based on the Cache Line
7182                  * Size in order to help avoid False Sharing performance
7183                  * issues between CPUs, etc.  We also want the Packing
7184                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
7185                  * get best performance when the Packing Boundary is a
7186                  * multiple of the Maximum Payload Size.
7187                  */
7188                 pack_align = fl_align;
7189                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
7190                 if (pcie_cap) {
7191                         unsigned int mps, mps_log;
7192                         u16 devctl;
7193
7194                         /* The PCIe Device Control Maximum Payload Size field
7195                          * [bits 7:5] encodes sizes as powers of 2 starting at
7196                          * 128 bytes.
7197                          */
7198                         pci_read_config_word(adap->pdev,
7199                                              pcie_cap + PCI_EXP_DEVCTL,
7200                                              &devctl);
7201                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7202                         mps = 1 << mps_log;
7203                         if (mps > pack_align)
7204                                 pack_align = mps;
7205                 }
7206
7207                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7208                  * value for the Packing Boundary.  This corresponds to 16
7209                  * bytes instead of the expected 32 bytes.  So if we want 32
7210                  * bytes, the best we can really do is 64 bytes ...
7211                  */
7212                 if (pack_align <= 16) {
7213                         ingpack = INGPACKBOUNDARY_16B_X;
7214                         fl_align = 16;
7215                 } else if (pack_align == 32) {
7216                         ingpack = INGPACKBOUNDARY_64B_X;
7217                         fl_align = 64;
7218                 } else {
7219                         unsigned int pack_align_log = fls(pack_align) - 1;
7220
7221                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7222                         fl_align = pack_align;
7223                 }
7224
7225                 /* Use the smallest Ingress Padding which isn't smaller than
7226                  * the Memory Controller Read/Write Size.  We'll take that as
7227                  * being 8 bytes since we don't know of any system with a
7228                  * wider Memory Controller Bus Width.
7229                  */
7230                 if (is_t5(adap->params.chip))
7231                         ingpad = INGPADBOUNDARY_32B_X;
7232                 else
7233                         ingpad = T6_INGPADBOUNDARY_8B_X;
7234
7235                 t4_set_reg_field(adap, SGE_CONTROL_A,
7236                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7237                                  EGRSTATUSPAGESIZE_F,
7238                                  INGPADBOUNDARY_V(ingpad) |
7239                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7240                 t4_set_reg_field(adap, SGE_CONTROL2_A,
7241                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7242                                  INGPACKBOUNDARY_V(ingpack));
7243         }
7244         /*
7245          * Adjust various SGE Free List Host Buffer Sizes.
7246          *
7247          * This is something of a crock since we're using fixed indices into
7248          * the array which are also known by the sge.c code and the T4
7249          * Firmware Configuration File.  We need to come up with a much better
7250          * approach to managing this array.  For now, the first four entries
7251          * are:
7252          *
7253          *   0: Host Page Size
7254          *   1: 64KB
7255          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7256          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7257          *
7258          * For the single-MTU buffers in unpacked mode we need to include
7259          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7260          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7261          * Padding boundary.  All of these are accommodated in the Factory
7262          * Default Firmware Configuration File but we need to adjust it for
7263          * this host's cache line size.
7264          */
7265         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7266         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7267                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7268                      & ~(fl_align-1));
7269         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7270                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7271                      & ~(fl_align-1));
7272
7273         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7274
7275         return 0;
7276 }
7277
7278 /**
7279  *      t4_fw_initialize - ask FW to initialize the device
7280  *      @adap: the adapter
7281  *      @mbox: mailbox to use for the FW command
7282  *
7283  *      Issues a command to FW to partially initialize the device.  This
7284  *      performs initialization that generally doesn't depend on user input.
7285  */
7286 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7287 {
7288         struct fw_initialize_cmd c;
7289
7290         memset(&c, 0, sizeof(c));
7291         INIT_CMD(c, INITIALIZE, WRITE);
7292         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7293 }
7294
7295 /**
7296  *      t4_query_params_rw - query FW or device parameters
7297  *      @adap: the adapter
7298  *      @mbox: mailbox to use for the FW command
7299  *      @pf: the PF
7300  *      @vf: the VF
7301  *      @nparams: the number of parameters
7302  *      @params: the parameter names
7303  *      @val: the parameter values
7304  *      @rw: Write and read flag
7305  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7306  *
7307  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7308  *      queried at once.
7309  */
7310 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7311                        unsigned int vf, unsigned int nparams, const u32 *params,
7312                        u32 *val, int rw, bool sleep_ok)
7313 {
7314         int i, ret;
7315         struct fw_params_cmd c;
7316         __be32 *p = &c.param[0].mnem;
7317
7318         if (nparams > 7)
7319                 return -EINVAL;
7320
7321         memset(&c, 0, sizeof(c));
7322         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7323                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7324                                   FW_PARAMS_CMD_PFN_V(pf) |
7325                                   FW_PARAMS_CMD_VFN_V(vf));
7326         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7327
7328         for (i = 0; i < nparams; i++) {
7329                 *p++ = cpu_to_be32(*params++);
7330                 if (rw)
7331                         *p = cpu_to_be32(*(val + i));
7332                 p++;
7333         }
7334
7335         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7336         if (ret == 0)
7337                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7338                         *val++ = be32_to_cpu(*p);
7339         return ret;
7340 }
7341
7342 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7343                     unsigned int vf, unsigned int nparams, const u32 *params,
7344                     u32 *val)
7345 {
7346         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7347                                   true);
7348 }
7349
7350 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7351                        unsigned int vf, unsigned int nparams, const u32 *params,
7352                        u32 *val)
7353 {
7354         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7355                                   false);
7356 }
7357
7358 /**
7359  *      t4_set_params_timeout - sets FW or device parameters
7360  *      @adap: the adapter
7361  *      @mbox: mailbox to use for the FW command
7362  *      @pf: the PF
7363  *      @vf: the VF
7364  *      @nparams: the number of parameters
7365  *      @params: the parameter names
7366  *      @val: the parameter values
7367  *      @timeout: the timeout time
7368  *
7369  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7370  *      specified at once.
7371  */
7372 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7373                           unsigned int pf, unsigned int vf,
7374                           unsigned int nparams, const u32 *params,
7375                           const u32 *val, int timeout)
7376 {
7377         struct fw_params_cmd c;
7378         __be32 *p = &c.param[0].mnem;
7379
7380         if (nparams > 7)
7381                 return -EINVAL;
7382
7383         memset(&c, 0, sizeof(c));
7384         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7385                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7386                                   FW_PARAMS_CMD_PFN_V(pf) |
7387                                   FW_PARAMS_CMD_VFN_V(vf));
7388         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7389
7390         while (nparams--) {
7391                 *p++ = cpu_to_be32(*params++);
7392                 *p++ = cpu_to_be32(*val++);
7393         }
7394
7395         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7396 }
7397
7398 /**
7399  *      t4_set_params - sets FW or device parameters
7400  *      @adap: the adapter
7401  *      @mbox: mailbox to use for the FW command
7402  *      @pf: the PF
7403  *      @vf: the VF
7404  *      @nparams: the number of parameters
7405  *      @params: the parameter names
7406  *      @val: the parameter values
7407  *
7408  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7409  *      specified at once.
7410  */
7411 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7412                   unsigned int vf, unsigned int nparams, const u32 *params,
7413                   const u32 *val)
7414 {
7415         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7416                                      FW_CMD_MAX_TIMEOUT);
7417 }
7418
7419 /**
7420  *      t4_cfg_pfvf - configure PF/VF resource limits
7421  *      @adap: the adapter
7422  *      @mbox: mailbox to use for the FW command
7423  *      @pf: the PF being configured
7424  *      @vf: the VF being configured
7425  *      @txq: the max number of egress queues
7426  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7427  *      @rxqi: the max number of interrupt-capable ingress queues
7428  *      @rxq: the max number of interruptless ingress queues
7429  *      @tc: the PCI traffic class
7430  *      @vi: the max number of virtual interfaces
7431  *      @cmask: the channel access rights mask for the PF/VF
7432  *      @pmask: the port access rights mask for the PF/VF
7433  *      @nexact: the maximum number of exact MPS filters
7434  *      @rcaps: read capabilities
7435  *      @wxcaps: write/execute capabilities
7436  *
7437  *      Configures resource limits and capabilities for a physical or virtual
7438  *      function.
7439  */
7440 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7441                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7442                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7443                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7444                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7445 {
7446         struct fw_pfvf_cmd c;
7447
7448         memset(&c, 0, sizeof(c));
7449         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7450                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7451                                   FW_PFVF_CMD_VFN_V(vf));
7452         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7453         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7454                                      FW_PFVF_CMD_NIQ_V(rxq));
7455         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7456                                     FW_PFVF_CMD_PMASK_V(pmask) |
7457                                     FW_PFVF_CMD_NEQ_V(txq));
7458         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7459                                       FW_PFVF_CMD_NVI_V(vi) |
7460                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7461         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7462                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7463                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7464         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7465 }
7466
7467 /**
7468  *      t4_alloc_vi - allocate a virtual interface
7469  *      @adap: the adapter
7470  *      @mbox: mailbox to use for the FW command
7471  *      @port: physical port associated with the VI
7472  *      @pf: the PF owning the VI
7473  *      @vf: the VF owning the VI
7474  *      @nmac: number of MAC addresses needed (1 to 5)
7475  *      @mac: the MAC addresses of the VI
7476  *      @rss_size: size of RSS table slice associated with this VI
7477  *
7478  *      Allocates a virtual interface for the given physical port.  If @mac is
7479  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7480  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7481  *      stored consecutively so the space needed is @nmac * 6 bytes.
7482  *      Returns a negative error number or the non-negative VI id.
7483  */
7484 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7485                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7486                 unsigned int *rss_size)
7487 {
7488         int ret;
7489         struct fw_vi_cmd c;
7490
7491         memset(&c, 0, sizeof(c));
7492         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7493                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7494                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7495         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7496         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7497         c.nmac = nmac - 1;
7498
7499         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7500         if (ret)
7501                 return ret;
7502
7503         if (mac) {
7504                 memcpy(mac, c.mac, sizeof(c.mac));
7505                 switch (nmac) {
7506                 case 5:
7507                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7508                         /* Fall through */
7509                 case 4:
7510                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7511                         /* Fall through */
7512                 case 3:
7513                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7514                         /* Fall through */
7515                 case 2:
7516                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7517                 }
7518         }
7519         if (rss_size)
7520                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7521         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7522 }
7523
7524 /**
7525  *      t4_free_vi - free a virtual interface
7526  *      @adap: the adapter
7527  *      @mbox: mailbox to use for the FW command
7528  *      @pf: the PF owning the VI
7529  *      @vf: the VF owning the VI
7530  *      @viid: virtual interface identifiler
7531  *
7532  *      Free a previously allocated virtual interface.
7533  */
7534 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7535                unsigned int vf, unsigned int viid)
7536 {
7537         struct fw_vi_cmd c;
7538
7539         memset(&c, 0, sizeof(c));
7540         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7541                                   FW_CMD_REQUEST_F |
7542                                   FW_CMD_EXEC_F |
7543                                   FW_VI_CMD_PFN_V(pf) |
7544                                   FW_VI_CMD_VFN_V(vf));
7545         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7546         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7547
7548         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7549 }
7550
7551 /**
7552  *      t4_set_rxmode - set Rx properties of a virtual interface
7553  *      @adap: the adapter
7554  *      @mbox: mailbox to use for the FW command
7555  *      @viid: the VI id
7556  *      @mtu: the new MTU or -1
7557  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7558  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7559  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7560  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7561  *      @sleep_ok: if true we may sleep while awaiting command completion
7562  *
7563  *      Sets Rx properties of a virtual interface.
7564  */
7565 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7566                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7567                   bool sleep_ok)
7568 {
7569         struct fw_vi_rxmode_cmd c;
7570
7571         /* convert to FW values */
7572         if (mtu < 0)
7573                 mtu = FW_RXMODE_MTU_NO_CHG;
7574         if (promisc < 0)
7575                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7576         if (all_multi < 0)
7577                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7578         if (bcast < 0)
7579                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7580         if (vlanex < 0)
7581                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7582
7583         memset(&c, 0, sizeof(c));
7584         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7585                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7586                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7587         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7588         c.mtu_to_vlanexen =
7589                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7590                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7591                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7592                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7593                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7594         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7595 }
7596
7597 /**
7598  *      t4_free_encap_mac_filt - frees MPS entry at given index
7599  *      @adap: the adapter
7600  *      @viid: the VI id
7601  *      @idx: index of MPS entry to be freed
7602  *      @sleep_ok: call is allowed to sleep
7603  *
7604  *      Frees the MPS entry at supplied index
7605  *
7606  *      Returns a negative error number or zero on success
7607  */
7608 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7609                            int idx, bool sleep_ok)
7610 {
7611         struct fw_vi_mac_exact *p;
7612         u8 addr[] = {0, 0, 0, 0, 0, 0};
7613         struct fw_vi_mac_cmd c;
7614         int ret = 0;
7615         u32 exact;
7616
7617         memset(&c, 0, sizeof(c));
7618         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7619                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7620                                    FW_CMD_EXEC_V(0) |
7621                                    FW_VI_MAC_CMD_VIID_V(viid));
7622         exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7623         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7624                                           exact |
7625                                           FW_CMD_LEN16_V(1));
7626         p = c.u.exact;
7627         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7628                                       FW_VI_MAC_CMD_IDX_V(idx));
7629         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7630         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7631         return ret;
7632 }
7633
7634 /**
7635  *      t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7636  *      @adap: the adapter
7637  *      @viid: the VI id
7638  *      @addr: the MAC address
7639  *      @mask: the mask
7640  *      @idx: index of the entry in mps tcam
7641  *      @lookup_type: MAC address for inner (1) or outer (0) header
7642  *      @port_id: the port index
7643  *      @sleep_ok: call is allowed to sleep
7644  *
7645  *      Removes the mac entry at the specified index using raw mac interface.
7646  *
7647  *      Returns a negative error number on failure.
7648  */
7649 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7650                          const u8 *addr, const u8 *mask, unsigned int idx,
7651                          u8 lookup_type, u8 port_id, bool sleep_ok)
7652 {
7653         struct fw_vi_mac_cmd c;
7654         struct fw_vi_mac_raw *p = &c.u.raw;
7655         u32 val;
7656
7657         memset(&c, 0, sizeof(c));
7658         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7659                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7660                                    FW_CMD_EXEC_V(0) |
7661                                    FW_VI_MAC_CMD_VIID_V(viid));
7662         val = FW_CMD_LEN16_V(1) |
7663               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7664         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7665                                           FW_CMD_LEN16_V(val));
7666
7667         p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7668                                      FW_VI_MAC_ID_BASED_FREE);
7669
7670         /* Lookup Type. Outer header: 0, Inner header: 1 */
7671         p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7672                                    DATAPORTNUM_V(port_id));
7673         /* Lookup mask and port mask */
7674         p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7675                                     DATAPORTNUM_V(DATAPORTNUM_M));
7676
7677         /* Copy the address and the mask */
7678         memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7679         memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7680
7681         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7682 }
7683
7684 /**
7685  *      t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7686  *      @adap: the adapter
7687  *      @viid: the VI id
7688  *      @mac: the MAC address
7689  *      @mask: the mask
7690  *      @vni: the VNI id for the tunnel protocol
7691  *      @vni_mask: mask for the VNI id
7692  *      @dip_hit: to enable DIP match for the MPS entry
7693  *      @lookup_type: MAC address for inner (1) or outer (0) header
7694  *      @sleep_ok: call is allowed to sleep
7695  *
7696  *      Allocates an MPS entry with specified MAC address and VNI value.
7697  *
7698  *      Returns a negative error number or the allocated index for this mac.
7699  */
7700 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7701                             const u8 *addr, const u8 *mask, unsigned int vni,
7702                             unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7703                             bool sleep_ok)
7704 {
7705         struct fw_vi_mac_cmd c;
7706         struct fw_vi_mac_vni *p = c.u.exact_vni;
7707         int ret = 0;
7708         u32 val;
7709
7710         memset(&c, 0, sizeof(c));
7711         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7712                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7713                                    FW_VI_MAC_CMD_VIID_V(viid));
7714         val = FW_CMD_LEN16_V(1) |
7715               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7716         c.freemacs_to_len16 = cpu_to_be32(val);
7717         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7718                                       FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7719         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7720         memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7721
7722         p->lookup_type_to_vni =
7723                 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7724                             FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7725                             FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7726         p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7727         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7728         if (ret == 0)
7729                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7730         return ret;
7731 }
7732
7733 /**
7734  *      t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7735  *      @adap: the adapter
7736  *      @viid: the VI id
7737  *      @mac: the MAC address
7738  *      @mask: the mask
7739  *      @idx: index at which to add this entry
7740  *      @port_id: the port index
7741  *      @lookup_type: MAC address for inner (1) or outer (0) header
7742  *      @sleep_ok: call is allowed to sleep
7743  *
7744  *      Adds the mac entry at the specified index using raw mac interface.
7745  *
7746  *      Returns a negative error number or the allocated index for this mac.
7747  */
7748 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7749                           const u8 *addr, const u8 *mask, unsigned int idx,
7750                           u8 lookup_type, u8 port_id, bool sleep_ok)
7751 {
7752         int ret = 0;
7753         struct fw_vi_mac_cmd c;
7754         struct fw_vi_mac_raw *p = &c.u.raw;
7755         u32 val;
7756
7757         memset(&c, 0, sizeof(c));
7758         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7759                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7760                                    FW_VI_MAC_CMD_VIID_V(viid));
7761         val = FW_CMD_LEN16_V(1) |
7762               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7763         c.freemacs_to_len16 = cpu_to_be32(val);
7764
7765         /* Specify that this is an inner mac address */
7766         p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7767
7768         /* Lookup Type. Outer header: 0, Inner header: 1 */
7769         p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7770                                    DATAPORTNUM_V(port_id));
7771         /* Lookup mask and port mask */
7772         p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7773                                     DATAPORTNUM_V(DATAPORTNUM_M));
7774
7775         /* Copy the address and the mask */
7776         memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7777         memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7778
7779         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7780         if (ret == 0) {
7781                 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7782                 if (ret != idx)
7783                         ret = -ENOMEM;
7784         }
7785
7786         return ret;
7787 }
7788
7789 /**
7790  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7791  *      @adap: the adapter
7792  *      @mbox: mailbox to use for the FW command
7793  *      @viid: the VI id
7794  *      @free: if true any existing filters for this VI id are first removed
7795  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7796  *      @addr: the MAC address(es)
7797  *      @idx: where to store the index of each allocated filter
7798  *      @hash: pointer to hash address filter bitmap
7799  *      @sleep_ok: call is allowed to sleep
7800  *
7801  *      Allocates an exact-match filter for each of the supplied addresses and
7802  *      sets it to the corresponding address.  If @idx is not %NULL it should
7803  *      have at least @naddr entries, each of which will be set to the index of
7804  *      the filter allocated for the corresponding MAC address.  If a filter
7805  *      could not be allocated for an address its index is set to 0xffff.
7806  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7807  *      are hashed and update the hash filter bitmap pointed at by @hash.
7808  *
7809  *      Returns a negative error number or the number of filters allocated.
7810  */
7811 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7812                       unsigned int viid, bool free, unsigned int naddr,
7813                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7814 {
7815         int offset, ret = 0;
7816         struct fw_vi_mac_cmd c;
7817         unsigned int nfilters = 0;
7818         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7819         unsigned int rem = naddr;
7820
7821         if (naddr > max_naddr)
7822                 return -EINVAL;
7823
7824         for (offset = 0; offset < naddr ; /**/) {
7825                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7826                                          rem : ARRAY_SIZE(c.u.exact));
7827                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7828                                                      u.exact[fw_naddr]), 16);
7829                 struct fw_vi_mac_exact *p;
7830                 int i;
7831
7832                 memset(&c, 0, sizeof(c));
7833                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7834                                            FW_CMD_REQUEST_F |
7835                                            FW_CMD_WRITE_F |
7836                                            FW_CMD_EXEC_V(free) |
7837                                            FW_VI_MAC_CMD_VIID_V(viid));
7838                 c.freemacs_to_len16 =
7839                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7840                                     FW_CMD_LEN16_V(len16));
7841
7842                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7843                         p->valid_to_idx =
7844                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7845                                             FW_VI_MAC_CMD_IDX_V(
7846                                                     FW_VI_MAC_ADD_MAC));
7847                         memcpy(p->macaddr, addr[offset + i],
7848                                sizeof(p->macaddr));
7849                 }
7850
7851                 /* It's okay if we run out of space in our MAC address arena.
7852                  * Some of the addresses we submit may get stored so we need
7853                  * to run through the reply to see what the results were ...
7854                  */
7855                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7856                 if (ret && ret != -FW_ENOMEM)
7857                         break;
7858
7859                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7860                         u16 index = FW_VI_MAC_CMD_IDX_G(
7861                                         be16_to_cpu(p->valid_to_idx));
7862
7863                         if (idx)
7864                                 idx[offset + i] = (index >= max_naddr ?
7865                                                    0xffff : index);
7866                         if (index < max_naddr)
7867                                 nfilters++;
7868                         else if (hash)
7869                                 *hash |= (1ULL <<
7870                                           hash_mac_addr(addr[offset + i]));
7871                 }
7872
7873                 free = false;
7874                 offset += fw_naddr;
7875                 rem -= fw_naddr;
7876         }
7877
7878         if (ret == 0 || ret == -FW_ENOMEM)
7879                 ret = nfilters;
7880         return ret;
7881 }
7882
7883 /**
7884  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
7885  *      @adap: the adapter
7886  *      @mbox: mailbox to use for the FW command
7887  *      @viid: the VI id
7888  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7889  *      @addr: the MAC address(es)
7890  *      @sleep_ok: call is allowed to sleep
7891  *
7892  *      Frees the exact-match filter for each of the supplied addresses
7893  *
7894  *      Returns a negative error number or the number of filters freed.
7895  */
7896 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7897                      unsigned int viid, unsigned int naddr,
7898                      const u8 **addr, bool sleep_ok)
7899 {
7900         int offset, ret = 0;
7901         struct fw_vi_mac_cmd c;
7902         unsigned int nfilters = 0;
7903         unsigned int max_naddr = is_t4(adap->params.chip) ?
7904                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
7905                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7906         unsigned int rem = naddr;
7907
7908         if (naddr > max_naddr)
7909                 return -EINVAL;
7910
7911         for (offset = 0; offset < (int)naddr ; /**/) {
7912                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7913                                          ? rem
7914                                          : ARRAY_SIZE(c.u.exact));
7915                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7916                                                      u.exact[fw_naddr]), 16);
7917                 struct fw_vi_mac_exact *p;
7918                 int i;
7919
7920                 memset(&c, 0, sizeof(c));
7921                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7922                                      FW_CMD_REQUEST_F |
7923                                      FW_CMD_WRITE_F |
7924                                      FW_CMD_EXEC_V(0) |
7925                                      FW_VI_MAC_CMD_VIID_V(viid));
7926                 c.freemacs_to_len16 =
7927                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7928                                             FW_CMD_LEN16_V(len16));
7929
7930                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7931                         p->valid_to_idx = cpu_to_be16(
7932                                 FW_VI_MAC_CMD_VALID_F |
7933                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7934                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7935                 }
7936
7937                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7938                 if (ret)
7939                         break;
7940
7941                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7942                         u16 index = FW_VI_MAC_CMD_IDX_G(
7943                                                 be16_to_cpu(p->valid_to_idx));
7944
7945                         if (index < max_naddr)
7946                                 nfilters++;
7947                 }
7948
7949                 offset += fw_naddr;
7950                 rem -= fw_naddr;
7951         }
7952
7953         if (ret == 0)
7954                 ret = nfilters;
7955         return ret;
7956 }
7957
7958 /**
7959  *      t4_change_mac - modifies the exact-match filter for a MAC address
7960  *      @adap: the adapter
7961  *      @mbox: mailbox to use for the FW command
7962  *      @viid: the VI id
7963  *      @idx: index of existing filter for old value of MAC address, or -1
7964  *      @addr: the new MAC address value
7965  *      @persist: whether a new MAC allocation should be persistent
7966  *      @add_smt: if true also add the address to the HW SMT
7967  *
7968  *      Modifies an exact-match filter and sets it to the new MAC address.
7969  *      Note that in general it is not possible to modify the value of a given
7970  *      filter so the generic way to modify an address filter is to free the one
7971  *      being used by the old address value and allocate a new filter for the
7972  *      new address value.  @idx can be -1 if the address is a new addition.
7973  *
7974  *      Returns a negative error number or the index of the filter with the new
7975  *      MAC value.
7976  */
7977 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7978                   int idx, const u8 *addr, bool persist, bool add_smt)
7979 {
7980         int ret, mode;
7981         struct fw_vi_mac_cmd c;
7982         struct fw_vi_mac_exact *p = c.u.exact;
7983         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7984
7985         if (idx < 0)                             /* new allocation */
7986                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7987         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7988
7989         memset(&c, 0, sizeof(c));
7990         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7991                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7992                                    FW_VI_MAC_CMD_VIID_V(viid));
7993         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7994         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7995                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7996                                       FW_VI_MAC_CMD_IDX_V(idx));
7997         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7998
7999         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8000         if (ret == 0) {
8001                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8002                 if (ret >= max_mac_addr)
8003                         ret = -ENOMEM;
8004         }
8005         return ret;
8006 }
8007
8008 /**
8009  *      t4_set_addr_hash - program the MAC inexact-match hash filter
8010  *      @adap: the adapter
8011  *      @mbox: mailbox to use for the FW command
8012  *      @viid: the VI id
8013  *      @ucast: whether the hash filter should also match unicast addresses
8014  *      @vec: the value to be written to the hash filter
8015  *      @sleep_ok: call is allowed to sleep
8016  *
8017  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
8018  */
8019 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8020                      bool ucast, u64 vec, bool sleep_ok)
8021 {
8022         struct fw_vi_mac_cmd c;
8023
8024         memset(&c, 0, sizeof(c));
8025         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8026                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8027                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8028         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8029                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8030                                           FW_CMD_LEN16_V(1));
8031         c.u.hash.hashvec = cpu_to_be64(vec);
8032         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8033 }
8034
8035 /**
8036  *      t4_enable_vi_params - enable/disable a virtual interface
8037  *      @adap: the adapter
8038  *      @mbox: mailbox to use for the FW command
8039  *      @viid: the VI id
8040  *      @rx_en: 1=enable Rx, 0=disable Rx
8041  *      @tx_en: 1=enable Tx, 0=disable Tx
8042  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8043  *
8044  *      Enables/disables a virtual interface.  Note that setting DCB Enable
8045  *      only makes sense when enabling a Virtual Interface ...
8046  */
8047 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8048                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8049 {
8050         struct fw_vi_enable_cmd c;
8051
8052         memset(&c, 0, sizeof(c));
8053         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8054                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8055                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8056         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8057                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8058                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8059                                      FW_LEN16(c));
8060         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8061 }
8062
8063 /**
8064  *      t4_enable_vi - enable/disable a virtual interface
8065  *      @adap: the adapter
8066  *      @mbox: mailbox to use for the FW command
8067  *      @viid: the VI id
8068  *      @rx_en: 1=enable Rx, 0=disable Rx
8069  *      @tx_en: 1=enable Tx, 0=disable Tx
8070  *
8071  *      Enables/disables a virtual interface.
8072  */
8073 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8074                  bool rx_en, bool tx_en)
8075 {
8076         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8077 }
8078
8079 /**
8080  *      t4_enable_pi_params - enable/disable a Port's Virtual Interface
8081  *      @adap: the adapter
8082  *      @mbox: mailbox to use for the FW command
8083  *      @pi: the Port Information structure
8084  *      @rx_en: 1=enable Rx, 0=disable Rx
8085  *      @tx_en: 1=enable Tx, 0=disable Tx
8086  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8087  *
8088  *      Enables/disables a Port's Virtual Interface.  Note that setting DCB
8089  *      Enable only makes sense when enabling a Virtual Interface ...
8090  *      If the Virtual Interface enable/disable operation is successful,
8091  *      we notify the OS-specific code of a potential Link Status change
8092  *      via the OS Contract API t4_os_link_changed().
8093  */
8094 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8095                         struct port_info *pi,
8096                         bool rx_en, bool tx_en, bool dcb_en)
8097 {
8098         int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8099                                       rx_en, tx_en, dcb_en);
8100         if (ret)
8101                 return ret;
8102         t4_os_link_changed(adap, pi->port_id,
8103                            rx_en && tx_en && pi->link_cfg.link_ok);
8104         return 0;
8105 }
8106
8107 /**
8108  *      t4_identify_port - identify a VI's port by blinking its LED
8109  *      @adap: the adapter
8110  *      @mbox: mailbox to use for the FW command
8111  *      @viid: the VI id
8112  *      @nblinks: how many times to blink LED at 2.5 Hz
8113  *
8114  *      Identifies a VI's port by blinking its LED.
8115  */
8116 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8117                      unsigned int nblinks)
8118 {
8119         struct fw_vi_enable_cmd c;
8120
8121         memset(&c, 0, sizeof(c));
8122         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8123                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8124                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8125         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8126         c.blinkdur = cpu_to_be16(nblinks);
8127         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8128 }
8129
8130 /**
8131  *      t4_iq_stop - stop an ingress queue and its FLs
8132  *      @adap: the adapter
8133  *      @mbox: mailbox to use for the FW command
8134  *      @pf: the PF owning the queues
8135  *      @vf: the VF owning the queues
8136  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8137  *      @iqid: ingress queue id
8138  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8139  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8140  *
8141  *      Stops an ingress queue and its associated FLs, if any.  This causes
8142  *      any current or future data/messages destined for these queues to be
8143  *      tossed.
8144  */
8145 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8146                unsigned int vf, unsigned int iqtype, unsigned int iqid,
8147                unsigned int fl0id, unsigned int fl1id)
8148 {
8149         struct fw_iq_cmd c;
8150
8151         memset(&c, 0, sizeof(c));
8152         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8153                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8154                                   FW_IQ_CMD_VFN_V(vf));
8155         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8156         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8157         c.iqid = cpu_to_be16(iqid);
8158         c.fl0id = cpu_to_be16(fl0id);
8159         c.fl1id = cpu_to_be16(fl1id);
8160         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8161 }
8162
8163 /**
8164  *      t4_iq_free - free an ingress queue and its FLs
8165  *      @adap: the adapter
8166  *      @mbox: mailbox to use for the FW command
8167  *      @pf: the PF owning the queues
8168  *      @vf: the VF owning the queues
8169  *      @iqtype: the ingress queue type
8170  *      @iqid: ingress queue id
8171  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8172  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8173  *
8174  *      Frees an ingress queue and its associated FLs, if any.
8175  */
8176 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8177                unsigned int vf, unsigned int iqtype, unsigned int iqid,
8178                unsigned int fl0id, unsigned int fl1id)
8179 {
8180         struct fw_iq_cmd c;
8181
8182         memset(&c, 0, sizeof(c));
8183         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8184                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8185                                   FW_IQ_CMD_VFN_V(vf));
8186         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8187         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8188         c.iqid = cpu_to_be16(iqid);
8189         c.fl0id = cpu_to_be16(fl0id);
8190         c.fl1id = cpu_to_be16(fl1id);
8191         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8192 }
8193
8194 /**
8195  *      t4_eth_eq_free - free an Ethernet egress queue
8196  *      @adap: the adapter
8197  *      @mbox: mailbox to use for the FW command
8198  *      @pf: the PF owning the queue
8199  *      @vf: the VF owning the queue
8200  *      @eqid: egress queue id
8201  *
8202  *      Frees an Ethernet egress queue.
8203  */
8204 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8205                    unsigned int vf, unsigned int eqid)
8206 {
8207         struct fw_eq_eth_cmd c;
8208
8209         memset(&c, 0, sizeof(c));
8210         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8211                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8212                                   FW_EQ_ETH_CMD_PFN_V(pf) |
8213                                   FW_EQ_ETH_CMD_VFN_V(vf));
8214         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8215         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8216         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8217 }
8218
8219 /**
8220  *      t4_ctrl_eq_free - free a control egress queue
8221  *      @adap: the adapter
8222  *      @mbox: mailbox to use for the FW command
8223  *      @pf: the PF owning the queue
8224  *      @vf: the VF owning the queue
8225  *      @eqid: egress queue id
8226  *
8227  *      Frees a control egress queue.
8228  */
8229 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8230                     unsigned int vf, unsigned int eqid)
8231 {
8232         struct fw_eq_ctrl_cmd c;
8233
8234         memset(&c, 0, sizeof(c));
8235         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8236                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8237                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
8238                                   FW_EQ_CTRL_CMD_VFN_V(vf));
8239         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8240         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8241         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8242 }
8243
8244 /**
8245  *      t4_ofld_eq_free - free an offload egress queue
8246  *      @adap: the adapter
8247  *      @mbox: mailbox to use for the FW command
8248  *      @pf: the PF owning the queue
8249  *      @vf: the VF owning the queue
8250  *      @eqid: egress queue id
8251  *
8252  *      Frees a control egress queue.
8253  */
8254 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8255                     unsigned int vf, unsigned int eqid)
8256 {
8257         struct fw_eq_ofld_cmd c;
8258
8259         memset(&c, 0, sizeof(c));
8260         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8261                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8262                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
8263                                   FW_EQ_OFLD_CMD_VFN_V(vf));
8264         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8265         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8266         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8267 }
8268
8269 /**
8270  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
8271  *      @adap: the adapter
8272  *      @link_down_rc: Link Down Reason Code
8273  *
8274  *      Returns a string representation of the Link Down Reason Code.
8275  */
8276 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8277 {
8278         static const char * const reason[] = {
8279                 "Link Down",
8280                 "Remote Fault",
8281                 "Auto-negotiation Failure",
8282                 "Reserved",
8283                 "Insufficient Airflow",
8284                 "Unable To Determine Reason",
8285                 "No RX Signal Detected",
8286                 "Reserved",
8287         };
8288
8289         if (link_down_rc >= ARRAY_SIZE(reason))
8290                 return "Bad Reason Code";
8291
8292         return reason[link_down_rc];
8293 }
8294
8295 /**
8296  * Return the highest speed set in the port capabilities, in Mb/s.
8297  */
8298 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8299 {
8300         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8301                 do { \
8302                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8303                                 return __speed; \
8304                 } while (0)
8305
8306         TEST_SPEED_RETURN(400G, 400000);
8307         TEST_SPEED_RETURN(200G, 200000);
8308         TEST_SPEED_RETURN(100G, 100000);
8309         TEST_SPEED_RETURN(50G,   50000);
8310         TEST_SPEED_RETURN(40G,   40000);
8311         TEST_SPEED_RETURN(25G,   25000);
8312         TEST_SPEED_RETURN(10G,   10000);
8313         TEST_SPEED_RETURN(1G,     1000);
8314         TEST_SPEED_RETURN(100M,    100);
8315
8316         #undef TEST_SPEED_RETURN
8317
8318         return 0;
8319 }
8320
8321 /**
8322  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
8323  *      @acaps: advertised Port Capabilities
8324  *
8325  *      Get the highest speed for the port from the advertised Port
8326  *      Capabilities.  It will be either the highest speed from the list of
8327  *      speeds or whatever user has set using ethtool.
8328  */
8329 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8330 {
8331         #define TEST_SPEED_RETURN(__caps_speed) \
8332                 do { \
8333                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8334                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8335                 } while (0)
8336
8337         TEST_SPEED_RETURN(400G);
8338         TEST_SPEED_RETURN(200G);
8339         TEST_SPEED_RETURN(100G);
8340         TEST_SPEED_RETURN(50G);
8341         TEST_SPEED_RETURN(40G);
8342         TEST_SPEED_RETURN(25G);
8343         TEST_SPEED_RETURN(10G);
8344         TEST_SPEED_RETURN(1G);
8345         TEST_SPEED_RETURN(100M);
8346
8347         #undef TEST_SPEED_RETURN
8348
8349         return 0;
8350 }
8351
8352 /**
8353  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8354  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8355  *
8356  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8357  *      32-bit Port Capabilities value.
8358  */
8359 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8360 {
8361         fw_port_cap32_t linkattr = 0;
8362
8363         /* Unfortunately the format of the Link Status in the old
8364          * 16-bit Port Information message isn't the same as the
8365          * 16-bit Port Capabilities bitfield used everywhere else ...
8366          */
8367         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8368                 linkattr |= FW_PORT_CAP32_FC_RX;
8369         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8370                 linkattr |= FW_PORT_CAP32_FC_TX;
8371         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8372                 linkattr |= FW_PORT_CAP32_SPEED_100M;
8373         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8374                 linkattr |= FW_PORT_CAP32_SPEED_1G;
8375         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8376                 linkattr |= FW_PORT_CAP32_SPEED_10G;
8377         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8378                 linkattr |= FW_PORT_CAP32_SPEED_25G;
8379         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8380                 linkattr |= FW_PORT_CAP32_SPEED_40G;
8381         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8382                 linkattr |= FW_PORT_CAP32_SPEED_100G;
8383
8384         return linkattr;
8385 }
8386
8387 /**
8388  *      t4_handle_get_port_info - process a FW reply message
8389  *      @pi: the port info
8390  *      @rpl: start of the FW message
8391  *
8392  *      Processes a GET_PORT_INFO FW reply message.
8393  */
8394 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8395 {
8396         const struct fw_port_cmd *cmd = (const void *)rpl;
8397         int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8398         struct adapter *adapter = pi->adapter;
8399         struct link_config *lc = &pi->link_cfg;
8400         int link_ok, linkdnrc;
8401         enum fw_port_type port_type;
8402         enum fw_port_module_type mod_type;
8403         unsigned int speed, fc, fec;
8404         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8405
8406         /* Extract the various fields from the Port Information message.
8407          */
8408         switch (action) {
8409         case FW_PORT_ACTION_GET_PORT_INFO: {
8410                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8411
8412                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8413                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8414                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8415                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8416                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8417                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8418                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8419                 linkattr = lstatus_to_fwcap(lstatus);
8420                 break;
8421         }
8422
8423         case FW_PORT_ACTION_GET_PORT_INFO32: {
8424                 u32 lstatus32;
8425
8426                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8427                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8428                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8429                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8430                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8431                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8432                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8433                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8434                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8435                 break;
8436         }
8437
8438         default:
8439                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8440                         be32_to_cpu(cmd->action_to_len16));
8441                 return;
8442         }
8443
8444         fec = fwcap_to_cc_fec(acaps);
8445         fc = fwcap_to_cc_pause(linkattr);
8446         speed = fwcap_to_speed(linkattr);
8447
8448         lc->new_module = false;
8449         lc->redo_l1cfg = false;
8450
8451         if (mod_type != pi->mod_type) {
8452                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8453                  * various fundamental Port Capabilities which used to be
8454                  * immutable can now change radically.  We can now have
8455                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8456                  * all change based on what Transceiver Module is inserted.
8457                  * So we need to record the Physical "Port" Capabilities on
8458                  * every Transceiver Module change.
8459                  */
8460                 lc->pcaps = pcaps;
8461
8462                 /* When a new Transceiver Module is inserted, the Firmware
8463                  * will examine its i2c EPROM to determine its type and
8464                  * general operating parameters including things like Forward
8465                  * Error Control, etc.  Various IEEE 802.3 standards dictate
8466                  * how to interpret these i2c values to determine default
8467                  * "sutomatic" settings.  We record these for future use when
8468                  * the user explicitly requests these standards-based values.
8469                  */
8470                 lc->def_acaps = acaps;
8471
8472                 /* Some versions of the early T6 Firmware "cheated" when
8473                  * handling different Transceiver Modules by changing the
8474                  * underlaying Port Type reported to the Host Drivers.  As
8475                  * such we need to capture whatever Port Type the Firmware
8476                  * sends us and record it in case it's different from what we
8477                  * were told earlier.  Unfortunately, since Firmware is
8478                  * forever, we'll need to keep this code here forever, but in
8479                  * later T6 Firmware it should just be an assignment of the
8480                  * same value already recorded.
8481                  */
8482                 pi->port_type = port_type;
8483
8484                 pi->mod_type = mod_type;
8485
8486                 lc->new_module = t4_is_inserted_mod_type(mod_type);
8487                 t4_os_portmod_changed(adapter, pi->port_id);
8488         }
8489
8490         if (link_ok != lc->link_ok || speed != lc->speed ||
8491             fc != lc->fc || fec != lc->fec) {   /* something changed */
8492                 if (!link_ok && lc->link_ok) {
8493                         lc->link_down_rc = linkdnrc;
8494                         dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
8495                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
8496                 }
8497                 lc->link_ok = link_ok;
8498                 lc->speed = speed;
8499                 lc->fc = fc;
8500                 lc->fec = fec;
8501
8502                 lc->lpacaps = lpacaps;
8503                 lc->acaps = acaps & ADVERT_MASK;
8504
8505                 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8506                         lc->autoneg = AUTONEG_DISABLE;
8507                 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8508                         lc->autoneg = AUTONEG_ENABLE;
8509                 } else {
8510                         /* When Autoneg is disabled, user needs to set
8511                          * single speed.
8512                          * Similar to cxgb4_ethtool.c: set_link_ksettings
8513                          */
8514                         lc->acaps = 0;
8515                         lc->speed_caps = fwcap_to_fwspeed(acaps);
8516                         lc->autoneg = AUTONEG_DISABLE;
8517                 }
8518
8519                 t4_os_link_changed(adapter, pi->port_id, link_ok);
8520         }
8521
8522         if (lc->new_module && lc->redo_l1cfg) {
8523                 struct link_config old_lc;
8524                 int ret;
8525
8526                 /* Save the current L1 Configuration and restore it if an
8527                  * error occurs.  We probably should fix the l1_cfg*()
8528                  * routines not to change the link_config when an error
8529                  * occurs ...
8530                  */
8531                 old_lc = *lc;
8532                 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8533                 if (ret) {
8534                         *lc = old_lc;
8535                         dev_warn(adapter->pdev_dev,
8536                                  "Attempt to update new Transceiver Module settings failed\n");
8537                 }
8538         }
8539         lc->new_module = false;
8540         lc->redo_l1cfg = false;
8541 }
8542
8543 /**
8544  *      t4_update_port_info - retrieve and update port information if changed
8545  *      @pi: the port_info
8546  *
8547  *      We issue a Get Port Information Command to the Firmware and, if
8548  *      successful, we check to see if anything is different from what we
8549  *      last recorded and update things accordingly.
8550  */
8551 int t4_update_port_info(struct port_info *pi)
8552 {
8553         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8554         struct fw_port_cmd port_cmd;
8555         int ret;
8556
8557         memset(&port_cmd, 0, sizeof(port_cmd));
8558         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8559                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8560                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8561         port_cmd.action_to_len16 = cpu_to_be32(
8562                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8563                                      ? FW_PORT_ACTION_GET_PORT_INFO
8564                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8565                 FW_LEN16(port_cmd));
8566         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8567                          &port_cmd, sizeof(port_cmd), &port_cmd);
8568         if (ret)
8569                 return ret;
8570
8571         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8572         return 0;
8573 }
8574
8575 /**
8576  *      t4_get_link_params - retrieve basic link parameters for given port
8577  *      @pi: the port
8578  *      @link_okp: value return pointer for link up/down
8579  *      @speedp: value return pointer for speed (Mb/s)
8580  *      @mtup: value return pointer for mtu
8581  *
8582  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8583  *      and MTU for a specified port.  A negative error is returned on
8584  *      failure; 0 on success.
8585  */
8586 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8587                        unsigned int *speedp, unsigned int *mtup)
8588 {
8589         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8590         struct fw_port_cmd port_cmd;
8591         unsigned int action, link_ok, speed, mtu;
8592         fw_port_cap32_t linkattr;
8593         int ret;
8594
8595         memset(&port_cmd, 0, sizeof(port_cmd));
8596         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8597                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8598                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8599         action = (fw_caps == FW_CAPS16
8600                   ? FW_PORT_ACTION_GET_PORT_INFO
8601                   : FW_PORT_ACTION_GET_PORT_INFO32);
8602         port_cmd.action_to_len16 = cpu_to_be32(
8603                 FW_PORT_CMD_ACTION_V(action) |
8604                 FW_LEN16(port_cmd));
8605         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8606                          &port_cmd, sizeof(port_cmd), &port_cmd);
8607         if (ret)
8608                 return ret;
8609
8610         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8611                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8612
8613                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8614                 linkattr = lstatus_to_fwcap(lstatus);
8615                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8616         } else {
8617                 u32 lstatus32 =
8618                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8619
8620                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8621                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8622                 mtu = FW_PORT_CMD_MTU32_G(
8623                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8624         }
8625         speed = fwcap_to_speed(linkattr);
8626
8627         *link_okp = link_ok;
8628         *speedp = fwcap_to_speed(linkattr);
8629         *mtup = mtu;
8630
8631         return 0;
8632 }
8633
8634 /**
8635  *      t4_handle_fw_rpl - process a FW reply message
8636  *      @adap: the adapter
8637  *      @rpl: start of the FW message
8638  *
8639  *      Processes a FW message, such as link state change messages.
8640  */
8641 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8642 {
8643         u8 opcode = *(const u8 *)rpl;
8644
8645         /* This might be a port command ... this simplifies the following
8646          * conditionals ...  We can get away with pre-dereferencing
8647          * action_to_len16 because it's in the first 16 bytes and all messages
8648          * will be at least that long.
8649          */
8650         const struct fw_port_cmd *p = (const void *)rpl;
8651         unsigned int action =
8652                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8653
8654         if (opcode == FW_PORT_CMD &&
8655             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8656              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8657                 int i;
8658                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8659                 struct port_info *pi = NULL;
8660
8661                 for_each_port(adap, i) {
8662                         pi = adap2pinfo(adap, i);
8663                         if (pi->tx_chan == chan)
8664                                 break;
8665                 }
8666
8667                 t4_handle_get_port_info(pi, rpl);
8668         } else {
8669                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8670                          opcode);
8671                 return -EINVAL;
8672         }
8673         return 0;
8674 }
8675
8676 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8677 {
8678         u16 val;
8679
8680         if (pci_is_pcie(adapter->pdev)) {
8681                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8682                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8683                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8684         }
8685 }
8686
8687 /**
8688  *      init_link_config - initialize a link's SW state
8689  *      @lc: pointer to structure holding the link state
8690  *      @pcaps: link Port Capabilities
8691  *      @acaps: link current Advertised Port Capabilities
8692  *
8693  *      Initializes the SW state maintained for each link, including the link's
8694  *      capabilities and default speed/flow-control/autonegotiation settings.
8695  */
8696 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8697                              fw_port_cap32_t acaps)
8698 {
8699         lc->pcaps = pcaps;
8700         lc->def_acaps = acaps;
8701         lc->lpacaps = 0;
8702         lc->speed_caps = 0;
8703         lc->speed = 0;
8704         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8705
8706         /* For Forward Error Control, we default to whatever the Firmware
8707          * tells us the Link is currently advertising.
8708          */
8709         lc->requested_fec = FEC_AUTO;
8710         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8711
8712         /* If the Port is capable of Auto-Negtotiation, initialize it as
8713          * "enabled" and copy over all of the Physical Port Capabilities
8714          * to the Advertised Port Capabilities.  Otherwise mark it as
8715          * Auto-Negotiate disabled and select the highest supported speed
8716          * for the link.  Note parallel structure in t4_link_l1cfg_core()
8717          * and t4_handle_get_port_info().
8718          */
8719         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8720                 lc->acaps = lc->pcaps & ADVERT_MASK;
8721                 lc->autoneg = AUTONEG_ENABLE;
8722                 lc->requested_fc |= PAUSE_AUTONEG;
8723         } else {
8724                 lc->acaps = 0;
8725                 lc->autoneg = AUTONEG_DISABLE;
8726                 lc->speed_caps = fwcap_to_fwspeed(acaps);
8727         }
8728 }
8729
8730 #define CIM_PF_NOACCESS 0xeeeeeeee
8731
8732 int t4_wait_dev_ready(void __iomem *regs)
8733 {
8734         u32 whoami;
8735
8736         whoami = readl(regs + PL_WHOAMI_A);
8737         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8738                 return 0;
8739
8740         msleep(500);
8741         whoami = readl(regs + PL_WHOAMI_A);
8742         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8743 }
8744
8745 struct flash_desc {
8746         u32 vendor_and_model_id;
8747         u32 size_mb;
8748 };
8749
8750 static int t4_get_flash_params(struct adapter *adap)
8751 {
8752         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8753          * to the preexisting code.  All flash parts have 64KB sectors.
8754          */
8755         static struct flash_desc supported_flash[] = {
8756                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8757         };
8758
8759         unsigned int part, manufacturer;
8760         unsigned int density, size = 0;
8761         u32 flashid = 0;
8762         int ret;
8763
8764         /* Issue a Read ID Command to the Flash part.  We decode supported
8765          * Flash parts and their sizes from this.  There's a newer Query
8766          * Command which can retrieve detailed geometry information but many
8767          * Flash parts don't support it.
8768          */
8769
8770         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8771         if (!ret)
8772                 ret = sf1_read(adap, 3, 0, 1, &flashid);
8773         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8774         if (ret)
8775                 return ret;
8776
8777         /* Check to see if it's one of our non-standard supported Flash parts.
8778          */
8779         for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8780                 if (supported_flash[part].vendor_and_model_id == flashid) {
8781                         adap->params.sf_size = supported_flash[part].size_mb;
8782                         adap->params.sf_nsec =
8783                                 adap->params.sf_size / SF_SEC_SIZE;
8784                         goto found;
8785                 }
8786
8787         /* Decode Flash part size.  The code below looks repetative with
8788          * common encodings, but that's not guaranteed in the JEDEC
8789          * specification for the Read JADEC ID command.  The only thing that
8790          * we're guaranteed by the JADEC specification is where the
8791          * Manufacturer ID is in the returned result.  After that each
8792          * Manufacturer ~could~ encode things completely differently.
8793          * Note, all Flash parts must have 64KB sectors.
8794          */
8795         manufacturer = flashid & 0xff;
8796         switch (manufacturer) {
8797         case 0x20: { /* Micron/Numonix */
8798                 /* This Density -> Size decoding table is taken from Micron
8799                  * Data Sheets.
8800                  */
8801                 density = (flashid >> 16) & 0xff;
8802                 switch (density) {
8803                 case 0x14: /* 1MB */
8804                         size = 1 << 20;
8805                         break;
8806                 case 0x15: /* 2MB */
8807                         size = 1 << 21;
8808                         break;
8809                 case 0x16: /* 4MB */
8810                         size = 1 << 22;
8811                         break;
8812                 case 0x17: /* 8MB */
8813                         size = 1 << 23;
8814                         break;
8815                 case 0x18: /* 16MB */
8816                         size = 1 << 24;
8817                         break;
8818                 case 0x19: /* 32MB */
8819                         size = 1 << 25;
8820                         break;
8821                 case 0x20: /* 64MB */
8822                         size = 1 << 26;
8823                         break;
8824                 case 0x21: /* 128MB */
8825                         size = 1 << 27;
8826                         break;
8827                 case 0x22: /* 256MB */
8828                         size = 1 << 28;
8829                         break;
8830                 }
8831                 break;
8832         }
8833         case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
8834                 /* This Density -> Size decoding table is taken from ISSI
8835                  * Data Sheets.
8836                  */
8837                 density = (flashid >> 16) & 0xff;
8838                 switch (density) {
8839                 case 0x16: /* 32 MB */
8840                         size = 1 << 25;
8841                         break;
8842                 case 0x17: /* 64MB */
8843                         size = 1 << 26;
8844                         break;
8845                 }
8846                 break;
8847         }
8848         case 0xc2: { /* Macronix */
8849                 /* This Density -> Size decoding table is taken from Macronix
8850                  * Data Sheets.
8851                  */
8852                 density = (flashid >> 16) & 0xff;
8853                 switch (density) {
8854                 case 0x17: /* 8MB */
8855                         size = 1 << 23;
8856                         break;
8857                 case 0x18: /* 16MB */
8858                         size = 1 << 24;
8859                         break;
8860                 }
8861                 break;
8862         }
8863         case 0xef: { /* Winbond */
8864                 /* This Density -> Size decoding table is taken from Winbond
8865                  * Data Sheets.
8866                  */
8867                 density = (flashid >> 16) & 0xff;
8868                 switch (density) {
8869                 case 0x17: /* 8MB */
8870                         size = 1 << 23;
8871                         break;
8872                 case 0x18: /* 16MB */
8873                         size = 1 << 24;
8874                         break;
8875                 }
8876                 break;
8877         }
8878         }
8879
8880         /* If we didn't recognize the FLASH part, that's no real issue: the
8881          * Hardware/Software contract says that Hardware will _*ALWAYS*_
8882          * use a FLASH part which is at least 4MB in size and has 64KB
8883          * sectors.  The unrecognized FLASH part is likely to be much larger
8884          * than 4MB, but that's all we really need.
8885          */
8886         if (size == 0) {
8887                 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
8888                          flashid);
8889                 size = 1 << 22;
8890         }
8891
8892         /* Store decoded Flash size and fall through into vetting code. */
8893         adap->params.sf_size = size;
8894         adap->params.sf_nsec = size / SF_SEC_SIZE;
8895
8896 found:
8897         if (adap->params.sf_size < FLASH_MIN_SIZE)
8898                 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8899                          flashid, adap->params.sf_size, FLASH_MIN_SIZE);
8900         return 0;
8901 }
8902
8903 /**
8904  *      t4_prep_adapter - prepare SW and HW for operation
8905  *      @adapter: the adapter
8906  *      @reset: if true perform a HW reset
8907  *
8908  *      Initialize adapter SW state for the various HW modules, set initial
8909  *      values for some adapter tunables, take PHYs out of reset, and
8910  *      initialize the MDIO interface.
8911  */
8912 int t4_prep_adapter(struct adapter *adapter)
8913 {
8914         int ret, ver;
8915         uint16_t device_id;
8916         u32 pl_rev;
8917
8918         get_pci_mode(adapter, &adapter->params.pci);
8919         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8920
8921         ret = t4_get_flash_params(adapter);
8922         if (ret < 0) {
8923                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8924                 return ret;
8925         }
8926
8927         /* Retrieve adapter's device ID
8928          */
8929         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8930         ver = device_id >> 12;
8931         adapter->params.chip = 0;
8932         switch (ver) {
8933         case CHELSIO_T4:
8934                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8935                 adapter->params.arch.sge_fl_db = DBPRIO_F;
8936                 adapter->params.arch.mps_tcam_size =
8937                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
8938                 adapter->params.arch.mps_rplc_size = 128;
8939                 adapter->params.arch.nchan = NCHAN;
8940                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8941                 adapter->params.arch.vfcount = 128;
8942                 /* Congestion map is for 4 channels so that
8943                  * MPS can have 4 priority per port.
8944                  */
8945                 adapter->params.arch.cng_ch_bits_log = 2;
8946                 break;
8947         case CHELSIO_T5:
8948                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8949                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8950                 adapter->params.arch.mps_tcam_size =
8951                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8952                 adapter->params.arch.mps_rplc_size = 128;
8953                 adapter->params.arch.nchan = NCHAN;
8954                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8955                 adapter->params.arch.vfcount = 128;
8956                 adapter->params.arch.cng_ch_bits_log = 2;
8957                 break;
8958         case CHELSIO_T6:
8959                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8960                 adapter->params.arch.sge_fl_db = 0;
8961                 adapter->params.arch.mps_tcam_size =
8962                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8963                 adapter->params.arch.mps_rplc_size = 256;
8964                 adapter->params.arch.nchan = 2;
8965                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8966                 adapter->params.arch.vfcount = 256;
8967                 /* Congestion map will be for 2 channels so that
8968                  * MPS can have 8 priority per port.
8969                  */
8970                 adapter->params.arch.cng_ch_bits_log = 3;
8971                 break;
8972         default:
8973                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8974                         device_id);
8975                 return -EINVAL;
8976         }
8977
8978         adapter->params.cim_la_size = CIMLA_SIZE;
8979         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8980
8981         /*
8982          * Default port for debugging in case we can't reach FW.
8983          */
8984         adapter->params.nports = 1;
8985         adapter->params.portvec = 1;
8986         adapter->params.vpd.cclk = 50000;
8987
8988         /* Set PCIe completion timeout to 4 seconds. */
8989         pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
8990                                            PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
8991         return 0;
8992 }
8993
8994 /**
8995  *      t4_shutdown_adapter - shut down adapter, host & wire
8996  *      @adapter: the adapter
8997  *
8998  *      Perform an emergency shutdown of the adapter and stop it from
8999  *      continuing any further communication on the ports or DMA to the
9000  *      host.  This is typically used when the adapter and/or firmware
9001  *      have crashed and we want to prevent any further accidental
9002  *      communication with the rest of the world.  This will also force
9003  *      the port Link Status to go down -- if register writes work --
9004  *      which should help our peers figure out that we're down.
9005  */
9006 int t4_shutdown_adapter(struct adapter *adapter)
9007 {
9008         int port;
9009
9010         t4_intr_disable(adapter);
9011         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9012         for_each_port(adapter, port) {
9013                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9014                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
9015                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
9016
9017                 t4_write_reg(adapter, a_port_cfg,
9018                              t4_read_reg(adapter, a_port_cfg)
9019                              & ~SIGNAL_DET_V(1));
9020         }
9021         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9022
9023         return 0;
9024 }
9025
9026 /**
9027  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9028  *      @adapter: the adapter
9029  *      @qid: the Queue ID
9030  *      @qtype: the Ingress or Egress type for @qid
9031  *      @user: true if this request is for a user mode queue
9032  *      @pbar2_qoffset: BAR2 Queue Offset
9033  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9034  *
9035  *      Returns the BAR2 SGE Queue Registers information associated with the
9036  *      indicated Absolute Queue ID.  These are passed back in return value
9037  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9038  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9039  *
9040  *      This may return an error which indicates that BAR2 SGE Queue
9041  *      registers aren't available.  If an error is not returned, then the
9042  *      following values are returned:
9043  *
9044  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9045  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9046  *
9047  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9048  *      require the "Inferred Queue ID" ability may be used.  E.g. the
9049  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9050  *      then these "Inferred Queue ID" register may not be used.
9051  */
9052 int t4_bar2_sge_qregs(struct adapter *adapter,
9053                       unsigned int qid,
9054                       enum t4_bar2_qtype qtype,
9055                       int user,
9056                       u64 *pbar2_qoffset,
9057                       unsigned int *pbar2_qid)
9058 {
9059         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9060         u64 bar2_page_offset, bar2_qoffset;
9061         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9062
9063         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9064         if (!user && is_t4(adapter->params.chip))
9065                 return -EINVAL;
9066
9067         /* Get our SGE Page Size parameters.
9068          */
9069         page_shift = adapter->params.sge.hps + 10;
9070         page_size = 1 << page_shift;
9071
9072         /* Get the right Queues per Page parameters for our Queue.
9073          */
9074         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9075                      ? adapter->params.sge.eq_qpp
9076                      : adapter->params.sge.iq_qpp);
9077         qpp_mask = (1 << qpp_shift) - 1;
9078
9079         /*  Calculate the basics of the BAR2 SGE Queue register area:
9080          *  o The BAR2 page the Queue registers will be in.
9081          *  o The BAR2 Queue ID.
9082          *  o The BAR2 Queue ID Offset into the BAR2 page.
9083          */
9084         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9085         bar2_qid = qid & qpp_mask;
9086         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9087
9088         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9089          * hardware will infer the Absolute Queue ID simply from the writes to
9090          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9091          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
9092          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9093          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9094          * from the BAR2 Page and BAR2 Queue ID.
9095          *
9096          * One important censequence of this is that some BAR2 SGE registers
9097          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9098          * there.  But other registers synthesize the SGE Queue ID purely
9099          * from the writes to the registers -- the Write Combined Doorbell
9100          * Buffer is a good example.  These BAR2 SGE Registers are only
9101          * available for those BAR2 SGE Register areas where the SGE Absolute
9102          * Queue ID can be inferred from simple writes.
9103          */
9104         bar2_qoffset = bar2_page_offset;
9105         bar2_qinferred = (bar2_qid_offset < page_size);
9106         if (bar2_qinferred) {
9107                 bar2_qoffset += bar2_qid_offset;
9108                 bar2_qid = 0;
9109         }
9110
9111         *pbar2_qoffset = bar2_qoffset;
9112         *pbar2_qid = bar2_qid;
9113         return 0;
9114 }
9115
9116 /**
9117  *      t4_init_devlog_params - initialize adapter->params.devlog
9118  *      @adap: the adapter
9119  *
9120  *      Initialize various fields of the adapter's Firmware Device Log
9121  *      Parameters structure.
9122  */
9123 int t4_init_devlog_params(struct adapter *adap)
9124 {
9125         struct devlog_params *dparams = &adap->params.devlog;
9126         u32 pf_dparams;
9127         unsigned int devlog_meminfo;
9128         struct fw_devlog_cmd devlog_cmd;
9129         int ret;
9130
9131         /* If we're dealing with newer firmware, the Device Log Paramerters
9132          * are stored in a designated register which allows us to access the
9133          * Device Log even if we can't talk to the firmware.
9134          */
9135         pf_dparams =
9136                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9137         if (pf_dparams) {
9138                 unsigned int nentries, nentries128;
9139
9140                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9141                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9142
9143                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9144                 nentries = (nentries128 + 1) * 128;
9145                 dparams->size = nentries * sizeof(struct fw_devlog_e);
9146
9147                 return 0;
9148         }
9149
9150         /* Otherwise, ask the firmware for it's Device Log Parameters.
9151          */
9152         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9153         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9154                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
9155         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9156         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9157                          &devlog_cmd);
9158         if (ret)
9159                 return ret;
9160
9161         devlog_meminfo =
9162                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9163         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9164         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9165         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9166
9167         return 0;
9168 }
9169
9170 /**
9171  *      t4_init_sge_params - initialize adap->params.sge
9172  *      @adapter: the adapter
9173  *
9174  *      Initialize various fields of the adapter's SGE Parameters structure.
9175  */
9176 int t4_init_sge_params(struct adapter *adapter)
9177 {
9178         struct sge_params *sge_params = &adapter->params.sge;
9179         u32 hps, qpp;
9180         unsigned int s_hps, s_qpp;
9181
9182         /* Extract the SGE Page Size for our PF.
9183          */
9184         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9185         s_hps = (HOSTPAGESIZEPF0_S +
9186                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9187         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9188
9189         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9190          */
9191         s_qpp = (QUEUESPERPAGEPF0_S +
9192                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9193         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9194         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9195         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9196         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9197
9198         return 0;
9199 }
9200
9201 /**
9202  *      t4_init_tp_params - initialize adap->params.tp
9203  *      @adap: the adapter
9204  *      @sleep_ok: if true we may sleep while awaiting command completion
9205  *
9206  *      Initialize various fields of the adapter's TP Parameters structure.
9207  */
9208 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9209 {
9210         int chan;
9211         u32 v;
9212
9213         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9214         adap->params.tp.tre = TIMERRESOLUTION_G(v);
9215         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9216
9217         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9218         for (chan = 0; chan < NCHAN; chan++)
9219                 adap->params.tp.tx_modq[chan] = chan;
9220
9221         /* Cache the adapter's Compressed Filter Mode and global Incress
9222          * Configuration.
9223          */
9224         t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9225                        TP_VLAN_PRI_MAP_A, sleep_ok);
9226         t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9227                        TP_INGRESS_CONFIG_A, sleep_ok);
9228
9229         /* For T6, cache the adapter's compressed error vector
9230          * and passing outer header info for encapsulated packets.
9231          */
9232         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9233                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9234                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9235         }
9236
9237         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9238          * shift positions of several elements of the Compressed Filter Tuple
9239          * for this adapter which we need frequently ...
9240          */
9241         adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9242         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9243         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9244         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9245         adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9246         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9247                                                                PROTOCOL_F);
9248         adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9249                                                                 ETHERTYPE_F);
9250         adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9251                                                                MACMATCH_F);
9252         adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9253                                                                 MPSHITTYPE_F);
9254         adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9255                                                            FRAGMENTATION_F);
9256
9257         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9258          * represents the presence of an Outer VLAN instead of a VNIC ID.
9259          */
9260         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9261                 adap->params.tp.vnic_shift = -1;
9262
9263         v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9264         adap->params.tp.hash_filter_mask = v;
9265         v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9266         adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9267         return 0;
9268 }
9269
9270 /**
9271  *      t4_filter_field_shift - calculate filter field shift
9272  *      @adap: the adapter
9273  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9274  *
9275  *      Return the shift position of a filter field within the Compressed
9276  *      Filter Tuple.  The filter field is specified via its selection bit
9277  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
9278  */
9279 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9280 {
9281         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9282         unsigned int sel;
9283         int field_shift;
9284
9285         if ((filter_mode & filter_sel) == 0)
9286                 return -1;
9287
9288         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9289                 switch (filter_mode & sel) {
9290                 case FCOE_F:
9291                         field_shift += FT_FCOE_W;
9292                         break;
9293                 case PORT_F:
9294                         field_shift += FT_PORT_W;
9295                         break;
9296                 case VNIC_ID_F:
9297                         field_shift += FT_VNIC_ID_W;
9298                         break;
9299                 case VLAN_F:
9300                         field_shift += FT_VLAN_W;
9301                         break;
9302                 case TOS_F:
9303                         field_shift += FT_TOS_W;
9304                         break;
9305                 case PROTOCOL_F:
9306                         field_shift += FT_PROTOCOL_W;
9307                         break;
9308                 case ETHERTYPE_F:
9309                         field_shift += FT_ETHERTYPE_W;
9310                         break;
9311                 case MACMATCH_F:
9312                         field_shift += FT_MACMATCH_W;
9313                         break;
9314                 case MPSHITTYPE_F:
9315                         field_shift += FT_MPSHITTYPE_W;
9316                         break;
9317                 case FRAGMENTATION_F:
9318                         field_shift += FT_FRAGMENTATION_W;
9319                         break;
9320                 }
9321         }
9322         return field_shift;
9323 }
9324
9325 int t4_init_rss_mode(struct adapter *adap, int mbox)
9326 {
9327         int i, ret;
9328         struct fw_rss_vi_config_cmd rvc;
9329
9330         memset(&rvc, 0, sizeof(rvc));
9331
9332         for_each_port(adap, i) {
9333                 struct port_info *p = adap2pinfo(adap, i);
9334
9335                 rvc.op_to_viid =
9336                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9337                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
9338                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9339                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9340                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9341                 if (ret)
9342                         return ret;
9343                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9344         }
9345         return 0;
9346 }
9347
9348 /**
9349  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
9350  *      @pi: the port_info
9351  *      @mbox: mailbox to use for the FW command
9352  *      @port: physical port associated with the VI
9353  *      @pf: the PF owning the VI
9354  *      @vf: the VF owning the VI
9355  *      @mac: the MAC address of the VI
9356  *
9357  *      Allocates a virtual interface for the given physical port.  If @mac is
9358  *      not %NULL it contains the MAC address of the VI as assigned by FW.
9359  *      @mac should be large enough to hold an Ethernet address.
9360  *      Returns < 0 on error.
9361  */
9362 int t4_init_portinfo(struct port_info *pi, int mbox,
9363                      int port, int pf, int vf, u8 mac[])
9364 {
9365         struct adapter *adapter = pi->adapter;
9366         unsigned int fw_caps = adapter->params.fw_caps_support;
9367         struct fw_port_cmd cmd;
9368         unsigned int rss_size;
9369         enum fw_port_type port_type;
9370         int mdio_addr;
9371         fw_port_cap32_t pcaps, acaps;
9372         int ret;
9373
9374         /* If we haven't yet determined whether we're talking to Firmware
9375          * which knows the new 32-bit Port Capabilities, it's time to find
9376          * out now.  This will also tell new Firmware to send us Port Status
9377          * Updates using the new 32-bit Port Capabilities version of the
9378          * Port Information message.
9379          */
9380         if (fw_caps == FW_CAPS_UNKNOWN) {
9381                 u32 param, val;
9382
9383                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9384                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9385                 val = 1;
9386                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
9387                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9388                 adapter->params.fw_caps_support = fw_caps;
9389         }
9390
9391         memset(&cmd, 0, sizeof(cmd));
9392         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9393                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
9394                                        FW_PORT_CMD_PORTID_V(port));
9395         cmd.action_to_len16 = cpu_to_be32(
9396                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9397                                      ? FW_PORT_ACTION_GET_PORT_INFO
9398                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
9399                 FW_LEN16(cmd));
9400         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9401         if (ret)
9402                 return ret;
9403
9404         /* Extract the various fields from the Port Information message.
9405          */
9406         if (fw_caps == FW_CAPS16) {
9407                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9408
9409                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9410                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9411                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9412                              : -1);
9413                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9414                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9415         } else {
9416                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9417
9418                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9419                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9420                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9421                              : -1);
9422                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9423                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9424         }
9425
9426         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
9427         if (ret < 0)
9428                 return ret;
9429
9430         pi->viid = ret;
9431         pi->tx_chan = port;
9432         pi->lport = port;
9433         pi->rss_size = rss_size;
9434
9435         pi->port_type = port_type;
9436         pi->mdio_addr = mdio_addr;
9437         pi->mod_type = FW_PORT_MOD_TYPE_NA;
9438
9439         init_link_config(&pi->link_cfg, pcaps, acaps);
9440         return 0;
9441 }
9442
9443 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9444 {
9445         u8 addr[6];
9446         int ret, i, j = 0;
9447
9448         for_each_port(adap, i) {
9449                 struct port_info *pi = adap2pinfo(adap, i);
9450
9451                 while ((adap->params.portvec & (1 << j)) == 0)
9452                         j++;
9453
9454                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9455                 if (ret)
9456                         return ret;
9457
9458                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9459                 j++;
9460         }
9461         return 0;
9462 }
9463
9464 /**
9465  *      t4_read_cimq_cfg - read CIM queue configuration
9466  *      @adap: the adapter
9467  *      @base: holds the queue base addresses in bytes
9468  *      @size: holds the queue sizes in bytes
9469  *      @thres: holds the queue full thresholds in bytes
9470  *
9471  *      Returns the current configuration of the CIM queues, starting with
9472  *      the IBQs, then the OBQs.
9473  */
9474 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9475 {
9476         unsigned int i, v;
9477         int cim_num_obq = is_t4(adap->params.chip) ?
9478                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9479
9480         for (i = 0; i < CIM_NUM_IBQ; i++) {
9481                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9482                              QUENUMSELECT_V(i));
9483                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9484                 /* value is in 256-byte units */
9485                 *base++ = CIMQBASE_G(v) * 256;
9486                 *size++ = CIMQSIZE_G(v) * 256;
9487                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9488         }
9489         for (i = 0; i < cim_num_obq; i++) {
9490                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9491                              QUENUMSELECT_V(i));
9492                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9493                 /* value is in 256-byte units */
9494                 *base++ = CIMQBASE_G(v) * 256;
9495                 *size++ = CIMQSIZE_G(v) * 256;
9496         }
9497 }
9498
9499 /**
9500  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
9501  *      @adap: the adapter
9502  *      @qid: the queue index
9503  *      @data: where to store the queue contents
9504  *      @n: capacity of @data in 32-bit words
9505  *
9506  *      Reads the contents of the selected CIM queue starting at address 0 up
9507  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9508  *      error and the number of 32-bit words actually read on success.
9509  */
9510 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9511 {
9512         int i, err, attempts;
9513         unsigned int addr;
9514         const unsigned int nwords = CIM_IBQ_SIZE * 4;
9515
9516         if (qid > 5 || (n & 3))
9517                 return -EINVAL;
9518
9519         addr = qid * nwords;
9520         if (n > nwords)
9521                 n = nwords;
9522
9523         /* It might take 3-10ms before the IBQ debug read access is allowed.
9524          * Wait for 1 Sec with a delay of 1 usec.
9525          */
9526         attempts = 1000000;
9527
9528         for (i = 0; i < n; i++, addr++) {
9529                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9530                              IBQDBGEN_F);
9531                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9532                                       attempts, 1);
9533                 if (err)
9534                         return err;
9535                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9536         }
9537         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9538         return i;
9539 }
9540
9541 /**
9542  *      t4_read_cim_obq - read the contents of a CIM outbound queue
9543  *      @adap: the adapter
9544  *      @qid: the queue index
9545  *      @data: where to store the queue contents
9546  *      @n: capacity of @data in 32-bit words
9547  *
9548  *      Reads the contents of the selected CIM queue starting at address 0 up
9549  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9550  *      error and the number of 32-bit words actually read on success.
9551  */
9552 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9553 {
9554         int i, err;
9555         unsigned int addr, v, nwords;
9556         int cim_num_obq = is_t4(adap->params.chip) ?
9557                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9558
9559         if ((qid > (cim_num_obq - 1)) || (n & 3))
9560                 return -EINVAL;
9561
9562         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9563                      QUENUMSELECT_V(qid));
9564         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9565
9566         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9567         nwords = CIMQSIZE_G(v) * 64;  /* same */
9568         if (n > nwords)
9569                 n = nwords;
9570
9571         for (i = 0; i < n; i++, addr++) {
9572                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9573                              OBQDBGEN_F);
9574                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9575                                       2, 1);
9576                 if (err)
9577                         return err;
9578                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9579         }
9580         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9581         return i;
9582 }
9583
9584 /**
9585  *      t4_cim_read - read a block from CIM internal address space
9586  *      @adap: the adapter
9587  *      @addr: the start address within the CIM address space
9588  *      @n: number of words to read
9589  *      @valp: where to store the result
9590  *
9591  *      Reads a block of 4-byte words from the CIM intenal address space.
9592  */
9593 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9594                 unsigned int *valp)
9595 {
9596         int ret = 0;
9597
9598         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9599                 return -EBUSY;
9600
9601         for ( ; !ret && n--; addr += 4) {
9602                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9603                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9604                                       0, 5, 2);
9605                 if (!ret)
9606                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9607         }
9608         return ret;
9609 }
9610
9611 /**
9612  *      t4_cim_write - write a block into CIM internal address space
9613  *      @adap: the adapter
9614  *      @addr: the start address within the CIM address space
9615  *      @n: number of words to write
9616  *      @valp: set of values to write
9617  *
9618  *      Writes a block of 4-byte words into the CIM intenal address space.
9619  */
9620 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9621                  const unsigned int *valp)
9622 {
9623         int ret = 0;
9624
9625         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9626                 return -EBUSY;
9627
9628         for ( ; !ret && n--; addr += 4) {
9629                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9630                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9631                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9632                                       0, 5, 2);
9633         }
9634         return ret;
9635 }
9636
9637 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9638                          unsigned int val)
9639 {
9640         return t4_cim_write(adap, addr, 1, &val);
9641 }
9642
9643 /**
9644  *      t4_cim_read_la - read CIM LA capture buffer
9645  *      @adap: the adapter
9646  *      @la_buf: where to store the LA data
9647  *      @wrptr: the HW write pointer within the capture buffer
9648  *
9649  *      Reads the contents of the CIM LA buffer with the most recent entry at
9650  *      the end of the returned data and with the entry at @wrptr first.
9651  *      We try to leave the LA in the running state we find it in.
9652  */
9653 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9654 {
9655         int i, ret;
9656         unsigned int cfg, val, idx;
9657
9658         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9659         if (ret)
9660                 return ret;
9661
9662         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9663                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9664                 if (ret)
9665                         return ret;
9666         }
9667
9668         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9669         if (ret)
9670                 goto restart;
9671
9672         idx = UPDBGLAWRPTR_G(val);
9673         if (wrptr)
9674                 *wrptr = idx;
9675
9676         for (i = 0; i < adap->params.cim_la_size; i++) {
9677                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9678                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9679                 if (ret)
9680                         break;
9681                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9682                 if (ret)
9683                         break;
9684                 if (val & UPDBGLARDEN_F) {
9685                         ret = -ETIMEDOUT;
9686                         break;
9687                 }
9688                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9689                 if (ret)
9690                         break;
9691
9692                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9693                  * identify the 32-bit portion of the full 312-bit data
9694                  */
9695                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9696                         idx = (idx & 0xff0) + 0x10;
9697                 else
9698                         idx++;
9699                 /* address can't exceed 0xfff */
9700                 idx &= UPDBGLARDPTR_M;
9701         }
9702 restart:
9703         if (cfg & UPDBGLAEN_F) {
9704                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9705                                       cfg & ~UPDBGLARDEN_F);
9706                 if (!ret)
9707                         ret = r;
9708         }
9709         return ret;
9710 }
9711
9712 /**
9713  *      t4_tp_read_la - read TP LA capture buffer
9714  *      @adap: the adapter
9715  *      @la_buf: where to store the LA data
9716  *      @wrptr: the HW write pointer within the capture buffer
9717  *
9718  *      Reads the contents of the TP LA buffer with the most recent entry at
9719  *      the end of the returned data and with the entry at @wrptr first.
9720  *      We leave the LA in the running state we find it in.
9721  */
9722 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9723 {
9724         bool last_incomplete;
9725         unsigned int i, cfg, val, idx;
9726
9727         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9728         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9729                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9730                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9731
9732         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9733         idx = DBGLAWPTR_G(val);
9734         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9735         if (last_incomplete)
9736                 idx = (idx + 1) & DBGLARPTR_M;
9737         if (wrptr)
9738                 *wrptr = idx;
9739
9740         val &= 0xffff;
9741         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9742         val |= adap->params.tp.la_mask;
9743
9744         for (i = 0; i < TPLA_SIZE; i++) {
9745                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9746                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9747                 idx = (idx + 1) & DBGLARPTR_M;
9748         }
9749
9750         /* Wipe out last entry if it isn't valid */
9751         if (last_incomplete)
9752                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9753
9754         if (cfg & DBGLAENABLE_F)                    /* restore running state */
9755                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9756                              cfg | adap->params.tp.la_mask);
9757 }
9758
9759 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9760  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9761  * state for more than the Warning Threshold then we'll issue a warning about
9762  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9763  * appears to be hung every Warning Repeat second till the situation clears.
9764  * If the situation clears, we'll note that as well.
9765  */
9766 #define SGE_IDMA_WARN_THRESH 1
9767 #define SGE_IDMA_WARN_REPEAT 300
9768
9769 /**
9770  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9771  *      @adapter: the adapter
9772  *      @idma: the adapter IDMA Monitor state
9773  *
9774  *      Initialize the state of an SGE Ingress DMA Monitor.
9775  */
9776 void t4_idma_monitor_init(struct adapter *adapter,
9777                           struct sge_idma_monitor_state *idma)
9778 {
9779         /* Initialize the state variables for detecting an SGE Ingress DMA
9780          * hang.  The SGE has internal counters which count up on each clock
9781          * tick whenever the SGE finds its Ingress DMA State Engines in the
9782          * same state they were on the previous clock tick.  The clock used is
9783          * the Core Clock so we have a limit on the maximum "time" they can
9784          * record; typically a very small number of seconds.  For instance,
9785          * with a 600MHz Core Clock, we can only count up to a bit more than
9786          * 7s.  So we'll synthesize a larger counter in order to not run the
9787          * risk of having the "timers" overflow and give us the flexibility to
9788          * maintain a Hung SGE State Machine of our own which operates across
9789          * a longer time frame.
9790          */
9791         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9792         idma->idma_stalled[0] = 0;
9793         idma->idma_stalled[1] = 0;
9794 }
9795
9796 /**
9797  *      t4_idma_monitor - monitor SGE Ingress DMA state
9798  *      @adapter: the adapter
9799  *      @idma: the adapter IDMA Monitor state
9800  *      @hz: number of ticks/second
9801  *      @ticks: number of ticks since the last IDMA Monitor call
9802  */
9803 void t4_idma_monitor(struct adapter *adapter,
9804                      struct sge_idma_monitor_state *idma,
9805                      int hz, int ticks)
9806 {
9807         int i, idma_same_state_cnt[2];
9808
9809          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9810           * are counters inside the SGE which count up on each clock when the
9811           * SGE finds its Ingress DMA State Engines in the same states they
9812           * were in the previous clock.  The counters will peg out at
9813           * 0xffffffff without wrapping around so once they pass the 1s
9814           * threshold they'll stay above that till the IDMA state changes.
9815           */
9816         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9817         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9818         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9819
9820         for (i = 0; i < 2; i++) {
9821                 u32 debug0, debug11;
9822
9823                 /* If the Ingress DMA Same State Counter ("timer") is less
9824                  * than 1s, then we can reset our synthesized Stall Timer and
9825                  * continue.  If we have previously emitted warnings about a
9826                  * potential stalled Ingress Queue, issue a note indicating
9827                  * that the Ingress Queue has resumed forward progress.
9828                  */
9829                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9830                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9831                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9832                                          "resumed after %d seconds\n",
9833                                          i, idma->idma_qid[i],
9834                                          idma->idma_stalled[i] / hz);
9835                         idma->idma_stalled[i] = 0;
9836                         continue;
9837                 }
9838
9839                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9840                  * domain.  The first time we get here it'll be because we
9841                  * passed the 1s Threshold; each additional time it'll be
9842                  * because the RX Timer Callback is being fired on its regular
9843                  * schedule.
9844                  *
9845                  * If the stall is below our Potential Hung Ingress Queue
9846                  * Warning Threshold, continue.
9847                  */
9848                 if (idma->idma_stalled[i] == 0) {
9849                         idma->idma_stalled[i] = hz;
9850                         idma->idma_warn[i] = 0;
9851                 } else {
9852                         idma->idma_stalled[i] += ticks;
9853                         idma->idma_warn[i] -= ticks;
9854                 }
9855
9856                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9857                         continue;
9858
9859                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9860                  */
9861                 if (idma->idma_warn[i] > 0)
9862                         continue;
9863                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9864
9865                 /* Read and save the SGE IDMA State and Queue ID information.
9866                  * We do this every time in case it changes across time ...
9867                  * can't be too careful ...
9868                  */
9869                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9870                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9871                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9872
9873                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9874                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9875                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9876
9877                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9878                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9879                          i, idma->idma_qid[i], idma->idma_state[i],
9880                          idma->idma_stalled[i] / hz,
9881                          debug0, debug11);
9882                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9883         }
9884 }
9885
9886 /**
9887  *      t4_load_cfg - download config file
9888  *      @adap: the adapter
9889  *      @cfg_data: the cfg text file to write
9890  *      @size: text file size
9891  *
9892  *      Write the supplied config text file to the card's serial flash.
9893  */
9894 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9895 {
9896         int ret, i, n, cfg_addr;
9897         unsigned int addr;
9898         unsigned int flash_cfg_start_sec;
9899         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9900
9901         cfg_addr = t4_flash_cfg_addr(adap);
9902         if (cfg_addr < 0)
9903                 return cfg_addr;
9904
9905         addr = cfg_addr;
9906         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9907
9908         if (size > FLASH_CFG_MAX_SIZE) {
9909                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9910                         FLASH_CFG_MAX_SIZE);
9911                 return -EFBIG;
9912         }
9913
9914         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
9915                          sf_sec_size);
9916         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9917                                      flash_cfg_start_sec + i - 1);
9918         /* If size == 0 then we're simply erasing the FLASH sectors associated
9919          * with the on-adapter Firmware Configuration File.
9920          */
9921         if (ret || size == 0)
9922                 goto out;
9923
9924         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9925         for (i = 0; i < size; i += SF_PAGE_SIZE) {
9926                 if ((size - i) <  SF_PAGE_SIZE)
9927                         n = size - i;
9928                 else
9929                         n = SF_PAGE_SIZE;
9930                 ret = t4_write_flash(adap, addr, n, cfg_data);
9931                 if (ret)
9932                         goto out;
9933
9934                 addr += SF_PAGE_SIZE;
9935                 cfg_data += SF_PAGE_SIZE;
9936         }
9937
9938 out:
9939         if (ret)
9940                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9941                         (size == 0 ? "clear" : "download"), ret);
9942         return ret;
9943 }
9944
9945 /**
9946  *      t4_set_vf_mac - Set MAC address for the specified VF
9947  *      @adapter: The adapter
9948  *      @vf: one of the VFs instantiated by the specified PF
9949  *      @naddr: the number of MAC addresses
9950  *      @addr: the MAC address(es) to be set to the specified VF
9951  */
9952 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9953                       unsigned int naddr, u8 *addr)
9954 {
9955         struct fw_acl_mac_cmd cmd;
9956
9957         memset(&cmd, 0, sizeof(cmd));
9958         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9959                                     FW_CMD_REQUEST_F |
9960                                     FW_CMD_WRITE_F |
9961                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9962                                     FW_ACL_MAC_CMD_VFN_V(vf));
9963
9964         /* Note: Do not enable the ACL */
9965         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9966         cmd.nmac = naddr;
9967
9968         switch (adapter->pf) {
9969         case 3:
9970                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9971                 break;
9972         case 2:
9973                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9974                 break;
9975         case 1:
9976                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9977                 break;
9978         case 0:
9979                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9980                 break;
9981         }
9982
9983         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9984 }
9985
9986 /**
9987  * t4_read_pace_tbl - read the pace table
9988  * @adap: the adapter
9989  * @pace_vals: holds the returned values
9990  *
9991  * Returns the values of TP's pace table in microseconds.
9992  */
9993 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9994 {
9995         unsigned int i, v;
9996
9997         for (i = 0; i < NTX_SCHED; i++) {
9998                 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
9999                 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10000                 pace_vals[i] = dack_ticks_to_usec(adap, v);
10001         }
10002 }
10003
10004 /**
10005  * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10006  * @adap: the adapter
10007  * @sched: the scheduler index
10008  * @kbps: the byte rate in Kbps
10009  * @ipg: the interpacket delay in tenths of nanoseconds
10010  * @sleep_ok: if true we may sleep while awaiting command completion
10011  *
10012  * Return the current configuration of a HW Tx scheduler.
10013  */
10014 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10015                      unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10016 {
10017         unsigned int v, addr, bpt, cpt;
10018
10019         if (kbps) {
10020                 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10021                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10022                 if (sched & 1)
10023                         v >>= 16;
10024                 bpt = (v >> 8) & 0xff;
10025                 cpt = v & 0xff;
10026                 if (!cpt) {
10027                         *kbps = 0;      /* scheduler disabled */
10028                 } else {
10029                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10030                         *kbps = (v * bpt) / 125;
10031                 }
10032         }
10033         if (ipg) {
10034                 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10035                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10036                 if (sched & 1)
10037                         v >>= 16;
10038                 v &= 0xffff;
10039                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10040         }
10041 }
10042
10043 /* t4_sge_ctxt_rd - read an SGE context through FW
10044  * @adap: the adapter
10045  * @mbox: mailbox to use for the FW command
10046  * @cid: the context id
10047  * @ctype: the context type
10048  * @data: where to store the context data
10049  *
10050  * Issues a FW command through the given mailbox to read an SGE context.
10051  */
10052 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10053                    enum ctxt_type ctype, u32 *data)
10054 {
10055         struct fw_ldst_cmd c;
10056         int ret;
10057
10058         if (ctype == CTXT_FLM)
10059                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10060         else
10061                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10062
10063         memset(&c, 0, sizeof(c));
10064         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10065                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
10066                                         FW_LDST_CMD_ADDRSPACE_V(ret));
10067         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10068         c.u.idctxt.physid = cpu_to_be32(cid);
10069
10070         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10071         if (ret == 0) {
10072                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10073                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10074                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10075                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10076                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10077                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10078         }
10079         return ret;
10080 }
10081
10082 /**
10083  * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10084  * @adap: the adapter
10085  * @cid: the context id
10086  * @ctype: the context type
10087  * @data: where to store the context data
10088  *
10089  * Reads an SGE context directly, bypassing FW.  This is only for
10090  * debugging when FW is unavailable.
10091  */
10092 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10093                       enum ctxt_type ctype, u32 *data)
10094 {
10095         int i, ret;
10096
10097         t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10098         ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10099         if (!ret)
10100                 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10101                         *data++ = t4_read_reg(adap, i);
10102         return ret;
10103 }
10104
10105 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10106                     int rateunit, int ratemode, int channel, int class,
10107                     int minrate, int maxrate, int weight, int pktsize)
10108 {
10109         struct fw_sched_cmd cmd;
10110
10111         memset(&cmd, 0, sizeof(cmd));
10112         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10113                                       FW_CMD_REQUEST_F |
10114                                       FW_CMD_WRITE_F);
10115         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10116
10117         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10118         cmd.u.params.type = type;
10119         cmd.u.params.level = level;
10120         cmd.u.params.mode = mode;
10121         cmd.u.params.ch = channel;
10122         cmd.u.params.cl = class;
10123         cmd.u.params.unit = rateunit;
10124         cmd.u.params.rate = ratemode;
10125         cmd.u.params.min = cpu_to_be32(minrate);
10126         cmd.u.params.max = cpu_to_be32(maxrate);
10127         cmd.u.params.weight = cpu_to_be16(weight);
10128         cmd.u.params.pktsize = cpu_to_be16(pktsize);
10129
10130         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10131                                NULL, 1);
10132 }
10133
10134 /**
10135  *      t4_i2c_rd - read I2C data from adapter
10136  *      @adap: the adapter
10137  *      @port: Port number if per-port device; <0 if not
10138  *      @devid: per-port device ID or absolute device ID
10139  *      @offset: byte offset into device I2C space
10140  *      @len: byte length of I2C space data
10141  *      @buf: buffer in which to return I2C data
10142  *
10143  *      Reads the I2C data from the indicated device and location.
10144  */
10145 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10146               unsigned int devid, unsigned int offset,
10147               unsigned int len, u8 *buf)
10148 {
10149         struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10150         unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10151         int ret = 0;
10152
10153         if (len > I2C_PAGE_SIZE)
10154                 return -EINVAL;
10155
10156         /* Dont allow reads that spans multiple pages */
10157         if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10158                 return -EINVAL;
10159
10160         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10161         ldst_cmd.op_to_addrspace =
10162                 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10163                             FW_CMD_REQUEST_F |
10164                             FW_CMD_READ_F |
10165                             FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10166         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10167         ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10168         ldst_cmd.u.i2c.did = devid;
10169
10170         while (len > 0) {
10171                 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10172
10173                 ldst_cmd.u.i2c.boffset = offset;
10174                 ldst_cmd.u.i2c.blen = i2c_len;
10175
10176                 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10177                                  &ldst_rpl);
10178                 if (ret)
10179                         break;
10180
10181                 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10182                 offset += i2c_len;
10183                 buf += i2c_len;
10184                 len -= i2c_len;
10185         }
10186
10187         return ret;
10188 }
10189
10190 /**
10191  *      t4_set_vlan_acl - Set a VLAN id for the specified VF
10192  *      @adapter: the adapter
10193  *      @mbox: mailbox to use for the FW command
10194  *      @vf: one of the VFs instantiated by the specified PF
10195  *      @vlan: The vlanid to be set
10196  */
10197 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10198                     u16 vlan)
10199 {
10200         struct fw_acl_vlan_cmd vlan_cmd;
10201         unsigned int enable;
10202
10203         enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10204         memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10205         vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10206                                          FW_CMD_REQUEST_F |
10207                                          FW_CMD_WRITE_F |
10208                                          FW_CMD_EXEC_F |
10209                                          FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10210                                          FW_ACL_VLAN_CMD_VFN_V(vf));
10211         vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10212         /* Drop all packets that donot match vlan id */
10213         vlan_cmd.dropnovlan_fm = FW_ACL_VLAN_CMD_FM_F;
10214         if (enable != 0) {
10215                 vlan_cmd.nvlan = 1;
10216                 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10217         }
10218
10219         return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10220 }