drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         struct mbox_list entry;
 288         u16 access = 0;
 289         u16 execute = 0;
 290         u32 v;
 291         u64 res;
 292         int i, ms, delay_idx, ret;
 293         const __be64 *p = cmd;
 294         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 295         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 296         __be64 cmd_rpl[MBOX_LEN / 8];
 297         u32 pcie_fw;
 298
 299         if ((size & 15) || size > MBOX_LEN)
 300                 return -EINVAL;
 301
 302         /*
 303          * If the device is off-line, as in EEH, commands will time out.
 304          * Fail them early so we don't waste time waiting.
 305          */
 306         if (adap->pdev->error_state != pci_channel_io_normal)
 307                 return -EIO;
 308
 309         /* If we have a negative timeout, that implies that we can't sleep. */
 310         if (timeout < 0) {
 311                 sleep_ok = false;
 312                 timeout = -timeout;
 313         }
 314
 315         /* Queue ourselves onto the mailbox access list.  When our entry is at
 316          * the front of the list, we have rights to access the mailbox.  So we
 317          * wait [for a while] till we're at the front [or bail out with an
 318          * EBUSY] ...
 319          */
 320         spin_lock(&adap->mbox_lock);
 321         list_add_tail(&entry.list, &adap->mlist.list);
 322         spin_unlock(&adap->mbox_lock);
 323
 324         delay_idx = 0;
 325         ms = delay[0];
 326
 327         for (i = 0; ; i += ms) {
 328                 /* If we've waited too long, return a busy indication.  This
 329                  * really ought to be based on our initial position in the
 330                  * mailbox access list but this is a start.  We very rearely
 331                  * contend on access to the mailbox ...
 332                  */
 333                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 334                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 335                         spin_lock(&adap->mbox_lock);
 336                         list_del(&entry.list);
 337                         spin_unlock(&adap->mbox_lock);
 338                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 339                         t4_record_mbox(adap, cmd, size, access, ret);
 340                         return ret;
 341                 }
 342
 343                 /* If we're at the head, break out and start the mailbox
 344                  * protocol.
 345                  */
 346                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 347                                      list) == &entry)
 348                         break;
 349
 350                 /* Delay for a bit before checking again ... */
 351                 if (sleep_ok) {
 352                         ms = delay[delay_idx];  /* last element may repeat */
 353                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 354                                 delay_idx++;
 355                         msleep(ms);
 356                 } else {
 357                         mdelay(ms);
 358                 }
 359         }
 360
 361         /* Loop trying to get ownership of the mailbox.  Return an error
 362          * if we can't gain ownership.
 363          */
 364         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 365         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 366                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         if (v != MBOX_OWNER_DRV) {
 368                 spin_lock(&adap->mbox_lock);
 369                 list_del(&entry.list);
 370                 spin_unlock(&adap->mbox_lock);
 371                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 372                 t4_record_mbox(adap, cmd, size, access, ret);
 373                 return ret;
 374         }
 375
 376         /* Copy in the new mailbox command and send it on its way ... */
 377         t4_record_mbox(adap, cmd, size, access, 0);
 378         for (i = 0; i < size; i += 8)
 379                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 380
 381         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 382         t4_read_reg(adap, ctl_reg);          /* flush write */
 383
 384         delay_idx = 0;
 385         ms = delay[0];
 386
 387         for (i = 0;
 388              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 389              i < timeout;
 390              i += ms) {
 391                 if (sleep_ok) {
 392                         ms = delay[delay_idx];  /* last element may repeat */
 393                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 394                                 delay_idx++;
 395                         msleep(ms);
 396                 } else
 397                         mdelay(ms);
 398
 399                 v = t4_read_reg(adap, ctl_reg);
 400                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 401                         if (!(v & MBMSGVALID_F)) {
 402                                 t4_write_reg(adap, ctl_reg, 0);
 403                                 continue;
 404                         }
 405
 406                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 407                         res = be64_to_cpu(cmd_rpl[0]);
 408
 409                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 410                                 fw_asrt(adap, data_reg);
 411                                 res = FW_CMD_RETVAL_V(EIO);
 412                         } else if (rpl) {
 413                                 memcpy(rpl, cmd_rpl, size);
 414                         }
 415
 416                         t4_write_reg(adap, ctl_reg, 0);
 417
 418                         execute = i + ms;
 419                         t4_record_mbox(adap, cmd_rpl,
 420                                        MBOX_LEN, access, execute);
 421                         spin_lock(&adap->mbox_lock);
 422                         list_del(&entry.list);
 423                         spin_unlock(&adap->mbox_lock);
 424                         return -FW_CMD_RETVAL_G((int)res);
 425                 }
 426         }
 427
 428         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 429         t4_record_mbox(adap, cmd, size, access, ret);
 430         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 431                 *(const u8 *)cmd, mbox);
 432         t4_report_fw_error(adap);
 433         spin_lock(&adap->mbox_lock);
 434         list_del(&entry.list);
 435         spin_unlock(&adap->mbox_lock);
 436         t4_fatal_err(adap);
 437         return ret;
 438 }
 439
 440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 441                     void *rpl, bool sleep_ok)
 442 {
 443         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 444                                        FW_CMD_MAX_TIMEOUT);
 445 }
 446
 447 static int t4_edc_err_read(struct adapter *adap, int idx)
 448 {
 449         u32 edc_ecc_err_addr_reg;
 450         u32 rdata_reg;
 451
 452         if (is_t4(adap->params.chip)) {
 453                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 454                 return 0;
 455         }
 456         if (idx != 0 && idx != 1) {
 457                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 458                 return 0;
 459         }
 460
 461         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 462         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 463
 464         CH_WARN(adap,
 465                 "edc%d err addr 0x%x: 0x%x.\n",
 466                 idx, edc_ecc_err_addr_reg,
 467                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 468         CH_WARN(adap,
 469                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 470                 rdata_reg,
 471                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 472                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 486  *      @adap: the adapter
 487  *      @win: PCI-E Memory Window to use
 488  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 489  *      @addr: address within indicated memory type
 490  *      @len: amount of memory to transfer
 491  *      @hbuf: host memory buffer
 492  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 493  *
 494  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 495  *      firmware memory address and host buffer must be aligned on 32-bit
 496  *      boudaries; the length may be arbitrary.  The memory is transferred as
 497  *      a raw byte sequence from/to the firmware's memory.  If this memory
 498  *      contains data structures which contain multi-byte integers, it's the
 499  *      caller's responsibility to perform appropriate byte order conversions.
 500  */
 501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 502                  u32 len, void *hbuf, int dir)
 503 {
 504         u32 pos, offset, resid, memoffset;
 505         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 506         u32 *buf;
 507
 508         /* Argument sanity checks ...
 509          */
 510         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 511                 return -EINVAL;
 512         buf = (u32 *)hbuf;
 513
 514         /* It's convenient to be able to handle lengths which aren't a
 515          * multiple of 32-bits because we often end up transferring files to
 516          * the firmware.  So we'll handle that by normalizing the length here
 517          * and then handling any residual transfer at the end.
 518          */
 519         resid = len & 0x3;
 520         len -= resid;
 521
 522         /* Offset into the region of memory which is being accessed
 523          * MEM_EDC0 = 0
 524          * MEM_EDC1 = 1
 525          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 526          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 527          */
 528         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 529         if (mtype != MEM_MC1)
 530                 memoffset = (mtype * (edc_size * 1024 * 1024));
 531         else {
 532                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 533                                                       MA_EXT_MEMORY0_BAR_A));
 534                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 535         }
 536
 537         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 538         addr = addr + memoffset;
 539
 540         /* Each PCI-E Memory Window is programmed with a window size -- or
 541          * "aperture" -- which controls the granularity of its mapping onto
 542          * adapter memory.  We need to grab that aperture in order to know
 543          * how to use the specified window.  The window is also programmed
 544          * with the base address of the Memory Window in BAR0's address
 545          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 546          * the address is relative to BAR0.
 547          */
 548         mem_reg = t4_read_reg(adap,
 549                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 550                                                   win));
 551         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 552         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 553         if (is_t4(adap->params.chip))
 554                 mem_base -= adap->t4_bar0;
 555         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 556
 557         /* Calculate our initial PCI-E Memory Window Position and Offset into
 558          * that Window.
 559          */
 560         pos = addr & ~(mem_aperture-1);
 561         offset = addr - pos;
 562
 563         /* Set up initial PCI-E Memory Window to cover the start of our
 564          * transfer.  (Read it back to ensure that changes propagate before we
 565          * attempt to use the new value.)
 566          */
 567         t4_write_reg(adap,
 568                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 569                      pos | win_pf);
 570         t4_read_reg(adap,
 571                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 572
 573         /* Transfer data to/from the adapter as long as there's an integral
 574          * number of 32-bit transfers to complete.
 575          *
 576          * A note on Endianness issues:
 577          *
 578          * The "register" reads and writes below from/to the PCI-E Memory
 579          * Window invoke the standard adapter Big-Endian to PCI-E Link
 580          * Little-Endian "swizzel."  As a result, if we have the following
 581          * data in adapter memory:
 582          *
 583          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 584          *     Address:      i+0  i+1  i+2  i+3
 585          *
 586          * Then a read of the adapter memory via the PCI-E Memory Window
 587          * will yield:
 588          *
 589          *     x = readl(i)
 590          *         31                  0
 591          *         [ b3 | b2 | b1 | b0 ]
 592          *
 593          * If this value is stored into local memory on a Little-Endian system
 594          * it will show up correctly in local memory as:
 595          *
 596          *     ( ..., b0, b1, b2, b3, ... )
 597          *
 598          * But on a Big-Endian system, the store will show up in memory
 599          * incorrectly swizzled as:
 600          *
 601          *     ( ..., b3, b2, b1, b0, ... )
 602          *
 603          * So we need to account for this in the reads and writes to the
 604          * PCI-E Memory Window below by undoing the register read/write
 605          * swizzels.
 606          */
 607         while (len > 0) {
 608                 if (dir == T4_MEMORY_READ)
 609                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 610                                                 mem_base + offset));
 611                 else
 612                         t4_write_reg(adap, mem_base + offset,
 613                                      (__force u32)cpu_to_le32(*buf++));
 614                 offset += sizeof(__be32);
 615                 len -= sizeof(__be32);
 616
 617                 /* If we've reached the end of our current window aperture,
 618                  * move the PCI-E Memory Window on to the next.  Note that
 619                  * doing this here after "len" may be 0 allows us to set up
 620                  * the PCI-E Memory Window for a possible final residual
 621                  * transfer below ...
 622                  */
 623                 if (offset == mem_aperture) {
 624                         pos += mem_aperture;
 625                         offset = 0;
 626                         t4_write_reg(adap,
 627                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 628                                                     win), pos | win_pf);
 629                         t4_read_reg(adap,
 630                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 631                                                     win));
 632                 }
 633         }
 634
 635         /* If the original transfer had a length which wasn't a multiple of
 636          * 32-bits, now's where we need to finish off the transfer of the
 637          * residual amount.  The PCI-E Memory Window has already been moved
 638          * above (if necessary) to cover this final transfer.
 639          */
 640         if (resid) {
 641                 union {
 642                         u32 word;
 643                         char byte[4];
 644                 } last;
 645                 unsigned char *bp;
 646                 int i;
 647
 648                 if (dir == T4_MEMORY_READ) {
 649                         last.word = le32_to_cpu(
 650                                         (__force __le32)t4_read_reg(adap,
 651                                                 mem_base + offset));
 652                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 653                                 bp[i] = last.byte[i];
 654                 } else {
 655                         last.word = *buf;
 656                         for (i = resid; i < 4; i++)
 657                                 last.byte[i] = 0;
 658                         t4_write_reg(adap, mem_base + offset,
 659                                      (__force u32)cpu_to_le32(last.word));
 660                 }
 661         }
 662
 663         return 0;
 664 }
 665
 666 /* Return the specified PCI-E Configuration Space register from our Physical
 667  * Function.  We try first via a Firmware LDST Command since we prefer to let
 668  * the firmware own all of these registers, but if that fails we go for it
 669  * directly ourselves.
 670  */
 671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 672 {
 673         u32 val, ldst_addrspace;
 674
 675         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 676          * retrieve the specified PCI-E Configuration Space register.
 677          */
 678         struct fw_ldst_cmd ldst_cmd;
 679         int ret;
 680
 681         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 682         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 683         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 684                                                FW_CMD_REQUEST_F |
 685                                                FW_CMD_READ_F |
 686                                                ldst_addrspace);
 687         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 688         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 689         ldst_cmd.u.pcie.ctrl_to_fn =
 690                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 691         ldst_cmd.u.pcie.r = reg;
 692
 693         /* If the LDST Command succeeds, return the result, otherwise
 694          * fall through to reading it directly ourselves ...
 695          */
 696         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 697                          &ldst_cmd);
 698         if (ret == 0)
 699                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 700         else
 701                 /* Read the desired Configuration Space register via the PCI-E
 702                  * Backdoor mechanism.
 703                  */
 704                 t4_hw_pci_read_cfg4(adap, reg, &val);
 705         return val;
 706 }
 707
 708 /* Get the window based on base passed to it.
 709  * Window aperture is currently unhandled, but there is no use case for it
 710  * right now
 711  */
 712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 713                          u32 memwin_base)
 714 {
 715         u32 ret;
 716
 717         if (is_t4(adap->params.chip)) {
 718                 u32 bar0;
 719
 720                 /* Truncation intentional: we only read the bottom 32-bits of
 721                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 722                  * mechanism to read BAR0 instead of using
 723                  * pci_resource_start() because we could be operating from
 724                  * within a Virtual Machine which is trapping our accesses to
 725                  * our Configuration Space and we need to set up the PCI-E
 726                  * Memory Window decoders with the actual addresses which will
 727                  * be coming across the PCI-E link.
 728                  */
 729                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 730                 bar0 &= pci_mask;
 731                 adap->t4_bar0 = bar0;
 732
 733                 ret = bar0 + memwin_base;
 734         } else {
 735                 /* For T5, only relative offset inside the PCIe BAR is passed */
 736                 ret = memwin_base;
 737         }
 738         return ret;
 739 }
 740
 741 /* Get the default utility window (win0) used by everyone */
 742 u32 t4_get_util_window(struct adapter *adap)
 743 {
 744         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 745                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 746 }
 747
 748 /* Set up memory window for accessing adapter memory ranges.  (Read
 749  * back MA register to ensure that changes propagate before we attempt
 750  * to use the new values.)
 751  */
 752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 753 {
 754         t4_write_reg(adap,
 755                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 756                      memwin_base | BIR_V(0) |
 757                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 758         t4_read_reg(adap,
 759                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 760 }
 761
 762 /**
 763  *      t4_get_regs_len - return the size of the chips register set
 764  *      @adapter: the adapter
 765  *
 766  *      Returns the size of the chip's BAR0 register space.
 767  */
 768 unsigned int t4_get_regs_len(struct adapter *adapter)
 769 {
 770         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 771
 772         switch (chip_version) {
 773         case CHELSIO_T4:
 774                 return T4_REGMAP_SIZE;
 775
 776         case CHELSIO_T5:
 777         case CHELSIO_T6:
 778                 return T5_REGMAP_SIZE;
 779         }
 780
 781         dev_err(adapter->pdev_dev,
 782                 "Unsupported chip version %d\n", chip_version);
 783         return 0;
 784 }
 785
 786 /**
 787  *      t4_get_regs - read chip registers into provided buffer
 788  *      @adap: the adapter
 789  *      @buf: register buffer
 790  *      @buf_size: size (in bytes) of register buffer
 791  *
 792  *      If the provided register buffer isn't large enough for the chip's
 793  *      full register range, the register dump will be truncated to the
 794  *      register buffer's size.
 795  */
 796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 797 {
 798         static const unsigned int t4_reg_ranges[] = {
 799                 0x1008, 0x1108,
 800                 0x1180, 0x1184,
 801                 0x1190, 0x1194,
 802                 0x11a0, 0x11a4,
 803                 0x11b0, 0x11b4,
 804                 0x11fc, 0x123c,
 805                 0x1300, 0x173c,
 806                 0x1800, 0x18fc,
 807                 0x3000, 0x30d8,
 808                 0x30e0, 0x30e4,
 809                 0x30ec, 0x5910,
 810                 0x5920, 0x5924,
 811                 0x5960, 0x5960,
 812                 0x5968, 0x5968,
 813                 0x5970, 0x5970,
 814                 0x5978, 0x5978,
 815                 0x5980, 0x5980,
 816                 0x5988, 0x5988,
 817                 0x5990, 0x5990,
 818                 0x5998, 0x5998,
 819                 0x59a0, 0x59d4,
 820                 0x5a00, 0x5ae0,
 821                 0x5ae8, 0x5ae8,
 822                 0x5af0, 0x5af0,
 823                 0x5af8, 0x5af8,
 824                 0x6000, 0x6098,
 825                 0x6100, 0x6150,
 826                 0x6200, 0x6208,
 827                 0x6240, 0x6248,
 828                 0x6280, 0x62b0,
 829                 0x62c0, 0x6338,
 830                 0x6370, 0x638c,
 831                 0x6400, 0x643c,
 832                 0x6500, 0x6524,
 833                 0x6a00, 0x6a04,
 834                 0x6a14, 0x6a38,
 835                 0x6a60, 0x6a70,
 836                 0x6a78, 0x6a78,
 837                 0x6b00, 0x6b0c,
 838                 0x6b1c, 0x6b84,
 839                 0x6bf0, 0x6bf8,
 840                 0x6c00, 0x6c0c,
 841                 0x6c1c, 0x6c84,
 842                 0x6cf0, 0x6cf8,
 843                 0x6d00, 0x6d0c,
 844                 0x6d1c, 0x6d84,
 845                 0x6df0, 0x6df8,
 846                 0x6e00, 0x6e0c,
 847                 0x6e1c, 0x6e84,
 848                 0x6ef0, 0x6ef8,
 849                 0x6f00, 0x6f0c,
 850                 0x6f1c, 0x6f84,
 851                 0x6ff0, 0x6ff8,
 852                 0x7000, 0x700c,
 853                 0x701c, 0x7084,
 854                 0x70f0, 0x70f8,
 855                 0x7100, 0x710c,
 856                 0x711c, 0x7184,
 857                 0x71f0, 0x71f8,
 858                 0x7200, 0x720c,
 859                 0x721c, 0x7284,
 860                 0x72f0, 0x72f8,
 861                 0x7300, 0x730c,
 862                 0x731c, 0x7384,
 863                 0x73f0, 0x73f8,
 864                 0x7400, 0x7450,
 865                 0x7500, 0x7530,
 866                 0x7600, 0x760c,
 867                 0x7614, 0x761c,
 868                 0x7680, 0x76cc,
 869                 0x7700, 0x7798,
 870                 0x77c0, 0x77fc,
 871                 0x7900, 0x79fc,
 872                 0x7b00, 0x7b58,
 873                 0x7b60, 0x7b84,
 874                 0x7b8c, 0x7c38,
 875                 0x7d00, 0x7d38,
 876                 0x7d40, 0x7d80,
 877                 0x7d8c, 0x7ddc,
 878                 0x7de4, 0x7e04,
 879                 0x7e10, 0x7e1c,
 880                 0x7e24, 0x7e38,
 881                 0x7e40, 0x7e44,
 882                 0x7e4c, 0x7e78,
 883                 0x7e80, 0x7ea4,
 884                 0x7eac, 0x7edc,
 885                 0x7ee8, 0x7efc,
 886                 0x8dc0, 0x8e04,
 887                 0x8e10, 0x8e1c,
 888                 0x8e30, 0x8e78,
 889                 0x8ea0, 0x8eb8,
 890                 0x8ec0, 0x8f6c,
 891                 0x8fc0, 0x9008,
 892                 0x9010, 0x9058,
 893                 0x9060, 0x9060,
 894                 0x9068, 0x9074,
 895                 0x90fc, 0x90fc,
 896                 0x9400, 0x9408,
 897                 0x9410, 0x9458,
 898                 0x9600, 0x9600,
 899                 0x9608, 0x9638,
 900                 0x9640, 0x96bc,
 901                 0x9800, 0x9808,
 902                 0x9820, 0x983c,
 903                 0x9850, 0x9864,
 904                 0x9c00, 0x9c6c,
 905                 0x9c80, 0x9cec,
 906                 0x9d00, 0x9d6c,
 907                 0x9d80, 0x9dec,
 908                 0x9e00, 0x9e6c,
 909                 0x9e80, 0x9eec,
 910                 0x9f00, 0x9f6c,
 911                 0x9f80, 0x9fec,
 912                 0xd004, 0xd004,
 913                 0xd010, 0xd03c,
 914                 0xdfc0, 0xdfe0,
 915                 0xe000, 0xea7c,
 916                 0xf000, 0x11110,
 917                 0x11118, 0x11190,
 918                 0x19040, 0x1906c,
 919                 0x19078, 0x19080,
 920                 0x1908c, 0x190e4,
 921                 0x190f0, 0x190f8,
 922                 0x19100, 0x19110,
 923                 0x19120, 0x19124,
 924                 0x19150, 0x19194,
 925                 0x1919c, 0x191b0,
 926                 0x191d0, 0x191e8,
 927                 0x19238, 0x1924c,
 928                 0x193f8, 0x1943c,
 929                 0x1944c, 0x19474,
 930                 0x19490, 0x194e0,
 931                 0x194f0, 0x194f8,
 932                 0x19800, 0x19c08,
 933                 0x19c10, 0x19c90,
 934                 0x19ca0, 0x19ce4,
 935                 0x19cf0, 0x19d40,
 936                 0x19d50, 0x19d94,
 937                 0x19da0, 0x19de8,
 938                 0x19df0, 0x19e40,
 939                 0x19e50, 0x19e90,
 940                 0x19ea0, 0x19f4c,
 941                 0x1a000, 0x1a004,
 942                 0x1a010, 0x1a06c,
 943                 0x1a0b0, 0x1a0e4,
 944                 0x1a0ec, 0x1a0f4,
 945                 0x1a100, 0x1a108,
 946                 0x1a114, 0x1a120,
 947                 0x1a128, 0x1a130,
 948                 0x1a138, 0x1a138,
 949                 0x1a190, 0x1a1c4,
 950                 0x1a1fc, 0x1a1fc,
 951                 0x1e040, 0x1e04c,
 952                 0x1e284, 0x1e28c,
 953                 0x1e2c0, 0x1e2c0,
 954                 0x1e2e0, 0x1e2e0,
 955                 0x1e300, 0x1e384,
 956                 0x1e3c0, 0x1e3c8,
 957                 0x1e440, 0x1e44c,
 958                 0x1e684, 0x1e68c,
 959                 0x1e6c0, 0x1e6c0,
 960                 0x1e6e0, 0x1e6e0,
 961                 0x1e700, 0x1e784,
 962                 0x1e7c0, 0x1e7c8,
 963                 0x1e840, 0x1e84c,
 964                 0x1ea84, 0x1ea8c,
 965                 0x1eac0, 0x1eac0,
 966                 0x1eae0, 0x1eae0,
 967                 0x1eb00, 0x1eb84,
 968                 0x1ebc0, 0x1ebc8,
 969                 0x1ec40, 0x1ec4c,
 970                 0x1ee84, 0x1ee8c,
 971                 0x1eec0, 0x1eec0,
 972                 0x1eee0, 0x1eee0,
 973                 0x1ef00, 0x1ef84,
 974                 0x1efc0, 0x1efc8,
 975                 0x1f040, 0x1f04c,
 976                 0x1f284, 0x1f28c,
 977                 0x1f2c0, 0x1f2c0,
 978                 0x1f2e0, 0x1f2e0,
 979                 0x1f300, 0x1f384,
 980                 0x1f3c0, 0x1f3c8,
 981                 0x1f440, 0x1f44c,
 982                 0x1f684, 0x1f68c,
 983                 0x1f6c0, 0x1f6c0,
 984                 0x1f6e0, 0x1f6e0,
 985                 0x1f700, 0x1f784,
 986                 0x1f7c0, 0x1f7c8,
 987                 0x1f840, 0x1f84c,
 988                 0x1fa84, 0x1fa8c,
 989                 0x1fac0, 0x1fac0,
 990                 0x1fae0, 0x1fae0,
 991                 0x1fb00, 0x1fb84,
 992                 0x1fbc0, 0x1fbc8,
 993                 0x1fc40, 0x1fc4c,
 994                 0x1fe84, 0x1fe8c,
 995                 0x1fec0, 0x1fec0,
 996                 0x1fee0, 0x1fee0,
 997                 0x1ff00, 0x1ff84,
 998                 0x1ffc0, 0x1ffc8,
 999                 0x20000, 0x2002c,
1000                 0x20100, 0x2013c,
1001                 0x20190, 0x201a0,
1002                 0x201a8, 0x201b8,
1003                 0x201c4, 0x201c8,
1004                 0x20200, 0x20318,
1005                 0x20400, 0x204b4,
1006                 0x204c0, 0x20528,
1007                 0x20540, 0x20614,
1008                 0x21000, 0x21040,
1009                 0x2104c, 0x21060,
1010                 0x210c0, 0x210ec,
1011                 0x21200, 0x21268,
1012                 0x21270, 0x21284,
1013                 0x212fc, 0x21388,
1014                 0x21400, 0x21404,
1015                 0x21500, 0x21500,
1016                 0x21510, 0x21518,
1017                 0x2152c, 0x21530,
1018                 0x2153c, 0x2153c,
1019                 0x21550, 0x21554,
1020                 0x21600, 0x21600,
1021                 0x21608, 0x2161c,
1022                 0x21624, 0x21628,
1023                 0x21630, 0x21634,
1024                 0x2163c, 0x2163c,
1025                 0x21700, 0x2171c,
1026                 0x21780, 0x2178c,
1027                 0x21800, 0x21818,
1028                 0x21820, 0x21828,
1029                 0x21830, 0x21848,
1030                 0x21850, 0x21854,
1031                 0x21860, 0x21868,
1032                 0x21870, 0x21870,
1033                 0x21878, 0x21898,
1034                 0x218a0, 0x218a8,
1035                 0x218b0, 0x218c8,
1036                 0x218d0, 0x218d4,
1037                 0x218e0, 0x218e8,
1038                 0x218f0, 0x218f0,
1039                 0x218f8, 0x21a18,
1040                 0x21a20, 0x21a28,
1041                 0x21a30, 0x21a48,
1042                 0x21a50, 0x21a54,
1043                 0x21a60, 0x21a68,
1044                 0x21a70, 0x21a70,
1045                 0x21a78, 0x21a98,
1046                 0x21aa0, 0x21aa8,
1047                 0x21ab0, 0x21ac8,
1048                 0x21ad0, 0x21ad4,
1049                 0x21ae0, 0x21ae8,
1050                 0x21af0, 0x21af0,
1051                 0x21af8, 0x21c18,
1052                 0x21c20, 0x21c20,
1053                 0x21c28, 0x21c30,
1054                 0x21c38, 0x21c38,
1055                 0x21c80, 0x21c98,
1056                 0x21ca0, 0x21ca8,
1057                 0x21cb0, 0x21cc8,
1058                 0x21cd0, 0x21cd4,
1059                 0x21ce0, 0x21ce8,
1060                 0x21cf0, 0x21cf0,
1061                 0x21cf8, 0x21d7c,
1062                 0x21e00, 0x21e04,
1063                 0x22000, 0x2202c,
1064                 0x22100, 0x2213c,
1065                 0x22190, 0x221a0,
1066                 0x221a8, 0x221b8,
1067                 0x221c4, 0x221c8,
1068                 0x22200, 0x22318,
1069                 0x22400, 0x224b4,
1070                 0x224c0, 0x22528,
1071                 0x22540, 0x22614,
1072                 0x23000, 0x23040,
1073                 0x2304c, 0x23060,
1074                 0x230c0, 0x230ec,
1075                 0x23200, 0x23268,
1076                 0x23270, 0x23284,
1077                 0x232fc, 0x23388,
1078                 0x23400, 0x23404,
1079                 0x23500, 0x23500,
1080                 0x23510, 0x23518,
1081                 0x2352c, 0x23530,
1082                 0x2353c, 0x2353c,
1083                 0x23550, 0x23554,
1084                 0x23600, 0x23600,
1085                 0x23608, 0x2361c,
1086                 0x23624, 0x23628,
1087                 0x23630, 0x23634,
1088                 0x2363c, 0x2363c,
1089                 0x23700, 0x2371c,
1090                 0x23780, 0x2378c,
1091                 0x23800, 0x23818,
1092                 0x23820, 0x23828,
1093                 0x23830, 0x23848,
1094                 0x23850, 0x23854,
1095                 0x23860, 0x23868,
1096                 0x23870, 0x23870,
1097                 0x23878, 0x23898,
1098                 0x238a0, 0x238a8,
1099                 0x238b0, 0x238c8,
1100                 0x238d0, 0x238d4,
1101                 0x238e0, 0x238e8,
1102                 0x238f0, 0x238f0,
1103                 0x238f8, 0x23a18,
1104                 0x23a20, 0x23a28,
1105                 0x23a30, 0x23a48,
1106                 0x23a50, 0x23a54,
1107                 0x23a60, 0x23a68,
1108                 0x23a70, 0x23a70,
1109                 0x23a78, 0x23a98,
1110                 0x23aa0, 0x23aa8,
1111                 0x23ab0, 0x23ac8,
1112                 0x23ad0, 0x23ad4,
1113                 0x23ae0, 0x23ae8,
1114                 0x23af0, 0x23af0,
1115                 0x23af8, 0x23c18,
1116                 0x23c20, 0x23c20,
1117                 0x23c28, 0x23c30,
1118                 0x23c38, 0x23c38,
1119                 0x23c80, 0x23c98,
1120                 0x23ca0, 0x23ca8,
1121                 0x23cb0, 0x23cc8,
1122                 0x23cd0, 0x23cd4,
1123                 0x23ce0, 0x23ce8,
1124                 0x23cf0, 0x23cf0,
1125                 0x23cf8, 0x23d7c,
1126                 0x23e00, 0x23e04,
1127                 0x24000, 0x2402c,
1128                 0x24100, 0x2413c,
1129                 0x24190, 0x241a0,
1130                 0x241a8, 0x241b8,
1131                 0x241c4, 0x241c8,
1132                 0x24200, 0x24318,
1133                 0x24400, 0x244b4,
1134                 0x244c0, 0x24528,
1135                 0x24540, 0x24614,
1136                 0x25000, 0x25040,
1137                 0x2504c, 0x25060,
1138                 0x250c0, 0x250ec,
1139                 0x25200, 0x25268,
1140                 0x25270, 0x25284,
1141                 0x252fc, 0x25388,
1142                 0x25400, 0x25404,
1143                 0x25500, 0x25500,
1144                 0x25510, 0x25518,
1145                 0x2552c, 0x25530,
1146                 0x2553c, 0x2553c,
1147                 0x25550, 0x25554,
1148                 0x25600, 0x25600,
1149                 0x25608, 0x2561c,
1150                 0x25624, 0x25628,
1151                 0x25630, 0x25634,
1152                 0x2563c, 0x2563c,
1153                 0x25700, 0x2571c,
1154                 0x25780, 0x2578c,
1155                 0x25800, 0x25818,
1156                 0x25820, 0x25828,
1157                 0x25830, 0x25848,
1158                 0x25850, 0x25854,
1159                 0x25860, 0x25868,
1160                 0x25870, 0x25870,
1161                 0x25878, 0x25898,
1162                 0x258a0, 0x258a8,
1163                 0x258b0, 0x258c8,
1164                 0x258d0, 0x258d4,
1165                 0x258e0, 0x258e8,
1166                 0x258f0, 0x258f0,
1167                 0x258f8, 0x25a18,
1168                 0x25a20, 0x25a28,
1169                 0x25a30, 0x25a48,
1170                 0x25a50, 0x25a54,
1171                 0x25a60, 0x25a68,
1172                 0x25a70, 0x25a70,
1173                 0x25a78, 0x25a98,
1174                 0x25aa0, 0x25aa8,
1175                 0x25ab0, 0x25ac8,
1176                 0x25ad0, 0x25ad4,
1177                 0x25ae0, 0x25ae8,
1178                 0x25af0, 0x25af0,
1179                 0x25af8, 0x25c18,
1180                 0x25c20, 0x25c20,
1181                 0x25c28, 0x25c30,
1182                 0x25c38, 0x25c38,
1183                 0x25c80, 0x25c98,
1184                 0x25ca0, 0x25ca8,
1185                 0x25cb0, 0x25cc8,
1186                 0x25cd0, 0x25cd4,
1187                 0x25ce0, 0x25ce8,
1188                 0x25cf0, 0x25cf0,
1189                 0x25cf8, 0x25d7c,
1190                 0x25e00, 0x25e04,
1191                 0x26000, 0x2602c,
1192                 0x26100, 0x2613c,
1193                 0x26190, 0x261a0,
1194                 0x261a8, 0x261b8,
1195                 0x261c4, 0x261c8,
1196                 0x26200, 0x26318,
1197                 0x26400, 0x264b4,
1198                 0x264c0, 0x26528,
1199                 0x26540, 0x26614,
1200                 0x27000, 0x27040,
1201                 0x2704c, 0x27060,
1202                 0x270c0, 0x270ec,
1203                 0x27200, 0x27268,
1204                 0x27270, 0x27284,
1205                 0x272fc, 0x27388,
1206                 0x27400, 0x27404,
1207                 0x27500, 0x27500,
1208                 0x27510, 0x27518,
1209                 0x2752c, 0x27530,
1210                 0x2753c, 0x2753c,
1211                 0x27550, 0x27554,
1212                 0x27600, 0x27600,
1213                 0x27608, 0x2761c,
1214                 0x27624, 0x27628,
1215                 0x27630, 0x27634,
1216                 0x2763c, 0x2763c,
1217                 0x27700, 0x2771c,
1218                 0x27780, 0x2778c,
1219                 0x27800, 0x27818,
1220                 0x27820, 0x27828,
1221                 0x27830, 0x27848,
1222                 0x27850, 0x27854,
1223                 0x27860, 0x27868,
1224                 0x27870, 0x27870,
1225                 0x27878, 0x27898,
1226                 0x278a0, 0x278a8,
1227                 0x278b0, 0x278c8,
1228                 0x278d0, 0x278d4,
1229                 0x278e0, 0x278e8,
1230                 0x278f0, 0x278f0,
1231                 0x278f8, 0x27a18,
1232                 0x27a20, 0x27a28,
1233                 0x27a30, 0x27a48,
1234                 0x27a50, 0x27a54,
1235                 0x27a60, 0x27a68,
1236                 0x27a70, 0x27a70,
1237                 0x27a78, 0x27a98,
1238                 0x27aa0, 0x27aa8,
1239                 0x27ab0, 0x27ac8,
1240                 0x27ad0, 0x27ad4,
1241                 0x27ae0, 0x27ae8,
1242                 0x27af0, 0x27af0,
1243                 0x27af8, 0x27c18,
1244                 0x27c20, 0x27c20,
1245                 0x27c28, 0x27c30,
1246                 0x27c38, 0x27c38,
1247                 0x27c80, 0x27c98,
1248                 0x27ca0, 0x27ca8,
1249                 0x27cb0, 0x27cc8,
1250                 0x27cd0, 0x27cd4,
1251                 0x27ce0, 0x27ce8,
1252                 0x27cf0, 0x27cf0,
1253                 0x27cf8, 0x27d7c,
1254                 0x27e00, 0x27e04,
1255         };
1256
1257         static const unsigned int t5_reg_ranges[] = {
1258                 0x1008, 0x10c0,
1259                 0x10cc, 0x10f8,
1260                 0x1100, 0x1100,
1261                 0x110c, 0x1148,
1262                 0x1180, 0x1184,
1263                 0x1190, 0x1194,
1264                 0x11a0, 0x11a4,
1265                 0x11b0, 0x11b4,
1266                 0x11fc, 0x123c,
1267                 0x1280, 0x173c,
1268                 0x1800, 0x18fc,
1269                 0x3000, 0x3028,
1270                 0x3060, 0x30b0,
1271                 0x30b8, 0x30d8,
1272                 0x30e0, 0x30fc,
1273                 0x3140, 0x357c,
1274                 0x35a8, 0x35cc,
1275                 0x35ec, 0x35ec,
1276                 0x3600, 0x5624,
1277                 0x56cc, 0x56ec,
1278                 0x56f4, 0x5720,
1279                 0x5728, 0x575c,
1280                 0x580c, 0x5814,
1281                 0x5890, 0x589c,
1282                 0x58a4, 0x58ac,
1283                 0x58b8, 0x58bc,
1284                 0x5940, 0x59c8,
1285                 0x59d0, 0x59dc,
1286                 0x59fc, 0x5a18,
1287                 0x5a60, 0x5a70,
1288                 0x5a80, 0x5a9c,
1289                 0x5b94, 0x5bfc,
1290                 0x6000, 0x6020,
1291                 0x6028, 0x6040,
1292                 0x6058, 0x609c,
1293                 0x60a8, 0x614c,
1294                 0x7700, 0x7798,
1295                 0x77c0, 0x78fc,
1296                 0x7b00, 0x7b58,
1297                 0x7b60, 0x7b84,
1298                 0x7b8c, 0x7c54,
1299                 0x7d00, 0x7d38,
1300                 0x7d40, 0x7d80,
1301                 0x7d8c, 0x7ddc,
1302                 0x7de4, 0x7e04,
1303                 0x7e10, 0x7e1c,
1304                 0x7e24, 0x7e38,
1305                 0x7e40, 0x7e44,
1306                 0x7e4c, 0x7e78,
1307                 0x7e80, 0x7edc,
1308                 0x7ee8, 0x7efc,
1309                 0x8dc0, 0x8de0,
1310                 0x8df8, 0x8e04,
1311                 0x8e10, 0x8e84,
1312                 0x8ea0, 0x8f84,
1313                 0x8fc0, 0x9058,
1314                 0x9060, 0x9060,
1315                 0x9068, 0x90f8,
1316                 0x9400, 0x9408,
1317                 0x9410, 0x9470,
1318                 0x9600, 0x9600,
1319                 0x9608, 0x9638,
1320                 0x9640, 0x96f4,
1321                 0x9800, 0x9808,
1322                 0x9820, 0x983c,
1323                 0x9850, 0x9864,
1324                 0x9c00, 0x9c6c,
1325                 0x9c80, 0x9cec,
1326                 0x9d00, 0x9d6c,
1327                 0x9d80, 0x9dec,
1328                 0x9e00, 0x9e6c,
1329                 0x9e80, 0x9eec,
1330                 0x9f00, 0x9f6c,
1331                 0x9f80, 0xa020,
1332                 0xd004, 0xd004,
1333                 0xd010, 0xd03c,
1334                 0xdfc0, 0xdfe0,
1335                 0xe000, 0x1106c,
1336                 0x11074, 0x11088,
1337                 0x1109c, 0x1117c,
1338                 0x11190, 0x11204,
1339                 0x19040, 0x1906c,
1340                 0x19078, 0x19080,
1341                 0x1908c, 0x190e8,
1342                 0x190f0, 0x190f8,
1343                 0x19100, 0x19110,
1344                 0x19120, 0x19124,
1345                 0x19150, 0x19194,
1346                 0x1919c, 0x191b0,
1347                 0x191d0, 0x191e8,
1348                 0x19238, 0x19290,
1349                 0x193f8, 0x19428,
1350                 0x19430, 0x19444,
1351                 0x1944c, 0x1946c,
1352                 0x19474, 0x19474,
1353                 0x19490, 0x194cc,
1354                 0x194f0, 0x194f8,
1355                 0x19c00, 0x19c08,
1356                 0x19c10, 0x19c60,
1357                 0x19c94, 0x19ce4,
1358                 0x19cf0, 0x19d40,
1359                 0x19d50, 0x19d94,
1360                 0x19da0, 0x19de8,
1361                 0x19df0, 0x19e10,
1362                 0x19e50, 0x19e90,
1363                 0x19ea0, 0x19f24,
1364                 0x19f34, 0x19f34,
1365                 0x19f40, 0x19f50,
1366                 0x19f90, 0x19fb4,
1367                 0x19fc4, 0x19fe4,
1368                 0x1a000, 0x1a004,
1369                 0x1a010, 0x1a06c,
1370                 0x1a0b0, 0x1a0e4,
1371                 0x1a0ec, 0x1a0f8,
1372                 0x1a100, 0x1a108,
1373                 0x1a114, 0x1a120,
1374                 0x1a128, 0x1a130,
1375                 0x1a138, 0x1a138,
1376                 0x1a190, 0x1a1c4,
1377                 0x1a1fc, 0x1a1fc,
1378                 0x1e008, 0x1e00c,
1379                 0x1e040, 0x1e044,
1380                 0x1e04c, 0x1e04c,
1381                 0x1e284, 0x1e290,
1382                 0x1e2c0, 0x1e2c0,
1383                 0x1e2e0, 0x1e2e0,
1384                 0x1e300, 0x1e384,
1385                 0x1e3c0, 0x1e3c8,
1386                 0x1e408, 0x1e40c,
1387                 0x1e440, 0x1e444,
1388                 0x1e44c, 0x1e44c,
1389                 0x1e684, 0x1e690,
1390                 0x1e6c0, 0x1e6c0,
1391                 0x1e6e0, 0x1e6e0,
1392                 0x1e700, 0x1e784,
1393                 0x1e7c0, 0x1e7c8,
1394                 0x1e808, 0x1e80c,
1395                 0x1e840, 0x1e844,
1396                 0x1e84c, 0x1e84c,
1397                 0x1ea84, 0x1ea90,
1398                 0x1eac0, 0x1eac0,
1399                 0x1eae0, 0x1eae0,
1400                 0x1eb00, 0x1eb84,
1401                 0x1ebc0, 0x1ebc8,
1402                 0x1ec08, 0x1ec0c,
1403                 0x1ec40, 0x1ec44,
1404                 0x1ec4c, 0x1ec4c,
1405                 0x1ee84, 0x1ee90,
1406                 0x1eec0, 0x1eec0,
1407                 0x1eee0, 0x1eee0,
1408                 0x1ef00, 0x1ef84,
1409                 0x1efc0, 0x1efc8,
1410                 0x1f008, 0x1f00c,
1411                 0x1f040, 0x1f044,
1412                 0x1f04c, 0x1f04c,
1413                 0x1f284, 0x1f290,
1414                 0x1f2c0, 0x1f2c0,
1415                 0x1f2e0, 0x1f2e0,
1416                 0x1f300, 0x1f384,
1417                 0x1f3c0, 0x1f3c8,
1418                 0x1f408, 0x1f40c,
1419                 0x1f440, 0x1f444,
1420                 0x1f44c, 0x1f44c,
1421                 0x1f684, 0x1f690,
1422                 0x1f6c0, 0x1f6c0,
1423                 0x1f6e0, 0x1f6e0,
1424                 0x1f700, 0x1f784,
1425                 0x1f7c0, 0x1f7c8,
1426                 0x1f808, 0x1f80c,
1427                 0x1f840, 0x1f844,
1428                 0x1f84c, 0x1f84c,
1429                 0x1fa84, 0x1fa90,
1430                 0x1fac0, 0x1fac0,
1431                 0x1fae0, 0x1fae0,
1432                 0x1fb00, 0x1fb84,
1433                 0x1fbc0, 0x1fbc8,
1434                 0x1fc08, 0x1fc0c,
1435                 0x1fc40, 0x1fc44,
1436                 0x1fc4c, 0x1fc4c,
1437                 0x1fe84, 0x1fe90,
1438                 0x1fec0, 0x1fec0,
1439                 0x1fee0, 0x1fee0,
1440                 0x1ff00, 0x1ff84,
1441                 0x1ffc0, 0x1ffc8,
1442                 0x30000, 0x30030,
1443                 0x30100, 0x30144,
1444                 0x30190, 0x301a0,
1445                 0x301a8, 0x301b8,
1446                 0x301c4, 0x301c8,
1447                 0x301d0, 0x301d0,
1448                 0x30200, 0x30318,
1449                 0x30400, 0x304b4,
1450                 0x304c0, 0x3052c,
1451                 0x30540, 0x3061c,
1452                 0x30800, 0x30828,
1453                 0x30834, 0x30834,
1454                 0x308c0, 0x30908,
1455                 0x30910, 0x309ac,
1456                 0x30a00, 0x30a14,
1457                 0x30a1c, 0x30a2c,
1458                 0x30a44, 0x30a50,
1459                 0x30a74, 0x30a74,
1460                 0x30a7c, 0x30afc,
1461                 0x30b08, 0x30c24,
1462                 0x30d00, 0x30d00,
1463                 0x30d08, 0x30d14,
1464                 0x30d1c, 0x30d20,
1465                 0x30d3c, 0x30d3c,
1466                 0x30d48, 0x30d50,
1467                 0x31200, 0x3120c,
1468                 0x31220, 0x31220,
1469                 0x31240, 0x31240,
1470                 0x31600, 0x3160c,
1471                 0x31a00, 0x31a1c,
1472                 0x31e00, 0x31e20,
1473                 0x31e38, 0x31e3c,
1474                 0x31e80, 0x31e80,
1475                 0x31e88, 0x31ea8,
1476                 0x31eb0, 0x31eb4,
1477                 0x31ec8, 0x31ed4,
1478                 0x31fb8, 0x32004,
1479                 0x32200, 0x32200,
1480                 0x32208, 0x32240,
1481                 0x32248, 0x32280,
1482                 0x32288, 0x322c0,
1483                 0x322c8, 0x322fc,
1484                 0x32600, 0x32630,
1485                 0x32a00, 0x32abc,
1486                 0x32b00, 0x32b10,
1487                 0x32b20, 0x32b30,
1488                 0x32b40, 0x32b50,
1489                 0x32b60, 0x32b70,
1490                 0x33000, 0x33028,
1491                 0x33030, 0x33048,
1492                 0x33060, 0x33068,
1493                 0x33070, 0x3309c,
1494                 0x330f0, 0x33128,
1495                 0x33130, 0x33148,
1496                 0x33160, 0x33168,
1497                 0x33170, 0x3319c,
1498                 0x331f0, 0x33238,
1499                 0x33240, 0x33240,
1500                 0x33248, 0x33250,
1501                 0x3325c, 0x33264,
1502                 0x33270, 0x332b8,
1503                 0x332c0, 0x332e4,
1504                 0x332f8, 0x33338,
1505                 0x33340, 0x33340,
1506                 0x33348, 0x33350,
1507                 0x3335c, 0x33364,
1508                 0x33370, 0x333b8,
1509                 0x333c0, 0x333e4,
1510                 0x333f8, 0x33428,
1511                 0x33430, 0x33448,
1512                 0x33460, 0x33468,
1513                 0x33470, 0x3349c,
1514                 0x334f0, 0x33528,
1515                 0x33530, 0x33548,
1516                 0x33560, 0x33568,
1517                 0x33570, 0x3359c,
1518                 0x335f0, 0x33638,
1519                 0x33640, 0x33640,
1520                 0x33648, 0x33650,
1521                 0x3365c, 0x33664,
1522                 0x33670, 0x336b8,
1523                 0x336c0, 0x336e4,
1524                 0x336f8, 0x33738,
1525                 0x33740, 0x33740,
1526                 0x33748, 0x33750,
1527                 0x3375c, 0x33764,
1528                 0x33770, 0x337b8,
1529                 0x337c0, 0x337e4,
1530                 0x337f8, 0x337fc,
1531                 0x33814, 0x33814,
1532                 0x3382c, 0x3382c,
1533                 0x33880, 0x3388c,
1534                 0x338e8, 0x338ec,
1535                 0x33900, 0x33928,
1536                 0x33930, 0x33948,
1537                 0x33960, 0x33968,
1538                 0x33970, 0x3399c,
1539                 0x339f0, 0x33a38,
1540                 0x33a40, 0x33a40,
1541                 0x33a48, 0x33a50,
1542                 0x33a5c, 0x33a64,
1543                 0x33a70, 0x33ab8,
1544                 0x33ac0, 0x33ae4,
1545                 0x33af8, 0x33b10,
1546                 0x33b28, 0x33b28,
1547                 0x33b3c, 0x33b50,
1548                 0x33bf0, 0x33c10,
1549                 0x33c28, 0x33c28,
1550                 0x33c3c, 0x33c50,
1551                 0x33cf0, 0x33cfc,
1552                 0x34000, 0x34030,
1553                 0x34100, 0x34144,
1554                 0x34190, 0x341a0,
1555                 0x341a8, 0x341b8,
1556                 0x341c4, 0x341c8,
1557                 0x341d0, 0x341d0,
1558                 0x34200, 0x34318,
1559                 0x34400, 0x344b4,
1560                 0x344c0, 0x3452c,
1561                 0x34540, 0x3461c,
1562                 0x34800, 0x34828,
1563                 0x34834, 0x34834,
1564                 0x348c0, 0x34908,
1565                 0x34910, 0x349ac,
1566                 0x34a00, 0x34a14,
1567                 0x34a1c, 0x34a2c,
1568                 0x34a44, 0x34a50,
1569                 0x34a74, 0x34a74,
1570                 0x34a7c, 0x34afc,
1571                 0x34b08, 0x34c24,
1572                 0x34d00, 0x34d00,
1573                 0x34d08, 0x34d14,
1574                 0x34d1c, 0x34d20,
1575                 0x34d3c, 0x34d3c,
1576                 0x34d48, 0x34d50,
1577                 0x35200, 0x3520c,
1578                 0x35220, 0x35220,
1579                 0x35240, 0x35240,
1580                 0x35600, 0x3560c,
1581                 0x35a00, 0x35a1c,
1582                 0x35e00, 0x35e20,
1583                 0x35e38, 0x35e3c,
1584                 0x35e80, 0x35e80,
1585                 0x35e88, 0x35ea8,
1586                 0x35eb0, 0x35eb4,
1587                 0x35ec8, 0x35ed4,
1588                 0x35fb8, 0x36004,
1589                 0x36200, 0x36200,
1590                 0x36208, 0x36240,
1591                 0x36248, 0x36280,
1592                 0x36288, 0x362c0,
1593                 0x362c8, 0x362fc,
1594                 0x36600, 0x36630,
1595                 0x36a00, 0x36abc,
1596                 0x36b00, 0x36b10,
1597                 0x36b20, 0x36b30,
1598                 0x36b40, 0x36b50,
1599                 0x36b60, 0x36b70,
1600                 0x37000, 0x37028,
1601                 0x37030, 0x37048,
1602                 0x37060, 0x37068,
1603                 0x37070, 0x3709c,
1604                 0x370f0, 0x37128,
1605                 0x37130, 0x37148,
1606                 0x37160, 0x37168,
1607                 0x37170, 0x3719c,
1608                 0x371f0, 0x37238,
1609                 0x37240, 0x37240,
1610                 0x37248, 0x37250,
1611                 0x3725c, 0x37264,
1612                 0x37270, 0x372b8,
1613                 0x372c0, 0x372e4,
1614                 0x372f8, 0x37338,
1615                 0x37340, 0x37340,
1616                 0x37348, 0x37350,
1617                 0x3735c, 0x37364,
1618                 0x37370, 0x373b8,
1619                 0x373c0, 0x373e4,
1620                 0x373f8, 0x37428,
1621                 0x37430, 0x37448,
1622                 0x37460, 0x37468,
1623                 0x37470, 0x3749c,
1624                 0x374f0, 0x37528,
1625                 0x37530, 0x37548,
1626                 0x37560, 0x37568,
1627                 0x37570, 0x3759c,
1628                 0x375f0, 0x37638,
1629                 0x37640, 0x37640,
1630                 0x37648, 0x37650,
1631                 0x3765c, 0x37664,
1632                 0x37670, 0x376b8,
1633                 0x376c0, 0x376e4,
1634                 0x376f8, 0x37738,
1635                 0x37740, 0x37740,
1636                 0x37748, 0x37750,
1637                 0x3775c, 0x37764,
1638                 0x37770, 0x377b8,
1639                 0x377c0, 0x377e4,
1640                 0x377f8, 0x377fc,
1641                 0x37814, 0x37814,
1642                 0x3782c, 0x3782c,
1643                 0x37880, 0x3788c,
1644                 0x378e8, 0x378ec,
1645                 0x37900, 0x37928,
1646                 0x37930, 0x37948,
1647                 0x37960, 0x37968,
1648                 0x37970, 0x3799c,
1649                 0x379f0, 0x37a38,
1650                 0x37a40, 0x37a40,
1651                 0x37a48, 0x37a50,
1652                 0x37a5c, 0x37a64,
1653                 0x37a70, 0x37ab8,
1654                 0x37ac0, 0x37ae4,
1655                 0x37af8, 0x37b10,
1656                 0x37b28, 0x37b28,
1657                 0x37b3c, 0x37b50,
1658                 0x37bf0, 0x37c10,
1659                 0x37c28, 0x37c28,
1660                 0x37c3c, 0x37c50,
1661                 0x37cf0, 0x37cfc,
1662                 0x38000, 0x38030,
1663                 0x38100, 0x38144,
1664                 0x38190, 0x381a0,
1665                 0x381a8, 0x381b8,
1666                 0x381c4, 0x381c8,
1667                 0x381d0, 0x381d0,
1668                 0x38200, 0x38318,
1669                 0x38400, 0x384b4,
1670                 0x384c0, 0x3852c,
1671                 0x38540, 0x3861c,
1672                 0x38800, 0x38828,
1673                 0x38834, 0x38834,
1674                 0x388c0, 0x38908,
1675                 0x38910, 0x389ac,
1676                 0x38a00, 0x38a14,
1677                 0x38a1c, 0x38a2c,
1678                 0x38a44, 0x38a50,
1679                 0x38a74, 0x38a74,
1680                 0x38a7c, 0x38afc,
1681                 0x38b08, 0x38c24,
1682                 0x38d00, 0x38d00,
1683                 0x38d08, 0x38d14,
1684                 0x38d1c, 0x38d20,
1685                 0x38d3c, 0x38d3c,
1686                 0x38d48, 0x38d50,
1687                 0x39200, 0x3920c,
1688                 0x39220, 0x39220,
1689                 0x39240, 0x39240,
1690                 0x39600, 0x3960c,
1691                 0x39a00, 0x39a1c,
1692                 0x39e00, 0x39e20,
1693                 0x39e38, 0x39e3c,
1694                 0x39e80, 0x39e80,
1695                 0x39e88, 0x39ea8,
1696                 0x39eb0, 0x39eb4,
1697                 0x39ec8, 0x39ed4,
1698                 0x39fb8, 0x3a004,
1699                 0x3a200, 0x3a200,
1700                 0x3a208, 0x3a240,
1701                 0x3a248, 0x3a280,
1702                 0x3a288, 0x3a2c0,
1703                 0x3a2c8, 0x3a2fc,
1704                 0x3a600, 0x3a630,
1705                 0x3aa00, 0x3aabc,
1706                 0x3ab00, 0x3ab10,
1707                 0x3ab20, 0x3ab30,
1708                 0x3ab40, 0x3ab50,
1709                 0x3ab60, 0x3ab70,
1710                 0x3b000, 0x3b028,
1711                 0x3b030, 0x3b048,
1712                 0x3b060, 0x3b068,
1713                 0x3b070, 0x3b09c,
1714                 0x3b0f0, 0x3b128,
1715                 0x3b130, 0x3b148,
1716                 0x3b160, 0x3b168,
1717                 0x3b170, 0x3b19c,
1718                 0x3b1f0, 0x3b238,
1719                 0x3b240, 0x3b240,
1720                 0x3b248, 0x3b250,
1721                 0x3b25c, 0x3b264,
1722                 0x3b270, 0x3b2b8,
1723                 0x3b2c0, 0x3b2e4,
1724                 0x3b2f8, 0x3b338,
1725                 0x3b340, 0x3b340,
1726                 0x3b348, 0x3b350,
1727                 0x3b35c, 0x3b364,
1728                 0x3b370, 0x3b3b8,
1729                 0x3b3c0, 0x3b3e4,
1730                 0x3b3f8, 0x3b428,
1731                 0x3b430, 0x3b448,
1732                 0x3b460, 0x3b468,
1733                 0x3b470, 0x3b49c,
1734                 0x3b4f0, 0x3b528,
1735                 0x3b530, 0x3b548,
1736                 0x3b560, 0x3b568,
1737                 0x3b570, 0x3b59c,
1738                 0x3b5f0, 0x3b638,
1739                 0x3b640, 0x3b640,
1740                 0x3b648, 0x3b650,
1741                 0x3b65c, 0x3b664,
1742                 0x3b670, 0x3b6b8,
1743                 0x3b6c0, 0x3b6e4,
1744                 0x3b6f8, 0x3b738,
1745                 0x3b740, 0x3b740,
1746                 0x3b748, 0x3b750,
1747                 0x3b75c, 0x3b764,
1748                 0x3b770, 0x3b7b8,
1749                 0x3b7c0, 0x3b7e4,
1750                 0x3b7f8, 0x3b7fc,
1751                 0x3b814, 0x3b814,
1752                 0x3b82c, 0x3b82c,
1753                 0x3b880, 0x3b88c,
1754                 0x3b8e8, 0x3b8ec,
1755                 0x3b900, 0x3b928,
1756                 0x3b930, 0x3b948,
1757                 0x3b960, 0x3b968,
1758                 0x3b970, 0x3b99c,
1759                 0x3b9f0, 0x3ba38,
1760                 0x3ba40, 0x3ba40,
1761                 0x3ba48, 0x3ba50,
1762                 0x3ba5c, 0x3ba64,
1763                 0x3ba70, 0x3bab8,
1764                 0x3bac0, 0x3bae4,
1765                 0x3baf8, 0x3bb10,
1766                 0x3bb28, 0x3bb28,
1767                 0x3bb3c, 0x3bb50,
1768                 0x3bbf0, 0x3bc10,
1769                 0x3bc28, 0x3bc28,
1770                 0x3bc3c, 0x3bc50,
1771                 0x3bcf0, 0x3bcfc,
1772                 0x3c000, 0x3c030,
1773                 0x3c100, 0x3c144,
1774                 0x3c190, 0x3c1a0,
1775                 0x3c1a8, 0x3c1b8,
1776                 0x3c1c4, 0x3c1c8,
1777                 0x3c1d0, 0x3c1d0,
1778                 0x3c200, 0x3c318,
1779                 0x3c400, 0x3c4b4,
1780                 0x3c4c0, 0x3c52c,
1781                 0x3c540, 0x3c61c,
1782                 0x3c800, 0x3c828,
1783                 0x3c834, 0x3c834,
1784                 0x3c8c0, 0x3c908,
1785                 0x3c910, 0x3c9ac,
1786                 0x3ca00, 0x3ca14,
1787                 0x3ca1c, 0x3ca2c,
1788                 0x3ca44, 0x3ca50,
1789                 0x3ca74, 0x3ca74,
1790                 0x3ca7c, 0x3cafc,
1791                 0x3cb08, 0x3cc24,
1792                 0x3cd00, 0x3cd00,
1793                 0x3cd08, 0x3cd14,
1794                 0x3cd1c, 0x3cd20,
1795                 0x3cd3c, 0x3cd3c,
1796                 0x3cd48, 0x3cd50,
1797                 0x3d200, 0x3d20c,
1798                 0x3d220, 0x3d220,
1799                 0x3d240, 0x3d240,
1800                 0x3d600, 0x3d60c,
1801                 0x3da00, 0x3da1c,
1802                 0x3de00, 0x3de20,
1803                 0x3de38, 0x3de3c,
1804                 0x3de80, 0x3de80,
1805                 0x3de88, 0x3dea8,
1806                 0x3deb0, 0x3deb4,
1807                 0x3dec8, 0x3ded4,
1808                 0x3dfb8, 0x3e004,
1809                 0x3e200, 0x3e200,
1810                 0x3e208, 0x3e240,
1811                 0x3e248, 0x3e280,
1812                 0x3e288, 0x3e2c0,
1813                 0x3e2c8, 0x3e2fc,
1814                 0x3e600, 0x3e630,
1815                 0x3ea00, 0x3eabc,
1816                 0x3eb00, 0x3eb10,
1817                 0x3eb20, 0x3eb30,
1818                 0x3eb40, 0x3eb50,
1819                 0x3eb60, 0x3eb70,
1820                 0x3f000, 0x3f028,
1821                 0x3f030, 0x3f048,
1822                 0x3f060, 0x3f068,
1823                 0x3f070, 0x3f09c,
1824                 0x3f0f0, 0x3f128,
1825                 0x3f130, 0x3f148,
1826                 0x3f160, 0x3f168,
1827                 0x3f170, 0x3f19c,
1828                 0x3f1f0, 0x3f238,
1829                 0x3f240, 0x3f240,
1830                 0x3f248, 0x3f250,
1831                 0x3f25c, 0x3f264,
1832                 0x3f270, 0x3f2b8,
1833                 0x3f2c0, 0x3f2e4,
1834                 0x3f2f8, 0x3f338,
1835                 0x3f340, 0x3f340,
1836                 0x3f348, 0x3f350,
1837                 0x3f35c, 0x3f364,
1838                 0x3f370, 0x3f3b8,
1839                 0x3f3c0, 0x3f3e4,
1840                 0x3f3f8, 0x3f428,
1841                 0x3f430, 0x3f448,
1842                 0x3f460, 0x3f468,
1843                 0x3f470, 0x3f49c,
1844                 0x3f4f0, 0x3f528,
1845                 0x3f530, 0x3f548,
1846                 0x3f560, 0x3f568,
1847                 0x3f570, 0x3f59c,
1848                 0x3f5f0, 0x3f638,
1849                 0x3f640, 0x3f640,
1850                 0x3f648, 0x3f650,
1851                 0x3f65c, 0x3f664,
1852                 0x3f670, 0x3f6b8,
1853                 0x3f6c0, 0x3f6e4,
1854                 0x3f6f8, 0x3f738,
1855                 0x3f740, 0x3f740,
1856                 0x3f748, 0x3f750,
1857                 0x3f75c, 0x3f764,
1858                 0x3f770, 0x3f7b8,
1859                 0x3f7c0, 0x3f7e4,
1860                 0x3f7f8, 0x3f7fc,
1861                 0x3f814, 0x3f814,
1862                 0x3f82c, 0x3f82c,
1863                 0x3f880, 0x3f88c,
1864                 0x3f8e8, 0x3f8ec,
1865                 0x3f900, 0x3f928,
1866                 0x3f930, 0x3f948,
1867                 0x3f960, 0x3f968,
1868                 0x3f970, 0x3f99c,
1869                 0x3f9f0, 0x3fa38,
1870                 0x3fa40, 0x3fa40,
1871                 0x3fa48, 0x3fa50,
1872                 0x3fa5c, 0x3fa64,
1873                 0x3fa70, 0x3fab8,
1874                 0x3fac0, 0x3fae4,
1875                 0x3faf8, 0x3fb10,
1876                 0x3fb28, 0x3fb28,
1877                 0x3fb3c, 0x3fb50,
1878                 0x3fbf0, 0x3fc10,
1879                 0x3fc28, 0x3fc28,
1880                 0x3fc3c, 0x3fc50,
1881                 0x3fcf0, 0x3fcfc,
1882                 0x40000, 0x4000c,
1883                 0x40040, 0x40050,
1884                 0x40060, 0x40068,
1885                 0x4007c, 0x4008c,
1886                 0x40094, 0x400b0,
1887                 0x400c0, 0x40144,
1888                 0x40180, 0x4018c,
1889                 0x40200, 0x40254,
1890                 0x40260, 0x40264,
1891                 0x40270, 0x40288,
1892                 0x40290, 0x40298,
1893                 0x402ac, 0x402c8,
1894                 0x402d0, 0x402e0,
1895                 0x402f0, 0x402f0,
1896                 0x40300, 0x4033c,
1897                 0x403f8, 0x403fc,
1898                 0x41304, 0x413c4,
1899                 0x41400, 0x4140c,
1900                 0x41414, 0x4141c,
1901                 0x41480, 0x414d0,
1902                 0x44000, 0x44054,
1903                 0x4405c, 0x44078,
1904                 0x440c0, 0x44174,
1905                 0x44180, 0x441ac,
1906                 0x441b4, 0x441b8,
1907                 0x441c0, 0x44254,
1908                 0x4425c, 0x44278,
1909                 0x442c0, 0x44374,
1910                 0x44380, 0x443ac,
1911                 0x443b4, 0x443b8,
1912                 0x443c0, 0x44454,
1913                 0x4445c, 0x44478,
1914                 0x444c0, 0x44574,
1915                 0x44580, 0x445ac,
1916                 0x445b4, 0x445b8,
1917                 0x445c0, 0x44654,
1918                 0x4465c, 0x44678,
1919                 0x446c0, 0x44774,
1920                 0x44780, 0x447ac,
1921                 0x447b4, 0x447b8,
1922                 0x447c0, 0x44854,
1923                 0x4485c, 0x44878,
1924                 0x448c0, 0x44974,
1925                 0x44980, 0x449ac,
1926                 0x449b4, 0x449b8,
1927                 0x449c0, 0x449fc,
1928                 0x45000, 0x45004,
1929                 0x45010, 0x45030,
1930                 0x45040, 0x45060,
1931                 0x45068, 0x45068,
1932                 0x45080, 0x45084,
1933                 0x450a0, 0x450b0,
1934                 0x45200, 0x45204,
1935                 0x45210, 0x45230,
1936                 0x45240, 0x45260,
1937                 0x45268, 0x45268,
1938                 0x45280, 0x45284,
1939                 0x452a0, 0x452b0,
1940                 0x460c0, 0x460e4,
1941                 0x47000, 0x4703c,
1942                 0x47044, 0x4708c,
1943                 0x47200, 0x47250,
1944                 0x47400, 0x47408,
1945                 0x47414, 0x47420,
1946                 0x47600, 0x47618,
1947                 0x47800, 0x47814,
1948                 0x48000, 0x4800c,
1949                 0x48040, 0x48050,
1950                 0x48060, 0x48068,
1951                 0x4807c, 0x4808c,
1952                 0x48094, 0x480b0,
1953                 0x480c0, 0x48144,
1954                 0x48180, 0x4818c,
1955                 0x48200, 0x48254,
1956                 0x48260, 0x48264,
1957                 0x48270, 0x48288,
1958                 0x48290, 0x48298,
1959                 0x482ac, 0x482c8,
1960                 0x482d0, 0x482e0,
1961                 0x482f0, 0x482f0,
1962                 0x48300, 0x4833c,
1963                 0x483f8, 0x483fc,
1964                 0x49304, 0x493c4,
1965                 0x49400, 0x4940c,
1966                 0x49414, 0x4941c,
1967                 0x49480, 0x494d0,
1968                 0x4c000, 0x4c054,
1969                 0x4c05c, 0x4c078,
1970                 0x4c0c0, 0x4c174,
1971                 0x4c180, 0x4c1ac,
1972                 0x4c1b4, 0x4c1b8,
1973                 0x4c1c0, 0x4c254,
1974                 0x4c25c, 0x4c278,
1975                 0x4c2c0, 0x4c374,
1976                 0x4c380, 0x4c3ac,
1977                 0x4c3b4, 0x4c3b8,
1978                 0x4c3c0, 0x4c454,
1979                 0x4c45c, 0x4c478,
1980                 0x4c4c0, 0x4c574,
1981                 0x4c580, 0x4c5ac,
1982                 0x4c5b4, 0x4c5b8,
1983                 0x4c5c0, 0x4c654,
1984                 0x4c65c, 0x4c678,
1985                 0x4c6c0, 0x4c774,
1986                 0x4c780, 0x4c7ac,
1987                 0x4c7b4, 0x4c7b8,
1988                 0x4c7c0, 0x4c854,
1989                 0x4c85c, 0x4c878,
1990                 0x4c8c0, 0x4c974,
1991                 0x4c980, 0x4c9ac,
1992                 0x4c9b4, 0x4c9b8,
1993                 0x4c9c0, 0x4c9fc,
1994                 0x4d000, 0x4d004,
1995                 0x4d010, 0x4d030,
1996                 0x4d040, 0x4d060,
1997                 0x4d068, 0x4d068,
1998                 0x4d080, 0x4d084,
1999                 0x4d0a0, 0x4d0b0,
2000                 0x4d200, 0x4d204,
2001                 0x4d210, 0x4d230,
2002                 0x4d240, 0x4d260,
2003                 0x4d268, 0x4d268,
2004                 0x4d280, 0x4d284,
2005                 0x4d2a0, 0x4d2b0,
2006                 0x4e0c0, 0x4e0e4,
2007                 0x4f000, 0x4f03c,
2008                 0x4f044, 0x4f08c,
2009                 0x4f200, 0x4f250,
2010                 0x4f400, 0x4f408,
2011                 0x4f414, 0x4f420,
2012                 0x4f600, 0x4f618,
2013                 0x4f800, 0x4f814,
2014                 0x50000, 0x50084,
2015                 0x50090, 0x500cc,
2016                 0x50400, 0x50400,
2017                 0x50800, 0x50884,
2018                 0x50890, 0x508cc,
2019                 0x50c00, 0x50c00,
2020                 0x51000, 0x5101c,
2021                 0x51300, 0x51308,
2022         };
2023
2024         static const unsigned int t6_reg_ranges[] = {
2025                 0x1008, 0x101c,
2026                 0x1024, 0x10a8,
2027                 0x10b4, 0x10f8,
2028                 0x1100, 0x1114,
2029                 0x111c, 0x112c,
2030                 0x1138, 0x113c,
2031                 0x1144, 0x114c,
2032                 0x1180, 0x1184,
2033                 0x1190, 0x1194,
2034                 0x11a0, 0x11a4,
2035                 0x11b0, 0x11b4,
2036                 0x11fc, 0x1274,
2037                 0x1280, 0x133c,
2038                 0x1800, 0x18fc,
2039                 0x3000, 0x302c,
2040                 0x3060, 0x30b0,
2041                 0x30b8, 0x30d8,
2042                 0x30e0, 0x30fc,
2043                 0x3140, 0x357c,
2044                 0x35a8, 0x35cc,
2045                 0x35ec, 0x35ec,
2046                 0x3600, 0x5624,
2047                 0x56cc, 0x56ec,
2048                 0x56f4, 0x5720,
2049                 0x5728, 0x575c,
2050                 0x580c, 0x5814,
2051                 0x5890, 0x589c,
2052                 0x58a4, 0x58ac,
2053                 0x58b8, 0x58bc,
2054                 0x5940, 0x595c,
2055                 0x5980, 0x598c,
2056                 0x59b0, 0x59c8,
2057                 0x59d0, 0x59dc,
2058                 0x59fc, 0x5a18,
2059                 0x5a60, 0x5a6c,
2060                 0x5a80, 0x5a8c,
2061                 0x5a94, 0x5a9c,
2062                 0x5b94, 0x5bfc,
2063                 0x5c10, 0x5e48,
2064                 0x5e50, 0x5e94,
2065                 0x5ea0, 0x5eb0,
2066                 0x5ec0, 0x5ec0,
2067                 0x5ec8, 0x5ed0,
2068                 0x5ee0, 0x5ee0,
2069                 0x5ef0, 0x5ef0,
2070                 0x5f00, 0x5f00,
2071                 0x6000, 0x6020,
2072                 0x6028, 0x6040,
2073                 0x6058, 0x609c,
2074                 0x60a8, 0x619c,
2075                 0x7700, 0x7798,
2076                 0x77c0, 0x7880,
2077                 0x78cc, 0x78fc,
2078                 0x7b00, 0x7b58,
2079                 0x7b60, 0x7b84,
2080                 0x7b8c, 0x7c54,
2081                 0x7d00, 0x7d38,
2082                 0x7d40, 0x7d84,
2083                 0x7d8c, 0x7ddc,
2084                 0x7de4, 0x7e04,
2085                 0x7e10, 0x7e1c,
2086                 0x7e24, 0x7e38,
2087                 0x7e40, 0x7e44,
2088                 0x7e4c, 0x7e78,
2089                 0x7e80, 0x7edc,
2090                 0x7ee8, 0x7efc,
2091                 0x8dc0, 0x8de4,
2092                 0x8df8, 0x8e04,
2093                 0x8e10, 0x8e84,
2094                 0x8ea0, 0x8f88,
2095                 0x8fb8, 0x9058,
2096                 0x9060, 0x9060,
2097                 0x9068, 0x90f8,
2098                 0x9100, 0x9124,
2099                 0x9400, 0x9470,
2100                 0x9600, 0x9600,
2101                 0x9608, 0x9638,
2102                 0x9640, 0x9704,
2103                 0x9710, 0x971c,
2104                 0x9800, 0x9808,
2105                 0x9820, 0x983c,
2106                 0x9850, 0x9864,
2107                 0x9c00, 0x9c6c,
2108                 0x9c80, 0x9cec,
2109                 0x9d00, 0x9d6c,
2110                 0x9d80, 0x9dec,
2111                 0x9e00, 0x9e6c,
2112                 0x9e80, 0x9eec,
2113                 0x9f00, 0x9f6c,
2114                 0x9f80, 0xa020,
2115                 0xd004, 0xd03c,
2116                 0xd100, 0xd118,
2117                 0xd200, 0xd214,
2118                 0xd220, 0xd234,
2119                 0xd240, 0xd254,
2120                 0xd260, 0xd274,
2121                 0xd280, 0xd294,
2122                 0xd2a0, 0xd2b4,
2123                 0xd2c0, 0xd2d4,
2124                 0xd2e0, 0xd2f4,
2125                 0xd300, 0xd31c,
2126                 0xdfc0, 0xdfe0,
2127                 0xe000, 0xf008,
2128                 0xf010, 0xf018,
2129                 0xf020, 0xf028,
2130                 0x11000, 0x11014,
2131                 0x11048, 0x1106c,
2132                 0x11074, 0x11088,
2133                 0x11098, 0x11120,
2134                 0x1112c, 0x1117c,
2135                 0x11190, 0x112e0,
2136                 0x11300, 0x1130c,
2137                 0x12000, 0x1206c,
2138                 0x19040, 0x1906c,
2139                 0x19078, 0x19080,
2140                 0x1908c, 0x190e8,
2141                 0x190f0, 0x190f8,
2142                 0x19100, 0x19110,
2143                 0x19120, 0x19124,
2144                 0x19150, 0x19194,
2145                 0x1919c, 0x191b0,
2146                 0x191d0, 0x191e8,
2147                 0x19238, 0x19290,
2148                 0x192a4, 0x192b0,
2149                 0x192bc, 0x192bc,
2150                 0x19348, 0x1934c,
2151                 0x193f8, 0x19418,
2152                 0x19420, 0x19428,
2153                 0x19430, 0x19444,
2154                 0x1944c, 0x1946c,
2155                 0x19474, 0x19474,
2156                 0x19490, 0x194cc,
2157                 0x194f0, 0x194f8,
2158                 0x19c00, 0x19c48,
2159                 0x19c50, 0x19c80,
2160                 0x19c94, 0x19c98,
2161                 0x19ca0, 0x19cbc,
2162                 0x19ce4, 0x19ce4,
2163                 0x19cf0, 0x19cf8,
2164                 0x19d00, 0x19d28,
2165                 0x19d50, 0x19d78,
2166                 0x19d94, 0x19d98,
2167                 0x19da0, 0x19dc8,
2168                 0x19df0, 0x19e10,
2169                 0x19e50, 0x19e6c,
2170                 0x19ea0, 0x19ebc,
2171                 0x19ec4, 0x19ef4,
2172                 0x19f04, 0x19f2c,
2173                 0x19f34, 0x19f34,
2174                 0x19f40, 0x19f50,
2175                 0x19f90, 0x19fac,
2176                 0x19fc4, 0x19fc8,
2177                 0x19fd0, 0x19fe4,
2178                 0x1a000, 0x1a004,
2179                 0x1a010, 0x1a06c,
2180                 0x1a0b0, 0x1a0e4,
2181                 0x1a0ec, 0x1a0f8,
2182                 0x1a100, 0x1a108,
2183                 0x1a114, 0x1a120,
2184                 0x1a128, 0x1a130,
2185                 0x1a138, 0x1a138,
2186                 0x1a190, 0x1a1c4,
2187                 0x1a1fc, 0x1a1fc,
2188                 0x1e008, 0x1e00c,
2189                 0x1e040, 0x1e044,
2190                 0x1e04c, 0x1e04c,
2191                 0x1e284, 0x1e290,
2192                 0x1e2c0, 0x1e2c0,
2193                 0x1e2e0, 0x1e2e0,
2194                 0x1e300, 0x1e384,
2195                 0x1e3c0, 0x1e3c8,
2196                 0x1e408, 0x1e40c,
2197                 0x1e440, 0x1e444,
2198                 0x1e44c, 0x1e44c,
2199                 0x1e684, 0x1e690,
2200                 0x1e6c0, 0x1e6c0,
2201                 0x1e6e0, 0x1e6e0,
2202                 0x1e700, 0x1e784,
2203                 0x1e7c0, 0x1e7c8,
2204                 0x1e808, 0x1e80c,
2205                 0x1e840, 0x1e844,
2206                 0x1e84c, 0x1e84c,
2207                 0x1ea84, 0x1ea90,
2208                 0x1eac0, 0x1eac0,
2209                 0x1eae0, 0x1eae0,
2210                 0x1eb00, 0x1eb84,
2211                 0x1ebc0, 0x1ebc8,
2212                 0x1ec08, 0x1ec0c,
2213                 0x1ec40, 0x1ec44,
2214                 0x1ec4c, 0x1ec4c,
2215                 0x1ee84, 0x1ee90,
2216                 0x1eec0, 0x1eec0,
2217                 0x1eee0, 0x1eee0,
2218                 0x1ef00, 0x1ef84,
2219                 0x1efc0, 0x1efc8,
2220                 0x1f008, 0x1f00c,
2221                 0x1f040, 0x1f044,
2222                 0x1f04c, 0x1f04c,
2223                 0x1f284, 0x1f290,
2224                 0x1f2c0, 0x1f2c0,
2225                 0x1f2e0, 0x1f2e0,
2226                 0x1f300, 0x1f384,
2227                 0x1f3c0, 0x1f3c8,
2228                 0x1f408, 0x1f40c,
2229                 0x1f440, 0x1f444,
2230                 0x1f44c, 0x1f44c,
2231                 0x1f684, 0x1f690,
2232                 0x1f6c0, 0x1f6c0,
2233                 0x1f6e0, 0x1f6e0,
2234                 0x1f700, 0x1f784,
2235                 0x1f7c0, 0x1f7c8,
2236                 0x1f808, 0x1f80c,
2237                 0x1f840, 0x1f844,
2238                 0x1f84c, 0x1f84c,
2239                 0x1fa84, 0x1fa90,
2240                 0x1fac0, 0x1fac0,
2241                 0x1fae0, 0x1fae0,
2242                 0x1fb00, 0x1fb84,
2243                 0x1fbc0, 0x1fbc8,
2244                 0x1fc08, 0x1fc0c,
2245                 0x1fc40, 0x1fc44,
2246                 0x1fc4c, 0x1fc4c,
2247                 0x1fe84, 0x1fe90,
2248                 0x1fec0, 0x1fec0,
2249                 0x1fee0, 0x1fee0,
2250                 0x1ff00, 0x1ff84,
2251                 0x1ffc0, 0x1ffc8,
2252                 0x30000, 0x30030,
2253                 0x30100, 0x30168,
2254                 0x30190, 0x301a0,
2255                 0x301a8, 0x301b8,
2256                 0x301c4, 0x301c8,
2257                 0x301d0, 0x301d0,
2258                 0x30200, 0x30320,
2259                 0x30400, 0x304b4,
2260                 0x304c0, 0x3052c,
2261                 0x30540, 0x3061c,
2262                 0x30800, 0x308a0,
2263                 0x308c0, 0x30908,
2264                 0x30910, 0x309b8,
2265                 0x30a00, 0x30a04,
2266                 0x30a0c, 0x30a14,
2267                 0x30a1c, 0x30a2c,
2268                 0x30a44, 0x30a50,
2269                 0x30a74, 0x30a74,
2270                 0x30a7c, 0x30afc,
2271                 0x30b08, 0x30c24,
2272                 0x30d00, 0x30d14,
2273                 0x30d1c, 0x30d3c,
2274                 0x30d44, 0x30d4c,
2275                 0x30d54, 0x30d74,
2276                 0x30d7c, 0x30d7c,
2277                 0x30de0, 0x30de0,
2278                 0x30e00, 0x30ed4,
2279                 0x30f00, 0x30fa4,
2280                 0x30fc0, 0x30fc4,
2281                 0x31000, 0x31004,
2282                 0x31080, 0x310fc,
2283                 0x31208, 0x31220,
2284                 0x3123c, 0x31254,
2285                 0x31300, 0x31300,
2286                 0x31308, 0x3131c,
2287                 0x31338, 0x3133c,
2288                 0x31380, 0x31380,
2289                 0x31388, 0x313a8,
2290                 0x313b4, 0x313b4,
2291                 0x31400, 0x31420,
2292                 0x31438, 0x3143c,
2293                 0x31480, 0x31480,
2294                 0x314a8, 0x314a8,
2295                 0x314b0, 0x314b4,
2296                 0x314c8, 0x314d4,
2297                 0x31a40, 0x31a4c,
2298                 0x31af0, 0x31b20,
2299                 0x31b38, 0x31b3c,
2300                 0x31b80, 0x31b80,
2301                 0x31ba8, 0x31ba8,
2302                 0x31bb0, 0x31bb4,
2303                 0x31bc8, 0x31bd4,
2304                 0x32140, 0x3218c,
2305                 0x321f0, 0x321f4,
2306                 0x32200, 0x32200,
2307                 0x32218, 0x32218,
2308                 0x32400, 0x32400,
2309                 0x32408, 0x3241c,
2310                 0x32618, 0x32620,
2311                 0x32664, 0x32664,
2312                 0x326a8, 0x326a8,
2313                 0x326ec, 0x326ec,
2314                 0x32a00, 0x32abc,
2315                 0x32b00, 0x32b18,
2316                 0x32b20, 0x32b38,
2317                 0x32b40, 0x32b58,
2318                 0x32b60, 0x32b78,
2319                 0x32c00, 0x32c00,
2320                 0x32c08, 0x32c3c,
2321                 0x33000, 0x3302c,
2322                 0x33034, 0x33050,
2323                 0x33058, 0x33058,
2324                 0x33060, 0x3308c,
2325                 0x3309c, 0x330ac,
2326                 0x330c0, 0x330c0,
2327                 0x330c8, 0x330d0,
2328                 0x330d8, 0x330e0,
2329                 0x330ec, 0x3312c,
2330                 0x33134, 0x33150,
2331                 0x33158, 0x33158,
2332                 0x33160, 0x3318c,
2333                 0x3319c, 0x331ac,
2334                 0x331c0, 0x331c0,
2335                 0x331c8, 0x331d0,
2336                 0x331d8, 0x331e0,
2337                 0x331ec, 0x33290,
2338                 0x33298, 0x332c4,
2339                 0x332e4, 0x33390,
2340                 0x33398, 0x333c4,
2341                 0x333e4, 0x3342c,
2342                 0x33434, 0x33450,
2343                 0x33458, 0x33458,
2344                 0x33460, 0x3348c,
2345                 0x3349c, 0x334ac,
2346                 0x334c0, 0x334c0,
2347                 0x334c8, 0x334d0,
2348                 0x334d8, 0x334e0,
2349                 0x334ec, 0x3352c,
2350                 0x33534, 0x33550,
2351                 0x33558, 0x33558,
2352                 0x33560, 0x3358c,
2353                 0x3359c, 0x335ac,
2354                 0x335c0, 0x335c0,
2355                 0x335c8, 0x335d0,
2356                 0x335d8, 0x335e0,
2357                 0x335ec, 0x33690,
2358                 0x33698, 0x336c4,
2359                 0x336e4, 0x33790,
2360                 0x33798, 0x337c4,
2361                 0x337e4, 0x337fc,
2362                 0x33814, 0x33814,
2363                 0x33854, 0x33868,
2364                 0x33880, 0x3388c,
2365                 0x338c0, 0x338d0,
2366                 0x338e8, 0x338ec,
2367                 0x33900, 0x3392c,
2368                 0x33934, 0x33950,
2369                 0x33958, 0x33958,
2370                 0x33960, 0x3398c,
2371                 0x3399c, 0x339ac,
2372                 0x339c0, 0x339c0,
2373                 0x339c8, 0x339d0,
2374                 0x339d8, 0x339e0,
2375                 0x339ec, 0x33a90,
2376                 0x33a98, 0x33ac4,
2377                 0x33ae4, 0x33b10,
2378                 0x33b24, 0x33b28,
2379                 0x33b38, 0x33b50,
2380                 0x33bf0, 0x33c10,
2381                 0x33c24, 0x33c28,
2382                 0x33c38, 0x33c50,
2383                 0x33cf0, 0x33cfc,
2384                 0x34000, 0x34030,
2385                 0x34100, 0x34168,
2386                 0x34190, 0x341a0,
2387                 0x341a8, 0x341b8,
2388                 0x341c4, 0x341c8,
2389                 0x341d0, 0x341d0,
2390                 0x34200, 0x34320,
2391                 0x34400, 0x344b4,
2392                 0x344c0, 0x3452c,
2393                 0x34540, 0x3461c,
2394                 0x34800, 0x348a0,
2395                 0x348c0, 0x34908,
2396                 0x34910, 0x349b8,
2397                 0x34a00, 0x34a04,
2398                 0x34a0c, 0x34a14,
2399                 0x34a1c, 0x34a2c,
2400                 0x34a44, 0x34a50,
2401                 0x34a74, 0x34a74,
2402                 0x34a7c, 0x34afc,
2403                 0x34b08, 0x34c24,
2404                 0x34d00, 0x34d14,
2405                 0x34d1c, 0x34d3c,
2406                 0x34d44, 0x34d4c,
2407                 0x34d54, 0x34d74,
2408                 0x34d7c, 0x34d7c,
2409                 0x34de0, 0x34de0,
2410                 0x34e00, 0x34ed4,
2411                 0x34f00, 0x34fa4,
2412                 0x34fc0, 0x34fc4,
2413                 0x35000, 0x35004,
2414                 0x35080, 0x350fc,
2415                 0x35208, 0x35220,
2416                 0x3523c, 0x35254,
2417                 0x35300, 0x35300,
2418                 0x35308, 0x3531c,
2419                 0x35338, 0x3533c,
2420                 0x35380, 0x35380,
2421                 0x35388, 0x353a8,
2422                 0x353b4, 0x353b4,
2423                 0x35400, 0x35420,
2424                 0x35438, 0x3543c,
2425                 0x35480, 0x35480,
2426                 0x354a8, 0x354a8,
2427                 0x354b0, 0x354b4,
2428                 0x354c8, 0x354d4,
2429                 0x35a40, 0x35a4c,
2430                 0x35af0, 0x35b20,
2431                 0x35b38, 0x35b3c,
2432                 0x35b80, 0x35b80,
2433                 0x35ba8, 0x35ba8,
2434                 0x35bb0, 0x35bb4,
2435                 0x35bc8, 0x35bd4,
2436                 0x36140, 0x3618c,
2437                 0x361f0, 0x361f4,
2438                 0x36200, 0x36200,
2439                 0x36218, 0x36218,
2440                 0x36400, 0x36400,
2441                 0x36408, 0x3641c,
2442                 0x36618, 0x36620,
2443                 0x36664, 0x36664,
2444                 0x366a8, 0x366a8,
2445                 0x366ec, 0x366ec,
2446                 0x36a00, 0x36abc,
2447                 0x36b00, 0x36b18,
2448                 0x36b20, 0x36b38,
2449                 0x36b40, 0x36b58,
2450                 0x36b60, 0x36b78,
2451                 0x36c00, 0x36c00,
2452                 0x36c08, 0x36c3c,
2453                 0x37000, 0x3702c,
2454                 0x37034, 0x37050,
2455                 0x37058, 0x37058,
2456                 0x37060, 0x3708c,
2457                 0x3709c, 0x370ac,
2458                 0x370c0, 0x370c0,
2459                 0x370c8, 0x370d0,
2460                 0x370d8, 0x370e0,
2461                 0x370ec, 0x3712c,
2462                 0x37134, 0x37150,
2463                 0x37158, 0x37158,
2464                 0x37160, 0x3718c,
2465                 0x3719c, 0x371ac,
2466                 0x371c0, 0x371c0,
2467                 0x371c8, 0x371d0,
2468                 0x371d8, 0x371e0,
2469                 0x371ec, 0x37290,
2470                 0x37298, 0x372c4,
2471                 0x372e4, 0x37390,
2472                 0x37398, 0x373c4,
2473                 0x373e4, 0x3742c,
2474                 0x37434, 0x37450,
2475                 0x37458, 0x37458,
2476                 0x37460, 0x3748c,
2477                 0x3749c, 0x374ac,
2478                 0x374c0, 0x374c0,
2479                 0x374c8, 0x374d0,
2480                 0x374d8, 0x374e0,
2481                 0x374ec, 0x3752c,
2482                 0x37534, 0x37550,
2483                 0x37558, 0x37558,
2484                 0x37560, 0x3758c,
2485                 0x3759c, 0x375ac,
2486                 0x375c0, 0x375c0,
2487                 0x375c8, 0x375d0,
2488                 0x375d8, 0x375e0,
2489                 0x375ec, 0x37690,
2490                 0x37698, 0x376c4,
2491                 0x376e4, 0x37790,
2492                 0x37798, 0x377c4,
2493                 0x377e4, 0x377fc,
2494                 0x37814, 0x37814,
2495                 0x37854, 0x37868,
2496                 0x37880, 0x3788c,
2497                 0x378c0, 0x378d0,
2498                 0x378e8, 0x378ec,
2499                 0x37900, 0x3792c,
2500                 0x37934, 0x37950,
2501                 0x37958, 0x37958,
2502                 0x37960, 0x3798c,
2503                 0x3799c, 0x379ac,
2504                 0x379c0, 0x379c0,
2505                 0x379c8, 0x379d0,
2506                 0x379d8, 0x379e0,
2507                 0x379ec, 0x37a90,
2508                 0x37a98, 0x37ac4,
2509                 0x37ae4, 0x37b10,
2510                 0x37b24, 0x37b28,
2511                 0x37b38, 0x37b50,
2512                 0x37bf0, 0x37c10,
2513                 0x37c24, 0x37c28,
2514                 0x37c38, 0x37c50,
2515                 0x37cf0, 0x37cfc,
2516                 0x40040, 0x40040,
2517                 0x40080, 0x40084,
2518                 0x40100, 0x40100,
2519                 0x40140, 0x401bc,
2520                 0x40200, 0x40214,
2521                 0x40228, 0x40228,
2522                 0x40240, 0x40258,
2523                 0x40280, 0x40280,
2524                 0x40304, 0x40304,
2525                 0x40330, 0x4033c,
2526                 0x41304, 0x413c8,
2527                 0x413d0, 0x413dc,
2528                 0x413f0, 0x413f0,
2529                 0x41400, 0x4140c,
2530                 0x41414, 0x4141c,
2531                 0x41480, 0x414d0,
2532                 0x44000, 0x4407c,
2533                 0x440c0, 0x441ac,
2534                 0x441b4, 0x4427c,
2535                 0x442c0, 0x443ac,
2536                 0x443b4, 0x4447c,
2537                 0x444c0, 0x445ac,
2538                 0x445b4, 0x4467c,
2539                 0x446c0, 0x447ac,
2540                 0x447b4, 0x4487c,
2541                 0x448c0, 0x449ac,
2542                 0x449b4, 0x44a7c,
2543                 0x44ac0, 0x44bac,
2544                 0x44bb4, 0x44c7c,
2545                 0x44cc0, 0x44dac,
2546                 0x44db4, 0x44e7c,
2547                 0x44ec0, 0x44fac,
2548                 0x44fb4, 0x4507c,
2549                 0x450c0, 0x451ac,
2550                 0x451b4, 0x451fc,
2551                 0x45800, 0x45804,
2552                 0x45810, 0x45830,
2553                 0x45840, 0x45860,
2554                 0x45868, 0x45868,
2555                 0x45880, 0x45884,
2556                 0x458a0, 0x458b0,
2557                 0x45a00, 0x45a04,
2558                 0x45a10, 0x45a30,
2559                 0x45a40, 0x45a60,
2560                 0x45a68, 0x45a68,
2561                 0x45a80, 0x45a84,
2562                 0x45aa0, 0x45ab0,
2563                 0x460c0, 0x460e4,
2564                 0x47000, 0x4703c,
2565                 0x47044, 0x4708c,
2566                 0x47200, 0x47250,
2567                 0x47400, 0x47408,
2568                 0x47414, 0x47420,
2569                 0x47600, 0x47618,
2570                 0x47800, 0x47814,
2571                 0x47820, 0x4782c,
2572                 0x50000, 0x50084,
2573                 0x50090, 0x500cc,
2574                 0x50300, 0x50384,
2575                 0x50400, 0x50400,
2576                 0x50800, 0x50884,
2577                 0x50890, 0x508cc,
2578                 0x50b00, 0x50b84,
2579                 0x50c00, 0x50c00,
2580                 0x51000, 0x51020,
2581                 0x51028, 0x510b0,
2582                 0x51300, 0x51324,
2583         };
2584
2585         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2586         const unsigned int *reg_ranges;
2587         int reg_ranges_size, range;
2588         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2589
2590         /* Select the right set of register ranges to dump depending on the
2591          * adapter chip type.
2592          */
2593         switch (chip_version) {
2594         case CHELSIO_T4:
2595                 reg_ranges = t4_reg_ranges;
2596                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2597                 break;
2598
2599         case CHELSIO_T5:
2600                 reg_ranges = t5_reg_ranges;
2601                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2602                 break;
2603
2604         case CHELSIO_T6:
2605                 reg_ranges = t6_reg_ranges;
2606                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2607                 break;
2608
2609         default:
2610                 dev_err(adap->pdev_dev,
2611                         "Unsupported chip version %d\n", chip_version);
2612                 return;
2613         }
2614
2615         /* Clear the register buffer and insert the appropriate register
2616          * values selected by the above register ranges.
2617          */
2618         memset(buf, 0, buf_size);
2619         for (range = 0; range < reg_ranges_size; range += 2) {
2620                 unsigned int reg = reg_ranges[range];
2621                 unsigned int last_reg = reg_ranges[range + 1];
2622                 u32 *bufp = (u32 *)((char *)buf + reg);
2623
2624                 /* Iterate across the register range filling in the register
2625                  * buffer but don't write past the end of the register buffer.
2626                  */
2627                 while (reg <= last_reg && bufp < buf_end) {
2628                         *bufp++ = t4_read_reg(adap, reg);
2629                         reg += sizeof(u32);
2630                 }
2631         }
2632 }
2633
2634 #define EEPROM_STAT_ADDR   0x7bfc
2635 #define VPD_BASE           0x400
2636 #define VPD_BASE_OLD       0
2637 #define VPD_LEN            1024
2638 #define CHELSIO_VPD_UNIQUE_ID 0x82
2639
2640 /**
2641  *      t4_seeprom_wp - enable/disable EEPROM write protection
2642  *      @adapter: the adapter
2643  *      @enable: whether to enable or disable write protection
2644  *
2645  *      Enables or disables write protection on the serial EEPROM.
2646  */
2647 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2648 {
2649         unsigned int v = enable ? 0xc : 0;
2650         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2651         return ret < 0 ? ret : 0;
2652 }
2653
2654 /**
2655  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2656  *      @adapter: adapter to read
2657  *      @p: where to store the parameters
2658  *
2659  *      Reads card parameters stored in VPD EEPROM.
2660  */
2661 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2662 {
2663         int i, ret = 0, addr;
2664         int ec, sn, pn, na;
2665         u8 *vpd, csum;
2666         unsigned int vpdr_len, kw_offset, id_len;
2667
2668         vpd = vmalloc(VPD_LEN);
2669         if (!vpd)
2670                 return -ENOMEM;
2671
2672         /* Card information normally starts at VPD_BASE but early cards had
2673          * it at 0.
2674          */
2675         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2676         if (ret < 0)
2677                 goto out;
2678
2679         /* The VPD shall have a unique identifier specified by the PCI SIG.
2680          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2681          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2682          * is expected to automatically put this entry at the
2683          * beginning of the VPD.
2684          */
2685         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2686
2687         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2688         if (ret < 0)
2689                 goto out;
2690
2691         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2692                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2693                 ret = -EINVAL;
2694                 goto out;
2695         }
2696
2697         id_len = pci_vpd_lrdt_size(vpd);
2698         if (id_len > ID_LEN)
2699                 id_len = ID_LEN;
2700
2701         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2702         if (i < 0) {
2703                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2704                 ret = -EINVAL;
2705                 goto out;
2706         }
2707
2708         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2709         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2710         if (vpdr_len + kw_offset > VPD_LEN) {
2711                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2712                 ret = -EINVAL;
2713                 goto out;
2714         }
2715
2716 #define FIND_VPD_KW(var, name) do { \
2717         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2718         if (var < 0) { \
2719                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2720                 ret = -EINVAL; \
2721                 goto out; \
2722         } \
2723         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2724 } while (0)
2725
2726         FIND_VPD_KW(i, "RV");
2727         for (csum = 0; i >= 0; i--)
2728                 csum += vpd[i];
2729
2730         if (csum) {
2731                 dev_err(adapter->pdev_dev,
2732                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2733                 ret = -EINVAL;
2734                 goto out;
2735         }
2736
2737         FIND_VPD_KW(ec, "EC");
2738         FIND_VPD_KW(sn, "SN");
2739         FIND_VPD_KW(pn, "PN");
2740         FIND_VPD_KW(na, "NA");
2741 #undef FIND_VPD_KW
2742
2743         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2744         strim(p->id);
2745         memcpy(p->ec, vpd + ec, EC_LEN);
2746         strim(p->ec);
2747         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2748         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2749         strim(p->sn);
2750         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2751         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2752         strim(p->pn);
2753         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2754         strim((char *)p->na);
2755
2756 out:
2757         vfree(vpd);
2758         return ret < 0 ? ret : 0;
2759 }
2760
2761 /**
2762  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2763  *      @adapter: adapter to read
2764  *      @p: where to store the parameters
2765  *
2766  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2767  *      Clock.  This can only be called after a connection to the firmware
2768  *      is established.
2769  */
2770 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2771 {
2772         u32 cclk_param, cclk_val;
2773         int ret;
2774
2775         /* Grab the raw VPD parameters.
2776          */
2777         ret = t4_get_raw_vpd_params(adapter, p);
2778         if (ret)
2779                 return ret;
2780
2781         /* Ask firmware for the Core Clock since it knows how to translate the
2782          * Reference Clock ('V2') VPD field into a Core Clock value ...
2783          */
2784         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2785                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2786         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2787                               1, &cclk_param, &cclk_val);
2788
2789         if (ret)
2790                 return ret;
2791         p->cclk = cclk_val;
2792
2793         return 0;
2794 }
2795
2796 /* serial flash and firmware constants */
2797 enum {
2798         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2799
2800         /* flash command opcodes */
2801         SF_PROG_PAGE    = 2,          /* program page */
2802         SF_WR_DISABLE   = 4,          /* disable writes */
2803         SF_RD_STATUS    = 5,          /* read status register */
2804         SF_WR_ENABLE    = 6,          /* enable writes */
2805         SF_RD_DATA_FAST = 0xb,        /* read flash */
2806         SF_RD_ID        = 0x9f,       /* read ID */
2807         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2808
2809         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2810 };
2811
2812 /**
2813  *      sf1_read - read data from the serial flash
2814  *      @adapter: the adapter
2815  *      @byte_cnt: number of bytes to read
2816  *      @cont: whether another operation will be chained
2817  *      @lock: whether to lock SF for PL access only
2818  *      @valp: where to store the read data
2819  *
2820  *      Reads up to 4 bytes of data from the serial flash.  The location of
2821  *      the read needs to be specified prior to calling this by issuing the
2822  *      appropriate commands to the serial flash.
2823  */
2824 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2825                     int lock, u32 *valp)
2826 {
2827         int ret;
2828
2829         if (!byte_cnt || byte_cnt > 4)
2830                 return -EINVAL;
2831         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2832                 return -EBUSY;
2833         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2834                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2835         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2836         if (!ret)
2837                 *valp = t4_read_reg(adapter, SF_DATA_A);
2838         return ret;
2839 }
2840
2841 /**
2842  *      sf1_write - write data to the serial flash
2843  *      @adapter: the adapter
2844  *      @byte_cnt: number of bytes to write
2845  *      @cont: whether another operation will be chained
2846  *      @lock: whether to lock SF for PL access only
2847  *      @val: value to write
2848  *
2849  *      Writes up to 4 bytes of data to the serial flash.  The location of
2850  *      the write needs to be specified prior to calling this by issuing the
2851  *      appropriate commands to the serial flash.
2852  */
2853 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2854                      int lock, u32 val)
2855 {
2856         if (!byte_cnt || byte_cnt > 4)
2857                 return -EINVAL;
2858         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2859                 return -EBUSY;
2860         t4_write_reg(adapter, SF_DATA_A, val);
2861         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2862                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2863         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2864 }
2865
2866 /**
2867  *      flash_wait_op - wait for a flash operation to complete
2868  *      @adapter: the adapter
2869  *      @attempts: max number of polls of the status register
2870  *      @delay: delay between polls in ms
2871  *
2872  *      Wait for a flash operation to complete by polling the status register.
2873  */
2874 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2875 {
2876         int ret;
2877         u32 status;
2878
2879         while (1) {
2880                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2881                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2882                         return ret;
2883                 if (!(status & 1))
2884                         return 0;
2885                 if (--attempts == 0)
2886                         return -EAGAIN;
2887                 if (delay)
2888                         msleep(delay);
2889         }
2890 }
2891
2892 /**
2893  *      t4_read_flash - read words from serial flash
2894  *      @adapter: the adapter
2895  *      @addr: the start address for the read
2896  *      @nwords: how many 32-bit words to read
2897  *      @data: where to store the read data
2898  *      @byte_oriented: whether to store data as bytes or as words
2899  *
2900  *      Read the specified number of 32-bit words from the serial flash.
2901  *      If @byte_oriented is set the read data is stored as a byte array
2902  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2903  *      natural endianness.
2904  */
2905 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2906                   unsigned int nwords, u32 *data, int byte_oriented)
2907 {
2908         int ret;
2909
2910         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2911                 return -EINVAL;
2912
2913         addr = swab32(addr) | SF_RD_DATA_FAST;
2914
2915         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2916             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2917                 return ret;
2918
2919         for ( ; nwords; nwords--, data++) {
2920                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2921                 if (nwords == 1)
2922                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2923                 if (ret)
2924                         return ret;
2925                 if (byte_oriented)
2926                         *data = (__force __u32)(cpu_to_be32(*data));
2927         }
2928         return 0;
2929 }
2930
2931 /**
2932  *      t4_write_flash - write up to a page of data to the serial flash
2933  *      @adapter: the adapter
2934  *      @addr: the start address to write
2935  *      @n: length of data to write in bytes
2936  *      @data: the data to write
2937  *
2938  *      Writes up to a page of data (256 bytes) to the serial flash starting
2939  *      at the given address.  All the data must be written to the same page.
2940  */
2941 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2942                           unsigned int n, const u8 *data)
2943 {
2944         int ret;
2945         u32 buf[64];
2946         unsigned int i, c, left, val, offset = addr & 0xff;
2947
2948         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2949                 return -EINVAL;
2950
2951         val = swab32(addr) | SF_PROG_PAGE;
2952
2953         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2954             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2955                 goto unlock;
2956
2957         for (left = n; left; left -= c) {
2958                 c = min(left, 4U);
2959                 for (val = 0, i = 0; i < c; ++i)
2960                         val = (val << 8) + *data++;
2961
2962                 ret = sf1_write(adapter, c, c != left, 1, val);
2963                 if (ret)
2964                         goto unlock;
2965         }
2966         ret = flash_wait_op(adapter, 8, 1);
2967         if (ret)
2968                 goto unlock;
2969
2970         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2971
2972         /* Read the page to verify the write succeeded */
2973         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2974         if (ret)
2975                 return ret;
2976
2977         if (memcmp(data - n, (u8 *)buf + offset, n)) {
2978                 dev_err(adapter->pdev_dev,
2979                         "failed to correctly write the flash page at %#x\n",
2980                         addr);
2981                 return -EIO;
2982         }
2983         return 0;
2984
2985 unlock:
2986         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2987         return ret;
2988 }
2989
2990 /**
2991  *      t4_get_fw_version - read the firmware version
2992  *      @adapter: the adapter
2993  *      @vers: where to place the version
2994  *
2995  *      Reads the FW version from flash.
2996  */
2997 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2998 {
2999         return t4_read_flash(adapter, FLASH_FW_START +
3000                              offsetof(struct fw_hdr, fw_ver), 1,
3001                              vers, 0);
3002 }
3003
3004 /**
3005  *      t4_get_bs_version - read the firmware bootstrap version
3006  *      @adapter: the adapter
3007  *      @vers: where to place the version
3008  *
3009  *      Reads the FW Bootstrap version from flash.
3010  */
3011 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3012 {
3013         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3014                              offsetof(struct fw_hdr, fw_ver), 1,
3015                              vers, 0);
3016 }
3017
3018 /**
3019  *      t4_get_tp_version - read the TP microcode version
3020  *      @adapter: the adapter
3021  *      @vers: where to place the version
3022  *
3023  *      Reads the TP microcode version from flash.
3024  */
3025 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3026 {
3027         return t4_read_flash(adapter, FLASH_FW_START +
3028                              offsetof(struct fw_hdr, tp_microcode_ver),
3029                              1, vers, 0);
3030 }
3031
3032 /**
3033  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3034  *      @adapter: the adapter
3035  *      @vers: where to place the version
3036  *
3037  *      Reads the Expansion ROM header from FLASH and returns the version
3038  *      number (if present) through the @vers return value pointer.  We return
3039  *      this in the Firmware Version Format since it's convenient.  Return
3040  *      0 on success, -ENOENT if no Expansion ROM is present.
3041  */
3042 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3043 {
3044         struct exprom_header {
3045                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3046                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3047         } *hdr;
3048         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3049                                            sizeof(u32))];
3050         int ret;
3051
3052         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3053                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3054                             0);
3055         if (ret)
3056                 return ret;
3057
3058         hdr = (struct exprom_header *)exprom_header_buf;
3059         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3060                 return -ENOENT;
3061
3062         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3063                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3064                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3065                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3066         return 0;
3067 }
3068
3069 /**
3070  *      t4_get_vpd_version - return the VPD version
3071  *      @adapter: the adapter
3072  *      @vers: where to place the version
3073  *
3074  *      Reads the VPD via the Firmware interface (thus this can only be called
3075  *      once we're ready to issue Firmware commands).  The format of the
3076  *      VPD version is adapter specific.  Returns 0 on success, an error on
3077  *      failure.
3078  *
3079  *      Note that early versions of the Firmware didn't include the ability
3080  *      to retrieve the VPD version, so we zero-out the return-value parameter
3081  *      in that case to avoid leaving it with garbage in it.
3082  *
3083  *      Also note that the Firmware will return its cached copy of the VPD
3084  *      Revision ID, not the actual Revision ID as written in the Serial
3085  *      EEPROM.  This is only an issue if a new VPD has been written and the
3086  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3087  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3088  *      if the Host Driver will be performing a full adapter initialization.
3089  */
3090 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3091 {
3092         u32 vpdrev_param;
3093         int ret;
3094
3095         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3096                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3097         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3098                               1, &vpdrev_param, vers);
3099         if (ret)
3100                 *vers = 0;
3101         return ret;
3102 }
3103
3104 /**
3105  *      t4_get_scfg_version - return the Serial Configuration version
3106  *      @adapter: the adapter
3107  *      @vers: where to place the version
3108  *
3109  *      Reads the Serial Configuration Version via the Firmware interface
3110  *      (thus this can only be called once we're ready to issue Firmware
3111  *      commands).  The format of the Serial Configuration version is
3112  *      adapter specific.  Returns 0 on success, an error on failure.
3113  *
3114  *      Note that early versions of the Firmware didn't include the ability
3115  *      to retrieve the Serial Configuration version, so we zero-out the
3116  *      return-value parameter in that case to avoid leaving it with
3117  *      garbage in it.
3118  *
3119  *      Also note that the Firmware will return its cached copy of the Serial
3120  *      Initialization Revision ID, not the actual Revision ID as written in
3121  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3122  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3123  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3124  *      been issued if the Host Driver will be performing a full adapter
3125  *      initialization.
3126  */
3127 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3128 {
3129         u32 scfgrev_param;
3130         int ret;
3131
3132         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3133                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3134         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3135                               1, &scfgrev_param, vers);
3136         if (ret)
3137                 *vers = 0;
3138         return ret;
3139 }
3140
3141 /**
3142  *      t4_get_version_info - extract various chip/firmware version information
3143  *      @adapter: the adapter
3144  *
3145  *      Reads various chip/firmware version numbers and stores them into the
3146  *      adapter Adapter Parameters structure.  If any of the efforts fails
3147  *      the first failure will be returned, but all of the version numbers
3148  *      will be read.
3149  */
3150 int t4_get_version_info(struct adapter *adapter)
3151 {
3152         int ret = 0;
3153
3154         #define FIRST_RET(__getvinfo) \
3155         do { \
3156                 int __ret = __getvinfo; \
3157                 if (__ret && !ret) \
3158                         ret = __ret; \
3159         } while (0)
3160
3161         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3162         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3163         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3164         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3165         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3166         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3167
3168         #undef FIRST_RET
3169         return ret;
3170 }
3171
3172 /**
3173  *      t4_dump_version_info - dump all of the adapter configuration IDs
3174  *      @adapter: the adapter
3175  *
3176  *      Dumps all of the various bits of adapter configuration version/revision
3177  *      IDs information.  This is typically called at some point after
3178  *      t4_get_version_info() has been called.
3179  */
3180 void t4_dump_version_info(struct adapter *adapter)
3181 {
3182         /* Device information */
3183         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3184                  adapter->params.vpd.id,
3185                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3186         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3187                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3188
3189         /* Firmware Version */
3190         if (!adapter->params.fw_vers)
3191                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3192         else
3193                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3194                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3195                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3196                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3197                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3198
3199         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3200          * Firmware, so dev_info() is more appropriate here.)
3201          */
3202         if (!adapter->params.bs_vers)
3203                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3204         else
3205                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3206                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3207                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3208                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3209                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3210
3211         /* TP Microcode Version */
3212         if (!adapter->params.tp_vers)
3213                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3214         else
3215                 dev_info(adapter->pdev_dev,
3216                          "TP Microcode version: %u.%u.%u.%u\n",
3217                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3218                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3219                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3220                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3221
3222         /* Expansion ROM version */
3223         if (!adapter->params.er_vers)
3224                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3225         else
3226                 dev_info(adapter->pdev_dev,
3227                          "Expansion ROM version: %u.%u.%u.%u\n",
3228                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3229                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3230                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3231                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3232
3233         /* Serial Configuration version */
3234         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3235                  adapter->params.scfg_vers);
3236
3237         /* VPD Version */
3238         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3239                  adapter->params.vpd_vers);
3240 }
3241
3242 /**
3243  *      t4_check_fw_version - check if the FW is supported with this driver
3244  *      @adap: the adapter
3245  *
3246  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3247  *      if there's exact match, a negative error if the version could not be
3248  *      read or there's a major version mismatch
3249  */
3250 int t4_check_fw_version(struct adapter *adap)
3251 {
3252         int i, ret, major, minor, micro;
3253         int exp_major, exp_minor, exp_micro;
3254         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3255
3256         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3257         /* Try multiple times before returning error */
3258         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3259                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3260
3261         if (ret)
3262                 return ret;
3263
3264         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3265         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3266         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3267
3268         switch (chip_version) {
3269         case CHELSIO_T4:
3270                 exp_major = T4FW_MIN_VERSION_MAJOR;
3271                 exp_minor = T4FW_MIN_VERSION_MINOR;
3272                 exp_micro = T4FW_MIN_VERSION_MICRO;
3273                 break;
3274         case CHELSIO_T5:
3275                 exp_major = T5FW_MIN_VERSION_MAJOR;
3276                 exp_minor = T5FW_MIN_VERSION_MINOR;
3277                 exp_micro = T5FW_MIN_VERSION_MICRO;
3278                 break;
3279         case CHELSIO_T6:
3280                 exp_major = T6FW_MIN_VERSION_MAJOR;
3281                 exp_minor = T6FW_MIN_VERSION_MINOR;
3282                 exp_micro = T6FW_MIN_VERSION_MICRO;
3283                 break;
3284         default:
3285                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3286                         adap->chip);
3287                 return -EINVAL;
3288         }
3289
3290         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3291             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3292                 dev_err(adap->pdev_dev,
3293                         "Card has firmware version %u.%u.%u, minimum "
3294                         "supported firmware is %u.%u.%u.\n", major, minor,
3295                         micro, exp_major, exp_minor, exp_micro);
3296                 return -EFAULT;
3297         }
3298         return 0;
3299 }
3300
3301 /* Is the given firmware API compatible with the one the driver was compiled
3302  * with?
3303  */
3304 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3305 {
3306
3307         /* short circuit if it's the exact same firmware version */
3308         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3309                 return 1;
3310
3311 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3312         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3313             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3314                 return 1;
3315 #undef SAME_INTF
3316
3317         return 0;
3318 }
3319
3320 /* The firmware in the filesystem is usable, but should it be installed?
3321  * This routine explains itself in detail if it indicates the filesystem
3322  * firmware should be installed.
3323  */
3324 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3325                                 int k, int c)
3326 {
3327         const char *reason;
3328
3329         if (!card_fw_usable) {
3330                 reason = "incompatible or unusable";
3331                 goto install;
3332         }
3333
3334         if (k > c) {
3335                 reason = "older than the version supported with this driver";
3336                 goto install;
3337         }
3338
3339         return 0;
3340
3341 install:
3342         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3343                 "installing firmware %u.%u.%u.%u on card.\n",
3344                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3345                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3346                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3347                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3348
3349         return 1;
3350 }
3351
3352 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3353                const u8 *fw_data, unsigned int fw_size,
3354                struct fw_hdr *card_fw, enum dev_state state,
3355                int *reset)
3356 {
3357         int ret, card_fw_usable, fs_fw_usable;
3358         const struct fw_hdr *fs_fw;
3359         const struct fw_hdr *drv_fw;
3360
3361         drv_fw = &fw_info->fw_hdr;
3362
3363         /* Read the header of the firmware on the card */
3364         ret = t4_read_flash(adap, FLASH_FW_START,
3365                             sizeof(*card_fw) / sizeof(uint32_t),
3366                             (uint32_t *)card_fw, 1);
3367         if (ret == 0) {
3368                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3369         } else {
3370                 dev_err(adap->pdev_dev,
3371                         "Unable to read card's firmware header: %d\n", ret);
3372                 card_fw_usable = 0;
3373         }
3374
3375         if (fw_data != NULL) {
3376                 fs_fw = (const void *)fw_data;
3377                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3378         } else {
3379                 fs_fw = NULL;
3380                 fs_fw_usable = 0;
3381         }
3382
3383         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3384             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3385                 /* Common case: the firmware on the card is an exact match and
3386                  * the filesystem one is an exact match too, or the filesystem
3387                  * one is absent/incompatible.
3388                  */
3389         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3390                    should_install_fs_fw(adap, card_fw_usable,
3391                                         be32_to_cpu(fs_fw->fw_ver),
3392                                         be32_to_cpu(card_fw->fw_ver))) {
3393                 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3394                                     fw_size, 0);
3395                 if (ret != 0) {
3396                         dev_err(adap->pdev_dev,
3397                                 "failed to install firmware: %d\n", ret);
3398                         goto bye;
3399                 }
3400
3401                 /* Installed successfully, update the cached header too. */
3402                 *card_fw = *fs_fw;
3403                 card_fw_usable = 1;
3404                 *reset = 0;     /* already reset as part of load_fw */
3405         }
3406
3407         if (!card_fw_usable) {
3408                 uint32_t d, c, k;
3409
3410                 d = be32_to_cpu(drv_fw->fw_ver);
3411                 c = be32_to_cpu(card_fw->fw_ver);
3412                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3413
3414                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3415                         "chip state %d, "
3416                         "driver compiled with %d.%d.%d.%d, "
3417                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3418                         state,
3419                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3420                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3421                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3422                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3423                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3424                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3425                 ret = -EINVAL;
3426                 goto bye;
3427         }
3428
3429         /* We're using whatever's on the card and it's known to be good. */
3430         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3431         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3432
3433 bye:
3434         return ret;
3435 }
3436
3437 /**
3438  *      t4_flash_erase_sectors - erase a range of flash sectors
3439  *      @adapter: the adapter
3440  *      @start: the first sector to erase
3441  *      @end: the last sector to erase
3442  *
3443  *      Erases the sectors in the given inclusive range.
3444  */
3445 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3446 {
3447         int ret = 0;
3448
3449         if (end >= adapter->params.sf_nsec)
3450                 return -EINVAL;
3451
3452         while (start <= end) {
3453                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3454                     (ret = sf1_write(adapter, 4, 0, 1,
3455                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3456                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3457                         dev_err(adapter->pdev_dev,
3458                                 "erase of flash sector %d failed, error %d\n",
3459                                 start, ret);
3460                         break;
3461                 }
3462                 start++;
3463         }
3464         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3465         return ret;
3466 }
3467
3468 /**
3469  *      t4_flash_cfg_addr - return the address of the flash configuration file
3470  *      @adapter: the adapter
3471  *
3472  *      Return the address within the flash where the Firmware Configuration
3473  *      File is stored.
3474  */
3475 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3476 {
3477         if (adapter->params.sf_size == 0x100000)
3478                 return FLASH_FPGA_CFG_START;
3479         else
3480                 return FLASH_CFG_START;
3481 }
3482
3483 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3484  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3485  * and emit an error message for mismatched firmware to save our caller the
3486  * effort ...
3487  */
3488 static bool t4_fw_matches_chip(const struct adapter *adap,
3489                                const struct fw_hdr *hdr)
3490 {
3491         /* The expression below will return FALSE for any unsupported adapter
3492          * which will keep us "honest" in the future ...
3493          */
3494         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3495             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3496             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3497                 return true;
3498
3499         dev_err(adap->pdev_dev,
3500                 "FW image (%d) is not suitable for this adapter (%d)\n",
3501                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3502         return false;
3503 }
3504
3505 /**
3506  *      t4_load_fw - download firmware
3507  *      @adap: the adapter
3508  *      @fw_data: the firmware image to write
3509  *      @size: image size
3510  *
3511  *      Write the supplied firmware image to the card's serial flash.
3512  */
3513 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3514 {
3515         u32 csum;
3516         int ret, addr;
3517         unsigned int i;
3518         u8 first_page[SF_PAGE_SIZE];
3519         const __be32 *p = (const __be32 *)fw_data;
3520         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3521         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3522         unsigned int fw_img_start = adap->params.sf_fw_start;
3523         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3524
3525         if (!size) {
3526                 dev_err(adap->pdev_dev, "FW image has no data\n");
3527                 return -EINVAL;
3528         }
3529         if (size & 511) {
3530                 dev_err(adap->pdev_dev,
3531                         "FW image size not multiple of 512 bytes\n");
3532                 return -EINVAL;
3533         }
3534         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3535                 dev_err(adap->pdev_dev,
3536                         "FW image size differs from size in FW header\n");
3537                 return -EINVAL;
3538         }
3539         if (size > FW_MAX_SIZE) {
3540                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3541                         FW_MAX_SIZE);
3542                 return -EFBIG;
3543         }
3544         if (!t4_fw_matches_chip(adap, hdr))
3545                 return -EINVAL;
3546
3547         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3548                 csum += be32_to_cpu(p[i]);
3549
3550         if (csum != 0xffffffff) {
3551                 dev_err(adap->pdev_dev,
3552                         "corrupted firmware image, checksum %#x\n", csum);
3553                 return -EINVAL;
3554         }
3555
3556         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3557         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3558         if (ret)
3559                 goto out;
3560
3561         /*
3562          * We write the correct version at the end so the driver can see a bad
3563          * version if the FW write fails.  Start by writing a copy of the
3564          * first page with a bad version.
3565          */
3566         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3567         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3568         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3569         if (ret)
3570                 goto out;
3571
3572         addr = fw_img_start;
3573         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3574                 addr += SF_PAGE_SIZE;
3575                 fw_data += SF_PAGE_SIZE;
3576                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3577                 if (ret)
3578                         goto out;
3579         }
3580
3581         ret = t4_write_flash(adap,
3582                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3583                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3584 out:
3585         if (ret)
3586                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3587                         ret);
3588         else
3589                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3590         return ret;
3591 }
3592
3593 /**
3594  *      t4_phy_fw_ver - return current PHY firmware version
3595  *      @adap: the adapter
3596  *      @phy_fw_ver: return value buffer for PHY firmware version
3597  *
3598  *      Returns the current version of external PHY firmware on the
3599  *      adapter.
3600  */
3601 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3602 {
3603         u32 param, val;
3604         int ret;
3605
3606         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3607                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3608                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3609                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3610         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3611                               &param, &val);
3612         if (ret)
3613                 return ret;
3614         *phy_fw_ver = val;
3615         return 0;
3616 }
3617
3618 /**
3619  *      t4_load_phy_fw - download port PHY firmware
3620  *      @adap: the adapter
3621  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3622  *      @win_lock: the lock to use to guard the memory copy
3623  *      @phy_fw_version: function to check PHY firmware versions
3624  *      @phy_fw_data: the PHY firmware image to write
3625  *      @phy_fw_size: image size
3626  *
3627  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3628  *      @phy_fw_version is supplied, then it will be used to determine if
3629  *      it's necessary to perform the transfer by comparing the version
3630  *      of any existing adapter PHY firmware with that of the passed in
3631  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3632  *      around the call to t4_memory_rw() which transfers the PHY firmware
3633  *      to the adapter.
3634  *
3635  *      A negative error number will be returned if an error occurs.  If
3636  *      version number support is available and there's no need to upgrade
3637  *      the firmware, 0 will be returned.  If firmware is successfully
3638  *      transferred to the adapter, 1 will be retured.
3639  *
3640  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3641  *      a result, a RESET of the adapter would cause that RAM to lose its
3642  *      contents.  Thus, loading PHY firmware on such adapters must happen
3643  *      after any FW_RESET_CMDs ...
3644  */
3645 int t4_load_phy_fw(struct adapter *adap,
3646                    int win, spinlock_t *win_lock,
3647                    int (*phy_fw_version)(const u8 *, size_t),
3648                    const u8 *phy_fw_data, size_t phy_fw_size)
3649 {
3650         unsigned long mtype = 0, maddr = 0;
3651         u32 param, val;
3652         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3653         int ret;
3654
3655         /* If we have version number support, then check to see if the adapter
3656          * already has up-to-date PHY firmware loaded.
3657          */
3658          if (phy_fw_version) {
3659                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3660                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3661                 if (ret < 0)
3662                         return ret;
3663
3664                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3665                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3666                                 "version %#x\n", cur_phy_fw_ver);
3667                         return 0;
3668                 }
3669         }
3670
3671         /* Ask the firmware where it wants us to copy the PHY firmware image.
3672          * The size of the file requires a special version of the READ coommand
3673          * which will pass the file size via the values field in PARAMS_CMD and
3674          * retrieve the return value from firmware and place it in the same
3675          * buffer values
3676          */
3677         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3678                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3679                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3680                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3681         val = phy_fw_size;
3682         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3683                                  &param, &val, 1, true);
3684         if (ret < 0)
3685                 return ret;
3686         mtype = val >> 8;
3687         maddr = (val & 0xff) << 16;
3688
3689         /* Copy the supplied PHY Firmware image to the adapter memory location
3690          * allocated by the adapter firmware.
3691          */
3692         if (win_lock)
3693                 spin_lock_bh(win_lock);
3694         ret = t4_memory_rw(adap, win, mtype, maddr,
3695                            phy_fw_size, (__be32 *)phy_fw_data,
3696                            T4_MEMORY_WRITE);
3697         if (win_lock)
3698                 spin_unlock_bh(win_lock);
3699         if (ret)
3700                 return ret;
3701
3702         /* Tell the firmware that the PHY firmware image has been written to
3703          * RAM and it can now start copying it over to the PHYs.  The chip
3704          * firmware will RESET the affected PHYs as part of this operation
3705          * leaving them running the new PHY firmware image.
3706          */
3707         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3708                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3709                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3710                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3711         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3712                                     &param, &val, 30000);
3713
3714         /* If we have version number support, then check to see that the new
3715          * firmware got loaded properly.
3716          */
3717         if (phy_fw_version) {
3718                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3719                 if (ret < 0)
3720                         return ret;
3721
3722                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3723                         CH_WARN(adap, "PHY Firmware did not update: "
3724                                 "version on adapter %#x, "
3725                                 "version flashed %#x\n",
3726                                 cur_phy_fw_ver, new_phy_fw_vers);
3727                         return -ENXIO;
3728                 }
3729         }
3730
3731         return 1;
3732 }
3733
3734 /**
3735  *      t4_fwcache - firmware cache operation
3736  *      @adap: the adapter
3737  *      @op  : the operation (flush or flush and invalidate)
3738  */
3739 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3740 {
3741         struct fw_params_cmd c;
3742
3743         memset(&c, 0, sizeof(c));
3744         c.op_to_vfn =
3745                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3746                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3747                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3748                             FW_PARAMS_CMD_VFN_V(0));
3749         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3750         c.param[0].mnem =
3751                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3752                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3753         c.param[0].val = cpu_to_be32(op);
3754
3755         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3756 }
3757
3758 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3759                         unsigned int *pif_req_wrptr,
3760                         unsigned int *pif_rsp_wrptr)
3761 {
3762         int i, j;
3763         u32 cfg, val, req, rsp;
3764
3765         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3766         if (cfg & LADBGEN_F)
3767                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3768
3769         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3770         req = POLADBGWRPTR_G(val);
3771         rsp = PILADBGWRPTR_G(val);
3772         if (pif_req_wrptr)
3773                 *pif_req_wrptr = req;
3774         if (pif_rsp_wrptr)
3775                 *pif_rsp_wrptr = rsp;
3776
3777         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3778                 for (j = 0; j < 6; j++) {
3779                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3780                                      PILADBGRDPTR_V(rsp));
3781                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3782                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3783                         req++;
3784                         rsp++;
3785                 }
3786                 req = (req + 2) & POLADBGRDPTR_M;
3787                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3788         }
3789         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3790 }
3791
3792 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3793 {
3794         u32 cfg;
3795         int i, j, idx;
3796
3797         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3798         if (cfg & LADBGEN_F)
3799                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3800
3801         for (i = 0; i < CIM_MALA_SIZE; i++) {
3802                 for (j = 0; j < 5; j++) {
3803                         idx = 8 * i + j;
3804                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3805                                      PILADBGRDPTR_V(idx));
3806                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3807                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3808                 }
3809         }
3810         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3811 }
3812
3813 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3814 {
3815         unsigned int i, j;
3816
3817         for (i = 0; i < 8; i++) {
3818                 u32 *p = la_buf + i;
3819
3820                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3821                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3822                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3823                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3824                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3825         }
3826 }
3827
3828 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3829                      FW_PORT_CAP32_ANEG)
3830
3831 /**
3832  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3833  *      @caps16: a 16-bit Port Capabilities value
3834  *
3835  *      Returns the equivalent 32-bit Port Capabilities value.
3836  */
3837 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3838 {
3839         fw_port_cap32_t caps32 = 0;
3840
3841         #define CAP16_TO_CAP32(__cap) \
3842                 do { \
3843                         if (caps16 & FW_PORT_CAP_##__cap) \
3844                                 caps32 |= FW_PORT_CAP32_##__cap; \
3845                 } while (0)
3846
3847         CAP16_TO_CAP32(SPEED_100M);
3848         CAP16_TO_CAP32(SPEED_1G);
3849         CAP16_TO_CAP32(SPEED_25G);
3850         CAP16_TO_CAP32(SPEED_10G);
3851         CAP16_TO_CAP32(SPEED_40G);
3852         CAP16_TO_CAP32(SPEED_100G);
3853         CAP16_TO_CAP32(FC_RX);
3854         CAP16_TO_CAP32(FC_TX);
3855         CAP16_TO_CAP32(ANEG);
3856         CAP16_TO_CAP32(MDIX);
3857         CAP16_TO_CAP32(MDIAUTO);
3858         CAP16_TO_CAP32(FEC_RS);
3859         CAP16_TO_CAP32(FEC_BASER_RS);
3860         CAP16_TO_CAP32(802_3_PAUSE);
3861         CAP16_TO_CAP32(802_3_ASM_DIR);
3862
3863         #undef CAP16_TO_CAP32
3864
3865         return caps32;
3866 }
3867
3868 /**
3869  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3870  *      @caps32: a 32-bit Port Capabilities value
3871  *
3872  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
3873  *      not all 32-bit Port Capabilities can be represented in the 16-bit
3874  *      Port Capabilities and some fields/values may not make it.
3875  */
3876 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3877 {
3878         fw_port_cap16_t caps16 = 0;
3879
3880         #define CAP32_TO_CAP16(__cap) \
3881                 do { \
3882                         if (caps32 & FW_PORT_CAP32_##__cap) \
3883                                 caps16 |= FW_PORT_CAP_##__cap; \
3884                 } while (0)
3885
3886         CAP32_TO_CAP16(SPEED_100M);
3887         CAP32_TO_CAP16(SPEED_1G);
3888         CAP32_TO_CAP16(SPEED_10G);
3889         CAP32_TO_CAP16(SPEED_25G);
3890         CAP32_TO_CAP16(SPEED_40G);
3891         CAP32_TO_CAP16(SPEED_100G);
3892         CAP32_TO_CAP16(FC_RX);
3893         CAP32_TO_CAP16(FC_TX);
3894         CAP32_TO_CAP16(802_3_PAUSE);
3895         CAP32_TO_CAP16(802_3_ASM_DIR);
3896         CAP32_TO_CAP16(ANEG);
3897         CAP32_TO_CAP16(MDIX);
3898         CAP32_TO_CAP16(MDIAUTO);
3899         CAP32_TO_CAP16(FEC_RS);
3900         CAP32_TO_CAP16(FEC_BASER_RS);
3901
3902         #undef CAP32_TO_CAP16
3903
3904         return caps16;
3905 }
3906
3907 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3908 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
3909 {
3910         enum cc_pause cc_pause = 0;
3911
3912         if (fw_pause & FW_PORT_CAP32_FC_RX)
3913                 cc_pause |= PAUSE_RX;
3914         if (fw_pause & FW_PORT_CAP32_FC_TX)
3915                 cc_pause |= PAUSE_TX;
3916
3917         return cc_pause;
3918 }
3919
3920 /* Translate Common Code Pause specification into Firmware Port Capabilities */
3921 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
3922 {
3923         fw_port_cap32_t fw_pause = 0;
3924
3925         if (cc_pause & PAUSE_RX)
3926                 fw_pause |= FW_PORT_CAP32_FC_RX;
3927         if (cc_pause & PAUSE_TX)
3928                 fw_pause |= FW_PORT_CAP32_FC_TX;
3929
3930         return fw_pause;
3931 }
3932
3933 /* Translate Firmware Forward Error Correction specification to Common Code */
3934 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
3935 {
3936         enum cc_fec cc_fec = 0;
3937
3938         if (fw_fec & FW_PORT_CAP32_FEC_RS)
3939                 cc_fec |= FEC_RS;
3940         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
3941                 cc_fec |= FEC_BASER_RS;
3942
3943         return cc_fec;
3944 }
3945
3946 /* Translate Common Code Forward Error Correction specification to Firmware */
3947 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
3948 {
3949         fw_port_cap32_t fw_fec = 0;
3950
3951         if (cc_fec & FEC_RS)
3952                 fw_fec |= FW_PORT_CAP32_FEC_RS;
3953         if (cc_fec & FEC_BASER_RS)
3954                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
3955
3956         return fw_fec;
3957 }
3958
3959 /**
3960  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3961  *      @adapter: the adapter
3962  *      @mbox: the Firmware Mailbox to use
3963  *      @port: the Port ID
3964  *      @lc: the Port's Link Configuration
3965  *
3966  *      Set up a port's MAC and PHY according to a desired link configuration.
3967  *      - If the PHY can auto-negotiate first decide what to advertise, then
3968  *        enable/disable auto-negotiation as desired, and reset.
3969  *      - If the PHY does not auto-negotiate just reset it.
3970  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3971  *        otherwise do it later based on the outcome of auto-negotiation.
3972  */
3973 int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
3974                   unsigned int port, struct link_config *lc)
3975 {
3976         unsigned int fw_caps = adapter->params.fw_caps_support;
3977         struct fw_port_cmd cmd;
3978         unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
3979         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
3980
3981         lc->link_ok = 0;
3982
3983         /* Convert driver coding of Pause Frame Flow Control settings into the
3984          * Firmware's API.
3985          */
3986         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
3987
3988         /* Convert Common Code Forward Error Control settings into the
3989          * Firmware's API.  If the current Requested FEC has "Automatic"
3990          * (IEEE 802.3) specified, then we use whatever the Firmware
3991          * sent us as part of it's IEEE 802.3-based interpratation of
3992          * the Transceiver Module EPROM FEC parameters.  Otherwise we
3993          * use whatever is in the current Requested FEC settings.
3994          */
3995         if (lc->requested_fec & FEC_AUTO)
3996                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
3997         else
3998                 cc_fec = lc->requested_fec;
3999         fw_fec = cc_to_fwcap_fec(cc_fec);
4000
4001         /* Figure out what our Requested Port Capabilities are going to be.
4002          */
4003         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4004                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
4005                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4006                 lc->fec = cc_fec;
4007         } else if (lc->autoneg == AUTONEG_DISABLE) {
4008                 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4009                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4010                 lc->fec = cc_fec;
4011         } else {
4012                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4013         }
4014
4015         /* And send that on to the Firmware ...
4016          */
4017         memset(&cmd, 0, sizeof(cmd));
4018         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4019                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4020                                        FW_PORT_CMD_PORTID_V(port));
4021         cmd.action_to_len16 =
4022                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4023                                                  ? FW_PORT_ACTION_L1_CFG
4024                                                  : FW_PORT_ACTION_L1_CFG32) |
4025                             FW_LEN16(cmd));
4026         if (fw_caps == FW_CAPS16)
4027                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4028         else
4029                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4030         return t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4031 }
4032
4033 /**
4034  *      t4_restart_aneg - restart autonegotiation
4035  *      @adap: the adapter
4036  *      @mbox: mbox to use for the FW command
4037  *      @port: the port id
4038  *
4039  *      Restarts autonegotiation for the selected port.
4040  */
4041 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4042 {
4043         struct fw_port_cmd c;
4044
4045         memset(&c, 0, sizeof(c));
4046         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4047                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4048                                      FW_PORT_CMD_PORTID_V(port));
4049         c.action_to_len16 =
4050                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4051                             FW_LEN16(c));
4052         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4053         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4054 }
4055
4056 typedef void (*int_handler_t)(struct adapter *adap);
4057
4058 struct intr_info {
4059         unsigned int mask;       /* bits to check in interrupt status */
4060         const char *msg;         /* message to print or NULL */
4061         short stat_idx;          /* stat counter to increment or -1 */
4062         unsigned short fatal;    /* whether the condition reported is fatal */
4063         int_handler_t int_handler; /* platform-specific int handler */
4064 };
4065
4066 /**
4067  *      t4_handle_intr_status - table driven interrupt handler
4068  *      @adapter: the adapter that generated the interrupt
4069  *      @reg: the interrupt status register to process
4070  *      @acts: table of interrupt actions
4071  *
4072  *      A table driven interrupt handler that applies a set of masks to an
4073  *      interrupt status word and performs the corresponding actions if the
4074  *      interrupts described by the mask have occurred.  The actions include
4075  *      optionally emitting a warning or alert message.  The table is terminated
4076  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4077  *      conditions.
4078  */
4079 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4080                                  const struct intr_info *acts)
4081 {
4082         int fatal = 0;
4083         unsigned int mask = 0;
4084         unsigned int status = t4_read_reg(adapter, reg);
4085
4086         for ( ; acts->mask; ++acts) {
4087                 if (!(status & acts->mask))
4088                         continue;
4089                 if (acts->fatal) {
4090                         fatal++;
4091                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4092                                   status & acts->mask);
4093                 } else if (acts->msg && printk_ratelimit())
4094                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4095                                  status & acts->mask);
4096                 if (acts->int_handler)
4097                         acts->int_handler(adapter);
4098                 mask |= acts->mask;
4099         }
4100         status &= mask;
4101         if (status)                           /* clear processed interrupts */
4102                 t4_write_reg(adapter, reg, status);
4103         return fatal;
4104 }
4105
4106 /*
4107  * Interrupt handler for the PCIE module.
4108  */
4109 static void pcie_intr_handler(struct adapter *adapter)
4110 {
4111         static const struct intr_info sysbus_intr_info[] = {
4112                 { RNPP_F, "RXNP array parity error", -1, 1 },
4113                 { RPCP_F, "RXPC array parity error", -1, 1 },
4114                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4115                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4116                 { RFTP_F, "RXFT array parity error", -1, 1 },
4117                 { 0 }
4118         };
4119         static const struct intr_info pcie_port_intr_info[] = {
4120                 { TPCP_F, "TXPC array parity error", -1, 1 },
4121                 { TNPP_F, "TXNP array parity error", -1, 1 },
4122                 { TFTP_F, "TXFT array parity error", -1, 1 },
4123                 { TCAP_F, "TXCA array parity error", -1, 1 },
4124                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4125                 { RCAP_F, "RXCA array parity error", -1, 1 },
4126                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4127                 { RDPE_F, "Rx data parity error", -1, 1 },
4128                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4129                 { 0 }
4130         };
4131         static const struct intr_info pcie_intr_info[] = {
4132                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4133                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4134                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4135                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4136                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4137                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4138                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4139                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4140                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4141                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4142                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4143                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4144                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4145                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4146                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4147                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4148                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4149                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4150                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4151                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4152                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4153                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4154                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4155                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4156                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4157                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4158                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4159                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4160                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4161                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4162                   -1, 0 },
4163                 { 0 }
4164         };
4165
4166         static struct intr_info t5_pcie_intr_info[] = {
4167                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4168                   -1, 1 },
4169                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4170                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4171                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4172                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4173                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4174                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4175                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4176                   -1, 1 },
4177                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4178                   -1, 1 },
4179                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4180                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4181                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4182                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4183                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4184                   -1, 1 },
4185                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4186                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4187                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4188                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4189                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4190                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4191                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4192                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4193                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4194                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4195                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4196                   -1, 1 },
4197                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4198                   -1, 1 },
4199                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4200                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4201                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4202                 { READRSPERR_F, "Outbound read error", -1, 0 },
4203                 { 0 }
4204         };
4205
4206         int fat;
4207
4208         if (is_t4(adapter->params.chip))
4209                 fat = t4_handle_intr_status(adapter,
4210                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4211                                 sysbus_intr_info) +
4212                         t4_handle_intr_status(adapter,
4213                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4214                                         pcie_port_intr_info) +
4215                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4216                                               pcie_intr_info);
4217         else
4218                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4219                                             t5_pcie_intr_info);
4220
4221         if (fat)
4222                 t4_fatal_err(adapter);
4223 }
4224
4225 /*
4226  * TP interrupt handler.
4227  */
4228 static void tp_intr_handler(struct adapter *adapter)
4229 {
4230         static const struct intr_info tp_intr_info[] = {
4231                 { 0x3fffffff, "TP parity error", -1, 1 },
4232                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4233                 { 0 }
4234         };
4235
4236         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4237                 t4_fatal_err(adapter);
4238 }
4239
4240 /*
4241  * SGE interrupt handler.
4242  */
4243 static void sge_intr_handler(struct adapter *adapter)
4244 {
4245         u64 v;
4246         u32 err;
4247
4248         static const struct intr_info sge_intr_info[] = {
4249                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4250                   "SGE received CPL exceeding IQE size", -1, 1 },
4251                 { ERR_INVALID_CIDX_INC_F,
4252                   "SGE GTS CIDX increment too large", -1, 0 },
4253                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4254                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4255                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4256                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4257                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4258                   0 },
4259                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4260                   0 },
4261                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4262                   0 },
4263                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4264                   0 },
4265                 { ERR_ING_CTXT_PRIO_F,
4266                   "SGE too many priority ingress contexts", -1, 0 },
4267                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4268                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4269                 { 0 }
4270         };
4271
4272         static struct intr_info t4t5_sge_intr_info[] = {
4273                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4274                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4275                 { ERR_EGR_CTXT_PRIO_F,
4276                   "SGE too many priority egress contexts", -1, 0 },
4277                 { 0 }
4278         };
4279
4280         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4281                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4282         if (v) {
4283                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4284                                 (unsigned long long)v);
4285                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4286                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4287         }
4288
4289         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4290         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4291                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4292                                            t4t5_sge_intr_info);
4293
4294         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4295         if (err & ERROR_QID_VALID_F) {
4296                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4297                         ERROR_QID_G(err));
4298                 if (err & UNCAPTURED_ERROR_F)
4299                         dev_err(adapter->pdev_dev,
4300                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4301                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4302                              UNCAPTURED_ERROR_F);
4303         }
4304
4305         if (v != 0)
4306                 t4_fatal_err(adapter);
4307 }
4308
4309 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4310                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4311 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4312                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4313
4314 /*
4315  * CIM interrupt handler.
4316  */
4317 static void cim_intr_handler(struct adapter *adapter)
4318 {
4319         static const struct intr_info cim_intr_info[] = {
4320                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4321                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4322                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4323                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4324                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4325                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4326                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4327                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4328                 { 0 }
4329         };
4330         static const struct intr_info cim_upintr_info[] = {
4331                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4332                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4333                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4334                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4335                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4336                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4337                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4338                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4339                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4340                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4341                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4342                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4343                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4344                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4345                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4346                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4347                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4348                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4349                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4350                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4351                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4352                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4353                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4354                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4355                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4356                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4357                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4358                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4359                 { 0 }
4360         };
4361
4362         u32 val, fw_err;
4363         int fat;
4364
4365         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4366         if (fw_err & PCIE_FW_ERR_F)
4367                 t4_report_fw_error(adapter);
4368
4369         /* When the Firmware detects an internal error which normally
4370          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4371          * in order to make sure the Host sees the Firmware Crash.  So
4372          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4373          * ignore the Timer0 interrupt.
4374          */
4375
4376         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4377         if (val & TIMER0INT_F)
4378                 if (!(fw_err & PCIE_FW_ERR_F) ||
4379                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4380                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4381                                      TIMER0INT_F);
4382
4383         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4384                                     cim_intr_info) +
4385               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4386                                     cim_upintr_info);
4387         if (fat)
4388                 t4_fatal_err(adapter);
4389 }
4390
4391 /*
4392  * ULP RX interrupt handler.
4393  */
4394 static void ulprx_intr_handler(struct adapter *adapter)
4395 {
4396         static const struct intr_info ulprx_intr_info[] = {
4397                 { 0x1800000, "ULPRX context error", -1, 1 },
4398                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4399                 { 0 }
4400         };
4401
4402         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4403                 t4_fatal_err(adapter);
4404 }
4405
4406 /*
4407  * ULP TX interrupt handler.
4408  */
4409 static void ulptx_intr_handler(struct adapter *adapter)
4410 {
4411         static const struct intr_info ulptx_intr_info[] = {
4412                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4413                   0 },
4414                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4415                   0 },
4416                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4417                   0 },
4418                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4419                   0 },
4420                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4421                 { 0 }
4422         };
4423
4424         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4425                 t4_fatal_err(adapter);
4426 }
4427
4428 /*
4429  * PM TX interrupt handler.
4430  */
4431 static void pmtx_intr_handler(struct adapter *adapter)
4432 {
4433         static const struct intr_info pmtx_intr_info[] = {
4434                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4435                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4436                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4437                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4438                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4439                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4440                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4441                   -1, 1 },
4442                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4443                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4444                 { 0 }
4445         };
4446
4447         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4448                 t4_fatal_err(adapter);
4449 }
4450
4451 /*
4452  * PM RX interrupt handler.
4453  */
4454 static void pmrx_intr_handler(struct adapter *adapter)
4455 {
4456         static const struct intr_info pmrx_intr_info[] = {
4457                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4458                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4459                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4460                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4461                   -1, 1 },
4462                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4463                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4464                 { 0 }
4465         };
4466
4467         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4468                 t4_fatal_err(adapter);
4469 }
4470
4471 /*
4472  * CPL switch interrupt handler.
4473  */
4474 static void cplsw_intr_handler(struct adapter *adapter)
4475 {
4476         static const struct intr_info cplsw_intr_info[] = {
4477                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4478                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4479                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4480                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4481                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4482                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4483                 { 0 }
4484         };
4485
4486         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4487                 t4_fatal_err(adapter);
4488 }
4489
4490 /*
4491  * LE interrupt handler.
4492  */
4493 static void le_intr_handler(struct adapter *adap)
4494 {
4495         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4496         static const struct intr_info le_intr_info[] = {
4497                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4498                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4499                 { PARITYERR_F, "LE parity error", -1, 1 },
4500                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4501                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4502                 { 0 }
4503         };
4504
4505         static struct intr_info t6_le_intr_info[] = {
4506                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4507                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4508                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4509                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4510                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4511                 { 0 }
4512         };
4513
4514         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4515                                   (chip <= CHELSIO_T5) ?
4516                                   le_intr_info : t6_le_intr_info))
4517                 t4_fatal_err(adap);
4518 }
4519
4520 /*
4521  * MPS interrupt handler.
4522  */
4523 static void mps_intr_handler(struct adapter *adapter)
4524 {
4525         static const struct intr_info mps_rx_intr_info[] = {
4526                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4527                 { 0 }
4528         };
4529         static const struct intr_info mps_tx_intr_info[] = {
4530                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4531                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4532                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4533                   -1, 1 },
4534                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4535                   -1, 1 },
4536                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4537                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4538                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4539                 { 0 }
4540         };
4541         static const struct intr_info t6_mps_tx_intr_info[] = {
4542                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4543                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4544                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4545                   -1, 1 },
4546                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4547                   -1, 1 },
4548                 /* MPS Tx Bubble is normal for T6 */
4549                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4550                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4551                 { 0 }
4552         };
4553         static const struct intr_info mps_trc_intr_info[] = {
4554                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4555                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4556                   -1, 1 },
4557                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4558                 { 0 }
4559         };
4560         static const struct intr_info mps_stat_sram_intr_info[] = {
4561                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4562                 { 0 }
4563         };
4564         static const struct intr_info mps_stat_tx_intr_info[] = {
4565                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4566                 { 0 }
4567         };
4568         static const struct intr_info mps_stat_rx_intr_info[] = {
4569                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4570                 { 0 }
4571         };
4572         static const struct intr_info mps_cls_intr_info[] = {
4573                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4574                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4575                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4576                 { 0 }
4577         };
4578
4579         int fat;
4580
4581         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4582                                     mps_rx_intr_info) +
4583               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4584                                     is_t6(adapter->params.chip)
4585                                     ? t6_mps_tx_intr_info
4586                                     : mps_tx_intr_info) +
4587               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4588                                     mps_trc_intr_info) +
4589               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4590                                     mps_stat_sram_intr_info) +
4591               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4592                                     mps_stat_tx_intr_info) +
4593               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4594                                     mps_stat_rx_intr_info) +
4595               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4596                                     mps_cls_intr_info);
4597
4598         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4599         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4600         if (fat)
4601                 t4_fatal_err(adapter);
4602 }
4603
4604 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4605                       ECC_UE_INT_CAUSE_F)
4606
4607 /*
4608  * EDC/MC interrupt handler.
4609  */
4610 static void mem_intr_handler(struct adapter *adapter, int idx)
4611 {
4612         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4613
4614         unsigned int addr, cnt_addr, v;
4615
4616         if (idx <= MEM_EDC1) {
4617                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4618                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4619         } else if (idx == MEM_MC) {
4620                 if (is_t4(adapter->params.chip)) {
4621                         addr = MC_INT_CAUSE_A;
4622                         cnt_addr = MC_ECC_STATUS_A;
4623                 } else {
4624                         addr = MC_P_INT_CAUSE_A;
4625                         cnt_addr = MC_P_ECC_STATUS_A;
4626                 }
4627         } else {
4628                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4629                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4630         }
4631
4632         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4633         if (v & PERR_INT_CAUSE_F)
4634                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4635                           name[idx]);
4636         if (v & ECC_CE_INT_CAUSE_F) {
4637                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4638
4639                 t4_edc_err_read(adapter, idx);
4640
4641                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4642                 if (printk_ratelimit())
4643                         dev_warn(adapter->pdev_dev,
4644                                  "%u %s correctable ECC data error%s\n",
4645                                  cnt, name[idx], cnt > 1 ? "s" : "");
4646         }
4647         if (v & ECC_UE_INT_CAUSE_F)
4648                 dev_alert(adapter->pdev_dev,
4649                           "%s uncorrectable ECC data error\n", name[idx]);
4650
4651         t4_write_reg(adapter, addr, v);
4652         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4653                 t4_fatal_err(adapter);
4654 }
4655
4656 /*
4657  * MA interrupt handler.
4658  */
4659 static void ma_intr_handler(struct adapter *adap)
4660 {
4661         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4662
4663         if (status & MEM_PERR_INT_CAUSE_F) {
4664                 dev_alert(adap->pdev_dev,
4665                           "MA parity error, parity status %#x\n",
4666                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4667                 if (is_t5(adap->params.chip))
4668                         dev_alert(adap->pdev_dev,
4669                                   "MA parity error, parity status %#x\n",
4670                                   t4_read_reg(adap,
4671                                               MA_PARITY_ERROR_STATUS2_A));
4672         }
4673         if (status & MEM_WRAP_INT_CAUSE_F) {
4674                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4675                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4676                           "client %u to address %#x\n",
4677                           MEM_WRAP_CLIENT_NUM_G(v),
4678                           MEM_WRAP_ADDRESS_G(v) << 4);
4679         }
4680         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4681         t4_fatal_err(adap);
4682 }
4683
4684 /*
4685  * SMB interrupt handler.
4686  */
4687 static void smb_intr_handler(struct adapter *adap)
4688 {
4689         static const struct intr_info smb_intr_info[] = {
4690                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4691                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4692                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4693                 { 0 }
4694         };
4695
4696         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4697                 t4_fatal_err(adap);
4698 }
4699
4700 /*
4701  * NC-SI interrupt handler.
4702  */
4703 static void ncsi_intr_handler(struct adapter *adap)
4704 {
4705         static const struct intr_info ncsi_intr_info[] = {
4706                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4707                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4708                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4709                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4710                 { 0 }
4711         };
4712
4713         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4714                 t4_fatal_err(adap);
4715 }
4716
4717 /*
4718  * XGMAC interrupt handler.
4719  */
4720 static void xgmac_intr_handler(struct adapter *adap, int port)
4721 {
4722         u32 v, int_cause_reg;
4723
4724         if (is_t4(adap->params.chip))
4725                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4726         else
4727                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4728
4729         v = t4_read_reg(adap, int_cause_reg);
4730
4731         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4732         if (!v)
4733                 return;
4734
4735         if (v & TXFIFO_PRTY_ERR_F)
4736                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4737                           port);
4738         if (v & RXFIFO_PRTY_ERR_F)
4739                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4740                           port);
4741         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4742         t4_fatal_err(adap);
4743 }
4744
4745 /*
4746  * PL interrupt handler.
4747  */
4748 static void pl_intr_handler(struct adapter *adap)
4749 {
4750         static const struct intr_info pl_intr_info[] = {
4751                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4752                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4753                 { 0 }
4754         };
4755
4756         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4757                 t4_fatal_err(adap);
4758 }
4759
4760 #define PF_INTR_MASK (PFSW_F)
4761 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4762                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4763                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4764
4765 /**
4766  *      t4_slow_intr_handler - control path interrupt handler
4767  *      @adapter: the adapter
4768  *
4769  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4770  *      The designation 'slow' is because it involves register reads, while
4771  *      data interrupts typically don't involve any MMIOs.
4772  */
4773 int t4_slow_intr_handler(struct adapter *adapter)
4774 {
4775         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4776
4777         if (!(cause & GLBL_INTR_MASK))
4778                 return 0;
4779         if (cause & CIM_F)
4780                 cim_intr_handler(adapter);
4781         if (cause & MPS_F)
4782                 mps_intr_handler(adapter);
4783         if (cause & NCSI_F)
4784                 ncsi_intr_handler(adapter);
4785         if (cause & PL_F)
4786                 pl_intr_handler(adapter);
4787         if (cause & SMB_F)
4788                 smb_intr_handler(adapter);
4789         if (cause & XGMAC0_F)
4790                 xgmac_intr_handler(adapter, 0);
4791         if (cause & XGMAC1_F)
4792                 xgmac_intr_handler(adapter, 1);
4793         if (cause & XGMAC_KR0_F)
4794                 xgmac_intr_handler(adapter, 2);
4795         if (cause & XGMAC_KR1_F)
4796                 xgmac_intr_handler(adapter, 3);
4797         if (cause & PCIE_F)
4798                 pcie_intr_handler(adapter);
4799         if (cause & MC_F)
4800                 mem_intr_handler(adapter, MEM_MC);
4801         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4802                 mem_intr_handler(adapter, MEM_MC1);
4803         if (cause & EDC0_F)
4804                 mem_intr_handler(adapter, MEM_EDC0);
4805         if (cause & EDC1_F)
4806                 mem_intr_handler(adapter, MEM_EDC1);
4807         if (cause & LE_F)
4808                 le_intr_handler(adapter);
4809         if (cause & TP_F)
4810                 tp_intr_handler(adapter);
4811         if (cause & MA_F)
4812                 ma_intr_handler(adapter);
4813         if (cause & PM_TX_F)
4814                 pmtx_intr_handler(adapter);
4815         if (cause & PM_RX_F)
4816                 pmrx_intr_handler(adapter);
4817         if (cause & ULP_RX_F)
4818                 ulprx_intr_handler(adapter);
4819         if (cause & CPL_SWITCH_F)
4820                 cplsw_intr_handler(adapter);
4821         if (cause & SGE_F)
4822                 sge_intr_handler(adapter);
4823         if (cause & ULP_TX_F)
4824                 ulptx_intr_handler(adapter);
4825
4826         /* Clear the interrupts just processed for which we are the master. */
4827         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4828         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4829         return 1;
4830 }
4831
4832 /**
4833  *      t4_intr_enable - enable interrupts
4834  *      @adapter: the adapter whose interrupts should be enabled
4835  *
4836  *      Enable PF-specific interrupts for the calling function and the top-level
4837  *      interrupt concentrator for global interrupts.  Interrupts are already
4838  *      enabled at each module, here we just enable the roots of the interrupt
4839  *      hierarchies.
4840  *
4841  *      Note: this function should be called only when the driver manages
4842  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4843  *      function at a time should be doing this.
4844  */
4845 void t4_intr_enable(struct adapter *adapter)
4846 {
4847         u32 val = 0;
4848         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4849         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4850                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4851
4852         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4853                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4854         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4855                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4856                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4857                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4858                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4859                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4860                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4861         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4862         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4863 }
4864
4865 /**
4866  *      t4_intr_disable - disable interrupts
4867  *      @adapter: the adapter whose interrupts should be disabled
4868  *
4869  *      Disable interrupts.  We only disable the top-level interrupt
4870  *      concentrators.  The caller must be a PCI function managing global
4871  *      interrupts.
4872  */
4873 void t4_intr_disable(struct adapter *adapter)
4874 {
4875         u32 whoami, pf;
4876
4877         if (pci_channel_offline(adapter->pdev))
4878                 return;
4879
4880         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4881         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4882                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4883
4884         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4885         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4886 }
4887
4888 /**
4889  *      t4_config_rss_range - configure a portion of the RSS mapping table
4890  *      @adapter: the adapter
4891  *      @mbox: mbox to use for the FW command
4892  *      @viid: virtual interface whose RSS subtable is to be written
4893  *      @start: start entry in the table to write
4894  *      @n: how many table entries to write
4895  *      @rspq: values for the response queue lookup table
4896  *      @nrspq: number of values in @rspq
4897  *
4898  *      Programs the selected part of the VI's RSS mapping table with the
4899  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4900  *      until the full table range is populated.
4901  *
4902  *      The caller must ensure the values in @rspq are in the range allowed for
4903  *      @viid.
4904  */
4905 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4906                         int start, int n, const u16 *rspq, unsigned int nrspq)
4907 {
4908         int ret;
4909         const u16 *rsp = rspq;
4910         const u16 *rsp_end = rspq + nrspq;
4911         struct fw_rss_ind_tbl_cmd cmd;
4912
4913         memset(&cmd, 0, sizeof(cmd));
4914         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4915                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4916                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4917         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4918
4919         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4920         while (n > 0) {
4921                 int nq = min(n, 32);
4922                 __be32 *qp = &cmd.iq0_to_iq2;
4923
4924                 cmd.niqid = cpu_to_be16(nq);
4925                 cmd.startidx = cpu_to_be16(start);
4926
4927                 start += nq;
4928                 n -= nq;
4929
4930                 while (nq > 0) {
4931                         unsigned int v;
4932
4933                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4934                         if (++rsp >= rsp_end)
4935                                 rsp = rspq;
4936                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4937                         if (++rsp >= rsp_end)
4938                                 rsp = rspq;
4939                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4940                         if (++rsp >= rsp_end)
4941                                 rsp = rspq;
4942
4943                         *qp++ = cpu_to_be32(v);
4944                         nq -= 3;
4945                 }
4946
4947                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4948                 if (ret)
4949                         return ret;
4950         }
4951         return 0;
4952 }
4953
4954 /**
4955  *      t4_config_glbl_rss - configure the global RSS mode
4956  *      @adapter: the adapter
4957  *      @mbox: mbox to use for the FW command
4958  *      @mode: global RSS mode
4959  *      @flags: mode-specific flags
4960  *
4961  *      Sets the global RSS mode.
4962  */
4963 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4964                        unsigned int flags)
4965 {
4966         struct fw_rss_glb_config_cmd c;
4967
4968         memset(&c, 0, sizeof(c));
4969         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4970                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4971         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4972         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4973                 c.u.manual.mode_pkd =
4974                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4975         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4976                 c.u.basicvirtual.mode_pkd =
4977                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4978                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4979         } else
4980                 return -EINVAL;
4981         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4982 }
4983
4984 /**
4985  *      t4_config_vi_rss - configure per VI RSS settings
4986  *      @adapter: the adapter
4987  *      @mbox: mbox to use for the FW command
4988  *      @viid: the VI id
4989  *      @flags: RSS flags
4990  *      @defq: id of the default RSS queue for the VI.
4991  *
4992  *      Configures VI-specific RSS properties.
4993  */
4994 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4995                      unsigned int flags, unsigned int defq)
4996 {
4997         struct fw_rss_vi_config_cmd c;
4998
4999         memset(&c, 0, sizeof(c));
5000         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5001                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5002                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5003         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5004         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5005                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5006         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5007 }
5008
5009 /* Read an RSS table row */
5010 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5011 {
5012         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5013         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5014                                    5, 0, val);
5015 }
5016
5017 /**
5018  *      t4_read_rss - read the contents of the RSS mapping table
5019  *      @adapter: the adapter
5020  *      @map: holds the contents of the RSS mapping table
5021  *
5022  *      Reads the contents of the RSS hash->queue mapping table.
5023  */
5024 int t4_read_rss(struct adapter *adapter, u16 *map)
5025 {
5026         u32 val;
5027         int i, ret;
5028
5029         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5030                 ret = rd_rss_row(adapter, i, &val);
5031                 if (ret)
5032                         return ret;
5033                 *map++ = LKPTBLQUEUE0_G(val);
5034                 *map++ = LKPTBLQUEUE1_G(val);
5035         }
5036         return 0;
5037 }
5038
5039 static unsigned int t4_use_ldst(struct adapter *adap)
5040 {
5041         return (adap->flags & FW_OK) || !adap->use_bd;
5042 }
5043
5044 /**
5045  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
5046  *      @adap: the adapter
5047  *      @vals: where the indirect register values are stored/written
5048  *      @nregs: how many indirect registers to read/write
5049  *      @start_idx: index of first indirect register to read/write
5050  *      @rw: Read (1) or Write (0)
5051  *
5052  *      Access TP PIO registers through LDST
5053  */
5054 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
5055                             unsigned int start_index, unsigned int rw)
5056 {
5057         int ret, i;
5058         int cmd = FW_LDST_ADDRSPC_TP_PIO;
5059         struct fw_ldst_cmd c;
5060
5061         for (i = 0 ; i < nregs; i++) {
5062                 memset(&c, 0, sizeof(c));
5063                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5064                                                 FW_CMD_REQUEST_F |
5065                                                 (rw ? FW_CMD_READ_F :
5066                                                       FW_CMD_WRITE_F) |
5067                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5068                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5069
5070                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5071                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5072                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
5073                 if (!ret && rw)
5074                         vals[i] = be32_to_cpu(c.u.addrval.val);
5075         }
5076 }
5077
5078 /**
5079  *      t4_read_rss_key - read the global RSS key
5080  *      @adap: the adapter
5081  *      @key: 10-entry array holding the 320-bit RSS key
5082  *
5083  *      Reads the global 320-bit RSS key.
5084  */
5085 void t4_read_rss_key(struct adapter *adap, u32 *key)
5086 {
5087         if (t4_use_ldst(adap))
5088                 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
5089         else
5090                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
5091                                  TP_RSS_SECRET_KEY0_A);
5092 }
5093
5094 /**
5095  *      t4_write_rss_key - program one of the RSS keys
5096  *      @adap: the adapter
5097  *      @key: 10-entry array holding the 320-bit RSS key
5098  *      @idx: which RSS key to write
5099  *
5100  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5101  *      0..15 the corresponding entry in the RSS key table is written,
5102  *      otherwise the global RSS key is written.
5103  */
5104 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
5105 {
5106         u8 rss_key_addr_cnt = 16;
5107         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5108
5109         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5110          * allows access to key addresses 16-63 by using KeyWrAddrX
5111          * as index[5:4](upper 2) into key table
5112          */
5113         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5114             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5115                 rss_key_addr_cnt = 32;
5116
5117         if (t4_use_ldst(adap))
5118                 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
5119         else
5120                 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
5121                                   TP_RSS_SECRET_KEY0_A);
5122
5123         if (idx >= 0 && idx < rss_key_addr_cnt) {
5124                 if (rss_key_addr_cnt > 16)
5125                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5126                                      KEYWRADDRX_V(idx >> 4) |
5127                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5128                 else
5129                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5130                                      KEYWRADDR_V(idx) | KEYWREN_F);
5131         }
5132 }
5133
5134 /**
5135  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5136  *      @adapter: the adapter
5137  *      @index: the entry in the PF RSS table to read
5138  *      @valp: where to store the returned value
5139  *
5140  *      Reads the PF RSS Configuration Table at the specified index and returns
5141  *      the value found there.
5142  */
5143 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5144                            u32 *valp)
5145 {
5146         if (t4_use_ldst(adapter))
5147                 t4_fw_tp_pio_rw(adapter, valp, 1,
5148                                 TP_RSS_PF0_CONFIG_A + index, 1);
5149         else
5150                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5151                                  valp, 1, TP_RSS_PF0_CONFIG_A + index);
5152 }
5153
5154 /**
5155  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5156  *      @adapter: the adapter
5157  *      @index: the entry in the VF RSS table to read
5158  *      @vfl: where to store the returned VFL
5159  *      @vfh: where to store the returned VFH
5160  *
5161  *      Reads the VF RSS Configuration Table at the specified index and returns
5162  *      the (VFL, VFH) values found there.
5163  */
5164 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5165                            u32 *vfl, u32 *vfh)
5166 {
5167         u32 vrt, mask, data;
5168
5169         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5170                 mask = VFWRADDR_V(VFWRADDR_M);
5171                 data = VFWRADDR_V(index);
5172         } else {
5173                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5174                  data = T6_VFWRADDR_V(index);
5175         }
5176
5177         /* Request that the index'th VF Table values be read into VFL/VFH.
5178          */
5179         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5180         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5181         vrt |= data | VFRDEN_F;
5182         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5183
5184         /* Grab the VFL/VFH values ...
5185          */
5186         if (t4_use_ldst(adapter)) {
5187                 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
5188                 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
5189         } else {
5190                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5191                                  vfl, 1, TP_RSS_VFL_CONFIG_A);
5192                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5193                                  vfh, 1, TP_RSS_VFH_CONFIG_A);
5194         }
5195 }
5196
5197 /**
5198  *      t4_read_rss_pf_map - read PF RSS Map
5199  *      @adapter: the adapter
5200  *
5201  *      Reads the PF RSS Map register and returns its value.
5202  */
5203 u32 t4_read_rss_pf_map(struct adapter *adapter)
5204 {
5205         u32 pfmap;
5206
5207         if (t4_use_ldst(adapter))
5208                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
5209         else
5210                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5211                                  &pfmap, 1, TP_RSS_PF_MAP_A);
5212         return pfmap;
5213 }
5214
5215 /**
5216  *      t4_read_rss_pf_mask - read PF RSS Mask
5217  *      @adapter: the adapter
5218  *
5219  *      Reads the PF RSS Mask register and returns its value.
5220  */
5221 u32 t4_read_rss_pf_mask(struct adapter *adapter)
5222 {
5223         u32 pfmask;
5224
5225         if (t4_use_ldst(adapter))
5226                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
5227         else
5228                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5229                                  &pfmask, 1, TP_RSS_PF_MSK_A);
5230         return pfmask;
5231 }
5232
5233 /**
5234  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5235  *      @adap: the adapter
5236  *      @v4: holds the TCP/IP counter values
5237  *      @v6: holds the TCP/IPv6 counter values
5238  *
5239  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5240  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5241  */
5242 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5243                          struct tp_tcp_stats *v6)
5244 {
5245         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5246
5247 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5248 #define STAT(x)     val[STAT_IDX(x)]
5249 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5250
5251         if (v4) {
5252                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5253                                  ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
5254                 v4->tcp_out_rsts = STAT(OUT_RST);
5255                 v4->tcp_in_segs  = STAT64(IN_SEG);
5256                 v4->tcp_out_segs = STAT64(OUT_SEG);
5257                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5258         }
5259         if (v6) {
5260                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5261                                  ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
5262                 v6->tcp_out_rsts = STAT(OUT_RST);
5263                 v6->tcp_in_segs  = STAT64(IN_SEG);
5264                 v6->tcp_out_segs = STAT64(OUT_SEG);
5265                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5266         }
5267 #undef STAT64
5268 #undef STAT
5269 #undef STAT_IDX
5270 }
5271
5272 /**
5273  *      t4_tp_get_err_stats - read TP's error MIB counters
5274  *      @adap: the adapter
5275  *      @st: holds the counter values
5276  *
5277  *      Returns the values of TP's error counters.
5278  */
5279 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
5280 {
5281         int nchan = adap->params.arch.nchan;
5282
5283         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5284                          st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
5285         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5286                          st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
5287         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5288                          st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
5289         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5290                          st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
5291         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5292                          st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
5293         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5294                          st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
5295         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5296                          st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
5297         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5298                          st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
5299
5300         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5301                          &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
5302 }
5303
5304 /**
5305  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5306  *      @adap: the adapter
5307  *      @st: holds the counter values
5308  *
5309  *      Returns the values of TP's CPL counters.
5310  */
5311 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
5312 {
5313         int nchan = adap->params.arch.nchan;
5314
5315         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
5316                          nchan, TP_MIB_CPL_IN_REQ_0_A);
5317         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
5318                          nchan, TP_MIB_CPL_OUT_RSP_0_A);
5319
5320 }
5321
5322 /**
5323  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5324  *      @adap: the adapter
5325  *      @st: holds the counter values
5326  *
5327  *      Returns the values of TP's RDMA counters.
5328  */
5329 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5330 {
5331         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5332                          2, TP_MIB_RQE_DFR_PKT_A);
5333 }
5334
5335 /**
5336  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5337  *      @adap: the adapter
5338  *      @idx: the port index
5339  *      @st: holds the counter values
5340  *
5341  *      Returns the values of TP's FCoE counters for the selected port.
5342  */
5343 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5344                        struct tp_fcoe_stats *st)
5345 {
5346         u32 val[2];
5347
5348         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5349                          1, TP_MIB_FCOE_DDP_0_A + idx);
5350         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5351                          1, TP_MIB_FCOE_DROP_0_A + idx);
5352         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5353                          2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5354         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5355 }
5356
5357 /**
5358  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5359  *      @adap: the adapter
5360  *      @st: holds the counter values
5361  *
5362  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5363  */
5364 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5365 {
5366         u32 val[4];
5367
5368         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5369                          TP_MIB_USM_PKTS_A);
5370         st->frames = val[0];
5371         st->drops = val[1];
5372         st->octets = ((u64)val[2] << 32) | val[3];
5373 }
5374
5375 /**
5376  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5377  *      @adap: the adapter
5378  *      @mtus: where to store the MTU values
5379  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5380  *
5381  *      Reads the HW path MTU table.
5382  */
5383 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5384 {
5385         u32 v;
5386         int i;
5387
5388         for (i = 0; i < NMTUS; ++i) {
5389                 t4_write_reg(adap, TP_MTU_TABLE_A,
5390                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5391                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5392                 mtus[i] = MTUVALUE_G(v);
5393                 if (mtu_log)
5394                         mtu_log[i] = MTUWIDTH_G(v);
5395         }
5396 }
5397
5398 /**
5399  *      t4_read_cong_tbl - reads the congestion control table
5400  *      @adap: the adapter
5401  *      @incr: where to store the alpha values
5402  *
5403  *      Reads the additive increments programmed into the HW congestion
5404  *      control table.
5405  */
5406 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5407 {
5408         unsigned int mtu, w;
5409
5410         for (mtu = 0; mtu < NMTUS; ++mtu)
5411                 for (w = 0; w < NCCTRL_WIN; ++w) {
5412                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5413                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5414                         incr[mtu][w] = (u16)t4_read_reg(adap,
5415                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5416                 }
5417 }
5418
5419 /**
5420  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5421  *      @adap: the adapter
5422  *      @addr: the indirect TP register address
5423  *      @mask: specifies the field within the register to modify
5424  *      @val: new value for the field
5425  *
5426  *      Sets a field of an indirect TP register to the given value.
5427  */
5428 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5429                             unsigned int mask, unsigned int val)
5430 {
5431         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5432         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5433         t4_write_reg(adap, TP_PIO_DATA_A, val);
5434 }
5435
5436 /**
5437  *      init_cong_ctrl - initialize congestion control parameters
5438  *      @a: the alpha values for congestion control
5439  *      @b: the beta values for congestion control
5440  *
5441  *      Initialize the congestion control parameters.
5442  */
5443 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5444 {
5445         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5446         a[9] = 2;
5447         a[10] = 3;
5448         a[11] = 4;
5449         a[12] = 5;
5450         a[13] = 6;
5451         a[14] = 7;
5452         a[15] = 8;
5453         a[16] = 9;
5454         a[17] = 10;
5455         a[18] = 14;
5456         a[19] = 17;
5457         a[20] = 21;
5458         a[21] = 25;
5459         a[22] = 30;
5460         a[23] = 35;
5461         a[24] = 45;
5462         a[25] = 60;
5463         a[26] = 80;
5464         a[27] = 100;
5465         a[28] = 200;
5466         a[29] = 300;
5467         a[30] = 400;
5468         a[31] = 500;
5469
5470         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5471         b[9] = b[10] = 1;
5472         b[11] = b[12] = 2;
5473         b[13] = b[14] = b[15] = b[16] = 3;
5474         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5475         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5476         b[28] = b[29] = 6;
5477         b[30] = b[31] = 7;
5478 }
5479
5480 /* The minimum additive increment value for the congestion control table */
5481 #define CC_MIN_INCR 2U
5482
5483 /**
5484  *      t4_load_mtus - write the MTU and congestion control HW tables
5485  *      @adap: the adapter
5486  *      @mtus: the values for the MTU table
5487  *      @alpha: the values for the congestion control alpha parameter
5488  *      @beta: the values for the congestion control beta parameter
5489  *
5490  *      Write the HW MTU table with the supplied MTUs and the high-speed
5491  *      congestion control table with the supplied alpha, beta, and MTUs.
5492  *      We write the two tables together because the additive increments
5493  *      depend on the MTUs.
5494  */
5495 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5496                   const unsigned short *alpha, const unsigned short *beta)
5497 {
5498         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5499                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5500                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5501                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5502         };
5503
5504         unsigned int i, w;
5505
5506         for (i = 0; i < NMTUS; ++i) {
5507                 unsigned int mtu = mtus[i];
5508                 unsigned int log2 = fls(mtu);
5509
5510                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5511                         log2--;
5512                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5513                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5514
5515                 for (w = 0; w < NCCTRL_WIN; ++w) {
5516                         unsigned int inc;
5517
5518                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5519                                   CC_MIN_INCR);
5520
5521                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5522                                      (w << 16) | (beta[w] << 13) | inc);
5523                 }
5524         }
5525 }
5526
5527 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5528  * clocks.  The formula is
5529  *
5530  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5531  *
5532  * which is equivalent to
5533  *
5534  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5535  */
5536 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5537 {
5538         u64 v = bytes256 * adap->params.vpd.cclk;
5539
5540         return v * 62 + v / 2;
5541 }
5542
5543 /**
5544  *      t4_get_chan_txrate - get the current per channel Tx rates
5545  *      @adap: the adapter
5546  *      @nic_rate: rates for NIC traffic
5547  *      @ofld_rate: rates for offloaded traffic
5548  *
5549  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5550  *      for each channel.
5551  */
5552 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5553 {
5554         u32 v;
5555
5556         v = t4_read_reg(adap, TP_TX_TRATE_A);
5557         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5558         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5559         if (adap->params.arch.nchan == NCHAN) {
5560                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5561                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5562         }
5563
5564         v = t4_read_reg(adap, TP_TX_ORATE_A);
5565         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5566         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5567         if (adap->params.arch.nchan == NCHAN) {
5568                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5569                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5570         }
5571 }
5572
5573 /**
5574  *      t4_set_trace_filter - configure one of the tracing filters
5575  *      @adap: the adapter
5576  *      @tp: the desired trace filter parameters
5577  *      @idx: which filter to configure
5578  *      @enable: whether to enable or disable the filter
5579  *
5580  *      Configures one of the tracing filters available in HW.  If @enable is
5581  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5582  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5583  */
5584 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5585                         int idx, int enable)
5586 {
5587         int i, ofst = idx * 4;
5588         u32 data_reg, mask_reg, cfg;
5589         u32 multitrc = TRCMULTIFILTER_F;
5590
5591         if (!enable) {
5592                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5593                 return 0;
5594         }
5595
5596         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5597         if (cfg & TRCMULTIFILTER_F) {
5598                 /* If multiple tracers are enabled, then maximum
5599                  * capture size is 2.5KB (FIFO size of a single channel)
5600                  * minus 2 flits for CPL_TRACE_PKT header.
5601                  */
5602                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5603                         return -EINVAL;
5604         } else {
5605                 /* If multiple tracers are disabled, to avoid deadlocks
5606                  * maximum packet capture size of 9600 bytes is recommended.
5607                  * Also in this mode, only trace0 can be enabled and running.
5608                  */
5609                 multitrc = 0;
5610                 if (tp->snap_len > 9600 || idx)
5611                         return -EINVAL;
5612         }
5613
5614         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5615             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5616             tp->min_len > TFMINPKTSIZE_M)
5617                 return -EINVAL;
5618
5619         /* stop the tracer we'll be changing */
5620         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5621
5622         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5623         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5624         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5625
5626         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5627                 t4_write_reg(adap, data_reg, tp->data[i]);
5628                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5629         }
5630         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5631                      TFCAPTUREMAX_V(tp->snap_len) |
5632                      TFMINPKTSIZE_V(tp->min_len));
5633         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5634                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5635                      (is_t4(adap->params.chip) ?
5636                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5637                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5638                      T5_TFINVERTMATCH_V(tp->invert)));
5639
5640         return 0;
5641 }
5642
5643 /**
5644  *      t4_get_trace_filter - query one of the tracing filters
5645  *      @adap: the adapter
5646  *      @tp: the current trace filter parameters
5647  *      @idx: which trace filter to query
5648  *      @enabled: non-zero if the filter is enabled
5649  *
5650  *      Returns the current settings of one of the HW tracing filters.
5651  */
5652 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5653                          int *enabled)
5654 {
5655         u32 ctla, ctlb;
5656         int i, ofst = idx * 4;
5657         u32 data_reg, mask_reg;
5658
5659         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5660         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5661
5662         if (is_t4(adap->params.chip)) {
5663                 *enabled = !!(ctla & TFEN_F);
5664                 tp->port =  TFPORT_G(ctla);
5665                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5666         } else {
5667                 *enabled = !!(ctla & T5_TFEN_F);
5668                 tp->port = T5_TFPORT_G(ctla);
5669                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5670         }
5671         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5672         tp->min_len = TFMINPKTSIZE_G(ctlb);
5673         tp->skip_ofst = TFOFFSET_G(ctla);
5674         tp->skip_len = TFLENGTH_G(ctla);
5675
5676         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5677         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5678         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5679
5680         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5681                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5682                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5683         }
5684 }
5685
5686 /**
5687  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5688  *      @adap: the adapter
5689  *      @cnt: where to store the count statistics
5690  *      @cycles: where to store the cycle statistics
5691  *
5692  *      Returns performance statistics from PMTX.
5693  */
5694 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5695 {
5696         int i;
5697         u32 data[2];
5698
5699         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5700                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5701                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5702                 if (is_t4(adap->params.chip)) {
5703                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5704                 } else {
5705                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5706                                          PM_TX_DBG_DATA_A, data, 2,
5707                                          PM_TX_DBG_STAT_MSB_A);
5708                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5709                 }
5710         }
5711 }
5712
5713 /**
5714  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5715  *      @adap: the adapter
5716  *      @cnt: where to store the count statistics
5717  *      @cycles: where to store the cycle statistics
5718  *
5719  *      Returns performance statistics from PMRX.
5720  */
5721 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5722 {
5723         int i;
5724         u32 data[2];
5725
5726         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5727                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5728                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5729                 if (is_t4(adap->params.chip)) {
5730                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5731                 } else {
5732                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5733                                          PM_RX_DBG_DATA_A, data, 2,
5734                                          PM_RX_DBG_STAT_MSB_A);
5735                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5736                 }
5737         }
5738 }
5739
5740 /**
5741  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5742  *      @adap: the adapter
5743  *      @pidx: the port index
5744  *
5745  *      Computes and returns a bitmap indicating which MPS buffer groups are
5746  *      associated with the given Port.  Bit i is set if buffer group i is
5747  *      used by the Port.
5748  */
5749 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5750                                               int pidx)
5751 {
5752         unsigned int chip_version, nports;
5753
5754         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5755         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5756
5757         switch (chip_version) {
5758         case CHELSIO_T4:
5759         case CHELSIO_T5:
5760                 switch (nports) {
5761                 case 1: return 0xf;
5762                 case 2: return 3 << (2 * pidx);
5763                 case 4: return 1 << pidx;
5764                 }
5765                 break;
5766
5767         case CHELSIO_T6:
5768                 switch (nports) {
5769                 case 2: return 1 << (2 * pidx);
5770                 }
5771                 break;
5772         }
5773
5774         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5775                 chip_version, nports);
5776
5777         return 0;
5778 }
5779
5780 /**
5781  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5782  *      @adapter: the adapter
5783  *      @pidx: the port index
5784  *
5785  *      Returns a bitmap indicating which MPS buffer groups are associated
5786  *      with the given Port.  Bit i is set if buffer group i is used by the
5787  *      Port.
5788  */
5789 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
5790 {
5791         u8 *mps_bg_map;
5792         unsigned int nports;
5793
5794         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5795         if (pidx >= nports) {
5796                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
5797                         pidx, nports);
5798                 return 0;
5799         }
5800
5801         /* If we've already retrieved/computed this, just return the result.
5802          */
5803         mps_bg_map = adapter->params.mps_bg_map;
5804         if (mps_bg_map[pidx])
5805                 return mps_bg_map[pidx];
5806
5807         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
5808          * If we're talking to such Firmware, let it tell us.  If the new
5809          * API isn't supported, revert back to old hardcoded way.  The value
5810          * obtained from Firmware is encoded in below format:
5811          *
5812          * val = (( MPSBGMAP[Port 3] << 24 ) |
5813          *        ( MPSBGMAP[Port 2] << 16 ) |
5814          *        ( MPSBGMAP[Port 1] <<  8 ) |
5815          *        ( MPSBGMAP[Port 0] <<  0 ))
5816          */
5817         if (adapter->flags & FW_OK) {
5818                 u32 param, val;
5819                 int ret;
5820
5821                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5822                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
5823                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
5824                                          0, 1, &param, &val);
5825                 if (!ret) {
5826                         int p;
5827
5828                         /* Store the BG Map for all of the Ports in order to
5829                          * avoid more calls to the Firmware in the future.
5830                          */
5831                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
5832                                 mps_bg_map[p] = val & 0xff;
5833
5834                         return mps_bg_map[pidx];
5835                 }
5836         }
5837
5838         /* Either we're not talking to the Firmware or we're dealing with
5839          * older Firmware which doesn't support the new API to get the MPS
5840          * Buffer Group Map.  Fall back to computing it ourselves.
5841          */
5842         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
5843         return mps_bg_map[pidx];
5844 }
5845
5846 /**
5847  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
5848  *      @adapter: the adapter
5849  *      @pidx: the port index
5850  *
5851  *      Returns a bitmap indicating which TP Ingress Channels are associated
5852  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
5853  *      the Port.
5854  */
5855 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
5856 {
5857         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
5858         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5859
5860         if (pidx >= nports) {
5861                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
5862                          pidx, nports);
5863                 return 0;
5864         }
5865
5866         switch (chip_version) {
5867         case CHELSIO_T4:
5868         case CHELSIO_T5:
5869                 /* Note that this happens to be the same values as the MPS
5870                  * Buffer Group Map for these Chips.  But we replicate the code
5871                  * here because they're really separate concepts.
5872                  */
5873                 switch (nports) {
5874                 case 1: return 0xf;
5875                 case 2: return 3 << (2 * pidx);
5876                 case 4: return 1 << pidx;
5877                 }
5878                 break;
5879
5880         case CHELSIO_T6:
5881                 switch (nports) {
5882                 case 2: return 1 << pidx;
5883                 }
5884                 break;
5885         }
5886
5887         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
5888                 chip_version, nports);
5889         return 0;
5890 }
5891
5892 /**
5893  *      t4_get_port_type_description - return Port Type string description
5894  *      @port_type: firmware Port Type enumeration
5895  */
5896 const char *t4_get_port_type_description(enum fw_port_type port_type)
5897 {
5898         static const char *const port_type_description[] = {
5899                 "Fiber_XFI",
5900                 "Fiber_XAUI",
5901                 "BT_SGMII",
5902                 "BT_XFI",
5903                 "BT_XAUI",
5904                 "KX4",
5905                 "CX4",
5906                 "KX",
5907                 "KR",
5908                 "SFP",
5909                 "BP_AP",
5910                 "BP4_AP",
5911                 "QSFP_10G",
5912                 "QSA",
5913                 "QSFP",
5914                 "BP40_BA",
5915                 "KR4_100G",
5916                 "CR4_QSFP",
5917                 "CR_QSFP",
5918                 "CR2_QSFP",
5919                 "SFP28",
5920                 "KR_SFP28",
5921         };
5922
5923         if (port_type < ARRAY_SIZE(port_type_description))
5924                 return port_type_description[port_type];
5925         return "UNKNOWN";
5926 }
5927
5928 /**
5929  *      t4_get_port_stats_offset - collect port stats relative to a previous
5930  *                                 snapshot
5931  *      @adap: The adapter
5932  *      @idx: The port
5933  *      @stats: Current stats to fill
5934  *      @offset: Previous stats snapshot
5935  */
5936 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5937                               struct port_stats *stats,
5938                               struct port_stats *offset)
5939 {
5940         u64 *s, *o;
5941         int i;
5942
5943         t4_get_port_stats(adap, idx, stats);
5944         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5945                         i < (sizeof(struct port_stats) / sizeof(u64));
5946                         i++, s++, o++)
5947                 *s -= *o;
5948 }
5949
5950 /**
5951  *      t4_get_port_stats - collect port statistics
5952  *      @adap: the adapter
5953  *      @idx: the port index
5954  *      @p: the stats structure to fill
5955  *
5956  *      Collect statistics related to the given port from HW.
5957  */
5958 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5959 {
5960         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5961         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5962
5963 #define GET_STAT(name) \
5964         t4_read_reg64(adap, \
5965         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5966         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5967 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5968
5969         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
5970         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
5971         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
5972         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
5973         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
5974         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
5975         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
5976         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
5977         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
5978         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
5979         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
5980         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5981         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
5982         p->tx_drop             = GET_STAT(TX_PORT_DROP);
5983         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
5984         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
5985         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
5986         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
5987         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
5988         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
5989         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
5990         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
5991         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
5992
5993         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5994                 if (stat_ctl & COUNTPAUSESTATTX_F)
5995                         p->tx_frames_64 -= p->tx_pause;
5996                 if (stat_ctl & COUNTPAUSEMCTX_F)
5997                         p->tx_mcast_frames -= p->tx_pause;
5998         }
5999         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6000         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6001         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6002         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6003         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6004         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6005         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6006         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6007         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6008         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6009         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6010         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6011         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6012         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6013         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6014         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6015         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6016         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6017         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6018         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6019         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6020         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6021         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6022         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6023         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6024         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6025         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6026
6027         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6028                 if (stat_ctl & COUNTPAUSESTATRX_F)
6029                         p->rx_frames_64 -= p->rx_pause;
6030                 if (stat_ctl & COUNTPAUSEMCRX_F)
6031                         p->rx_mcast_frames -= p->rx_pause;
6032         }
6033
6034         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6035         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6036         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6037         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6038         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6039         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6040         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6041         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6042
6043 #undef GET_STAT
6044 #undef GET_STAT_COM
6045 }
6046
6047 /**
6048  *      t4_get_lb_stats - collect loopback port statistics
6049  *      @adap: the adapter
6050  *      @idx: the loopback port index
6051  *      @p: the stats structure to fill
6052  *
6053  *      Return HW statistics for the given loopback port.
6054  */
6055 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6056 {
6057         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6058
6059 #define GET_STAT(name) \
6060         t4_read_reg64(adap, \
6061         (is_t4(adap->params.chip) ? \
6062         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6063         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6064 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6065
6066         p->octets           = GET_STAT(BYTES);
6067         p->frames           = GET_STAT(FRAMES);
6068         p->bcast_frames     = GET_STAT(BCAST);
6069         p->mcast_frames     = GET_STAT(MCAST);
6070         p->ucast_frames     = GET_STAT(UCAST);
6071         p->error_frames     = GET_STAT(ERROR);
6072
6073         p->frames_64        = GET_STAT(64B);
6074         p->frames_65_127    = GET_STAT(65B_127B);
6075         p->frames_128_255   = GET_STAT(128B_255B);
6076         p->frames_256_511   = GET_STAT(256B_511B);
6077         p->frames_512_1023  = GET_STAT(512B_1023B);
6078         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6079         p->frames_1519_max  = GET_STAT(1519B_MAX);
6080         p->drop             = GET_STAT(DROP_FRAMES);
6081
6082         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6083         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6084         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6085         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6086         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6087         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6088         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6089         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6090
6091 #undef GET_STAT
6092 #undef GET_STAT_COM
6093 }
6094
6095 /*     t4_mk_filtdelwr - create a delete filter WR
6096  *     @ftid: the filter ID
6097  *     @wr: the filter work request to populate
6098  *     @qid: ingress queue to receive the delete notification
6099  *
6100  *     Creates a filter work request to delete the supplied filter.  If @qid is
6101  *     negative the delete notification is suppressed.
6102  */
6103 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6104 {
6105         memset(wr, 0, sizeof(*wr));
6106         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6107         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6108         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6109                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6110         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6111         if (qid >= 0)
6112                 wr->rx_chan_rx_rpl_iq =
6113                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6114 }
6115
6116 #define INIT_CMD(var, cmd, rd_wr) do { \
6117         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6118                                         FW_CMD_REQUEST_F | \
6119                                         FW_CMD_##rd_wr##_F); \
6120         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6121 } while (0)
6122
6123 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6124                           u32 addr, u32 val)
6125 {
6126         u32 ldst_addrspace;
6127         struct fw_ldst_cmd c;
6128
6129         memset(&c, 0, sizeof(c));
6130         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6131         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6132                                         FW_CMD_REQUEST_F |
6133                                         FW_CMD_WRITE_F |
6134                                         ldst_addrspace);
6135         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6136         c.u.addrval.addr = cpu_to_be32(addr);
6137         c.u.addrval.val = cpu_to_be32(val);
6138
6139         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6140 }
6141
6142 /**
6143  *      t4_mdio_rd - read a PHY register through MDIO
6144  *      @adap: the adapter
6145  *      @mbox: mailbox to use for the FW command
6146  *      @phy_addr: the PHY address
6147  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6148  *      @reg: the register to read
6149  *      @valp: where to store the value
6150  *
6151  *      Issues a FW command through the given mailbox to read a PHY register.
6152  */
6153 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6154                unsigned int mmd, unsigned int reg, u16 *valp)
6155 {
6156         int ret;
6157         u32 ldst_addrspace;
6158         struct fw_ldst_cmd c;
6159
6160         memset(&c, 0, sizeof(c));
6161         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6162         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6163                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6164                                         ldst_addrspace);
6165         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6166         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6167                                          FW_LDST_CMD_MMD_V(mmd));
6168         c.u.mdio.raddr = cpu_to_be16(reg);
6169
6170         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6171         if (ret == 0)
6172                 *valp = be16_to_cpu(c.u.mdio.rval);
6173         return ret;
6174 }
6175
6176 /**
6177  *      t4_mdio_wr - write a PHY register through MDIO
6178  *      @adap: the adapter
6179  *      @mbox: mailbox to use for the FW command
6180  *      @phy_addr: the PHY address
6181  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6182  *      @reg: the register to write
6183  *      @valp: value to write
6184  *
6185  *      Issues a FW command through the given mailbox to write a PHY register.
6186  */
6187 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6188                unsigned int mmd, unsigned int reg, u16 val)
6189 {
6190         u32 ldst_addrspace;
6191         struct fw_ldst_cmd c;
6192
6193         memset(&c, 0, sizeof(c));
6194         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6195         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6196                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6197                                         ldst_addrspace);
6198         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6199         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6200                                          FW_LDST_CMD_MMD_V(mmd));
6201         c.u.mdio.raddr = cpu_to_be16(reg);
6202         c.u.mdio.rval = cpu_to_be16(val);
6203
6204         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6205 }
6206
6207 /**
6208  *      t4_sge_decode_idma_state - decode the idma state
6209  *      @adap: the adapter
6210  *      @state: the state idma is stuck in
6211  */
6212 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6213 {
6214         static const char * const t4_decode[] = {
6215                 "IDMA_IDLE",
6216                 "IDMA_PUSH_MORE_CPL_FIFO",
6217                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6218                 "Not used",
6219                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6220                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6221                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6222                 "IDMA_SEND_FIFO_TO_IMSG",
6223                 "IDMA_FL_REQ_DATA_FL_PREP",
6224                 "IDMA_FL_REQ_DATA_FL",
6225                 "IDMA_FL_DROP",
6226                 "IDMA_FL_H_REQ_HEADER_FL",
6227                 "IDMA_FL_H_SEND_PCIEHDR",
6228                 "IDMA_FL_H_PUSH_CPL_FIFO",
6229                 "IDMA_FL_H_SEND_CPL",
6230                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6231                 "IDMA_FL_H_SEND_IP_HDR",
6232                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6233                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6234                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6235                 "IDMA_FL_D_SEND_PCIEHDR",
6236                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6237                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6238                 "IDMA_FL_SEND_PCIEHDR",
6239                 "IDMA_FL_PUSH_CPL_FIFO",
6240                 "IDMA_FL_SEND_CPL",
6241                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6242                 "IDMA_FL_SEND_PAYLOAD",
6243                 "IDMA_FL_REQ_NEXT_DATA_FL",
6244                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6245                 "IDMA_FL_SEND_PADDING",
6246                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6247                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6248                 "IDMA_FL_REQ_DATAFL_DONE",
6249                 "IDMA_FL_REQ_HEADERFL_DONE",
6250         };
6251         static const char * const t5_decode[] = {
6252                 "IDMA_IDLE",
6253                 "IDMA_ALMOST_IDLE",
6254                 "IDMA_PUSH_MORE_CPL_FIFO",
6255                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6256                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6257                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6258                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6259                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6260                 "IDMA_SEND_FIFO_TO_IMSG",
6261                 "IDMA_FL_REQ_DATA_FL",
6262                 "IDMA_FL_DROP",
6263                 "IDMA_FL_DROP_SEND_INC",
6264                 "IDMA_FL_H_REQ_HEADER_FL",
6265                 "IDMA_FL_H_SEND_PCIEHDR",
6266                 "IDMA_FL_H_PUSH_CPL_FIFO",
6267                 "IDMA_FL_H_SEND_CPL",
6268                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6269                 "IDMA_FL_H_SEND_IP_HDR",
6270                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6271                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6272                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6273                 "IDMA_FL_D_SEND_PCIEHDR",
6274                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6275                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6276                 "IDMA_FL_SEND_PCIEHDR",
6277                 "IDMA_FL_PUSH_CPL_FIFO",
6278                 "IDMA_FL_SEND_CPL",
6279                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6280                 "IDMA_FL_SEND_PAYLOAD",
6281                 "IDMA_FL_REQ_NEXT_DATA_FL",
6282                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6283                 "IDMA_FL_SEND_PADDING",
6284                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6285         };
6286         static const char * const t6_decode[] = {
6287                 "IDMA_IDLE",
6288                 "IDMA_PUSH_MORE_CPL_FIFO",
6289                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6290                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6291                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6292                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6293                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6294                 "IDMA_FL_REQ_DATA_FL",
6295                 "IDMA_FL_DROP",
6296                 "IDMA_FL_DROP_SEND_INC",
6297                 "IDMA_FL_H_REQ_HEADER_FL",
6298                 "IDMA_FL_H_SEND_PCIEHDR",
6299                 "IDMA_FL_H_PUSH_CPL_FIFO",
6300                 "IDMA_FL_H_SEND_CPL",
6301                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6302                 "IDMA_FL_H_SEND_IP_HDR",
6303                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6304                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6305                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6306                 "IDMA_FL_D_SEND_PCIEHDR",
6307                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6308                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6309                 "IDMA_FL_SEND_PCIEHDR",
6310                 "IDMA_FL_PUSH_CPL_FIFO",
6311                 "IDMA_FL_SEND_CPL",
6312                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6313                 "IDMA_FL_SEND_PAYLOAD",
6314                 "IDMA_FL_REQ_NEXT_DATA_FL",
6315                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6316                 "IDMA_FL_SEND_PADDING",
6317                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6318         };
6319         static const u32 sge_regs[] = {
6320                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6321                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6322                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6323         };
6324         const char **sge_idma_decode;
6325         int sge_idma_decode_nstates;
6326         int i;
6327         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6328
6329         /* Select the right set of decode strings to dump depending on the
6330          * adapter chip type.
6331          */
6332         switch (chip_version) {
6333         case CHELSIO_T4:
6334                 sge_idma_decode = (const char **)t4_decode;
6335                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6336                 break;
6337
6338         case CHELSIO_T5:
6339                 sge_idma_decode = (const char **)t5_decode;
6340                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6341                 break;
6342
6343         case CHELSIO_T6:
6344                 sge_idma_decode = (const char **)t6_decode;
6345                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6346                 break;
6347
6348         default:
6349                 dev_err(adapter->pdev_dev,
6350                         "Unsupported chip version %d\n", chip_version);
6351                 return;
6352         }
6353
6354         if (is_t4(adapter->params.chip)) {
6355                 sge_idma_decode = (const char **)t4_decode;
6356                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6357         } else {
6358                 sge_idma_decode = (const char **)t5_decode;
6359                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6360         }
6361
6362         if (state < sge_idma_decode_nstates)
6363                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6364         else
6365                 CH_WARN(adapter, "idma state %d unknown\n", state);
6366
6367         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6368                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6369                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6370 }
6371
6372 /**
6373  *      t4_sge_ctxt_flush - flush the SGE context cache
6374  *      @adap: the adapter
6375  *      @mbox: mailbox to use for the FW command
6376  *
6377  *      Issues a FW command through the given mailbox to flush the
6378  *      SGE context cache.
6379  */
6380 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6381 {
6382         int ret;
6383         u32 ldst_addrspace;
6384         struct fw_ldst_cmd c;
6385
6386         memset(&c, 0, sizeof(c));
6387         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
6388         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6389                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6390                                         ldst_addrspace);
6391         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6392         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6393
6394         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6395         return ret;
6396 }
6397
6398 /**
6399  *      t4_fw_hello - establish communication with FW
6400  *      @adap: the adapter
6401  *      @mbox: mailbox to use for the FW command
6402  *      @evt_mbox: mailbox to receive async FW events
6403  *      @master: specifies the caller's willingness to be the device master
6404  *      @state: returns the current device state (if non-NULL)
6405  *
6406  *      Issues a command to establish communication with FW.  Returns either
6407  *      an error (negative integer) or the mailbox of the Master PF.
6408  */
6409 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6410                 enum dev_master master, enum dev_state *state)
6411 {
6412         int ret;
6413         struct fw_hello_cmd c;
6414         u32 v;
6415         unsigned int master_mbox;
6416         int retries = FW_CMD_HELLO_RETRIES;
6417
6418 retry:
6419         memset(&c, 0, sizeof(c));
6420         INIT_CMD(c, HELLO, WRITE);
6421         c.err_to_clearinit = cpu_to_be32(
6422                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6423                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6424                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6425                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6426                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6427                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6428                 FW_HELLO_CMD_CLEARINIT_F);
6429
6430         /*
6431          * Issue the HELLO command to the firmware.  If it's not successful
6432          * but indicates that we got a "busy" or "timeout" condition, retry
6433          * the HELLO until we exhaust our retry limit.  If we do exceed our
6434          * retry limit, check to see if the firmware left us any error
6435          * information and report that if so.
6436          */
6437         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6438         if (ret < 0) {
6439                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6440                         goto retry;
6441                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6442                         t4_report_fw_error(adap);
6443                 return ret;
6444         }
6445
6446         v = be32_to_cpu(c.err_to_clearinit);
6447         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6448         if (state) {
6449                 if (v & FW_HELLO_CMD_ERR_F)
6450                         *state = DEV_STATE_ERR;
6451                 else if (v & FW_HELLO_CMD_INIT_F)
6452                         *state = DEV_STATE_INIT;
6453                 else
6454                         *state = DEV_STATE_UNINIT;
6455         }
6456
6457         /*
6458          * If we're not the Master PF then we need to wait around for the
6459          * Master PF Driver to finish setting up the adapter.
6460          *
6461          * Note that we also do this wait if we're a non-Master-capable PF and
6462          * there is no current Master PF; a Master PF may show up momentarily
6463          * and we wouldn't want to fail pointlessly.  (This can happen when an
6464          * OS loads lots of different drivers rapidly at the same time).  In
6465          * this case, the Master PF returned by the firmware will be
6466          * PCIE_FW_MASTER_M so the test below will work ...
6467          */
6468         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6469             master_mbox != mbox) {
6470                 int waiting = FW_CMD_HELLO_TIMEOUT;
6471
6472                 /*
6473                  * Wait for the firmware to either indicate an error or
6474                  * initialized state.  If we see either of these we bail out
6475                  * and report the issue to the caller.  If we exhaust the
6476                  * "hello timeout" and we haven't exhausted our retries, try
6477                  * again.  Otherwise bail with a timeout error.
6478                  */
6479                 for (;;) {
6480                         u32 pcie_fw;
6481
6482                         msleep(50);
6483                         waiting -= 50;
6484
6485                         /*
6486                          * If neither Error nor Initialialized are indicated
6487                          * by the firmware keep waiting till we exaust our
6488                          * timeout ... and then retry if we haven't exhausted
6489                          * our retries ...
6490                          */
6491                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6492                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6493                                 if (waiting <= 0) {
6494                                         if (retries-- > 0)
6495                                                 goto retry;
6496
6497                                         return -ETIMEDOUT;
6498                                 }
6499                                 continue;
6500                         }
6501
6502                         /*
6503                          * We either have an Error or Initialized condition
6504                          * report errors preferentially.
6505                          */
6506                         if (state) {
6507                                 if (pcie_fw & PCIE_FW_ERR_F)
6508                                         *state = DEV_STATE_ERR;
6509                                 else if (pcie_fw & PCIE_FW_INIT_F)
6510                                         *state = DEV_STATE_INIT;
6511                         }
6512
6513                         /*
6514                          * If we arrived before a Master PF was selected and
6515                          * there's not a valid Master PF, grab its identity
6516                          * for our caller.
6517                          */
6518                         if (master_mbox == PCIE_FW_MASTER_M &&
6519                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6520                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6521                         break;
6522                 }
6523         }
6524
6525         return master_mbox;
6526 }
6527
6528 /**
6529  *      t4_fw_bye - end communication with FW
6530  *      @adap: the adapter
6531  *      @mbox: mailbox to use for the FW command
6532  *
6533  *      Issues a command to terminate communication with FW.
6534  */
6535 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6536 {
6537         struct fw_bye_cmd c;
6538
6539         memset(&c, 0, sizeof(c));
6540         INIT_CMD(c, BYE, WRITE);
6541         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6542 }
6543
6544 /**
6545  *      t4_init_cmd - ask FW to initialize the device
6546  *      @adap: the adapter
6547  *      @mbox: mailbox to use for the FW command
6548  *
6549  *      Issues a command to FW to partially initialize the device.  This
6550  *      performs initialization that generally doesn't depend on user input.
6551  */
6552 int t4_early_init(struct adapter *adap, unsigned int mbox)
6553 {
6554         struct fw_initialize_cmd c;
6555
6556         memset(&c, 0, sizeof(c));
6557         INIT_CMD(c, INITIALIZE, WRITE);
6558         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6559 }
6560
6561 /**
6562  *      t4_fw_reset - issue a reset to FW
6563  *      @adap: the adapter
6564  *      @mbox: mailbox to use for the FW command
6565  *      @reset: specifies the type of reset to perform
6566  *
6567  *      Issues a reset command of the specified type to FW.
6568  */
6569 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6570 {
6571         struct fw_reset_cmd c;
6572
6573         memset(&c, 0, sizeof(c));
6574         INIT_CMD(c, RESET, WRITE);
6575         c.val = cpu_to_be32(reset);
6576         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6577 }
6578
6579 /**
6580  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6581  *      @adap: the adapter
6582  *      @mbox: mailbox to use for the FW RESET command (if desired)
6583  *      @force: force uP into RESET even if FW RESET command fails
6584  *
6585  *      Issues a RESET command to firmware (if desired) with a HALT indication
6586  *      and then puts the microprocessor into RESET state.  The RESET command
6587  *      will only be issued if a legitimate mailbox is provided (mbox <=
6588  *      PCIE_FW_MASTER_M).
6589  *
6590  *      This is generally used in order for the host to safely manipulate the
6591  *      adapter without fear of conflicting with whatever the firmware might
6592  *      be doing.  The only way out of this state is to RESTART the firmware
6593  *      ...
6594  */
6595 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6596 {
6597         int ret = 0;
6598
6599         /*
6600          * If a legitimate mailbox is provided, issue a RESET command
6601          * with a HALT indication.
6602          */
6603         if (mbox <= PCIE_FW_MASTER_M) {
6604                 struct fw_reset_cmd c;
6605
6606                 memset(&c, 0, sizeof(c));
6607                 INIT_CMD(c, RESET, WRITE);
6608                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6609                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6610                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6611         }
6612
6613         /*
6614          * Normally we won't complete the operation if the firmware RESET
6615          * command fails but if our caller insists we'll go ahead and put the
6616          * uP into RESET.  This can be useful if the firmware is hung or even
6617          * missing ...  We'll have to take the risk of putting the uP into
6618          * RESET without the cooperation of firmware in that case.
6619          *
6620          * We also force the firmware's HALT flag to be on in case we bypassed
6621          * the firmware RESET command above or we're dealing with old firmware
6622          * which doesn't have the HALT capability.  This will serve as a flag
6623          * for the incoming firmware to know that it's coming out of a HALT
6624          * rather than a RESET ... if it's new enough to understand that ...
6625          */
6626         if (ret == 0 || force) {
6627                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6628                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6629                                  PCIE_FW_HALT_F);
6630         }
6631
6632         /*
6633          * And we always return the result of the firmware RESET command
6634          * even when we force the uP into RESET ...
6635          */
6636         return ret;
6637 }
6638
6639 /**
6640  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6641  *      @adap: the adapter
6642  *      @reset: if we want to do a RESET to restart things
6643  *
6644  *      Restart firmware previously halted by t4_fw_halt().  On successful
6645  *      return the previous PF Master remains as the new PF Master and there
6646  *      is no need to issue a new HELLO command, etc.
6647  *
6648  *      We do this in two ways:
6649  *
6650  *       1. If we're dealing with newer firmware we'll simply want to take
6651  *          the chip's microprocessor out of RESET.  This will cause the
6652  *          firmware to start up from its start vector.  And then we'll loop
6653  *          until the firmware indicates it's started again (PCIE_FW.HALT
6654  *          reset to 0) or we timeout.
6655  *
6656  *       2. If we're dealing with older firmware then we'll need to RESET
6657  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6658  *          flag and automatically RESET itself on startup.
6659  */
6660 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6661 {
6662         if (reset) {
6663                 /*
6664                  * Since we're directing the RESET instead of the firmware
6665                  * doing it automatically, we need to clear the PCIE_FW.HALT
6666                  * bit.
6667                  */
6668                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6669
6670                 /*
6671                  * If we've been given a valid mailbox, first try to get the
6672                  * firmware to do the RESET.  If that works, great and we can
6673                  * return success.  Otherwise, if we haven't been given a
6674                  * valid mailbox or the RESET command failed, fall back to
6675                  * hitting the chip with a hammer.
6676                  */
6677                 if (mbox <= PCIE_FW_MASTER_M) {
6678                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6679                         msleep(100);
6680                         if (t4_fw_reset(adap, mbox,
6681                                         PIORST_F | PIORSTMODE_F) == 0)
6682                                 return 0;
6683                 }
6684
6685                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6686                 msleep(2000);
6687         } else {
6688                 int ms;
6689
6690                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6691                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6692                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6693                                 return 0;
6694                         msleep(100);
6695                         ms += 100;
6696                 }
6697                 return -ETIMEDOUT;
6698         }
6699         return 0;
6700 }
6701
6702 /**
6703  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6704  *      @adap: the adapter
6705  *      @mbox: mailbox to use for the FW RESET command (if desired)
6706  *      @fw_data: the firmware image to write
6707  *      @size: image size
6708  *      @force: force upgrade even if firmware doesn't cooperate
6709  *
6710  *      Perform all of the steps necessary for upgrading an adapter's
6711  *      firmware image.  Normally this requires the cooperation of the
6712  *      existing firmware in order to halt all existing activities
6713  *      but if an invalid mailbox token is passed in we skip that step
6714  *      (though we'll still put the adapter microprocessor into RESET in
6715  *      that case).
6716  *
6717  *      On successful return the new firmware will have been loaded and
6718  *      the adapter will have been fully RESET losing all previous setup
6719  *      state.  On unsuccessful return the adapter may be completely hosed ...
6720  *      positive errno indicates that the adapter is ~probably~ intact, a
6721  *      negative errno indicates that things are looking bad ...
6722  */
6723 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6724                   const u8 *fw_data, unsigned int size, int force)
6725 {
6726         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6727         int reset, ret;
6728
6729         if (!t4_fw_matches_chip(adap, fw_hdr))
6730                 return -EINVAL;
6731
6732         /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6733          * wont be sent when we are flashing FW.
6734          */
6735         adap->flags &= ~FW_OK;
6736
6737         ret = t4_fw_halt(adap, mbox, force);
6738         if (ret < 0 && !force)
6739                 goto out;
6740
6741         ret = t4_load_fw(adap, fw_data, size);
6742         if (ret < 0)
6743                 goto out;
6744
6745         /*
6746          * If there was a Firmware Configuration File stored in FLASH,
6747          * there's a good chance that it won't be compatible with the new
6748          * Firmware.  In order to prevent difficult to diagnose adapter
6749          * initialization issues, we clear out the Firmware Configuration File
6750          * portion of the FLASH .  The user will need to re-FLASH a new
6751          * Firmware Configuration File which is compatible with the new
6752          * Firmware if that's desired.
6753          */
6754         (void)t4_load_cfg(adap, NULL, 0);
6755
6756         /*
6757          * Older versions of the firmware don't understand the new
6758          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6759          * restart.  So for newly loaded older firmware we'll have to do the
6760          * RESET for it so it starts up on a clean slate.  We can tell if
6761          * the newly loaded firmware will handle this right by checking
6762          * its header flags to see if it advertises the capability.
6763          */
6764         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6765         ret = t4_fw_restart(adap, mbox, reset);
6766
6767         /* Grab potentially new Firmware Device Log parameters so we can see
6768          * how healthy the new Firmware is.  It's okay to contact the new
6769          * Firmware for these parameters even though, as far as it's
6770          * concerned, we've never said "HELLO" to it ...
6771          */
6772         (void)t4_init_devlog_params(adap);
6773 out:
6774         adap->flags |= FW_OK;
6775         return ret;
6776 }
6777
6778 /**
6779  *      t4_fl_pkt_align - return the fl packet alignment
6780  *      @adap: the adapter
6781  *
6782  *      T4 has a single field to specify the packing and padding boundary.
6783  *      T5 onwards has separate fields for this and hence the alignment for
6784  *      next packet offset is maximum of these two.
6785  *
6786  */
6787 int t4_fl_pkt_align(struct adapter *adap)
6788 {
6789         u32 sge_control, sge_control2;
6790         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6791
6792         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6793
6794         /* T4 uses a single control field to specify both the PCIe Padding and
6795          * Packing Boundary.  T5 introduced the ability to specify these
6796          * separately.  The actual Ingress Packet Data alignment boundary
6797          * within Packed Buffer Mode is the maximum of these two
6798          * specifications.  (Note that it makes no real practical sense to
6799          * have the Pading Boudary be larger than the Packing Boundary but you
6800          * could set the chip up that way and, in fact, legacy T4 code would
6801          * end doing this because it would initialize the Padding Boundary and
6802          * leave the Packing Boundary initialized to 0 (16 bytes).)
6803          * Padding Boundary values in T6 starts from 8B,
6804          * where as it is 32B for T4 and T5.
6805          */
6806         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6807                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6808         else
6809                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6810
6811         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6812
6813         fl_align = ingpadboundary;
6814         if (!is_t4(adap->params.chip)) {
6815                 /* T5 has a weird interpretation of one of the PCIe Packing
6816                  * Boundary values.  No idea why ...
6817                  */
6818                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6819                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6820                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6821                         ingpackboundary = 16;
6822                 else
6823                         ingpackboundary = 1 << (ingpackboundary +
6824                                                 INGPACKBOUNDARY_SHIFT_X);
6825
6826                 fl_align = max(ingpadboundary, ingpackboundary);
6827         }
6828         return fl_align;
6829 }
6830
6831 /**
6832  *      t4_fixup_host_params - fix up host-dependent parameters
6833  *      @adap: the adapter
6834  *      @page_size: the host's Base Page Size
6835  *      @cache_line_size: the host's Cache Line Size
6836  *
6837  *      Various registers in T4 contain values which are dependent on the
6838  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6839  *      those registers with the appropriate values as passed in ...
6840  */
6841 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6842                          unsigned int cache_line_size)
6843 {
6844         unsigned int page_shift = fls(page_size) - 1;
6845         unsigned int sge_hps = page_shift - 10;
6846         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6847         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6848         unsigned int fl_align_log = fls(fl_align) - 1;
6849
6850         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6851                      HOSTPAGESIZEPF0_V(sge_hps) |
6852                      HOSTPAGESIZEPF1_V(sge_hps) |
6853                      HOSTPAGESIZEPF2_V(sge_hps) |
6854                      HOSTPAGESIZEPF3_V(sge_hps) |
6855                      HOSTPAGESIZEPF4_V(sge_hps) |
6856                      HOSTPAGESIZEPF5_V(sge_hps) |
6857                      HOSTPAGESIZEPF6_V(sge_hps) |
6858                      HOSTPAGESIZEPF7_V(sge_hps));
6859
6860         if (is_t4(adap->params.chip)) {
6861                 t4_set_reg_field(adap, SGE_CONTROL_A,
6862                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6863                                  EGRSTATUSPAGESIZE_F,
6864                                  INGPADBOUNDARY_V(fl_align_log -
6865                                                   INGPADBOUNDARY_SHIFT_X) |
6866                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6867         } else {
6868                 unsigned int pack_align;
6869                 unsigned int ingpad, ingpack;
6870                 unsigned int pcie_cap;
6871
6872                 /* T5 introduced the separation of the Free List Padding and
6873                  * Packing Boundaries.  Thus, we can select a smaller Padding
6874                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
6875                  * Bandwidth, and use a Packing Boundary which is large enough
6876                  * to avoid false sharing between CPUs, etc.
6877                  *
6878                  * For the PCI Link, the smaller the Padding Boundary the
6879                  * better.  For the Memory Controller, a smaller Padding
6880                  * Boundary is better until we cross under the Memory Line
6881                  * Size (the minimum unit of transfer to/from Memory).  If we
6882                  * have a Padding Boundary which is smaller than the Memory
6883                  * Line Size, that'll involve a Read-Modify-Write cycle on the
6884                  * Memory Controller which is never good.
6885                  */
6886
6887                 /* We want the Packing Boundary to be based on the Cache Line
6888                  * Size in order to help avoid False Sharing performance
6889                  * issues between CPUs, etc.  We also want the Packing
6890                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
6891                  * get best performance when the Packing Boundary is a
6892                  * multiple of the Maximum Payload Size.
6893                  */
6894                 pack_align = fl_align;
6895                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6896                 if (pcie_cap) {
6897                         unsigned int mps, mps_log;
6898                         u16 devctl;
6899
6900                         /* The PCIe Device Control Maximum Payload Size field
6901                          * [bits 7:5] encodes sizes as powers of 2 starting at
6902                          * 128 bytes.
6903                          */
6904                         pci_read_config_word(adap->pdev,
6905                                              pcie_cap + PCI_EXP_DEVCTL,
6906                                              &devctl);
6907                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6908                         mps = 1 << mps_log;
6909                         if (mps > pack_align)
6910                                 pack_align = mps;
6911                 }
6912
6913                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6914                  * value for the Packing Boundary.  This corresponds to 16
6915                  * bytes instead of the expected 32 bytes.  So if we want 32
6916                  * bytes, the best we can really do is 64 bytes ...
6917                  */
6918                 if (pack_align <= 16) {
6919                         ingpack = INGPACKBOUNDARY_16B_X;
6920                         fl_align = 16;
6921                 } else if (pack_align == 32) {
6922                         ingpack = INGPACKBOUNDARY_64B_X;
6923                         fl_align = 64;
6924                 } else {
6925                         unsigned int pack_align_log = fls(pack_align) - 1;
6926
6927                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6928                         fl_align = pack_align;
6929                 }
6930
6931                 /* Use the smallest Ingress Padding which isn't smaller than
6932                  * the Memory Controller Read/Write Size.  We'll take that as
6933                  * being 8 bytes since we don't know of any system with a
6934                  * wider Memory Controller Bus Width.
6935                  */
6936                 if (is_t5(adap->params.chip))
6937                         ingpad = INGPADBOUNDARY_32B_X;
6938                 else
6939                         ingpad = T6_INGPADBOUNDARY_8B_X;
6940
6941                 t4_set_reg_field(adap, SGE_CONTROL_A,
6942                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6943                                  EGRSTATUSPAGESIZE_F,
6944                                  INGPADBOUNDARY_V(ingpad) |
6945                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6946                 t4_set_reg_field(adap, SGE_CONTROL2_A,
6947                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6948                                  INGPACKBOUNDARY_V(ingpack));
6949         }
6950         /*
6951          * Adjust various SGE Free List Host Buffer Sizes.
6952          *
6953          * This is something of a crock since we're using fixed indices into
6954          * the array which are also known by the sge.c code and the T4
6955          * Firmware Configuration File.  We need to come up with a much better
6956          * approach to managing this array.  For now, the first four entries
6957          * are:
6958          *
6959          *   0: Host Page Size
6960          *   1: 64KB
6961          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6962          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6963          *
6964          * For the single-MTU buffers in unpacked mode we need to include
6965          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6966          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6967          * Padding boundary.  All of these are accommodated in the Factory
6968          * Default Firmware Configuration File but we need to adjust it for
6969          * this host's cache line size.
6970          */
6971         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6972         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6973                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6974                      & ~(fl_align-1));
6975         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6976                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6977                      & ~(fl_align-1));
6978
6979         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6980
6981         return 0;
6982 }
6983
6984 /**
6985  *      t4_fw_initialize - ask FW to initialize the device
6986  *      @adap: the adapter
6987  *      @mbox: mailbox to use for the FW command
6988  *
6989  *      Issues a command to FW to partially initialize the device.  This
6990  *      performs initialization that generally doesn't depend on user input.
6991  */
6992 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6993 {
6994         struct fw_initialize_cmd c;
6995
6996         memset(&c, 0, sizeof(c));
6997         INIT_CMD(c, INITIALIZE, WRITE);
6998         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6999 }
7000
7001 /**
7002  *      t4_query_params_rw - query FW or device parameters
7003  *      @adap: the adapter
7004  *      @mbox: mailbox to use for the FW command
7005  *      @pf: the PF
7006  *      @vf: the VF
7007  *      @nparams: the number of parameters
7008  *      @params: the parameter names
7009  *      @val: the parameter values
7010  *      @rw: Write and read flag
7011  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7012  *
7013  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7014  *      queried at once.
7015  */
7016 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7017                        unsigned int vf, unsigned int nparams, const u32 *params,
7018                        u32 *val, int rw, bool sleep_ok)
7019 {
7020         int i, ret;
7021         struct fw_params_cmd c;
7022         __be32 *p = &c.param[0].mnem;
7023
7024         if (nparams > 7)
7025                 return -EINVAL;
7026
7027         memset(&c, 0, sizeof(c));
7028         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7029                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7030                                   FW_PARAMS_CMD_PFN_V(pf) |
7031                                   FW_PARAMS_CMD_VFN_V(vf));
7032         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7033
7034         for (i = 0; i < nparams; i++) {
7035                 *p++ = cpu_to_be32(*params++);
7036                 if (rw)
7037                         *p = cpu_to_be32(*(val + i));
7038                 p++;
7039         }
7040
7041         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7042         if (ret == 0)
7043                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7044                         *val++ = be32_to_cpu(*p);
7045         return ret;
7046 }
7047
7048 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7049                     unsigned int vf, unsigned int nparams, const u32 *params,
7050                     u32 *val)
7051 {
7052         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7053                                   true);
7054 }
7055
7056 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7057                        unsigned int vf, unsigned int nparams, const u32 *params,
7058                        u32 *val)
7059 {
7060         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7061                                   false);
7062 }
7063
7064 /**
7065  *      t4_set_params_timeout - sets FW or device parameters
7066  *      @adap: the adapter
7067  *      @mbox: mailbox to use for the FW command
7068  *      @pf: the PF
7069  *      @vf: the VF
7070  *      @nparams: the number of parameters
7071  *      @params: the parameter names
7072  *      @val: the parameter values
7073  *      @timeout: the timeout time
7074  *
7075  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7076  *      specified at once.
7077  */
7078 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7079                           unsigned int pf, unsigned int vf,
7080                           unsigned int nparams, const u32 *params,
7081                           const u32 *val, int timeout)
7082 {
7083         struct fw_params_cmd c;
7084         __be32 *p = &c.param[0].mnem;
7085
7086         if (nparams > 7)
7087                 return -EINVAL;
7088
7089         memset(&c, 0, sizeof(c));
7090         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7091                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7092                                   FW_PARAMS_CMD_PFN_V(pf) |
7093                                   FW_PARAMS_CMD_VFN_V(vf));
7094         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7095
7096         while (nparams--) {
7097                 *p++ = cpu_to_be32(*params++);
7098                 *p++ = cpu_to_be32(*val++);
7099         }
7100
7101         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7102 }
7103
7104 /**
7105  *      t4_set_params - sets FW or device parameters
7106  *      @adap: the adapter
7107  *      @mbox: mailbox to use for the FW command
7108  *      @pf: the PF
7109  *      @vf: the VF
7110  *      @nparams: the number of parameters
7111  *      @params: the parameter names
7112  *      @val: the parameter values
7113  *
7114  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7115  *      specified at once.
7116  */
7117 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7118                   unsigned int vf, unsigned int nparams, const u32 *params,
7119                   const u32 *val)
7120 {
7121         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7122                                      FW_CMD_MAX_TIMEOUT);
7123 }
7124
7125 /**
7126  *      t4_cfg_pfvf - configure PF/VF resource limits
7127  *      @adap: the adapter
7128  *      @mbox: mailbox to use for the FW command
7129  *      @pf: the PF being configured
7130  *      @vf: the VF being configured
7131  *      @txq: the max number of egress queues
7132  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7133  *      @rxqi: the max number of interrupt-capable ingress queues
7134  *      @rxq: the max number of interruptless ingress queues
7135  *      @tc: the PCI traffic class
7136  *      @vi: the max number of virtual interfaces
7137  *      @cmask: the channel access rights mask for the PF/VF
7138  *      @pmask: the port access rights mask for the PF/VF
7139  *      @nexact: the maximum number of exact MPS filters
7140  *      @rcaps: read capabilities
7141  *      @wxcaps: write/execute capabilities
7142  *
7143  *      Configures resource limits and capabilities for a physical or virtual
7144  *      function.
7145  */
7146 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7147                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7148                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7149                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7150                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7151 {
7152         struct fw_pfvf_cmd c;
7153
7154         memset(&c, 0, sizeof(c));
7155         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7156                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7157                                   FW_PFVF_CMD_VFN_V(vf));
7158         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7159         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7160                                      FW_PFVF_CMD_NIQ_V(rxq));
7161         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7162                                     FW_PFVF_CMD_PMASK_V(pmask) |
7163                                     FW_PFVF_CMD_NEQ_V(txq));
7164         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7165                                       FW_PFVF_CMD_NVI_V(vi) |
7166                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7167         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7168                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7169                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7170         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7171 }
7172
7173 /**
7174  *      t4_alloc_vi - allocate a virtual interface
7175  *      @adap: the adapter
7176  *      @mbox: mailbox to use for the FW command
7177  *      @port: physical port associated with the VI
7178  *      @pf: the PF owning the VI
7179  *      @vf: the VF owning the VI
7180  *      @nmac: number of MAC addresses needed (1 to 5)
7181  *      @mac: the MAC addresses of the VI
7182  *      @rss_size: size of RSS table slice associated with this VI
7183  *
7184  *      Allocates a virtual interface for the given physical port.  If @mac is
7185  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7186  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7187  *      stored consecutively so the space needed is @nmac * 6 bytes.
7188  *      Returns a negative error number or the non-negative VI id.
7189  */
7190 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7191                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7192                 unsigned int *rss_size)
7193 {
7194         int ret;
7195         struct fw_vi_cmd c;
7196
7197         memset(&c, 0, sizeof(c));
7198         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7199                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7200                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7201         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7202         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7203         c.nmac = nmac - 1;
7204
7205         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7206         if (ret)
7207                 return ret;
7208
7209         if (mac) {
7210                 memcpy(mac, c.mac, sizeof(c.mac));
7211                 switch (nmac) {
7212                 case 5:
7213                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7214                 case 4:
7215                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7216                 case 3:
7217                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7218                 case 2:
7219                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7220                 }
7221         }
7222         if (rss_size)
7223                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7224         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7225 }
7226
7227 /**
7228  *      t4_free_vi - free a virtual interface
7229  *      @adap: the adapter
7230  *      @mbox: mailbox to use for the FW command
7231  *      @pf: the PF owning the VI
7232  *      @vf: the VF owning the VI
7233  *      @viid: virtual interface identifiler
7234  *
7235  *      Free a previously allocated virtual interface.
7236  */
7237 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7238                unsigned int vf, unsigned int viid)
7239 {
7240         struct fw_vi_cmd c;
7241
7242         memset(&c, 0, sizeof(c));
7243         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7244                                   FW_CMD_REQUEST_F |
7245                                   FW_CMD_EXEC_F |
7246                                   FW_VI_CMD_PFN_V(pf) |
7247                                   FW_VI_CMD_VFN_V(vf));
7248         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7249         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7250
7251         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7252 }
7253
7254 /**
7255  *      t4_set_rxmode - set Rx properties of a virtual interface
7256  *      @adap: the adapter
7257  *      @mbox: mailbox to use for the FW command
7258  *      @viid: the VI id
7259  *      @mtu: the new MTU or -1
7260  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7261  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7262  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7263  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7264  *      @sleep_ok: if true we may sleep while awaiting command completion
7265  *
7266  *      Sets Rx properties of a virtual interface.
7267  */
7268 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7269                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7270                   bool sleep_ok)
7271 {
7272         struct fw_vi_rxmode_cmd c;
7273
7274         /* convert to FW values */
7275         if (mtu < 0)
7276                 mtu = FW_RXMODE_MTU_NO_CHG;
7277         if (promisc < 0)
7278                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7279         if (all_multi < 0)
7280                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7281         if (bcast < 0)
7282                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7283         if (vlanex < 0)
7284                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7285
7286         memset(&c, 0, sizeof(c));
7287         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7288                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7289                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7290         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7291         c.mtu_to_vlanexen =
7292                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7293                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7294                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7295                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7296                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7297         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7298 }
7299
7300 /**
7301  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7302  *      @adap: the adapter
7303  *      @mbox: mailbox to use for the FW command
7304  *      @viid: the VI id
7305  *      @free: if true any existing filters for this VI id are first removed
7306  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7307  *      @addr: the MAC address(es)
7308  *      @idx: where to store the index of each allocated filter
7309  *      @hash: pointer to hash address filter bitmap
7310  *      @sleep_ok: call is allowed to sleep
7311  *
7312  *      Allocates an exact-match filter for each of the supplied addresses and
7313  *      sets it to the corresponding address.  If @idx is not %NULL it should
7314  *      have at least @naddr entries, each of which will be set to the index of
7315  *      the filter allocated for the corresponding MAC address.  If a filter
7316  *      could not be allocated for an address its index is set to 0xffff.
7317  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7318  *      are hashed and update the hash filter bitmap pointed at by @hash.
7319  *
7320  *      Returns a negative error number or the number of filters allocated.
7321  */
7322 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7323                       unsigned int viid, bool free, unsigned int naddr,
7324                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7325 {
7326         int offset, ret = 0;
7327         struct fw_vi_mac_cmd c;
7328         unsigned int nfilters = 0;
7329         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7330         unsigned int rem = naddr;
7331
7332         if (naddr > max_naddr)
7333                 return -EINVAL;
7334
7335         for (offset = 0; offset < naddr ; /**/) {
7336                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7337                                          rem : ARRAY_SIZE(c.u.exact));
7338                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7339                                                      u.exact[fw_naddr]), 16);
7340                 struct fw_vi_mac_exact *p;
7341                 int i;
7342
7343                 memset(&c, 0, sizeof(c));
7344                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7345                                            FW_CMD_REQUEST_F |
7346                                            FW_CMD_WRITE_F |
7347                                            FW_CMD_EXEC_V(free) |
7348                                            FW_VI_MAC_CMD_VIID_V(viid));
7349                 c.freemacs_to_len16 =
7350                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7351                                     FW_CMD_LEN16_V(len16));
7352
7353                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7354                         p->valid_to_idx =
7355                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7356                                             FW_VI_MAC_CMD_IDX_V(
7357                                                     FW_VI_MAC_ADD_MAC));
7358                         memcpy(p->macaddr, addr[offset + i],
7359                                sizeof(p->macaddr));
7360                 }
7361
7362                 /* It's okay if we run out of space in our MAC address arena.
7363                  * Some of the addresses we submit may get stored so we need
7364                  * to run through the reply to see what the results were ...
7365                  */
7366                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7367                 if (ret && ret != -FW_ENOMEM)
7368                         break;
7369
7370                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7371                         u16 index = FW_VI_MAC_CMD_IDX_G(
7372                                         be16_to_cpu(p->valid_to_idx));
7373
7374                         if (idx)
7375                                 idx[offset + i] = (index >= max_naddr ?
7376                                                    0xffff : index);
7377                         if (index < max_naddr)
7378                                 nfilters++;
7379                         else if (hash)
7380                                 *hash |= (1ULL <<
7381                                           hash_mac_addr(addr[offset + i]));
7382                 }
7383
7384                 free = false;
7385                 offset += fw_naddr;
7386                 rem -= fw_naddr;
7387         }
7388
7389         if (ret == 0 || ret == -FW_ENOMEM)
7390                 ret = nfilters;
7391         return ret;
7392 }
7393
7394 /**
7395  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
7396  *      @adap: the adapter
7397  *      @mbox: mailbox to use for the FW command
7398  *      @viid: the VI id
7399  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7400  *      @addr: the MAC address(es)
7401  *      @sleep_ok: call is allowed to sleep
7402  *
7403  *      Frees the exact-match filter for each of the supplied addresses
7404  *
7405  *      Returns a negative error number or the number of filters freed.
7406  */
7407 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7408                      unsigned int viid, unsigned int naddr,
7409                      const u8 **addr, bool sleep_ok)
7410 {
7411         int offset, ret = 0;
7412         struct fw_vi_mac_cmd c;
7413         unsigned int nfilters = 0;
7414         unsigned int max_naddr = is_t4(adap->params.chip) ?
7415                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
7416                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7417         unsigned int rem = naddr;
7418
7419         if (naddr > max_naddr)
7420                 return -EINVAL;
7421
7422         for (offset = 0; offset < (int)naddr ; /**/) {
7423                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7424                                          ? rem
7425                                          : ARRAY_SIZE(c.u.exact));
7426                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7427                                                      u.exact[fw_naddr]), 16);
7428                 struct fw_vi_mac_exact *p;
7429                 int i;
7430
7431                 memset(&c, 0, sizeof(c));
7432                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7433                                      FW_CMD_REQUEST_F |
7434                                      FW_CMD_WRITE_F |
7435                                      FW_CMD_EXEC_V(0) |
7436                                      FW_VI_MAC_CMD_VIID_V(viid));
7437                 c.freemacs_to_len16 =
7438                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7439                                             FW_CMD_LEN16_V(len16));
7440
7441                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7442                         p->valid_to_idx = cpu_to_be16(
7443                                 FW_VI_MAC_CMD_VALID_F |
7444                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7445                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7446                 }
7447
7448                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7449                 if (ret)
7450                         break;
7451
7452                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7453                         u16 index = FW_VI_MAC_CMD_IDX_G(
7454                                                 be16_to_cpu(p->valid_to_idx));
7455
7456                         if (index < max_naddr)
7457                                 nfilters++;
7458                 }
7459
7460                 offset += fw_naddr;
7461                 rem -= fw_naddr;
7462         }
7463
7464         if (ret == 0)
7465                 ret = nfilters;
7466         return ret;
7467 }
7468
7469 /**
7470  *      t4_change_mac - modifies the exact-match filter for a MAC address
7471  *      @adap: the adapter
7472  *      @mbox: mailbox to use for the FW command
7473  *      @viid: the VI id
7474  *      @idx: index of existing filter for old value of MAC address, or -1
7475  *      @addr: the new MAC address value
7476  *      @persist: whether a new MAC allocation should be persistent
7477  *      @add_smt: if true also add the address to the HW SMT
7478  *
7479  *      Modifies an exact-match filter and sets it to the new MAC address.
7480  *      Note that in general it is not possible to modify the value of a given
7481  *      filter so the generic way to modify an address filter is to free the one
7482  *      being used by the old address value and allocate a new filter for the
7483  *      new address value.  @idx can be -1 if the address is a new addition.
7484  *
7485  *      Returns a negative error number or the index of the filter with the new
7486  *      MAC value.
7487  */
7488 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7489                   int idx, const u8 *addr, bool persist, bool add_smt)
7490 {
7491         int ret, mode;
7492         struct fw_vi_mac_cmd c;
7493         struct fw_vi_mac_exact *p = c.u.exact;
7494         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7495
7496         if (idx < 0)                             /* new allocation */
7497                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7498         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7499
7500         memset(&c, 0, sizeof(c));
7501         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7502                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7503                                    FW_VI_MAC_CMD_VIID_V(viid));
7504         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7505         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7506                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7507                                       FW_VI_MAC_CMD_IDX_V(idx));
7508         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7509
7510         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7511         if (ret == 0) {
7512                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7513                 if (ret >= max_mac_addr)
7514                         ret = -ENOMEM;
7515         }
7516         return ret;
7517 }
7518
7519 /**
7520  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7521  *      @adap: the adapter
7522  *      @mbox: mailbox to use for the FW command
7523  *      @viid: the VI id
7524  *      @ucast: whether the hash filter should also match unicast addresses
7525  *      @vec: the value to be written to the hash filter
7526  *      @sleep_ok: call is allowed to sleep
7527  *
7528  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7529  */
7530 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7531                      bool ucast, u64 vec, bool sleep_ok)
7532 {
7533         struct fw_vi_mac_cmd c;
7534
7535         memset(&c, 0, sizeof(c));
7536         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7537                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7538                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7539         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7540                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7541                                           FW_CMD_LEN16_V(1));
7542         c.u.hash.hashvec = cpu_to_be64(vec);
7543         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7544 }
7545
7546 /**
7547  *      t4_enable_vi_params - enable/disable a virtual interface
7548  *      @adap: the adapter
7549  *      @mbox: mailbox to use for the FW command
7550  *      @viid: the VI id
7551  *      @rx_en: 1=enable Rx, 0=disable Rx
7552  *      @tx_en: 1=enable Tx, 0=disable Tx
7553  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7554  *
7555  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7556  *      only makes sense when enabling a Virtual Interface ...
7557  */
7558 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7559                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7560 {
7561         struct fw_vi_enable_cmd c;
7562
7563         memset(&c, 0, sizeof(c));
7564         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7565                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7566                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7567         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7568                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7569                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7570                                      FW_LEN16(c));
7571         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7572 }
7573
7574 /**
7575  *      t4_enable_vi - enable/disable a virtual interface
7576  *      @adap: the adapter
7577  *      @mbox: mailbox to use for the FW command
7578  *      @viid: the VI id
7579  *      @rx_en: 1=enable Rx, 0=disable Rx
7580  *      @tx_en: 1=enable Tx, 0=disable Tx
7581  *
7582  *      Enables/disables a virtual interface.
7583  */
7584 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7585                  bool rx_en, bool tx_en)
7586 {
7587         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7588 }
7589
7590 /**
7591  *      t4_identify_port - identify a VI's port by blinking its LED
7592  *      @adap: the adapter
7593  *      @mbox: mailbox to use for the FW command
7594  *      @viid: the VI id
7595  *      @nblinks: how many times to blink LED at 2.5 Hz
7596  *
7597  *      Identifies a VI's port by blinking its LED.
7598  */
7599 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7600                      unsigned int nblinks)
7601 {
7602         struct fw_vi_enable_cmd c;
7603
7604         memset(&c, 0, sizeof(c));
7605         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7606                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7607                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7608         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7609         c.blinkdur = cpu_to_be16(nblinks);
7610         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7611 }
7612
7613 /**
7614  *      t4_iq_stop - stop an ingress queue and its FLs
7615  *      @adap: the adapter
7616  *      @mbox: mailbox to use for the FW command
7617  *      @pf: the PF owning the queues
7618  *      @vf: the VF owning the queues
7619  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7620  *      @iqid: ingress queue id
7621  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7622  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7623  *
7624  *      Stops an ingress queue and its associated FLs, if any.  This causes
7625  *      any current or future data/messages destined for these queues to be
7626  *      tossed.
7627  */
7628 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7629                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7630                unsigned int fl0id, unsigned int fl1id)
7631 {
7632         struct fw_iq_cmd c;
7633
7634         memset(&c, 0, sizeof(c));
7635         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7636                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7637                                   FW_IQ_CMD_VFN_V(vf));
7638         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7639         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7640         c.iqid = cpu_to_be16(iqid);
7641         c.fl0id = cpu_to_be16(fl0id);
7642         c.fl1id = cpu_to_be16(fl1id);
7643         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7644 }
7645
7646 /**
7647  *      t4_iq_free - free an ingress queue and its FLs
7648  *      @adap: the adapter
7649  *      @mbox: mailbox to use for the FW command
7650  *      @pf: the PF owning the queues
7651  *      @vf: the VF owning the queues
7652  *      @iqtype: the ingress queue type
7653  *      @iqid: ingress queue id
7654  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7655  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7656  *
7657  *      Frees an ingress queue and its associated FLs, if any.
7658  */
7659 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7660                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7661                unsigned int fl0id, unsigned int fl1id)
7662 {
7663         struct fw_iq_cmd c;
7664
7665         memset(&c, 0, sizeof(c));
7666         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7667                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7668                                   FW_IQ_CMD_VFN_V(vf));
7669         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7670         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7671         c.iqid = cpu_to_be16(iqid);
7672         c.fl0id = cpu_to_be16(fl0id);
7673         c.fl1id = cpu_to_be16(fl1id);
7674         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7675 }
7676
7677 /**
7678  *      t4_eth_eq_free - free an Ethernet egress queue
7679  *      @adap: the adapter
7680  *      @mbox: mailbox to use for the FW command
7681  *      @pf: the PF owning the queue
7682  *      @vf: the VF owning the queue
7683  *      @eqid: egress queue id
7684  *
7685  *      Frees an Ethernet egress queue.
7686  */
7687 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7688                    unsigned int vf, unsigned int eqid)
7689 {
7690         struct fw_eq_eth_cmd c;
7691
7692         memset(&c, 0, sizeof(c));
7693         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7694                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7695                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7696                                   FW_EQ_ETH_CMD_VFN_V(vf));
7697         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7698         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7699         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7700 }
7701
7702 /**
7703  *      t4_ctrl_eq_free - free a control egress queue
7704  *      @adap: the adapter
7705  *      @mbox: mailbox to use for the FW command
7706  *      @pf: the PF owning the queue
7707  *      @vf: the VF owning the queue
7708  *      @eqid: egress queue id
7709  *
7710  *      Frees a control egress queue.
7711  */
7712 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7713                     unsigned int vf, unsigned int eqid)
7714 {
7715         struct fw_eq_ctrl_cmd c;
7716
7717         memset(&c, 0, sizeof(c));
7718         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7719                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7720                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7721                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7722         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7723         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7724         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7725 }
7726
7727 /**
7728  *      t4_ofld_eq_free - free an offload egress queue
7729  *      @adap: the adapter
7730  *      @mbox: mailbox to use for the FW command
7731  *      @pf: the PF owning the queue
7732  *      @vf: the VF owning the queue
7733  *      @eqid: egress queue id
7734  *
7735  *      Frees a control egress queue.
7736  */
7737 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7738                     unsigned int vf, unsigned int eqid)
7739 {
7740         struct fw_eq_ofld_cmd c;
7741
7742         memset(&c, 0, sizeof(c));
7743         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7744                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7745                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7746                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7747         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7748         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7749         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7750 }
7751
7752 /**
7753  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7754  *      @adap: the adapter
7755  *      @link_down_rc: Link Down Reason Code
7756  *
7757  *      Returns a string representation of the Link Down Reason Code.
7758  */
7759 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7760 {
7761         static const char * const reason[] = {
7762                 "Link Down",
7763                 "Remote Fault",
7764                 "Auto-negotiation Failure",
7765                 "Reserved",
7766                 "Insufficient Airflow",
7767                 "Unable To Determine Reason",
7768                 "No RX Signal Detected",
7769                 "Reserved",
7770         };
7771
7772         if (link_down_rc >= ARRAY_SIZE(reason))
7773                 return "Bad Reason Code";
7774
7775         return reason[link_down_rc];
7776 }
7777
7778 /**
7779  * Return the highest speed set in the port capabilities, in Mb/s.
7780  */
7781 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
7782 {
7783         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
7784                 do { \
7785                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7786                                 return __speed; \
7787                 } while (0)
7788
7789         TEST_SPEED_RETURN(400G, 400000);
7790         TEST_SPEED_RETURN(200G, 200000);
7791         TEST_SPEED_RETURN(100G, 100000);
7792         TEST_SPEED_RETURN(50G,   50000);
7793         TEST_SPEED_RETURN(40G,   40000);
7794         TEST_SPEED_RETURN(25G,   25000);
7795         TEST_SPEED_RETURN(10G,   10000);
7796         TEST_SPEED_RETURN(1G,     1000);
7797         TEST_SPEED_RETURN(100M,    100);
7798
7799         #undef TEST_SPEED_RETURN
7800
7801         return 0;
7802 }
7803
7804 /**
7805  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
7806  *      @acaps: advertised Port Capabilities
7807  *
7808  *      Get the highest speed for the port from the advertised Port
7809  *      Capabilities.  It will be either the highest speed from the list of
7810  *      speeds or whatever user has set using ethtool.
7811  */
7812 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
7813 {
7814         #define TEST_SPEED_RETURN(__caps_speed) \
7815                 do { \
7816                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7817                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
7818                 } while (0)
7819
7820         TEST_SPEED_RETURN(400G);
7821         TEST_SPEED_RETURN(200G);
7822         TEST_SPEED_RETURN(100G);
7823         TEST_SPEED_RETURN(50G);
7824         TEST_SPEED_RETURN(40G);
7825         TEST_SPEED_RETURN(25G);
7826         TEST_SPEED_RETURN(10G);
7827         TEST_SPEED_RETURN(1G);
7828         TEST_SPEED_RETURN(100M);
7829
7830         #undef TEST_SPEED_RETURN
7831
7832         return 0;
7833 }
7834
7835 /**
7836  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
7837  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
7838  *
7839  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
7840  *      32-bit Port Capabilities value.
7841  */
7842 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
7843 {
7844         fw_port_cap32_t linkattr = 0;
7845
7846         /* Unfortunately the format of the Link Status in the old
7847          * 16-bit Port Information message isn't the same as the
7848          * 16-bit Port Capabilities bitfield used everywhere else ...
7849          */
7850         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
7851                 linkattr |= FW_PORT_CAP32_FC_RX;
7852         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
7853                 linkattr |= FW_PORT_CAP32_FC_TX;
7854         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7855                 linkattr |= FW_PORT_CAP32_SPEED_100M;
7856         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7857                 linkattr |= FW_PORT_CAP32_SPEED_1G;
7858         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7859                 linkattr |= FW_PORT_CAP32_SPEED_10G;
7860         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7861                 linkattr |= FW_PORT_CAP32_SPEED_25G;
7862         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7863                 linkattr |= FW_PORT_CAP32_SPEED_40G;
7864         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7865                 linkattr |= FW_PORT_CAP32_SPEED_100G;
7866
7867         return linkattr;
7868 }
7869
7870 /**
7871  *      t4_handle_get_port_info - process a FW reply message
7872  *      @pi: the port info
7873  *      @rpl: start of the FW message
7874  *
7875  *      Processes a GET_PORT_INFO FW reply message.
7876  */
7877 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7878 {
7879         const struct fw_port_cmd *cmd = (const void *)rpl;
7880         int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
7881         struct adapter *adapter = pi->adapter;
7882         struct link_config *lc = &pi->link_cfg;
7883         int link_ok, linkdnrc;
7884         enum fw_port_type port_type;
7885         enum fw_port_module_type mod_type;
7886         unsigned int speed, fc, fec;
7887         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
7888
7889         /* Extract the various fields from the Port Information message.
7890          */
7891         switch (action) {
7892         case FW_PORT_ACTION_GET_PORT_INFO: {
7893                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
7894
7895                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
7896                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
7897                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
7898                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
7899                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
7900                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
7901                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
7902                 linkattr = lstatus_to_fwcap(lstatus);
7903                 break;
7904         }
7905
7906         case FW_PORT_ACTION_GET_PORT_INFO32: {
7907                 u32 lstatus32;
7908
7909                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
7910                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
7911                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
7912                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
7913                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
7914                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
7915                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
7916                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
7917                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
7918                 break;
7919         }
7920
7921         default:
7922                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
7923                         be32_to_cpu(cmd->action_to_len16));
7924                 return;
7925         }
7926
7927         fec = fwcap_to_cc_fec(acaps);
7928         fc = fwcap_to_cc_pause(linkattr);
7929         speed = fwcap_to_speed(linkattr);
7930
7931         if (mod_type != pi->mod_type) {
7932                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
7933                  * various fundamental Port Capabilities which used to be
7934                  * immutable can now change radically.  We can now have
7935                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
7936                  * all change based on what Transceiver Module is inserted.
7937                  * So we need to record the Physical "Port" Capabilities on
7938                  * every Transceiver Module change.
7939                  */
7940                 lc->pcaps = pcaps;
7941
7942                 /* When a new Transceiver Module is inserted, the Firmware
7943                  * will examine its i2c EPROM to determine its type and
7944                  * general operating parameters including things like Forward
7945                  * Error Control, etc.  Various IEEE 802.3 standards dictate
7946                  * how to interpret these i2c values to determine default
7947                  * "sutomatic" settings.  We record these for future use when
7948                  * the user explicitly requests these standards-based values.
7949                  */
7950                 lc->def_acaps = acaps;
7951
7952                 /* Some versions of the early T6 Firmware "cheated" when
7953                  * handling different Transceiver Modules by changing the
7954                  * underlaying Port Type reported to the Host Drivers.  As
7955                  * such we need to capture whatever Port Type the Firmware
7956                  * sends us and record it in case it's different from what we
7957                  * were told earlier.  Unfortunately, since Firmware is
7958                  * forever, we'll need to keep this code here forever, but in
7959                  * later T6 Firmware it should just be an assignment of the
7960                  * same value already recorded.
7961                  */
7962                 pi->port_type = port_type;
7963
7964                 pi->mod_type = mod_type;
7965                 t4_os_portmod_changed(adapter, pi->port_id);
7966         }
7967
7968         if (link_ok != lc->link_ok || speed != lc->speed ||
7969             fc != lc->fc || fec != lc->fec) {   /* something changed */
7970                 if (!link_ok && lc->link_ok) {
7971                         lc->link_down_rc = linkdnrc;
7972                         dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
7973                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
7974                 }
7975                 lc->link_ok = link_ok;
7976                 lc->speed = speed;
7977                 lc->fc = fc;
7978                 lc->fec = fec;
7979
7980                 lc->lpacaps = lpacaps;
7981                 lc->acaps = acaps & ADVERT_MASK;
7982
7983                 if (lc->acaps & FW_PORT_CAP32_ANEG) {
7984                         lc->autoneg = AUTONEG_ENABLE;
7985                 } else {
7986                         /* When Autoneg is disabled, user needs to set
7987                          * single speed.
7988                          * Similar to cxgb4_ethtool.c: set_link_ksettings
7989                          */
7990                         lc->acaps = 0;
7991                         lc->speed_caps = fwcap_to_fwspeed(acaps);
7992                         lc->autoneg = AUTONEG_DISABLE;
7993                 }
7994
7995                 t4_os_link_changed(adapter, pi->port_id, link_ok);
7996         }
7997 }
7998
7999 /**
8000  *      t4_update_port_info - retrieve and update port information if changed
8001  *      @pi: the port_info
8002  *
8003  *      We issue a Get Port Information Command to the Firmware and, if
8004  *      successful, we check to see if anything is different from what we
8005  *      last recorded and update things accordingly.
8006  */
8007 int t4_update_port_info(struct port_info *pi)
8008 {
8009         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8010         struct fw_port_cmd port_cmd;
8011         int ret;
8012
8013         memset(&port_cmd, 0, sizeof(port_cmd));
8014         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8015                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8016                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8017         port_cmd.action_to_len16 = cpu_to_be32(
8018                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8019                                      ? FW_PORT_ACTION_GET_PORT_INFO
8020                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8021                 FW_LEN16(port_cmd));
8022         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8023                          &port_cmd, sizeof(port_cmd), &port_cmd);
8024         if (ret)
8025                 return ret;
8026
8027         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8028         return 0;
8029 }
8030
8031 /**
8032  *      t4_get_link_params - retrieve basic link parameters for given port
8033  *      @pi: the port
8034  *      @link_okp: value return pointer for link up/down
8035  *      @speedp: value return pointer for speed (Mb/s)
8036  *      @mtup: value return pointer for mtu
8037  *
8038  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8039  *      and MTU for a specified port.  A negative error is returned on
8040  *      failure; 0 on success.
8041  */
8042 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8043                        unsigned int *speedp, unsigned int *mtup)
8044 {
8045         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8046         struct fw_port_cmd port_cmd;
8047         unsigned int action, link_ok, speed, mtu;
8048         fw_port_cap32_t linkattr;
8049         int ret;
8050
8051         memset(&port_cmd, 0, sizeof(port_cmd));
8052         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8053                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8054                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8055         action = (fw_caps == FW_CAPS16
8056                   ? FW_PORT_ACTION_GET_PORT_INFO
8057                   : FW_PORT_ACTION_GET_PORT_INFO32);
8058         port_cmd.action_to_len16 = cpu_to_be32(
8059                 FW_PORT_CMD_ACTION_V(action) |
8060                 FW_LEN16(port_cmd));
8061         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8062                          &port_cmd, sizeof(port_cmd), &port_cmd);
8063         if (ret)
8064                 return ret;
8065
8066         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8067                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8068
8069                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8070                 linkattr = lstatus_to_fwcap(lstatus);
8071                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8072         } else {
8073                 u32 lstatus32 =
8074                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8075
8076                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8077                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8078                 mtu = FW_PORT_CMD_MTU32_G(
8079                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8080         }
8081         speed = fwcap_to_speed(linkattr);
8082
8083         *link_okp = link_ok;
8084         *speedp = fwcap_to_speed(linkattr);
8085         *mtup = mtu;
8086
8087         return 0;
8088 }
8089
8090 /**
8091  *      t4_handle_fw_rpl - process a FW reply message
8092  *      @adap: the adapter
8093  *      @rpl: start of the FW message
8094  *
8095  *      Processes a FW message, such as link state change messages.
8096  */
8097 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8098 {
8099         u8 opcode = *(const u8 *)rpl;
8100
8101         /* This might be a port command ... this simplifies the following
8102          * conditionals ...  We can get away with pre-dereferencing
8103          * action_to_len16 because it's in the first 16 bytes and all messages
8104          * will be at least that long.
8105          */
8106         const struct fw_port_cmd *p = (const void *)rpl;
8107         unsigned int action =
8108                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8109
8110         if (opcode == FW_PORT_CMD &&
8111             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8112              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8113                 int i;
8114                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8115                 struct port_info *pi = NULL;
8116
8117                 for_each_port(adap, i) {
8118                         pi = adap2pinfo(adap, i);
8119                         if (pi->tx_chan == chan)
8120                                 break;
8121                 }
8122
8123                 t4_handle_get_port_info(pi, rpl);
8124         } else {
8125                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8126                          opcode);
8127                 return -EINVAL;
8128         }
8129         return 0;
8130 }
8131
8132 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8133 {
8134         u16 val;
8135
8136         if (pci_is_pcie(adapter->pdev)) {
8137                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8138                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8139                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8140         }
8141 }
8142
8143 /**
8144  *      init_link_config - initialize a link's SW state
8145  *      @lc: pointer to structure holding the link state
8146  *      @pcaps: link Port Capabilities
8147  *      @acaps: link current Advertised Port Capabilities
8148  *
8149  *      Initializes the SW state maintained for each link, including the link's
8150  *      capabilities and default speed/flow-control/autonegotiation settings.
8151  */
8152 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8153                              fw_port_cap32_t acaps)
8154 {
8155         lc->pcaps = pcaps;
8156         lc->def_acaps = acaps;
8157         lc->lpacaps = 0;
8158         lc->speed_caps = 0;
8159         lc->speed = 0;
8160         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8161
8162         /* For Forward Error Control, we default to whatever the Firmware
8163          * tells us the Link is currently advertising.
8164          */
8165         lc->requested_fec = FEC_AUTO;
8166         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8167
8168         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8169                 lc->acaps = lc->pcaps & ADVERT_MASK;
8170                 lc->autoneg = AUTONEG_ENABLE;
8171                 lc->requested_fc |= PAUSE_AUTONEG;
8172         } else {
8173                 lc->acaps = 0;
8174                 lc->autoneg = AUTONEG_DISABLE;
8175         }
8176 }
8177
8178 #define CIM_PF_NOACCESS 0xeeeeeeee
8179
8180 int t4_wait_dev_ready(void __iomem *regs)
8181 {
8182         u32 whoami;
8183
8184         whoami = readl(regs + PL_WHOAMI_A);
8185         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8186                 return 0;
8187
8188         msleep(500);
8189         whoami = readl(regs + PL_WHOAMI_A);
8190         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8191 }
8192
8193 struct flash_desc {
8194         u32 vendor_and_model_id;
8195         u32 size_mb;
8196 };
8197
8198 static int get_flash_params(struct adapter *adap)
8199 {
8200         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8201          * to the preexisting code.  All flash parts have 64KB sectors.
8202          */
8203         static struct flash_desc supported_flash[] = {
8204                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8205         };
8206
8207         int ret;
8208         u32 info;
8209
8210         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8211         if (!ret)
8212                 ret = sf1_read(adap, 3, 0, 1, &info);
8213         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8214         if (ret)
8215                 return ret;
8216
8217         for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
8218                 if (supported_flash[ret].vendor_and_model_id == info) {
8219                         adap->params.sf_size = supported_flash[ret].size_mb;
8220                         adap->params.sf_nsec =
8221                                 adap->params.sf_size / SF_SEC_SIZE;
8222                         return 0;
8223                 }
8224
8225         if ((info & 0xff) != 0x20)             /* not a Numonix flash */
8226                 return -EINVAL;
8227         info >>= 16;                           /* log2 of size */
8228         if (info >= 0x14 && info < 0x18)
8229                 adap->params.sf_nsec = 1 << (info - 16);
8230         else if (info == 0x18)
8231                 adap->params.sf_nsec = 64;
8232         else
8233                 return -EINVAL;
8234         adap->params.sf_size = 1 << info;
8235         adap->params.sf_fw_start =
8236                 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
8237
8238         if (adap->params.sf_size < FLASH_MIN_SIZE)
8239                 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
8240                          adap->params.sf_size, FLASH_MIN_SIZE);
8241         return 0;
8242 }
8243
8244 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
8245 {
8246         u16 val;
8247         u32 pcie_cap;
8248
8249         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
8250         if (pcie_cap) {
8251                 pci_read_config_word(adapter->pdev,
8252                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
8253                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
8254                 val |= range;
8255                 pci_write_config_word(adapter->pdev,
8256                                       pcie_cap + PCI_EXP_DEVCTL2, val);
8257         }
8258 }
8259
8260 /**
8261  *      t4_prep_adapter - prepare SW and HW for operation
8262  *      @adapter: the adapter
8263  *      @reset: if true perform a HW reset
8264  *
8265  *      Initialize adapter SW state for the various HW modules, set initial
8266  *      values for some adapter tunables, take PHYs out of reset, and
8267  *      initialize the MDIO interface.
8268  */
8269 int t4_prep_adapter(struct adapter *adapter)
8270 {
8271         int ret, ver;
8272         uint16_t device_id;
8273         u32 pl_rev;
8274
8275         get_pci_mode(adapter, &adapter->params.pci);
8276         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8277
8278         ret = get_flash_params(adapter);
8279         if (ret < 0) {
8280                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8281                 return ret;
8282         }
8283
8284         /* Retrieve adapter's device ID
8285          */
8286         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8287         ver = device_id >> 12;
8288         adapter->params.chip = 0;
8289         switch (ver) {
8290         case CHELSIO_T4:
8291                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8292                 adapter->params.arch.sge_fl_db = DBPRIO_F;
8293                 adapter->params.arch.mps_tcam_size =
8294                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
8295                 adapter->params.arch.mps_rplc_size = 128;
8296                 adapter->params.arch.nchan = NCHAN;
8297                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8298                 adapter->params.arch.vfcount = 128;
8299                 /* Congestion map is for 4 channels so that
8300                  * MPS can have 4 priority per port.
8301                  */
8302                 adapter->params.arch.cng_ch_bits_log = 2;
8303                 break;
8304         case CHELSIO_T5:
8305                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8306                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8307                 adapter->params.arch.mps_tcam_size =
8308                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8309                 adapter->params.arch.mps_rplc_size = 128;
8310                 adapter->params.arch.nchan = NCHAN;
8311                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8312                 adapter->params.arch.vfcount = 128;
8313                 adapter->params.arch.cng_ch_bits_log = 2;
8314                 break;
8315         case CHELSIO_T6:
8316                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8317                 adapter->params.arch.sge_fl_db = 0;
8318                 adapter->params.arch.mps_tcam_size =
8319                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8320                 adapter->params.arch.mps_rplc_size = 256;
8321                 adapter->params.arch.nchan = 2;
8322                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8323                 adapter->params.arch.vfcount = 256;
8324                 /* Congestion map will be for 2 channels so that
8325                  * MPS can have 8 priority per port.
8326                  */
8327                 adapter->params.arch.cng_ch_bits_log = 3;
8328                 break;
8329         default:
8330                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8331                         device_id);
8332                 return -EINVAL;
8333         }
8334
8335         adapter->params.cim_la_size = CIMLA_SIZE;
8336         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8337
8338         /*
8339          * Default port for debugging in case we can't reach FW.
8340          */
8341         adapter->params.nports = 1;
8342         adapter->params.portvec = 1;
8343         adapter->params.vpd.cclk = 50000;
8344
8345         /* Set pci completion timeout value to 4 seconds. */
8346         set_pcie_completion_timeout(adapter, 0xd);
8347         return 0;
8348 }
8349
8350 /**
8351  *      t4_shutdown_adapter - shut down adapter, host & wire
8352  *      @adapter: the adapter
8353  *
8354  *      Perform an emergency shutdown of the adapter and stop it from
8355  *      continuing any further communication on the ports or DMA to the
8356  *      host.  This is typically used when the adapter and/or firmware
8357  *      have crashed and we want to prevent any further accidental
8358  *      communication with the rest of the world.  This will also force
8359  *      the port Link Status to go down -- if register writes work --
8360  *      which should help our peers figure out that we're down.
8361  */
8362 int t4_shutdown_adapter(struct adapter *adapter)
8363 {
8364         int port;
8365
8366         t4_intr_disable(adapter);
8367         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8368         for_each_port(adapter, port) {
8369                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8370                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
8371                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
8372
8373                 t4_write_reg(adapter, a_port_cfg,
8374                              t4_read_reg(adapter, a_port_cfg)
8375                              & ~SIGNAL_DET_V(1));
8376         }
8377         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8378
8379         return 0;
8380 }
8381
8382 /**
8383  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8384  *      @adapter: the adapter
8385  *      @qid: the Queue ID
8386  *      @qtype: the Ingress or Egress type for @qid
8387  *      @user: true if this request is for a user mode queue
8388  *      @pbar2_qoffset: BAR2 Queue Offset
8389  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8390  *
8391  *      Returns the BAR2 SGE Queue Registers information associated with the
8392  *      indicated Absolute Queue ID.  These are passed back in return value
8393  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8394  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8395  *
8396  *      This may return an error which indicates that BAR2 SGE Queue
8397  *      registers aren't available.  If an error is not returned, then the
8398  *      following values are returned:
8399  *
8400  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8401  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8402  *
8403  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8404  *      require the "Inferred Queue ID" ability may be used.  E.g. the
8405  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8406  *      then these "Inferred Queue ID" register may not be used.
8407  */
8408 int t4_bar2_sge_qregs(struct adapter *adapter,
8409                       unsigned int qid,
8410                       enum t4_bar2_qtype qtype,
8411                       int user,
8412                       u64 *pbar2_qoffset,
8413                       unsigned int *pbar2_qid)
8414 {
8415         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
8416         u64 bar2_page_offset, bar2_qoffset;
8417         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
8418
8419         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8420         if (!user && is_t4(adapter->params.chip))
8421                 return -EINVAL;
8422
8423         /* Get our SGE Page Size parameters.
8424          */
8425         page_shift = adapter->params.sge.hps + 10;
8426         page_size = 1 << page_shift;
8427
8428         /* Get the right Queues per Page parameters for our Queue.
8429          */
8430         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
8431                      ? adapter->params.sge.eq_qpp
8432                      : adapter->params.sge.iq_qpp);
8433         qpp_mask = (1 << qpp_shift) - 1;
8434
8435         /*  Calculate the basics of the BAR2 SGE Queue register area:
8436          *  o The BAR2 page the Queue registers will be in.
8437          *  o The BAR2 Queue ID.
8438          *  o The BAR2 Queue ID Offset into the BAR2 page.
8439          */
8440         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
8441         bar2_qid = qid & qpp_mask;
8442         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
8443
8444         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8445          * hardware will infer the Absolute Queue ID simply from the writes to
8446          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8447          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
8448          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8449          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8450          * from the BAR2 Page and BAR2 Queue ID.
8451          *
8452          * One important censequence of this is that some BAR2 SGE registers
8453          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8454          * there.  But other registers synthesize the SGE Queue ID purely
8455          * from the writes to the registers -- the Write Combined Doorbell
8456          * Buffer is a good example.  These BAR2 SGE Registers are only
8457          * available for those BAR2 SGE Register areas where the SGE Absolute
8458          * Queue ID can be inferred from simple writes.
8459          */
8460         bar2_qoffset = bar2_page_offset;
8461         bar2_qinferred = (bar2_qid_offset < page_size);
8462         if (bar2_qinferred) {
8463                 bar2_qoffset += bar2_qid_offset;
8464                 bar2_qid = 0;
8465         }
8466
8467         *pbar2_qoffset = bar2_qoffset;
8468         *pbar2_qid = bar2_qid;
8469         return 0;
8470 }
8471
8472 /**
8473  *      t4_init_devlog_params - initialize adapter->params.devlog
8474  *      @adap: the adapter
8475  *
8476  *      Initialize various fields of the adapter's Firmware Device Log
8477  *      Parameters structure.
8478  */
8479 int t4_init_devlog_params(struct adapter *adap)
8480 {
8481         struct devlog_params *dparams = &adap->params.devlog;
8482         u32 pf_dparams;
8483         unsigned int devlog_meminfo;
8484         struct fw_devlog_cmd devlog_cmd;
8485         int ret;
8486
8487         /* If we're dealing with newer firmware, the Device Log Paramerters
8488          * are stored in a designated register which allows us to access the
8489          * Device Log even if we can't talk to the firmware.
8490          */
8491         pf_dparams =
8492                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
8493         if (pf_dparams) {
8494                 unsigned int nentries, nentries128;
8495
8496                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
8497                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
8498
8499                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
8500                 nentries = (nentries128 + 1) * 128;
8501                 dparams->size = nentries * sizeof(struct fw_devlog_e);
8502
8503                 return 0;
8504         }
8505
8506         /* Otherwise, ask the firmware for it's Device Log Parameters.
8507          */
8508         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
8509         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
8510                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
8511         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
8512         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
8513                          &devlog_cmd);
8514         if (ret)
8515                 return ret;
8516
8517         devlog_meminfo =
8518                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
8519         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
8520         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
8521         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8522
8523         return 0;
8524 }
8525
8526 /**
8527  *      t4_init_sge_params - initialize adap->params.sge
8528  *      @adapter: the adapter
8529  *
8530  *      Initialize various fields of the adapter's SGE Parameters structure.
8531  */
8532 int t4_init_sge_params(struct adapter *adapter)
8533 {
8534         struct sge_params *sge_params = &adapter->params.sge;
8535         u32 hps, qpp;
8536         unsigned int s_hps, s_qpp;
8537
8538         /* Extract the SGE Page Size for our PF.
8539          */
8540         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
8541         s_hps = (HOSTPAGESIZEPF0_S +
8542                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
8543         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
8544
8545         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8546          */
8547         s_qpp = (QUEUESPERPAGEPF0_S +
8548                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
8549         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
8550         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8551         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
8552         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8553
8554         return 0;
8555 }
8556
8557 /**
8558  *      t4_init_tp_params - initialize adap->params.tp
8559  *      @adap: the adapter
8560  *
8561  *      Initialize various fields of the adapter's TP Parameters structure.
8562  */
8563 int t4_init_tp_params(struct adapter *adap)
8564 {
8565         int chan;
8566         u32 v;
8567
8568         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
8569         adap->params.tp.tre = TIMERRESOLUTION_G(v);
8570         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
8571
8572         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8573         for (chan = 0; chan < NCHAN; chan++)
8574                 adap->params.tp.tx_modq[chan] = chan;
8575
8576         /* Cache the adapter's Compressed Filter Mode and global Incress
8577          * Configuration.
8578          */
8579         if (t4_use_ldst(adap)) {
8580                 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
8581                                 TP_VLAN_PRI_MAP_A, 1);
8582                 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
8583                                 TP_INGRESS_CONFIG_A, 1);
8584         } else {
8585                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8586                                  &adap->params.tp.vlan_pri_map, 1,
8587                                  TP_VLAN_PRI_MAP_A);
8588                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8589                                  &adap->params.tp.ingress_config, 1,
8590                                  TP_INGRESS_CONFIG_A);
8591         }
8592         /* For T6, cache the adapter's compressed error vector
8593          * and passing outer header info for encapsulated packets.
8594          */
8595         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
8596                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
8597                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
8598         }
8599
8600         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8601          * shift positions of several elements of the Compressed Filter Tuple
8602          * for this adapter which we need frequently ...
8603          */
8604         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
8605         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
8606         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
8607         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
8608                                                                PROTOCOL_F);
8609
8610         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8611          * represents the presence of an Outer VLAN instead of a VNIC ID.
8612          */
8613         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
8614                 adap->params.tp.vnic_shift = -1;
8615
8616         return 0;
8617 }
8618
8619 /**
8620  *      t4_filter_field_shift - calculate filter field shift
8621  *      @adap: the adapter
8622  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8623  *
8624  *      Return the shift position of a filter field within the Compressed
8625  *      Filter Tuple.  The filter field is specified via its selection bit
8626  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8627  */
8628 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8629 {
8630         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8631         unsigned int sel;
8632         int field_shift;
8633
8634         if ((filter_mode & filter_sel) == 0)
8635                 return -1;
8636
8637         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8638                 switch (filter_mode & sel) {
8639                 case FCOE_F:
8640                         field_shift += FT_FCOE_W;
8641                         break;
8642                 case PORT_F:
8643                         field_shift += FT_PORT_W;
8644                         break;
8645                 case VNIC_ID_F:
8646                         field_shift += FT_VNIC_ID_W;
8647                         break;
8648                 case VLAN_F:
8649                         field_shift += FT_VLAN_W;
8650                         break;
8651                 case TOS_F:
8652                         field_shift += FT_TOS_W;
8653                         break;
8654                 case PROTOCOL_F:
8655                         field_shift += FT_PROTOCOL_W;
8656                         break;
8657                 case ETHERTYPE_F:
8658                         field_shift += FT_ETHERTYPE_W;
8659                         break;
8660                 case MACMATCH_F:
8661                         field_shift += FT_MACMATCH_W;
8662                         break;
8663                 case MPSHITTYPE_F:
8664                         field_shift += FT_MPSHITTYPE_W;
8665                         break;
8666                 case FRAGMENTATION_F:
8667                         field_shift += FT_FRAGMENTATION_W;
8668                         break;
8669                 }
8670         }
8671         return field_shift;
8672 }
8673
8674 int t4_init_rss_mode(struct adapter *adap, int mbox)
8675 {
8676         int i, ret;
8677         struct fw_rss_vi_config_cmd rvc;
8678
8679         memset(&rvc, 0, sizeof(rvc));
8680
8681         for_each_port(adap, i) {
8682                 struct port_info *p = adap2pinfo(adap, i);
8683
8684                 rvc.op_to_viid =
8685                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
8686                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
8687                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
8688                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
8689                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
8690                 if (ret)
8691                         return ret;
8692                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
8693         }
8694         return 0;
8695 }
8696
8697 /**
8698  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
8699  *      @pi: the port_info
8700  *      @mbox: mailbox to use for the FW command
8701  *      @port: physical port associated with the VI
8702  *      @pf: the PF owning the VI
8703  *      @vf: the VF owning the VI
8704  *      @mac: the MAC address of the VI
8705  *
8706  *      Allocates a virtual interface for the given physical port.  If @mac is
8707  *      not %NULL it contains the MAC address of the VI as assigned by FW.
8708  *      @mac should be large enough to hold an Ethernet address.
8709  *      Returns < 0 on error.
8710  */
8711 int t4_init_portinfo(struct port_info *pi, int mbox,
8712                      int port, int pf, int vf, u8 mac[])
8713 {
8714         struct adapter *adapter = pi->adapter;
8715         unsigned int fw_caps = adapter->params.fw_caps_support;
8716         struct fw_port_cmd cmd;
8717         unsigned int rss_size;
8718         enum fw_port_type port_type;
8719         int mdio_addr;
8720         fw_port_cap32_t pcaps, acaps;
8721         int ret;
8722
8723         /* If we haven't yet determined whether we're talking to Firmware
8724          * which knows the new 32-bit Port Capabilities, it's time to find
8725          * out now.  This will also tell new Firmware to send us Port Status
8726          * Updates using the new 32-bit Port Capabilities version of the
8727          * Port Information message.
8728          */
8729         if (fw_caps == FW_CAPS_UNKNOWN) {
8730                 u32 param, val;
8731
8732                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
8733                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
8734                 val = 1;
8735                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
8736                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
8737                 adapter->params.fw_caps_support = fw_caps;
8738         }
8739
8740         memset(&cmd, 0, sizeof(cmd));
8741         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8742                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
8743                                        FW_PORT_CMD_PORTID_V(port));
8744         cmd.action_to_len16 = cpu_to_be32(
8745                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8746                                      ? FW_PORT_ACTION_GET_PORT_INFO
8747                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8748                 FW_LEN16(cmd));
8749         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
8750         if (ret)
8751                 return ret;
8752
8753         /* Extract the various fields from the Port Information message.
8754          */
8755         if (fw_caps == FW_CAPS16) {
8756                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
8757
8758                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8759                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
8760                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
8761                              : -1);
8762                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
8763                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
8764         } else {
8765                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
8766
8767                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8768                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
8769                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
8770                              : -1);
8771                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
8772                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
8773         }
8774
8775         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
8776         if (ret < 0)
8777                 return ret;
8778
8779         pi->viid = ret;
8780         pi->tx_chan = port;
8781         pi->lport = port;
8782         pi->rss_size = rss_size;
8783
8784         pi->port_type = port_type;
8785         pi->mdio_addr = mdio_addr;
8786         pi->mod_type = FW_PORT_MOD_TYPE_NA;
8787
8788         init_link_config(&pi->link_cfg, pcaps, acaps);
8789         return 0;
8790 }
8791
8792 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8793 {
8794         u8 addr[6];
8795         int ret, i, j = 0;
8796
8797         for_each_port(adap, i) {
8798                 struct port_info *pi = adap2pinfo(adap, i);
8799
8800                 while ((adap->params.portvec & (1 << j)) == 0)
8801                         j++;
8802
8803                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8804                 if (ret)
8805                         return ret;
8806
8807                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8808                 j++;
8809         }
8810         return 0;
8811 }
8812
8813 /**
8814  *      t4_read_cimq_cfg - read CIM queue configuration
8815  *      @adap: the adapter
8816  *      @base: holds the queue base addresses in bytes
8817  *      @size: holds the queue sizes in bytes
8818  *      @thres: holds the queue full thresholds in bytes
8819  *
8820  *      Returns the current configuration of the CIM queues, starting with
8821  *      the IBQs, then the OBQs.
8822  */
8823 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8824 {
8825         unsigned int i, v;
8826         int cim_num_obq = is_t4(adap->params.chip) ?
8827                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8828
8829         for (i = 0; i < CIM_NUM_IBQ; i++) {
8830                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8831                              QUENUMSELECT_V(i));
8832                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8833                 /* value is in 256-byte units */
8834                 *base++ = CIMQBASE_G(v) * 256;
8835                 *size++ = CIMQSIZE_G(v) * 256;
8836                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8837         }
8838         for (i = 0; i < cim_num_obq; i++) {
8839                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8840                              QUENUMSELECT_V(i));
8841                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8842                 /* value is in 256-byte units */
8843                 *base++ = CIMQBASE_G(v) * 256;
8844                 *size++ = CIMQSIZE_G(v) * 256;
8845         }
8846 }
8847
8848 /**
8849  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
8850  *      @adap: the adapter
8851  *      @qid: the queue index
8852  *      @data: where to store the queue contents
8853  *      @n: capacity of @data in 32-bit words
8854  *
8855  *      Reads the contents of the selected CIM queue starting at address 0 up
8856  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8857  *      error and the number of 32-bit words actually read on success.
8858  */
8859 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8860 {
8861         int i, err, attempts;
8862         unsigned int addr;
8863         const unsigned int nwords = CIM_IBQ_SIZE * 4;
8864
8865         if (qid > 5 || (n & 3))
8866                 return -EINVAL;
8867
8868         addr = qid * nwords;
8869         if (n > nwords)
8870                 n = nwords;
8871
8872         /* It might take 3-10ms before the IBQ debug read access is allowed.
8873          * Wait for 1 Sec with a delay of 1 usec.
8874          */
8875         attempts = 1000000;
8876
8877         for (i = 0; i < n; i++, addr++) {
8878                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8879                              IBQDBGEN_F);
8880                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8881                                       attempts, 1);
8882                 if (err)
8883                         return err;
8884                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8885         }
8886         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8887         return i;
8888 }
8889
8890 /**
8891  *      t4_read_cim_obq - read the contents of a CIM outbound queue
8892  *      @adap: the adapter
8893  *      @qid: the queue index
8894  *      @data: where to store the queue contents
8895  *      @n: capacity of @data in 32-bit words
8896  *
8897  *      Reads the contents of the selected CIM queue starting at address 0 up
8898  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8899  *      error and the number of 32-bit words actually read on success.
8900  */
8901 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8902 {
8903         int i, err;
8904         unsigned int addr, v, nwords;
8905         int cim_num_obq = is_t4(adap->params.chip) ?
8906                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8907
8908         if ((qid > (cim_num_obq - 1)) || (n & 3))
8909                 return -EINVAL;
8910
8911         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8912                      QUENUMSELECT_V(qid));
8913         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8914
8915         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
8916         nwords = CIMQSIZE_G(v) * 64;  /* same */
8917         if (n > nwords)
8918                 n = nwords;
8919
8920         for (i = 0; i < n; i++, addr++) {
8921                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
8922                              OBQDBGEN_F);
8923                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
8924                                       2, 1);
8925                 if (err)
8926                         return err;
8927                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
8928         }
8929         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
8930         return i;
8931 }
8932
8933 /**
8934  *      t4_cim_read - read a block from CIM internal address space
8935  *      @adap: the adapter
8936  *      @addr: the start address within the CIM address space
8937  *      @n: number of words to read
8938  *      @valp: where to store the result
8939  *
8940  *      Reads a block of 4-byte words from the CIM intenal address space.
8941  */
8942 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8943                 unsigned int *valp)
8944 {
8945         int ret = 0;
8946
8947         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8948                 return -EBUSY;
8949
8950         for ( ; !ret && n--; addr += 4) {
8951                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8952                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8953                                       0, 5, 2);
8954                 if (!ret)
8955                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8956         }
8957         return ret;
8958 }
8959
8960 /**
8961  *      t4_cim_write - write a block into CIM internal address space
8962  *      @adap: the adapter
8963  *      @addr: the start address within the CIM address space
8964  *      @n: number of words to write
8965  *      @valp: set of values to write
8966  *
8967  *      Writes a block of 4-byte words into the CIM intenal address space.
8968  */
8969 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8970                  const unsigned int *valp)
8971 {
8972         int ret = 0;
8973
8974         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8975                 return -EBUSY;
8976
8977         for ( ; !ret && n--; addr += 4) {
8978                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8979                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8980                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8981                                       0, 5, 2);
8982         }
8983         return ret;
8984 }
8985
8986 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8987                          unsigned int val)
8988 {
8989         return t4_cim_write(adap, addr, 1, &val);
8990 }
8991
8992 /**
8993  *      t4_cim_read_la - read CIM LA capture buffer
8994  *      @adap: the adapter
8995  *      @la_buf: where to store the LA data
8996  *      @wrptr: the HW write pointer within the capture buffer
8997  *
8998  *      Reads the contents of the CIM LA buffer with the most recent entry at
8999  *      the end of the returned data and with the entry at @wrptr first.
9000  *      We try to leave the LA in the running state we find it in.
9001  */
9002 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9003 {
9004         int i, ret;
9005         unsigned int cfg, val, idx;
9006
9007         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9008         if (ret)
9009                 return ret;
9010
9011         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9012                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9013                 if (ret)
9014                         return ret;
9015         }
9016
9017         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9018         if (ret)
9019                 goto restart;
9020
9021         idx = UPDBGLAWRPTR_G(val);
9022         if (wrptr)
9023                 *wrptr = idx;
9024
9025         for (i = 0; i < adap->params.cim_la_size; i++) {
9026                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9027                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9028                 if (ret)
9029                         break;
9030                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9031                 if (ret)
9032                         break;
9033                 if (val & UPDBGLARDEN_F) {
9034                         ret = -ETIMEDOUT;
9035                         break;
9036                 }
9037                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9038                 if (ret)
9039                         break;
9040
9041                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9042                  * identify the 32-bit portion of the full 312-bit data
9043                  */
9044                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9045                         idx = (idx & 0xff0) + 0x10;
9046                 else
9047                         idx++;
9048                 /* address can't exceed 0xfff */
9049                 idx &= UPDBGLARDPTR_M;
9050         }
9051 restart:
9052         if (cfg & UPDBGLAEN_F) {
9053                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9054                                       cfg & ~UPDBGLARDEN_F);
9055                 if (!ret)
9056                         ret = r;
9057         }
9058         return ret;
9059 }
9060
9061 /**
9062  *      t4_tp_read_la - read TP LA capture buffer
9063  *      @adap: the adapter
9064  *      @la_buf: where to store the LA data
9065  *      @wrptr: the HW write pointer within the capture buffer
9066  *
9067  *      Reads the contents of the TP LA buffer with the most recent entry at
9068  *      the end of the returned data and with the entry at @wrptr first.
9069  *      We leave the LA in the running state we find it in.
9070  */
9071 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9072 {
9073         bool last_incomplete;
9074         unsigned int i, cfg, val, idx;
9075
9076         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9077         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9078                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9079                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9080
9081         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9082         idx = DBGLAWPTR_G(val);
9083         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9084         if (last_incomplete)
9085                 idx = (idx + 1) & DBGLARPTR_M;
9086         if (wrptr)
9087                 *wrptr = idx;
9088
9089         val &= 0xffff;
9090         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9091         val |= adap->params.tp.la_mask;
9092
9093         for (i = 0; i < TPLA_SIZE; i++) {
9094                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9095                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9096                 idx = (idx + 1) & DBGLARPTR_M;
9097         }
9098
9099         /* Wipe out last entry if it isn't valid */
9100         if (last_incomplete)
9101                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9102
9103         if (cfg & DBGLAENABLE_F)                    /* restore running state */
9104                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9105                              cfg | adap->params.tp.la_mask);
9106 }
9107
9108 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9109  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9110  * state for more than the Warning Threshold then we'll issue a warning about
9111  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9112  * appears to be hung every Warning Repeat second till the situation clears.
9113  * If the situation clears, we'll note that as well.
9114  */
9115 #define SGE_IDMA_WARN_THRESH 1
9116 #define SGE_IDMA_WARN_REPEAT 300
9117
9118 /**
9119  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9120  *      @adapter: the adapter
9121  *      @idma: the adapter IDMA Monitor state
9122  *
9123  *      Initialize the state of an SGE Ingress DMA Monitor.
9124  */
9125 void t4_idma_monitor_init(struct adapter *adapter,
9126                           struct sge_idma_monitor_state *idma)
9127 {
9128         /* Initialize the state variables for detecting an SGE Ingress DMA
9129          * hang.  The SGE has internal counters which count up on each clock
9130          * tick whenever the SGE finds its Ingress DMA State Engines in the
9131          * same state they were on the previous clock tick.  The clock used is
9132          * the Core Clock so we have a limit on the maximum "time" they can
9133          * record; typically a very small number of seconds.  For instance,
9134          * with a 600MHz Core Clock, we can only count up to a bit more than
9135          * 7s.  So we'll synthesize a larger counter in order to not run the
9136          * risk of having the "timers" overflow and give us the flexibility to
9137          * maintain a Hung SGE State Machine of our own which operates across
9138          * a longer time frame.
9139          */
9140         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9141         idma->idma_stalled[0] = 0;
9142         idma->idma_stalled[1] = 0;
9143 }
9144
9145 /**
9146  *      t4_idma_monitor - monitor SGE Ingress DMA state
9147  *      @adapter: the adapter
9148  *      @idma: the adapter IDMA Monitor state
9149  *      @hz: number of ticks/second
9150  *      @ticks: number of ticks since the last IDMA Monitor call
9151  */
9152 void t4_idma_monitor(struct adapter *adapter,
9153                      struct sge_idma_monitor_state *idma,
9154                      int hz, int ticks)
9155 {
9156         int i, idma_same_state_cnt[2];
9157
9158          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9159           * are counters inside the SGE which count up on each clock when the
9160           * SGE finds its Ingress DMA State Engines in the same states they
9161           * were in the previous clock.  The counters will peg out at
9162           * 0xffffffff without wrapping around so once they pass the 1s
9163           * threshold they'll stay above that till the IDMA state changes.
9164           */
9165         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9166         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9167         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9168
9169         for (i = 0; i < 2; i++) {
9170                 u32 debug0, debug11;
9171
9172                 /* If the Ingress DMA Same State Counter ("timer") is less
9173                  * than 1s, then we can reset our synthesized Stall Timer and
9174                  * continue.  If we have previously emitted warnings about a
9175                  * potential stalled Ingress Queue, issue a note indicating
9176                  * that the Ingress Queue has resumed forward progress.
9177                  */
9178                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9179                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9180                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9181                                          "resumed after %d seconds\n",
9182                                          i, idma->idma_qid[i],
9183                                          idma->idma_stalled[i] / hz);
9184                         idma->idma_stalled[i] = 0;
9185                         continue;
9186                 }
9187
9188                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9189                  * domain.  The first time we get here it'll be because we
9190                  * passed the 1s Threshold; each additional time it'll be
9191                  * because the RX Timer Callback is being fired on its regular
9192                  * schedule.
9193                  *
9194                  * If the stall is below our Potential Hung Ingress Queue
9195                  * Warning Threshold, continue.
9196                  */
9197                 if (idma->idma_stalled[i] == 0) {
9198                         idma->idma_stalled[i] = hz;
9199                         idma->idma_warn[i] = 0;
9200                 } else {
9201                         idma->idma_stalled[i] += ticks;
9202                         idma->idma_warn[i] -= ticks;
9203                 }
9204
9205                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9206                         continue;
9207
9208                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9209                  */
9210                 if (idma->idma_warn[i] > 0)
9211                         continue;
9212                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9213
9214                 /* Read and save the SGE IDMA State and Queue ID information.
9215                  * We do this every time in case it changes across time ...
9216                  * can't be too careful ...
9217                  */
9218                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9219                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9220                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9221
9222                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9223                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9224                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9225
9226                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9227                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9228                          i, idma->idma_qid[i], idma->idma_state[i],
9229                          idma->idma_stalled[i] / hz,
9230                          debug0, debug11);
9231                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9232         }
9233 }
9234
9235 /**
9236  *      t4_load_cfg - download config file
9237  *      @adap: the adapter
9238  *      @cfg_data: the cfg text file to write
9239  *      @size: text file size
9240  *
9241  *      Write the supplied config text file to the card's serial flash.
9242  */
9243 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9244 {
9245         int ret, i, n, cfg_addr;
9246         unsigned int addr;
9247         unsigned int flash_cfg_start_sec;
9248         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9249
9250         cfg_addr = t4_flash_cfg_addr(adap);
9251         if (cfg_addr < 0)
9252                 return cfg_addr;
9253
9254         addr = cfg_addr;
9255         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9256
9257         if (size > FLASH_CFG_MAX_SIZE) {
9258                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9259                         FLASH_CFG_MAX_SIZE);
9260                 return -EFBIG;
9261         }
9262
9263         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
9264                          sf_sec_size);
9265         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9266                                      flash_cfg_start_sec + i - 1);
9267         /* If size == 0 then we're simply erasing the FLASH sectors associated
9268          * with the on-adapter Firmware Configuration File.
9269          */
9270         if (ret || size == 0)
9271                 goto out;
9272
9273         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9274         for (i = 0; i < size; i += SF_PAGE_SIZE) {
9275                 if ((size - i) <  SF_PAGE_SIZE)
9276                         n = size - i;
9277                 else
9278                         n = SF_PAGE_SIZE;
9279                 ret = t4_write_flash(adap, addr, n, cfg_data);
9280                 if (ret)
9281                         goto out;
9282
9283                 addr += SF_PAGE_SIZE;
9284                 cfg_data += SF_PAGE_SIZE;
9285         }
9286
9287 out:
9288         if (ret)
9289                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9290                         (size == 0 ? "clear" : "download"), ret);
9291         return ret;
9292 }
9293
9294 /**
9295  *      t4_set_vf_mac - Set MAC address for the specified VF
9296  *      @adapter: The adapter
9297  *      @vf: one of the VFs instantiated by the specified PF
9298  *      @naddr: the number of MAC addresses
9299  *      @addr: the MAC address(es) to be set to the specified VF
9300  */
9301 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9302                       unsigned int naddr, u8 *addr)
9303 {
9304         struct fw_acl_mac_cmd cmd;
9305
9306         memset(&cmd, 0, sizeof(cmd));
9307         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9308                                     FW_CMD_REQUEST_F |
9309                                     FW_CMD_WRITE_F |
9310                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9311                                     FW_ACL_MAC_CMD_VFN_V(vf));
9312
9313         /* Note: Do not enable the ACL */
9314         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9315         cmd.nmac = naddr;
9316
9317         switch (adapter->pf) {
9318         case 3:
9319                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9320                 break;
9321         case 2:
9322                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9323                 break;
9324         case 1:
9325                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9326                 break;
9327         case 0:
9328                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9329                 break;
9330         }
9331
9332         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9333 }
9334
9335 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9336                     int rateunit, int ratemode, int channel, int class,
9337                     int minrate, int maxrate, int weight, int pktsize)
9338 {
9339         struct fw_sched_cmd cmd;
9340
9341         memset(&cmd, 0, sizeof(cmd));
9342         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
9343                                       FW_CMD_REQUEST_F |
9344                                       FW_CMD_WRITE_F);
9345         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9346
9347         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9348         cmd.u.params.type = type;
9349         cmd.u.params.level = level;
9350         cmd.u.params.mode = mode;
9351         cmd.u.params.ch = channel;
9352         cmd.u.params.cl = class;
9353         cmd.u.params.unit = rateunit;
9354         cmd.u.params.rate = ratemode;
9355         cmd.u.params.min = cpu_to_be32(minrate);
9356         cmd.u.params.max = cpu_to_be32(maxrate);
9357         cmd.u.params.weight = cpu_to_be16(weight);
9358         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9359
9360         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
9361                                NULL, 1);
9362 }