2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
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7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
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10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
50 CPL_RX_DATA_ACK = 0xD,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
54 CPL_TX_DATA_ISO = 0x1F,
56 CPL_CLOSE_LISTSRV_RPL = 0x20,
57 CPL_L2T_WRITE_RPL = 0x23,
58 CPL_PASS_OPEN_RPL = 0x24,
59 CPL_ACT_OPEN_RPL = 0x25,
60 CPL_PEER_CLOSE = 0x26,
61 CPL_ABORT_REQ_RSS = 0x2B,
62 CPL_ABORT_RPL_RSS = 0x2D,
64 CPL_RX_PHYS_ADDR = 0x30,
65 CPL_CLOSE_CON_RPL = 0x32,
68 CPL_RDMA_CQE_READ_RSP = 0x36,
69 CPL_RDMA_CQE_ERR = 0x37,
71 CPL_SET_TCB_RPL = 0x3A,
73 CPL_RX_DDP_COMPLETE = 0x3F,
75 CPL_ACT_ESTABLISH = 0x40,
76 CPL_PASS_ESTABLISH = 0x41,
77 CPL_RX_DATA_DDP = 0x42,
78 CPL_PASS_ACCEPT_REQ = 0x44,
79 CPL_RX_ISCSI_CMP = 0x45,
80 CPL_TRACE_PKT_T5 = 0x48,
81 CPL_RX_ISCSI_DDP = 0x49,
83 CPL_RDMA_READ_REQ = 0x60,
85 CPL_PASS_OPEN_REQ6 = 0x81,
86 CPL_ACT_OPEN_REQ6 = 0x83,
88 CPL_TX_TLS_PDU = 0x88,
89 CPL_TX_SEC_PDU = 0x8A,
90 CPL_TX_TLS_ACK = 0x8B,
92 CPL_RDMA_TERMINATE = 0xA2,
93 CPL_RDMA_WRITE = 0xA4,
94 CPL_SGE_EGR_UPDATE = 0xA5,
95 CPL_RX_MPS_PKT = 0xAF,
98 CPL_ISCSI_DATA = 0xB2,
104 CPL_RX_PHYS_DSGL = 0xD0,
108 CPL_TX_PKT_LSO = 0xED,
109 CPL_TX_PKT_XT = 0xEE,
116 CPL_ERR_TCAM_PARITY = 1,
117 CPL_ERR_TCAM_MISS = 2,
118 CPL_ERR_TCAM_FULL = 3,
119 CPL_ERR_BAD_LENGTH = 15,
120 CPL_ERR_BAD_ROUTE = 18,
121 CPL_ERR_CONN_RESET = 20,
122 CPL_ERR_CONN_EXIST_SYNRECV = 21,
123 CPL_ERR_CONN_EXIST = 22,
124 CPL_ERR_ARP_MISS = 23,
125 CPL_ERR_BAD_SYN = 24,
126 CPL_ERR_CONN_TIMEDOUT = 30,
127 CPL_ERR_XMIT_TIMEDOUT = 31,
128 CPL_ERR_PERSIST_TIMEDOUT = 32,
129 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
130 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
131 CPL_ERR_RTX_NEG_ADVICE = 35,
132 CPL_ERR_PERSIST_NEG_ADVICE = 36,
133 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
134 CPL_ERR_ABORT_FAILED = 42,
135 CPL_ERR_IWARP_FLM = 50,
139 CPL_CONN_POLICY_AUTO = 0,
140 CPL_CONN_POLICY_ASK = 1,
141 CPL_CONN_POLICY_FILTER = 2,
142 CPL_CONN_POLICY_DENY = 3
154 ULP_CRC_HEADER = 1 << 0,
155 ULP_CRC_DATA = 1 << 1
159 CPL_ABORT_SEND_RST = 0,
163 enum { /* TX_PKT_XT checksum types */
182 #define CPL_OPCODE_S 24
183 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
184 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
185 #define TID_G(x) ((x) & 0xFFFFFF)
187 /* tid is assumed to be 24-bits */
188 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
190 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
192 /* extract the TID from a CPL command */
193 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
195 /* partitioning of TID fields that also carry a queue id */
197 #define TID_TID_M 0x3fff
198 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
201 #define TID_QID_M 0x3ff
202 #define TID_QID_V(x) ((x) << TID_QID_S)
203 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
207 #if defined(__LITTLE_ENDIAN_BITFIELD)
226 struct work_request_hdr {
234 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
236 #define WR_HDR struct work_request_hdr wr
238 /* option 0 fields */
240 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
243 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
245 #define RCV_BUFSIZ_S 12
246 #define RCV_BUFSIZ_M 0x3FFU
247 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
249 #define SMAC_SEL_S 28
250 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
253 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
255 #define WND_SCALE_S 50
256 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
258 #define KEEP_ALIVE_S 54
259 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
260 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
263 #define MSS_IDX_M 0xF
264 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
265 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
267 /* option 2 fields */
268 #define RSS_QUEUE_S 0
269 #define RSS_QUEUE_M 0x3FF
270 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
271 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
273 #define RSS_QUEUE_VALID_S 10
274 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
275 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
277 #define RX_FC_DISABLE_S 20
278 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
279 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
281 #define RX_FC_VALID_S 22
282 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
283 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
285 #define RX_CHANNEL_S 26
286 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
288 #define WND_SCALE_EN_S 28
289 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
290 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
292 #define T5_OPT_2_VALID_S 31
293 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
294 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
296 struct cpl_pass_open_req {
307 /* option 0 fields */
309 #define NO_CONG_V(x) ((x) << NO_CONG_S)
310 #define NO_CONG_F NO_CONG_V(1U)
313 #define DELACK_V(x) ((x) << DELACK_S)
314 #define DELACK_F DELACK_V(1U)
318 #define DSCP_V(x) ((x) << DSCP_S)
319 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
321 #define TCAM_BYPASS_S 48
322 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
323 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
326 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
327 #define NAGLE_F NAGLE_V(1ULL)
329 /* option 1 fields */
330 #define SYN_RSS_ENABLE_S 0
331 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
332 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
334 #define SYN_RSS_QUEUE_S 2
335 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
337 #define CONN_POLICY_S 22
338 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
340 struct cpl_pass_open_req6 {
353 struct cpl_pass_open_rpl {
362 #if defined(__LITTLE_ENDIAN_BITFIELD)
377 struct cpl_pass_accept_req {
385 struct tcp_options tcpopt;
388 /* cpl_pass_accept_req.hdr_len fields */
389 #define SYN_RX_CHAN_S 0
390 #define SYN_RX_CHAN_M 0xF
391 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
392 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
394 #define TCP_HDR_LEN_S 10
395 #define TCP_HDR_LEN_M 0x3F
396 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
397 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
399 #define IP_HDR_LEN_S 16
400 #define IP_HDR_LEN_M 0x3FF
401 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
402 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
404 #define ETH_HDR_LEN_S 26
405 #define ETH_HDR_LEN_M 0x1F
406 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
407 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
409 /* cpl_pass_accept_req.l2info fields */
410 #define SYN_MAC_IDX_S 0
411 #define SYN_MAC_IDX_M 0x1FF
412 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
413 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
415 #define SYN_XACT_MATCH_S 9
416 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
417 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
419 #define SYN_INTF_S 12
420 #define SYN_INTF_M 0xF
421 #define SYN_INTF_V(x) ((x) << SYN_INTF_S)
422 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
424 enum { /* TCP congestion control algorithms */
431 #define CONG_CNTRL_S 14
432 #define CONG_CNTRL_M 0x3
433 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
434 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
437 #define T5_ISS_V(x) ((x) << T5_ISS_S)
438 #define T5_ISS_F T5_ISS_V(1U)
440 struct cpl_pass_accept_rpl {
447 /* option 2 fields */
448 #define RX_COALESCE_VALID_S 11
449 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
450 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
452 #define RX_COALESCE_S 12
453 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
456 #define PACE_V(x) ((x) << PACE_S)
458 #define TX_QUEUE_S 23
459 #define TX_QUEUE_M 0x7
460 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
461 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
463 #define CCTRL_ECN_S 27
464 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
465 #define CCTRL_ECN_F CCTRL_ECN_V(1U)
467 #define TSTAMPS_EN_S 29
468 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
469 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
472 #define SACK_EN_V(x) ((x) << SACK_EN_S)
473 #define SACK_EN_F SACK_EN_V(1U)
475 struct cpl_t5_pass_accept_rpl {
484 struct cpl_act_open_req {
496 #define FILTER_TUPLE_S 24
497 #define FILTER_TUPLE_M 0xFFFFFFFFFF
498 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
499 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
500 struct cpl_t5_act_open_req {
513 struct cpl_t6_act_open_req {
528 struct cpl_act_open_req6 {
542 struct cpl_t5_act_open_req6 {
557 struct cpl_t6_act_open_req6 {
574 struct cpl_act_open_rpl {
579 /* cpl_act_open_rpl.atid_status fields */
580 #define AOPEN_STATUS_S 0
581 #define AOPEN_STATUS_M 0xFF
582 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
584 #define AOPEN_ATID_S 8
585 #define AOPEN_ATID_M 0xFFFFFF
586 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
588 struct cpl_pass_establish {
598 /* cpl_pass_establish.tos_stid fields */
599 #define PASS_OPEN_TID_S 0
600 #define PASS_OPEN_TID_M 0xFFFFFF
601 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
602 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
604 #define PASS_OPEN_TOS_S 24
605 #define PASS_OPEN_TOS_M 0xFF
606 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
607 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
609 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
610 #define TCPOPT_WSCALE_OK_S 5
611 #define TCPOPT_WSCALE_OK_M 0x1
612 #define TCPOPT_WSCALE_OK_G(x) \
613 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
615 #define TCPOPT_SACK_S 6
616 #define TCPOPT_SACK_M 0x1
617 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
619 #define TCPOPT_TSTAMP_S 7
620 #define TCPOPT_TSTAMP_M 0x1
621 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
623 #define TCPOPT_SND_WSCALE_S 8
624 #define TCPOPT_SND_WSCALE_M 0xF
625 #define TCPOPT_SND_WSCALE_G(x) \
626 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
628 #define TCPOPT_MSS_S 12
629 #define TCPOPT_MSS_M 0xF
630 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
632 #define T6_TCP_HDR_LEN_S 8
633 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
634 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
636 #define T6_IP_HDR_LEN_S 14
637 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
638 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
640 #define T6_ETH_HDR_LEN_S 24
641 #define T6_ETH_HDR_LEN_M 0xFF
642 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
643 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
645 struct cpl_act_establish {
662 /* cpl_get_tcb.reply_ctrl fields */
664 #define QUEUENO_V(x) ((x) << QUEUENO_S)
666 #define REPLY_CHAN_S 14
667 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
668 #define REPLY_CHAN_F REPLY_CHAN_V(1U)
670 #define NO_REPLY_S 15
671 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
672 #define NO_REPLY_F NO_REPLY_V(1U)
674 struct cpl_set_tcb_field {
683 /* cpl_set_tcb_field.word_cookie fields */
685 #define TCB_WORD(x) ((x) << TCB_WORD_S)
687 #define TCB_COOKIE_S 5
688 #define TCB_COOKIE_M 0x7
689 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
690 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
692 struct cpl_set_tcb_rpl {
700 struct cpl_close_con_req {
706 struct cpl_close_con_rpl {
714 struct cpl_close_listsvr_req {
721 /* additional cpl_close_listsvr_req.reply_ctrl field */
722 #define LISTSVR_IPV6_S 14
723 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
724 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
726 struct cpl_close_listsvr_rpl {
732 struct cpl_abort_req_rss {
738 struct cpl_abort_req {
747 struct cpl_abort_rpl_rss {
753 struct cpl_abort_rpl {
762 struct cpl_peer_close {
767 struct cpl_tid_release {
773 struct cpl_tx_pkt_core {
782 struct cpl_tx_pkt_core c;
785 #define cpl_tx_pkt_xt cpl_tx_pkt
787 /* cpl_tx_pkt_core.ctrl0 fields */
789 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
792 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
794 #define TXPKT_VF_VLD_S 11
795 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
796 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
798 #define TXPKT_OVLAN_IDX_S 12
799 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
801 #define TXPKT_T5_OVLAN_IDX_S 12
802 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
804 #define TXPKT_INTF_S 16
805 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
807 #define TXPKT_INS_OVLAN_S 21
808 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
809 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
811 #define TXPKT_TSTAMP_S 23
812 #define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S)
813 #define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL)
815 #define TXPKT_OPCODE_S 24
816 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
818 /* cpl_tx_pkt_core.ctrl1 fields */
819 #define TXPKT_CSUM_END_S 12
820 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
822 #define TXPKT_CSUM_START_S 20
823 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
825 #define TXPKT_IPHDR_LEN_S 20
826 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
828 #define TXPKT_CSUM_LOC_S 30
829 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
831 #define TXPKT_ETHHDR_LEN_S 34
832 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
834 #define T6_TXPKT_ETHHDR_LEN_S 32
835 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
837 #define TXPKT_CSUM_TYPE_S 40
838 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
840 #define TXPKT_VLAN_S 44
841 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
843 #define TXPKT_VLAN_VLD_S 60
844 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
845 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
847 #define TXPKT_IPCSUM_DIS_S 62
848 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
849 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
851 #define TXPKT_L4CSUM_DIS_S 63
852 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
853 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
855 struct cpl_tx_pkt_lso_core {
861 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
864 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
865 #define LSO_TCPHDR_LEN_S 0
866 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
868 #define LSO_IPHDR_LEN_S 4
869 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
871 #define LSO_ETHHDR_LEN_S 16
872 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
874 #define LSO_IPV6_S 20
875 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
876 #define LSO_IPV6_F LSO_IPV6_V(1U)
878 #define LSO_LAST_SLICE_S 22
879 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
880 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
882 #define LSO_FIRST_SLICE_S 23
883 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
884 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
886 #define LSO_OPCODE_S 24
887 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
889 #define LSO_T5_XFER_SIZE_S 0
890 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
892 struct cpl_tx_pkt_lso {
894 struct cpl_tx_pkt_lso_core c;
895 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
898 struct cpl_iscsi_hdr {
908 /* cpl_iscsi_hdr.pdu_len_ddp fields */
909 #define ISCSI_PDU_LEN_S 0
910 #define ISCSI_PDU_LEN_M 0x7FFF
911 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
912 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
914 #define ISCSI_DDP_S 15
915 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
916 #define ISCSI_DDP_F ISCSI_DDP_V(1U)
918 struct cpl_rx_data_ddp {
931 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
933 struct cpl_iscsi_data {
943 struct cpl_rx_iscsi_cmp {
955 struct cpl_tx_data_iso {
962 __be32 reserved2_seglen_offset;
963 __be32 datasn_offset;
964 __be32 buffer_offset;
967 /* encapsulated CPL_TX_DATA follows here */
970 /* cpl_tx_data_iso.op_to_scsi fields */
971 #define CPL_TX_DATA_ISO_OP_S 24
972 #define CPL_TX_DATA_ISO_OP_M 0xff
973 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
974 #define CPL_TX_DATA_ISO_OP_G(x) \
975 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
977 #define CPL_TX_DATA_ISO_FIRST_S 23
978 #define CPL_TX_DATA_ISO_FIRST_M 0x1
979 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
980 #define CPL_TX_DATA_ISO_FIRST_G(x) \
981 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
982 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
984 #define CPL_TX_DATA_ISO_LAST_S 22
985 #define CPL_TX_DATA_ISO_LAST_M 0x1
986 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
987 #define CPL_TX_DATA_ISO_LAST_G(x) \
988 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
989 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
991 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
992 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
993 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
994 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
995 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
996 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
998 #define CPL_TX_DATA_ISO_HDRCRC_S 20
999 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1
1000 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
1001 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \
1002 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
1003 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
1005 #define CPL_TX_DATA_ISO_PLDCRC_S 19
1006 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1
1007 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
1008 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \
1009 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
1010 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
1012 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18
1013 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
1014 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
1015 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
1016 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
1017 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1019 #define CPL_TX_DATA_ISO_SCSI_S 16
1020 #define CPL_TX_DATA_ISO_SCSI_M 0x3
1021 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1022 #define CPL_TX_DATA_ISO_SCSI_G(x) \
1023 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1025 /* cpl_tx_data_iso.reserved2_seglen_offset fields */
1026 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1027 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1028 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1029 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1030 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1031 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1032 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1034 struct cpl_rx_data {
1035 union opcode_tid ot;
1040 #if defined(__LITTLE_ENDIAN_BITFIELD)
1056 struct cpl_rx_data_ack {
1058 union opcode_tid ot;
1062 /* cpl_rx_data_ack.ack_seq fields */
1063 #define RX_CREDITS_S 0
1064 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1066 #define RX_FORCE_ACK_S 28
1067 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1068 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1070 #define RX_DACK_MODE_S 29
1071 #define RX_DACK_MODE_M 0x3
1072 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1073 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1075 #define RX_DACK_CHANGE_S 31
1076 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1077 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1080 struct rss_header rsshdr;
1082 #if defined(__LITTLE_ENDIAN_BITFIELD)
1103 #define RX_T6_ETHHDR_LEN_M 0xFF
1104 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1106 #define RXF_PSH_S 20
1107 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1108 #define RXF_PSH_F RXF_PSH_V(1U)
1110 #define RXF_SYN_S 21
1111 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1112 #define RXF_SYN_F RXF_SYN_V(1U)
1114 #define RXF_UDP_S 22
1115 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1116 #define RXF_UDP_F RXF_UDP_V(1U)
1118 #define RXF_TCP_S 23
1119 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1120 #define RXF_TCP_F RXF_TCP_V(1U)
1123 #define RXF_IP_V(x) ((x) << RXF_IP_S)
1124 #define RXF_IP_F RXF_IP_V(1U)
1126 #define RXF_IP6_S 25
1127 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1128 #define RXF_IP6_F RXF_IP6_V(1U)
1130 #define RXF_SYN_COOKIE_S 26
1131 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1132 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1134 #define RXF_FCOE_S 26
1135 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1136 #define RXF_FCOE_F RXF_FCOE_V(1U)
1138 #define RXF_LRO_S 27
1139 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1140 #define RXF_LRO_F RXF_LRO_V(1U)
1142 /* rx_pkt.l2info fields */
1143 #define RX_ETHHDR_LEN_S 0
1144 #define RX_ETHHDR_LEN_M 0x1F
1145 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1146 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1148 #define RX_T5_ETHHDR_LEN_S 0
1149 #define RX_T5_ETHHDR_LEN_M 0x3F
1150 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1151 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1153 #define RX_MACIDX_S 8
1154 #define RX_MACIDX_M 0x1FF
1155 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1156 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1158 #define RXF_SYN_S 21
1159 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1160 #define RXF_SYN_F RXF_SYN_V(1U)
1162 #define RX_CHAN_S 28
1163 #define RX_CHAN_M 0xF
1164 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1165 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1167 /* rx_pkt.hdr_len fields */
1168 #define RX_TCPHDR_LEN_S 0
1169 #define RX_TCPHDR_LEN_M 0x3F
1170 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1171 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1173 #define RX_IPHDR_LEN_S 6
1174 #define RX_IPHDR_LEN_M 0x3FF
1175 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1176 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1178 /* rx_pkt.err_vec fields */
1179 #define RXERR_CSUM_S 13
1180 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1181 #define RXERR_CSUM_F RXERR_CSUM_V(1U)
1183 #define T6_COMPR_RXERR_LEN_S 1
1184 #define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1185 #define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U)
1187 #define T6_COMPR_RXERR_VEC_S 0
1188 #define T6_COMPR_RXERR_VEC_M 0x3F
1189 #define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1190 #define T6_COMPR_RXERR_VEC_G(x) \
1191 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M)
1193 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */
1194 #define T6_COMPR_RXERR_SUM_S 4
1195 #define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S)
1196 #define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U)
1198 struct cpl_trace_pkt {
1201 #if defined(__LITTLE_ENDIAN_BITFIELD)
1219 struct cpl_t5_trace_pkt {
1222 #if defined(__LITTLE_ENDIAN_BITFIELD)
1241 struct cpl_l2t_write_req {
1243 union opcode_tid ot;
1250 /* cpl_l2t_write_req.params fields */
1251 #define L2T_W_INFO_S 2
1252 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1254 #define L2T_W_PORT_S 8
1255 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1257 #define L2T_W_NOREPLY_S 15
1258 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1259 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1261 #define CPL_L2T_VLAN_NONE 0xfff
1263 struct cpl_l2t_write_rpl {
1264 union opcode_tid ot;
1269 struct cpl_rdma_terminate {
1270 union opcode_tid ot;
1275 struct cpl_sge_egr_update {
1281 /* cpl_sge_egr_update.ot fields */
1283 #define EGR_QID_M 0x1FFFF
1284 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1286 /* cpl_fw*.type values */
1288 FW_TYPE_CMD_RPL = 0,
1291 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1295 struct cpl_fw4_pld {
1305 struct cpl_fw6_pld {
1312 struct cpl_fw4_msg {
1320 struct cpl_fw4_ack {
1321 union opcode_tid ot;
1331 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
1332 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
1333 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
1336 struct cpl_fw6_msg {
1344 /* cpl_fw6_msg.type values */
1346 FW6_TYPE_CMD_RPL = 0,
1347 FW6_TYPE_WR_RPL = 1,
1349 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1350 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1353 struct cpl_fw6_msg_ofld_connection_wr_rpl {
1355 __be32 tid; /* or atid in case of active failure */
1361 struct cpl_tx_data {
1362 union opcode_tid ot;
1368 /* cpl_tx_data.flags field */
1369 #define TX_FORCE_S 13
1370 #define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1372 #define T6_TX_FORCE_S 20
1373 #define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S)
1374 #define T6_TX_FORCE_F T6_TX_FORCE_V(1U)
1377 ULP_TX_MEM_READ = 2,
1378 ULP_TX_MEM_WRITE = 3,
1383 ULP_TX_SC_NOOP = 0x80,
1384 ULP_TX_SC_IMM = 0x81,
1385 ULP_TX_SC_DSGL = 0x82,
1386 ULP_TX_SC_ISGL = 0x83
1389 #define ULPTX_CMD_S 24
1390 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1392 struct ulptx_sge_pair {
1401 struct ulptx_sge_pair sge[0];
1404 struct ulptx_idata {
1414 #define ULPTX_CMD_S 24
1415 #define ULPTX_CMD_M 0xFF
1416 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1418 #define ULPTX_NSGE_S 0
1419 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1421 #define ULPTX_MORE_S 23
1422 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1423 #define ULPTX_MORE_F ULPTX_MORE_V(1U)
1425 #define ULP_TXPKT_DEST_S 16
1426 #define ULP_TXPKT_DEST_M 0x3
1427 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1429 #define ULP_TXPKT_FID_S 4
1430 #define ULP_TXPKT_FID_M 0x7ff
1431 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1433 #define ULP_TXPKT_RO_S 3
1434 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1435 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1437 #define ULP_TX_SC_MORE_S 23
1438 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1439 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1444 __be32 len16; /* command length */
1445 __be32 dlen; /* data length in 32-byte units */
1449 #define ULP_MEMIO_LOCK_S 31
1450 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1451 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1453 /* additional ulp_mem_io.cmd fields */
1454 #define ULP_MEMIO_ORDER_S 23
1455 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1456 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1458 #define T5_ULP_MEMIO_IMM_S 23
1459 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1460 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1462 #define T5_ULP_MEMIO_ORDER_S 22
1463 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1464 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1466 #define T5_ULP_MEMIO_FID_S 4
1467 #define T5_ULP_MEMIO_FID_M 0x7ff
1468 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1470 /* ulp_mem_io.lock_addr fields */
1471 #define ULP_MEMIO_ADDR_S 0
1472 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1474 /* ulp_mem_io.dlen fields */
1475 #define ULP_MEMIO_DATA_LEN_S 0
1476 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1478 #define ULPTX_NSGE_S 0
1479 #define ULPTX_NSGE_M 0xFFFF
1480 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1481 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1483 struct ulptx_sc_memrd {
1488 #define ULP_TXPKT_DATAMODIFY_S 23
1489 #define ULP_TXPKT_DATAMODIFY_M 0x1
1490 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1491 #define ULP_TXPKT_DATAMODIFY_G(x) \
1492 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1493 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1495 #define ULP_TXPKT_CHANNELID_S 22
1496 #define ULP_TXPKT_CHANNELID_M 0x1
1497 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1498 #define ULP_TXPKT_CHANNELID_G(x) \
1499 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1500 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1502 #define SCMD_SEQ_NO_CTRL_S 29
1503 #define SCMD_SEQ_NO_CTRL_M 0x3
1504 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1505 #define SCMD_SEQ_NO_CTRL_G(x) \
1506 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1508 /* StsFieldPrsnt- Status field at the end of the TLS PDU */
1509 #define SCMD_STATUS_PRESENT_S 28
1510 #define SCMD_STATUS_PRESENT_M 0x1
1511 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1512 #define SCMD_STATUS_PRESENT_G(x) \
1513 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1514 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1516 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
1519 #define SCMD_PROTO_VERSION_S 24
1520 #define SCMD_PROTO_VERSION_M 0xf
1521 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1522 #define SCMD_PROTO_VERSION_G(x) \
1523 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1525 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
1526 #define SCMD_ENC_DEC_CTRL_S 23
1527 #define SCMD_ENC_DEC_CTRL_M 0x1
1528 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1529 #define SCMD_ENC_DEC_CTRL_G(x) \
1530 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1531 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1533 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
1534 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1535 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1536 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1537 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1538 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1539 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1540 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1542 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
1543 * 4:Generic-AES, 5-15: Reserved.
1545 #define SCMD_CIPH_MODE_S 18
1546 #define SCMD_CIPH_MODE_M 0xf
1547 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1548 #define SCMD_CIPH_MODE_G(x) \
1549 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1551 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
1554 #define SCMD_AUTH_MODE_S 14
1555 #define SCMD_AUTH_MODE_M 0xf
1556 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1557 #define SCMD_AUTH_MODE_G(x) \
1558 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1560 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
1561 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved
1563 #define SCMD_HMAC_CTRL_S 11
1564 #define SCMD_HMAC_CTRL_M 0x7
1565 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1566 #define SCMD_HMAC_CTRL_G(x) \
1567 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1569 /* IvSize - IV size in units of 2 bytes */
1570 #define SCMD_IV_SIZE_S 7
1571 #define SCMD_IV_SIZE_M 0xf
1572 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1573 #define SCMD_IV_SIZE_G(x) \
1574 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1576 /* NumIVs - Number of IVs */
1577 #define SCMD_NUM_IVS_S 0
1578 #define SCMD_NUM_IVS_M 0x7f
1579 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1580 #define SCMD_NUM_IVS_G(x) \
1581 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1583 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber
1584 * (below) are used as Cid (connection id for debug status), these
1585 * bits are padded to zero for forming the 64 bit
1586 * sequence number for TLS
1588 #define SCMD_ENB_DBGID_S 31
1589 #define SCMD_ENB_DBGID_M 0x1
1590 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1591 #define SCMD_ENB_DBGID_G(x) \
1592 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1594 /* IV generation in SW. */
1595 #define SCMD_IV_GEN_CTRL_S 30
1596 #define SCMD_IV_GEN_CTRL_M 0x1
1597 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1598 #define SCMD_IV_GEN_CTRL_G(x) \
1599 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1600 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1603 #define SCMD_MORE_FRAGS_S 20
1604 #define SCMD_MORE_FRAGS_M 0x1
1605 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1606 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1609 #define SCMD_LAST_FRAG_S 19
1610 #define SCMD_LAST_FRAG_M 0x1
1611 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1612 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1615 #define SCMD_TLS_COMPPDU_S 18
1616 #define SCMD_TLS_COMPPDU_M 0x1
1617 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1618 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1620 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/
1621 #define SCMD_KEY_CTX_INLINE_S 17
1622 #define SCMD_KEY_CTX_INLINE_M 0x1
1623 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1624 #define SCMD_KEY_CTX_INLINE_G(x) \
1625 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1626 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1628 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
1629 #define SCMD_TLS_FRAG_ENABLE_S 16
1630 #define SCMD_TLS_FRAG_ENABLE_M 0x1
1631 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1632 #define SCMD_TLS_FRAG_ENABLE_G(x) \
1633 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1634 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1636 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only
1637 * modes, in this case TLS_TX will drop the PDU and only
1638 * send back the MAC bytes.
1640 #define SCMD_MAC_ONLY_S 15
1641 #define SCMD_MAC_ONLY_M 0x1
1642 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1643 #define SCMD_MAC_ONLY_G(x) \
1644 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1645 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1647 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols
1648 * which have complex AAD and IV formations Eg:AES-CCM
1650 #define SCMD_AADIVDROP_S 14
1651 #define SCMD_AADIVDROP_M 0x1
1652 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1653 #define SCMD_AADIVDROP_G(x) \
1654 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1655 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1657 /* HdrLength - Length of all headers excluding TLS header
1658 * present before start of crypto PDU/payload.
1660 #define SCMD_HDR_LEN_S 0
1661 #define SCMD_HDR_LEN_M 0x3fff
1662 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1663 #define SCMD_HDR_LEN_G(x) \
1664 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1666 struct cpl_tx_sec_pdu {
1667 __be32 op_ivinsrtofst;
1669 __be32 aadstart_cipherstop_hi;
1670 __be32 cipherstop_lo_authinsert;
1671 __be32 seqno_numivs;
1672 __be32 ivgen_hdrlen;
1676 #define CPL_TX_SEC_PDU_OPCODE_S 24
1677 #define CPL_TX_SEC_PDU_OPCODE_M 0xff
1678 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1679 #define CPL_TX_SEC_PDU_OPCODE_G(x) \
1680 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1683 #define CPL_TX_SEC_PDU_RXCHID_S 22
1684 #define CPL_TX_SEC_PDU_RXCHID_M 0x1
1685 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1686 #define CPL_TX_SEC_PDU_RXCHID_G(x) \
1687 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1688 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1691 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1692 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1693 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1694 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1695 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1696 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1698 /* Loopback bit in cpl_tx_sec_pdu */
1699 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1700 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1701 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1702 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1703 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1704 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1706 /* Length of cpl header encapsulated */
1707 #define CPL_TX_SEC_PDU_CPLLEN_S 16
1708 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1709 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1710 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1711 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1714 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1715 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1716 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1717 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1718 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1719 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1721 /* IvInsrtOffset: Insertion location for IV */
1722 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1723 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1724 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1725 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1726 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1727 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1729 /* AadStartOffset: Offset in bytes for AAD start from
1730 * the first byte following the pkt headers (0-255 bytes)
1732 #define CPL_TX_SEC_PDU_AADSTART_S 24
1733 #define CPL_TX_SEC_PDU_AADSTART_M 0xff
1734 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
1735 #define CPL_TX_SEC_PDU_AADSTART_G(x) \
1736 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
1737 CPL_TX_SEC_PDU_AADSTART_M)
1739 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following
1740 * the pkt headers (0-511 bytes)
1742 #define CPL_TX_SEC_PDU_AADSTOP_S 15
1743 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
1744 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
1745 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \
1746 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
1748 /* CipherStartOffset: offset in bytes for encryption/decryption start from the
1749 * first byte following the pkt headers (0-1023 bytes)
1751 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5
1752 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
1753 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
1754 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
1755 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
1756 CPL_TX_SEC_PDU_CIPHERSTART_M)
1758 /* CipherStopOffset: offset in bytes for encryption/decryption end
1759 * from end of the payload of this command (0-511 bytes)
1761 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
1762 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
1763 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
1764 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
1765 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
1766 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
1767 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
1769 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
1770 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
1771 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
1772 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
1773 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
1774 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
1775 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
1777 /* AuthStartOffset: offset in bytes for authentication start from
1778 * the first byte following the pkt headers (0-1023)
1780 #define CPL_TX_SEC_PDU_AUTHSTART_S 18
1781 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
1782 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
1783 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
1784 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
1785 CPL_TX_SEC_PDU_AUTHSTART_M)
1787 /* AuthStopOffset: offset in bytes for authentication
1788 * end from end of the payload of this command (0-511 Bytes)
1790 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9
1791 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
1792 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
1793 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
1794 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
1795 CPL_TX_SEC_PDU_AUTHSTOP_M)
1797 /* AuthInsrtOffset: offset in bytes for authentication insertion
1798 * from end of the payload of this command (0-511 bytes)
1800 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0
1801 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
1802 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
1803 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
1804 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
1805 CPL_TX_SEC_PDU_AUTHINSERT_M)
1807 struct cpl_rx_phys_dsgl {
1809 __be32 pcirlxorder_to_noofsgentr;
1810 struct rss_header rss_hdr_int;
1813 #define CPL_RX_PHYS_DSGL_OPCODE_S 24
1814 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
1815 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
1816 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
1817 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
1819 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23
1820 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
1821 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
1822 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
1823 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
1824 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
1826 #define CPL_RX_PHYS_DSGL_RSVD1_S 20
1827 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
1828 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
1829 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
1830 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
1831 CPL_RX_PHYS_DSGL_RSVD1_M)
1833 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
1834 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
1835 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
1836 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
1837 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
1838 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
1839 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
1840 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
1842 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
1843 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
1844 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
1845 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
1846 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
1847 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
1848 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
1850 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
1852 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
1853 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
1854 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
1855 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
1856 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
1857 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
1858 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
1859 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
1861 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
1862 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
1863 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
1864 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
1865 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
1866 CPL_RX_PHYS_DSGL_PCITPHNT_M)
1868 #define CPL_RX_PHYS_DSGL_DCAID_S 16
1869 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
1870 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
1871 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \
1872 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
1873 CPL_RX_PHYS_DSGL_DCAID_M)
1875 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
1876 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
1877 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
1878 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
1879 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
1880 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
1881 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
1883 struct cpl_rx_mps_pkt {
1885 __be32 r1_lo_length;
1888 #define CPL_RX_MPS_PKT_OP_S 24
1889 #define CPL_RX_MPS_PKT_OP_M 0xff
1890 #define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S)
1891 #define CPL_RX_MPS_PKT_OP_G(x) \
1892 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M)
1894 #define CPL_RX_MPS_PKT_TYPE_S 20
1895 #define CPL_RX_MPS_PKT_TYPE_M 0xf
1896 #define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S)
1897 #define CPL_RX_MPS_PKT_TYPE_G(x) \
1898 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M)
1901 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0,
1902 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1,
1903 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2,
1904 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3
1906 #endif /* __T4_MSG_H */