drivers/net/ethernet/freescale/dpaa/dpaa_eth.c

   1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc.
   2  *
   3  * Redistribution and use in source and binary forms, with or without
   4  * modification, are permitted provided that the following conditions are met:
   5  *     * Redistributions of source code must retain the above copyright
   6  *       notice, this list of conditions and the following disclaimer.
   7  *     * Redistributions in binary form must reproduce the above copyright
   8  *       notice, this list of conditions and the following disclaimer in the
   9  *       documentation and/or other materials provided with the distribution.
  10  *     * Neither the name of Freescale Semiconductor nor the
  11  *       names of its contributors may be used to endorse or promote products
  12  *       derived from this software without specific prior written permission.
  13  *
  14  * ALTERNATIVELY, this software may be distributed under the terms of the
  15  * GNU General Public License ("GPL") as published by the Free Software
  16  * Foundation, either version 2 of that License or (at your option) any
  17  * later version.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  20  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32
  33 #include <linux/init.h>
  34 #include <linux/module.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/of_mdio.h>
  37 #include <linux/of_net.h>
  38 #include <linux/io.h>
  39 #include <linux/if_arp.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/icmp.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/udp.h>
  45 #include <linux/tcp.h>
  46 #include <linux/net.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/if_ether.h>
  50 #include <linux/highmem.h>
  51 #include <linux/percpu.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/sort.h>
  54 #include <soc/fsl/bman.h>
  55 #include <soc/fsl/qman.h>
  56
  57 #include "fman.h"
  58 #include "fman_port.h"
  59 #include "mac.h"
  60 #include "dpaa_eth.h"
  61
  62 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
  63  * using trace events only need to #include <trace/events/sched.h>
  64  */
  65 #define CREATE_TRACE_POINTS
  66 #include "dpaa_eth_trace.h"
  67
  68 static int debug = -1;
  69 module_param(debug, int, 0444);
  70 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
  71
  72 static u16 tx_timeout = 1000;
  73 module_param(tx_timeout, ushort, 0444);
  74 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
  75
  76 #define FM_FD_STAT_RX_ERRORS                                            \
  77         (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL     | \
  78          FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
  79          FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME     | \
  80          FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
  81          FM_FD_ERR_PRS_HDR_ERR)
  82
  83 #define FM_FD_STAT_TX_ERRORS \
  84         (FM_FD_ERR_UNSUPPORTED_FORMAT | \
  85          FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
  86
  87 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
  88                           NETIF_MSG_LINK | NETIF_MSG_IFUP | \
  89                           NETIF_MSG_IFDOWN)
  90
  91 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000
  92 /* Ingress congestion threshold on FMan ports
  93  * The size in bytes of the ingress tail-drop threshold on FMan ports.
  94  * Traffic piling up above this value will be rejected by QMan and discarded
  95  * by FMan.
  96  */
  97
  98 /* Size in bytes of the FQ taildrop threshold */
  99 #define DPAA_FQ_TD 0x200000
 100
 101 #define DPAA_CS_THRESHOLD_1G 0x06000000
 102 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
 103  * The size in bytes of the egress Congestion State notification threshold on
 104  * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
 105  * tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
 106  * and the larger the frame size, the more acute the problem.
 107  * So we have to find a balance between these factors:
 108  * - avoiding the device staying congested for a prolonged time (risking
 109  *   the netdev watchdog to fire - see also the tx_timeout module param);
 110  * - affecting performance of protocols such as TCP, which otherwise
 111  *   behave well under the congestion notification mechanism;
 112  * - preventing the Tx cores from tightly-looping (as if the congestion
 113  *   threshold was too low to be effective);
 114  * - running out of memory if the CS threshold is set too high.
 115  */
 116
 117 #define DPAA_CS_THRESHOLD_10G 0x10000000
 118 /* The size in bytes of the egress Congestion State notification threshold on
 119  * 10G ports, range 0x1000 .. 0x10000000
 120  */
 121
 122 /* Largest value that the FQD's OAL field can hold */
 123 #define FSL_QMAN_MAX_OAL        127
 124
 125 /* Default alignment for start of data in an Rx FD */
 126 #define DPAA_FD_DATA_ALIGNMENT  16
 127
 128 /* The DPAA requires 256 bytes reserved and mapped for the SGT */
 129 #define DPAA_SGT_SIZE 256
 130
 131 /* Values for the L3R field of the FM Parse Results
 132  */
 133 /* L3 Type field: First IP Present IPv4 */
 134 #define FM_L3_PARSE_RESULT_IPV4 0x8000
 135 /* L3 Type field: First IP Present IPv6 */
 136 #define FM_L3_PARSE_RESULT_IPV6 0x4000
 137 /* Values for the L4R field of the FM Parse Results */
 138 /* L4 Type field: UDP */
 139 #define FM_L4_PARSE_RESULT_UDP  0x40
 140 /* L4 Type field: TCP */
 141 #define FM_L4_PARSE_RESULT_TCP  0x20
 142
 143 /* FD status field indicating whether the FM Parser has attempted to validate
 144  * the L4 csum of the frame.
 145  * Note that having this bit set doesn't necessarily imply that the checksum
 146  * is valid. One would have to check the parse results to find that out.
 147  */
 148 #define FM_FD_STAT_L4CV         0x00000004
 149
 150 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
 151 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
 152
 153 #define FSL_DPAA_BPID_INV               0xff
 154 #define FSL_DPAA_ETH_MAX_BUF_COUNT      128
 155 #define FSL_DPAA_ETH_REFILL_THRESHOLD   80
 156
 157 #define DPAA_TX_PRIV_DATA_SIZE  16
 158 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
 159 #define DPAA_TIME_STAMP_SIZE 8
 160 #define DPAA_HASH_RESULTS_SIZE 8
 161 #define DPAA_RX_PRIV_DATA_SIZE  (u16)(DPAA_TX_PRIV_DATA_SIZE + \
 162                                         dpaa_rx_extra_headroom)
 163
 164 #define DPAA_ETH_PCD_RXQ_NUM    128
 165
 166 #define DPAA_ENQUEUE_RETRIES    100000
 167
 168 enum port_type {RX, TX};
 169
 170 struct fm_port_fqs {
 171         struct dpaa_fq *tx_defq;
 172         struct dpaa_fq *tx_errq;
 173         struct dpaa_fq *rx_defq;
 174         struct dpaa_fq *rx_errq;
 175         struct dpaa_fq *rx_pcdq;
 176 };
 177
 178 /* All the dpa bps in use at any moment */
 179 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
 180
 181 /* The raw buffer size must be cacheline aligned */
 182 #define DPAA_BP_RAW_SIZE 4096
 183 /* When using more than one buffer pool, the raw sizes are as follows:
 184  * 1 bp: 4KB
 185  * 2 bp: 2KB, 4KB
 186  * 3 bp: 1KB, 2KB, 4KB
 187  * 4 bp: 1KB, 2KB, 4KB, 8KB
 188  */
 189 static inline size_t bpool_buffer_raw_size(u8 index, u8 cnt)
 190 {
 191         size_t res = DPAA_BP_RAW_SIZE / 4;
 192         u8 i;
 193
 194         for (i = (cnt < 3) ? cnt : 3; i < 3 + index; i++)
 195                 res *= 2;
 196         return res;
 197 }
 198
 199 /* FMan-DMA requires 16-byte alignment for Rx buffers, but SKB_DATA_ALIGN is
 200  * even stronger (SMP_CACHE_BYTES-aligned), so we just get away with that,
 201  * via SKB_WITH_OVERHEAD(). We can't rely on netdev_alloc_frag() giving us
 202  * half-page-aligned buffers, so we reserve some more space for start-of-buffer
 203  * alignment.
 204  */
 205 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD((raw_size) - SMP_CACHE_BYTES)
 206
 207 static int dpaa_max_frm;
 208
 209 static int dpaa_rx_extra_headroom;
 210
 211 #define dpaa_get_max_mtu()      \
 212         (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
 213
 214 static int dpaa_netdev_init(struct net_device *net_dev,
 215                             const struct net_device_ops *dpaa_ops,
 216                             u16 tx_timeout)
 217 {
 218         struct dpaa_priv *priv = netdev_priv(net_dev);
 219         struct device *dev = net_dev->dev.parent;
 220         struct dpaa_percpu_priv *percpu_priv;
 221         const u8 *mac_addr;
 222         int i, err;
 223
 224         /* Although we access another CPU's private data here
 225          * we do it at initialization so it is safe
 226          */
 227         for_each_possible_cpu(i) {
 228                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
 229                 percpu_priv->net_dev = net_dev;
 230         }
 231
 232         net_dev->netdev_ops = dpaa_ops;
 233         mac_addr = priv->mac_dev->addr;
 234
 235         net_dev->mem_start = priv->mac_dev->res->start;
 236         net_dev->mem_end = priv->mac_dev->res->end;
 237
 238         net_dev->min_mtu = ETH_MIN_MTU;
 239         net_dev->max_mtu = dpaa_get_max_mtu();
 240
 241         net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 242                                  NETIF_F_LLTX | NETIF_F_RXHASH);
 243
 244         net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
 245         /* The kernels enables GSO automatically, if we declare NETIF_F_SG.
 246          * For conformity, we'll still declare GSO explicitly.
 247          */
 248         net_dev->features |= NETIF_F_GSO;
 249         net_dev->features |= NETIF_F_RXCSUM;
 250
 251         net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
 252         /* we do not want shared skbs on TX */
 253         net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
 254
 255         net_dev->features |= net_dev->hw_features;
 256         net_dev->vlan_features = net_dev->features;
 257
 258         memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
 259         memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
 260
 261         net_dev->ethtool_ops = &dpaa_ethtool_ops;
 262
 263         net_dev->needed_headroom = priv->tx_headroom;
 264         net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
 265
 266         /* start without the RUNNING flag, phylib controls it later */
 267         netif_carrier_off(net_dev);
 268
 269         err = register_netdev(net_dev);
 270         if (err < 0) {
 271                 dev_err(dev, "register_netdev() = %d\n", err);
 272                 return err;
 273         }
 274
 275         return 0;
 276 }
 277
 278 static int dpaa_stop(struct net_device *net_dev)
 279 {
 280         struct mac_device *mac_dev;
 281         struct dpaa_priv *priv;
 282         int i, err, error;
 283
 284         priv = netdev_priv(net_dev);
 285         mac_dev = priv->mac_dev;
 286
 287         netif_tx_stop_all_queues(net_dev);
 288         /* Allow the Fman (Tx) port to process in-flight frames before we
 289          * try switching it off.
 290          */
 291         usleep_range(5000, 10000);
 292
 293         err = mac_dev->stop(mac_dev);
 294         if (err < 0)
 295                 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n",
 296                           err);
 297
 298         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
 299                 error = fman_port_disable(mac_dev->port[i]);
 300                 if (error)
 301                         err = error;
 302         }
 303
 304         if (net_dev->phydev)
 305                 phy_disconnect(net_dev->phydev);
 306         net_dev->phydev = NULL;
 307
 308         return err;
 309 }
 310
 311 static void dpaa_tx_timeout(struct net_device *net_dev)
 312 {
 313         struct dpaa_percpu_priv *percpu_priv;
 314         const struct dpaa_priv  *priv;
 315
 316         priv = netdev_priv(net_dev);
 317         percpu_priv = this_cpu_ptr(priv->percpu_priv);
 318
 319         netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
 320                    jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
 321
 322         percpu_priv->stats.tx_errors++;
 323 }
 324
 325 /* Calculates the statistics for the given device by adding the statistics
 326  * collected by each CPU.
 327  */
 328 static void dpaa_get_stats64(struct net_device *net_dev,
 329                              struct rtnl_link_stats64 *s)
 330 {
 331         int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
 332         struct dpaa_priv *priv = netdev_priv(net_dev);
 333         struct dpaa_percpu_priv *percpu_priv;
 334         u64 *netstats = (u64 *)s;
 335         u64 *cpustats;
 336         int i, j;
 337
 338         for_each_possible_cpu(i) {
 339                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
 340
 341                 cpustats = (u64 *)&percpu_priv->stats;
 342
 343                 /* add stats from all CPUs */
 344                 for (j = 0; j < numstats; j++)
 345                         netstats[j] += cpustats[j];
 346         }
 347 }
 348
 349 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
 350                          void *type_data)
 351 {
 352         struct dpaa_priv *priv = netdev_priv(net_dev);
 353         struct tc_mqprio_qopt *mqprio = type_data;
 354         u8 num_tc;
 355         int i;
 356
 357         if (type != TC_SETUP_MQPRIO)
 358                 return -EOPNOTSUPP;
 359
 360         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
 361         num_tc = mqprio->num_tc;
 362
 363         if (num_tc == priv->num_tc)
 364                 return 0;
 365
 366         if (!num_tc) {
 367                 netdev_reset_tc(net_dev);
 368                 goto out;
 369         }
 370
 371         if (num_tc > DPAA_TC_NUM) {
 372                 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
 373                            DPAA_TC_NUM);
 374                 return -EINVAL;
 375         }
 376
 377         netdev_set_num_tc(net_dev, num_tc);
 378
 379         for (i = 0; i < num_tc; i++)
 380                 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM,
 381                                     i * DPAA_TC_TXQ_NUM);
 382
 383 out:
 384         priv->num_tc = num_tc ? : 1;
 385         netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
 386         return 0;
 387 }
 388
 389 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
 390 {
 391         struct platform_device *of_dev;
 392         struct dpaa_eth_data *eth_data;
 393         struct device *dpaa_dev, *dev;
 394         struct device_node *mac_node;
 395         struct mac_device *mac_dev;
 396
 397         dpaa_dev = &pdev->dev;
 398         eth_data = dpaa_dev->platform_data;
 399         if (!eth_data)
 400                 return ERR_PTR(-ENODEV);
 401
 402         mac_node = eth_data->mac_node;
 403
 404         of_dev = of_find_device_by_node(mac_node);
 405         if (!of_dev) {
 406                 dev_err(dpaa_dev, "of_find_device_by_node(%pOF) failed\n",
 407                         mac_node);
 408                 of_node_put(mac_node);
 409                 return ERR_PTR(-EINVAL);
 410         }
 411         of_node_put(mac_node);
 412
 413         dev = &of_dev->dev;
 414
 415         mac_dev = dev_get_drvdata(dev);
 416         if (!mac_dev) {
 417                 dev_err(dpaa_dev, "dev_get_drvdata(%s) failed\n",
 418                         dev_name(dev));
 419                 return ERR_PTR(-EINVAL);
 420         }
 421
 422         return mac_dev;
 423 }
 424
 425 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
 426 {
 427         const struct dpaa_priv *priv;
 428         struct mac_device *mac_dev;
 429         struct sockaddr old_addr;
 430         int err;
 431
 432         priv = netdev_priv(net_dev);
 433
 434         memcpy(old_addr.sa_data, net_dev->dev_addr,  ETH_ALEN);
 435
 436         err = eth_mac_addr(net_dev, addr);
 437         if (err < 0) {
 438                 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
 439                 return err;
 440         }
 441
 442         mac_dev = priv->mac_dev;
 443
 444         err = mac_dev->change_addr(mac_dev->fman_mac,
 445                                    (enet_addr_t *)net_dev->dev_addr);
 446         if (err < 0) {
 447                 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
 448                           err);
 449                 /* reverting to previous address */
 450                 eth_mac_addr(net_dev, &old_addr);
 451
 452                 return err;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static void dpaa_set_rx_mode(struct net_device *net_dev)
 459 {
 460         const struct dpaa_priv  *priv;
 461         int err;
 462
 463         priv = netdev_priv(net_dev);
 464
 465         if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
 466                 priv->mac_dev->promisc = !priv->mac_dev->promisc;
 467                 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
 468                                                  priv->mac_dev->promisc);
 469                 if (err < 0)
 470                         netif_err(priv, drv, net_dev,
 471                                   "mac_dev->set_promisc() = %d\n",
 472                                   err);
 473         }
 474
 475         err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
 476         if (err < 0)
 477                 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
 478                           err);
 479 }
 480
 481 static struct dpaa_bp *dpaa_bpid2pool(int bpid)
 482 {
 483         if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
 484                 return NULL;
 485
 486         return dpaa_bp_array[bpid];
 487 }
 488
 489 /* checks if this bpool is already allocated */
 490 static bool dpaa_bpid2pool_use(int bpid)
 491 {
 492         if (dpaa_bpid2pool(bpid)) {
 493                 atomic_inc(&dpaa_bp_array[bpid]->refs);
 494                 return true;
 495         }
 496
 497         return false;
 498 }
 499
 500 /* called only once per bpid by dpaa_bp_alloc_pool() */
 501 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
 502 {
 503         dpaa_bp_array[bpid] = dpaa_bp;
 504         atomic_set(&dpaa_bp->refs, 1);
 505 }
 506
 507 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
 508 {
 509         int err;
 510
 511         if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
 512                 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
 513                        __func__);
 514                 return -EINVAL;
 515         }
 516
 517         /* If the pool is already specified, we only create one per bpid */
 518         if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
 519             dpaa_bpid2pool_use(dpaa_bp->bpid))
 520                 return 0;
 521
 522         if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
 523                 dpaa_bp->pool = bman_new_pool();
 524                 if (!dpaa_bp->pool) {
 525                         pr_err("%s: bman_new_pool() failed\n",
 526                                __func__);
 527                         return -ENODEV;
 528                 }
 529
 530                 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
 531         }
 532
 533         if (dpaa_bp->seed_cb) {
 534                 err = dpaa_bp->seed_cb(dpaa_bp);
 535                 if (err)
 536                         goto pool_seed_failed;
 537         }
 538
 539         dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
 540
 541         return 0;
 542
 543 pool_seed_failed:
 544         pr_err("%s: pool seeding failed\n", __func__);
 545         bman_free_pool(dpaa_bp->pool);
 546
 547         return err;
 548 }
 549
 550 /* remove and free all the buffers from the given buffer pool */
 551 static void dpaa_bp_drain(struct dpaa_bp *bp)
 552 {
 553         u8 num = 8;
 554         int ret;
 555
 556         do {
 557                 struct bm_buffer bmb[8];
 558                 int i;
 559
 560                 ret = bman_acquire(bp->pool, bmb, num);
 561                 if (ret < 0) {
 562                         if (num == 8) {
 563                                 /* we have less than 8 buffers left;
 564                                  * drain them one by one
 565                                  */
 566                                 num = 1;
 567                                 ret = 1;
 568                                 continue;
 569                         } else {
 570                                 /* Pool is fully drained */
 571                                 break;
 572                         }
 573                 }
 574
 575                 if (bp->free_buf_cb)
 576                         for (i = 0; i < num; i++)
 577                                 bp->free_buf_cb(bp, &bmb[i]);
 578         } while (ret > 0);
 579 }
 580
 581 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
 582 {
 583         struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
 584
 585         /* the mapping between bpid and dpaa_bp is done very late in the
 586          * allocation procedure; if something failed before the mapping, the bp
 587          * was not configured, therefore we don't need the below instructions
 588          */
 589         if (!bp)
 590                 return;
 591
 592         if (!atomic_dec_and_test(&bp->refs))
 593                 return;
 594
 595         if (bp->free_buf_cb)
 596                 dpaa_bp_drain(bp);
 597
 598         dpaa_bp_array[bp->bpid] = NULL;
 599         bman_free_pool(bp->pool);
 600 }
 601
 602 static void dpaa_bps_free(struct dpaa_priv *priv)
 603 {
 604         int i;
 605
 606         for (i = 0; i < DPAA_BPS_NUM; i++)
 607                 dpaa_bp_free(priv->dpaa_bps[i]);
 608 }
 609
 610 /* Use multiple WQs for FQ assignment:
 611  *      - Tx Confirmation queues go to WQ1.
 612  *      - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
 613  *        to be scheduled, in case there are many more FQs in WQ6).
 614  *      - Rx Default goes to WQ6.
 615  *      - Tx queues go to different WQs depending on their priority. Equal
 616  *        chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
 617  *        WQ0 (highest priority).
 618  * This ensures that Tx-confirmed buffers are timely released. In particular,
 619  * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
 620  * are greatly outnumbered by other FQs in the system, while
 621  * dequeue scheduling is round-robin.
 622  */
 623 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
 624 {
 625         switch (fq->fq_type) {
 626         case FQ_TYPE_TX_CONFIRM:
 627         case FQ_TYPE_TX_CONF_MQ:
 628                 fq->wq = 1;
 629                 break;
 630         case FQ_TYPE_RX_ERROR:
 631         case FQ_TYPE_TX_ERROR:
 632                 fq->wq = 5;
 633                 break;
 634         case FQ_TYPE_RX_DEFAULT:
 635         case FQ_TYPE_RX_PCD:
 636                 fq->wq = 6;
 637                 break;
 638         case FQ_TYPE_TX:
 639                 switch (idx / DPAA_TC_TXQ_NUM) {
 640                 case 0:
 641                         /* Low priority (best effort) */
 642                         fq->wq = 6;
 643                         break;
 644                 case 1:
 645                         /* Medium priority */
 646                         fq->wq = 2;
 647                         break;
 648                 case 2:
 649                         /* High priority */
 650                         fq->wq = 1;
 651                         break;
 652                 case 3:
 653                         /* Very high priority */
 654                         fq->wq = 0;
 655                         break;
 656                 default:
 657                         WARN(1, "Too many TX FQs: more than %d!\n",
 658                              DPAA_ETH_TXQ_NUM);
 659                 }
 660                 break;
 661         default:
 662                 WARN(1, "Invalid FQ type %d for FQID %d!\n",
 663                      fq->fq_type, fq->fqid);
 664         }
 665 }
 666
 667 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
 668                                      u32 start, u32 count,
 669                                      struct list_head *list,
 670                                      enum dpaa_fq_type fq_type)
 671 {
 672         struct dpaa_fq *dpaa_fq;
 673         int i;
 674
 675         dpaa_fq = devm_kzalloc(dev, sizeof(*dpaa_fq) * count,
 676                                GFP_KERNEL);
 677         if (!dpaa_fq)
 678                 return NULL;
 679
 680         for (i = 0; i < count; i++) {
 681                 dpaa_fq[i].fq_type = fq_type;
 682                 dpaa_fq[i].fqid = start ? start + i : 0;
 683                 list_add_tail(&dpaa_fq[i].list, list);
 684         }
 685
 686         for (i = 0; i < count; i++)
 687                 dpaa_assign_wq(dpaa_fq + i, i);
 688
 689         return dpaa_fq;
 690 }
 691
 692 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
 693                               struct fm_port_fqs *port_fqs)
 694 {
 695         struct dpaa_fq *dpaa_fq;
 696         u32 fq_base, fq_base_aligned, i;
 697
 698         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
 699         if (!dpaa_fq)
 700                 goto fq_alloc_failed;
 701
 702         port_fqs->rx_errq = &dpaa_fq[0];
 703
 704         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
 705         if (!dpaa_fq)
 706                 goto fq_alloc_failed;
 707
 708         port_fqs->rx_defq = &dpaa_fq[0];
 709
 710         /* the PCD FQIDs range needs to be aligned for correct operation */
 711         if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
 712                 goto fq_alloc_failed;
 713
 714         fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
 715
 716         for (i = fq_base; i < fq_base_aligned; i++)
 717                 qman_release_fqid(i);
 718
 719         for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
 720              i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
 721                 qman_release_fqid(i);
 722
 723         dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
 724                                 list, FQ_TYPE_RX_PCD);
 725         if (!dpaa_fq)
 726                 goto fq_alloc_failed;
 727
 728         port_fqs->rx_pcdq = &dpaa_fq[0];
 729
 730         if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
 731                 goto fq_alloc_failed;
 732
 733         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
 734         if (!dpaa_fq)
 735                 goto fq_alloc_failed;
 736
 737         port_fqs->tx_errq = &dpaa_fq[0];
 738
 739         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
 740         if (!dpaa_fq)
 741                 goto fq_alloc_failed;
 742
 743         port_fqs->tx_defq = &dpaa_fq[0];
 744
 745         if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX))
 746                 goto fq_alloc_failed;
 747
 748         return 0;
 749
 750 fq_alloc_failed:
 751         dev_err(dev, "dpaa_fq_alloc() failed\n");
 752         return -ENOMEM;
 753 }
 754
 755 static u32 rx_pool_channel;
 756 static DEFINE_SPINLOCK(rx_pool_channel_init);
 757
 758 static int dpaa_get_channel(void)
 759 {
 760         spin_lock(&rx_pool_channel_init);
 761         if (!rx_pool_channel) {
 762                 u32 pool;
 763                 int ret;
 764
 765                 ret = qman_alloc_pool(&pool);
 766
 767                 if (!ret)
 768                         rx_pool_channel = pool;
 769         }
 770         spin_unlock(&rx_pool_channel_init);
 771         if (!rx_pool_channel)
 772                 return -ENOMEM;
 773         return rx_pool_channel;
 774 }
 775
 776 static void dpaa_release_channel(void)
 777 {
 778         qman_release_pool(rx_pool_channel);
 779 }
 780
 781 static void dpaa_eth_add_channel(u16 channel)
 782 {
 783         u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
 784         const cpumask_t *cpus = qman_affine_cpus();
 785         struct qman_portal *portal;
 786         int cpu;
 787
 788         for_each_cpu(cpu, cpus) {
 789                 portal = qman_get_affine_portal(cpu);
 790                 qman_p_static_dequeue_add(portal, pool);
 791         }
 792 }
 793
 794 /* Congestion group state change notification callback.
 795  * Stops the device's egress queues while they are congested and
 796  * wakes them upon exiting congested state.
 797  * Also updates some CGR-related stats.
 798  */
 799 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
 800                            int congested)
 801 {
 802         struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
 803                 struct dpaa_priv, cgr_data.cgr);
 804
 805         if (congested) {
 806                 priv->cgr_data.congestion_start_jiffies = jiffies;
 807                 netif_tx_stop_all_queues(priv->net_dev);
 808                 priv->cgr_data.cgr_congested_count++;
 809         } else {
 810                 priv->cgr_data.congested_jiffies +=
 811                         (jiffies - priv->cgr_data.congestion_start_jiffies);
 812                 netif_tx_wake_all_queues(priv->net_dev);
 813         }
 814 }
 815
 816 static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
 817 {
 818         struct qm_mcc_initcgr initcgr;
 819         u32 cs_th;
 820         int err;
 821
 822         err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
 823         if (err < 0) {
 824                 if (netif_msg_drv(priv))
 825                         pr_err("%s: Error %d allocating CGR ID\n",
 826                                __func__, err);
 827                 goto out_error;
 828         }
 829         priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
 830
 831         /* Enable Congestion State Change Notifications and CS taildrop */
 832         memset(&initcgr, 0, sizeof(initcgr));
 833         initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
 834         initcgr.cgr.cscn_en = QM_CGR_EN;
 835
 836         /* Set different thresholds based on the MAC speed.
 837          * This may turn suboptimal if the MAC is reconfigured at a speed
 838          * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link.
 839          * In such cases, we ought to reconfigure the threshold, too.
 840          */
 841         if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
 842                 cs_th = DPAA_CS_THRESHOLD_10G;
 843         else
 844                 cs_th = DPAA_CS_THRESHOLD_1G;
 845         qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
 846
 847         initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
 848         initcgr.cgr.cstd_en = QM_CGR_EN;
 849
 850         err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
 851                               &initcgr);
 852         if (err < 0) {
 853                 if (netif_msg_drv(priv))
 854                         pr_err("%s: Error %d creating CGR with ID %d\n",
 855                                __func__, err, priv->cgr_data.cgr.cgrid);
 856                 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
 857                 goto out_error;
 858         }
 859         if (netif_msg_drv(priv))
 860                 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
 861                          priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
 862                          priv->cgr_data.cgr.chan);
 863
 864 out_error:
 865         return err;
 866 }
 867
 868 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
 869                                       struct dpaa_fq *fq,
 870                                       const struct qman_fq *template)
 871 {
 872         fq->fq_base = *template;
 873         fq->net_dev = priv->net_dev;
 874
 875         fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
 876         fq->channel = priv->channel;
 877 }
 878
 879 static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
 880                                      struct dpaa_fq *fq,
 881                                      struct fman_port *port,
 882                                      const struct qman_fq *template)
 883 {
 884         fq->fq_base = *template;
 885         fq->net_dev = priv->net_dev;
 886
 887         if (port) {
 888                 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
 889                 fq->channel = (u16)fman_port_get_qman_channel_id(port);
 890         } else {
 891                 fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
 892         }
 893 }
 894
 895 static void dpaa_fq_setup(struct dpaa_priv *priv,
 896                           const struct dpaa_fq_cbs *fq_cbs,
 897                           struct fman_port *tx_port)
 898 {
 899         int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
 900         const cpumask_t *affine_cpus = qman_affine_cpus();
 901         u16 channels[NR_CPUS];
 902         struct dpaa_fq *fq;
 903
 904         for_each_cpu(cpu, affine_cpus)
 905                 channels[num_portals++] = qman_affine_channel(cpu);
 906
 907         if (num_portals == 0)
 908                 dev_err(priv->net_dev->dev.parent,
 909                         "No Qman software (affine) channels found");
 910
 911         /* Initialize each FQ in the list */
 912         list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
 913                 switch (fq->fq_type) {
 914                 case FQ_TYPE_RX_DEFAULT:
 915                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
 916                         break;
 917                 case FQ_TYPE_RX_ERROR:
 918                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
 919                         break;
 920                 case FQ_TYPE_RX_PCD:
 921                         if (!num_portals)
 922                                 continue;
 923                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
 924                         fq->channel = channels[portal_cnt++ % num_portals];
 925                         break;
 926                 case FQ_TYPE_TX:
 927                         dpaa_setup_egress(priv, fq, tx_port,
 928                                           &fq_cbs->egress_ern);
 929                         /* If we have more Tx queues than the number of cores,
 930                          * just ignore the extra ones.
 931                          */
 932                         if (egress_cnt < DPAA_ETH_TXQ_NUM)
 933                                 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
 934                         break;
 935                 case FQ_TYPE_TX_CONF_MQ:
 936                         priv->conf_fqs[conf_cnt++] = &fq->fq_base;
 937                         /* fall through */
 938                 case FQ_TYPE_TX_CONFIRM:
 939                         dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
 940                         break;
 941                 case FQ_TYPE_TX_ERROR:
 942                         dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
 943                         break;
 944                 default:
 945                         dev_warn(priv->net_dev->dev.parent,
 946                                  "Unknown FQ type detected!\n");
 947                         break;
 948                 }
 949         }
 950
 951          /* Make sure all CPUs receive a corresponding Tx queue. */
 952         while (egress_cnt < DPAA_ETH_TXQ_NUM) {
 953                 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
 954                         if (fq->fq_type != FQ_TYPE_TX)
 955                                 continue;
 956                         priv->egress_fqs[egress_cnt++] = &fq->fq_base;
 957                         if (egress_cnt == DPAA_ETH_TXQ_NUM)
 958                                 break;
 959                 }
 960         }
 961 }
 962
 963 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
 964                                    struct qman_fq *tx_fq)
 965 {
 966         int i;
 967
 968         for (i = 0; i < DPAA_ETH_TXQ_NUM; i++)
 969                 if (priv->egress_fqs[i] == tx_fq)
 970                         return i;
 971
 972         return -EINVAL;
 973 }
 974
 975 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
 976 {
 977         const struct dpaa_priv  *priv;
 978         struct qman_fq *confq = NULL;
 979         struct qm_mcc_initfq initfq;
 980         struct device *dev;
 981         struct qman_fq *fq;
 982         int queue_id;
 983         int err;
 984
 985         priv = netdev_priv(dpaa_fq->net_dev);
 986         dev = dpaa_fq->net_dev->dev.parent;
 987
 988         if (dpaa_fq->fqid == 0)
 989                 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
 990
 991         dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
 992
 993         err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
 994         if (err) {
 995                 dev_err(dev, "qman_create_fq() failed\n");
 996                 return err;
 997         }
 998         fq = &dpaa_fq->fq_base;
 999
1000         if (dpaa_fq->init) {
1001                 memset(&initfq, 0, sizeof(initfq));
1002
1003                 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
1004                 /* Note: we may get to keep an empty FQ in cache */
1005                 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
1006
1007                 /* Try to reduce the number of portal interrupts for
1008                  * Tx Confirmation FQs.
1009                  */
1010                 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
1011                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
1012
1013                 /* FQ placement */
1014                 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1015
1016                 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
1017
1018                 /* Put all egress queues in a congestion group of their own.
1019                  * Sensu stricto, the Tx confirmation queues are Rx FQs,
1020                  * rather than Tx - but they nonetheless account for the
1021                  * memory footprint on behalf of egress traffic. We therefore
1022                  * place them in the netdev's CGR, along with the Tx FQs.
1023                  */
1024                 if (dpaa_fq->fq_type == FQ_TYPE_TX ||
1025                     dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
1026                     dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
1027                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1028                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1029                         initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1030                         /* Set a fixed overhead accounting, in an attempt to
1031                          * reduce the impact of fixed-size skb shells and the
1032                          * driver's needed headroom on system memory. This is
1033                          * especially the case when the egress traffic is
1034                          * composed of small datagrams.
1035                          * Unfortunately, QMan's OAL value is capped to an
1036                          * insufficient value, but even that is better than
1037                          * no overhead accounting at all.
1038                          */
1039                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1040                         qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1041                         qm_fqd_set_oal(&initfq.fqd,
1042                                        min(sizeof(struct sk_buff) +
1043                                        priv->tx_headroom,
1044                                        (size_t)FSL_QMAN_MAX_OAL));
1045                 }
1046
1047                 if (td_enable) {
1048                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1049                         qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1050                         initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1051                 }
1052
1053                 if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1054                         queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1055                         if (queue_id >= 0)
1056                                 confq = priv->conf_fqs[queue_id];
1057                         if (confq) {
1058                                 initfq.we_mask |=
1059                                         cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1060                         /* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1061                          *           A2V=1 (contextA A2 field is valid)
1062                          *           A0V=1 (contextA A0 field is valid)
1063                          *           B0V=1 (contextB field is valid)
1064                          * ContextA A2: EBD=1 (deallocate buffers inside FMan)
1065                          * ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1066                          */
1067                                 qm_fqd_context_a_set64(&initfq.fqd,
1068                                                        0x1e00000080000000ULL);
1069                         }
1070                 }
1071
1072                 /* Put all the ingress queues in our "ingress CGR". */
1073                 if (priv->use_ingress_cgr &&
1074                     (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1075                      dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
1076                      dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
1077                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1078                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1079                         initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1080                         /* Set a fixed overhead accounting, just like for the
1081                          * egress CGR.
1082                          */
1083                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1084                         qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1085                         qm_fqd_set_oal(&initfq.fqd,
1086                                        min(sizeof(struct sk_buff) +
1087                                        priv->tx_headroom,
1088                                        (size_t)FSL_QMAN_MAX_OAL));
1089                 }
1090
1091                 /* Initialization common to all ingress queues */
1092                 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1093                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1094                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
1095                                                 QM_FQCTRL_CTXASTASHING);
1096                         initfq.fqd.context_a.stashing.exclusive =
1097                                 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
1098                                 QM_STASHING_EXCL_ANNOTATION;
1099                         qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1100                                             DIV_ROUND_UP(sizeof(struct qman_fq),
1101                                                          64));
1102                 }
1103
1104                 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1105                 if (err < 0) {
1106                         dev_err(dev, "qman_init_fq(%u) = %d\n",
1107                                 qman_fq_fqid(fq), err);
1108                         qman_destroy_fq(fq);
1109                         return err;
1110                 }
1111         }
1112
1113         dpaa_fq->fqid = qman_fq_fqid(fq);
1114
1115         return 0;
1116 }
1117
1118 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
1119 {
1120         const struct dpaa_priv  *priv;
1121         struct dpaa_fq *dpaa_fq;
1122         int err, error;
1123
1124         err = 0;
1125
1126         dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1127         priv = netdev_priv(dpaa_fq->net_dev);
1128
1129         if (dpaa_fq->init) {
1130                 err = qman_retire_fq(fq, NULL);
1131                 if (err < 0 && netif_msg_drv(priv))
1132                         dev_err(dev, "qman_retire_fq(%u) = %d\n",
1133                                 qman_fq_fqid(fq), err);
1134
1135                 error = qman_oos_fq(fq);
1136                 if (error < 0 && netif_msg_drv(priv)) {
1137                         dev_err(dev, "qman_oos_fq(%u) = %d\n",
1138                                 qman_fq_fqid(fq), error);
1139                         if (err >= 0)
1140                                 err = error;
1141                 }
1142         }
1143
1144         qman_destroy_fq(fq);
1145         list_del(&dpaa_fq->list);
1146
1147         return err;
1148 }
1149
1150 static int dpaa_fq_free(struct device *dev, struct list_head *list)
1151 {
1152         struct dpaa_fq *dpaa_fq, *tmp;
1153         int err, error;
1154
1155         err = 0;
1156         list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1157                 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1158                 if (error < 0 && err >= 0)
1159                         err = error;
1160         }
1161
1162         return err;
1163 }
1164
1165 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
1166                                  struct dpaa_fq *defq,
1167                                  struct dpaa_buffer_layout *buf_layout)
1168 {
1169         struct fman_buffer_prefix_content buf_prefix_content;
1170         struct fman_port_params params;
1171         int err;
1172
1173         memset(&params, 0, sizeof(params));
1174         memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1175
1176         buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1177         buf_prefix_content.pass_prs_result = true;
1178         buf_prefix_content.pass_hash_result = true;
1179         buf_prefix_content.pass_time_stamp = false;
1180         buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1181
1182         params.specific_params.non_rx_params.err_fqid = errq->fqid;
1183         params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1184
1185         err = fman_port_config(port, &params);
1186         if (err) {
1187                 pr_err("%s: fman_port_config failed\n", __func__);
1188                 return err;
1189         }
1190
1191         err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1192         if (err) {
1193                 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1194                        __func__);
1195                 return err;
1196         }
1197
1198         err = fman_port_init(port);
1199         if (err)
1200                 pr_err("%s: fm_port_init failed\n", __func__);
1201
1202         return err;
1203 }
1204
1205 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp **bps,
1206                                  size_t count, struct dpaa_fq *errq,
1207                                  struct dpaa_fq *defq, struct dpaa_fq *pcdq,
1208                                  struct dpaa_buffer_layout *buf_layout)
1209 {
1210         struct fman_buffer_prefix_content buf_prefix_content;
1211         struct fman_port_rx_params *rx_p;
1212         struct fman_port_params params;
1213         int i, err;
1214
1215         memset(&params, 0, sizeof(params));
1216         memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1217
1218         buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1219         buf_prefix_content.pass_prs_result = true;
1220         buf_prefix_content.pass_hash_result = true;
1221         buf_prefix_content.pass_time_stamp = false;
1222         buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1223
1224         rx_p = &params.specific_params.rx_params;
1225         rx_p->err_fqid = errq->fqid;
1226         rx_p->dflt_fqid = defq->fqid;
1227         if (pcdq) {
1228                 rx_p->pcd_base_fqid = pcdq->fqid;
1229                 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
1230         }
1231
1232         count = min(ARRAY_SIZE(rx_p->ext_buf_pools.ext_buf_pool), count);
1233         rx_p->ext_buf_pools.num_of_pools_used = (u8)count;
1234         for (i = 0; i < count; i++) {
1235                 rx_p->ext_buf_pools.ext_buf_pool[i].id =  bps[i]->bpid;
1236                 rx_p->ext_buf_pools.ext_buf_pool[i].size = (u16)bps[i]->size;
1237         }
1238
1239         err = fman_port_config(port, &params);
1240         if (err) {
1241                 pr_err("%s: fman_port_config failed\n", __func__);
1242                 return err;
1243         }
1244
1245         err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1246         if (err) {
1247                 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1248                        __func__);
1249                 return err;
1250         }
1251
1252         err = fman_port_init(port);
1253         if (err)
1254                 pr_err("%s: fm_port_init failed\n", __func__);
1255
1256         return err;
1257 }
1258
1259 static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1260                                struct dpaa_bp **bps, size_t count,
1261                                struct fm_port_fqs *port_fqs,
1262                                struct dpaa_buffer_layout *buf_layout,
1263                                struct device *dev)
1264 {
1265         struct fman_port *rxport = mac_dev->port[RX];
1266         struct fman_port *txport = mac_dev->port[TX];
1267         int err;
1268
1269         err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1270                                     port_fqs->tx_defq, &buf_layout[TX]);
1271         if (err)
1272                 return err;
1273
1274         err = dpaa_eth_init_rx_port(rxport, bps, count, port_fqs->rx_errq,
1275                                     port_fqs->rx_defq, port_fqs->rx_pcdq,
1276                                     &buf_layout[RX]);
1277
1278         return err;
1279 }
1280
1281 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1282                              struct bm_buffer *bmb, int cnt)
1283 {
1284         int err;
1285
1286         err = bman_release(dpaa_bp->pool, bmb, cnt);
1287         /* Should never occur, address anyway to avoid leaking the buffers */
1288         if (unlikely(WARN_ON(err)) && dpaa_bp->free_buf_cb)
1289                 while (cnt-- > 0)
1290                         dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1291
1292         return cnt;
1293 }
1294
1295 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1296 {
1297         struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1298         struct dpaa_bp *dpaa_bp;
1299         int i = 0, j;
1300
1301         memset(bmb, 0, sizeof(bmb));
1302
1303         do {
1304                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1305                 if (!dpaa_bp)
1306                         return;
1307
1308                 j = 0;
1309                 do {
1310                         WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1311
1312                         bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1313
1314                         j++; i++;
1315                 } while (j < ARRAY_SIZE(bmb) &&
1316                                 !qm_sg_entry_is_final(&sgt[i - 1]) &&
1317                                 sgt[i - 1].bpid == sgt[i].bpid);
1318
1319                 dpaa_bman_release(dpaa_bp, bmb, j);
1320         } while (!qm_sg_entry_is_final(&sgt[i - 1]));
1321 }
1322
1323 static void dpaa_fd_release(const struct net_device *net_dev,
1324                             const struct qm_fd *fd)
1325 {
1326         struct qm_sg_entry *sgt;
1327         struct dpaa_bp *dpaa_bp;
1328         struct bm_buffer bmb;
1329         dma_addr_t addr;
1330         void *vaddr;
1331
1332         bmb.data = 0;
1333         bm_buffer_set64(&bmb, qm_fd_addr(fd));
1334
1335         dpaa_bp = dpaa_bpid2pool(fd->bpid);
1336         if (!dpaa_bp)
1337                 return;
1338
1339         if (qm_fd_get_format(fd) == qm_fd_sg) {
1340                 vaddr = phys_to_virt(qm_fd_addr(fd));
1341                 sgt = vaddr + qm_fd_get_offset(fd);
1342
1343                 dma_unmap_single(dpaa_bp->dev, qm_fd_addr(fd), dpaa_bp->size,
1344                                  DMA_FROM_DEVICE);
1345
1346                 dpaa_release_sgt_members(sgt);
1347
1348                 addr = dma_map_single(dpaa_bp->dev, vaddr, dpaa_bp->size,
1349                                       DMA_FROM_DEVICE);
1350                 if (dma_mapping_error(dpaa_bp->dev, addr)) {
1351                         dev_err(dpaa_bp->dev, "DMA mapping failed");
1352                         return;
1353                 }
1354                 bm_buffer_set64(&bmb, addr);
1355         }
1356
1357         dpaa_bman_release(dpaa_bp, &bmb, 1);
1358 }
1359
1360 static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1361                       const union qm_mr_entry *msg)
1362 {
1363         switch (msg->ern.rc & QM_MR_RC_MASK) {
1364         case QM_MR_RC_CGR_TAILDROP:
1365                 percpu_priv->ern_cnt.cg_tdrop++;
1366                 break;
1367         case QM_MR_RC_WRED:
1368                 percpu_priv->ern_cnt.wred++;
1369                 break;
1370         case QM_MR_RC_ERROR:
1371                 percpu_priv->ern_cnt.err_cond++;
1372                 break;
1373         case QM_MR_RC_ORPWINDOW_EARLY:
1374                 percpu_priv->ern_cnt.early_window++;
1375                 break;
1376         case QM_MR_RC_ORPWINDOW_LATE:
1377                 percpu_priv->ern_cnt.late_window++;
1378                 break;
1379         case QM_MR_RC_FQ_TAILDROP:
1380                 percpu_priv->ern_cnt.fq_tdrop++;
1381                 break;
1382         case QM_MR_RC_ORPWINDOW_RETIRED:
1383                 percpu_priv->ern_cnt.fq_retired++;
1384                 break;
1385         case QM_MR_RC_ORP_ZERO:
1386                 percpu_priv->ern_cnt.orp_zero++;
1387                 break;
1388         }
1389 }
1390
1391 /* Turn on HW checksum computation for this outgoing frame.
1392  * If the current protocol is not something we support in this regard
1393  * (or if the stack has already computed the SW checksum), we do nothing.
1394  *
1395  * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1396  * otherwise.
1397  *
1398  * Note that this function may modify the fd->cmd field and the skb data buffer
1399  * (the Parse Results area).
1400  */
1401 static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1402                                struct sk_buff *skb,
1403                                struct qm_fd *fd,
1404                                char *parse_results)
1405 {
1406         struct fman_prs_result *parse_result;
1407         u16 ethertype = ntohs(skb->protocol);
1408         struct ipv6hdr *ipv6h = NULL;
1409         struct iphdr *iph;
1410         int retval = 0;
1411         u8 l4_proto;
1412
1413         if (skb->ip_summed != CHECKSUM_PARTIAL)
1414                 return 0;
1415
1416         /* Note: L3 csum seems to be already computed in sw, but we can't choose
1417          * L4 alone from the FM configuration anyway.
1418          */
1419
1420         /* Fill in some fields of the Parse Results array, so the FMan
1421          * can find them as if they came from the FMan Parser.
1422          */
1423         parse_result = (struct fman_prs_result *)parse_results;
1424
1425         /* If we're dealing with VLAN, get the real Ethernet type */
1426         if (ethertype == ETH_P_8021Q) {
1427                 /* We can't always assume the MAC header is set correctly
1428                  * by the stack, so reset to beginning of skb->data
1429                  */
1430                 skb_reset_mac_header(skb);
1431                 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1432         }
1433
1434         /* Fill in the relevant L3 parse result fields
1435          * and read the L4 protocol type
1436          */
1437         switch (ethertype) {
1438         case ETH_P_IP:
1439                 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1440                 iph = ip_hdr(skb);
1441                 WARN_ON(!iph);
1442                 l4_proto = iph->protocol;
1443                 break;
1444         case ETH_P_IPV6:
1445                 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1446                 ipv6h = ipv6_hdr(skb);
1447                 WARN_ON(!ipv6h);
1448                 l4_proto = ipv6h->nexthdr;
1449                 break;
1450         default:
1451                 /* We shouldn't even be here */
1452                 if (net_ratelimit())
1453                         netif_alert(priv, tx_err, priv->net_dev,
1454                                     "Can't compute HW csum for L3 proto 0x%x\n",
1455                                     ntohs(skb->protocol));
1456                 retval = -EIO;
1457                 goto return_error;
1458         }
1459
1460         /* Fill in the relevant L4 parse result fields */
1461         switch (l4_proto) {
1462         case IPPROTO_UDP:
1463                 parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1464                 break;
1465         case IPPROTO_TCP:
1466                 parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1467                 break;
1468         default:
1469                 if (net_ratelimit())
1470                         netif_alert(priv, tx_err, priv->net_dev,
1471                                     "Can't compute HW csum for L4 proto 0x%x\n",
1472                                     l4_proto);
1473                 retval = -EIO;
1474                 goto return_error;
1475         }
1476
1477         /* At index 0 is IPOffset_1 as defined in the Parse Results */
1478         parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1479         parse_result->l4_off = (u8)skb_transport_offset(skb);
1480
1481         /* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1482         fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
1483
1484         /* On P1023 and similar platforms fd->cmd interpretation could
1485          * be disabled by setting CONTEXT_A bit ICMD; currently this bit
1486          * is not set so we do not need to check; in the future, if/when
1487          * using context_a we need to check this bit
1488          */
1489
1490 return_error:
1491         return retval;
1492 }
1493
1494 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1495 {
1496         struct device *dev = dpaa_bp->dev;
1497         struct bm_buffer bmb[8];
1498         dma_addr_t addr;
1499         void *new_buf;
1500         u8 i;
1501
1502         for (i = 0; i < 8; i++) {
1503                 new_buf = netdev_alloc_frag(dpaa_bp->raw_size);
1504                 if (unlikely(!new_buf)) {
1505                         dev_err(dev, "netdev_alloc_frag() failed, size %zu\n",
1506                                 dpaa_bp->raw_size);
1507                         goto release_previous_buffs;
1508                 }
1509                 new_buf = PTR_ALIGN(new_buf, SMP_CACHE_BYTES);
1510
1511                 addr = dma_map_single(dev, new_buf,
1512                                       dpaa_bp->size, DMA_FROM_DEVICE);
1513                 if (unlikely(dma_mapping_error(dev, addr))) {
1514                         dev_err(dpaa_bp->dev, "DMA map failed");
1515                         goto release_previous_buffs;
1516                 }
1517
1518                 bmb[i].data = 0;
1519                 bm_buffer_set64(&bmb[i], addr);
1520         }
1521
1522 release_bufs:
1523         return dpaa_bman_release(dpaa_bp, bmb, i);
1524
1525 release_previous_buffs:
1526         WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1527
1528         bm_buffer_set64(&bmb[i], 0);
1529         /* Avoid releasing a completely null buffer; bman_release() requires
1530          * at least one buffer.
1531          */
1532         if (likely(i))
1533                 goto release_bufs;
1534
1535         return 0;
1536 }
1537
1538 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1539 {
1540         int i;
1541
1542         /* Give each CPU an allotment of "config_count" buffers */
1543         for_each_possible_cpu(i) {
1544                 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1545                 int j;
1546
1547                 /* Although we access another CPU's counters here
1548                  * we do it at boot time so it is safe
1549                  */
1550                 for (j = 0; j < dpaa_bp->config_count; j += 8)
1551                         *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1552         }
1553         return 0;
1554 }
1555
1556 /* Add buffers/(pages) for Rx processing whenever bpool count falls below
1557  * REFILL_THRESHOLD.
1558  */
1559 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
1560 {
1561         int count = *countptr;
1562         int new_bufs;
1563
1564         if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1565                 do {
1566                         new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1567                         if (unlikely(!new_bufs)) {
1568                                 /* Avoid looping forever if we've temporarily
1569                                  * run out of memory. We'll try again at the
1570                                  * next NAPI cycle.
1571                                  */
1572                                 break;
1573                         }
1574                         count += new_bufs;
1575                 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1576
1577                 *countptr = count;
1578                 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1579                         return -ENOMEM;
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1586 {
1587         struct dpaa_bp *dpaa_bp;
1588         int *countptr;
1589         int res, i;
1590
1591         for (i = 0; i < DPAA_BPS_NUM; i++) {
1592                 dpaa_bp = priv->dpaa_bps[i];
1593                 if (!dpaa_bp)
1594                         return -EINVAL;
1595                 countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1596                 res  = dpaa_eth_refill_bpool(dpaa_bp, countptr);
1597                 if (res)
1598                         return res;
1599         }
1600         return 0;
1601 }
1602
1603 /* Cleanup function for outgoing frame descriptors that were built on Tx path,
1604  * either contiguous frames or scatter/gather ones.
1605  * Skb freeing is not handled here.
1606  *
1607  * This function may be called on error paths in the Tx function, so guard
1608  * against cases when not all fd relevant fields were filled in.
1609  *
1610  * Return the skb backpointer, since for S/G frames the buffer containing it
1611  * gets freed here.
1612  */
1613 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
1614                                           const struct qm_fd *fd)
1615 {
1616         const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1617         struct device *dev = priv->net_dev->dev.parent;
1618         dma_addr_t addr = qm_fd_addr(fd);
1619         const struct qm_sg_entry *sgt;
1620         struct sk_buff **skbh, *skb;
1621         int nr_frags, i;
1622
1623         skbh = (struct sk_buff **)phys_to_virt(addr);
1624         skb = *skbh;
1625
1626         if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1627                 nr_frags = skb_shinfo(skb)->nr_frags;
1628                 dma_unmap_single(dev, addr,
1629                                  qm_fd_get_offset(fd) + DPAA_SGT_SIZE,
1630                                  dma_dir);
1631
1632                 /* The sgt buffer has been allocated with netdev_alloc_frag(),
1633                  * it's from lowmem.
1634                  */
1635                 sgt = phys_to_virt(addr + qm_fd_get_offset(fd));
1636
1637                 /* sgt[0] is from lowmem, was dma_map_single()-ed */
1638                 dma_unmap_single(dev, qm_sg_addr(&sgt[0]),
1639                                  qm_sg_entry_get_len(&sgt[0]), dma_dir);
1640
1641                 /* remaining pages were mapped with skb_frag_dma_map() */
1642                 for (i = 1; i <= nr_frags; i++) {
1643                         WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1644
1645                         dma_unmap_page(dev, qm_sg_addr(&sgt[i]),
1646                                        qm_sg_entry_get_len(&sgt[i]), dma_dir);
1647                 }
1648
1649                 /* Free the page frag that we allocated on Tx */
1650                 skb_free_frag(phys_to_virt(addr));
1651         } else {
1652                 dma_unmap_single(dev, addr,
1653                                  skb_tail_pointer(skb) - (u8 *)skbh, dma_dir);
1654         }
1655
1656         return skb;
1657 }
1658
1659 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
1660 {
1661         /* The parser has run and performed L4 checksum validation.
1662          * We know there were no parser errors (and implicitly no
1663          * L4 csum error), otherwise we wouldn't be here.
1664          */
1665         if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1666             (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1667                 return CHECKSUM_UNNECESSARY;
1668
1669         /* We're here because either the parser didn't run or the L4 checksum
1670          * was not verified. This may include the case of a UDP frame with
1671          * checksum zero or an L4 proto other than TCP/UDP
1672          */
1673         return CHECKSUM_NONE;
1674 }
1675
1676 /* Build a linear skb around the received buffer.
1677  * We are guaranteed there is enough room at the end of the data buffer to
1678  * accommodate the shared info area of the skb.
1679  */
1680 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
1681                                         const struct qm_fd *fd)
1682 {
1683         ssize_t fd_off = qm_fd_get_offset(fd);
1684         dma_addr_t addr = qm_fd_addr(fd);
1685         struct dpaa_bp *dpaa_bp;
1686         struct sk_buff *skb;
1687         void *vaddr;
1688
1689         vaddr = phys_to_virt(addr);
1690         WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1691
1692         dpaa_bp = dpaa_bpid2pool(fd->bpid);
1693         if (!dpaa_bp)
1694                 goto free_buffer;
1695
1696         skb = build_skb(vaddr, dpaa_bp->size +
1697                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1698         if (unlikely(!skb)) {
1699                 WARN_ONCE(1, "Build skb failure on Rx\n");
1700                 goto free_buffer;
1701         }
1702         WARN_ON(fd_off != priv->rx_headroom);
1703         skb_reserve(skb, fd_off);
1704         skb_put(skb, qm_fd_get_length(fd));
1705
1706         skb->ip_summed = rx_csum_offload(priv, fd);
1707
1708         return skb;
1709
1710 free_buffer:
1711         skb_free_frag(vaddr);
1712         return NULL;
1713 }
1714
1715 /* Build an skb with the data of the first S/G entry in the linear portion and
1716  * the rest of the frame as skb fragments.
1717  *
1718  * The page fragment holding the S/G Table is recycled here.
1719  */
1720 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
1721                                     const struct qm_fd *fd)
1722 {
1723         ssize_t fd_off = qm_fd_get_offset(fd);
1724         dma_addr_t addr = qm_fd_addr(fd);
1725         const struct qm_sg_entry *sgt;
1726         struct page *page, *head_page;
1727         struct dpaa_bp *dpaa_bp;
1728         void *vaddr, *sg_vaddr;
1729         int frag_off, frag_len;
1730         struct sk_buff *skb;
1731         dma_addr_t sg_addr;
1732         int page_offset;
1733         unsigned int sz;
1734         int *count_ptr;
1735         int i;
1736
1737         vaddr = phys_to_virt(addr);
1738         WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1739
1740         /* Iterate through the SGT entries and add data buffers to the skb */
1741         sgt = vaddr + fd_off;
1742         for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1743                 /* Extension bit is not supported */
1744                 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1745
1746                 sg_addr = qm_sg_addr(&sgt[i]);
1747                 sg_vaddr = phys_to_virt(sg_addr);
1748                 WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr,
1749                                     SMP_CACHE_BYTES));
1750
1751                 /* We may use multiple Rx pools */
1752                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1753                 if (!dpaa_bp)
1754                         goto free_buffers;
1755
1756                 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1757                 dma_unmap_single(dpaa_bp->dev, sg_addr, dpaa_bp->size,
1758                                  DMA_FROM_DEVICE);
1759                 if (i == 0) {
1760                         sz = dpaa_bp->size +
1761                                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1762                         skb = build_skb(sg_vaddr, sz);
1763                         if (WARN_ON(unlikely(!skb)))
1764                                 goto free_buffers;
1765
1766                         skb->ip_summed = rx_csum_offload(priv, fd);
1767
1768                         /* Make sure forwarded skbs will have enough space
1769                          * on Tx, if extra headers are added.
1770                          */
1771                         WARN_ON(fd_off != priv->rx_headroom);
1772                         skb_reserve(skb, fd_off);
1773                         skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1774                 } else {
1775                         /* Not the first S/G entry; all data from buffer will
1776                          * be added in an skb fragment; fragment index is offset
1777                          * by one since first S/G entry was incorporated in the
1778                          * linear part of the skb.
1779                          *
1780                          * Caution: 'page' may be a tail page.
1781                          */
1782                         page = virt_to_page(sg_vaddr);
1783                         head_page = virt_to_head_page(sg_vaddr);
1784
1785                         /* Compute offset in (possibly tail) page */
1786                         page_offset = ((unsigned long)sg_vaddr &
1787                                         (PAGE_SIZE - 1)) +
1788                                 (page_address(page) - page_address(head_page));
1789                         /* page_offset only refers to the beginning of sgt[i];
1790                          * but the buffer itself may have an internal offset.
1791                          */
1792                         frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset;
1793                         frag_len = qm_sg_entry_get_len(&sgt[i]);
1794                         /* skb_add_rx_frag() does no checking on the page; if
1795                          * we pass it a tail page, we'll end up with
1796                          * bad page accounting and eventually with segafults.
1797                          */
1798                         skb_add_rx_frag(skb, i - 1, head_page, frag_off,
1799                                         frag_len, dpaa_bp->size);
1800                 }
1801                 /* Update the pool count for the current {cpu x bpool} */
1802                 (*count_ptr)--;
1803
1804                 if (qm_sg_entry_is_final(&sgt[i]))
1805                         break;
1806         }
1807         WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1808
1809         /* free the SG table buffer */
1810         skb_free_frag(vaddr);
1811
1812         return skb;
1813
1814 free_buffers:
1815         /* compensate sw bpool counter changes */
1816         for (i--; i >= 0; i--) {
1817                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1818                 if (dpaa_bp) {
1819                         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1820                         (*count_ptr)++;
1821                 }
1822         }
1823         /* free all the SG entries */
1824         for (i = 0; i < DPAA_SGT_MAX_ENTRIES ; i++) {
1825                 sg_addr = qm_sg_addr(&sgt[i]);
1826                 sg_vaddr = phys_to_virt(sg_addr);
1827                 skb_free_frag(sg_vaddr);
1828                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1829                 if (dpaa_bp) {
1830                         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1831                         (*count_ptr)--;
1832                 }
1833
1834                 if (qm_sg_entry_is_final(&sgt[i]))
1835                         break;
1836         }
1837         /* free the SGT fragment */
1838         skb_free_frag(vaddr);
1839
1840         return NULL;
1841 }
1842
1843 static int skb_to_contig_fd(struct dpaa_priv *priv,
1844                             struct sk_buff *skb, struct qm_fd *fd,
1845                             int *offset)
1846 {
1847         struct net_device *net_dev = priv->net_dev;
1848         struct device *dev = net_dev->dev.parent;
1849         enum dma_data_direction dma_dir;
1850         unsigned char *buffer_start;
1851         struct sk_buff **skbh;
1852         dma_addr_t addr;
1853         int err;
1854
1855         /* We are guaranteed to have at least tx_headroom bytes
1856          * available, so just use that for offset.
1857          */
1858         fd->bpid = FSL_DPAA_BPID_INV;
1859         buffer_start = skb->data - priv->tx_headroom;
1860         dma_dir = DMA_TO_DEVICE;
1861
1862         skbh = (struct sk_buff **)buffer_start;
1863         *skbh = skb;
1864
1865         /* Enable L3/L4 hardware checksum computation.
1866          *
1867          * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1868          * need to write into the skb.
1869          */
1870         err = dpaa_enable_tx_csum(priv, skb, fd,
1871                                   ((char *)skbh) + DPAA_TX_PRIV_DATA_SIZE);
1872         if (unlikely(err < 0)) {
1873                 if (net_ratelimit())
1874                         netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1875                                   err);
1876                 return err;
1877         }
1878
1879         /* Fill in the rest of the FD fields */
1880         qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1881         fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1882
1883         /* Map the entire buffer size that may be seen by FMan, but no more */
1884         addr = dma_map_single(dev, skbh,
1885                               skb_tail_pointer(skb) - buffer_start, dma_dir);
1886         if (unlikely(dma_mapping_error(dev, addr))) {
1887                 if (net_ratelimit())
1888                         netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1889                 return -EINVAL;
1890         }
1891         qm_fd_addr_set64(fd, addr);
1892
1893         return 0;
1894 }
1895
1896 static int skb_to_sg_fd(struct dpaa_priv *priv,
1897                         struct sk_buff *skb, struct qm_fd *fd)
1898 {
1899         const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1900         const int nr_frags = skb_shinfo(skb)->nr_frags;
1901         struct net_device *net_dev = priv->net_dev;
1902         struct device *dev = net_dev->dev.parent;
1903         struct qm_sg_entry *sgt;
1904         struct sk_buff **skbh;
1905         int i, j, err, sz;
1906         void *buffer_start;
1907         skb_frag_t *frag;
1908         dma_addr_t addr;
1909         size_t frag_len;
1910         void *sgt_buf;
1911
1912         /* get a page frag to store the SGTable */
1913         sz = SKB_DATA_ALIGN(priv->tx_headroom + DPAA_SGT_SIZE);
1914         sgt_buf = netdev_alloc_frag(sz);
1915         if (unlikely(!sgt_buf)) {
1916                 netdev_err(net_dev, "netdev_alloc_frag() failed for size %d\n",
1917                            sz);
1918                 return -ENOMEM;
1919         }
1920
1921         /* Enable L3/L4 hardware checksum computation.
1922          *
1923          * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1924          * need to write into the skb.
1925          */
1926         err = dpaa_enable_tx_csum(priv, skb, fd,
1927                                   sgt_buf + DPAA_TX_PRIV_DATA_SIZE);
1928         if (unlikely(err < 0)) {
1929                 if (net_ratelimit())
1930                         netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1931                                   err);
1932                 goto csum_failed;
1933         }
1934
1935         /* SGT[0] is used by the linear part */
1936         sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom);
1937         frag_len = skb_headlen(skb);
1938         qm_sg_entry_set_len(&sgt[0], frag_len);
1939         sgt[0].bpid = FSL_DPAA_BPID_INV;
1940         sgt[0].offset = 0;
1941         addr = dma_map_single(dev, skb->data,
1942                               skb_headlen(skb), dma_dir);
1943         if (unlikely(dma_mapping_error(dev, addr))) {
1944                 dev_err(dev, "DMA mapping failed");
1945                 err = -EINVAL;
1946                 goto sg0_map_failed;
1947         }
1948         qm_sg_entry_set64(&sgt[0], addr);
1949
1950         /* populate the rest of SGT entries */
1951         for (i = 0; i < nr_frags; i++) {
1952                 frag = &skb_shinfo(skb)->frags[i];
1953                 frag_len = frag->size;
1954                 WARN_ON(!skb_frag_page(frag));
1955                 addr = skb_frag_dma_map(dev, frag, 0,
1956                                         frag_len, dma_dir);
1957                 if (unlikely(dma_mapping_error(dev, addr))) {
1958                         dev_err(dev, "DMA mapping failed");
1959                         err = -EINVAL;
1960                         goto sg_map_failed;
1961                 }
1962
1963                 qm_sg_entry_set_len(&sgt[i + 1], frag_len);
1964                 sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
1965                 sgt[i + 1].offset = 0;
1966
1967                 /* keep the offset in the address */
1968                 qm_sg_entry_set64(&sgt[i + 1], addr);
1969         }
1970
1971         /* Set the final bit in the last used entry of the SGT */
1972         qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
1973
1974         qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
1975
1976         /* DMA map the SGT page */
1977         buffer_start = (void *)sgt - priv->tx_headroom;
1978         skbh = (struct sk_buff **)buffer_start;
1979         *skbh = skb;
1980
1981         addr = dma_map_single(dev, buffer_start,
1982                               priv->tx_headroom + DPAA_SGT_SIZE, dma_dir);
1983         if (unlikely(dma_mapping_error(dev, addr))) {
1984                 dev_err(dev, "DMA mapping failed");
1985                 err = -EINVAL;
1986                 goto sgt_map_failed;
1987         }
1988
1989         fd->bpid = FSL_DPAA_BPID_INV;
1990         fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1991         qm_fd_addr_set64(fd, addr);
1992
1993         return 0;
1994
1995 sgt_map_failed:
1996 sg_map_failed:
1997         for (j = 0; j < i; j++)
1998                 dma_unmap_page(dev, qm_sg_addr(&sgt[j]),
1999                                qm_sg_entry_get_len(&sgt[j]), dma_dir);
2000 sg0_map_failed:
2001 csum_failed:
2002         skb_free_frag(sgt_buf);
2003
2004         return err;
2005 }
2006
2007 static inline int dpaa_xmit(struct dpaa_priv *priv,
2008                             struct rtnl_link_stats64 *percpu_stats,
2009                             int queue,
2010                             struct qm_fd *fd)
2011 {
2012         struct qman_fq *egress_fq;
2013         int err, i;
2014
2015         egress_fq = priv->egress_fqs[queue];
2016         if (fd->bpid == FSL_DPAA_BPID_INV)
2017                 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2018
2019         /* Trace this Tx fd */
2020         trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2021
2022         for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2023                 err = qman_enqueue(egress_fq, fd);
2024                 if (err != -EBUSY)
2025                         break;
2026         }
2027
2028         if (unlikely(err < 0)) {
2029                 percpu_stats->tx_fifo_errors++;
2030                 return err;
2031         }
2032
2033         percpu_stats->tx_packets++;
2034         percpu_stats->tx_bytes += qm_fd_get_length(fd);
2035
2036         return 0;
2037 }
2038
2039 static netdev_tx_t
2040 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2041 {
2042         const int queue_mapping = skb_get_queue_mapping(skb);
2043         bool nonlinear = skb_is_nonlinear(skb);
2044         struct rtnl_link_stats64 *percpu_stats;
2045         struct dpaa_percpu_priv *percpu_priv;
2046         struct dpaa_priv *priv;
2047         struct qm_fd fd;
2048         int offset = 0;
2049         int err = 0;
2050
2051         priv = netdev_priv(net_dev);
2052         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2053         percpu_stats = &percpu_priv->stats;
2054
2055         qm_fd_clear_fd(&fd);
2056
2057         if (!nonlinear) {
2058                 /* We're going to store the skb backpointer at the beginning
2059                  * of the data buffer, so we need a privately owned skb
2060                  *
2061                  * We've made sure skb is not shared in dev->priv_flags,
2062                  * we need to verify the skb head is not cloned
2063                  */
2064                 if (skb_cow_head(skb, priv->tx_headroom))
2065                         goto enomem;
2066
2067                 WARN_ON(skb_is_nonlinear(skb));
2068         }
2069
2070         /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2071          * make sure we don't feed FMan with more fragments than it supports.
2072          */
2073         if (nonlinear &&
2074             likely(skb_shinfo(skb)->nr_frags < DPAA_SGT_MAX_ENTRIES)) {
2075                 /* Just create a S/G fd based on the skb */
2076                 err = skb_to_sg_fd(priv, skb, &fd);
2077                 percpu_priv->tx_frag_skbuffs++;
2078         } else {
2079                 /* If the egress skb contains more fragments than we support
2080                  * we have no choice but to linearize it ourselves.
2081                  */
2082                 if (unlikely(nonlinear) && __skb_linearize(skb))
2083                         goto enomem;
2084
2085                 /* Finally, create a contig FD from this skb */
2086                 err = skb_to_contig_fd(priv, skb, &fd, &offset);
2087         }
2088         if (unlikely(err < 0))
2089                 goto skb_to_fd_failed;
2090
2091         if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2092                 return NETDEV_TX_OK;
2093
2094         dpaa_cleanup_tx_fd(priv, &fd);
2095 skb_to_fd_failed:
2096 enomem:
2097         percpu_stats->tx_errors++;
2098         dev_kfree_skb(skb);
2099         return NETDEV_TX_OK;
2100 }
2101
2102 static void dpaa_rx_error(struct net_device *net_dev,
2103                           const struct dpaa_priv *priv,
2104                           struct dpaa_percpu_priv *percpu_priv,
2105                           const struct qm_fd *fd,
2106                           u32 fqid)
2107 {
2108         if (net_ratelimit())
2109                 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2110                           be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2111
2112         percpu_priv->stats.rx_errors++;
2113
2114         if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2115                 percpu_priv->rx_errors.dme++;
2116         if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2117                 percpu_priv->rx_errors.fpe++;
2118         if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2119                 percpu_priv->rx_errors.fse++;
2120         if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2121                 percpu_priv->rx_errors.phe++;
2122
2123         dpaa_fd_release(net_dev, fd);
2124 }
2125
2126 static void dpaa_tx_error(struct net_device *net_dev,
2127                           const struct dpaa_priv *priv,
2128                           struct dpaa_percpu_priv *percpu_priv,
2129                           const struct qm_fd *fd,
2130                           u32 fqid)
2131 {
2132         struct sk_buff *skb;
2133
2134         if (net_ratelimit())
2135                 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2136                            be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2137
2138         percpu_priv->stats.tx_errors++;
2139
2140         skb = dpaa_cleanup_tx_fd(priv, fd);
2141         dev_kfree_skb(skb);
2142 }
2143
2144 static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2145 {
2146         struct dpaa_napi_portal *np =
2147                         container_of(napi, struct dpaa_napi_portal, napi);
2148
2149         int cleaned = qman_p_poll_dqrr(np->p, budget);
2150
2151         if (cleaned < budget) {
2152                 napi_complete_done(napi, cleaned);
2153                 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2154
2155         } else if (np->down) {
2156                 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2157         }
2158
2159         return cleaned;
2160 }
2161
2162 static void dpaa_tx_conf(struct net_device *net_dev,
2163                          const struct dpaa_priv *priv,
2164                          struct dpaa_percpu_priv *percpu_priv,
2165                          const struct qm_fd *fd,
2166                          u32 fqid)
2167 {
2168         struct sk_buff  *skb;
2169
2170         if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2171                 if (net_ratelimit())
2172                         netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2173                                    be32_to_cpu(fd->status) &
2174                                    FM_FD_STAT_TX_ERRORS);
2175
2176                 percpu_priv->stats.tx_errors++;
2177         }
2178
2179         percpu_priv->tx_confirm++;
2180
2181         skb = dpaa_cleanup_tx_fd(priv, fd);
2182
2183         consume_skb(skb);
2184 }
2185
2186 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2187                                          struct qman_portal *portal)
2188 {
2189         if (unlikely(in_irq() || !in_serving_softirq())) {
2190                 /* Disable QMan IRQ and invoke NAPI */
2191                 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2192
2193                 percpu_priv->np.p = portal;
2194                 napi_schedule(&percpu_priv->np.napi);
2195                 percpu_priv->in_interrupt++;
2196                 return 1;
2197         }
2198         return 0;
2199 }
2200
2201 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2202                                               struct qman_fq *fq,
2203                                               const struct qm_dqrr_entry *dq)
2204 {
2205         struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2206         struct dpaa_percpu_priv *percpu_priv;
2207         struct net_device *net_dev;
2208         struct dpaa_bp *dpaa_bp;
2209         struct dpaa_priv *priv;
2210
2211         net_dev = dpaa_fq->net_dev;
2212         priv = netdev_priv(net_dev);
2213         dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2214         if (!dpaa_bp)
2215                 return qman_cb_dqrr_consume;
2216
2217         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2218
2219         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2220                 return qman_cb_dqrr_stop;
2221
2222         if (dpaa_eth_refill_bpools(priv))
2223                 /* Unable to refill the buffer pool due to insufficient
2224                  * system memory. Just release the frame back into the pool,
2225                  * otherwise we'll soon end up with an empty buffer pool.
2226                  */
2227                 dpaa_fd_release(net_dev, &dq->fd);
2228         else
2229                 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2230
2231         return qman_cb_dqrr_consume;
2232 }
2233
2234 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2235                                                 struct qman_fq *fq,
2236                                                 const struct qm_dqrr_entry *dq)
2237 {
2238         struct rtnl_link_stats64 *percpu_stats;
2239         struct dpaa_percpu_priv *percpu_priv;
2240         const struct qm_fd *fd = &dq->fd;
2241         dma_addr_t addr = qm_fd_addr(fd);
2242         enum qm_fd_format fd_format;
2243         struct net_device *net_dev;
2244         u32 fd_status, hash_offset;
2245         struct dpaa_bp *dpaa_bp;
2246         struct dpaa_priv *priv;
2247         unsigned int skb_len;
2248         struct sk_buff *skb;
2249         int *count_ptr;
2250         void *vaddr;
2251
2252         fd_status = be32_to_cpu(fd->status);
2253         fd_format = qm_fd_get_format(fd);
2254         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2255         priv = netdev_priv(net_dev);
2256         dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2257         if (!dpaa_bp)
2258                 return qman_cb_dqrr_consume;
2259
2260         /* Trace the Rx fd */
2261         trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2262
2263         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2264         percpu_stats = &percpu_priv->stats;
2265
2266         if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal)))
2267                 return qman_cb_dqrr_stop;
2268
2269         /* Make sure we didn't run out of buffers */
2270         if (unlikely(dpaa_eth_refill_bpools(priv))) {
2271                 /* Unable to refill the buffer pool due to insufficient
2272                  * system memory. Just release the frame back into the pool,
2273                  * otherwise we'll soon end up with an empty buffer pool.
2274                  */
2275                 dpaa_fd_release(net_dev, &dq->fd);
2276                 return qman_cb_dqrr_consume;
2277         }
2278
2279         if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2280                 if (net_ratelimit())
2281                         netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2282                                    fd_status & FM_FD_STAT_RX_ERRORS);
2283
2284                 percpu_stats->rx_errors++;
2285                 dpaa_fd_release(net_dev, fd);
2286                 return qman_cb_dqrr_consume;
2287         }
2288
2289         dpaa_bp = dpaa_bpid2pool(fd->bpid);
2290         if (!dpaa_bp)
2291                 return qman_cb_dqrr_consume;
2292
2293         dma_unmap_single(dpaa_bp->dev, addr, dpaa_bp->size, DMA_FROM_DEVICE);
2294
2295         /* prefetch the first 64 bytes of the frame or the SGT start */
2296         vaddr = phys_to_virt(addr);
2297         prefetch(vaddr + qm_fd_get_offset(fd));
2298
2299         /* The only FD types that we may receive are contig and S/G */
2300         WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2301
2302         /* Account for either the contig buffer or the SGT buffer (depending on
2303          * which case we were in) having been removed from the pool.
2304          */
2305         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2306         (*count_ptr)--;
2307
2308         if (likely(fd_format == qm_fd_contig))
2309                 skb = contig_fd_to_skb(priv, fd);
2310         else
2311                 skb = sg_fd_to_skb(priv, fd);
2312         if (!skb)
2313                 return qman_cb_dqrr_consume;
2314
2315         skb->protocol = eth_type_trans(skb, net_dev);
2316
2317         if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
2318             !fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
2319                                               &hash_offset)) {
2320                 enum pkt_hash_types type;
2321
2322                 /* if L4 exists, it was used in the hash generation */
2323                 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
2324                         PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
2325                 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)),
2326                              type);
2327         }
2328
2329         skb_len = skb->len;
2330
2331         if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
2332                 percpu_stats->rx_dropped++;
2333                 return qman_cb_dqrr_consume;
2334         }
2335
2336         percpu_stats->rx_packets++;
2337         percpu_stats->rx_bytes += skb_len;
2338
2339         return qman_cb_dqrr_consume;
2340 }
2341
2342 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2343                                                 struct qman_fq *fq,
2344                                                 const struct qm_dqrr_entry *dq)
2345 {
2346         struct dpaa_percpu_priv *percpu_priv;
2347         struct net_device *net_dev;
2348         struct dpaa_priv *priv;
2349
2350         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2351         priv = netdev_priv(net_dev);
2352
2353         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2354
2355         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2356                 return qman_cb_dqrr_stop;
2357
2358         dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2359
2360         return qman_cb_dqrr_consume;
2361 }
2362
2363 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2364                                                struct qman_fq *fq,
2365                                                const struct qm_dqrr_entry *dq)
2366 {
2367         struct dpaa_percpu_priv *percpu_priv;
2368         struct net_device *net_dev;
2369         struct dpaa_priv *priv;
2370
2371         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2372         priv = netdev_priv(net_dev);
2373
2374         /* Trace the fd */
2375         trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2376
2377         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2378
2379         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2380                 return qman_cb_dqrr_stop;
2381
2382         dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2383
2384         return qman_cb_dqrr_consume;
2385 }
2386
2387 static void egress_ern(struct qman_portal *portal,
2388                        struct qman_fq *fq,
2389                        const union qm_mr_entry *msg)
2390 {
2391         const struct qm_fd *fd = &msg->ern.fd;
2392         struct dpaa_percpu_priv *percpu_priv;
2393         const struct dpaa_priv *priv;
2394         struct net_device *net_dev;
2395         struct sk_buff *skb;
2396
2397         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2398         priv = netdev_priv(net_dev);
2399         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2400
2401         percpu_priv->stats.tx_dropped++;
2402         percpu_priv->stats.tx_fifo_errors++;
2403         count_ern(percpu_priv, msg);
2404
2405         skb = dpaa_cleanup_tx_fd(priv, fd);
2406         dev_kfree_skb_any(skb);
2407 }
2408
2409 static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2410         .rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2411         .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2412         .rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2413         .tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2414         .egress_ern = { .cb = { .ern = egress_ern } }
2415 };
2416
2417 static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2418 {
2419         struct dpaa_percpu_priv *percpu_priv;
2420         int i;
2421
2422         for_each_possible_cpu(i) {
2423                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2424
2425                 percpu_priv->np.down = 0;
2426                 napi_enable(&percpu_priv->np.napi);
2427         }
2428 }
2429
2430 static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2431 {
2432         struct dpaa_percpu_priv *percpu_priv;
2433         int i;
2434
2435         for_each_possible_cpu(i) {
2436                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2437
2438                 percpu_priv->np.down = 1;
2439                 napi_disable(&percpu_priv->np.napi);
2440         }
2441 }
2442
2443 static int dpaa_open(struct net_device *net_dev)
2444 {
2445         struct mac_device *mac_dev;
2446         struct dpaa_priv *priv;
2447         int err, i;
2448
2449         priv = netdev_priv(net_dev);
2450         mac_dev = priv->mac_dev;
2451         dpaa_eth_napi_enable(priv);
2452
2453         net_dev->phydev = mac_dev->init_phy(net_dev, priv->mac_dev);
2454         if (!net_dev->phydev) {
2455                 netif_err(priv, ifup, net_dev, "init_phy() failed\n");
2456                 err = -ENODEV;
2457                 goto phy_init_failed;
2458         }
2459
2460         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2461                 err = fman_port_enable(mac_dev->port[i]);
2462                 if (err)
2463                         goto mac_start_failed;
2464         }
2465
2466         err = priv->mac_dev->start(mac_dev);
2467         if (err < 0) {
2468                 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err);
2469                 goto mac_start_failed;
2470         }
2471
2472         netif_tx_start_all_queues(net_dev);
2473
2474         return 0;
2475
2476 mac_start_failed:
2477         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2478                 fman_port_disable(mac_dev->port[i]);
2479
2480 phy_init_failed:
2481         dpaa_eth_napi_disable(priv);
2482
2483         return err;
2484 }
2485
2486 static int dpaa_eth_stop(struct net_device *net_dev)
2487 {
2488         struct dpaa_priv *priv;
2489         int err;
2490
2491         err = dpaa_stop(net_dev);
2492
2493         priv = netdev_priv(net_dev);
2494         dpaa_eth_napi_disable(priv);
2495
2496         return err;
2497 }
2498
2499 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2500 {
2501         if (!net_dev->phydev)
2502                 return -EINVAL;
2503         return phy_mii_ioctl(net_dev->phydev, rq, cmd);
2504 }
2505
2506 static const struct net_device_ops dpaa_ops = {
2507         .ndo_open = dpaa_open,
2508         .ndo_start_xmit = dpaa_start_xmit,
2509         .ndo_stop = dpaa_eth_stop,
2510         .ndo_tx_timeout = dpaa_tx_timeout,
2511         .ndo_get_stats64 = dpaa_get_stats64,
2512         .ndo_set_mac_address = dpaa_set_mac_address,
2513         .ndo_validate_addr = eth_validate_addr,
2514         .ndo_set_rx_mode = dpaa_set_rx_mode,
2515         .ndo_do_ioctl = dpaa_ioctl,
2516         .ndo_setup_tc = dpaa_setup_tc,
2517 };
2518
2519 static int dpaa_napi_add(struct net_device *net_dev)
2520 {
2521         struct dpaa_priv *priv = netdev_priv(net_dev);
2522         struct dpaa_percpu_priv *percpu_priv;
2523         int cpu;
2524
2525         for_each_possible_cpu(cpu) {
2526                 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2527
2528                 netif_napi_add(net_dev, &percpu_priv->np.napi,
2529                                dpaa_eth_poll, NAPI_POLL_WEIGHT);
2530         }
2531
2532         return 0;
2533 }
2534
2535 static void dpaa_napi_del(struct net_device *net_dev)
2536 {
2537         struct dpaa_priv *priv = netdev_priv(net_dev);
2538         struct dpaa_percpu_priv *percpu_priv;
2539         int cpu;
2540
2541         for_each_possible_cpu(cpu) {
2542                 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2543
2544                 netif_napi_del(&percpu_priv->np.napi);
2545         }
2546 }
2547
2548 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
2549                                    struct bm_buffer *bmb)
2550 {
2551         dma_addr_t addr = bm_buf_addr(bmb);
2552
2553         dma_unmap_single(bp->dev, addr, bp->size, DMA_FROM_DEVICE);
2554
2555         skb_free_frag(phys_to_virt(addr));
2556 }
2557
2558 /* Alloc the dpaa_bp struct and configure default values */
2559 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
2560 {
2561         struct dpaa_bp *dpaa_bp;
2562
2563         dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
2564         if (!dpaa_bp)
2565                 return ERR_PTR(-ENOMEM);
2566
2567         dpaa_bp->bpid = FSL_DPAA_BPID_INV;
2568         dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
2569         if (!dpaa_bp->percpu_count)
2570                 return ERR_PTR(-ENOMEM);
2571
2572         dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
2573
2574         dpaa_bp->seed_cb = dpaa_bp_seed;
2575         dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
2576
2577         return dpaa_bp;
2578 }
2579
2580 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
2581  * We won't be sending congestion notifications to FMan; for now, we just use
2582  * this CGR to generate enqueue rejections to FMan in order to drop the frames
2583  * before they reach our ingress queues and eat up memory.
2584  */
2585 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
2586 {
2587         struct qm_mcc_initcgr initcgr;
2588         u32 cs_th;
2589         int err;
2590
2591         err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
2592         if (err < 0) {
2593                 if (netif_msg_drv(priv))
2594                         pr_err("Error %d allocating CGR ID\n", err);
2595                 goto out_error;
2596         }
2597
2598         /* Enable CS TD, but disable Congestion State Change Notifications. */
2599         memset(&initcgr, 0, sizeof(initcgr));
2600         initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
2601         initcgr.cgr.cscn_en = QM_CGR_EN;
2602         cs_th = DPAA_INGRESS_CS_THRESHOLD;
2603         qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
2604
2605         initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
2606         initcgr.cgr.cstd_en = QM_CGR_EN;
2607
2608         /* This CGR will be associated with the SWP affined to the current CPU.
2609          * However, we'll place all our ingress FQs in it.
2610          */
2611         err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
2612                               &initcgr);
2613         if (err < 0) {
2614                 if (netif_msg_drv(priv))
2615                         pr_err("Error %d creating ingress CGR with ID %d\n",
2616                                err, priv->ingress_cgr.cgrid);
2617                 qman_release_cgrid(priv->ingress_cgr.cgrid);
2618                 goto out_error;
2619         }
2620         if (netif_msg_drv(priv))
2621                 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
2622                          priv->ingress_cgr.cgrid, priv->mac_dev->addr);
2623
2624         priv->use_ingress_cgr = true;
2625
2626 out_error:
2627         return err;
2628 }
2629
2630 static const struct of_device_id dpaa_match[];
2631
2632 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
2633 {
2634         u16 headroom;
2635
2636         /* The frame headroom must accommodate:
2637          * - the driver private data area
2638          * - parse results, hash results, timestamp if selected
2639          * If either hash results or time stamp are selected, both will
2640          * be copied to/from the frame headroom, as TS is located between PR and
2641          * HR in the IC and IC copy size has a granularity of 16bytes
2642          * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
2643          *
2644          * Also make sure the headroom is a multiple of data_align bytes
2645          */
2646         headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
2647                 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
2648
2649         return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
2650 }
2651
2652 static int dpaa_eth_probe(struct platform_device *pdev)
2653 {
2654         struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM] = {NULL};
2655         struct dpaa_percpu_priv *percpu_priv;
2656         struct net_device *net_dev = NULL;
2657         struct dpaa_fq *dpaa_fq, *tmp;
2658         struct dpaa_priv *priv = NULL;
2659         struct fm_port_fqs port_fqs;
2660         struct mac_device *mac_dev;
2661         int err = 0, i, channel;
2662         struct device *dev;
2663
2664         dev = &pdev->dev;
2665
2666         /* Allocate this early, so we can store relevant information in
2667          * the private area
2668          */
2669         net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
2670         if (!net_dev) {
2671                 dev_err(dev, "alloc_etherdev_mq() failed\n");
2672                 goto alloc_etherdev_mq_failed;
2673         }
2674
2675         /* Do this here, so we can be verbose early */
2676         SET_NETDEV_DEV(net_dev, dev);
2677         dev_set_drvdata(dev, net_dev);
2678
2679         priv = netdev_priv(net_dev);
2680         priv->net_dev = net_dev;
2681
2682         priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
2683
2684         mac_dev = dpaa_mac_dev_get(pdev);
2685         if (IS_ERR(mac_dev)) {
2686                 dev_err(dev, "dpaa_mac_dev_get() failed\n");
2687                 err = PTR_ERR(mac_dev);
2688                 goto mac_probe_failed;
2689         }
2690
2691         /* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
2692          * we choose conservatively and let the user explicitly set a higher
2693          * MTU via ifconfig. Otherwise, the user may end up with different MTUs
2694          * in the same LAN.
2695          * If on the other hand fsl_fm_max_frm has been chosen below 1500,
2696          * start with the maximum allowed.
2697          */
2698         net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
2699
2700         netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
2701                    net_dev->mtu);
2702
2703         priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
2704         priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
2705
2706         /* device used for DMA mapping */
2707         set_dma_ops(dev, get_dma_ops(&pdev->dev));
2708         err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40));
2709         if (err) {
2710                 dev_err(dev, "dma_coerce_mask_and_coherent() failed\n");
2711                 goto dev_mask_failed;
2712         }
2713
2714         /* bp init */
2715         for (i = 0; i < DPAA_BPS_NUM; i++) {
2716                 int err;
2717
2718                 dpaa_bps[i] = dpaa_bp_alloc(dev);
2719                 if (IS_ERR(dpaa_bps[i]))
2720                         return PTR_ERR(dpaa_bps[i]);
2721                 /* the raw size of the buffers used for reception */
2722                 dpaa_bps[i]->raw_size = bpool_buffer_raw_size(i, DPAA_BPS_NUM);
2723                 /* avoid runtime computations by keeping the usable size here */
2724                 dpaa_bps[i]->size = dpaa_bp_size(dpaa_bps[i]->raw_size);
2725                 dpaa_bps[i]->dev = dev;
2726
2727                 err = dpaa_bp_alloc_pool(dpaa_bps[i]);
2728                 if (err < 0) {
2729                         dpaa_bps_free(priv);
2730                         priv->dpaa_bps[i] = NULL;
2731                         goto bp_create_failed;
2732                 }
2733                 priv->dpaa_bps[i] = dpaa_bps[i];
2734         }
2735
2736         INIT_LIST_HEAD(&priv->dpaa_fq_list);
2737
2738         memset(&port_fqs, 0, sizeof(port_fqs));
2739
2740         err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
2741         if (err < 0) {
2742                 dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
2743                 goto fq_probe_failed;
2744         }
2745
2746         priv->mac_dev = mac_dev;
2747
2748         channel = dpaa_get_channel();
2749         if (channel < 0) {
2750                 dev_err(dev, "dpaa_get_channel() failed\n");
2751                 err = channel;
2752                 goto get_channel_failed;
2753         }
2754
2755         priv->channel = (u16)channel;
2756
2757         /* Start a thread that will walk the CPUs with affine portals
2758          * and add this pool channel to each's dequeue mask.
2759          */
2760         dpaa_eth_add_channel(priv->channel);
2761
2762         dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
2763
2764         /* Create a congestion group for this netdev, with
2765          * dynamically-allocated CGR ID.
2766          * Must be executed after probing the MAC, but before
2767          * assigning the egress FQs to the CGRs.
2768          */
2769         err = dpaa_eth_cgr_init(priv);
2770         if (err < 0) {
2771                 dev_err(dev, "Error initializing CGR\n");
2772                 goto tx_cgr_init_failed;
2773         }
2774
2775         err = dpaa_ingress_cgr_init(priv);
2776         if (err < 0) {
2777                 dev_err(dev, "Error initializing ingress CGR\n");
2778                 goto rx_cgr_init_failed;
2779         }
2780
2781         /* Add the FQs to the interface, and make them active */
2782         list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
2783                 err = dpaa_fq_init(dpaa_fq, false);
2784                 if (err < 0)
2785                         goto fq_alloc_failed;
2786         }
2787
2788         priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
2789         priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]);
2790
2791         /* All real interfaces need their ports initialized */
2792         err = dpaa_eth_init_ports(mac_dev, dpaa_bps, DPAA_BPS_NUM, &port_fqs,
2793                                   &priv->buf_layout[0], dev);
2794         if (err)
2795                 goto init_ports_failed;
2796
2797         /* Rx traffic distribution based on keygen hashing defaults to on */
2798         priv->keygen_in_use = true;
2799
2800         priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
2801         if (!priv->percpu_priv) {
2802                 dev_err(dev, "devm_alloc_percpu() failed\n");
2803                 err = -ENOMEM;
2804                 goto alloc_percpu_failed;
2805         }
2806         for_each_possible_cpu(i) {
2807                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2808                 memset(percpu_priv, 0, sizeof(*percpu_priv));
2809         }
2810
2811         priv->num_tc = 1;
2812         netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
2813
2814         /* Initialize NAPI */
2815         err = dpaa_napi_add(net_dev);
2816         if (err < 0)
2817                 goto napi_add_failed;
2818
2819         err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
2820         if (err < 0)
2821                 goto netdev_init_failed;
2822
2823         dpaa_eth_sysfs_init(&net_dev->dev);
2824
2825         netif_info(priv, probe, net_dev, "Probed interface %s\n",
2826                    net_dev->name);
2827
2828         return 0;
2829
2830 netdev_init_failed:
2831 napi_add_failed:
2832         dpaa_napi_del(net_dev);
2833 alloc_percpu_failed:
2834 init_ports_failed:
2835         dpaa_fq_free(dev, &priv->dpaa_fq_list);
2836 fq_alloc_failed:
2837         qman_delete_cgr_safe(&priv->ingress_cgr);
2838         qman_release_cgrid(priv->ingress_cgr.cgrid);
2839 rx_cgr_init_failed:
2840         qman_delete_cgr_safe(&priv->cgr_data.cgr);
2841         qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2842 tx_cgr_init_failed:
2843 get_channel_failed:
2844         dpaa_bps_free(priv);
2845 bp_create_failed:
2846 fq_probe_failed:
2847 dev_mask_failed:
2848 mac_probe_failed:
2849         dev_set_drvdata(dev, NULL);
2850         free_netdev(net_dev);
2851 alloc_etherdev_mq_failed:
2852         for (i = 0; i < DPAA_BPS_NUM && dpaa_bps[i]; i++) {
2853                 if (atomic_read(&dpaa_bps[i]->refs) == 0)
2854                         devm_kfree(dev, dpaa_bps[i]);
2855         }
2856         return err;
2857 }
2858
2859 static int dpaa_remove(struct platform_device *pdev)
2860 {
2861         struct net_device *net_dev;
2862         struct dpaa_priv *priv;
2863         struct device *dev;
2864         int err;
2865
2866         dev = &pdev->dev;
2867         net_dev = dev_get_drvdata(dev);
2868
2869         priv = netdev_priv(net_dev);
2870
2871         dpaa_eth_sysfs_remove(dev);
2872
2873         dev_set_drvdata(dev, NULL);
2874         unregister_netdev(net_dev);
2875
2876         err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
2877
2878         qman_delete_cgr_safe(&priv->ingress_cgr);
2879         qman_release_cgrid(priv->ingress_cgr.cgrid);
2880         qman_delete_cgr_safe(&priv->cgr_data.cgr);
2881         qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2882
2883         dpaa_napi_del(net_dev);
2884
2885         dpaa_bps_free(priv);
2886
2887         free_netdev(net_dev);
2888
2889         return err;
2890 }
2891
2892 static const struct platform_device_id dpaa_devtype[] = {
2893         {
2894                 .name = "dpaa-ethernet",
2895                 .driver_data = 0,
2896         }, {
2897         }
2898 };
2899 MODULE_DEVICE_TABLE(platform, dpaa_devtype);
2900
2901 static struct platform_driver dpaa_driver = {
2902         .driver = {
2903                 .name = KBUILD_MODNAME,
2904         },
2905         .id_table = dpaa_devtype,
2906         .probe = dpaa_eth_probe,
2907         .remove = dpaa_remove
2908 };
2909
2910 static int __init dpaa_load(void)
2911 {
2912         int err;
2913
2914         pr_debug("FSL DPAA Ethernet driver\n");
2915
2916         /* initialize dpaa_eth mirror values */
2917         dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
2918         dpaa_max_frm = fman_get_max_frm();
2919
2920         err = platform_driver_register(&dpaa_driver);
2921         if (err < 0)
2922                 pr_err("Error, platform_driver_register() = %d\n", err);
2923
2924         return err;
2925 }
2926 module_init(dpaa_load);
2927
2928 static void __exit dpaa_unload(void)
2929 {
2930         platform_driver_unregister(&dpaa_driver);
2931
2932         /* Only one channel is used and needs to be released after all
2933          * interfaces are removed
2934          */
2935         dpaa_release_channel();
2936 }
2937 module_exit(dpaa_unload);
2938
2939 MODULE_LICENSE("Dual BSD/GPL");
2940 MODULE_DESCRIPTION("FSL DPAA Ethernet driver");