2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
63 #include <soc/imx/cpuidle.h>
65 #include <asm/cacheflush.h>
69 static void set_multicast_list(struct net_device *ndev);
70 static void fec_enet_itr_coal_init(struct net_device *ndev);
72 #define DRIVER_NAME "fec"
74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
76 /* Pause frame feild and FIFO threshold */
77 #define FEC_ENET_FCE (1 << 5)
78 #define FEC_ENET_RSEM_V 0x84
79 #define FEC_ENET_RSFL_V 16
80 #define FEC_ENET_RAEM_V 0x8
81 #define FEC_ENET_RAFL_V 0x8
82 #define FEC_ENET_OPD_V 0xFFF0
83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
85 static struct platform_device_id fec_devtype[] = {
87 /* keep it for coldfire */
92 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
96 .driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
99 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
100 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
104 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
105 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
106 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
109 .name = "mvf600-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
112 .name = "imx6sx-fec",
113 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
114 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
115 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
116 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
117 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
119 .name = "imx6ul-fec",
120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
123 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
124 FEC_QUIRK_HAS_COALESCE,
129 MODULE_DEVICE_TABLE(platform, fec_devtype);
132 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
133 IMX27_FEC, /* runs on i.mx27/35/51 */
141 static const struct of_device_id fec_dt_ids[] = {
142 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
143 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
144 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
145 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
146 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
147 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
148 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
151 MODULE_DEVICE_TABLE(of, fec_dt_ids);
153 static unsigned char macaddr[ETH_ALEN];
154 module_param_array(macaddr, byte, NULL, 0);
155 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
157 #if defined(CONFIG_M5272)
159 * Some hardware gets it MAC address out of local flash memory.
160 * if this is non-zero then assume it is the address to get MAC from.
162 #if defined(CONFIG_NETtel)
163 #define FEC_FLASHMAC 0xf0006006
164 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
165 #define FEC_FLASHMAC 0xf0006000
166 #elif defined(CONFIG_CANCam)
167 #define FEC_FLASHMAC 0xf0020000
168 #elif defined (CONFIG_M5272C3)
169 #define FEC_FLASHMAC (0xffe04000 + 4)
170 #elif defined(CONFIG_MOD5272)
171 #define FEC_FLASHMAC 0xffc0406b
173 #define FEC_FLASHMAC 0
175 #endif /* CONFIG_M5272 */
177 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
179 * 2048 byte skbufs are allocated. However, alignment requirements
180 * varies between FEC variants. Worst case is 64, so round down by 64.
182 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
183 #define PKT_MINBUF_SIZE 64
185 /* FEC receive acceleration */
186 #define FEC_RACC_IPDIS (1 << 1)
187 #define FEC_RACC_PRODIS (1 << 2)
188 #define FEC_RACC_SHIFT16 BIT(7)
189 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
191 /* MIB Control Register */
192 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
195 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
196 * size bits. Other FEC hardware does not, so we need to take that into
197 * account when setting it.
199 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
200 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
201 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
203 #define OPT_FRAME_SIZE 0
206 /* FEC MII MMFR bits definition */
207 #define FEC_MMFR_ST (1 << 30)
208 #define FEC_MMFR_OP_READ (2 << 28)
209 #define FEC_MMFR_OP_WRITE (1 << 28)
210 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
211 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
212 #define FEC_MMFR_TA (2 << 16)
213 #define FEC_MMFR_DATA(v) (v & 0xffff)
214 /* FEC ECR bits definition */
215 #define FEC_ECR_MAGICEN (1 << 2)
216 #define FEC_ECR_SLEEP (1 << 3)
218 #define FEC_MII_TIMEOUT 30000 /* us */
220 /* Transmitter timeout */
221 #define TX_TIMEOUT (2 * HZ)
223 #define FEC_PAUSE_FLAG_AUTONEG 0x1
224 #define FEC_PAUSE_FLAG_ENABLE 0x2
225 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
226 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
227 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
229 #define COPYBREAK_DEFAULT 256
231 /* Max number of allowed TCP segments for software TSO */
232 #define FEC_MAX_TSO_SEGS 100
233 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
235 #define IS_TSO_HEADER(txq, addr) \
236 ((addr >= txq->tso_hdrs_dma) && \
237 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
241 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
242 struct bufdesc_prop *bd)
244 return (bdp >= bd->last) ? bd->base
245 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
248 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
249 struct bufdesc_prop *bd)
251 return (bdp <= bd->base) ? bd->last
252 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
255 static int fec_enet_get_bd_index(struct bufdesc *bdp,
256 struct bufdesc_prop *bd)
258 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
261 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
265 entries = (((const char *)txq->dirty_tx -
266 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
268 return entries >= 0 ? entries : entries + txq->bd.ring_size;
271 static void swap_buffer(void *bufaddr, int len)
274 unsigned int *buf = bufaddr;
276 for (i = 0; i < len; i += 4, buf++)
280 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
283 unsigned int *src = src_buf;
284 unsigned int *dst = dst_buf;
286 for (i = 0; i < len; i += 4, src++, dst++)
290 static void fec_dump(struct net_device *ndev)
292 struct fec_enet_private *fep = netdev_priv(ndev);
294 struct fec_enet_priv_tx_q *txq;
297 netdev_info(ndev, "TX ring dump\n");
298 pr_info("Nr SC addr len SKB\n");
300 txq = fep->tx_queue[0];
304 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
306 bdp == txq->bd.cur ? 'S' : ' ',
307 bdp == txq->dirty_tx ? 'H' : ' ',
308 fec16_to_cpu(bdp->cbd_sc),
309 fec32_to_cpu(bdp->cbd_bufaddr),
310 fec16_to_cpu(bdp->cbd_datlen),
311 txq->tx_skbuff[index]);
312 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
314 } while (bdp != txq->bd.base);
317 static inline bool is_ipv4_pkt(struct sk_buff *skb)
319 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
323 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
325 /* Only run for packets requiring a checksum. */
326 if (skb->ip_summed != CHECKSUM_PARTIAL)
329 if (unlikely(skb_cow_head(skb, 0)))
332 if (is_ipv4_pkt(skb))
333 ip_hdr(skb)->check = 0;
334 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
339 static struct bufdesc *
340 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
342 struct net_device *ndev)
344 struct fec_enet_private *fep = netdev_priv(ndev);
345 struct bufdesc *bdp = txq->bd.cur;
346 struct bufdesc_ex *ebdp;
347 int nr_frags = skb_shinfo(skb)->nr_frags;
349 unsigned short status;
350 unsigned int estatus = 0;
351 skb_frag_t *this_frag;
357 for (frag = 0; frag < nr_frags; frag++) {
358 this_frag = &skb_shinfo(skb)->frags[frag];
359 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
360 ebdp = (struct bufdesc_ex *)bdp;
362 status = fec16_to_cpu(bdp->cbd_sc);
363 status &= ~BD_ENET_TX_STATS;
364 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
365 frag_len = skb_shinfo(skb)->frags[frag].size;
367 /* Handle the last BD specially */
368 if (frag == nr_frags - 1) {
369 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
370 if (fep->bufdesc_ex) {
371 estatus |= BD_ENET_TX_INT;
372 if (unlikely(skb_shinfo(skb)->tx_flags &
373 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
374 estatus |= BD_ENET_TX_TS;
378 if (fep->bufdesc_ex) {
379 if (fep->quirks & FEC_QUIRK_HAS_AVB)
380 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
381 if (skb->ip_summed == CHECKSUM_PARTIAL)
382 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
384 ebdp->cbd_esc = cpu_to_fec32(estatus);
387 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
389 index = fec_enet_get_bd_index(bdp, &txq->bd);
390 if (((unsigned long) bufaddr) & fep->tx_align ||
391 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
392 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
393 bufaddr = txq->tx_bounce[index];
395 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
396 swap_buffer(bufaddr, frag_len);
399 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
401 if (dma_mapping_error(&fep->pdev->dev, addr)) {
403 netdev_err(ndev, "Tx DMA memory map failed\n");
404 goto dma_mapping_error;
407 bdp->cbd_bufaddr = cpu_to_fec32(addr);
408 bdp->cbd_datlen = cpu_to_fec16(frag_len);
409 /* Make sure the updates to rest of the descriptor are
410 * performed before transferring ownership.
413 bdp->cbd_sc = cpu_to_fec16(status);
419 for (i = 0; i < frag; i++) {
420 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
421 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
422 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
424 return ERR_PTR(-ENOMEM);
427 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
428 struct sk_buff *skb, struct net_device *ndev)
430 struct fec_enet_private *fep = netdev_priv(ndev);
431 int nr_frags = skb_shinfo(skb)->nr_frags;
432 struct bufdesc *bdp, *last_bdp;
435 unsigned short status;
436 unsigned short buflen;
437 unsigned int estatus = 0;
441 entries_free = fec_enet_get_free_txdesc_num(txq);
442 if (entries_free < MAX_SKB_FRAGS + 1) {
443 dev_kfree_skb_any(skb);
445 netdev_err(ndev, "NOT enough BD for SG!\n");
449 /* Protocol checksum off-load for TCP and UDP. */
450 if (fec_enet_clear_csum(skb, ndev)) {
451 dev_kfree_skb_any(skb);
455 /* Fill in a Tx ring entry */
458 status = fec16_to_cpu(bdp->cbd_sc);
459 status &= ~BD_ENET_TX_STATS;
461 /* Set buffer length and buffer pointer */
463 buflen = skb_headlen(skb);
465 index = fec_enet_get_bd_index(bdp, &txq->bd);
466 if (((unsigned long) bufaddr) & fep->tx_align ||
467 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
468 memcpy(txq->tx_bounce[index], skb->data, buflen);
469 bufaddr = txq->tx_bounce[index];
471 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
472 swap_buffer(bufaddr, buflen);
475 /* Push the data cache so the CPM does not get stale memory data. */
476 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
477 if (dma_mapping_error(&fep->pdev->dev, addr)) {
478 dev_kfree_skb_any(skb);
480 netdev_err(ndev, "Tx DMA memory map failed\n");
485 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
486 if (IS_ERR(last_bdp)) {
487 dma_unmap_single(&fep->pdev->dev, addr,
488 buflen, DMA_TO_DEVICE);
489 dev_kfree_skb_any(skb);
493 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
494 if (fep->bufdesc_ex) {
495 estatus = BD_ENET_TX_INT;
496 if (unlikely(skb_shinfo(skb)->tx_flags &
497 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
498 estatus |= BD_ENET_TX_TS;
501 bdp->cbd_bufaddr = cpu_to_fec32(addr);
502 bdp->cbd_datlen = cpu_to_fec16(buflen);
504 if (fep->bufdesc_ex) {
506 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
508 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
510 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
512 if (fep->quirks & FEC_QUIRK_HAS_AVB)
513 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
515 if (skb->ip_summed == CHECKSUM_PARTIAL)
516 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
519 ebdp->cbd_esc = cpu_to_fec32(estatus);
522 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
523 /* Save skb pointer */
524 txq->tx_skbuff[index] = skb;
526 /* Make sure the updates to rest of the descriptor are performed before
527 * transferring ownership.
531 /* Send it on its way. Tell FEC it's ready, interrupt when done,
532 * it's the last BD of the frame, and to put the CRC on the end.
534 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
535 bdp->cbd_sc = cpu_to_fec16(status);
537 /* If this was the last BD in the ring, start at the beginning again. */
538 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
540 skb_tx_timestamp(skb);
542 /* Make sure the update to bdp and tx_skbuff are performed before
548 /* Trigger transmission start */
549 writel(0, txq->bd.reg_desc_active);
555 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
556 struct net_device *ndev,
557 struct bufdesc *bdp, int index, char *data,
558 int size, bool last_tcp, bool is_last)
560 struct fec_enet_private *fep = netdev_priv(ndev);
561 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
562 unsigned short status;
563 unsigned int estatus = 0;
566 status = fec16_to_cpu(bdp->cbd_sc);
567 status &= ~BD_ENET_TX_STATS;
569 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
571 if (((unsigned long) data) & fep->tx_align ||
572 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
573 memcpy(txq->tx_bounce[index], data, size);
574 data = txq->tx_bounce[index];
576 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
577 swap_buffer(data, size);
580 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
581 if (dma_mapping_error(&fep->pdev->dev, addr)) {
582 dev_kfree_skb_any(skb);
584 netdev_err(ndev, "Tx DMA memory map failed\n");
585 return NETDEV_TX_BUSY;
588 bdp->cbd_datlen = cpu_to_fec16(size);
589 bdp->cbd_bufaddr = cpu_to_fec32(addr);
591 if (fep->bufdesc_ex) {
592 if (fep->quirks & FEC_QUIRK_HAS_AVB)
593 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
594 if (skb->ip_summed == CHECKSUM_PARTIAL)
595 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
597 ebdp->cbd_esc = cpu_to_fec32(estatus);
600 /* Handle the last BD specially */
602 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
604 status |= BD_ENET_TX_INTR;
606 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
609 bdp->cbd_sc = cpu_to_fec16(status);
615 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
616 struct sk_buff *skb, struct net_device *ndev,
617 struct bufdesc *bdp, int index)
619 struct fec_enet_private *fep = netdev_priv(ndev);
620 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
621 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
623 unsigned long dmabuf;
624 unsigned short status;
625 unsigned int estatus = 0;
627 status = fec16_to_cpu(bdp->cbd_sc);
628 status &= ~BD_ENET_TX_STATS;
629 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
631 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
632 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
633 if (((unsigned long)bufaddr) & fep->tx_align ||
634 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
635 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
636 bufaddr = txq->tx_bounce[index];
638 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
639 swap_buffer(bufaddr, hdr_len);
641 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
642 hdr_len, DMA_TO_DEVICE);
643 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
644 dev_kfree_skb_any(skb);
646 netdev_err(ndev, "Tx DMA memory map failed\n");
647 return NETDEV_TX_BUSY;
651 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
652 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
654 if (fep->bufdesc_ex) {
655 if (fep->quirks & FEC_QUIRK_HAS_AVB)
656 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
657 if (skb->ip_summed == CHECKSUM_PARTIAL)
658 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
660 ebdp->cbd_esc = cpu_to_fec32(estatus);
663 bdp->cbd_sc = cpu_to_fec16(status);
668 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
670 struct net_device *ndev)
672 struct fec_enet_private *fep = netdev_priv(ndev);
673 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
674 int total_len, data_left;
675 struct bufdesc *bdp = txq->bd.cur;
677 unsigned int index = 0;
680 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
681 dev_kfree_skb_any(skb);
683 netdev_err(ndev, "NOT enough BD for TSO!\n");
687 /* Protocol checksum off-load for TCP and UDP. */
688 if (fec_enet_clear_csum(skb, ndev)) {
689 dev_kfree_skb_any(skb);
693 /* Initialize the TSO handler, and prepare the first payload */
694 tso_start(skb, &tso);
696 total_len = skb->len - hdr_len;
697 while (total_len > 0) {
700 index = fec_enet_get_bd_index(bdp, &txq->bd);
701 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
702 total_len -= data_left;
704 /* prepare packet headers: MAC + IP + TCP */
705 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
706 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
707 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
711 while (data_left > 0) {
714 size = min_t(int, tso.size, data_left);
715 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
716 index = fec_enet_get_bd_index(bdp, &txq->bd);
717 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
726 tso_build_data(skb, &tso, size);
729 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
732 /* Save skb pointer */
733 txq->tx_skbuff[index] = skb;
735 skb_tx_timestamp(skb);
738 /* Trigger transmission start */
739 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
740 !readl(txq->bd.reg_desc_active) ||
741 !readl(txq->bd.reg_desc_active) ||
742 !readl(txq->bd.reg_desc_active) ||
743 !readl(txq->bd.reg_desc_active))
744 writel(0, txq->bd.reg_desc_active);
749 /* TODO: Release all used data descriptors for TSO */
754 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
756 struct fec_enet_private *fep = netdev_priv(ndev);
758 unsigned short queue;
759 struct fec_enet_priv_tx_q *txq;
760 struct netdev_queue *nq;
763 queue = skb_get_queue_mapping(skb);
764 txq = fep->tx_queue[queue];
765 nq = netdev_get_tx_queue(ndev, queue);
768 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
770 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
774 entries_free = fec_enet_get_free_txdesc_num(txq);
775 if (entries_free <= txq->tx_stop_threshold)
776 netif_tx_stop_queue(nq);
781 /* Init RX & TX buffer descriptors
783 static void fec_enet_bd_init(struct net_device *dev)
785 struct fec_enet_private *fep = netdev_priv(dev);
786 struct fec_enet_priv_tx_q *txq;
787 struct fec_enet_priv_rx_q *rxq;
792 for (q = 0; q < fep->num_rx_queues; q++) {
793 /* Initialize the receive buffer descriptors. */
794 rxq = fep->rx_queue[q];
797 for (i = 0; i < rxq->bd.ring_size; i++) {
799 /* Initialize the BD for every fragment in the page. */
800 if (bdp->cbd_bufaddr)
801 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
803 bdp->cbd_sc = cpu_to_fec16(0);
804 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
807 /* Set the last buffer to wrap */
808 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
809 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
811 rxq->bd.cur = rxq->bd.base;
814 for (q = 0; q < fep->num_tx_queues; q++) {
815 /* ...and the same for transmit */
816 txq = fep->tx_queue[q];
820 for (i = 0; i < txq->bd.ring_size; i++) {
821 /* Initialize the BD for every fragment in the page. */
822 bdp->cbd_sc = cpu_to_fec16(0);
823 if (bdp->cbd_bufaddr &&
824 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
825 dma_unmap_single(&fep->pdev->dev,
826 fec32_to_cpu(bdp->cbd_bufaddr),
827 fec16_to_cpu(bdp->cbd_datlen),
829 if (txq->tx_skbuff[i]) {
830 dev_kfree_skb_any(txq->tx_skbuff[i]);
831 txq->tx_skbuff[i] = NULL;
833 bdp->cbd_bufaddr = cpu_to_fec32(0);
834 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
837 /* Set the last buffer to wrap */
838 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
839 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
844 static void fec_enet_active_rxring(struct net_device *ndev)
846 struct fec_enet_private *fep = netdev_priv(ndev);
849 for (i = 0; i < fep->num_rx_queues; i++)
850 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
853 static void fec_enet_enable_ring(struct net_device *ndev)
855 struct fec_enet_private *fep = netdev_priv(ndev);
856 struct fec_enet_priv_tx_q *txq;
857 struct fec_enet_priv_rx_q *rxq;
860 for (i = 0; i < fep->num_rx_queues; i++) {
861 rxq = fep->rx_queue[i];
862 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
863 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
867 writel(RCMR_MATCHEN | RCMR_CMP(i),
868 fep->hwp + FEC_RCMR(i));
871 for (i = 0; i < fep->num_tx_queues; i++) {
872 txq = fep->tx_queue[i];
873 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
877 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
878 fep->hwp + FEC_DMA_CFG(i));
882 static void fec_enet_reset_skb(struct net_device *ndev)
884 struct fec_enet_private *fep = netdev_priv(ndev);
885 struct fec_enet_priv_tx_q *txq;
888 for (i = 0; i < fep->num_tx_queues; i++) {
889 txq = fep->tx_queue[i];
891 for (j = 0; j < txq->bd.ring_size; j++) {
892 if (txq->tx_skbuff[j]) {
893 dev_kfree_skb_any(txq->tx_skbuff[j]);
894 txq->tx_skbuff[j] = NULL;
901 * This function is called to start or restart the FEC during a link
902 * change, transmit timeout, or to reconfigure the FEC. The network
903 * packet processing for this device must be stopped before this call.
906 fec_restart(struct net_device *ndev)
908 struct fec_enet_private *fep = netdev_priv(ndev);
911 u32 rcntl = OPT_FRAME_SIZE | 0x04;
912 u32 ecntl = 0x2; /* ETHEREN */
914 /* Whack a reset. We should wait for this.
915 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
916 * instead of reset MAC itself.
918 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
919 writel(0, fep->hwp + FEC_ECNTRL);
921 writel(1, fep->hwp + FEC_ECNTRL);
926 * enet-mac reset will reset mac address registers too,
927 * so need to reconfigure it.
929 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
930 writel((__force u32)cpu_to_be32(temp_mac[0]),
931 fep->hwp + FEC_ADDR_LOW);
932 writel((__force u32)cpu_to_be32(temp_mac[1]),
933 fep->hwp + FEC_ADDR_HIGH);
935 /* Clear any outstanding interrupt. */
936 writel(0xffffffff, fep->hwp + FEC_IEVENT);
938 fec_enet_bd_init(ndev);
940 fec_enet_enable_ring(ndev);
942 /* Reset tx SKB buffers. */
943 fec_enet_reset_skb(ndev);
945 /* Enable MII mode */
946 if (fep->full_duplex == DUPLEX_FULL) {
948 writel(0x04, fep->hwp + FEC_X_CNTRL);
952 writel(0x0, fep->hwp + FEC_X_CNTRL);
956 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
958 #if !defined(CONFIG_M5272)
959 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
960 val = readl(fep->hwp + FEC_RACC);
961 /* align IP header */
962 val |= FEC_RACC_SHIFT16;
963 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
964 /* set RX checksum */
965 val |= FEC_RACC_OPTIONS;
967 val &= ~FEC_RACC_OPTIONS;
968 writel(val, fep->hwp + FEC_RACC);
969 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
974 * The phy interface and speed need to get configured
975 * differently on enet-mac.
977 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
978 /* Enable flow control and length check */
979 rcntl |= 0x40000000 | 0x00000020;
981 /* RGMII, RMII or MII */
982 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
983 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
984 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
985 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
987 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
992 /* 1G, 100M or 10M */
994 if (ndev->phydev->speed == SPEED_1000)
996 else if (ndev->phydev->speed == SPEED_100)
1002 #ifdef FEC_MIIGSK_ENR
1003 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1005 /* disable the gasket and wait */
1006 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1007 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1011 * configure the gasket:
1012 * RMII, 50 MHz, no loopback, no echo
1013 * MII, 25 MHz, no loopback, no echo
1015 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1016 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1017 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1018 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1019 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1021 /* re-enable the gasket */
1022 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1027 #if !defined(CONFIG_M5272)
1028 /* enable pause frame*/
1029 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1030 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1031 ndev->phydev && ndev->phydev->pause)) {
1032 rcntl |= FEC_ENET_FCE;
1034 /* set FIFO threshold parameter to reduce overrun */
1035 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1036 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1037 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1038 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1041 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1043 rcntl &= ~FEC_ENET_FCE;
1045 #endif /* !defined(CONFIG_M5272) */
1047 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1049 /* Setup multicast filter. */
1050 set_multicast_list(ndev);
1051 #ifndef CONFIG_M5272
1052 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1053 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1056 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1057 /* enable ENET endian swap */
1059 /* enable ENET store and forward mode */
1060 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1063 if (fep->bufdesc_ex)
1066 #ifndef CONFIG_M5272
1067 /* Enable the MIB statistic event counters */
1068 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1071 /* And last, enable the transmit and receive processing */
1072 writel(ecntl, fep->hwp + FEC_ECNTRL);
1073 fec_enet_active_rxring(ndev);
1075 if (fep->bufdesc_ex)
1076 fec_ptp_start_cyclecounter(ndev);
1078 /* Enable interrupts we wish to service */
1080 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1082 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1084 /* Init the interrupt coalescing */
1085 fec_enet_itr_coal_init(ndev);
1090 fec_stop(struct net_device *ndev)
1092 struct fec_enet_private *fep = netdev_priv(ndev);
1093 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1094 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1097 /* We cannot expect a graceful transmit stop without link !!! */
1099 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1101 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1102 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1105 /* Whack a reset. We should wait for this.
1106 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1107 * instead of reset MAC itself.
1109 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1110 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1111 writel(0, fep->hwp + FEC_ECNTRL);
1113 writel(1, fep->hwp + FEC_ECNTRL);
1116 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1118 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1119 val = readl(fep->hwp + FEC_ECNTRL);
1120 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1121 writel(val, fep->hwp + FEC_ECNTRL);
1123 if (pdata && pdata->sleep_mode_enable)
1124 pdata->sleep_mode_enable(true);
1126 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1128 /* We have to keep ENET enabled to have MII interrupt stay working */
1129 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1130 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1131 writel(2, fep->hwp + FEC_ECNTRL);
1132 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1138 fec_timeout(struct net_device *ndev)
1140 struct fec_enet_private *fep = netdev_priv(ndev);
1144 ndev->stats.tx_errors++;
1146 schedule_work(&fep->tx_timeout_work);
1149 static void fec_enet_timeout_work(struct work_struct *work)
1151 struct fec_enet_private *fep =
1152 container_of(work, struct fec_enet_private, tx_timeout_work);
1153 struct net_device *ndev = fep->netdev;
1156 if (netif_device_present(ndev) || netif_running(ndev)) {
1157 napi_disable(&fep->napi);
1158 netif_tx_lock_bh(ndev);
1160 netif_tx_wake_all_queues(ndev);
1161 netif_tx_unlock_bh(ndev);
1162 napi_enable(&fep->napi);
1168 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1169 struct skb_shared_hwtstamps *hwtstamps)
1171 unsigned long flags;
1174 spin_lock_irqsave(&fep->tmreg_lock, flags);
1175 ns = timecounter_cyc2time(&fep->tc, ts);
1176 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1178 memset(hwtstamps, 0, sizeof(*hwtstamps));
1179 hwtstamps->hwtstamp = ns_to_ktime(ns);
1183 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1185 struct fec_enet_private *fep;
1186 struct bufdesc *bdp;
1187 unsigned short status;
1188 struct sk_buff *skb;
1189 struct fec_enet_priv_tx_q *txq;
1190 struct netdev_queue *nq;
1194 fep = netdev_priv(ndev);
1196 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1198 txq = fep->tx_queue[queue_id];
1199 /* get next bdp of dirty_tx */
1200 nq = netdev_get_tx_queue(ndev, queue_id);
1201 bdp = txq->dirty_tx;
1203 /* get next bdp of dirty_tx */
1204 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1206 while (bdp != READ_ONCE(txq->bd.cur)) {
1207 /* Order the load of bd.cur and cbd_sc */
1209 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1210 if (status & BD_ENET_TX_READY)
1213 index = fec_enet_get_bd_index(bdp, &txq->bd);
1215 skb = txq->tx_skbuff[index];
1216 txq->tx_skbuff[index] = NULL;
1217 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1218 dma_unmap_single(&fep->pdev->dev,
1219 fec32_to_cpu(bdp->cbd_bufaddr),
1220 fec16_to_cpu(bdp->cbd_datlen),
1222 bdp->cbd_bufaddr = cpu_to_fec32(0);
1226 /* Check for errors. */
1227 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1228 BD_ENET_TX_RL | BD_ENET_TX_UN |
1230 ndev->stats.tx_errors++;
1231 if (status & BD_ENET_TX_HB) /* No heartbeat */
1232 ndev->stats.tx_heartbeat_errors++;
1233 if (status & BD_ENET_TX_LC) /* Late collision */
1234 ndev->stats.tx_window_errors++;
1235 if (status & BD_ENET_TX_RL) /* Retrans limit */
1236 ndev->stats.tx_aborted_errors++;
1237 if (status & BD_ENET_TX_UN) /* Underrun */
1238 ndev->stats.tx_fifo_errors++;
1239 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1240 ndev->stats.tx_carrier_errors++;
1242 ndev->stats.tx_packets++;
1243 ndev->stats.tx_bytes += skb->len;
1246 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1248 struct skb_shared_hwtstamps shhwtstamps;
1249 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1251 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1252 skb_tstamp_tx(skb, &shhwtstamps);
1255 /* Deferred means some collisions occurred during transmit,
1256 * but we eventually sent the packet OK.
1258 if (status & BD_ENET_TX_DEF)
1259 ndev->stats.collisions++;
1261 /* Free the sk buffer associated with this last transmit */
1262 dev_kfree_skb_any(skb);
1264 /* Make sure the update to bdp and tx_skbuff are performed
1268 txq->dirty_tx = bdp;
1270 /* Update pointer to next buffer descriptor to be transmitted */
1271 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1273 /* Since we have freed up a buffer, the ring is no longer full
1275 if (netif_tx_queue_stopped(nq)) {
1276 entries_free = fec_enet_get_free_txdesc_num(txq);
1277 if (entries_free >= txq->tx_wake_threshold)
1278 netif_tx_wake_queue(nq);
1282 /* ERR006358: Keep the transmitter going */
1283 if (bdp != txq->bd.cur &&
1284 readl(txq->bd.reg_desc_active) == 0)
1285 writel(0, txq->bd.reg_desc_active);
1289 fec_enet_tx(struct net_device *ndev)
1291 struct fec_enet_private *fep = netdev_priv(ndev);
1293 /* First process class A queue, then Class B and Best Effort queue */
1294 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1295 clear_bit(queue_id, &fep->work_tx);
1296 fec_enet_tx_queue(ndev, queue_id);
1302 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1304 struct fec_enet_private *fep = netdev_priv(ndev);
1307 off = ((unsigned long)skb->data) & fep->rx_align;
1309 skb_reserve(skb, fep->rx_align + 1 - off);
1311 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1312 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1313 if (net_ratelimit())
1314 netdev_err(ndev, "Rx DMA memory map failed\n");
1321 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1322 struct bufdesc *bdp, u32 length, bool swap)
1324 struct fec_enet_private *fep = netdev_priv(ndev);
1325 struct sk_buff *new_skb;
1327 if (length > fep->rx_copybreak)
1330 new_skb = netdev_alloc_skb(ndev, length);
1334 dma_sync_single_for_cpu(&fep->pdev->dev,
1335 fec32_to_cpu(bdp->cbd_bufaddr),
1336 FEC_ENET_RX_FRSIZE - fep->rx_align,
1339 memcpy(new_skb->data, (*skb)->data, length);
1341 swap_buffer2(new_skb->data, (*skb)->data, length);
1347 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1348 * When we update through the ring, if the next incoming buffer has
1349 * not been given to the system, we just set the empty indicator,
1350 * effectively tossing the packet.
1353 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1355 struct fec_enet_private *fep = netdev_priv(ndev);
1356 struct fec_enet_priv_rx_q *rxq;
1357 struct bufdesc *bdp;
1358 unsigned short status;
1359 struct sk_buff *skb_new = NULL;
1360 struct sk_buff *skb;
1363 int pkt_received = 0;
1364 struct bufdesc_ex *ebdp = NULL;
1365 bool vlan_packet_rcvd = false;
1369 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1374 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1375 rxq = fep->rx_queue[queue_id];
1377 /* First, grab all of the stats for the incoming packet.
1378 * These get messed up if we get called due to a busy condition.
1382 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1384 if (pkt_received >= budget)
1388 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1390 /* Check for errors. */
1391 status ^= BD_ENET_RX_LAST;
1392 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1393 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1395 ndev->stats.rx_errors++;
1396 if (status & BD_ENET_RX_OV) {
1398 ndev->stats.rx_fifo_errors++;
1399 goto rx_processing_done;
1401 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1402 | BD_ENET_RX_LAST)) {
1403 /* Frame too long or too short. */
1404 ndev->stats.rx_length_errors++;
1405 if (status & BD_ENET_RX_LAST)
1406 netdev_err(ndev, "rcv is not +last\n");
1408 if (status & BD_ENET_RX_CR) /* CRC Error */
1409 ndev->stats.rx_crc_errors++;
1410 /* Report late collisions as a frame error. */
1411 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1412 ndev->stats.rx_frame_errors++;
1413 goto rx_processing_done;
1416 /* Process the incoming frame. */
1417 ndev->stats.rx_packets++;
1418 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1419 ndev->stats.rx_bytes += pkt_len;
1421 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1422 skb = rxq->rx_skbuff[index];
1424 /* The packet length includes FCS, but we don't want to
1425 * include that when passing upstream as it messes up
1426 * bridging applications.
1428 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1430 if (!is_copybreak) {
1431 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1432 if (unlikely(!skb_new)) {
1433 ndev->stats.rx_dropped++;
1434 goto rx_processing_done;
1436 dma_unmap_single(&fep->pdev->dev,
1437 fec32_to_cpu(bdp->cbd_bufaddr),
1438 FEC_ENET_RX_FRSIZE - fep->rx_align,
1442 prefetch(skb->data - NET_IP_ALIGN);
1443 skb_put(skb, pkt_len - 4);
1446 if (!is_copybreak && need_swap)
1447 swap_buffer(data, pkt_len);
1449 #if !defined(CONFIG_M5272)
1450 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1451 data = skb_pull_inline(skb, 2);
1454 /* Extract the enhanced buffer descriptor */
1456 if (fep->bufdesc_ex)
1457 ebdp = (struct bufdesc_ex *)bdp;
1459 /* If this is a VLAN packet remove the VLAN Tag */
1460 vlan_packet_rcvd = false;
1461 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1463 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1464 /* Push and remove the vlan tag */
1465 struct vlan_hdr *vlan_header =
1466 (struct vlan_hdr *) (data + ETH_HLEN);
1467 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1469 vlan_packet_rcvd = true;
1471 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1472 skb_pull(skb, VLAN_HLEN);
1475 skb->protocol = eth_type_trans(skb, ndev);
1477 /* Get receive timestamp from the skb */
1478 if (fep->hwts_rx_en && fep->bufdesc_ex)
1479 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1480 skb_hwtstamps(skb));
1482 if (fep->bufdesc_ex &&
1483 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1484 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1485 /* don't check it */
1486 skb->ip_summed = CHECKSUM_UNNECESSARY;
1488 skb_checksum_none_assert(skb);
1492 /* Handle received VLAN packets */
1493 if (vlan_packet_rcvd)
1494 __vlan_hwaccel_put_tag(skb,
1498 napi_gro_receive(&fep->napi, skb);
1501 dma_sync_single_for_device(&fep->pdev->dev,
1502 fec32_to_cpu(bdp->cbd_bufaddr),
1503 FEC_ENET_RX_FRSIZE - fep->rx_align,
1506 rxq->rx_skbuff[index] = skb_new;
1507 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1511 /* Clear the status flags for this buffer */
1512 status &= ~BD_ENET_RX_STATS;
1514 /* Mark the buffer empty */
1515 status |= BD_ENET_RX_EMPTY;
1517 if (fep->bufdesc_ex) {
1518 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1520 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1524 /* Make sure the updates to rest of the descriptor are
1525 * performed before transferring ownership.
1528 bdp->cbd_sc = cpu_to_fec16(status);
1530 /* Update BD pointer to next entry */
1531 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1533 /* Doing this here will keep the FEC running while we process
1534 * incoming frames. On a heavily loaded network, we should be
1535 * able to keep up at the expense of system resources.
1537 writel(0, rxq->bd.reg_desc_active);
1540 return pkt_received;
1544 fec_enet_rx(struct net_device *ndev, int budget)
1546 int pkt_received = 0;
1548 struct fec_enet_private *fep = netdev_priv(ndev);
1550 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1553 ret = fec_enet_rx_queue(ndev,
1554 budget - pkt_received, queue_id);
1556 if (ret < budget - pkt_received)
1557 clear_bit(queue_id, &fep->work_rx);
1559 pkt_received += ret;
1561 return pkt_received;
1565 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1567 if (int_events == 0)
1570 if (int_events & FEC_ENET_RXF_0)
1571 fep->work_rx |= (1 << 2);
1572 if (int_events & FEC_ENET_RXF_1)
1573 fep->work_rx |= (1 << 0);
1574 if (int_events & FEC_ENET_RXF_2)
1575 fep->work_rx |= (1 << 1);
1577 if (int_events & FEC_ENET_TXF_0)
1578 fep->work_tx |= (1 << 2);
1579 if (int_events & FEC_ENET_TXF_1)
1580 fep->work_tx |= (1 << 0);
1581 if (int_events & FEC_ENET_TXF_2)
1582 fep->work_tx |= (1 << 1);
1588 fec_enet_interrupt(int irq, void *dev_id)
1590 struct net_device *ndev = dev_id;
1591 struct fec_enet_private *fep = netdev_priv(ndev);
1593 irqreturn_t ret = IRQ_NONE;
1595 int_events = readl(fep->hwp + FEC_IEVENT);
1596 writel(int_events, fep->hwp + FEC_IEVENT);
1597 fec_enet_collect_events(fep, int_events);
1599 if ((fep->work_tx || fep->work_rx) && fep->link) {
1602 if (napi_schedule_prep(&fep->napi)) {
1603 /* Disable the NAPI interrupts */
1604 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1605 __napi_schedule(&fep->napi);
1609 if (int_events & FEC_ENET_MII) {
1611 complete(&fep->mdio_done);
1615 if (fec_ptp_check_pps_event(fep))
1620 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1622 struct net_device *ndev = napi->dev;
1623 struct fec_enet_private *fep = netdev_priv(ndev);
1626 pkts = fec_enet_rx(ndev, budget);
1630 if (pkts < budget) {
1631 napi_complete_done(napi, pkts);
1632 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1637 /* ------------------------------------------------------------------------- */
1638 static void fec_get_mac(struct net_device *ndev)
1640 struct fec_enet_private *fep = netdev_priv(ndev);
1641 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1642 unsigned char *iap, tmpaddr[ETH_ALEN];
1645 * try to get mac address in following order:
1647 * 1) module parameter via kernel command line in form
1648 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1653 * 2) from device tree data
1655 if (!is_valid_ether_addr(iap)) {
1656 struct device_node *np = fep->pdev->dev.of_node;
1658 const char *mac = of_get_mac_address(np);
1660 iap = (unsigned char *) mac;
1665 * 3) from flash or fuse (via platform data)
1667 if (!is_valid_ether_addr(iap)) {
1670 iap = (unsigned char *)FEC_FLASHMAC;
1673 iap = (unsigned char *)&pdata->mac;
1678 * 4) FEC mac registers set by bootloader
1680 if (!is_valid_ether_addr(iap)) {
1681 *((__be32 *) &tmpaddr[0]) =
1682 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1683 *((__be16 *) &tmpaddr[4]) =
1684 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1689 * 5) random mac address
1691 if (!is_valid_ether_addr(iap)) {
1692 /* Report it and use a random ethernet address instead */
1693 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1694 eth_hw_addr_random(ndev);
1695 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1700 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1702 /* Adjust MAC if using macaddr */
1704 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1707 /* ------------------------------------------------------------------------- */
1712 static void fec_enet_adjust_link(struct net_device *ndev)
1714 struct fec_enet_private *fep = netdev_priv(ndev);
1715 struct phy_device *phy_dev = ndev->phydev;
1716 int status_change = 0;
1718 /* Prevent a state halted on mii error */
1719 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1720 phy_dev->state = PHY_RESUMING;
1725 * If the netdev is down, or is going down, we're not interested
1726 * in link state events, so just mark our idea of the link as down
1727 * and ignore the event.
1729 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1731 } else if (phy_dev->link) {
1733 fep->link = phy_dev->link;
1737 if (fep->full_duplex != phy_dev->duplex) {
1738 fep->full_duplex = phy_dev->duplex;
1742 if (phy_dev->speed != fep->speed) {
1743 fep->speed = phy_dev->speed;
1747 /* if any of the above changed restart the FEC */
1748 if (status_change) {
1749 napi_disable(&fep->napi);
1750 netif_tx_lock_bh(ndev);
1752 netif_tx_wake_all_queues(ndev);
1753 netif_tx_unlock_bh(ndev);
1754 napi_enable(&fep->napi);
1758 napi_disable(&fep->napi);
1759 netif_tx_lock_bh(ndev);
1761 netif_tx_unlock_bh(ndev);
1762 napi_enable(&fep->napi);
1763 fep->link = phy_dev->link;
1769 phy_print_status(phy_dev);
1772 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1774 struct fec_enet_private *fep = bus->priv;
1775 struct device *dev = &fep->pdev->dev;
1776 unsigned long time_left;
1779 ret = pm_runtime_get_sync(dev);
1783 fep->mii_timeout = 0;
1784 reinit_completion(&fep->mdio_done);
1786 /* start a read op */
1787 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1788 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1789 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1791 /* wait for end of transfer */
1792 time_left = wait_for_completion_timeout(&fep->mdio_done,
1793 usecs_to_jiffies(FEC_MII_TIMEOUT));
1794 if (time_left == 0) {
1795 fep->mii_timeout = 1;
1796 netdev_err(fep->netdev, "MDIO read timeout\n");
1801 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1804 pm_runtime_mark_last_busy(dev);
1805 pm_runtime_put_autosuspend(dev);
1810 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1813 struct fec_enet_private *fep = bus->priv;
1814 struct device *dev = &fep->pdev->dev;
1815 unsigned long time_left;
1818 ret = pm_runtime_get_sync(dev);
1824 fep->mii_timeout = 0;
1825 reinit_completion(&fep->mdio_done);
1827 /* start a write op */
1828 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1829 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1830 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1831 fep->hwp + FEC_MII_DATA);
1833 /* wait for end of transfer */
1834 time_left = wait_for_completion_timeout(&fep->mdio_done,
1835 usecs_to_jiffies(FEC_MII_TIMEOUT));
1836 if (time_left == 0) {
1837 fep->mii_timeout = 1;
1838 netdev_err(fep->netdev, "MDIO write timeout\n");
1842 pm_runtime_mark_last_busy(dev);
1843 pm_runtime_put_autosuspend(dev);
1848 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1850 struct fec_enet_private *fep = netdev_priv(ndev);
1854 ret = clk_prepare_enable(fep->clk_enet_out);
1859 mutex_lock(&fep->ptp_clk_mutex);
1860 ret = clk_prepare_enable(fep->clk_ptp);
1862 mutex_unlock(&fep->ptp_clk_mutex);
1863 goto failed_clk_ptp;
1865 fep->ptp_clk_on = true;
1867 mutex_unlock(&fep->ptp_clk_mutex);
1870 ret = clk_prepare_enable(fep->clk_ref);
1872 goto failed_clk_ref;
1874 clk_disable_unprepare(fep->clk_enet_out);
1876 mutex_lock(&fep->ptp_clk_mutex);
1877 clk_disable_unprepare(fep->clk_ptp);
1878 fep->ptp_clk_on = false;
1879 mutex_unlock(&fep->ptp_clk_mutex);
1881 clk_disable_unprepare(fep->clk_ref);
1888 clk_disable_unprepare(fep->clk_ref);
1890 if (fep->clk_enet_out)
1891 clk_disable_unprepare(fep->clk_enet_out);
1896 static int fec_enet_mii_probe(struct net_device *ndev)
1898 struct fec_enet_private *fep = netdev_priv(ndev);
1899 struct phy_device *phy_dev = NULL;
1900 char mdio_bus_id[MII_BUS_ID_SIZE];
1901 char phy_name[MII_BUS_ID_SIZE + 3];
1903 int dev_id = fep->dev_id;
1905 if (fep->phy_node) {
1906 phy_dev = of_phy_connect(ndev, fep->phy_node,
1907 &fec_enet_adjust_link, 0,
1908 fep->phy_interface);
1910 netdev_err(ndev, "Unable to connect to phy\n");
1914 /* check for attached phy */
1915 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1916 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1920 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1924 if (phy_id >= PHY_MAX_ADDR) {
1925 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1926 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1930 snprintf(phy_name, sizeof(phy_name),
1931 PHY_ID_FMT, mdio_bus_id, phy_id);
1932 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1933 fep->phy_interface);
1936 if (IS_ERR(phy_dev)) {
1937 netdev_err(ndev, "could not attach to PHY\n");
1938 return PTR_ERR(phy_dev);
1941 /* mask with MAC supported features */
1942 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1943 phy_dev->supported &= PHY_GBIT_FEATURES;
1944 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1945 #if !defined(CONFIG_M5272)
1946 phy_dev->supported |= SUPPORTED_Pause;
1950 phy_dev->supported &= PHY_BASIC_FEATURES;
1952 phy_dev->advertising = phy_dev->supported;
1955 fep->full_duplex = 0;
1957 phy_attached_info(phy_dev);
1962 static int fec_enet_mii_init(struct platform_device *pdev)
1964 static struct mii_bus *fec0_mii_bus;
1965 struct net_device *ndev = platform_get_drvdata(pdev);
1966 struct fec_enet_private *fep = netdev_priv(ndev);
1967 struct device_node *node;
1969 u32 mii_speed, holdtime;
1972 * The i.MX28 dual fec interfaces are not equal.
1973 * Here are the differences:
1975 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1976 * - fec0 acts as the 1588 time master while fec1 is slave
1977 * - external phys can only be configured by fec0
1979 * That is to say fec1 can not work independently. It only works
1980 * when fec0 is working. The reason behind this design is that the
1981 * second interface is added primarily for Switch mode.
1983 * Because of the last point above, both phys are attached on fec0
1984 * mdio interface in board design, and need to be configured by
1987 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1988 /* fec1 uses fec0 mii_bus */
1989 if (mii_cnt && fec0_mii_bus) {
1990 fep->mii_bus = fec0_mii_bus;
1997 fep->mii_timeout = 0;
2000 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2002 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2003 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2004 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2007 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2008 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2010 if (mii_speed > 63) {
2012 "fec clock (%lu) too fast to get right mii speed\n",
2013 clk_get_rate(fep->clk_ipg));
2019 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2020 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2021 * versions are RAZ there, so just ignore the difference and write the
2023 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2024 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2026 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2027 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2028 * holdtime cannot result in a value greater than 3.
2030 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2032 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2034 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2036 fep->mii_bus = mdiobus_alloc();
2037 if (fep->mii_bus == NULL) {
2042 fep->mii_bus->name = "fec_enet_mii_bus";
2043 fep->mii_bus->read = fec_enet_mdio_read;
2044 fep->mii_bus->write = fec_enet_mdio_write;
2045 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2046 pdev->name, fep->dev_id + 1);
2047 fep->mii_bus->priv = fep;
2048 fep->mii_bus->parent = &pdev->dev;
2050 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2052 err = of_mdiobus_register(fep->mii_bus, node);
2055 err = mdiobus_register(fep->mii_bus);
2059 goto err_out_free_mdiobus;
2063 /* save fec0 mii_bus */
2064 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2065 fec0_mii_bus = fep->mii_bus;
2069 err_out_free_mdiobus:
2070 mdiobus_free(fep->mii_bus);
2075 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2077 if (--mii_cnt == 0) {
2078 mdiobus_unregister(fep->mii_bus);
2079 mdiobus_free(fep->mii_bus);
2083 static void fec_enet_get_drvinfo(struct net_device *ndev,
2084 struct ethtool_drvinfo *info)
2086 struct fec_enet_private *fep = netdev_priv(ndev);
2088 strlcpy(info->driver, fep->pdev->dev.driver->name,
2089 sizeof(info->driver));
2090 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2091 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2094 static int fec_enet_get_regs_len(struct net_device *ndev)
2096 struct fec_enet_private *fep = netdev_priv(ndev);
2100 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2102 s = resource_size(r);
2107 /* List of registers that can be safety be read to dump them with ethtool */
2108 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2109 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2110 static u32 fec_enet_register_offset[] = {
2111 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2112 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2113 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2114 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2115 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2116 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2117 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2118 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2119 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2120 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2121 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2122 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2123 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2124 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2125 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2126 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2127 RMON_T_P_GTE2048, RMON_T_OCTETS,
2128 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2129 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2130 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2131 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2132 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2133 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2134 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2135 RMON_R_P_GTE2048, RMON_R_OCTETS,
2136 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2137 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2140 static u32 fec_enet_register_offset[] = {
2141 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2142 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2143 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2144 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2145 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2146 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2147 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2148 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2149 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2153 static void fec_enet_get_regs(struct net_device *ndev,
2154 struct ethtool_regs *regs, void *regbuf)
2156 struct fec_enet_private *fep = netdev_priv(ndev);
2157 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2158 u32 *buf = (u32 *)regbuf;
2161 memset(buf, 0, regs->len);
2163 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2164 off = fec_enet_register_offset[i];
2166 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2167 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2171 buf[off] = readl(&theregs[off]);
2175 static int fec_enet_get_ts_info(struct net_device *ndev,
2176 struct ethtool_ts_info *info)
2178 struct fec_enet_private *fep = netdev_priv(ndev);
2180 if (fep->bufdesc_ex) {
2182 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2183 SOF_TIMESTAMPING_RX_SOFTWARE |
2184 SOF_TIMESTAMPING_SOFTWARE |
2185 SOF_TIMESTAMPING_TX_HARDWARE |
2186 SOF_TIMESTAMPING_RX_HARDWARE |
2187 SOF_TIMESTAMPING_RAW_HARDWARE;
2189 info->phc_index = ptp_clock_index(fep->ptp_clock);
2191 info->phc_index = -1;
2193 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2194 (1 << HWTSTAMP_TX_ON);
2196 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2197 (1 << HWTSTAMP_FILTER_ALL);
2200 return ethtool_op_get_ts_info(ndev, info);
2204 #if !defined(CONFIG_M5272)
2206 static void fec_enet_get_pauseparam(struct net_device *ndev,
2207 struct ethtool_pauseparam *pause)
2209 struct fec_enet_private *fep = netdev_priv(ndev);
2211 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2212 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2213 pause->rx_pause = pause->tx_pause;
2216 static int fec_enet_set_pauseparam(struct net_device *ndev,
2217 struct ethtool_pauseparam *pause)
2219 struct fec_enet_private *fep = netdev_priv(ndev);
2224 if (pause->tx_pause != pause->rx_pause) {
2226 "hardware only support enable/disable both tx and rx");
2230 fep->pause_flag = 0;
2232 /* tx pause must be same as rx pause */
2233 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2234 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2236 if (pause->rx_pause || pause->autoneg) {
2237 ndev->phydev->supported |= ADVERTISED_Pause;
2238 ndev->phydev->advertising |= ADVERTISED_Pause;
2240 ndev->phydev->supported &= ~ADVERTISED_Pause;
2241 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2244 if (pause->autoneg) {
2245 if (netif_running(ndev))
2247 phy_start_aneg(ndev->phydev);
2249 if (netif_running(ndev)) {
2250 napi_disable(&fep->napi);
2251 netif_tx_lock_bh(ndev);
2253 netif_tx_wake_all_queues(ndev);
2254 netif_tx_unlock_bh(ndev);
2255 napi_enable(&fep->napi);
2261 static const struct fec_stat {
2262 char name[ETH_GSTRING_LEN];
2266 { "tx_dropped", RMON_T_DROP },
2267 { "tx_packets", RMON_T_PACKETS },
2268 { "tx_broadcast", RMON_T_BC_PKT },
2269 { "tx_multicast", RMON_T_MC_PKT },
2270 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2271 { "tx_undersize", RMON_T_UNDERSIZE },
2272 { "tx_oversize", RMON_T_OVERSIZE },
2273 { "tx_fragment", RMON_T_FRAG },
2274 { "tx_jabber", RMON_T_JAB },
2275 { "tx_collision", RMON_T_COL },
2276 { "tx_64byte", RMON_T_P64 },
2277 { "tx_65to127byte", RMON_T_P65TO127 },
2278 { "tx_128to255byte", RMON_T_P128TO255 },
2279 { "tx_256to511byte", RMON_T_P256TO511 },
2280 { "tx_512to1023byte", RMON_T_P512TO1023 },
2281 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2282 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2283 { "tx_octets", RMON_T_OCTETS },
2286 { "IEEE_tx_drop", IEEE_T_DROP },
2287 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2288 { "IEEE_tx_1col", IEEE_T_1COL },
2289 { "IEEE_tx_mcol", IEEE_T_MCOL },
2290 { "IEEE_tx_def", IEEE_T_DEF },
2291 { "IEEE_tx_lcol", IEEE_T_LCOL },
2292 { "IEEE_tx_excol", IEEE_T_EXCOL },
2293 { "IEEE_tx_macerr", IEEE_T_MACERR },
2294 { "IEEE_tx_cserr", IEEE_T_CSERR },
2295 { "IEEE_tx_sqe", IEEE_T_SQE },
2296 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2297 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2300 { "rx_packets", RMON_R_PACKETS },
2301 { "rx_broadcast", RMON_R_BC_PKT },
2302 { "rx_multicast", RMON_R_MC_PKT },
2303 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2304 { "rx_undersize", RMON_R_UNDERSIZE },
2305 { "rx_oversize", RMON_R_OVERSIZE },
2306 { "rx_fragment", RMON_R_FRAG },
2307 { "rx_jabber", RMON_R_JAB },
2308 { "rx_64byte", RMON_R_P64 },
2309 { "rx_65to127byte", RMON_R_P65TO127 },
2310 { "rx_128to255byte", RMON_R_P128TO255 },
2311 { "rx_256to511byte", RMON_R_P256TO511 },
2312 { "rx_512to1023byte", RMON_R_P512TO1023 },
2313 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2314 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2315 { "rx_octets", RMON_R_OCTETS },
2318 { "IEEE_rx_drop", IEEE_R_DROP },
2319 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2320 { "IEEE_rx_crc", IEEE_R_CRC },
2321 { "IEEE_rx_align", IEEE_R_ALIGN },
2322 { "IEEE_rx_macerr", IEEE_R_MACERR },
2323 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2324 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2327 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2329 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2331 struct fec_enet_private *fep = netdev_priv(dev);
2334 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2335 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2338 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2339 struct ethtool_stats *stats, u64 *data)
2341 struct fec_enet_private *fep = netdev_priv(dev);
2343 if (netif_running(dev))
2344 fec_enet_update_ethtool_stats(dev);
2346 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2349 static void fec_enet_get_strings(struct net_device *netdev,
2350 u32 stringset, u8 *data)
2353 switch (stringset) {
2355 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2356 memcpy(data + i * ETH_GSTRING_LEN,
2357 fec_stats[i].name, ETH_GSTRING_LEN);
2362 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2366 return ARRAY_SIZE(fec_stats);
2372 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2374 struct fec_enet_private *fep = netdev_priv(dev);
2377 /* Disable MIB statistics counters */
2378 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2380 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2381 writel(0, fep->hwp + fec_stats[i].offset);
2383 /* Don't disable MIB statistics counters */
2384 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2387 #else /* !defined(CONFIG_M5272) */
2388 #define FEC_STATS_SIZE 0
2389 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2393 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2396 #endif /* !defined(CONFIG_M5272) */
2398 /* ITR clock source is enet system clock (clk_ahb).
2399 * TCTT unit is cycle_ns * 64 cycle
2400 * So, the ICTT value = X us / (cycle_ns * 64)
2402 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2404 struct fec_enet_private *fep = netdev_priv(ndev);
2406 return us * (fep->itr_clk_rate / 64000) / 1000;
2409 /* Set threshold for interrupt coalescing */
2410 static void fec_enet_itr_coal_set(struct net_device *ndev)
2412 struct fec_enet_private *fep = netdev_priv(ndev);
2415 /* Must be greater than zero to avoid unpredictable behavior */
2416 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2417 !fep->tx_time_itr || !fep->tx_pkts_itr)
2420 /* Select enet system clock as Interrupt Coalescing
2421 * timer Clock Source
2423 rx_itr = FEC_ITR_CLK_SEL;
2424 tx_itr = FEC_ITR_CLK_SEL;
2426 /* set ICFT and ICTT */
2427 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2428 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2429 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2430 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2432 rx_itr |= FEC_ITR_EN;
2433 tx_itr |= FEC_ITR_EN;
2435 writel(tx_itr, fep->hwp + FEC_TXIC0);
2436 writel(rx_itr, fep->hwp + FEC_RXIC0);
2437 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2438 writel(tx_itr, fep->hwp + FEC_TXIC1);
2439 writel(rx_itr, fep->hwp + FEC_RXIC1);
2440 writel(tx_itr, fep->hwp + FEC_TXIC2);
2441 writel(rx_itr, fep->hwp + FEC_RXIC2);
2446 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2448 struct fec_enet_private *fep = netdev_priv(ndev);
2450 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2453 ec->rx_coalesce_usecs = fep->rx_time_itr;
2454 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2456 ec->tx_coalesce_usecs = fep->tx_time_itr;
2457 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2463 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2465 struct fec_enet_private *fep = netdev_priv(ndev);
2468 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2471 if (ec->rx_max_coalesced_frames > 255) {
2472 pr_err("Rx coalesced frames exceed hardware limitation\n");
2476 if (ec->tx_max_coalesced_frames > 255) {
2477 pr_err("Tx coalesced frame exceed hardware limitation\n");
2481 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
2482 if (cycle > 0xFFFF) {
2483 pr_err("Rx coalesced usec exceed hardware limitation\n");
2487 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
2488 if (cycle > 0xFFFF) {
2489 pr_err("Tx coalesced usec exceed hardware limitation\n");
2493 fep->rx_time_itr = ec->rx_coalesce_usecs;
2494 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2496 fep->tx_time_itr = ec->tx_coalesce_usecs;
2497 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2499 fec_enet_itr_coal_set(ndev);
2504 static void fec_enet_itr_coal_init(struct net_device *ndev)
2506 struct ethtool_coalesce ec;
2508 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2509 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2511 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2512 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2514 fec_enet_set_coalesce(ndev, &ec);
2517 static int fec_enet_get_tunable(struct net_device *netdev,
2518 const struct ethtool_tunable *tuna,
2521 struct fec_enet_private *fep = netdev_priv(netdev);
2525 case ETHTOOL_RX_COPYBREAK:
2526 *(u32 *)data = fep->rx_copybreak;
2536 static int fec_enet_set_tunable(struct net_device *netdev,
2537 const struct ethtool_tunable *tuna,
2540 struct fec_enet_private *fep = netdev_priv(netdev);
2544 case ETHTOOL_RX_COPYBREAK:
2545 fep->rx_copybreak = *(u32 *)data;
2556 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2558 struct fec_enet_private *fep = netdev_priv(ndev);
2560 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2561 wol->supported = WAKE_MAGIC;
2562 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2564 wol->supported = wol->wolopts = 0;
2569 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2571 struct fec_enet_private *fep = netdev_priv(ndev);
2573 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2576 if (wol->wolopts & ~WAKE_MAGIC)
2579 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2580 if (device_may_wakeup(&ndev->dev)) {
2581 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2582 if (fep->irq[0] > 0)
2583 enable_irq_wake(fep->irq[0]);
2585 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2586 if (fep->irq[0] > 0)
2587 disable_irq_wake(fep->irq[0]);
2593 static const struct ethtool_ops fec_enet_ethtool_ops = {
2594 .get_drvinfo = fec_enet_get_drvinfo,
2595 .get_regs_len = fec_enet_get_regs_len,
2596 .get_regs = fec_enet_get_regs,
2597 .nway_reset = phy_ethtool_nway_reset,
2598 .get_link = ethtool_op_get_link,
2599 .get_coalesce = fec_enet_get_coalesce,
2600 .set_coalesce = fec_enet_set_coalesce,
2601 #ifndef CONFIG_M5272
2602 .get_pauseparam = fec_enet_get_pauseparam,
2603 .set_pauseparam = fec_enet_set_pauseparam,
2604 .get_strings = fec_enet_get_strings,
2605 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2606 .get_sset_count = fec_enet_get_sset_count,
2608 .get_ts_info = fec_enet_get_ts_info,
2609 .get_tunable = fec_enet_get_tunable,
2610 .set_tunable = fec_enet_set_tunable,
2611 .get_wol = fec_enet_get_wol,
2612 .set_wol = fec_enet_set_wol,
2613 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2614 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2617 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2619 struct fec_enet_private *fep = netdev_priv(ndev);
2620 struct phy_device *phydev = ndev->phydev;
2622 if (!netif_running(ndev))
2628 if (fep->bufdesc_ex) {
2629 if (cmd == SIOCSHWTSTAMP)
2630 return fec_ptp_set(ndev, rq);
2631 if (cmd == SIOCGHWTSTAMP)
2632 return fec_ptp_get(ndev, rq);
2635 return phy_mii_ioctl(phydev, rq, cmd);
2638 static void fec_enet_free_buffers(struct net_device *ndev)
2640 struct fec_enet_private *fep = netdev_priv(ndev);
2642 struct sk_buff *skb;
2643 struct bufdesc *bdp;
2644 struct fec_enet_priv_tx_q *txq;
2645 struct fec_enet_priv_rx_q *rxq;
2648 for (q = 0; q < fep->num_rx_queues; q++) {
2649 rxq = fep->rx_queue[q];
2651 for (i = 0; i < rxq->bd.ring_size; i++) {
2652 skb = rxq->rx_skbuff[i];
2653 rxq->rx_skbuff[i] = NULL;
2655 dma_unmap_single(&fep->pdev->dev,
2656 fec32_to_cpu(bdp->cbd_bufaddr),
2657 FEC_ENET_RX_FRSIZE - fep->rx_align,
2661 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2665 for (q = 0; q < fep->num_tx_queues; q++) {
2666 txq = fep->tx_queue[q];
2668 for (i = 0; i < txq->bd.ring_size; i++) {
2669 kfree(txq->tx_bounce[i]);
2670 txq->tx_bounce[i] = NULL;
2671 skb = txq->tx_skbuff[i];
2672 txq->tx_skbuff[i] = NULL;
2678 static void fec_enet_free_queue(struct net_device *ndev)
2680 struct fec_enet_private *fep = netdev_priv(ndev);
2682 struct fec_enet_priv_tx_q *txq;
2684 for (i = 0; i < fep->num_tx_queues; i++)
2685 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2686 txq = fep->tx_queue[i];
2687 dma_free_coherent(&fep->pdev->dev,
2688 txq->bd.ring_size * TSO_HEADER_SIZE,
2693 for (i = 0; i < fep->num_rx_queues; i++)
2694 kfree(fep->rx_queue[i]);
2695 for (i = 0; i < fep->num_tx_queues; i++)
2696 kfree(fep->tx_queue[i]);
2699 static int fec_enet_alloc_queue(struct net_device *ndev)
2701 struct fec_enet_private *fep = netdev_priv(ndev);
2704 struct fec_enet_priv_tx_q *txq;
2706 for (i = 0; i < fep->num_tx_queues; i++) {
2707 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2713 fep->tx_queue[i] = txq;
2714 txq->bd.ring_size = TX_RING_SIZE;
2715 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2717 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2718 txq->tx_wake_threshold =
2719 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2721 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2722 txq->bd.ring_size * TSO_HEADER_SIZE,
2725 if (!txq->tso_hdrs) {
2731 for (i = 0; i < fep->num_rx_queues; i++) {
2732 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2734 if (!fep->rx_queue[i]) {
2739 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2740 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2745 fec_enet_free_queue(ndev);
2750 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2752 struct fec_enet_private *fep = netdev_priv(ndev);
2754 struct sk_buff *skb;
2755 struct bufdesc *bdp;
2756 struct fec_enet_priv_rx_q *rxq;
2758 rxq = fep->rx_queue[queue];
2760 for (i = 0; i < rxq->bd.ring_size; i++) {
2761 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2765 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2770 rxq->rx_skbuff[i] = skb;
2771 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2773 if (fep->bufdesc_ex) {
2774 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2775 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2778 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2781 /* Set the last buffer to wrap. */
2782 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2783 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2787 fec_enet_free_buffers(ndev);
2792 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2794 struct fec_enet_private *fep = netdev_priv(ndev);
2796 struct bufdesc *bdp;
2797 struct fec_enet_priv_tx_q *txq;
2799 txq = fep->tx_queue[queue];
2801 for (i = 0; i < txq->bd.ring_size; i++) {
2802 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2803 if (!txq->tx_bounce[i])
2806 bdp->cbd_sc = cpu_to_fec16(0);
2807 bdp->cbd_bufaddr = cpu_to_fec32(0);
2809 if (fep->bufdesc_ex) {
2810 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2811 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2814 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2817 /* Set the last buffer to wrap. */
2818 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2819 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2824 fec_enet_free_buffers(ndev);
2828 static int fec_enet_alloc_buffers(struct net_device *ndev)
2830 struct fec_enet_private *fep = netdev_priv(ndev);
2833 for (i = 0; i < fep->num_rx_queues; i++)
2834 if (fec_enet_alloc_rxq_buffers(ndev, i))
2837 for (i = 0; i < fep->num_tx_queues; i++)
2838 if (fec_enet_alloc_txq_buffers(ndev, i))
2844 fec_enet_open(struct net_device *ndev)
2846 struct fec_enet_private *fep = netdev_priv(ndev);
2849 ret = pm_runtime_get_sync(&fep->pdev->dev);
2853 pinctrl_pm_select_default_state(&fep->pdev->dev);
2854 ret = fec_enet_clk_enable(ndev, true);
2858 /* I should reset the ring buffers here, but I don't yet know
2859 * a simple way to do that.
2862 ret = fec_enet_alloc_buffers(ndev);
2864 goto err_enet_alloc;
2866 /* Init MAC prior to mii bus probe */
2869 /* Probe and connect to PHY when open the interface */
2870 ret = fec_enet_mii_probe(ndev);
2872 goto err_enet_mii_probe;
2874 if (fep->quirks & FEC_QUIRK_ERR006687)
2875 imx6q_cpuidle_fec_irqs_used();
2877 napi_enable(&fep->napi);
2878 phy_start(ndev->phydev);
2879 netif_tx_start_all_queues(ndev);
2881 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2882 FEC_WOL_FLAG_ENABLE);
2887 fec_enet_free_buffers(ndev);
2889 fec_enet_clk_enable(ndev, false);
2891 pm_runtime_mark_last_busy(&fep->pdev->dev);
2892 pm_runtime_put_autosuspend(&fep->pdev->dev);
2893 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2898 fec_enet_close(struct net_device *ndev)
2900 struct fec_enet_private *fep = netdev_priv(ndev);
2902 phy_stop(ndev->phydev);
2904 if (netif_device_present(ndev)) {
2905 napi_disable(&fep->napi);
2906 netif_tx_disable(ndev);
2910 phy_disconnect(ndev->phydev);
2912 if (fep->quirks & FEC_QUIRK_ERR006687)
2913 imx6q_cpuidle_fec_irqs_unused();
2915 fec_enet_update_ethtool_stats(ndev);
2917 fec_enet_clk_enable(ndev, false);
2918 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2919 pm_runtime_mark_last_busy(&fep->pdev->dev);
2920 pm_runtime_put_autosuspend(&fep->pdev->dev);
2922 fec_enet_free_buffers(ndev);
2927 /* Set or clear the multicast filter for this adaptor.
2928 * Skeleton taken from sunlance driver.
2929 * The CPM Ethernet implementation allows Multicast as well as individual
2930 * MAC address filtering. Some of the drivers check to make sure it is
2931 * a group multicast address, and discard those that are not. I guess I
2932 * will do the same for now, but just remove the test if you want
2933 * individual filtering as well (do the upper net layers want or support
2934 * this kind of feature?).
2937 #define FEC_HASH_BITS 6 /* #bits in hash */
2938 #define CRC32_POLY 0xEDB88320
2940 static void set_multicast_list(struct net_device *ndev)
2942 struct fec_enet_private *fep = netdev_priv(ndev);
2943 struct netdev_hw_addr *ha;
2944 unsigned int i, bit, data, crc, tmp;
2946 unsigned int hash_high = 0, hash_low = 0;
2948 if (ndev->flags & IFF_PROMISC) {
2949 tmp = readl(fep->hwp + FEC_R_CNTRL);
2951 writel(tmp, fep->hwp + FEC_R_CNTRL);
2955 tmp = readl(fep->hwp + FEC_R_CNTRL);
2957 writel(tmp, fep->hwp + FEC_R_CNTRL);
2959 if (ndev->flags & IFF_ALLMULTI) {
2960 /* Catch all multicast addresses, so set the
2963 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2964 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2969 /* Add the addresses in hash register */
2970 netdev_for_each_mc_addr(ha, ndev) {
2971 /* calculate crc32 value of mac address */
2974 for (i = 0; i < ndev->addr_len; i++) {
2976 for (bit = 0; bit < 8; bit++, data >>= 1) {
2978 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2982 /* only upper 6 bits (FEC_HASH_BITS) are used
2983 * which point to specific bit in the hash registers
2985 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
2988 hash_high |= 1 << (hash - 32);
2990 hash_low |= 1 << hash;
2993 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2994 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2997 /* Set a MAC change in hardware. */
2999 fec_set_mac_address(struct net_device *ndev, void *p)
3001 struct fec_enet_private *fep = netdev_priv(ndev);
3002 struct sockaddr *addr = p;
3005 if (!is_valid_ether_addr(addr->sa_data))
3006 return -EADDRNOTAVAIL;
3007 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3010 /* Add netif status check here to avoid system hang in below case:
3011 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3012 * After ethx down, fec all clocks are gated off and then register
3013 * access causes system hang.
3015 if (!netif_running(ndev))
3018 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3019 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3020 fep->hwp + FEC_ADDR_LOW);
3021 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3022 fep->hwp + FEC_ADDR_HIGH);
3026 #ifdef CONFIG_NET_POLL_CONTROLLER
3028 * fec_poll_controller - FEC Poll controller function
3029 * @dev: The FEC network adapter
3031 * Polled functionality used by netconsole and others in non interrupt mode
3034 static void fec_poll_controller(struct net_device *dev)
3037 struct fec_enet_private *fep = netdev_priv(dev);
3039 for (i = 0; i < FEC_IRQ_NUM; i++) {
3040 if (fep->irq[i] > 0) {
3041 disable_irq(fep->irq[i]);
3042 fec_enet_interrupt(fep->irq[i], dev);
3043 enable_irq(fep->irq[i]);
3049 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3050 netdev_features_t features)
3052 struct fec_enet_private *fep = netdev_priv(netdev);
3053 netdev_features_t changed = features ^ netdev->features;
3055 netdev->features = features;
3057 /* Receive checksum has been changed */
3058 if (changed & NETIF_F_RXCSUM) {
3059 if (features & NETIF_F_RXCSUM)
3060 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3062 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3066 static int fec_set_features(struct net_device *netdev,
3067 netdev_features_t features)
3069 struct fec_enet_private *fep = netdev_priv(netdev);
3070 netdev_features_t changed = features ^ netdev->features;
3072 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3073 napi_disable(&fep->napi);
3074 netif_tx_lock_bh(netdev);
3076 fec_enet_set_netdev_features(netdev, features);
3077 fec_restart(netdev);
3078 netif_tx_wake_all_queues(netdev);
3079 netif_tx_unlock_bh(netdev);
3080 napi_enable(&fep->napi);
3082 fec_enet_set_netdev_features(netdev, features);
3088 static const struct net_device_ops fec_netdev_ops = {
3089 .ndo_open = fec_enet_open,
3090 .ndo_stop = fec_enet_close,
3091 .ndo_start_xmit = fec_enet_start_xmit,
3092 .ndo_set_rx_mode = set_multicast_list,
3093 .ndo_validate_addr = eth_validate_addr,
3094 .ndo_tx_timeout = fec_timeout,
3095 .ndo_set_mac_address = fec_set_mac_address,
3096 .ndo_do_ioctl = fec_enet_ioctl,
3097 #ifdef CONFIG_NET_POLL_CONTROLLER
3098 .ndo_poll_controller = fec_poll_controller,
3100 .ndo_set_features = fec_set_features,
3103 static const unsigned short offset_des_active_rxq[] = {
3104 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3107 static const unsigned short offset_des_active_txq[] = {
3108 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3112 * XXX: We need to clean up on failure exits here.
3115 static int fec_enet_init(struct net_device *ndev)
3117 struct fec_enet_private *fep = netdev_priv(ndev);
3118 struct bufdesc *cbd_base;
3122 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3123 sizeof(struct bufdesc);
3124 unsigned dsize_log2 = __fls(dsize);
3126 WARN_ON(dsize != (1 << dsize_log2));
3127 #if defined(CONFIG_ARM)
3128 fep->rx_align = 0xf;
3129 fep->tx_align = 0xf;
3131 fep->rx_align = 0x3;
3132 fep->tx_align = 0x3;
3135 fec_enet_alloc_queue(ndev);
3137 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3139 /* Allocate memory for buffer descriptors. */
3140 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3146 memset(cbd_base, 0, bd_size);
3148 /* Get the Ethernet address */
3150 /* make sure MAC we just acquired is programmed into the hw */
3151 fec_set_mac_address(ndev, NULL);
3153 /* Set receive and transmit descriptor base. */
3154 for (i = 0; i < fep->num_rx_queues; i++) {
3155 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3156 unsigned size = dsize * rxq->bd.ring_size;
3159 rxq->bd.base = cbd_base;
3160 rxq->bd.cur = cbd_base;
3161 rxq->bd.dma = bd_dma;
3162 rxq->bd.dsize = dsize;
3163 rxq->bd.dsize_log2 = dsize_log2;
3164 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3166 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3167 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3170 for (i = 0; i < fep->num_tx_queues; i++) {
3171 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3172 unsigned size = dsize * txq->bd.ring_size;
3175 txq->bd.base = cbd_base;
3176 txq->bd.cur = cbd_base;
3177 txq->bd.dma = bd_dma;
3178 txq->bd.dsize = dsize;
3179 txq->bd.dsize_log2 = dsize_log2;
3180 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3182 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3183 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3187 /* The FEC Ethernet specific entries in the device structure */
3188 ndev->watchdog_timeo = TX_TIMEOUT;
3189 ndev->netdev_ops = &fec_netdev_ops;
3190 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3192 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3193 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3195 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3196 /* enable hw VLAN support */
3197 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3199 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3200 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3202 /* enable hw accelerator */
3203 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3204 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3205 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3208 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3210 fep->rx_align = 0x3f;
3213 ndev->hw_features = ndev->features;
3217 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3218 fec_enet_clear_ethtool_stats(ndev);
3220 fec_enet_update_ethtool_stats(ndev);
3226 static int fec_reset_phy(struct platform_device *pdev)
3229 bool active_high = false;
3230 int msec = 1, phy_post_delay = 0;
3231 struct device_node *np = pdev->dev.of_node;
3236 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3237 /* A sane reset duration should not be longer than 1s */
3238 if (!err && msec > 1000)
3241 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3242 if (phy_reset == -EPROBE_DEFER)
3244 else if (!gpio_is_valid(phy_reset))
3247 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3248 /* valid reset duration should be less than 1s */
3249 if (!err && phy_post_delay > 1000)
3252 active_high = of_property_read_bool(np, "phy-reset-active-high");
3254 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3255 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3258 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3265 usleep_range(msec * 1000, msec * 1000 + 1000);
3267 gpio_set_value_cansleep(phy_reset, !active_high);
3269 if (!phy_post_delay)
3272 if (phy_post_delay > 20)
3273 msleep(phy_post_delay);
3275 usleep_range(phy_post_delay * 1000,
3276 phy_post_delay * 1000 + 1000);
3280 #else /* CONFIG_OF */
3281 static int fec_reset_phy(struct platform_device *pdev)
3284 * In case of platform probe, the reset has been done
3289 #endif /* CONFIG_OF */
3292 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3294 struct device_node *np = pdev->dev.of_node;
3296 *num_tx = *num_rx = 1;
3298 if (!np || !of_device_is_available(np))
3301 /* parse the num of tx and rx queues */
3302 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3304 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3306 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3307 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3313 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3314 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3323 fec_probe(struct platform_device *pdev)
3325 struct fec_enet_private *fep;
3326 struct fec_platform_data *pdata;
3327 struct net_device *ndev;
3328 int i, irq, ret = 0;
3330 const struct of_device_id *of_id;
3332 struct device_node *np = pdev->dev.of_node, *phy_node;
3336 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3338 /* Init network device */
3339 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3340 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3344 SET_NETDEV_DEV(ndev, &pdev->dev);
3346 /* setup board info structure */
3347 fep = netdev_priv(ndev);
3349 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3351 pdev->id_entry = of_id->data;
3352 fep->quirks = pdev->id_entry->driver_data;
3355 fep->num_rx_queues = num_rx_qs;
3356 fep->num_tx_queues = num_tx_qs;
3358 #if !defined(CONFIG_M5272)
3359 /* default enable pause frame auto negotiation */
3360 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3361 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3364 /* Select default pin state */
3365 pinctrl_pm_select_default_state(&pdev->dev);
3367 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3368 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3369 if (IS_ERR(fep->hwp)) {
3370 ret = PTR_ERR(fep->hwp);
3371 goto failed_ioremap;
3375 fep->dev_id = dev_id++;
3377 platform_set_drvdata(pdev, ndev);
3379 if ((of_machine_is_compatible("fsl,imx6q") ||
3380 of_machine_is_compatible("fsl,imx6dl")) &&
3381 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3382 fep->quirks |= FEC_QUIRK_ERR006687;
3384 if (of_get_property(np, "fsl,magic-packet", NULL))
3385 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3387 phy_node = of_parse_phandle(np, "phy-handle", 0);
3388 if (!phy_node && of_phy_is_fixed_link(np)) {
3389 ret = of_phy_register_fixed_link(np);
3392 "broken fixed-link specification\n");
3395 phy_node = of_node_get(np);
3397 fep->phy_node = phy_node;
3399 ret = of_get_phy_mode(pdev->dev.of_node);
3401 pdata = dev_get_platdata(&pdev->dev);
3403 fep->phy_interface = pdata->phy;
3405 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3407 fep->phy_interface = ret;
3410 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3411 if (IS_ERR(fep->clk_ipg)) {
3412 ret = PTR_ERR(fep->clk_ipg);
3416 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3417 if (IS_ERR(fep->clk_ahb)) {
3418 ret = PTR_ERR(fep->clk_ahb);
3422 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3424 /* enet_out is optional, depends on board */
3425 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3426 if (IS_ERR(fep->clk_enet_out))
3427 fep->clk_enet_out = NULL;
3429 fep->ptp_clk_on = false;
3430 mutex_init(&fep->ptp_clk_mutex);
3432 /* clk_ref is optional, depends on board */
3433 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3434 if (IS_ERR(fep->clk_ref))
3435 fep->clk_ref = NULL;
3437 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3438 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3439 if (IS_ERR(fep->clk_ptp)) {
3440 fep->clk_ptp = NULL;
3441 fep->bufdesc_ex = false;
3444 ret = fec_enet_clk_enable(ndev, true);
3448 ret = clk_prepare_enable(fep->clk_ipg);
3450 goto failed_clk_ipg;
3451 ret = clk_prepare_enable(fep->clk_ahb);
3453 goto failed_clk_ahb;
3455 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3456 if (!IS_ERR(fep->reg_phy)) {
3457 ret = regulator_enable(fep->reg_phy);
3460 "Failed to enable phy regulator: %d\n", ret);
3461 clk_disable_unprepare(fep->clk_ipg);
3462 goto failed_regulator;
3465 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3466 ret = -EPROBE_DEFER;
3467 goto failed_regulator;
3469 fep->reg_phy = NULL;
3472 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3473 pm_runtime_use_autosuspend(&pdev->dev);
3474 pm_runtime_get_noresume(&pdev->dev);
3475 pm_runtime_set_active(&pdev->dev);
3476 pm_runtime_enable(&pdev->dev);
3478 ret = fec_reset_phy(pdev);
3482 if (fep->bufdesc_ex)
3485 ret = fec_enet_init(ndev);
3489 for (i = 0; i < FEC_IRQ_NUM; i++) {
3490 irq = platform_get_irq(pdev, i);
3497 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3498 0, pdev->name, ndev);
3505 init_completion(&fep->mdio_done);
3506 ret = fec_enet_mii_init(pdev);
3508 goto failed_mii_init;
3510 /* Carrier starts down, phylib will bring it up */
3511 netif_carrier_off(ndev);
3512 fec_enet_clk_enable(ndev, false);
3513 pinctrl_pm_select_sleep_state(&pdev->dev);
3515 ret = register_netdev(ndev);
3517 goto failed_register;
3519 device_init_wakeup(&ndev->dev, fep->wol_flag &
3520 FEC_WOL_HAS_MAGIC_PACKET);
3522 if (fep->bufdesc_ex && fep->ptp_clock)
3523 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3525 fep->rx_copybreak = COPYBREAK_DEFAULT;
3526 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3528 pm_runtime_mark_last_busy(&pdev->dev);
3529 pm_runtime_put_autosuspend(&pdev->dev);
3534 fec_enet_mii_remove(fep);
3540 pm_runtime_put_noidle(&pdev->dev);
3541 pm_runtime_disable(&pdev->dev);
3543 regulator_disable(fep->reg_phy);
3545 clk_disable_unprepare(fep->clk_ahb);
3547 clk_disable_unprepare(fep->clk_ipg);
3549 fec_enet_clk_enable(ndev, false);
3551 if (of_phy_is_fixed_link(np))
3552 of_phy_deregister_fixed_link(np);
3553 of_node_put(phy_node);
3563 fec_drv_remove(struct platform_device *pdev)
3565 struct net_device *ndev = platform_get_drvdata(pdev);
3566 struct fec_enet_private *fep = netdev_priv(ndev);
3567 struct device_node *np = pdev->dev.of_node;
3570 ret = pm_runtime_get_sync(&pdev->dev);
3574 cancel_work_sync(&fep->tx_timeout_work);
3576 unregister_netdev(ndev);
3577 fec_enet_mii_remove(fep);
3579 regulator_disable(fep->reg_phy);
3581 if (of_phy_is_fixed_link(np))
3582 of_phy_deregister_fixed_link(np);
3583 of_node_put(fep->phy_node);
3585 clk_disable_unprepare(fep->clk_ahb);
3586 clk_disable_unprepare(fep->clk_ipg);
3587 pm_runtime_put_noidle(&pdev->dev);
3588 pm_runtime_disable(&pdev->dev);
3594 static int __maybe_unused fec_suspend(struct device *dev)
3596 struct net_device *ndev = dev_get_drvdata(dev);
3597 struct fec_enet_private *fep = netdev_priv(ndev);
3600 if (netif_running(ndev)) {
3601 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3602 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3603 phy_stop(ndev->phydev);
3604 napi_disable(&fep->napi);
3605 netif_tx_lock_bh(ndev);
3606 netif_device_detach(ndev);
3607 netif_tx_unlock_bh(ndev);
3609 fec_enet_clk_enable(ndev, false);
3610 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3611 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3615 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3616 regulator_disable(fep->reg_phy);
3618 /* SOC supply clock to phy, when clock is disabled, phy link down
3619 * SOC control phy regulator, when regulator is disabled, phy link down
3621 if (fep->clk_enet_out || fep->reg_phy)
3627 static int __maybe_unused fec_resume(struct device *dev)
3629 struct net_device *ndev = dev_get_drvdata(dev);
3630 struct fec_enet_private *fep = netdev_priv(ndev);
3631 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3635 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3636 ret = regulator_enable(fep->reg_phy);
3642 if (netif_running(ndev)) {
3643 ret = fec_enet_clk_enable(ndev, true);
3648 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3649 if (pdata && pdata->sleep_mode_enable)
3650 pdata->sleep_mode_enable(false);
3651 val = readl(fep->hwp + FEC_ECNTRL);
3652 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3653 writel(val, fep->hwp + FEC_ECNTRL);
3654 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3656 pinctrl_pm_select_default_state(&fep->pdev->dev);
3659 netif_tx_lock_bh(ndev);
3660 netif_device_attach(ndev);
3661 netif_tx_unlock_bh(ndev);
3662 napi_enable(&fep->napi);
3663 phy_start(ndev->phydev);
3671 regulator_disable(fep->reg_phy);
3675 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3677 struct net_device *ndev = dev_get_drvdata(dev);
3678 struct fec_enet_private *fep = netdev_priv(ndev);
3680 clk_disable_unprepare(fep->clk_ahb);
3681 clk_disable_unprepare(fep->clk_ipg);
3686 static int __maybe_unused fec_runtime_resume(struct device *dev)
3688 struct net_device *ndev = dev_get_drvdata(dev);
3689 struct fec_enet_private *fep = netdev_priv(ndev);
3692 ret = clk_prepare_enable(fep->clk_ahb);
3695 ret = clk_prepare_enable(fep->clk_ipg);
3697 goto failed_clk_ipg;
3702 clk_disable_unprepare(fep->clk_ahb);
3706 static const struct dev_pm_ops fec_pm_ops = {
3707 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3708 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3711 static struct platform_driver fec_driver = {
3713 .name = DRIVER_NAME,
3715 .of_match_table = fec_dt_ids,
3717 .id_table = fec_devtype,
3719 .remove = fec_drv_remove,
3722 module_platform_driver(fec_driver);
3724 MODULE_ALIAS("platform:"DRIVER_NAME);
3725 MODULE_LICENSE("GPL");