drivers/net/ethernet/freescale/fman/fman.c

   1 /*
   2  * Copyright 2008-2015 Freescale Semiconductor Inc.
   3  * Copyright 2020 NXP
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of Freescale Semiconductor nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  *
  17  * ALTERNATIVELY, this software may be distributed under the terms of the
  18  * GNU General Public License ("GPL") as published by the Free Software
  19  * Foundation, either version 2 of that License or (at your option) any
  20  * later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  23  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  35
  36 #include <linux/fsl/guts.h>
  37 #include <linux/slab.h>
  38 #include <linux/delay.h>
  39 #include <linux/module.h>
  40 #include <linux/of_platform.h>
  41 #include <linux/clk.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_irq.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/libfdt_env.h>
  46
  47 #include "fman.h"
  48 #include "fman_muram.h"
  49 #include "fman_keygen.h"
  50
  51 /* General defines */
  52 #define FMAN_LIODN_TBL                  64      /* size of LIODN table */
  53 #define MAX_NUM_OF_MACS                 10
  54 #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS  4
  55 #define BASE_RX_PORTID                  0x08
  56 #define BASE_TX_PORTID                  0x28
  57
  58 /* Modules registers offsets */
  59 #define BMI_OFFSET              0x00080000
  60 #define QMI_OFFSET              0x00080400
  61 #define KG_OFFSET               0x000C1000
  62 #define DMA_OFFSET              0x000C2000
  63 #define FPM_OFFSET              0x000C3000
  64 #define IMEM_OFFSET             0x000C4000
  65 #define HWP_OFFSET              0x000C7000
  66 #define CGP_OFFSET              0x000DB000
  67
  68 /* Exceptions bit map */
  69 #define EX_DMA_BUS_ERROR                0x80000000
  70 #define EX_DMA_READ_ECC                 0x40000000
  71 #define EX_DMA_SYSTEM_WRITE_ECC 0x20000000
  72 #define EX_DMA_FM_WRITE_ECC             0x10000000
  73 #define EX_FPM_STALL_ON_TASKS           0x08000000
  74 #define EX_FPM_SINGLE_ECC               0x04000000
  75 #define EX_FPM_DOUBLE_ECC               0x02000000
  76 #define EX_QMI_SINGLE_ECC               0x01000000
  77 #define EX_QMI_DEQ_FROM_UNKNOWN_PORTID  0x00800000
  78 #define EX_QMI_DOUBLE_ECC               0x00400000
  79 #define EX_BMI_LIST_RAM_ECC             0x00200000
  80 #define EX_BMI_STORAGE_PROFILE_ECC      0x00100000
  81 #define EX_BMI_STATISTICS_RAM_ECC       0x00080000
  82 #define EX_IRAM_ECC                     0x00040000
  83 #define EX_MURAM_ECC                    0x00020000
  84 #define EX_BMI_DISPATCH_RAM_ECC 0x00010000
  85 #define EX_DMA_SINGLE_PORT_ECC          0x00008000
  86
  87 /* DMA defines */
  88 /* masks */
  89 #define DMA_MODE_BER                    0x00200000
  90 #define DMA_MODE_ECC                    0x00000020
  91 #define DMA_MODE_SECURE_PROT            0x00000800
  92 #define DMA_MODE_AXI_DBG_MASK           0x0F000000
  93
  94 #define DMA_TRANSFER_PORTID_MASK        0xFF000000
  95 #define DMA_TRANSFER_TNUM_MASK          0x00FF0000
  96 #define DMA_TRANSFER_LIODN_MASK 0x00000FFF
  97
  98 #define DMA_STATUS_BUS_ERR              0x08000000
  99 #define DMA_STATUS_READ_ECC             0x04000000
 100 #define DMA_STATUS_SYSTEM_WRITE_ECC     0x02000000
 101 #define DMA_STATUS_FM_WRITE_ECC 0x01000000
 102 #define DMA_STATUS_FM_SPDAT_ECC 0x00080000
 103
 104 #define DMA_MODE_CACHE_OR_SHIFT         30
 105 #define DMA_MODE_AXI_DBG_SHIFT                  24
 106 #define DMA_MODE_CEN_SHIFT                      13
 107 #define DMA_MODE_CEN_MASK                       0x00000007
 108 #define DMA_MODE_DBG_SHIFT                      7
 109 #define DMA_MODE_AID_MODE_SHIFT         4
 110
 111 #define DMA_THRESH_COMMQ_SHIFT                  24
 112 #define DMA_THRESH_READ_INT_BUF_SHIFT           16
 113 #define DMA_THRESH_READ_INT_BUF_MASK            0x0000003f
 114 #define DMA_THRESH_WRITE_INT_BUF_MASK           0x0000003f
 115
 116 #define DMA_TRANSFER_PORTID_SHIFT               24
 117 #define DMA_TRANSFER_TNUM_SHIFT         16
 118
 119 #define DMA_CAM_SIZEOF_ENTRY                    0x40
 120 #define DMA_CAM_UNITS                           8
 121
 122 #define DMA_LIODN_SHIFT         16
 123 #define DMA_LIODN_BASE_MASK     0x00000FFF
 124
 125 /* FPM defines */
 126 #define FPM_EV_MASK_DOUBLE_ECC          0x80000000
 127 #define FPM_EV_MASK_STALL               0x40000000
 128 #define FPM_EV_MASK_SINGLE_ECC          0x20000000
 129 #define FPM_EV_MASK_RELEASE_FM          0x00010000
 130 #define FPM_EV_MASK_DOUBLE_ECC_EN       0x00008000
 131 #define FPM_EV_MASK_STALL_EN            0x00004000
 132 #define FPM_EV_MASK_SINGLE_ECC_EN       0x00002000
 133 #define FPM_EV_MASK_EXTERNAL_HALT       0x00000008
 134 #define FPM_EV_MASK_ECC_ERR_HALT        0x00000004
 135
 136 #define FPM_RAM_MURAM_ECC               0x00008000
 137 #define FPM_RAM_IRAM_ECC                0x00004000
 138 #define FPM_IRAM_ECC_ERR_EX_EN          0x00020000
 139 #define FPM_MURAM_ECC_ERR_EX_EN 0x00040000
 140 #define FPM_RAM_IRAM_ECC_EN             0x40000000
 141 #define FPM_RAM_RAMS_ECC_EN             0x80000000
 142 #define FPM_RAM_RAMS_ECC_EN_SRC_SEL     0x08000000
 143
 144 #define FPM_REV1_MAJOR_MASK             0x0000FF00
 145 #define FPM_REV1_MINOR_MASK             0x000000FF
 146
 147 #define FPM_DISP_LIMIT_SHIFT            24
 148
 149 #define FPM_PRT_FM_CTL1                 0x00000001
 150 #define FPM_PRT_FM_CTL2                 0x00000002
 151 #define FPM_PORT_FM_CTL_PORTID_SHIFT    24
 152 #define FPM_PRC_ORA_FM_CTL_SEL_SHIFT    16
 153
 154 #define FPM_THR1_PRS_SHIFT              24
 155 #define FPM_THR1_KG_SHIFT               16
 156 #define FPM_THR1_PLCR_SHIFT             8
 157 #define FPM_THR1_BMI_SHIFT              0
 158
 159 #define FPM_THR2_QMI_ENQ_SHIFT          24
 160 #define FPM_THR2_QMI_DEQ_SHIFT          0
 161 #define FPM_THR2_FM_CTL1_SHIFT          16
 162 #define FPM_THR2_FM_CTL2_SHIFT          8
 163
 164 #define FPM_EV_MASK_CAT_ERR_SHIFT       1
 165 #define FPM_EV_MASK_DMA_ERR_SHIFT       0
 166
 167 #define FPM_REV1_MAJOR_SHIFT            8
 168
 169 #define FPM_RSTC_FM_RESET               0x80000000
 170 #define FPM_RSTC_MAC0_RESET             0x40000000
 171 #define FPM_RSTC_MAC1_RESET             0x20000000
 172 #define FPM_RSTC_MAC2_RESET             0x10000000
 173 #define FPM_RSTC_MAC3_RESET             0x08000000
 174 #define FPM_RSTC_MAC8_RESET             0x04000000
 175 #define FPM_RSTC_MAC4_RESET             0x02000000
 176 #define FPM_RSTC_MAC5_RESET             0x01000000
 177 #define FPM_RSTC_MAC6_RESET             0x00800000
 178 #define FPM_RSTC_MAC7_RESET             0x00400000
 179 #define FPM_RSTC_MAC9_RESET             0x00200000
 180
 181 #define FPM_TS_INT_SHIFT                16
 182 #define FPM_TS_CTL_EN                   0x80000000
 183
 184 /* BMI defines */
 185 #define BMI_INIT_START                          0x80000000
 186 #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC     0x80000000
 187 #define BMI_ERR_INTR_EN_LIST_RAM_ECC            0x40000000
 188 #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC      0x20000000
 189 #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC        0x10000000
 190 #define BMI_NUM_OF_TASKS_MASK                   0x3F000000
 191 #define BMI_NUM_OF_EXTRA_TASKS_MASK             0x000F0000
 192 #define BMI_NUM_OF_DMAS_MASK                    0x00000F00
 193 #define BMI_NUM_OF_EXTRA_DMAS_MASK              0x0000000F
 194 #define BMI_FIFO_SIZE_MASK                      0x000003FF
 195 #define BMI_EXTRA_FIFO_SIZE_MASK                0x03FF0000
 196 #define BMI_CFG2_DMAS_MASK                      0x0000003F
 197 #define BMI_CFG2_TASKS_MASK                     0x0000003F
 198
 199 #define BMI_CFG2_TASKS_SHIFT            16
 200 #define BMI_CFG2_DMAS_SHIFT             0
 201 #define BMI_CFG1_FIFO_SIZE_SHIFT        16
 202 #define BMI_NUM_OF_TASKS_SHIFT          24
 203 #define BMI_EXTRA_NUM_OF_TASKS_SHIFT    16
 204 #define BMI_NUM_OF_DMAS_SHIFT           8
 205 #define BMI_EXTRA_NUM_OF_DMAS_SHIFT     0
 206
 207 #define BMI_FIFO_ALIGN                  0x100
 208
 209 #define BMI_EXTRA_FIFO_SIZE_SHIFT       16
 210
 211 /* QMI defines */
 212 #define QMI_CFG_ENQ_EN                  0x80000000
 213 #define QMI_CFG_DEQ_EN                  0x40000000
 214 #define QMI_CFG_EN_COUNTERS             0x10000000
 215 #define QMI_CFG_DEQ_MASK                0x0000003F
 216 #define QMI_CFG_ENQ_MASK                0x00003F00
 217 #define QMI_CFG_ENQ_SHIFT               8
 218
 219 #define QMI_ERR_INTR_EN_DOUBLE_ECC      0x80000000
 220 #define QMI_ERR_INTR_EN_DEQ_FROM_DEF    0x40000000
 221 #define QMI_INTR_EN_SINGLE_ECC          0x80000000
 222
 223 #define QMI_GS_HALT_NOT_BUSY            0x00000002
 224
 225 /* HWP defines */
 226 #define HWP_RPIMAC_PEN                  0x00000001
 227
 228 /* IRAM defines */
 229 #define IRAM_IADD_AIE                   0x80000000
 230 #define IRAM_READY                      0x80000000
 231
 232 /* Default values */
 233 #define DEFAULT_CATASTROPHIC_ERR                0
 234 #define DEFAULT_DMA_ERR                         0
 235 #define DEFAULT_AID_MODE                        FMAN_DMA_AID_OUT_TNUM
 236 #define DEFAULT_DMA_COMM_Q_LOW                  0x2A
 237 #define DEFAULT_DMA_COMM_Q_HIGH         0x3F
 238 #define DEFAULT_CACHE_OVERRIDE                  0
 239 #define DEFAULT_DMA_CAM_NUM_OF_ENTRIES          64
 240 #define DEFAULT_DMA_DBG_CNT_MODE                0
 241 #define DEFAULT_DMA_SOS_EMERGENCY               0
 242 #define DEFAULT_DMA_WATCHDOG                    0
 243 #define DEFAULT_DISP_LIMIT                      0
 244 #define DEFAULT_PRS_DISP_TH                     16
 245 #define DEFAULT_PLCR_DISP_TH                    16
 246 #define DEFAULT_KG_DISP_TH                      16
 247 #define DEFAULT_BMI_DISP_TH                     16
 248 #define DEFAULT_QMI_ENQ_DISP_TH         16
 249 #define DEFAULT_QMI_DEQ_DISP_TH         16
 250 #define DEFAULT_FM_CTL1_DISP_TH         16
 251 #define DEFAULT_FM_CTL2_DISP_TH         16
 252
 253 #define DFLT_AXI_DBG_NUM_OF_BEATS               1
 254
 255 #define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf)   \
 256         ((dma_thresh_max_buf + 1) / 2)
 257 #define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf)  \
 258         ((dma_thresh_max_buf + 1) * 3 / 4)
 259 #define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf)  \
 260         ((dma_thresh_max_buf + 1) / 2)
 261 #define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\
 262         ((dma_thresh_max_buf + 1) * 3 / 4)
 263
 264 #define DMA_COMM_Q_LOW_FMAN_V3          0x2A
 265 #define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq)            \
 266         ((dma_thresh_max_commq + 1) / 2)
 267 #define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq)        \
 268         ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 :                \
 269         DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq))
 270
 271 #define DMA_COMM_Q_HIGH_FMAN_V3 0x3f
 272 #define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq)           \
 273         ((dma_thresh_max_commq + 1) * 3 / 4)
 274 #define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq)       \
 275         ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 :               \
 276         DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq))
 277
 278 #define TOTAL_NUM_OF_TASKS_FMAN_V3L     59
 279 #define TOTAL_NUM_OF_TASKS_FMAN_V3H     124
 280 #define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks)     \
 281         ((major == 6) ? ((minor == 1 || minor == 4) ?                   \
 282         TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) :    \
 283         bmi_max_num_of_tasks)
 284
 285 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3          64
 286 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2          32
 287 #define DFLT_DMA_CAM_NUM_OF_ENTRIES(major)                      \
 288         (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 :          \
 289         DMA_CAM_NUM_OF_ENTRIES_FMAN_V2)
 290
 291 #define FM_TIMESTAMP_1_USEC_BIT             8
 292
 293 /* Defines used for enabling/disabling FMan interrupts */
 294 #define ERR_INTR_EN_DMA         0x00010000
 295 #define ERR_INTR_EN_FPM         0x80000000
 296 #define ERR_INTR_EN_BMI         0x00800000
 297 #define ERR_INTR_EN_QMI         0x00400000
 298 #define ERR_INTR_EN_MURAM       0x00040000
 299 #define ERR_INTR_EN_MAC0        0x00004000
 300 #define ERR_INTR_EN_MAC1        0x00002000
 301 #define ERR_INTR_EN_MAC2        0x00001000
 302 #define ERR_INTR_EN_MAC3        0x00000800
 303 #define ERR_INTR_EN_MAC4        0x00000400
 304 #define ERR_INTR_EN_MAC5        0x00000200
 305 #define ERR_INTR_EN_MAC6        0x00000100
 306 #define ERR_INTR_EN_MAC7        0x00000080
 307 #define ERR_INTR_EN_MAC8        0x00008000
 308 #define ERR_INTR_EN_MAC9        0x00000040
 309
 310 #define INTR_EN_QMI             0x40000000
 311 #define INTR_EN_MAC0            0x00080000
 312 #define INTR_EN_MAC1            0x00040000
 313 #define INTR_EN_MAC2            0x00020000
 314 #define INTR_EN_MAC3            0x00010000
 315 #define INTR_EN_MAC4            0x00000040
 316 #define INTR_EN_MAC5            0x00000020
 317 #define INTR_EN_MAC6            0x00000008
 318 #define INTR_EN_MAC7            0x00000002
 319 #define INTR_EN_MAC8            0x00200000
 320 #define INTR_EN_MAC9            0x00100000
 321 #define INTR_EN_REV0            0x00008000
 322 #define INTR_EN_REV1            0x00004000
 323 #define INTR_EN_REV2            0x00002000
 324 #define INTR_EN_REV3            0x00001000
 325 #define INTR_EN_TMR             0x01000000
 326
 327 enum fman_dma_aid_mode {
 328         FMAN_DMA_AID_OUT_PORT_ID = 0,             /* 4 LSB of PORT_ID */
 329         FMAN_DMA_AID_OUT_TNUM                     /* 4 LSB of TNUM */
 330 };
 331
 332 struct fman_iram_regs {
 333         u32 iadd;       /* FM IRAM instruction address register */
 334         u32 idata;      /* FM IRAM instruction data register */
 335         u32 itcfg;      /* FM IRAM timing config register */
 336         u32 iready;     /* FM IRAM ready register */
 337 };
 338
 339 struct fman_fpm_regs {
 340         u32 fmfp_tnc;           /* FPM TNUM Control 0x00 */
 341         u32 fmfp_prc;           /* FPM Port_ID FmCtl Association 0x04 */
 342         u32 fmfp_brkc;          /* FPM Breakpoint Control 0x08 */
 343         u32 fmfp_mxd;           /* FPM Flush Control 0x0c */
 344         u32 fmfp_dist1;         /* FPM Dispatch Thresholds1 0x10 */
 345         u32 fmfp_dist2;         /* FPM Dispatch Thresholds2 0x14 */
 346         u32 fm_epi;             /* FM Error Pending Interrupts 0x18 */
 347         u32 fm_rie;             /* FM Error Interrupt Enable 0x1c */
 348         u32 fmfp_fcev[4];       /* FPM FMan-Controller Event 1-4 0x20-0x2f */
 349         u32 res0030[4];         /* res 0x30 - 0x3f */
 350         u32 fmfp_cee[4];        /* PM FMan-Controller Event 1-4 0x40-0x4f */
 351         u32 res0050[4];         /* res 0x50-0x5f */
 352         u32 fmfp_tsc1;          /* FPM TimeStamp Control1 0x60 */
 353         u32 fmfp_tsc2;          /* FPM TimeStamp Control2 0x64 */
 354         u32 fmfp_tsp;           /* FPM Time Stamp 0x68 */
 355         u32 fmfp_tsf;           /* FPM Time Stamp Fraction 0x6c */
 356         u32 fm_rcr;             /* FM Rams Control 0x70 */
 357         u32 fmfp_extc;          /* FPM External Requests Control 0x74 */
 358         u32 fmfp_ext1;          /* FPM External Requests Config1 0x78 */
 359         u32 fmfp_ext2;          /* FPM External Requests Config2 0x7c */
 360         u32 fmfp_drd[16];       /* FPM Data_Ram Data 0-15 0x80 - 0xbf */
 361         u32 fmfp_dra;           /* FPM Data Ram Access 0xc0 */
 362         u32 fm_ip_rev_1;        /* FM IP Block Revision 1 0xc4 */
 363         u32 fm_ip_rev_2;        /* FM IP Block Revision 2 0xc8 */
 364         u32 fm_rstc;            /* FM Reset Command 0xcc */
 365         u32 fm_cld;             /* FM Classifier Debug 0xd0 */
 366         u32 fm_npi;             /* FM Normal Pending Interrupts 0xd4 */
 367         u32 fmfp_exte;          /* FPM External Requests Enable 0xd8 */
 368         u32 fmfp_ee;            /* FPM Event&Mask 0xdc */
 369         u32 fmfp_cev[4];        /* FPM CPU Event 1-4 0xe0-0xef */
 370         u32 res00f0[4];         /* res 0xf0-0xff */
 371         u32 fmfp_ps[50];        /* FPM Port Status 0x100-0x1c7 */
 372         u32 res01c8[14];        /* res 0x1c8-0x1ff */
 373         u32 fmfp_clfabc;        /* FPM CLFABC 0x200 */
 374         u32 fmfp_clfcc;         /* FPM CLFCC 0x204 */
 375         u32 fmfp_clfaval;       /* FPM CLFAVAL 0x208 */
 376         u32 fmfp_clfbval;       /* FPM CLFBVAL 0x20c */
 377         u32 fmfp_clfcval;       /* FPM CLFCVAL 0x210 */
 378         u32 fmfp_clfamsk;       /* FPM CLFAMSK 0x214 */
 379         u32 fmfp_clfbmsk;       /* FPM CLFBMSK 0x218 */
 380         u32 fmfp_clfcmsk;       /* FPM CLFCMSK 0x21c */
 381         u32 fmfp_clfamc;        /* FPM CLFAMC 0x220 */
 382         u32 fmfp_clfbmc;        /* FPM CLFBMC 0x224 */
 383         u32 fmfp_clfcmc;        /* FPM CLFCMC 0x228 */
 384         u32 fmfp_decceh;        /* FPM DECCEH 0x22c */
 385         u32 res0230[116];       /* res 0x230 - 0x3ff */
 386         u32 fmfp_ts[128];       /* 0x400: FPM Task Status 0x400 - 0x5ff */
 387         u32 res0600[0x400 - 384];
 388 };
 389
 390 struct fman_bmi_regs {
 391         u32 fmbm_init;          /* BMI Initialization 0x00 */
 392         u32 fmbm_cfg1;          /* BMI Configuration 1 0x04 */
 393         u32 fmbm_cfg2;          /* BMI Configuration 2 0x08 */
 394         u32 res000c[5];         /* 0x0c - 0x1f */
 395         u32 fmbm_ievr;          /* Interrupt Event Register 0x20 */
 396         u32 fmbm_ier;           /* Interrupt Enable Register 0x24 */
 397         u32 fmbm_ifr;           /* Interrupt Force Register 0x28 */
 398         u32 res002c[5];         /* 0x2c - 0x3f */
 399         u32 fmbm_arb[8];        /* BMI Arbitration 0x40 - 0x5f */
 400         u32 res0060[12];        /* 0x60 - 0x8f */
 401         u32 fmbm_dtc[3];        /* Debug Trap Counter 0x90 - 0x9b */
 402         u32 res009c;            /* 0x9c */
 403         u32 fmbm_dcv[3][4];     /* Debug Compare val 0xa0-0xcf */
 404         u32 fmbm_dcm[3][4];     /* Debug Compare Mask 0xd0-0xff */
 405         u32 fmbm_gde;           /* BMI Global Debug Enable 0x100 */
 406         u32 fmbm_pp[63];        /* BMI Port Parameters 0x104 - 0x1ff */
 407         u32 res0200;            /* 0x200 */
 408         u32 fmbm_pfs[63];       /* BMI Port FIFO Size 0x204 - 0x2ff */
 409         u32 res0300;            /* 0x300 */
 410         u32 fmbm_spliodn[63];   /* Port Partition ID 0x304 - 0x3ff */
 411 };
 412
 413 struct fman_qmi_regs {
 414         u32 fmqm_gc;            /* General Configuration Register 0x00 */
 415         u32 res0004;            /* 0x04 */
 416         u32 fmqm_eie;           /* Error Interrupt Event Register 0x08 */
 417         u32 fmqm_eien;          /* Error Interrupt Enable Register 0x0c */
 418         u32 fmqm_eif;           /* Error Interrupt Force Register 0x10 */
 419         u32 fmqm_ie;            /* Interrupt Event Register 0x14 */
 420         u32 fmqm_ien;           /* Interrupt Enable Register 0x18 */
 421         u32 fmqm_if;            /* Interrupt Force Register 0x1c */
 422         u32 fmqm_gs;            /* Global Status Register 0x20 */
 423         u32 fmqm_ts;            /* Task Status Register 0x24 */
 424         u32 fmqm_etfc;          /* Enqueue Total Frame Counter 0x28 */
 425         u32 fmqm_dtfc;          /* Dequeue Total Frame Counter 0x2c */
 426         u32 fmqm_dc0;           /* Dequeue Counter 0 0x30 */
 427         u32 fmqm_dc1;           /* Dequeue Counter 1 0x34 */
 428         u32 fmqm_dc2;           /* Dequeue Counter 2 0x38 */
 429         u32 fmqm_dc3;           /* Dequeue Counter 3 0x3c */
 430         u32 fmqm_dfdc;          /* Dequeue FQID from Default Counter 0x40 */
 431         u32 fmqm_dfcc;          /* Dequeue FQID from Context Counter 0x44 */
 432         u32 fmqm_dffc;          /* Dequeue FQID from FD Counter 0x48 */
 433         u32 fmqm_dcc;           /* Dequeue Confirm Counter 0x4c */
 434         u32 res0050[7];         /* 0x50 - 0x6b */
 435         u32 fmqm_tapc;          /* Tnum Aging Period Control 0x6c */
 436         u32 fmqm_dmcvc;         /* Dequeue MAC Command Valid Counter 0x70 */
 437         u32 fmqm_difdcc;        /* Dequeue Invalid FD Command Counter 0x74 */
 438         u32 fmqm_da1v;          /* Dequeue A1 Valid Counter 0x78 */
 439         u32 res007c;            /* 0x7c */
 440         u32 fmqm_dtc;           /* 0x80 Debug Trap Counter 0x80 */
 441         u32 fmqm_efddd;         /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
 442         u32 res0088[2];         /* 0x88 - 0x8f */
 443         struct {
 444                 u32 fmqm_dtcfg1;        /* 0x90 dbg trap cfg 1 Register 0x00 */
 445                 u32 fmqm_dtval1;        /* Debug Trap Value 1 Register 0x04 */
 446                 u32 fmqm_dtm1;          /* Debug Trap Mask 1 Register 0x08 */
 447                 u32 fmqm_dtc1;          /* Debug Trap Counter 1 Register 0x0c */
 448                 u32 fmqm_dtcfg2;        /* dbg Trap cfg 2 Register 0x10 */
 449                 u32 fmqm_dtval2;        /* Debug Trap Value 2 Register 0x14 */
 450                 u32 fmqm_dtm2;          /* Debug Trap Mask 2 Register 0x18 */
 451                 u32 res001c;            /* 0x1c */
 452         } dbg_traps[3];                 /* 0x90 - 0xef */
 453         u8 res00f0[0x400 - 0xf0];       /* 0xf0 - 0x3ff */
 454 };
 455
 456 struct fman_dma_regs {
 457         u32 fmdmsr;     /* FM DMA status register 0x00 */
 458         u32 fmdmmr;     /* FM DMA mode register 0x04 */
 459         u32 fmdmtr;     /* FM DMA bus threshold register 0x08 */
 460         u32 fmdmhy;     /* FM DMA bus hysteresis register 0x0c */
 461         u32 fmdmsetr;   /* FM DMA SOS emergency Threshold Register 0x10 */
 462         u32 fmdmtah;    /* FM DMA transfer bus address high reg 0x14 */
 463         u32 fmdmtal;    /* FM DMA transfer bus address low reg 0x18 */
 464         u32 fmdmtcid;   /* FM DMA transfer bus communication ID reg 0x1c */
 465         u32 fmdmra;     /* FM DMA bus internal ram address register 0x20 */
 466         u32 fmdmrd;     /* FM DMA bus internal ram data register 0x24 */
 467         u32 fmdmwcr;    /* FM DMA CAM watchdog counter value 0x28 */
 468         u32 fmdmebcr;   /* FM DMA CAM base in MURAM register 0x2c */
 469         u32 fmdmccqdr;  /* FM DMA CAM and CMD Queue Debug reg 0x30 */
 470         u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */
 471         u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */
 472         u32 fmdmcqvr3;  /* FM DMA CMD Queue Value register #3 0x3c */
 473         u32 fmdmcqvr4;  /* FM DMA CMD Queue Value register #4 0x40 */
 474         u32 fmdmcqvr5;  /* FM DMA CMD Queue Value register #5 0x44 */
 475         u32 fmdmsefrc;  /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */
 476         u32 fmdmsqfrc;  /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */
 477         u32 fmdmssrc;   /* FM DMA Semaphore SYNC Reject Counter 0x50 */
 478         u32 fmdmdcr;    /* FM DMA Debug Counter 0x54 */
 479         u32 fmdmemsr;   /* FM DMA Emergency Smoother Register 0x58 */
 480         u32 res005c;    /* 0x5c */
 481         u32 fmdmplr[FMAN_LIODN_TBL / 2];        /* DMA LIODN regs 0x60-0xdf */
 482         u32 res00e0[0x400 - 56];
 483 };
 484
 485 struct fman_hwp_regs {
 486         u32 res0000[0x844 / 4];         /* 0x000..0x843 */
 487         u32 fmprrpimac; /* FM Parser Internal memory access control */
 488         u32 res[(0x1000 - 0x848) / 4];  /* 0x848..0xFFF */
 489 };
 490
 491 /* Structure that holds current FMan state.
 492  * Used for saving run time information.
 493  */
 494 struct fman_state_struct {
 495         u8 fm_id;
 496         u16 fm_clk_freq;
 497         struct fman_rev_info rev_info;
 498         bool enabled_time_stamp;
 499         u8 count1_micro_bit;
 500         u8 total_num_of_tasks;
 501         u8 accumulated_num_of_tasks;
 502         u32 accumulated_fifo_size;
 503         u8 accumulated_num_of_open_dmas;
 504         u8 accumulated_num_of_deq_tnums;
 505         u32 exceptions;
 506         u32 extra_fifo_pool_size;
 507         u8 extra_tasks_pool_size;
 508         u8 extra_open_dmas_pool_size;
 509         u16 port_mfl[MAX_NUM_OF_MACS];
 510         u16 mac_mfl[MAX_NUM_OF_MACS];
 511
 512         /* SOC specific */
 513         u32 fm_iram_size;
 514         /* DMA */
 515         u32 dma_thresh_max_commq;
 516         u32 dma_thresh_max_buf;
 517         u32 max_num_of_open_dmas;
 518         /* QMI */
 519         u32 qmi_max_num_of_tnums;
 520         u32 qmi_def_tnums_thresh;
 521         /* BMI */
 522         u32 bmi_max_num_of_tasks;
 523         u32 bmi_max_fifo_size;
 524         /* General */
 525         u32 fm_port_num_of_cg;
 526         u32 num_of_rx_ports;
 527         u32 total_fifo_size;
 528
 529         u32 qman_channel_base;
 530         u32 num_of_qman_channels;
 531
 532         struct resource *res;
 533 };
 534
 535 /* Structure that holds FMan initial configuration */
 536 struct fman_cfg {
 537         u8 disp_limit_tsh;
 538         u8 prs_disp_tsh;
 539         u8 plcr_disp_tsh;
 540         u8 kg_disp_tsh;
 541         u8 bmi_disp_tsh;
 542         u8 qmi_enq_disp_tsh;
 543         u8 qmi_deq_disp_tsh;
 544         u8 fm_ctl1_disp_tsh;
 545         u8 fm_ctl2_disp_tsh;
 546         int dma_cache_override;
 547         enum fman_dma_aid_mode dma_aid_mode;
 548         u32 dma_axi_dbg_num_of_beats;
 549         u32 dma_cam_num_of_entries;
 550         u32 dma_watchdog;
 551         u8 dma_comm_qtsh_asrt_emer;
 552         u32 dma_write_buf_tsh_asrt_emer;
 553         u32 dma_read_buf_tsh_asrt_emer;
 554         u8 dma_comm_qtsh_clr_emer;
 555         u32 dma_write_buf_tsh_clr_emer;
 556         u32 dma_read_buf_tsh_clr_emer;
 557         u32 dma_sos_emergency;
 558         int dma_dbg_cnt_mode;
 559         int catastrophic_err;
 560         int dma_err;
 561         u32 exceptions;
 562         u16 clk_freq;
 563         u32 cam_base_addr;
 564         u32 fifo_base_addr;
 565         u32 total_fifo_size;
 566         u32 total_num_of_tasks;
 567         u32 qmi_def_tnums_thresh;
 568 };
 569
 570 #ifdef CONFIG_DPAA_ERRATUM_A050385
 571 static bool fman_has_err_a050385;
 572 #endif
 573
 574 static irqreturn_t fman_exceptions(struct fman *fman,
 575                                    enum fman_exceptions exception)
 576 {
 577         dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n",
 578                 __func__, fman->state->fm_id, exception);
 579
 580         return IRQ_HANDLED;
 581 }
 582
 583 static irqreturn_t fman_bus_error(struct fman *fman, u8 __maybe_unused port_id,
 584                                   u64 __maybe_unused addr,
 585                                   u8 __maybe_unused tnum,
 586                                   u16 __maybe_unused liodn)
 587 {
 588         dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n",
 589                 __func__, fman->state->fm_id, port_id);
 590
 591         return IRQ_HANDLED;
 592 }
 593
 594 static inline irqreturn_t call_mac_isr(struct fman *fman, u8 id)
 595 {
 596         if (fman->intr_mng[id].isr_cb) {
 597                 fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle);
 598
 599                 return IRQ_HANDLED;
 600         }
 601
 602         return IRQ_NONE;
 603 }
 604
 605 static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id)
 606 {
 607         u8 sw_port_id = 0;
 608
 609         if (hw_port_id >= BASE_TX_PORTID)
 610                 sw_port_id = hw_port_id - BASE_TX_PORTID;
 611         else if (hw_port_id >= BASE_RX_PORTID)
 612                 sw_port_id = hw_port_id - BASE_RX_PORTID;
 613         else
 614                 sw_port_id = 0;
 615
 616         return sw_port_id;
 617 }
 618
 619 static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg,
 620                                        u8 port_id)
 621 {
 622         u32 tmp = 0;
 623
 624         tmp = port_id << FPM_PORT_FM_CTL_PORTID_SHIFT;
 625
 626         tmp |= FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1;
 627
 628         /* order restoration */
 629         if (port_id % 2)
 630                 tmp |= FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 631         else
 632                 tmp |= FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 633
 634         iowrite32be(tmp, &fpm_rg->fmfp_prc);
 635 }
 636
 637 static void set_port_liodn(struct fman *fman, u8 port_id,
 638                            u32 liodn_base, u32 liodn_ofst)
 639 {
 640         u32 tmp;
 641
 642         /* set LIODN base for this port */
 643         tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]);
 644         if (port_id % 2) {
 645                 tmp &= ~DMA_LIODN_BASE_MASK;
 646                 tmp |= liodn_base;
 647         } else {
 648                 tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT);
 649                 tmp |= liodn_base << DMA_LIODN_SHIFT;
 650         }
 651         iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]);
 652         iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]);
 653 }
 654
 655 static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 656 {
 657         u32 tmp;
 658
 659         tmp = ioread32be(&fpm_rg->fm_rcr);
 660         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 661                 iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 662         else
 663                 iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN |
 664                             FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 665 }
 666
 667 static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 668 {
 669         u32 tmp;
 670
 671         tmp = ioread32be(&fpm_rg->fm_rcr);
 672         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 673                 iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 674         else
 675                 iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN),
 676                             &fpm_rg->fm_rcr);
 677 }
 678
 679 static void fman_defconfig(struct fman_cfg *cfg)
 680 {
 681         memset(cfg, 0, sizeof(struct fman_cfg));
 682
 683         cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR;
 684         cfg->dma_err = DEFAULT_DMA_ERR;
 685         cfg->dma_aid_mode = DEFAULT_AID_MODE;
 686         cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW;
 687         cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH;
 688         cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE;
 689         cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES;
 690         cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE;
 691         cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY;
 692         cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG;
 693         cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT;
 694         cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH;
 695         cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH;
 696         cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH;
 697         cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH;
 698         cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH;
 699         cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH;
 700         cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH;
 701         cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH;
 702 }
 703
 704 static int dma_init(struct fman *fman)
 705 {
 706         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
 707         struct fman_cfg *cfg = fman->cfg;
 708         u32 tmp_reg;
 709
 710         /* Init DMA Registers */
 711
 712         /* clear status reg events */
 713         tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
 714                    DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
 715         iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr);
 716
 717         /* configure mode register */
 718         tmp_reg = 0;
 719         tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;
 720         if (cfg->exceptions & EX_DMA_BUS_ERROR)
 721                 tmp_reg |= DMA_MODE_BER;
 722         if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) |
 723             (cfg->exceptions & EX_DMA_READ_ECC) |
 724             (cfg->exceptions & EX_DMA_FM_WRITE_ECC))
 725                 tmp_reg |= DMA_MODE_ECC;
 726         if (cfg->dma_axi_dbg_num_of_beats)
 727                 tmp_reg |= (DMA_MODE_AXI_DBG_MASK &
 728                         ((cfg->dma_axi_dbg_num_of_beats - 1)
 729                         << DMA_MODE_AXI_DBG_SHIFT));
 730
 731         tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) &
 732                 DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT;
 733         tmp_reg |= DMA_MODE_SECURE_PROT;
 734         tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;
 735         tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;
 736
 737         iowrite32be(tmp_reg, &dma_rg->fmdmmr);
 738
 739         /* configure thresholds register */
 740         tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer <<
 741                 DMA_THRESH_COMMQ_SHIFT);
 742         tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer &
 743                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 744         tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer &
 745                 DMA_THRESH_WRITE_INT_BUF_MASK;
 746
 747         iowrite32be(tmp_reg, &dma_rg->fmdmtr);
 748
 749         /* configure hysteresis register */
 750         tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer <<
 751                 DMA_THRESH_COMMQ_SHIFT);
 752         tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer &
 753                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 754         tmp_reg |= cfg->dma_write_buf_tsh_clr_emer &
 755                 DMA_THRESH_WRITE_INT_BUF_MASK;
 756
 757         iowrite32be(tmp_reg, &dma_rg->fmdmhy);
 758
 759         /* configure emergency threshold */
 760         iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr);
 761
 762         /* configure Watchdog */
 763         iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr);
 764
 765         iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr);
 766
 767         /* Allocate MURAM for CAM */
 768         fman->cam_size =
 769                 (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY);
 770         fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size);
 771         if (IS_ERR_VALUE(fman->cam_offset)) {
 772                 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 773                         __func__);
 774                 return -ENOMEM;
 775         }
 776
 777         if (fman->state->rev_info.major == 2) {
 778                 u32 __iomem *cam_base_addr;
 779
 780                 fman_muram_free_mem(fman->muram, fman->cam_offset,
 781                                     fman->cam_size);
 782
 783                 fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128;
 784                 fman->cam_offset = fman_muram_alloc(fman->muram,
 785                                                     fman->cam_size);
 786                 if (IS_ERR_VALUE(fman->cam_offset)) {
 787                         dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 788                                 __func__);
 789                         return -ENOMEM;
 790                 }
 791
 792                 if (fman->cfg->dma_cam_num_of_entries % 8 ||
 793                     fman->cfg->dma_cam_num_of_entries > 32) {
 794                         dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n",
 795                                 __func__);
 796                         return -EINVAL;
 797                 }
 798
 799                 cam_base_addr = (u32 __iomem *)
 800                         fman_muram_offset_to_vbase(fman->muram,
 801                                                    fman->cam_offset);
 802                 iowrite32be(~((1 <<
 803                             (32 - fman->cfg->dma_cam_num_of_entries)) - 1),
 804                             cam_base_addr);
 805         }
 806
 807         fman->cfg->cam_base_addr = fman->cam_offset;
 808
 809         return 0;
 810 }
 811
 812 static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg)
 813 {
 814         u32 tmp_reg;
 815         int i;
 816
 817         /* Init FPM Registers */
 818
 819         tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);
 820         iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);
 821
 822         tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |
 823                    ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) |
 824                    ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) |
 825                    ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT));
 826         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);
 827
 828         tmp_reg =
 829                 (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
 830                  ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) |
 831                  ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) |
 832                  ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT));
 833         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
 834
 835         /* define exceptions and error behavior */
 836         tmp_reg = 0;
 837         /* Clear events */
 838         tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
 839                     FPM_EV_MASK_SINGLE_ECC);
 840         /* enable interrupts */
 841         if (cfg->exceptions & EX_FPM_STALL_ON_TASKS)
 842                 tmp_reg |= FPM_EV_MASK_STALL_EN;
 843         if (cfg->exceptions & EX_FPM_SINGLE_ECC)
 844                 tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
 845         if (cfg->exceptions & EX_FPM_DOUBLE_ECC)
 846                 tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
 847         tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
 848         tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
 849         /* FMan is not halted upon external halt activation */
 850         tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
 851         /* Man is not halted upon  Unrecoverable ECC error behavior */
 852         tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
 853         iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
 854
 855         /* clear all fmCtls event registers */
 856         for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++)
 857                 iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]);
 858
 859         /* RAM ECC -  enable and clear events */
 860         /* first we need to clear all parser memory,
 861          * as it is uninitialized and may cause ECC errors
 862          */
 863         /* event bits */
 864         tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
 865
 866         iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
 867
 868         tmp_reg = 0;
 869         if (cfg->exceptions & EX_IRAM_ECC) {
 870                 tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
 871                 enable_rams_ecc(fpm_rg);
 872         }
 873         if (cfg->exceptions & EX_MURAM_ECC) {
 874                 tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
 875                 enable_rams_ecc(fpm_rg);
 876         }
 877         iowrite32be(tmp_reg, &fpm_rg->fm_rie);
 878 }
 879
 880 static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg,
 881                      struct fman_cfg *cfg)
 882 {
 883         u32 tmp_reg;
 884
 885         /* Init BMI Registers */
 886
 887         /* define common resources */
 888         tmp_reg = cfg->fifo_base_addr;
 889         tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
 890
 891         tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
 892                     BMI_CFG1_FIFO_SIZE_SHIFT);
 893         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
 894
 895         tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) <<
 896                    BMI_CFG2_TASKS_SHIFT;
 897         /* num of DMA's will be dynamically updated when each port is set */
 898         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
 899
 900         /* define unmaskable exceptions, enable and clear events */
 901         tmp_reg = 0;
 902         iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC |
 903                     BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC |
 904                     BMI_ERR_INTR_EN_STATISTICS_RAM_ECC |
 905                     BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr);
 906
 907         if (cfg->exceptions & EX_BMI_LIST_RAM_ECC)
 908                 tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
 909         if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC)
 910                 tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
 911         if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC)
 912                 tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
 913         if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC)
 914                 tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
 915         iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
 916 }
 917
 918 static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg,
 919                      struct fman_cfg *cfg)
 920 {
 921         u32 tmp_reg;
 922
 923         /* Init QMI Registers */
 924
 925         /* Clear error interrupt events */
 926
 927         iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF,
 928                     &qmi_rg->fmqm_eie);
 929         tmp_reg = 0;
 930         if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID)
 931                 tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
 932         if (cfg->exceptions & EX_QMI_DOUBLE_ECC)
 933                 tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
 934         /* enable events */
 935         iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
 936
 937         tmp_reg = 0;
 938         /* Clear interrupt events */
 939         iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie);
 940         if (cfg->exceptions & EX_QMI_SINGLE_ECC)
 941                 tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
 942         /* enable events */
 943         iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
 944 }
 945
 946 static void hwp_init(struct fman_hwp_regs __iomem *hwp_rg)
 947 {
 948         /* enable HW Parser */
 949         iowrite32be(HWP_RPIMAC_PEN, &hwp_rg->fmprrpimac);
 950 }
 951
 952 static int enable(struct fman *fman, struct fman_cfg *cfg)
 953 {
 954         u32 cfg_reg = 0;
 955
 956         /* Enable all modules */
 957
 958         /* clear&enable global counters - calculate reg and save for later,
 959          * because it's the same reg for QMI enable
 960          */
 961         cfg_reg = QMI_CFG_EN_COUNTERS;
 962
 963         /* Set enqueue and dequeue thresholds */
 964         cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh;
 965
 966         iowrite32be(BMI_INIT_START, &fman->bmi_regs->fmbm_init);
 967         iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN,
 968                     &fman->qmi_regs->fmqm_gc);
 969
 970         return 0;
 971 }
 972
 973 static int set_exception(struct fman *fman,
 974                          enum fman_exceptions exception, bool enable)
 975 {
 976         u32 tmp;
 977
 978         switch (exception) {
 979         case FMAN_EX_DMA_BUS_ERROR:
 980                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
 981                 if (enable)
 982                         tmp |= DMA_MODE_BER;
 983                 else
 984                         tmp &= ~DMA_MODE_BER;
 985                 /* disable bus error */
 986                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
 987                 break;
 988         case FMAN_EX_DMA_READ_ECC:
 989         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
 990         case FMAN_EX_DMA_FM_WRITE_ECC:
 991                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
 992                 if (enable)
 993                         tmp |= DMA_MODE_ECC;
 994                 else
 995                         tmp &= ~DMA_MODE_ECC;
 996                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
 997                 break;
 998         case FMAN_EX_FPM_STALL_ON_TASKS:
 999                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1000                 if (enable)
1001                         tmp |= FPM_EV_MASK_STALL_EN;
1002                 else
1003                         tmp &= ~FPM_EV_MASK_STALL_EN;
1004                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1005                 break;
1006         case FMAN_EX_FPM_SINGLE_ECC:
1007                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1008                 if (enable)
1009                         tmp |= FPM_EV_MASK_SINGLE_ECC_EN;
1010                 else
1011                         tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN;
1012                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1013                 break;
1014         case FMAN_EX_FPM_DOUBLE_ECC:
1015                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1016                 if (enable)
1017                         tmp |= FPM_EV_MASK_DOUBLE_ECC_EN;
1018                 else
1019                         tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN;
1020                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1021                 break;
1022         case FMAN_EX_QMI_SINGLE_ECC:
1023                 tmp = ioread32be(&fman->qmi_regs->fmqm_ien);
1024                 if (enable)
1025                         tmp |= QMI_INTR_EN_SINGLE_ECC;
1026                 else
1027                         tmp &= ~QMI_INTR_EN_SINGLE_ECC;
1028                 iowrite32be(tmp, &fman->qmi_regs->fmqm_ien);
1029                 break;
1030         case FMAN_EX_QMI_DOUBLE_ECC:
1031                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1032                 if (enable)
1033                         tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC;
1034                 else
1035                         tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC;
1036                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1037                 break;
1038         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1039                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1040                 if (enable)
1041                         tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1042                 else
1043                         tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1044                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1045                 break;
1046         case FMAN_EX_BMI_LIST_RAM_ECC:
1047                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1048                 if (enable)
1049                         tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
1050                 else
1051                         tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC;
1052                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1053                 break;
1054         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1055                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1056                 if (enable)
1057                         tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1058                 else
1059                         tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1060                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1061                 break;
1062         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1063                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1064                 if (enable)
1065                         tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1066                 else
1067                         tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1068                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1069                 break;
1070         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1071                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1072                 if (enable)
1073                         tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1074                 else
1075                         tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1076                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1077                 break;
1078         case FMAN_EX_IRAM_ECC:
1079                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1080                 if (enable) {
1081                         /* enable ECC if not enabled */
1082                         enable_rams_ecc(fman->fpm_regs);
1083                         /* enable ECC interrupts */
1084                         tmp |= FPM_IRAM_ECC_ERR_EX_EN;
1085                 } else {
1086                         /* ECC mechanism may be disabled,
1087                          * depending on driver status
1088                          */
1089                         disable_rams_ecc(fman->fpm_regs);
1090                         tmp &= ~FPM_IRAM_ECC_ERR_EX_EN;
1091                 }
1092                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1093                 break;
1094         case FMAN_EX_MURAM_ECC:
1095                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1096                 if (enable) {
1097                         /* enable ECC if not enabled */
1098                         enable_rams_ecc(fman->fpm_regs);
1099                         /* enable ECC interrupts */
1100                         tmp |= FPM_MURAM_ECC_ERR_EX_EN;
1101                 } else {
1102                         /* ECC mechanism may be disabled,
1103                          * depending on driver status
1104                          */
1105                         disable_rams_ecc(fman->fpm_regs);
1106                         tmp &= ~FPM_MURAM_ECC_ERR_EX_EN;
1107                 }
1108                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1109                 break;
1110         default:
1111                 return -EINVAL;
1112         }
1113         return 0;
1114 }
1115
1116 static void resume(struct fman_fpm_regs __iomem *fpm_rg)
1117 {
1118         u32 tmp;
1119
1120         tmp = ioread32be(&fpm_rg->fmfp_ee);
1121         /* clear tmp_reg event bits in order not to clear standing events */
1122         tmp &= ~(FPM_EV_MASK_DOUBLE_ECC |
1123                  FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC);
1124         tmp |= FPM_EV_MASK_RELEASE_FM;
1125
1126         iowrite32be(tmp, &fpm_rg->fmfp_ee);
1127 }
1128
1129 static int fill_soc_specific_params(struct fman_state_struct *state)
1130 {
1131         u8 minor = state->rev_info.minor;
1132         /* P4080 - Major 2
1133          * P2041/P3041/P5020/P5040 - Major 3
1134          * Tx/Bx - Major 6
1135          */
1136         switch (state->rev_info.major) {
1137         case 3:
1138                 state->bmi_max_fifo_size        = 160 * 1024;
1139                 state->fm_iram_size             = 64 * 1024;
1140                 state->dma_thresh_max_commq     = 31;
1141                 state->dma_thresh_max_buf       = 127;
1142                 state->qmi_max_num_of_tnums     = 64;
1143                 state->qmi_def_tnums_thresh     = 48;
1144                 state->bmi_max_num_of_tasks     = 128;
1145                 state->max_num_of_open_dmas     = 32;
1146                 state->fm_port_num_of_cg        = 256;
1147                 state->num_of_rx_ports  = 6;
1148                 state->total_fifo_size  = 136 * 1024;
1149                 break;
1150
1151         case 2:
1152                 state->bmi_max_fifo_size        = 160 * 1024;
1153                 state->fm_iram_size             = 64 * 1024;
1154                 state->dma_thresh_max_commq     = 31;
1155                 state->dma_thresh_max_buf       = 127;
1156                 state->qmi_max_num_of_tnums     = 64;
1157                 state->qmi_def_tnums_thresh     = 48;
1158                 state->bmi_max_num_of_tasks     = 128;
1159                 state->max_num_of_open_dmas     = 32;
1160                 state->fm_port_num_of_cg        = 256;
1161                 state->num_of_rx_ports  = 5;
1162                 state->total_fifo_size  = 100 * 1024;
1163                 break;
1164
1165         case 6:
1166                 state->dma_thresh_max_commq     = 83;
1167                 state->dma_thresh_max_buf       = 127;
1168                 state->qmi_max_num_of_tnums     = 64;
1169                 state->qmi_def_tnums_thresh     = 32;
1170                 state->fm_port_num_of_cg        = 256;
1171
1172                 /* FManV3L */
1173                 if (minor == 1 || minor == 4) {
1174                         state->bmi_max_fifo_size        = 192 * 1024;
1175                         state->bmi_max_num_of_tasks     = 64;
1176                         state->max_num_of_open_dmas     = 32;
1177                         state->num_of_rx_ports          = 5;
1178                         if (minor == 1)
1179                                 state->fm_iram_size     = 32 * 1024;
1180                         else
1181                                 state->fm_iram_size     = 64 * 1024;
1182                         state->total_fifo_size          = 156 * 1024;
1183                 }
1184                 /* FManV3H */
1185                 else if (minor == 0 || minor == 2 || minor == 3) {
1186                         state->bmi_max_fifo_size        = 384 * 1024;
1187                         state->fm_iram_size             = 64 * 1024;
1188                         state->bmi_max_num_of_tasks     = 128;
1189                         state->max_num_of_open_dmas     = 84;
1190                         state->num_of_rx_ports          = 8;
1191                         state->total_fifo_size          = 295 * 1024;
1192                 } else {
1193                         pr_err("Unsupported FManv3 version\n");
1194                         return -EINVAL;
1195                 }
1196
1197                 break;
1198         default:
1199                 pr_err("Unsupported FMan version\n");
1200                 return -EINVAL;
1201         }
1202
1203         return 0;
1204 }
1205
1206 static bool is_init_done(struct fman_cfg *cfg)
1207 {
1208         /* Checks if FMan driver parameters were initialized */
1209         if (!cfg)
1210                 return true;
1211
1212         return false;
1213 }
1214
1215 static void free_init_resources(struct fman *fman)
1216 {
1217         if (fman->cam_offset)
1218                 fman_muram_free_mem(fman->muram, fman->cam_offset,
1219                                     fman->cam_size);
1220         if (fman->fifo_offset)
1221                 fman_muram_free_mem(fman->muram, fman->fifo_offset,
1222                                     fman->fifo_size);
1223 }
1224
1225 static irqreturn_t bmi_err_event(struct fman *fman)
1226 {
1227         u32 event, mask, force;
1228         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1229         irqreturn_t ret = IRQ_NONE;
1230
1231         event = ioread32be(&bmi_rg->fmbm_ievr);
1232         mask = ioread32be(&bmi_rg->fmbm_ier);
1233         event &= mask;
1234         /* clear the forced events */
1235         force = ioread32be(&bmi_rg->fmbm_ifr);
1236         if (force & event)
1237                 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr);
1238         /* clear the acknowledged events */
1239         iowrite32be(event, &bmi_rg->fmbm_ievr);
1240
1241         if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC)
1242                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC);
1243         if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC)
1244                 ret = fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC);
1245         if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC)
1246                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC);
1247         if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC)
1248                 ret = fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC);
1249
1250         return ret;
1251 }
1252
1253 static irqreturn_t qmi_err_event(struct fman *fman)
1254 {
1255         u32 event, mask, force;
1256         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1257         irqreturn_t ret = IRQ_NONE;
1258
1259         event = ioread32be(&qmi_rg->fmqm_eie);
1260         mask = ioread32be(&qmi_rg->fmqm_eien);
1261         event &= mask;
1262
1263         /* clear the forced events */
1264         force = ioread32be(&qmi_rg->fmqm_eif);
1265         if (force & event)
1266                 iowrite32be(force & ~event, &qmi_rg->fmqm_eif);
1267         /* clear the acknowledged events */
1268         iowrite32be(event, &qmi_rg->fmqm_eie);
1269
1270         if (event & QMI_ERR_INTR_EN_DOUBLE_ECC)
1271                 ret = fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC);
1272         if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF)
1273                 ret = fman->exception_cb(fman,
1274                                          FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID);
1275
1276         return ret;
1277 }
1278
1279 static irqreturn_t dma_err_event(struct fman *fman)
1280 {
1281         u32 status, mask, com_id;
1282         u8 tnum, port_id, relative_port_id;
1283         u16 liodn;
1284         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
1285         irqreturn_t ret = IRQ_NONE;
1286
1287         status = ioread32be(&dma_rg->fmdmsr);
1288         mask = ioread32be(&dma_rg->fmdmmr);
1289
1290         /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */
1291         if ((mask & DMA_MODE_BER) != DMA_MODE_BER)
1292                 status &= ~DMA_STATUS_BUS_ERR;
1293
1294         /* clear relevant bits if mask has no DMA_MODE_ECC */
1295         if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC)
1296                 status &= ~(DMA_STATUS_FM_SPDAT_ECC |
1297                             DMA_STATUS_READ_ECC |
1298                             DMA_STATUS_SYSTEM_WRITE_ECC |
1299                             DMA_STATUS_FM_WRITE_ECC);
1300
1301         /* clear set events */
1302         iowrite32be(status, &dma_rg->fmdmsr);
1303
1304         if (status & DMA_STATUS_BUS_ERR) {
1305                 u64 addr;
1306
1307                 addr = (u64)ioread32be(&dma_rg->fmdmtal);
1308                 addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32);
1309
1310                 com_id = ioread32be(&dma_rg->fmdmtcid);
1311                 port_id = (u8)(((com_id & DMA_TRANSFER_PORTID_MASK) >>
1312                                DMA_TRANSFER_PORTID_SHIFT));
1313                 relative_port_id =
1314                 hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
1315                 tnum = (u8)((com_id & DMA_TRANSFER_TNUM_MASK) >>
1316                             DMA_TRANSFER_TNUM_SHIFT);
1317                 liodn = (u16)(com_id & DMA_TRANSFER_LIODN_MASK);
1318                 ret = fman->bus_error_cb(fman, relative_port_id, addr, tnum,
1319                                          liodn);
1320         }
1321         if (status & DMA_STATUS_FM_SPDAT_ECC)
1322                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC);
1323         if (status & DMA_STATUS_READ_ECC)
1324                 ret = fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC);
1325         if (status & DMA_STATUS_SYSTEM_WRITE_ECC)
1326                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC);
1327         if (status & DMA_STATUS_FM_WRITE_ECC)
1328                 ret = fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC);
1329
1330         return ret;
1331 }
1332
1333 static irqreturn_t fpm_err_event(struct fman *fman)
1334 {
1335         u32 event;
1336         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1337         irqreturn_t ret = IRQ_NONE;
1338
1339         event = ioread32be(&fpm_rg->fmfp_ee);
1340         /* clear the all occurred events */
1341         iowrite32be(event, &fpm_rg->fmfp_ee);
1342
1343         if ((event & FPM_EV_MASK_DOUBLE_ECC) &&
1344             (event & FPM_EV_MASK_DOUBLE_ECC_EN))
1345                 ret = fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC);
1346         if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN))
1347                 ret = fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS);
1348         if ((event & FPM_EV_MASK_SINGLE_ECC) &&
1349             (event & FPM_EV_MASK_SINGLE_ECC_EN))
1350                 ret = fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC);
1351
1352         return ret;
1353 }
1354
1355 static irqreturn_t muram_err_intr(struct fman *fman)
1356 {
1357         u32 event, mask;
1358         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1359         irqreturn_t ret = IRQ_NONE;
1360
1361         event = ioread32be(&fpm_rg->fm_rcr);
1362         mask = ioread32be(&fpm_rg->fm_rie);
1363
1364         /* clear MURAM event bit (do not clear IRAM event) */
1365         iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr);
1366
1367         if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC))
1368                 ret = fman->exception_cb(fman, FMAN_EX_MURAM_ECC);
1369
1370         return ret;
1371 }
1372
1373 static irqreturn_t qmi_event(struct fman *fman)
1374 {
1375         u32 event, mask, force;
1376         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1377         irqreturn_t ret = IRQ_NONE;
1378
1379         event = ioread32be(&qmi_rg->fmqm_ie);
1380         mask = ioread32be(&qmi_rg->fmqm_ien);
1381         event &= mask;
1382         /* clear the forced events */
1383         force = ioread32be(&qmi_rg->fmqm_if);
1384         if (force & event)
1385                 iowrite32be(force & ~event, &qmi_rg->fmqm_if);
1386         /* clear the acknowledged events */
1387         iowrite32be(event, &qmi_rg->fmqm_ie);
1388
1389         if (event & QMI_INTR_EN_SINGLE_ECC)
1390                 ret = fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC);
1391
1392         return ret;
1393 }
1394
1395 static void enable_time_stamp(struct fman *fman)
1396 {
1397         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1398         u16 fm_clk_freq = fman->state->fm_clk_freq;
1399         u32 tmp, intgr, ts_freq, frac;
1400
1401         ts_freq = (u32)(1 << fman->state->count1_micro_bit);
1402         /* configure timestamp so that bit 8 will count 1 microsecond
1403          * Find effective count rate at TIMESTAMP least significant bits:
1404          * Effective_Count_Rate = 1MHz x 2^8 = 256MHz
1405          * Find frequency ratio between effective count rate and the clock:
1406          * Effective_Count_Rate / CLK e.g. for 600 MHz clock:
1407          * 256/600 = 0.4266666...
1408          */
1409
1410         intgr = ts_freq / fm_clk_freq;
1411         /* we multiply by 2^16 to keep the fraction of the division
1412          * we do not div back, since we write this value as a fraction
1413          * see spec
1414          */
1415
1416         frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq;
1417         /* we check remainder of the division in order to round up if not int */
1418         if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq)
1419                 frac++;
1420
1421         tmp = (intgr << FPM_TS_INT_SHIFT) | (u16)frac;
1422         iowrite32be(tmp, &fpm_rg->fmfp_tsc2);
1423
1424         /* enable timestamp with original clock */
1425         iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1);
1426         fman->state->enabled_time_stamp = true;
1427 }
1428
1429 static int clear_iram(struct fman *fman)
1430 {
1431         struct fman_iram_regs __iomem *iram;
1432         int i, count;
1433
1434         iram = fman->base_addr + IMEM_OFFSET;
1435
1436         /* Enable the auto-increment */
1437         iowrite32be(IRAM_IADD_AIE, &iram->iadd);
1438         count = 100;
1439         do {
1440                 udelay(1);
1441         } while ((ioread32be(&iram->iadd) != IRAM_IADD_AIE) && --count);
1442         if (count == 0)
1443                 return -EBUSY;
1444
1445         for (i = 0; i < (fman->state->fm_iram_size / 4); i++)
1446                 iowrite32be(0xffffffff, &iram->idata);
1447
1448         iowrite32be(fman->state->fm_iram_size - 4, &iram->iadd);
1449         count = 100;
1450         do {
1451                 udelay(1);
1452         } while ((ioread32be(&iram->idata) != 0xffffffff) && --count);
1453         if (count == 0)
1454                 return -EBUSY;
1455
1456         return 0;
1457 }
1458
1459 static u32 get_exception_flag(enum fman_exceptions exception)
1460 {
1461         u32 bit_mask;
1462
1463         switch (exception) {
1464         case FMAN_EX_DMA_BUS_ERROR:
1465                 bit_mask = EX_DMA_BUS_ERROR;
1466                 break;
1467         case FMAN_EX_DMA_SINGLE_PORT_ECC:
1468                 bit_mask = EX_DMA_SINGLE_PORT_ECC;
1469                 break;
1470         case FMAN_EX_DMA_READ_ECC:
1471                 bit_mask = EX_DMA_READ_ECC;
1472                 break;
1473         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
1474                 bit_mask = EX_DMA_SYSTEM_WRITE_ECC;
1475                 break;
1476         case FMAN_EX_DMA_FM_WRITE_ECC:
1477                 bit_mask = EX_DMA_FM_WRITE_ECC;
1478                 break;
1479         case FMAN_EX_FPM_STALL_ON_TASKS:
1480                 bit_mask = EX_FPM_STALL_ON_TASKS;
1481                 break;
1482         case FMAN_EX_FPM_SINGLE_ECC:
1483                 bit_mask = EX_FPM_SINGLE_ECC;
1484                 break;
1485         case FMAN_EX_FPM_DOUBLE_ECC:
1486                 bit_mask = EX_FPM_DOUBLE_ECC;
1487                 break;
1488         case FMAN_EX_QMI_SINGLE_ECC:
1489                 bit_mask = EX_QMI_SINGLE_ECC;
1490                 break;
1491         case FMAN_EX_QMI_DOUBLE_ECC:
1492                 bit_mask = EX_QMI_DOUBLE_ECC;
1493                 break;
1494         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1495                 bit_mask = EX_QMI_DEQ_FROM_UNKNOWN_PORTID;
1496                 break;
1497         case FMAN_EX_BMI_LIST_RAM_ECC:
1498                 bit_mask = EX_BMI_LIST_RAM_ECC;
1499                 break;
1500         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1501                 bit_mask = EX_BMI_STORAGE_PROFILE_ECC;
1502                 break;
1503         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1504                 bit_mask = EX_BMI_STATISTICS_RAM_ECC;
1505                 break;
1506         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1507                 bit_mask = EX_BMI_DISPATCH_RAM_ECC;
1508                 break;
1509         case FMAN_EX_MURAM_ECC:
1510                 bit_mask = EX_MURAM_ECC;
1511                 break;
1512         default:
1513                 bit_mask = 0;
1514                 break;
1515         }
1516
1517         return bit_mask;
1518 }
1519
1520 static int get_module_event(enum fman_event_modules module, u8 mod_id,
1521                             enum fman_intr_type intr_type)
1522 {
1523         int event;
1524
1525         switch (module) {
1526         case FMAN_MOD_MAC:
1527                 if (intr_type == FMAN_INTR_TYPE_ERR)
1528                         event = FMAN_EV_ERR_MAC0 + mod_id;
1529                 else
1530                         event = FMAN_EV_MAC0 + mod_id;
1531                 break;
1532         case FMAN_MOD_FMAN_CTRL:
1533                 if (intr_type == FMAN_INTR_TYPE_ERR)
1534                         event = FMAN_EV_CNT;
1535                 else
1536                         event = (FMAN_EV_FMAN_CTRL_0 + mod_id);
1537                 break;
1538         case FMAN_MOD_DUMMY_LAST:
1539                 event = FMAN_EV_CNT;
1540                 break;
1541         default:
1542                 event = FMAN_EV_CNT;
1543                 break;
1544         }
1545
1546         return event;
1547 }
1548
1549 static int set_size_of_fifo(struct fman *fman, u8 port_id, u32 *size_of_fifo,
1550                             u32 *extra_size_of_fifo)
1551 {
1552         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1553         u32 fifo = *size_of_fifo;
1554         u32 extra_fifo = *extra_size_of_fifo;
1555         u32 tmp;
1556
1557         /* if this is the first time a port requires extra_fifo_pool_size,
1558          * the total extra_fifo_pool_size must be initialized to 1 buffer per
1559          * port
1560          */
1561         if (extra_fifo && !fman->state->extra_fifo_pool_size)
1562                 fman->state->extra_fifo_pool_size =
1563                         fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS;
1564
1565         fman->state->extra_fifo_pool_size =
1566                 max(fman->state->extra_fifo_pool_size, extra_fifo);
1567
1568         /* check that there are enough uncommitted fifo size */
1569         if ((fman->state->accumulated_fifo_size + fifo) >
1570             (fman->state->total_fifo_size -
1571             fman->state->extra_fifo_pool_size)) {
1572                 dev_err(fman->dev, "%s: Requested fifo size and extra size exceed total FIFO size.\n",
1573                         __func__);
1574                 return -EAGAIN;
1575         }
1576
1577         /* Read, modify and write to HW */
1578         tmp = (fifo / FMAN_BMI_FIFO_UNITS - 1) |
1579                ((extra_fifo / FMAN_BMI_FIFO_UNITS) <<
1580                BMI_EXTRA_FIFO_SIZE_SHIFT);
1581         iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]);
1582
1583         /* update accumulated */
1584         fman->state->accumulated_fifo_size += fifo;
1585
1586         return 0;
1587 }
1588
1589 static int set_num_of_tasks(struct fman *fman, u8 port_id, u8 *num_of_tasks,
1590                             u8 *num_of_extra_tasks)
1591 {
1592         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1593         u8 tasks = *num_of_tasks;
1594         u8 extra_tasks = *num_of_extra_tasks;
1595         u32 tmp;
1596
1597         if (extra_tasks)
1598                 fman->state->extra_tasks_pool_size =
1599                 max(fman->state->extra_tasks_pool_size, extra_tasks);
1600
1601         /* check that there are enough uncommitted tasks */
1602         if ((fman->state->accumulated_num_of_tasks + tasks) >
1603             (fman->state->total_num_of_tasks -
1604              fman->state->extra_tasks_pool_size)) {
1605                 dev_err(fman->dev, "%s: Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_tasks.\n",
1606                         __func__, fman->state->fm_id);
1607                 return -EAGAIN;
1608         }
1609         /* update accumulated */
1610         fman->state->accumulated_num_of_tasks += tasks;
1611
1612         /* Write to HW */
1613         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1614             ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
1615         tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) |
1616                 (u32)(extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT));
1617         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1618
1619         return 0;
1620 }
1621
1622 static int set_num_of_open_dmas(struct fman *fman, u8 port_id,
1623                                 u8 *num_of_open_dmas,
1624                                 u8 *num_of_extra_open_dmas)
1625 {
1626         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1627         u8 open_dmas = *num_of_open_dmas;
1628         u8 extra_open_dmas = *num_of_extra_open_dmas;
1629         u8 total_num_dmas = 0, current_val = 0, current_extra_val = 0;
1630         u32 tmp;
1631
1632         if (!open_dmas) {
1633                 /* Configuration according to values in the HW.
1634                  * read the current number of open Dma's
1635                  */
1636                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1637                 current_extra_val = (u8)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >>
1638                                          BMI_EXTRA_NUM_OF_DMAS_SHIFT);
1639
1640                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1641                 current_val = (u8)(((tmp & BMI_NUM_OF_DMAS_MASK) >>
1642                                    BMI_NUM_OF_DMAS_SHIFT) + 1);
1643
1644                 /* This is the first configuration and user did not
1645                  * specify value (!open_dmas), reset values will be used
1646                  * and we just save these values for resource management
1647                  */
1648                 fman->state->extra_open_dmas_pool_size =
1649                         (u8)max(fman->state->extra_open_dmas_pool_size,
1650                                 current_extra_val);
1651                 fman->state->accumulated_num_of_open_dmas += current_val;
1652                 *num_of_open_dmas = current_val;
1653                 *num_of_extra_open_dmas = current_extra_val;
1654                 return 0;
1655         }
1656
1657         if (extra_open_dmas > current_extra_val)
1658                 fman->state->extra_open_dmas_pool_size =
1659                     (u8)max(fman->state->extra_open_dmas_pool_size,
1660                             extra_open_dmas);
1661
1662         if ((fman->state->rev_info.major < 6) &&
1663             (fman->state->accumulated_num_of_open_dmas - current_val +
1664              open_dmas > fman->state->max_num_of_open_dmas)) {
1665                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n",
1666                         __func__, fman->state->fm_id);
1667                 return -EAGAIN;
1668         } else if ((fman->state->rev_info.major >= 6) &&
1669                    !((fman->state->rev_info.major == 6) &&
1670                    (fman->state->rev_info.minor == 0)) &&
1671                    (fman->state->accumulated_num_of_open_dmas -
1672                    current_val + open_dmas >
1673                    fman->state->dma_thresh_max_commq + 1)) {
1674                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n",
1675                         __func__, fman->state->fm_id,
1676                        fman->state->dma_thresh_max_commq + 1);
1677                 return -EAGAIN;
1678         }
1679
1680         WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val);
1681         /* update acummulated */
1682         fman->state->accumulated_num_of_open_dmas -= current_val;
1683         fman->state->accumulated_num_of_open_dmas += open_dmas;
1684
1685         if (fman->state->rev_info.major < 6)
1686                 total_num_dmas =
1687                     (u8)(fman->state->accumulated_num_of_open_dmas +
1688                     fman->state->extra_open_dmas_pool_size);
1689
1690         /* calculate reg */
1691         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1692             ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK);
1693         tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) |
1694                            (extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT));
1695         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1696
1697         /* update total num of DMA's with committed number of open DMAS,
1698          * and max uncommitted pool.
1699          */
1700         if (total_num_dmas) {
1701                 tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
1702                 tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT;
1703                 iowrite32be(tmp, &bmi_rg->fmbm_cfg2);
1704         }
1705
1706         return 0;
1707 }
1708
1709 static int fman_config(struct fman *fman)
1710 {
1711         void __iomem *base_addr;
1712         int err;
1713
1714         base_addr = fman->dts_params.base_addr;
1715
1716         fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL);
1717         if (!fman->state)
1718                 goto err_fm_state;
1719
1720         /* Allocate the FM driver's parameters structure */
1721         fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL);
1722         if (!fman->cfg)
1723                 goto err_fm_drv;
1724
1725         /* Initialize MURAM block */
1726         fman->muram =
1727                 fman_muram_init(fman->dts_params.muram_res.start,
1728                                 resource_size(&fman->dts_params.muram_res));
1729         if (!fman->muram)
1730                 goto err_fm_soc_specific;
1731
1732         /* Initialize FM parameters which will be kept by the driver */
1733         fman->state->fm_id = fman->dts_params.id;
1734         fman->state->fm_clk_freq = fman->dts_params.clk_freq;
1735         fman->state->qman_channel_base = fman->dts_params.qman_channel_base;
1736         fman->state->num_of_qman_channels =
1737                 fman->dts_params.num_of_qman_channels;
1738         fman->state->res = fman->dts_params.res;
1739         fman->exception_cb = fman_exceptions;
1740         fman->bus_error_cb = fman_bus_error;
1741         fman->fpm_regs = base_addr + FPM_OFFSET;
1742         fman->bmi_regs = base_addr + BMI_OFFSET;
1743         fman->qmi_regs = base_addr + QMI_OFFSET;
1744         fman->dma_regs = base_addr + DMA_OFFSET;
1745         fman->hwp_regs = base_addr + HWP_OFFSET;
1746         fman->kg_regs = base_addr + KG_OFFSET;
1747         fman->base_addr = base_addr;
1748
1749         spin_lock_init(&fman->spinlock);
1750         fman_defconfig(fman->cfg);
1751
1752         fman->state->extra_fifo_pool_size = 0;
1753         fman->state->exceptions = (EX_DMA_BUS_ERROR                 |
1754                                         EX_DMA_READ_ECC              |
1755                                         EX_DMA_SYSTEM_WRITE_ECC      |
1756                                         EX_DMA_FM_WRITE_ECC          |
1757                                         EX_FPM_STALL_ON_TASKS        |
1758                                         EX_FPM_SINGLE_ECC            |
1759                                         EX_FPM_DOUBLE_ECC            |
1760                                         EX_QMI_DEQ_FROM_UNKNOWN_PORTID |
1761                                         EX_BMI_LIST_RAM_ECC          |
1762                                         EX_BMI_STORAGE_PROFILE_ECC   |
1763                                         EX_BMI_STATISTICS_RAM_ECC    |
1764                                         EX_MURAM_ECC                 |
1765                                         EX_BMI_DISPATCH_RAM_ECC      |
1766                                         EX_QMI_DOUBLE_ECC            |
1767                                         EX_QMI_SINGLE_ECC);
1768
1769         /* Read FMan revision for future use*/
1770         fman_get_revision(fman, &fman->state->rev_info);
1771
1772         err = fill_soc_specific_params(fman->state);
1773         if (err)
1774                 goto err_fm_soc_specific;
1775
1776         /* FM_AID_MODE_NO_TNUM_SW005 Errata workaround */
1777         if (fman->state->rev_info.major >= 6)
1778                 fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID;
1779
1780         fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh;
1781
1782         fman->state->total_num_of_tasks =
1783         (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major,
1784                                     fman->state->rev_info.minor,
1785                                     fman->state->bmi_max_num_of_tasks);
1786
1787         if (fman->state->rev_info.major < 6) {
1788                 fman->cfg->dma_comm_qtsh_clr_emer =
1789                 (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major,
1790                                         fman->state->dma_thresh_max_commq);
1791
1792                 fman->cfg->dma_comm_qtsh_asrt_emer =
1793                 (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major,
1794                                          fman->state->dma_thresh_max_commq);
1795
1796                 fman->cfg->dma_cam_num_of_entries =
1797                 DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major);
1798
1799                 fman->cfg->dma_read_buf_tsh_clr_emer =
1800                 DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1801
1802                 fman->cfg->dma_read_buf_tsh_asrt_emer =
1803                 DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1804
1805                 fman->cfg->dma_write_buf_tsh_clr_emer =
1806                 DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1807
1808                 fman->cfg->dma_write_buf_tsh_asrt_emer =
1809                 DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1810
1811                 fman->cfg->dma_axi_dbg_num_of_beats =
1812                 DFLT_AXI_DBG_NUM_OF_BEATS;
1813         }
1814
1815         return 0;
1816
1817 err_fm_soc_specific:
1818         kfree(fman->cfg);
1819 err_fm_drv:
1820         kfree(fman->state);
1821 err_fm_state:
1822         kfree(fman);
1823         return -EINVAL;
1824 }
1825
1826 static int fman_reset(struct fman *fman)
1827 {
1828         u32 count;
1829         int err = 0;
1830
1831         if (fman->state->rev_info.major < 6) {
1832                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1833                 /* Wait for reset completion */
1834                 count = 100;
1835                 do {
1836                         udelay(1);
1837                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1838                          FPM_RSTC_FM_RESET) && --count);
1839                 if (count == 0)
1840                         err = -EBUSY;
1841
1842                 goto _return;
1843         } else {
1844 #ifdef CONFIG_PPC
1845                 struct device_node *guts_node;
1846                 struct ccsr_guts __iomem *guts_regs;
1847                 u32 devdisr2, reg;
1848
1849                 /* Errata A007273 */
1850                 guts_node =
1851                         of_find_compatible_node(NULL, NULL,
1852                                                 "fsl,qoriq-device-config-2.0");
1853                 if (!guts_node) {
1854                         dev_err(fman->dev, "%s: Couldn't find guts node\n",
1855                                 __func__);
1856                         goto guts_node;
1857                 }
1858
1859                 guts_regs = of_iomap(guts_node, 0);
1860                 if (!guts_regs) {
1861                         dev_err(fman->dev, "%s: Couldn't map %pOF regs\n",
1862                                 __func__, guts_node);
1863                         goto guts_regs;
1864                 }
1865 #define FMAN1_ALL_MACS_MASK     0xFCC00000
1866 #define FMAN2_ALL_MACS_MASK     0x000FCC00
1867                 /* Read current state */
1868                 devdisr2 = ioread32be(&guts_regs->devdisr2);
1869                 if (fman->dts_params.id == 0)
1870                         reg = devdisr2 & ~FMAN1_ALL_MACS_MASK;
1871                 else
1872                         reg = devdisr2 & ~FMAN2_ALL_MACS_MASK;
1873
1874                 /* Enable all MACs */
1875                 iowrite32be(reg, &guts_regs->devdisr2);
1876 #endif
1877
1878                 /* Perform FMan reset */
1879                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1880
1881                 /* Wait for reset completion */
1882                 count = 100;
1883                 do {
1884                         udelay(1);
1885                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1886                          FPM_RSTC_FM_RESET) && --count);
1887                 if (count == 0) {
1888 #ifdef CONFIG_PPC
1889                         iounmap(guts_regs);
1890                         of_node_put(guts_node);
1891 #endif
1892                         err = -EBUSY;
1893                         goto _return;
1894                 }
1895 #ifdef CONFIG_PPC
1896
1897                 /* Restore devdisr2 value */
1898                 iowrite32be(devdisr2, &guts_regs->devdisr2);
1899
1900                 iounmap(guts_regs);
1901                 of_node_put(guts_node);
1902 #endif
1903
1904                 goto _return;
1905
1906 #ifdef CONFIG_PPC
1907 guts_regs:
1908                 of_node_put(guts_node);
1909 guts_node:
1910                 dev_dbg(fman->dev, "%s: Didn't perform FManV3 reset due to Errata A007273!\n",
1911                         __func__);
1912 #endif
1913         }
1914 _return:
1915         return err;
1916 }
1917
1918 static int fman_init(struct fman *fman)
1919 {
1920         struct fman_cfg *cfg = NULL;
1921         int err = 0, i, count;
1922
1923         if (is_init_done(fman->cfg))
1924                 return -EINVAL;
1925
1926         fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT;
1927
1928         cfg = fman->cfg;
1929
1930         /* clear revision-dependent non existing exception */
1931         if (fman->state->rev_info.major < 6)
1932                 fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC;
1933
1934         if (fman->state->rev_info.major >= 6)
1935                 fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC;
1936
1937         /* clear CPG */
1938         memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0,
1939                   fman->state->fm_port_num_of_cg);
1940
1941         /* Save LIODN info before FMan reset
1942          * Skipping non-existent port 0 (i = 1)
1943          */
1944         for (i = 1; i < FMAN_LIODN_TBL; i++) {
1945                 u32 liodn_base;
1946
1947                 fman->liodn_offset[i] =
1948                         ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]);
1949                 liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]);
1950                 if (i % 2) {
1951                         /* FMDM_PLR LSB holds LIODN base for odd ports */
1952                         liodn_base &= DMA_LIODN_BASE_MASK;
1953                 } else {
1954                         /* FMDM_PLR MSB holds LIODN base for even ports */
1955                         liodn_base >>= DMA_LIODN_SHIFT;
1956                         liodn_base &= DMA_LIODN_BASE_MASK;
1957                 }
1958                 fman->liodn_base[i] = liodn_base;
1959         }
1960
1961         err = fman_reset(fman);
1962         if (err)
1963                 return err;
1964
1965         if (ioread32be(&fman->qmi_regs->fmqm_gs) & QMI_GS_HALT_NOT_BUSY) {
1966                 resume(fman->fpm_regs);
1967                 /* Wait until QMI is not in halt not busy state */
1968                 count = 100;
1969                 do {
1970                         udelay(1);
1971                 } while (((ioread32be(&fman->qmi_regs->fmqm_gs)) &
1972                          QMI_GS_HALT_NOT_BUSY) && --count);
1973                 if (count == 0)
1974                         dev_warn(fman->dev, "%s: QMI is in halt not busy state\n",
1975                                  __func__);
1976         }
1977
1978         if (clear_iram(fman) != 0)
1979                 return -EINVAL;
1980
1981         cfg->exceptions = fman->state->exceptions;
1982
1983         /* Init DMA Registers */
1984
1985         err = dma_init(fman);
1986         if (err != 0) {
1987                 free_init_resources(fman);
1988                 return err;
1989         }
1990
1991         /* Init FPM Registers */
1992         fpm_init(fman->fpm_regs, fman->cfg);
1993
1994         /* define common resources */
1995         /* allocate MURAM for FIFO according to total size */
1996         fman->fifo_offset = fman_muram_alloc(fman->muram,
1997                                              fman->state->total_fifo_size);
1998         if (IS_ERR_VALUE(fman->fifo_offset)) {
1999                 free_init_resources(fman);
2000                 dev_err(fman->dev, "%s: MURAM alloc for BMI FIFO failed\n",
2001                         __func__);
2002                 return -ENOMEM;
2003         }
2004
2005         cfg->fifo_base_addr = fman->fifo_offset;
2006         cfg->total_fifo_size = fman->state->total_fifo_size;
2007         cfg->total_num_of_tasks = fman->state->total_num_of_tasks;
2008         cfg->clk_freq = fman->state->fm_clk_freq;
2009
2010         /* Init BMI Registers */
2011         bmi_init(fman->bmi_regs, fman->cfg);
2012
2013         /* Init QMI Registers */
2014         qmi_init(fman->qmi_regs, fman->cfg);
2015
2016         /* Init HW Parser */
2017         hwp_init(fman->hwp_regs);
2018
2019         /* Init KeyGen */
2020         fman->keygen = keygen_init(fman->kg_regs);
2021         if (!fman->keygen)
2022                 return -EINVAL;
2023
2024         err = enable(fman, cfg);
2025         if (err != 0)
2026                 return err;
2027
2028         enable_time_stamp(fman);
2029
2030         kfree(fman->cfg);
2031         fman->cfg = NULL;
2032
2033         return 0;
2034 }
2035
2036 static int fman_set_exception(struct fman *fman,
2037                               enum fman_exceptions exception, bool enable)
2038 {
2039         u32 bit_mask = 0;
2040
2041         if (!is_init_done(fman->cfg))
2042                 return -EINVAL;
2043
2044         bit_mask = get_exception_flag(exception);
2045         if (bit_mask) {
2046                 if (enable)
2047                         fman->state->exceptions |= bit_mask;
2048                 else
2049                         fman->state->exceptions &= ~bit_mask;
2050         } else {
2051                 dev_err(fman->dev, "%s: Undefined exception (%d)\n",
2052                         __func__, exception);
2053                 return -EINVAL;
2054         }
2055
2056         return set_exception(fman, exception, enable);
2057 }
2058
2059 /**
2060  * fman_register_intr
2061  * @fman:       A Pointer to FMan device
2062  * @mod:        Calling module
2063  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2064  * @intr_type:  Interrupt type (error/normal) selection.
2065  * @f_isr:      The interrupt service routine.
2066  * @h_src_arg:  Argument to be passed to f_isr.
2067  *
2068  * Used to register an event handler to be processed by FMan
2069  *
2070  * Return: 0 on success; Error code otherwise.
2071  */
2072 void fman_register_intr(struct fman *fman, enum fman_event_modules module,
2073                         u8 mod_id, enum fman_intr_type intr_type,
2074                         void (*isr_cb)(void *src_arg), void *src_arg)
2075 {
2076         int event = 0;
2077
2078         event = get_module_event(module, mod_id, intr_type);
2079         WARN_ON(event >= FMAN_EV_CNT);
2080
2081         /* register in local FM structure */
2082         fman->intr_mng[event].isr_cb = isr_cb;
2083         fman->intr_mng[event].src_handle = src_arg;
2084 }
2085 EXPORT_SYMBOL(fman_register_intr);
2086
2087 /**
2088  * fman_unregister_intr
2089  * @fman:       A Pointer to FMan device
2090  * @mod:        Calling module
2091  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2092  * @intr_type:  Interrupt type (error/normal) selection.
2093  *
2094  * Used to unregister an event handler to be processed by FMan
2095  *
2096  * Return: 0 on success; Error code otherwise.
2097  */
2098 void fman_unregister_intr(struct fman *fman, enum fman_event_modules module,
2099                           u8 mod_id, enum fman_intr_type intr_type)
2100 {
2101         int event = 0;
2102
2103         event = get_module_event(module, mod_id, intr_type);
2104         WARN_ON(event >= FMAN_EV_CNT);
2105
2106         fman->intr_mng[event].isr_cb = NULL;
2107         fman->intr_mng[event].src_handle = NULL;
2108 }
2109 EXPORT_SYMBOL(fman_unregister_intr);
2110
2111 /**
2112  * fman_set_port_params
2113  * @fman:               A Pointer to FMan device
2114  * @port_params:        Port parameters
2115  *
2116  * Used by FMan Port to pass parameters to the FMan
2117  *
2118  * Return: 0 on success; Error code otherwise.
2119  */
2120 int fman_set_port_params(struct fman *fman,
2121                          struct fman_port_init_params *port_params)
2122 {
2123         int err;
2124         unsigned long flags;
2125         u8 port_id = port_params->port_id, mac_id;
2126
2127         spin_lock_irqsave(&fman->spinlock, flags);
2128
2129         err = set_num_of_tasks(fman, port_params->port_id,
2130                                &port_params->num_of_tasks,
2131                                &port_params->num_of_extra_tasks);
2132         if (err)
2133                 goto return_err;
2134
2135         /* TX Ports */
2136         if (port_params->port_type != FMAN_PORT_TYPE_RX) {
2137                 u32 enq_th, deq_th, reg;
2138
2139                 /* update qmi ENQ/DEQ threshold */
2140                 fman->state->accumulated_num_of_deq_tnums +=
2141                         port_params->deq_pipeline_depth;
2142                 enq_th = (ioread32be(&fman->qmi_regs->fmqm_gc) &
2143                           QMI_CFG_ENQ_MASK) >> QMI_CFG_ENQ_SHIFT;
2144                 /* if enq_th is too big, we reduce it to the max value
2145                  * that is still 0
2146                  */
2147                 if (enq_th >= (fman->state->qmi_max_num_of_tnums -
2148                     fman->state->accumulated_num_of_deq_tnums)) {
2149                         enq_th =
2150                         fman->state->qmi_max_num_of_tnums -
2151                         fman->state->accumulated_num_of_deq_tnums - 1;
2152
2153                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2154                         reg &= ~QMI_CFG_ENQ_MASK;
2155                         reg |= (enq_th << QMI_CFG_ENQ_SHIFT);
2156                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2157                 }
2158
2159                 deq_th = ioread32be(&fman->qmi_regs->fmqm_gc) &
2160                                     QMI_CFG_DEQ_MASK;
2161                 /* if deq_th is too small, we enlarge it to the min
2162                  * value that is still 0.
2163                  * depTh may not be larger than 63
2164                  * (fman->state->qmi_max_num_of_tnums-1).
2165                  */
2166                 if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) &&
2167                     (deq_th < fman->state->qmi_max_num_of_tnums - 1)) {
2168                         deq_th = fman->state->accumulated_num_of_deq_tnums + 1;
2169                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2170                         reg &= ~QMI_CFG_DEQ_MASK;
2171                         reg |= deq_th;
2172                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2173                 }
2174         }
2175
2176         err = set_size_of_fifo(fman, port_params->port_id,
2177                                &port_params->size_of_fifo,
2178                                &port_params->extra_size_of_fifo);
2179         if (err)
2180                 goto return_err;
2181
2182         err = set_num_of_open_dmas(fman, port_params->port_id,
2183                                    &port_params->num_of_open_dmas,
2184                                    &port_params->num_of_extra_open_dmas);
2185         if (err)
2186                 goto return_err;
2187
2188         set_port_liodn(fman, port_id, fman->liodn_base[port_id],
2189                        fman->liodn_offset[port_id]);
2190
2191         if (fman->state->rev_info.major < 6)
2192                 set_port_order_restoration(fman->fpm_regs, port_id);
2193
2194         mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
2195
2196         if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) {
2197                 fman->state->port_mfl[mac_id] = port_params->max_frame_length;
2198         } else {
2199                 dev_warn(fman->dev, "%s: Port (%d) max_frame_length is smaller than MAC (%d) current MTU\n",
2200                          __func__, port_id, mac_id);
2201                 err = -EINVAL;
2202                 goto return_err;
2203         }
2204
2205         spin_unlock_irqrestore(&fman->spinlock, flags);
2206
2207         return 0;
2208
2209 return_err:
2210         spin_unlock_irqrestore(&fman->spinlock, flags);
2211         return err;
2212 }
2213 EXPORT_SYMBOL(fman_set_port_params);
2214
2215 /**
2216  * fman_reset_mac
2217  * @fman:       A Pointer to FMan device
2218  * @mac_id:     MAC id to be reset
2219  *
2220  * Reset a specific MAC
2221  *
2222  * Return: 0 on success; Error code otherwise.
2223  */
2224 int fman_reset_mac(struct fman *fman, u8 mac_id)
2225 {
2226         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
2227         u32 msk, timeout = 100;
2228
2229         if (fman->state->rev_info.major >= 6) {
2230                 dev_err(fman->dev, "%s: FMan MAC reset no available for FMan V3!\n",
2231                         __func__);
2232                 return -EINVAL;
2233         }
2234
2235         /* Get the relevant bit mask */
2236         switch (mac_id) {
2237         case 0:
2238                 msk = FPM_RSTC_MAC0_RESET;
2239                 break;
2240         case 1:
2241                 msk = FPM_RSTC_MAC1_RESET;
2242                 break;
2243         case 2:
2244                 msk = FPM_RSTC_MAC2_RESET;
2245                 break;
2246         case 3:
2247                 msk = FPM_RSTC_MAC3_RESET;
2248                 break;
2249         case 4:
2250                 msk = FPM_RSTC_MAC4_RESET;
2251                 break;
2252         case 5:
2253                 msk = FPM_RSTC_MAC5_RESET;
2254                 break;
2255         case 6:
2256                 msk = FPM_RSTC_MAC6_RESET;
2257                 break;
2258         case 7:
2259                 msk = FPM_RSTC_MAC7_RESET;
2260                 break;
2261         case 8:
2262                 msk = FPM_RSTC_MAC8_RESET;
2263                 break;
2264         case 9:
2265                 msk = FPM_RSTC_MAC9_RESET;
2266                 break;
2267         default:
2268                 dev_warn(fman->dev, "%s: Illegal MAC Id [%d]\n",
2269                          __func__, mac_id);
2270                 return -EINVAL;
2271         }
2272
2273         /* reset */
2274         iowrite32be(msk, &fpm_rg->fm_rstc);
2275         while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout)
2276                 udelay(10);
2277
2278         if (!timeout)
2279                 return -EIO;
2280
2281         return 0;
2282 }
2283 EXPORT_SYMBOL(fman_reset_mac);
2284
2285 /**
2286  * fman_set_mac_max_frame
2287  * @fman:       A Pointer to FMan device
2288  * @mac_id:     MAC id
2289  * @mfl:        Maximum frame length
2290  *
2291  * Set maximum frame length of specific MAC in FMan driver
2292  *
2293  * Return: 0 on success; Error code otherwise.
2294  */
2295 int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl)
2296 {
2297         /* if port is already initialized, check that MaxFrameLength is smaller
2298          * or equal to the port's max
2299          */
2300         if ((!fman->state->port_mfl[mac_id]) ||
2301             (mfl <= fman->state->port_mfl[mac_id])) {
2302                 fman->state->mac_mfl[mac_id] = mfl;
2303         } else {
2304                 dev_warn(fman->dev, "%s: MAC max_frame_length is larger than Port max_frame_length\n",
2305                          __func__);
2306                 return -EINVAL;
2307         }
2308         return 0;
2309 }
2310 EXPORT_SYMBOL(fman_set_mac_max_frame);
2311
2312 /**
2313  * fman_get_clock_freq
2314  * @fman:       A Pointer to FMan device
2315  *
2316  * Get FMan clock frequency
2317  *
2318  * Return: FMan clock frequency
2319  */
2320 u16 fman_get_clock_freq(struct fman *fman)
2321 {
2322         return fman->state->fm_clk_freq;
2323 }
2324
2325 /**
2326  * fman_get_bmi_max_fifo_size
2327  * @fman:       A Pointer to FMan device
2328  *
2329  * Get FMan maximum FIFO size
2330  *
2331  * Return: FMan Maximum FIFO size
2332  */
2333 u32 fman_get_bmi_max_fifo_size(struct fman *fman)
2334 {
2335         return fman->state->bmi_max_fifo_size;
2336 }
2337 EXPORT_SYMBOL(fman_get_bmi_max_fifo_size);
2338
2339 /**
2340  * fman_get_revision
2341  * @fman                - Pointer to the FMan module
2342  * @rev_info            - A structure of revision information parameters.
2343  *
2344  * Returns the FM revision
2345  *
2346  * Allowed only following fman_init().
2347  *
2348  * Return: 0 on success; Error code otherwise.
2349  */
2350 void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info)
2351 {
2352         u32 tmp;
2353
2354         tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1);
2355         rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >>
2356                                 FPM_REV1_MAJOR_SHIFT);
2357         rev_info->minor = tmp & FPM_REV1_MINOR_MASK;
2358 }
2359 EXPORT_SYMBOL(fman_get_revision);
2360
2361 /**
2362  * fman_get_qman_channel_id
2363  * @fman:       A Pointer to FMan device
2364  * @port_id:    Port id
2365  *
2366  * Get QMan channel ID associated to the Port id
2367  *
2368  * Return: QMan channel ID
2369  */
2370 u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id)
2371 {
2372         int i;
2373
2374         if (fman->state->rev_info.major >= 6) {
2375                 static const u32 port_ids[] = {
2376                         0x30, 0x31, 0x28, 0x29, 0x2a, 0x2b,
2377                         0x2c, 0x2d, 0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2378                 };
2379
2380                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2381                         if (port_ids[i] == port_id)
2382                                 break;
2383                 }
2384         } else {
2385                 static const u32 port_ids[] = {
2386                         0x30, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x1,
2387                         0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2388                 };
2389
2390                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2391                         if (port_ids[i] == port_id)
2392                                 break;
2393                 }
2394         }
2395
2396         if (i == fman->state->num_of_qman_channels)
2397                 return 0;
2398
2399         return fman->state->qman_channel_base + i;
2400 }
2401 EXPORT_SYMBOL(fman_get_qman_channel_id);
2402
2403 /**
2404  * fman_get_mem_region
2405  * @fman:       A Pointer to FMan device
2406  *
2407  * Get FMan memory region
2408  *
2409  * Return: A structure with FMan memory region information
2410  */
2411 struct resource *fman_get_mem_region(struct fman *fman)
2412 {
2413         return fman->state->res;
2414 }
2415 EXPORT_SYMBOL(fman_get_mem_region);
2416
2417 /* Bootargs defines */
2418 /* Extra headroom for RX buffers - Default, min and max */
2419 #define FSL_FM_RX_EXTRA_HEADROOM        64
2420 #define FSL_FM_RX_EXTRA_HEADROOM_MIN    16
2421 #define FSL_FM_RX_EXTRA_HEADROOM_MAX    384
2422
2423 /* Maximum frame length */
2424 #define FSL_FM_MAX_FRAME_SIZE                   1522
2425 #define FSL_FM_MAX_POSSIBLE_FRAME_SIZE          9600
2426 #define FSL_FM_MIN_POSSIBLE_FRAME_SIZE          64
2427
2428 /* Extra headroom for Rx buffers.
2429  * FMan is instructed to allocate, on the Rx path, this amount of
2430  * space at the beginning of a data buffer, beside the DPA private
2431  * data area and the IC fields.
2432  * Does not impact Tx buffer layout.
2433  * Configurable from bootargs. 64 by default, it's needed on
2434  * particular forwarding scenarios that add extra headers to the
2435  * forwarded frame.
2436  */
2437 static int fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2438 module_param(fsl_fm_rx_extra_headroom, int, 0);
2439 MODULE_PARM_DESC(fsl_fm_rx_extra_headroom, "Extra headroom for Rx buffers");
2440
2441 /* Max frame size, across all interfaces.
2442  * Configurable from bootargs, to avoid allocating oversized (socket)
2443  * buffers when not using jumbo frames.
2444  * Must be large enough to accommodate the network MTU, but small enough
2445  * to avoid wasting skb memory.
2446  *
2447  * Could be overridden once, at boot-time, via the
2448  * fm_set_max_frm() callback.
2449  */
2450 static int fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2451 module_param(fsl_fm_max_frm, int, 0);
2452 MODULE_PARM_DESC(fsl_fm_max_frm, "Maximum frame size, across all interfaces");
2453
2454 /**
2455  * fman_get_max_frm
2456  *
2457  * Return: Max frame length configured in the FM driver
2458  */
2459 u16 fman_get_max_frm(void)
2460 {
2461         static bool fm_check_mfl;
2462
2463         if (!fm_check_mfl) {
2464                 if (fsl_fm_max_frm > FSL_FM_MAX_POSSIBLE_FRAME_SIZE ||
2465                     fsl_fm_max_frm < FSL_FM_MIN_POSSIBLE_FRAME_SIZE) {
2466                         pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2467                                 fsl_fm_max_frm,
2468                                 FSL_FM_MIN_POSSIBLE_FRAME_SIZE,
2469                                 FSL_FM_MAX_POSSIBLE_FRAME_SIZE,
2470                                 FSL_FM_MAX_FRAME_SIZE);
2471                         fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2472                 }
2473                 fm_check_mfl = true;
2474         }
2475
2476         return fsl_fm_max_frm;
2477 }
2478 EXPORT_SYMBOL(fman_get_max_frm);
2479
2480 /**
2481  * fman_get_rx_extra_headroom
2482  *
2483  * Return: Extra headroom size configured in the FM driver
2484  */
2485 int fman_get_rx_extra_headroom(void)
2486 {
2487         static bool fm_check_rx_extra_headroom;
2488
2489         if (!fm_check_rx_extra_headroom) {
2490                 if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX ||
2491                     fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN) {
2492                         pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2493                                 fsl_fm_rx_extra_headroom,
2494                                 FSL_FM_RX_EXTRA_HEADROOM_MIN,
2495                                 FSL_FM_RX_EXTRA_HEADROOM_MAX,
2496                                 FSL_FM_RX_EXTRA_HEADROOM);
2497                         fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2498                 }
2499
2500                 fm_check_rx_extra_headroom = true;
2501                 fsl_fm_rx_extra_headroom = ALIGN(fsl_fm_rx_extra_headroom, 16);
2502         }
2503
2504         return fsl_fm_rx_extra_headroom;
2505 }
2506 EXPORT_SYMBOL(fman_get_rx_extra_headroom);
2507
2508 /**
2509  * fman_bind
2510  * @dev:        FMan OF device pointer
2511  *
2512  * Bind to a specific FMan device.
2513  *
2514  * Allowed only after the port was created.
2515  *
2516  * Return: A pointer to the FMan device
2517  */
2518 struct fman *fman_bind(struct device *fm_dev)
2519 {
2520         return (struct fman *)(dev_get_drvdata(get_device(fm_dev)));
2521 }
2522 EXPORT_SYMBOL(fman_bind);
2523
2524 #ifdef CONFIG_DPAA_ERRATUM_A050385
2525 bool fman_has_errata_a050385(void)
2526 {
2527         return fman_has_err_a050385;
2528 }
2529 EXPORT_SYMBOL(fman_has_errata_a050385);
2530 #endif
2531
2532 static irqreturn_t fman_err_irq(int irq, void *handle)
2533 {
2534         struct fman *fman = (struct fman *)handle;
2535         u32 pending;
2536         struct fman_fpm_regs __iomem *fpm_rg;
2537         irqreturn_t single_ret, ret = IRQ_NONE;
2538
2539         if (!is_init_done(fman->cfg))
2540                 return IRQ_NONE;
2541
2542         fpm_rg = fman->fpm_regs;
2543
2544         /* error interrupts */
2545         pending = ioread32be(&fpm_rg->fm_epi);
2546         if (!pending)
2547                 return IRQ_NONE;
2548
2549         if (pending & ERR_INTR_EN_BMI) {
2550                 single_ret = bmi_err_event(fman);
2551                 if (single_ret == IRQ_HANDLED)
2552                         ret = IRQ_HANDLED;
2553         }
2554         if (pending & ERR_INTR_EN_QMI) {
2555                 single_ret = qmi_err_event(fman);
2556                 if (single_ret == IRQ_HANDLED)
2557                         ret = IRQ_HANDLED;
2558         }
2559         if (pending & ERR_INTR_EN_FPM) {
2560                 single_ret = fpm_err_event(fman);
2561                 if (single_ret == IRQ_HANDLED)
2562                         ret = IRQ_HANDLED;
2563         }
2564         if (pending & ERR_INTR_EN_DMA) {
2565                 single_ret = dma_err_event(fman);
2566                 if (single_ret == IRQ_HANDLED)
2567                         ret = IRQ_HANDLED;
2568         }
2569         if (pending & ERR_INTR_EN_MURAM) {
2570                 single_ret = muram_err_intr(fman);
2571                 if (single_ret == IRQ_HANDLED)
2572                         ret = IRQ_HANDLED;
2573         }
2574
2575         /* MAC error interrupts */
2576         if (pending & ERR_INTR_EN_MAC0) {
2577                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 0);
2578                 if (single_ret == IRQ_HANDLED)
2579                         ret = IRQ_HANDLED;
2580         }
2581         if (pending & ERR_INTR_EN_MAC1) {
2582                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 1);
2583                 if (single_ret == IRQ_HANDLED)
2584                         ret = IRQ_HANDLED;
2585         }
2586         if (pending & ERR_INTR_EN_MAC2) {
2587                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 2);
2588                 if (single_ret == IRQ_HANDLED)
2589                         ret = IRQ_HANDLED;
2590         }
2591         if (pending & ERR_INTR_EN_MAC3) {
2592                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 3);
2593                 if (single_ret == IRQ_HANDLED)
2594                         ret = IRQ_HANDLED;
2595         }
2596         if (pending & ERR_INTR_EN_MAC4) {
2597                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 4);
2598                 if (single_ret == IRQ_HANDLED)
2599                         ret = IRQ_HANDLED;
2600         }
2601         if (pending & ERR_INTR_EN_MAC5) {
2602                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 5);
2603                 if (single_ret == IRQ_HANDLED)
2604                         ret = IRQ_HANDLED;
2605         }
2606         if (pending & ERR_INTR_EN_MAC6) {
2607                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 6);
2608                 if (single_ret == IRQ_HANDLED)
2609                         ret = IRQ_HANDLED;
2610         }
2611         if (pending & ERR_INTR_EN_MAC7) {
2612                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 7);
2613                 if (single_ret == IRQ_HANDLED)
2614                         ret = IRQ_HANDLED;
2615         }
2616         if (pending & ERR_INTR_EN_MAC8) {
2617                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 8);
2618                 if (single_ret == IRQ_HANDLED)
2619                         ret = IRQ_HANDLED;
2620         }
2621         if (pending & ERR_INTR_EN_MAC9) {
2622                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 9);
2623                 if (single_ret == IRQ_HANDLED)
2624                         ret = IRQ_HANDLED;
2625         }
2626
2627         return ret;
2628 }
2629
2630 static irqreturn_t fman_irq(int irq, void *handle)
2631 {
2632         struct fman *fman = (struct fman *)handle;
2633         u32 pending;
2634         struct fman_fpm_regs __iomem *fpm_rg;
2635         irqreturn_t single_ret, ret = IRQ_NONE;
2636
2637         if (!is_init_done(fman->cfg))
2638                 return IRQ_NONE;
2639
2640         fpm_rg = fman->fpm_regs;
2641
2642         /* normal interrupts */
2643         pending = ioread32be(&fpm_rg->fm_npi);
2644         if (!pending)
2645                 return IRQ_NONE;
2646
2647         if (pending & INTR_EN_QMI) {
2648                 single_ret = qmi_event(fman);
2649                 if (single_ret == IRQ_HANDLED)
2650                         ret = IRQ_HANDLED;
2651         }
2652
2653         /* MAC interrupts */
2654         if (pending & INTR_EN_MAC0) {
2655                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 0);
2656                 if (single_ret == IRQ_HANDLED)
2657                         ret = IRQ_HANDLED;
2658         }
2659         if (pending & INTR_EN_MAC1) {
2660                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 1);
2661                 if (single_ret == IRQ_HANDLED)
2662                         ret = IRQ_HANDLED;
2663         }
2664         if (pending & INTR_EN_MAC2) {
2665                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 2);
2666                 if (single_ret == IRQ_HANDLED)
2667                         ret = IRQ_HANDLED;
2668         }
2669         if (pending & INTR_EN_MAC3) {
2670                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 3);
2671                 if (single_ret == IRQ_HANDLED)
2672                         ret = IRQ_HANDLED;
2673         }
2674         if (pending & INTR_EN_MAC4) {
2675                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 4);
2676                 if (single_ret == IRQ_HANDLED)
2677                         ret = IRQ_HANDLED;
2678         }
2679         if (pending & INTR_EN_MAC5) {
2680                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 5);
2681                 if (single_ret == IRQ_HANDLED)
2682                         ret = IRQ_HANDLED;
2683         }
2684         if (pending & INTR_EN_MAC6) {
2685                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 6);
2686                 if (single_ret == IRQ_HANDLED)
2687                         ret = IRQ_HANDLED;
2688         }
2689         if (pending & INTR_EN_MAC7) {
2690                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 7);
2691                 if (single_ret == IRQ_HANDLED)
2692                         ret = IRQ_HANDLED;
2693         }
2694         if (pending & INTR_EN_MAC8) {
2695                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 8);
2696                 if (single_ret == IRQ_HANDLED)
2697                         ret = IRQ_HANDLED;
2698         }
2699         if (pending & INTR_EN_MAC9) {
2700                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 9);
2701                 if (single_ret == IRQ_HANDLED)
2702                         ret = IRQ_HANDLED;
2703         }
2704
2705         return ret;
2706 }
2707
2708 static const struct of_device_id fman_muram_match[] = {
2709         {
2710                 .compatible = "fsl,fman-muram"},
2711         {}
2712 };
2713 MODULE_DEVICE_TABLE(of, fman_muram_match);
2714
2715 static struct fman *read_dts_node(struct platform_device *of_dev)
2716 {
2717         struct fman *fman;
2718         struct device_node *fm_node, *muram_node;
2719         struct resource *res;
2720         u32 val, range[2];
2721         int err, irq;
2722         struct clk *clk;
2723         u32 clk_rate;
2724         phys_addr_t phys_base_addr;
2725         resource_size_t mem_size;
2726
2727         fman = kzalloc(sizeof(*fman), GFP_KERNEL);
2728         if (!fman)
2729                 return NULL;
2730
2731         fm_node = of_node_get(of_dev->dev.of_node);
2732
2733         err = of_property_read_u32(fm_node, "cell-index", &val);
2734         if (err) {
2735                 dev_err(&of_dev->dev, "%s: failed to read cell-index for %pOF\n",
2736                         __func__, fm_node);
2737                 goto fman_node_put;
2738         }
2739         fman->dts_params.id = (u8)val;
2740
2741         /* Get the FM interrupt */
2742         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 0);
2743         if (!res) {
2744                 dev_err(&of_dev->dev, "%s: Can't get FMan IRQ resource\n",
2745                         __func__);
2746                 goto fman_node_put;
2747         }
2748         irq = res->start;
2749
2750         /* Get the FM error interrupt */
2751         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 1);
2752         if (!res) {
2753                 dev_err(&of_dev->dev, "%s: Can't get FMan Error IRQ resource\n",
2754                         __func__);
2755                 goto fman_node_put;
2756         }
2757         fman->dts_params.err_irq = res->start;
2758
2759         /* Get the FM address */
2760         res = platform_get_resource(of_dev, IORESOURCE_MEM, 0);
2761         if (!res) {
2762                 dev_err(&of_dev->dev, "%s: Can't get FMan memory resource\n",
2763                         __func__);
2764                 goto fman_node_put;
2765         }
2766
2767         phys_base_addr = res->start;
2768         mem_size = resource_size(res);
2769
2770         clk = of_clk_get(fm_node, 0);
2771         if (IS_ERR(clk)) {
2772                 dev_err(&of_dev->dev, "%s: Failed to get FM%d clock structure\n",
2773                         __func__, fman->dts_params.id);
2774                 goto fman_node_put;
2775         }
2776
2777         clk_rate = clk_get_rate(clk);
2778         if (!clk_rate) {
2779                 dev_err(&of_dev->dev, "%s: Failed to determine FM%d clock rate\n",
2780                         __func__, fman->dts_params.id);
2781                 goto fman_node_put;
2782         }
2783         /* Rounding to MHz */
2784         fman->dts_params.clk_freq = DIV_ROUND_UP(clk_rate, 1000000);
2785
2786         err = of_property_read_u32_array(fm_node, "fsl,qman-channel-range",
2787                                          &range[0], 2);
2788         if (err) {
2789                 dev_err(&of_dev->dev, "%s: failed to read fsl,qman-channel-range for %pOF\n",
2790                         __func__, fm_node);
2791                 goto fman_node_put;
2792         }
2793         fman->dts_params.qman_channel_base = range[0];
2794         fman->dts_params.num_of_qman_channels = range[1];
2795
2796         /* Get the MURAM base address and size */
2797         muram_node = of_find_matching_node(fm_node, fman_muram_match);
2798         if (!muram_node) {
2799                 dev_err(&of_dev->dev, "%s: could not find MURAM node\n",
2800                         __func__);
2801                 goto fman_free;
2802         }
2803
2804         err = of_address_to_resource(muram_node, 0,
2805                                      &fman->dts_params.muram_res);
2806         if (err) {
2807                 of_node_put(muram_node);
2808                 dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n",
2809                         __func__, err);
2810                 goto fman_free;
2811         }
2812
2813         of_node_put(muram_node);
2814
2815         err = devm_request_irq(&of_dev->dev, irq, fman_irq, 0, "fman", fman);
2816         if (err < 0) {
2817                 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2818                         __func__, irq, err);
2819                 goto fman_free;
2820         }
2821
2822         if (fman->dts_params.err_irq != 0) {
2823                 err = devm_request_irq(&of_dev->dev, fman->dts_params.err_irq,
2824                                        fman_err_irq, IRQF_SHARED,
2825                                        "fman-err", fman);
2826                 if (err < 0) {
2827                         dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2828                                 __func__, fman->dts_params.err_irq, err);
2829                         goto fman_free;
2830                 }
2831         }
2832
2833         fman->dts_params.res =
2834                 devm_request_mem_region(&of_dev->dev, phys_base_addr,
2835                                         mem_size, "fman");
2836         if (!fman->dts_params.res) {
2837                 dev_err(&of_dev->dev, "%s: request_mem_region() failed\n",
2838                         __func__);
2839                 goto fman_free;
2840         }
2841
2842         fman->dts_params.base_addr =
2843                 devm_ioremap(&of_dev->dev, phys_base_addr, mem_size);
2844         if (!fman->dts_params.base_addr) {
2845                 dev_err(&of_dev->dev, "%s: devm_ioremap() failed\n", __func__);
2846                 goto fman_free;
2847         }
2848
2849         fman->dev = &of_dev->dev;
2850
2851         err = of_platform_populate(fm_node, NULL, NULL, &of_dev->dev);
2852         if (err) {
2853                 dev_err(&of_dev->dev, "%s: of_platform_populate() failed\n",
2854                         __func__);
2855                 goto fman_free;
2856         }
2857
2858 #ifdef CONFIG_DPAA_ERRATUM_A050385
2859         fman_has_err_a050385 =
2860                 of_property_read_bool(fm_node, "fsl,erratum-a050385");
2861 #endif
2862
2863         return fman;
2864
2865 fman_node_put:
2866         of_node_put(fm_node);
2867 fman_free:
2868         kfree(fman);
2869         return NULL;
2870 }
2871
2872 static int fman_probe(struct platform_device *of_dev)
2873 {
2874         struct fman *fman;
2875         struct device *dev;
2876         int err;
2877
2878         dev = &of_dev->dev;
2879
2880         fman = read_dts_node(of_dev);
2881         if (!fman)
2882                 return -EIO;
2883
2884         err = fman_config(fman);
2885         if (err) {
2886                 dev_err(dev, "%s: FMan config failed\n", __func__);
2887                 return -EINVAL;
2888         }
2889
2890         if (fman_init(fman) != 0) {
2891                 dev_err(dev, "%s: FMan init failed\n", __func__);
2892                 return -EINVAL;
2893         }
2894
2895         if (fman->dts_params.err_irq == 0) {
2896                 fman_set_exception(fman, FMAN_EX_DMA_BUS_ERROR, false);
2897                 fman_set_exception(fman, FMAN_EX_DMA_READ_ECC, false);
2898                 fman_set_exception(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC, false);
2899                 fman_set_exception(fman, FMAN_EX_DMA_FM_WRITE_ECC, false);
2900                 fman_set_exception(fman, FMAN_EX_DMA_SINGLE_PORT_ECC, false);
2901                 fman_set_exception(fman, FMAN_EX_FPM_STALL_ON_TASKS, false);
2902                 fman_set_exception(fman, FMAN_EX_FPM_SINGLE_ECC, false);
2903                 fman_set_exception(fman, FMAN_EX_FPM_DOUBLE_ECC, false);
2904                 fman_set_exception(fman, FMAN_EX_QMI_SINGLE_ECC, false);
2905                 fman_set_exception(fman, FMAN_EX_QMI_DOUBLE_ECC, false);
2906                 fman_set_exception(fman,
2907                                    FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID, false);
2908                 fman_set_exception(fman, FMAN_EX_BMI_LIST_RAM_ECC, false);
2909                 fman_set_exception(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC,
2910                                    false);
2911                 fman_set_exception(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC, false);
2912                 fman_set_exception(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC, false);
2913         }
2914
2915         dev_set_drvdata(dev, fman);
2916
2917         dev_dbg(dev, "FMan%d probed\n", fman->dts_params.id);
2918
2919         return 0;
2920 }
2921
2922 static const struct of_device_id fman_match[] = {
2923         {
2924                 .compatible = "fsl,fman"},
2925         {}
2926 };
2927
2928 MODULE_DEVICE_TABLE(of, fman_match);
2929
2930 static struct platform_driver fman_driver = {
2931         .driver = {
2932                 .name = "fsl-fman",
2933                 .of_match_table = fman_match,
2934         },
2935         .probe = fman_probe,
2936 };
2937
2938 static int __init fman_load(void)
2939 {
2940         int err;
2941
2942         pr_debug("FSL DPAA FMan driver\n");
2943
2944         err = platform_driver_register(&fman_driver);
2945         if (err < 0)
2946                 pr_err("Error, platform_driver_register() = %d\n", err);
2947
2948         return err;
2949 }
2950 module_init(fman_load);
2951
2952 static void __exit fman_unload(void)
2953 {
2954         platform_driver_unregister(&fman_driver);
2955 }
2956 module_exit(fman_unload);
2957
2958 MODULE_LICENSE("Dual BSD/GPL");
2959 MODULE_DESCRIPTION("Freescale DPAA Frame Manager driver");