drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         int ret;
 489
 490         ret = eth_mac_addr(dev, p);
 491         if (ret)
 492                 return ret;
 493
 494         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 495
 496         return 0;
 497 }
 498
 499 static const struct net_device_ops gfar_netdev_ops = {
 500         .ndo_open = gfar_enet_open,
 501         .ndo_start_xmit = gfar_start_xmit,
 502         .ndo_stop = gfar_close,
 503         .ndo_change_mtu = gfar_change_mtu,
 504         .ndo_set_features = gfar_set_features,
 505         .ndo_set_rx_mode = gfar_set_multi,
 506         .ndo_tx_timeout = gfar_timeout,
 507         .ndo_do_ioctl = gfar_ioctl,
 508         .ndo_get_stats = gfar_get_stats,
 509         .ndo_set_mac_address = gfar_set_mac_addr,
 510         .ndo_validate_addr = eth_validate_addr,
 511 #ifdef CONFIG_NET_POLL_CONTROLLER
 512         .ndo_poll_controller = gfar_netpoll,
 513 #endif
 514 };
 515
 516 static void gfar_ints_disable(struct gfar_private *priv)
 517 {
 518         int i;
 519         for (i = 0; i < priv->num_grps; i++) {
 520                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 521                 /* Clear IEVENT */
 522                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 523
 524                 /* Initialize IMASK */
 525                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 526         }
 527 }
 528
 529 static void gfar_ints_enable(struct gfar_private *priv)
 530 {
 531         int i;
 532         for (i = 0; i < priv->num_grps; i++) {
 533                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 534                 /* Unmask the interrupts we look for */
 535                 gfar_write(&regs->imask, IMASK_DEFAULT);
 536         }
 537 }
 538
 539 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 540 {
 541         int i;
 542
 543         for (i = 0; i < priv->num_tx_queues; i++) {
 544                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 545                                             GFP_KERNEL);
 546                 if (!priv->tx_queue[i])
 547                         return -ENOMEM;
 548
 549                 priv->tx_queue[i]->tx_skbuff = NULL;
 550                 priv->tx_queue[i]->qindex = i;
 551                 priv->tx_queue[i]->dev = priv->ndev;
 552                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 553         }
 554         return 0;
 555 }
 556
 557 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 558 {
 559         int i;
 560
 561         for (i = 0; i < priv->num_rx_queues; i++) {
 562                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 563                                             GFP_KERNEL);
 564                 if (!priv->rx_queue[i])
 565                         return -ENOMEM;
 566
 567                 priv->rx_queue[i]->qindex = i;
 568                 priv->rx_queue[i]->ndev = priv->ndev;
 569         }
 570         return 0;
 571 }
 572
 573 static void gfar_free_tx_queues(struct gfar_private *priv)
 574 {
 575         int i;
 576
 577         for (i = 0; i < priv->num_tx_queues; i++)
 578                 kfree(priv->tx_queue[i]);
 579 }
 580
 581 static void gfar_free_rx_queues(struct gfar_private *priv)
 582 {
 583         int i;
 584
 585         for (i = 0; i < priv->num_rx_queues; i++)
 586                 kfree(priv->rx_queue[i]);
 587 }
 588
 589 static void unmap_group_regs(struct gfar_private *priv)
 590 {
 591         int i;
 592
 593         for (i = 0; i < MAXGROUPS; i++)
 594                 if (priv->gfargrp[i].regs)
 595                         iounmap(priv->gfargrp[i].regs);
 596 }
 597
 598 static void free_gfar_dev(struct gfar_private *priv)
 599 {
 600         int i, j;
 601
 602         for (i = 0; i < priv->num_grps; i++)
 603                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 604                         kfree(priv->gfargrp[i].irqinfo[j]);
 605                         priv->gfargrp[i].irqinfo[j] = NULL;
 606                 }
 607
 608         free_netdev(priv->ndev);
 609 }
 610
 611 static void disable_napi(struct gfar_private *priv)
 612 {
 613         int i;
 614
 615         for (i = 0; i < priv->num_grps; i++) {
 616                 napi_disable(&priv->gfargrp[i].napi_rx);
 617                 napi_disable(&priv->gfargrp[i].napi_tx);
 618         }
 619 }
 620
 621 static void enable_napi(struct gfar_private *priv)
 622 {
 623         int i;
 624
 625         for (i = 0; i < priv->num_grps; i++) {
 626                 napi_enable(&priv->gfargrp[i].napi_rx);
 627                 napi_enable(&priv->gfargrp[i].napi_tx);
 628         }
 629 }
 630
 631 static int gfar_parse_group(struct device_node *np,
 632                             struct gfar_private *priv, const char *model)
 633 {
 634         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 635         int i;
 636
 637         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 638                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 639                                           GFP_KERNEL);
 640                 if (!grp->irqinfo[i])
 641                         return -ENOMEM;
 642         }
 643
 644         grp->regs = of_iomap(np, 0);
 645         if (!grp->regs)
 646                 return -ENOMEM;
 647
 648         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 649
 650         /* If we aren't the FEC we have multiple interrupts */
 651         if (model && strcasecmp(model, "FEC")) {
 652                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 653                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 654                 if (!gfar_irq(grp, TX)->irq ||
 655                     !gfar_irq(grp, RX)->irq ||
 656                     !gfar_irq(grp, ER)->irq)
 657                         return -EINVAL;
 658         }
 659
 660         grp->priv = priv;
 661         spin_lock_init(&grp->grplock);
 662         if (priv->mode == MQ_MG_MODE) {
 663                 u32 rxq_mask, txq_mask;
 664                 int ret;
 665
 666                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 667                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 668
 669                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 670                 if (!ret) {
 671                         grp->rx_bit_map = rxq_mask ?
 672                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 673                 }
 674
 675                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 676                 if (!ret) {
 677                         grp->tx_bit_map = txq_mask ?
 678                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 679                 }
 680
 681                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 682                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 683                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 684                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 685                 }
 686         } else {
 687                 grp->rx_bit_map = 0xFF;
 688                 grp->tx_bit_map = 0xFF;
 689         }
 690
 691         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 692          * right to left, so we need to revert the 8 bits to get the q index
 693          */
 694         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 695         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 696
 697         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 698          * also assign queues to groups
 699          */
 700         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 701                 if (!grp->rx_queue)
 702                         grp->rx_queue = priv->rx_queue[i];
 703                 grp->num_rx_queues++;
 704                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 705                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 706                 priv->rx_queue[i]->grp = grp;
 707         }
 708
 709         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 710                 if (!grp->tx_queue)
 711                         grp->tx_queue = priv->tx_queue[i];
 712                 grp->num_tx_queues++;
 713                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 714                 priv->tqueue |= (TQUEUE_EN0 >> i);
 715                 priv->tx_queue[i]->grp = grp;
 716         }
 717
 718         priv->num_grps++;
 719
 720         return 0;
 721 }
 722
 723 static int gfar_of_group_count(struct device_node *np)
 724 {
 725         struct device_node *child;
 726         int num = 0;
 727
 728         for_each_available_child_of_node(np, child)
 729                 if (!of_node_cmp(child->name, "queue-group"))
 730                         num++;
 731
 732         return num;
 733 }
 734
 735 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 736 {
 737         const char *model;
 738         const char *ctype;
 739         const void *mac_addr;
 740         int err = 0, i;
 741         struct net_device *dev = NULL;
 742         struct gfar_private *priv = NULL;
 743         struct device_node *np = ofdev->dev.of_node;
 744         struct device_node *child = NULL;
 745         u32 stash_len = 0;
 746         u32 stash_idx = 0;
 747         unsigned int num_tx_qs, num_rx_qs;
 748         unsigned short mode, poll_mode;
 749
 750         if (!np)
 751                 return -ENODEV;
 752
 753         if (of_device_is_compatible(np, "fsl,etsec2")) {
 754                 mode = MQ_MG_MODE;
 755                 poll_mode = GFAR_SQ_POLLING;
 756         } else {
 757                 mode = SQ_SG_MODE;
 758                 poll_mode = GFAR_SQ_POLLING;
 759         }
 760
 761         if (mode == SQ_SG_MODE) {
 762                 num_tx_qs = 1;
 763                 num_rx_qs = 1;
 764         } else { /* MQ_MG_MODE */
 765                 /* get the actual number of supported groups */
 766                 unsigned int num_grps = gfar_of_group_count(np);
 767
 768                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 769                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 770                                 num_grps);
 771                         pr_err("Cannot do alloc_etherdev, aborting\n");
 772                         return -EINVAL;
 773                 }
 774
 775                 if (poll_mode == GFAR_SQ_POLLING) {
 776                         num_tx_qs = num_grps; /* one txq per int group */
 777                         num_rx_qs = num_grps; /* one rxq per int group */
 778                 } else { /* GFAR_MQ_POLLING */
 779                         u32 tx_queues, rx_queues;
 780                         int ret;
 781
 782                         /* parse the num of HW tx and rx queues */
 783                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 784                                                    &tx_queues);
 785                         num_tx_qs = ret ? 1 : tx_queues;
 786
 787                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 788                                                    &rx_queues);
 789                         num_rx_qs = ret ? 1 : rx_queues;
 790                 }
 791         }
 792
 793         if (num_tx_qs > MAX_TX_QS) {
 794                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 795                        num_tx_qs, MAX_TX_QS);
 796                 pr_err("Cannot do alloc_etherdev, aborting\n");
 797                 return -EINVAL;
 798         }
 799
 800         if (num_rx_qs > MAX_RX_QS) {
 801                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 802                        num_rx_qs, MAX_RX_QS);
 803                 pr_err("Cannot do alloc_etherdev, aborting\n");
 804                 return -EINVAL;
 805         }
 806
 807         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 808         dev = *pdev;
 809         if (NULL == dev)
 810                 return -ENOMEM;
 811
 812         priv = netdev_priv(dev);
 813         priv->ndev = dev;
 814
 815         priv->mode = mode;
 816         priv->poll_mode = poll_mode;
 817
 818         priv->num_tx_queues = num_tx_qs;
 819         netif_set_real_num_rx_queues(dev, num_rx_qs);
 820         priv->num_rx_queues = num_rx_qs;
 821
 822         err = gfar_alloc_tx_queues(priv);
 823         if (err)
 824                 goto tx_alloc_failed;
 825
 826         err = gfar_alloc_rx_queues(priv);
 827         if (err)
 828                 goto rx_alloc_failed;
 829
 830         err = of_property_read_string(np, "model", &model);
 831         if (err) {
 832                 pr_err("Device model property missing, aborting\n");
 833                 goto rx_alloc_failed;
 834         }
 835
 836         /* Init Rx queue filer rule set linked list */
 837         INIT_LIST_HEAD(&priv->rx_list.list);
 838         priv->rx_list.count = 0;
 839         mutex_init(&priv->rx_queue_access);
 840
 841         for (i = 0; i < MAXGROUPS; i++)
 842                 priv->gfargrp[i].regs = NULL;
 843
 844         /* Parse and initialize group specific information */
 845         if (priv->mode == MQ_MG_MODE) {
 846                 for_each_available_child_of_node(np, child) {
 847                         if (of_node_cmp(child->name, "queue-group"))
 848                                 continue;
 849
 850                         err = gfar_parse_group(child, priv, model);
 851                         if (err) {
 852                                 of_node_put(child);
 853                                 goto err_grp_init;
 854                         }
 855                 }
 856         } else { /* SQ_SG_MODE */
 857                 err = gfar_parse_group(np, priv, model);
 858                 if (err)
 859                         goto err_grp_init;
 860         }
 861
 862         if (of_property_read_bool(np, "bd-stash")) {
 863                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 864                 priv->bd_stash_en = 1;
 865         }
 866
 867         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 868
 869         if (err == 0)
 870                 priv->rx_stash_size = stash_len;
 871
 872         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 873
 874         if (err == 0)
 875                 priv->rx_stash_index = stash_idx;
 876
 877         if (stash_len || stash_idx)
 878                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 879
 880         mac_addr = of_get_mac_address(np);
 881
 882         if (mac_addr)
 883                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 884
 885         if (model && !strcasecmp(model, "TSEC"))
 886                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 887                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 888                                      FSL_GIANFAR_DEV_HAS_RMON |
 889                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 890
 891         if (model && !strcasecmp(model, "eTSEC"))
 892                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 893                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 894                                      FSL_GIANFAR_DEV_HAS_RMON |
 895                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 896                                      FSL_GIANFAR_DEV_HAS_CSUM |
 897                                      FSL_GIANFAR_DEV_HAS_VLAN |
 898                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 899                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 900                                      FSL_GIANFAR_DEV_HAS_TIMER |
 901                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 902
 903         err = of_property_read_string(np, "phy-connection-type", &ctype);
 904
 905         /* We only care about rgmii-id.  The rest are autodetected */
 906         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 907                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 908         else
 909                 priv->interface = PHY_INTERFACE_MODE_MII;
 910
 911         if (of_find_property(np, "fsl,magic-packet", NULL))
 912                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 913
 914         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 915                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 916
 917         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 918
 919         /* In the case of a fixed PHY, the DT node associated
 920          * to the PHY is the Ethernet MAC DT node.
 921          */
 922         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 923                 err = of_phy_register_fixed_link(np);
 924                 if (err)
 925                         goto err_grp_init;
 926
 927                 priv->phy_node = of_node_get(np);
 928         }
 929
 930         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 931         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 932
 933         return 0;
 934
 935 err_grp_init:
 936         unmap_group_regs(priv);
 937 rx_alloc_failed:
 938         gfar_free_rx_queues(priv);
 939 tx_alloc_failed:
 940         gfar_free_tx_queues(priv);
 941         free_gfar_dev(priv);
 942         return err;
 943 }
 944
 945 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 946 {
 947         struct hwtstamp_config config;
 948         struct gfar_private *priv = netdev_priv(netdev);
 949
 950         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 951                 return -EFAULT;
 952
 953         /* reserved for future extensions */
 954         if (config.flags)
 955                 return -EINVAL;
 956
 957         switch (config.tx_type) {
 958         case HWTSTAMP_TX_OFF:
 959                 priv->hwts_tx_en = 0;
 960                 break;
 961         case HWTSTAMP_TX_ON:
 962                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 963                         return -ERANGE;
 964                 priv->hwts_tx_en = 1;
 965                 break;
 966         default:
 967                 return -ERANGE;
 968         }
 969
 970         switch (config.rx_filter) {
 971         case HWTSTAMP_FILTER_NONE:
 972                 if (priv->hwts_rx_en) {
 973                         priv->hwts_rx_en = 0;
 974                         reset_gfar(netdev);
 975                 }
 976                 break;
 977         default:
 978                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 979                         return -ERANGE;
 980                 if (!priv->hwts_rx_en) {
 981                         priv->hwts_rx_en = 1;
 982                         reset_gfar(netdev);
 983                 }
 984                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 985                 break;
 986         }
 987
 988         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 989                 -EFAULT : 0;
 990 }
 991
 992 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 993 {
 994         struct hwtstamp_config config;
 995         struct gfar_private *priv = netdev_priv(netdev);
 996
 997         config.flags = 0;
 998         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 999         config.rx_filter = (priv->hwts_rx_en ?
1000                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1001
1002         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1003                 -EFAULT : 0;
1004 }
1005
1006 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1007 {
1008         struct phy_device *phydev = dev->phydev;
1009
1010         if (!netif_running(dev))
1011                 return -EINVAL;
1012
1013         if (cmd == SIOCSHWTSTAMP)
1014                 return gfar_hwtstamp_set(dev, rq);
1015         if (cmd == SIOCGHWTSTAMP)
1016                 return gfar_hwtstamp_get(dev, rq);
1017
1018         if (!phydev)
1019                 return -ENODEV;
1020
1021         return phy_mii_ioctl(phydev, rq, cmd);
1022 }
1023
1024 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1025                                    u32 class)
1026 {
1027         u32 rqfpr = FPR_FILER_MASK;
1028         u32 rqfcr = 0x0;
1029
1030         rqfar--;
1031         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1032         priv->ftp_rqfpr[rqfar] = rqfpr;
1033         priv->ftp_rqfcr[rqfar] = rqfcr;
1034         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1035
1036         rqfar--;
1037         rqfcr = RQFCR_CMP_NOMATCH;
1038         priv->ftp_rqfpr[rqfar] = rqfpr;
1039         priv->ftp_rqfcr[rqfar] = rqfcr;
1040         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1041
1042         rqfar--;
1043         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1044         rqfpr = class;
1045         priv->ftp_rqfcr[rqfar] = rqfcr;
1046         priv->ftp_rqfpr[rqfar] = rqfpr;
1047         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1048
1049         rqfar--;
1050         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1051         rqfpr = class;
1052         priv->ftp_rqfcr[rqfar] = rqfcr;
1053         priv->ftp_rqfpr[rqfar] = rqfpr;
1054         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1055
1056         return rqfar;
1057 }
1058
1059 static void gfar_init_filer_table(struct gfar_private *priv)
1060 {
1061         int i = 0x0;
1062         u32 rqfar = MAX_FILER_IDX;
1063         u32 rqfcr = 0x0;
1064         u32 rqfpr = FPR_FILER_MASK;
1065
1066         /* Default rule */
1067         rqfcr = RQFCR_CMP_MATCH;
1068         priv->ftp_rqfcr[rqfar] = rqfcr;
1069         priv->ftp_rqfpr[rqfar] = rqfpr;
1070         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1071
1072         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1073         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1074         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1075         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1076         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1077         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1078
1079         /* cur_filer_idx indicated the first non-masked rule */
1080         priv->cur_filer_idx = rqfar;
1081
1082         /* Rest are masked rules */
1083         rqfcr = RQFCR_CMP_NOMATCH;
1084         for (i = 0; i < rqfar; i++) {
1085                 priv->ftp_rqfcr[i] = rqfcr;
1086                 priv->ftp_rqfpr[i] = rqfpr;
1087                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1088         }
1089 }
1090
1091 #ifdef CONFIG_PPC
1092 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1093 {
1094         unsigned int pvr = mfspr(SPRN_PVR);
1095         unsigned int svr = mfspr(SPRN_SVR);
1096         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1097         unsigned int rev = svr & 0xffff;
1098
1099         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1100         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1101             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1102                 priv->errata |= GFAR_ERRATA_74;
1103
1104         /* MPC8313 and MPC837x all rev */
1105         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1106             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1107                 priv->errata |= GFAR_ERRATA_76;
1108
1109         /* MPC8313 Rev < 2.0 */
1110         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1111                 priv->errata |= GFAR_ERRATA_12;
1112 }
1113
1114 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1115 {
1116         unsigned int svr = mfspr(SPRN_SVR);
1117
1118         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1119                 priv->errata |= GFAR_ERRATA_12;
1120         /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
1121         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1122             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1123             ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
1124                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1125 }
1126 #endif
1127
1128 static void gfar_detect_errata(struct gfar_private *priv)
1129 {
1130         struct device *dev = &priv->ofdev->dev;
1131
1132         /* no plans to fix */
1133         priv->errata |= GFAR_ERRATA_A002;
1134
1135 #ifdef CONFIG_PPC
1136         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1137                 __gfar_detect_errata_85xx(priv);
1138         else /* non-mpc85xx parts, i.e. e300 core based */
1139                 __gfar_detect_errata_83xx(priv);
1140 #endif
1141
1142         if (priv->errata)
1143                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1144                          priv->errata);
1145 }
1146
1147 void gfar_mac_reset(struct gfar_private *priv)
1148 {
1149         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1150         u32 tempval;
1151
1152         /* Reset MAC layer */
1153         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1154
1155         /* We need to delay at least 3 TX clocks */
1156         udelay(3);
1157
1158         /* the soft reset bit is not self-resetting, so we need to
1159          * clear it before resuming normal operation
1160          */
1161         gfar_write(&regs->maccfg1, 0);
1162
1163         udelay(3);
1164
1165         gfar_rx_offload_en(priv);
1166
1167         /* Initialize the max receive frame/buffer lengths */
1168         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1169         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1170
1171         /* Initialize the Minimum Frame Length Register */
1172         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1173
1174         /* Initialize MACCFG2. */
1175         tempval = MACCFG2_INIT_SETTINGS;
1176
1177         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1178          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1179          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1180          */
1181         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1182                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1183
1184         gfar_write(&regs->maccfg2, tempval);
1185
1186         /* Clear mac addr hash registers */
1187         gfar_write(&regs->igaddr0, 0);
1188         gfar_write(&regs->igaddr1, 0);
1189         gfar_write(&regs->igaddr2, 0);
1190         gfar_write(&regs->igaddr3, 0);
1191         gfar_write(&regs->igaddr4, 0);
1192         gfar_write(&regs->igaddr5, 0);
1193         gfar_write(&regs->igaddr6, 0);
1194         gfar_write(&regs->igaddr7, 0);
1195
1196         gfar_write(&regs->gaddr0, 0);
1197         gfar_write(&regs->gaddr1, 0);
1198         gfar_write(&regs->gaddr2, 0);
1199         gfar_write(&regs->gaddr3, 0);
1200         gfar_write(&regs->gaddr4, 0);
1201         gfar_write(&regs->gaddr5, 0);
1202         gfar_write(&regs->gaddr6, 0);
1203         gfar_write(&regs->gaddr7, 0);
1204
1205         if (priv->extended_hash)
1206                 gfar_clear_exact_match(priv->ndev);
1207
1208         gfar_mac_rx_config(priv);
1209
1210         gfar_mac_tx_config(priv);
1211
1212         gfar_set_mac_address(priv->ndev);
1213
1214         gfar_set_multi(priv->ndev);
1215
1216         /* clear ievent and imask before configuring coalescing */
1217         gfar_ints_disable(priv);
1218
1219         /* Configure the coalescing support */
1220         gfar_configure_coalescing_all(priv);
1221 }
1222
1223 static void gfar_hw_init(struct gfar_private *priv)
1224 {
1225         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1226         u32 attrs;
1227
1228         /* Stop the DMA engine now, in case it was running before
1229          * (The firmware could have used it, and left it running).
1230          */
1231         gfar_halt(priv);
1232
1233         gfar_mac_reset(priv);
1234
1235         /* Zero out the rmon mib registers if it has them */
1236         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1237                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1238
1239                 /* Mask off the CAM interrupts */
1240                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1241                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1242         }
1243
1244         /* Initialize ECNTRL */
1245         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1246
1247         /* Set the extraction length and index */
1248         attrs = ATTRELI_EL(priv->rx_stash_size) |
1249                 ATTRELI_EI(priv->rx_stash_index);
1250
1251         gfar_write(&regs->attreli, attrs);
1252
1253         /* Start with defaults, and add stashing
1254          * depending on driver parameters
1255          */
1256         attrs = ATTR_INIT_SETTINGS;
1257
1258         if (priv->bd_stash_en)
1259                 attrs |= ATTR_BDSTASH;
1260
1261         if (priv->rx_stash_size != 0)
1262                 attrs |= ATTR_BUFSTASH;
1263
1264         gfar_write(&regs->attr, attrs);
1265
1266         /* FIFO configs */
1267         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1268         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1269         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1270
1271         /* Program the interrupt steering regs, only for MG devices */
1272         if (priv->num_grps > 1)
1273                 gfar_write_isrg(priv);
1274 }
1275
1276 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1277 {
1278         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1279
1280         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1281                 priv->extended_hash = 1;
1282                 priv->hash_width = 9;
1283
1284                 priv->hash_regs[0] = &regs->igaddr0;
1285                 priv->hash_regs[1] = &regs->igaddr1;
1286                 priv->hash_regs[2] = &regs->igaddr2;
1287                 priv->hash_regs[3] = &regs->igaddr3;
1288                 priv->hash_regs[4] = &regs->igaddr4;
1289                 priv->hash_regs[5] = &regs->igaddr5;
1290                 priv->hash_regs[6] = &regs->igaddr6;
1291                 priv->hash_regs[7] = &regs->igaddr7;
1292                 priv->hash_regs[8] = &regs->gaddr0;
1293                 priv->hash_regs[9] = &regs->gaddr1;
1294                 priv->hash_regs[10] = &regs->gaddr2;
1295                 priv->hash_regs[11] = &regs->gaddr3;
1296                 priv->hash_regs[12] = &regs->gaddr4;
1297                 priv->hash_regs[13] = &regs->gaddr5;
1298                 priv->hash_regs[14] = &regs->gaddr6;
1299                 priv->hash_regs[15] = &regs->gaddr7;
1300
1301         } else {
1302                 priv->extended_hash = 0;
1303                 priv->hash_width = 8;
1304
1305                 priv->hash_regs[0] = &regs->gaddr0;
1306                 priv->hash_regs[1] = &regs->gaddr1;
1307                 priv->hash_regs[2] = &regs->gaddr2;
1308                 priv->hash_regs[3] = &regs->gaddr3;
1309                 priv->hash_regs[4] = &regs->gaddr4;
1310                 priv->hash_regs[5] = &regs->gaddr5;
1311                 priv->hash_regs[6] = &regs->gaddr6;
1312                 priv->hash_regs[7] = &regs->gaddr7;
1313         }
1314 }
1315
1316 /* Set up the ethernet device structure, private data,
1317  * and anything else we need before we start
1318  */
1319 static int gfar_probe(struct platform_device *ofdev)
1320 {
1321         struct device_node *np = ofdev->dev.of_node;
1322         struct net_device *dev = NULL;
1323         struct gfar_private *priv = NULL;
1324         int err = 0, i;
1325
1326         err = gfar_of_init(ofdev, &dev);
1327
1328         if (err)
1329                 return err;
1330
1331         priv = netdev_priv(dev);
1332         priv->ndev = dev;
1333         priv->ofdev = ofdev;
1334         priv->dev = &ofdev->dev;
1335         SET_NETDEV_DEV(dev, &ofdev->dev);
1336
1337         INIT_WORK(&priv->reset_task, gfar_reset_task);
1338
1339         platform_set_drvdata(ofdev, priv);
1340
1341         gfar_detect_errata(priv);
1342
1343         /* Set the dev->base_addr to the gfar reg region */
1344         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1345
1346         /* Fill in the dev structure */
1347         dev->watchdog_timeo = TX_TIMEOUT;
1348         dev->mtu = 1500;
1349         dev->netdev_ops = &gfar_netdev_ops;
1350         dev->ethtool_ops = &gfar_ethtool_ops;
1351
1352         /* Register for napi ...We are registering NAPI for each grp */
1353         for (i = 0; i < priv->num_grps; i++) {
1354                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1355                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1356                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1357                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1358                                        gfar_poll_tx_sq, 2);
1359                 } else {
1360                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1361                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1362                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1363                                        gfar_poll_tx, 2);
1364                 }
1365         }
1366
1367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1368                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1369                                    NETIF_F_RXCSUM;
1370                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1371                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1372         }
1373
1374         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1375                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1376                                     NETIF_F_HW_VLAN_CTAG_RX;
1377                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1378         }
1379
1380         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1381
1382         gfar_init_addr_hash_table(priv);
1383
1384         /* Insert receive time stamps into padding alignment bytes, and
1385          * plus 2 bytes padding to ensure the cpu alignment.
1386          */
1387         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1388                 priv->padding = 8 + DEFAULT_PADDING;
1389
1390         if (dev->features & NETIF_F_IP_CSUM ||
1391             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1392                 dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1393
1394         /* Initializing some of the rx/tx queue level parameters */
1395         for (i = 0; i < priv->num_tx_queues; i++) {
1396                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1397                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1398                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1399                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1400         }
1401
1402         for (i = 0; i < priv->num_rx_queues; i++) {
1403                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1404                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1405                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1406         }
1407
1408         /* Always enable rx filer if available */
1409         priv->rx_filer_enable =
1410             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1411         /* Enable most messages by default */
1412         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1413         /* use pritority h/w tx queue scheduling for single queue devices */
1414         if (priv->num_tx_queues == 1)
1415                 priv->prio_sched_en = 1;
1416
1417         set_bit(GFAR_DOWN, &priv->state);
1418
1419         gfar_hw_init(priv);
1420
1421         /* Carrier starts down, phylib will bring it up */
1422         netif_carrier_off(dev);
1423
1424         err = register_netdev(dev);
1425
1426         if (err) {
1427                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1428                 goto register_fail;
1429         }
1430
1431         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1432                 priv->wol_supported |= GFAR_WOL_MAGIC;
1433
1434         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1435             priv->rx_filer_enable)
1436                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1437
1438         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1439
1440         /* fill out IRQ number and name fields */
1441         for (i = 0; i < priv->num_grps; i++) {
1442                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1443                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1444                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1445                                 dev->name, "_g", '0' + i, "_tx");
1446                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1447                                 dev->name, "_g", '0' + i, "_rx");
1448                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1449                                 dev->name, "_g", '0' + i, "_er");
1450                 } else
1451                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1452         }
1453
1454         /* Initialize the filer table */
1455         gfar_init_filer_table(priv);
1456
1457         /* Print out the device info */
1458         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1459
1460         /* Even more device info helps when determining which kernel
1461          * provided which set of benchmarks.
1462          */
1463         netdev_info(dev, "Running with NAPI enabled\n");
1464         for (i = 0; i < priv->num_rx_queues; i++)
1465                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1466                             i, priv->rx_queue[i]->rx_ring_size);
1467         for (i = 0; i < priv->num_tx_queues; i++)
1468                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1469                             i, priv->tx_queue[i]->tx_ring_size);
1470
1471         return 0;
1472
1473 register_fail:
1474         if (of_phy_is_fixed_link(np))
1475                 of_phy_deregister_fixed_link(np);
1476         unmap_group_regs(priv);
1477         gfar_free_rx_queues(priv);
1478         gfar_free_tx_queues(priv);
1479         of_node_put(priv->phy_node);
1480         of_node_put(priv->tbi_node);
1481         free_gfar_dev(priv);
1482         return err;
1483 }
1484
1485 static int gfar_remove(struct platform_device *ofdev)
1486 {
1487         struct gfar_private *priv = platform_get_drvdata(ofdev);
1488         struct device_node *np = ofdev->dev.of_node;
1489
1490         of_node_put(priv->phy_node);
1491         of_node_put(priv->tbi_node);
1492
1493         unregister_netdev(priv->ndev);
1494
1495         if (of_phy_is_fixed_link(np))
1496                 of_phy_deregister_fixed_link(np);
1497
1498         unmap_group_regs(priv);
1499         gfar_free_rx_queues(priv);
1500         gfar_free_tx_queues(priv);
1501         free_gfar_dev(priv);
1502
1503         return 0;
1504 }
1505
1506 #ifdef CONFIG_PM
1507
1508 static void __gfar_filer_disable(struct gfar_private *priv)
1509 {
1510         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1511         u32 temp;
1512
1513         temp = gfar_read(&regs->rctrl);
1514         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1515         gfar_write(&regs->rctrl, temp);
1516 }
1517
1518 static void __gfar_filer_enable(struct gfar_private *priv)
1519 {
1520         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1521         u32 temp;
1522
1523         temp = gfar_read(&regs->rctrl);
1524         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1525         gfar_write(&regs->rctrl, temp);
1526 }
1527
1528 /* Filer rules implementing wol capabilities */
1529 static void gfar_filer_config_wol(struct gfar_private *priv)
1530 {
1531         unsigned int i;
1532         u32 rqfcr;
1533
1534         __gfar_filer_disable(priv);
1535
1536         /* clear the filer table, reject any packet by default */
1537         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1538         for (i = 0; i <= MAX_FILER_IDX; i++)
1539                 gfar_write_filer(priv, i, rqfcr, 0);
1540
1541         i = 0;
1542         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1543                 /* unicast packet, accept it */
1544                 struct net_device *ndev = priv->ndev;
1545                 /* get the default rx queue index */
1546                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1547                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1548                                     (ndev->dev_addr[1] << 8) |
1549                                      ndev->dev_addr[2];
1550
1551                 rqfcr = (qindex << 10) | RQFCR_AND |
1552                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1553
1554                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1555
1556                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1557                                 (ndev->dev_addr[4] << 8) |
1558                                  ndev->dev_addr[5];
1559                 rqfcr = (qindex << 10) | RQFCR_GPI |
1560                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1561                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1562         }
1563
1564         __gfar_filer_enable(priv);
1565 }
1566
1567 static void gfar_filer_restore_table(struct gfar_private *priv)
1568 {
1569         u32 rqfcr, rqfpr;
1570         unsigned int i;
1571
1572         __gfar_filer_disable(priv);
1573
1574         for (i = 0; i <= MAX_FILER_IDX; i++) {
1575                 rqfcr = priv->ftp_rqfcr[i];
1576                 rqfpr = priv->ftp_rqfpr[i];
1577                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1578         }
1579
1580         __gfar_filer_enable(priv);
1581 }
1582
1583 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1584 static void gfar_start_wol_filer(struct gfar_private *priv)
1585 {
1586         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1587         u32 tempval;
1588         int i = 0;
1589
1590         /* Enable Rx hw queues */
1591         gfar_write(&regs->rqueue, priv->rqueue);
1592
1593         /* Initialize DMACTRL to have WWR and WOP */
1594         tempval = gfar_read(&regs->dmactrl);
1595         tempval |= DMACTRL_INIT_SETTINGS;
1596         gfar_write(&regs->dmactrl, tempval);
1597
1598         /* Make sure we aren't stopped */
1599         tempval = gfar_read(&regs->dmactrl);
1600         tempval &= ~DMACTRL_GRS;
1601         gfar_write(&regs->dmactrl, tempval);
1602
1603         for (i = 0; i < priv->num_grps; i++) {
1604                 regs = priv->gfargrp[i].regs;
1605                 /* Clear RHLT, so that the DMA starts polling now */
1606                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1607                 /* enable the Filer General Purpose Interrupt */
1608                 gfar_write(&regs->imask, IMASK_FGPI);
1609         }
1610
1611         /* Enable Rx DMA */
1612         tempval = gfar_read(&regs->maccfg1);
1613         tempval |= MACCFG1_RX_EN;
1614         gfar_write(&regs->maccfg1, tempval);
1615 }
1616
1617 static int gfar_suspend(struct device *dev)
1618 {
1619         struct gfar_private *priv = dev_get_drvdata(dev);
1620         struct net_device *ndev = priv->ndev;
1621         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1622         u32 tempval;
1623         u16 wol = priv->wol_opts;
1624
1625         if (!netif_running(ndev))
1626                 return 0;
1627
1628         disable_napi(priv);
1629         netif_tx_lock(ndev);
1630         netif_device_detach(ndev);
1631         netif_tx_unlock(ndev);
1632
1633         gfar_halt(priv);
1634
1635         if (wol & GFAR_WOL_MAGIC) {
1636                 /* Enable interrupt on Magic Packet */
1637                 gfar_write(&regs->imask, IMASK_MAG);
1638
1639                 /* Enable Magic Packet mode */
1640                 tempval = gfar_read(&regs->maccfg2);
1641                 tempval |= MACCFG2_MPEN;
1642                 gfar_write(&regs->maccfg2, tempval);
1643
1644                 /* re-enable the Rx block */
1645                 tempval = gfar_read(&regs->maccfg1);
1646                 tempval |= MACCFG1_RX_EN;
1647                 gfar_write(&regs->maccfg1, tempval);
1648
1649         } else if (wol & GFAR_WOL_FILER_UCAST) {
1650                 gfar_filer_config_wol(priv);
1651                 gfar_start_wol_filer(priv);
1652
1653         } else {
1654                 phy_stop(ndev->phydev);
1655         }
1656
1657         return 0;
1658 }
1659
1660 static int gfar_resume(struct device *dev)
1661 {
1662         struct gfar_private *priv = dev_get_drvdata(dev);
1663         struct net_device *ndev = priv->ndev;
1664         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1665         u32 tempval;
1666         u16 wol = priv->wol_opts;
1667
1668         if (!netif_running(ndev))
1669                 return 0;
1670
1671         if (wol & GFAR_WOL_MAGIC) {
1672                 /* Disable Magic Packet mode */
1673                 tempval = gfar_read(&regs->maccfg2);
1674                 tempval &= ~MACCFG2_MPEN;
1675                 gfar_write(&regs->maccfg2, tempval);
1676
1677         } else if (wol & GFAR_WOL_FILER_UCAST) {
1678                 /* need to stop rx only, tx is already down */
1679                 gfar_halt(priv);
1680                 gfar_filer_restore_table(priv);
1681
1682         } else {
1683                 phy_start(ndev->phydev);
1684         }
1685
1686         gfar_start(priv);
1687
1688         netif_device_attach(ndev);
1689         enable_napi(priv);
1690
1691         return 0;
1692 }
1693
1694 static int gfar_restore(struct device *dev)
1695 {
1696         struct gfar_private *priv = dev_get_drvdata(dev);
1697         struct net_device *ndev = priv->ndev;
1698
1699         if (!netif_running(ndev)) {
1700                 netif_device_attach(ndev);
1701
1702                 return 0;
1703         }
1704
1705         gfar_init_bds(ndev);
1706
1707         gfar_mac_reset(priv);
1708
1709         gfar_init_tx_rx_base(priv);
1710
1711         gfar_start(priv);
1712
1713         priv->oldlink = 0;
1714         priv->oldspeed = 0;
1715         priv->oldduplex = -1;
1716
1717         if (ndev->phydev)
1718                 phy_start(ndev->phydev);
1719
1720         netif_device_attach(ndev);
1721         enable_napi(priv);
1722
1723         return 0;
1724 }
1725
1726 static struct dev_pm_ops gfar_pm_ops = {
1727         .suspend = gfar_suspend,
1728         .resume = gfar_resume,
1729         .freeze = gfar_suspend,
1730         .thaw = gfar_resume,
1731         .restore = gfar_restore,
1732 };
1733
1734 #define GFAR_PM_OPS (&gfar_pm_ops)
1735
1736 #else
1737
1738 #define GFAR_PM_OPS NULL
1739
1740 #endif
1741
1742 /* Reads the controller's registers to determine what interface
1743  * connects it to the PHY.
1744  */
1745 static phy_interface_t gfar_get_interface(struct net_device *dev)
1746 {
1747         struct gfar_private *priv = netdev_priv(dev);
1748         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1749         u32 ecntrl;
1750
1751         ecntrl = gfar_read(&regs->ecntrl);
1752
1753         if (ecntrl & ECNTRL_SGMII_MODE)
1754                 return PHY_INTERFACE_MODE_SGMII;
1755
1756         if (ecntrl & ECNTRL_TBI_MODE) {
1757                 if (ecntrl & ECNTRL_REDUCED_MODE)
1758                         return PHY_INTERFACE_MODE_RTBI;
1759                 else
1760                         return PHY_INTERFACE_MODE_TBI;
1761         }
1762
1763         if (ecntrl & ECNTRL_REDUCED_MODE) {
1764                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1765                         return PHY_INTERFACE_MODE_RMII;
1766                 }
1767                 else {
1768                         phy_interface_t interface = priv->interface;
1769
1770                         /* This isn't autodetected right now, so it must
1771                          * be set by the device tree or platform code.
1772                          */
1773                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1774                                 return PHY_INTERFACE_MODE_RGMII_ID;
1775
1776                         return PHY_INTERFACE_MODE_RGMII;
1777                 }
1778         }
1779
1780         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1781                 return PHY_INTERFACE_MODE_GMII;
1782
1783         return PHY_INTERFACE_MODE_MII;
1784 }
1785
1786
1787 /* Initializes driver's PHY state, and attaches to the PHY.
1788  * Returns 0 on success.
1789  */
1790 static int init_phy(struct net_device *dev)
1791 {
1792         struct gfar_private *priv = netdev_priv(dev);
1793         uint gigabit_support =
1794                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1795                 GFAR_SUPPORTED_GBIT : 0;
1796         phy_interface_t interface;
1797         struct phy_device *phydev;
1798         struct ethtool_eee edata;
1799
1800         priv->oldlink = 0;
1801         priv->oldspeed = 0;
1802         priv->oldduplex = -1;
1803
1804         interface = gfar_get_interface(dev);
1805
1806         phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1807                                 interface);
1808         if (!phydev) {
1809                 dev_err(&dev->dev, "could not attach to PHY\n");
1810                 return -ENODEV;
1811         }
1812
1813         if (interface == PHY_INTERFACE_MODE_SGMII)
1814                 gfar_configure_serdes(dev);
1815
1816         /* Remove any features not supported by the controller */
1817         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1818         phydev->advertising = phydev->supported;
1819
1820         /* Add support for flow control, but don't advertise it by default */
1821         phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1822
1823         /* disable EEE autoneg, EEE not supported by eTSEC */
1824         memset(&edata, 0, sizeof(struct ethtool_eee));
1825         phy_ethtool_set_eee(phydev, &edata);
1826
1827         return 0;
1828 }
1829
1830 /* Initialize TBI PHY interface for communicating with the
1831  * SERDES lynx PHY on the chip.  We communicate with this PHY
1832  * through the MDIO bus on each controller, treating it as a
1833  * "normal" PHY at the address found in the TBIPA register.  We assume
1834  * that the TBIPA register is valid.  Either the MDIO bus code will set
1835  * it to a value that doesn't conflict with other PHYs on the bus, or the
1836  * value doesn't matter, as there are no other PHYs on the bus.
1837  */
1838 static void gfar_configure_serdes(struct net_device *dev)
1839 {
1840         struct gfar_private *priv = netdev_priv(dev);
1841         struct phy_device *tbiphy;
1842
1843         if (!priv->tbi_node) {
1844                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1845                                     "device tree specify a tbi-handle\n");
1846                 return;
1847         }
1848
1849         tbiphy = of_phy_find_device(priv->tbi_node);
1850         if (!tbiphy) {
1851                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1852                 return;
1853         }
1854
1855         /* If the link is already up, we must already be ok, and don't need to
1856          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1857          * everything for us?  Resetting it takes the link down and requires
1858          * several seconds for it to come back.
1859          */
1860         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1861                 put_device(&tbiphy->mdio.dev);
1862                 return;
1863         }
1864
1865         /* Single clk mode, mii mode off(for serdes communication) */
1866         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1867
1868         phy_write(tbiphy, MII_ADVERTISE,
1869                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1870                   ADVERTISE_1000XPSE_ASYM);
1871
1872         phy_write(tbiphy, MII_BMCR,
1873                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1874                   BMCR_SPEED1000);
1875
1876         put_device(&tbiphy->mdio.dev);
1877 }
1878
1879 static int __gfar_is_rx_idle(struct gfar_private *priv)
1880 {
1881         u32 res;
1882
1883         /* Normaly TSEC should not hang on GRS commands, so we should
1884          * actually wait for IEVENT_GRSC flag.
1885          */
1886         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1887                 return 0;
1888
1889         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1890          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1891          * and the Rx can be safely reset.
1892          */
1893         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1894         res &= 0x7f807f80;
1895         if ((res & 0xffff) == (res >> 16))
1896                 return 1;
1897
1898         return 0;
1899 }
1900
1901 /* Halt the receive and transmit queues */
1902 static void gfar_halt_nodisable(struct gfar_private *priv)
1903 {
1904         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1905         u32 tempval;
1906         unsigned int timeout;
1907         int stopped;
1908
1909         gfar_ints_disable(priv);
1910
1911         if (gfar_is_dma_stopped(priv))
1912                 return;
1913
1914         /* Stop the DMA, and wait for it to stop */
1915         tempval = gfar_read(&regs->dmactrl);
1916         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1917         gfar_write(&regs->dmactrl, tempval);
1918
1919 retry:
1920         timeout = 1000;
1921         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1922                 cpu_relax();
1923                 timeout--;
1924         }
1925
1926         if (!timeout)
1927                 stopped = gfar_is_dma_stopped(priv);
1928
1929         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1930             !__gfar_is_rx_idle(priv))
1931                 goto retry;
1932 }
1933
1934 /* Halt the receive and transmit queues */
1935 void gfar_halt(struct gfar_private *priv)
1936 {
1937         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1938         u32 tempval;
1939
1940         /* Dissable the Rx/Tx hw queues */
1941         gfar_write(&regs->rqueue, 0);
1942         gfar_write(&regs->tqueue, 0);
1943
1944         mdelay(10);
1945
1946         gfar_halt_nodisable(priv);
1947
1948         /* Disable Rx/Tx DMA */
1949         tempval = gfar_read(&regs->maccfg1);
1950         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1951         gfar_write(&regs->maccfg1, tempval);
1952 }
1953
1954 void stop_gfar(struct net_device *dev)
1955 {
1956         struct gfar_private *priv = netdev_priv(dev);
1957
1958         netif_tx_stop_all_queues(dev);
1959
1960         smp_mb__before_atomic();
1961         set_bit(GFAR_DOWN, &priv->state);
1962         smp_mb__after_atomic();
1963
1964         disable_napi(priv);
1965
1966         /* disable ints and gracefully shut down Rx/Tx DMA */
1967         gfar_halt(priv);
1968
1969         phy_stop(dev->phydev);
1970
1971         free_skb_resources(priv);
1972 }
1973
1974 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1975 {
1976         struct txbd8 *txbdp;
1977         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1978         int i, j;
1979
1980         txbdp = tx_queue->tx_bd_base;
1981
1982         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1983                 if (!tx_queue->tx_skbuff[i])
1984                         continue;
1985
1986                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1987                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1988                 txbdp->lstatus = 0;
1989                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1990                      j++) {
1991                         txbdp++;
1992                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1993                                        be16_to_cpu(txbdp->length),
1994                                        DMA_TO_DEVICE);
1995                 }
1996                 txbdp++;
1997                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1998                 tx_queue->tx_skbuff[i] = NULL;
1999         }
2000         kfree(tx_queue->tx_skbuff);
2001         tx_queue->tx_skbuff = NULL;
2002 }
2003
2004 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
2005 {
2006         int i;
2007
2008         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
2009
2010         if (rx_queue->skb)
2011                 dev_kfree_skb(rx_queue->skb);
2012
2013         for (i = 0; i < rx_queue->rx_ring_size; i++) {
2014                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
2015
2016                 rxbdp->lstatus = 0;
2017                 rxbdp->bufPtr = 0;
2018                 rxbdp++;
2019
2020                 if (!rxb->page)
2021                         continue;
2022
2023                 dma_unmap_page(rx_queue->dev, rxb->dma,
2024                                PAGE_SIZE, DMA_FROM_DEVICE);
2025                 __free_page(rxb->page);
2026
2027                 rxb->page = NULL;
2028         }
2029
2030         kfree(rx_queue->rx_buff);
2031         rx_queue->rx_buff = NULL;
2032 }
2033
2034 /* If there are any tx skbs or rx skbs still around, free them.
2035  * Then free tx_skbuff and rx_skbuff
2036  */
2037 static void free_skb_resources(struct gfar_private *priv)
2038 {
2039         struct gfar_priv_tx_q *tx_queue = NULL;
2040         struct gfar_priv_rx_q *rx_queue = NULL;
2041         int i;
2042
2043         /* Go through all the buffer descriptors and free their data buffers */
2044         for (i = 0; i < priv->num_tx_queues; i++) {
2045                 struct netdev_queue *txq;
2046
2047                 tx_queue = priv->tx_queue[i];
2048                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2049                 if (tx_queue->tx_skbuff)
2050                         free_skb_tx_queue(tx_queue);
2051                 netdev_tx_reset_queue(txq);
2052         }
2053
2054         for (i = 0; i < priv->num_rx_queues; i++) {
2055                 rx_queue = priv->rx_queue[i];
2056                 if (rx_queue->rx_buff)
2057                         free_skb_rx_queue(rx_queue);
2058         }
2059
2060         dma_free_coherent(priv->dev,
2061                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2062                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2063                           priv->tx_queue[0]->tx_bd_base,
2064                           priv->tx_queue[0]->tx_bd_dma_base);
2065 }
2066
2067 void gfar_start(struct gfar_private *priv)
2068 {
2069         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2070         u32 tempval;
2071         int i = 0;
2072
2073         /* Enable Rx/Tx hw queues */
2074         gfar_write(&regs->rqueue, priv->rqueue);
2075         gfar_write(&regs->tqueue, priv->tqueue);
2076
2077         /* Initialize DMACTRL to have WWR and WOP */
2078         tempval = gfar_read(&regs->dmactrl);
2079         tempval |= DMACTRL_INIT_SETTINGS;
2080         gfar_write(&regs->dmactrl, tempval);
2081
2082         /* Make sure we aren't stopped */
2083         tempval = gfar_read(&regs->dmactrl);
2084         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2085         gfar_write(&regs->dmactrl, tempval);
2086
2087         for (i = 0; i < priv->num_grps; i++) {
2088                 regs = priv->gfargrp[i].regs;
2089                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2090                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2091                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2092         }
2093
2094         /* Enable Rx/Tx DMA */
2095         tempval = gfar_read(&regs->maccfg1);
2096         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2097         gfar_write(&regs->maccfg1, tempval);
2098
2099         gfar_ints_enable(priv);
2100
2101         netif_trans_update(priv->ndev); /* prevent tx timeout */
2102 }
2103
2104 static void free_grp_irqs(struct gfar_priv_grp *grp)
2105 {
2106         free_irq(gfar_irq(grp, TX)->irq, grp);
2107         free_irq(gfar_irq(grp, RX)->irq, grp);
2108         free_irq(gfar_irq(grp, ER)->irq, grp);
2109 }
2110
2111 static int register_grp_irqs(struct gfar_priv_grp *grp)
2112 {
2113         struct gfar_private *priv = grp->priv;
2114         struct net_device *dev = priv->ndev;
2115         int err;
2116
2117         /* If the device has multiple interrupts, register for
2118          * them.  Otherwise, only register for the one
2119          */
2120         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2121                 /* Install our interrupt handlers for Error,
2122                  * Transmit, and Receive
2123                  */
2124                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2125                                   gfar_irq(grp, ER)->name, grp);
2126                 if (err < 0) {
2127                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2128                                   gfar_irq(grp, ER)->irq);
2129
2130                         goto err_irq_fail;
2131                 }
2132                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2133
2134                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2135                                   gfar_irq(grp, TX)->name, grp);
2136                 if (err < 0) {
2137                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2138                                   gfar_irq(grp, TX)->irq);
2139                         goto tx_irq_fail;
2140                 }
2141                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2142                                   gfar_irq(grp, RX)->name, grp);
2143                 if (err < 0) {
2144                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2145                                   gfar_irq(grp, RX)->irq);
2146                         goto rx_irq_fail;
2147                 }
2148                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2149
2150         } else {
2151                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2152                                   gfar_irq(grp, TX)->name, grp);
2153                 if (err < 0) {
2154                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2155                                   gfar_irq(grp, TX)->irq);
2156                         goto err_irq_fail;
2157                 }
2158                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2159         }
2160
2161         return 0;
2162
2163 rx_irq_fail:
2164         free_irq(gfar_irq(grp, TX)->irq, grp);
2165 tx_irq_fail:
2166         free_irq(gfar_irq(grp, ER)->irq, grp);
2167 err_irq_fail:
2168         return err;
2169
2170 }
2171
2172 static void gfar_free_irq(struct gfar_private *priv)
2173 {
2174         int i;
2175
2176         /* Free the IRQs */
2177         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2178                 for (i = 0; i < priv->num_grps; i++)
2179                         free_grp_irqs(&priv->gfargrp[i]);
2180         } else {
2181                 for (i = 0; i < priv->num_grps; i++)
2182                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2183                                  &priv->gfargrp[i]);
2184         }
2185 }
2186
2187 static int gfar_request_irq(struct gfar_private *priv)
2188 {
2189         int err, i, j;
2190
2191         for (i = 0; i < priv->num_grps; i++) {
2192                 err = register_grp_irqs(&priv->gfargrp[i]);
2193                 if (err) {
2194                         for (j = 0; j < i; j++)
2195                                 free_grp_irqs(&priv->gfargrp[j]);
2196                         return err;
2197                 }
2198         }
2199
2200         return 0;
2201 }
2202
2203 /* Bring the controller up and running */
2204 int startup_gfar(struct net_device *ndev)
2205 {
2206         struct gfar_private *priv = netdev_priv(ndev);
2207         int err;
2208
2209         gfar_mac_reset(priv);
2210
2211         err = gfar_alloc_skb_resources(ndev);
2212         if (err)
2213                 return err;
2214
2215         gfar_init_tx_rx_base(priv);
2216
2217         smp_mb__before_atomic();
2218         clear_bit(GFAR_DOWN, &priv->state);
2219         smp_mb__after_atomic();
2220
2221         /* Start Rx/Tx DMA and enable the interrupts */
2222         gfar_start(priv);
2223
2224         /* force link state update after mac reset */
2225         priv->oldlink = 0;
2226         priv->oldspeed = 0;
2227         priv->oldduplex = -1;
2228
2229         phy_start(ndev->phydev);
2230
2231         enable_napi(priv);
2232
2233         netif_tx_wake_all_queues(ndev);
2234
2235         return 0;
2236 }
2237
2238 /* Called when something needs to use the ethernet device
2239  * Returns 0 for success.
2240  */
2241 static int gfar_enet_open(struct net_device *dev)
2242 {
2243         struct gfar_private *priv = netdev_priv(dev);
2244         int err;
2245
2246         err = init_phy(dev);
2247         if (err)
2248                 return err;
2249
2250         err = gfar_request_irq(priv);
2251         if (err)
2252                 return err;
2253
2254         err = startup_gfar(dev);
2255         if (err)
2256                 return err;
2257
2258         return err;
2259 }
2260
2261 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2262 {
2263         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2264
2265         memset(fcb, 0, GMAC_FCB_LEN);
2266
2267         return fcb;
2268 }
2269
2270 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2271                                     int fcb_length)
2272 {
2273         /* If we're here, it's a IP packet with a TCP or UDP
2274          * payload.  We set it to checksum, using a pseudo-header
2275          * we provide
2276          */
2277         u8 flags = TXFCB_DEFAULT;
2278
2279         /* Tell the controller what the protocol is
2280          * And provide the already calculated phcs
2281          */
2282         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2283                 flags |= TXFCB_UDP;
2284                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2285         } else
2286                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2287
2288         /* l3os is the distance between the start of the
2289          * frame (skb->data) and the start of the IP hdr.
2290          * l4os is the distance between the start of the
2291          * l3 hdr and the l4 hdr
2292          */
2293         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2294         fcb->l4os = skb_network_header_len(skb);
2295
2296         fcb->flags = flags;
2297 }
2298
2299 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2300 {
2301         fcb->flags |= TXFCB_VLN;
2302         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2303 }
2304
2305 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2306                                       struct txbd8 *base, int ring_size)
2307 {
2308         struct txbd8 *new_bd = bdp + stride;
2309
2310         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2311 }
2312
2313 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2314                                       int ring_size)
2315 {
2316         return skip_txbd(bdp, 1, base, ring_size);
2317 }
2318
2319 /* eTSEC12: csum generation not supported for some fcb offsets */
2320 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2321                                        unsigned long fcb_addr)
2322 {
2323         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2324                (fcb_addr % 0x20) > 0x18);
2325 }
2326
2327 /* eTSEC76: csum generation for frames larger than 2500 may
2328  * cause excess delays before start of transmission
2329  */
2330 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2331                                        unsigned int len)
2332 {
2333         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2334                (len > 2500));
2335 }
2336
2337 /* This is called by the kernel when a frame is ready for transmission.
2338  * It is pointed to by the dev->hard_start_xmit function pointer
2339  */
2340 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2341 {
2342         struct gfar_private *priv = netdev_priv(dev);
2343         struct gfar_priv_tx_q *tx_queue = NULL;
2344         struct netdev_queue *txq;
2345         struct gfar __iomem *regs = NULL;
2346         struct txfcb *fcb = NULL;
2347         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2348         u32 lstatus;
2349         skb_frag_t *frag;
2350         int i, rq = 0;
2351         int do_tstamp, do_csum, do_vlan;
2352         u32 bufaddr;
2353         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2354
2355         rq = skb->queue_mapping;
2356         tx_queue = priv->tx_queue[rq];
2357         txq = netdev_get_tx_queue(dev, rq);
2358         base = tx_queue->tx_bd_base;
2359         regs = tx_queue->grp->regs;
2360
2361         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2362         do_vlan = skb_vlan_tag_present(skb);
2363         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2364                     priv->hwts_tx_en;
2365
2366         if (do_csum || do_vlan)
2367                 fcb_len = GMAC_FCB_LEN;
2368
2369         /* check if time stamp should be generated */
2370         if (unlikely(do_tstamp))
2371                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2372
2373         /* make space for additional header when fcb is needed */
2374         if (fcb_len) {
2375                 if (unlikely(skb_cow_head(skb, fcb_len))) {
2376                         dev->stats.tx_errors++;
2377                         dev_kfree_skb_any(skb);
2378                         return NETDEV_TX_OK;
2379                 }
2380         }
2381
2382         /* total number of fragments in the SKB */
2383         nr_frags = skb_shinfo(skb)->nr_frags;
2384
2385         /* calculate the required number of TxBDs for this skb */
2386         if (unlikely(do_tstamp))
2387                 nr_txbds = nr_frags + 2;
2388         else
2389                 nr_txbds = nr_frags + 1;
2390
2391         /* check if there is space to queue this packet */
2392         if (nr_txbds > tx_queue->num_txbdfree) {
2393                 /* no space, stop the queue */
2394                 netif_tx_stop_queue(txq);
2395                 dev->stats.tx_fifo_errors++;
2396                 return NETDEV_TX_BUSY;
2397         }
2398
2399         /* Update transmit stats */
2400         bytes_sent = skb->len;
2401         tx_queue->stats.tx_bytes += bytes_sent;
2402         /* keep Tx bytes on wire for BQL accounting */
2403         GFAR_CB(skb)->bytes_sent = bytes_sent;
2404         tx_queue->stats.tx_packets++;
2405
2406         txbdp = txbdp_start = tx_queue->cur_tx;
2407         lstatus = be32_to_cpu(txbdp->lstatus);
2408
2409         /* Add TxPAL between FCB and frame if required */
2410         if (unlikely(do_tstamp)) {
2411                 skb_push(skb, GMAC_TXPAL_LEN);
2412                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2413         }
2414
2415         /* Add TxFCB if required */
2416         if (fcb_len) {
2417                 fcb = gfar_add_fcb(skb);
2418                 lstatus |= BD_LFLAG(TXBD_TOE);
2419         }
2420
2421         /* Set up checksumming */
2422         if (do_csum) {
2423                 gfar_tx_checksum(skb, fcb, fcb_len);
2424
2425                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2426                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2427                         __skb_pull(skb, GMAC_FCB_LEN);
2428                         skb_checksum_help(skb);
2429                         if (do_vlan || do_tstamp) {
2430                                 /* put back a new fcb for vlan/tstamp TOE */
2431                                 fcb = gfar_add_fcb(skb);
2432                         } else {
2433                                 /* Tx TOE not used */
2434                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2435                                 fcb = NULL;
2436                         }
2437                 }
2438         }
2439
2440         if (do_vlan)
2441                 gfar_tx_vlan(skb, fcb);
2442
2443         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2444                                  DMA_TO_DEVICE);
2445         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2446                 goto dma_map_err;
2447
2448         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2449
2450         /* Time stamp insertion requires one additional TxBD */
2451         if (unlikely(do_tstamp))
2452                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2453                                                  tx_queue->tx_ring_size);
2454
2455         if (likely(!nr_frags)) {
2456                 if (likely(!do_tstamp))
2457                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2458         } else {
2459                 u32 lstatus_start = lstatus;
2460
2461                 /* Place the fragment addresses and lengths into the TxBDs */
2462                 frag = &skb_shinfo(skb)->frags[0];
2463                 for (i = 0; i < nr_frags; i++, frag++) {
2464                         unsigned int size;
2465
2466                         /* Point at the next BD, wrapping as needed */
2467                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2468
2469                         size = skb_frag_size(frag);
2470
2471                         lstatus = be32_to_cpu(txbdp->lstatus) | size |
2472                                   BD_LFLAG(TXBD_READY);
2473
2474                         /* Handle the last BD specially */
2475                         if (i == nr_frags - 1)
2476                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2477
2478                         bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
2479                                                    size, DMA_TO_DEVICE);
2480                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2481                                 goto dma_map_err;
2482
2483                         /* set the TxBD length and buffer pointer */
2484                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2485                         txbdp->lstatus = cpu_to_be32(lstatus);
2486                 }
2487
2488                 lstatus = lstatus_start;
2489         }
2490
2491         /* If time stamping is requested one additional TxBD must be set up. The
2492          * first TxBD points to the FCB and must have a data length of
2493          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2494          * the full frame length.
2495          */
2496         if (unlikely(do_tstamp)) {
2497                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2498
2499                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2500                 bufaddr += fcb_len;
2501
2502                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2503                               (skb_headlen(skb) - fcb_len);
2504                 if (!nr_frags)
2505                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2506
2507                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2508                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2509                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2510
2511                 /* Setup tx hardware time stamping */
2512                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2513                 fcb->ptp = 1;
2514         } else {
2515                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2516         }
2517
2518         netdev_tx_sent_queue(txq, bytes_sent);
2519
2520         gfar_wmb();
2521
2522         txbdp_start->lstatus = cpu_to_be32(lstatus);
2523
2524         gfar_wmb(); /* force lstatus write before tx_skbuff */
2525
2526         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2527
2528         /* Update the current skb pointer to the next entry we will use
2529          * (wrapping if necessary)
2530          */
2531         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2532                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2533
2534         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2535
2536         /* We can work in parallel with gfar_clean_tx_ring(), except
2537          * when modifying num_txbdfree. Note that we didn't grab the lock
2538          * when we were reading the num_txbdfree and checking for available
2539          * space, that's because outside of this function it can only grow.
2540          */
2541         spin_lock_bh(&tx_queue->txlock);
2542         /* reduce TxBD free count */
2543         tx_queue->num_txbdfree -= (nr_txbds);
2544         spin_unlock_bh(&tx_queue->txlock);
2545
2546         /* If the next BD still needs to be cleaned up, then the bds
2547          * are full.  We need to tell the kernel to stop sending us stuff.
2548          */
2549         if (!tx_queue->num_txbdfree) {
2550                 netif_tx_stop_queue(txq);
2551
2552                 dev->stats.tx_fifo_errors++;
2553         }
2554
2555         /* Tell the DMA to go go go */
2556         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2557
2558         return NETDEV_TX_OK;
2559
2560 dma_map_err:
2561         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2562         if (do_tstamp)
2563                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2564         for (i = 0; i < nr_frags; i++) {
2565                 lstatus = be32_to_cpu(txbdp->lstatus);
2566                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2567                         break;
2568
2569                 lstatus &= ~BD_LFLAG(TXBD_READY);
2570                 txbdp->lstatus = cpu_to_be32(lstatus);
2571                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2572                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2573                                DMA_TO_DEVICE);
2574                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2575         }
2576         gfar_wmb();
2577         dev_kfree_skb_any(skb);
2578         return NETDEV_TX_OK;
2579 }
2580
2581 /* Stops the kernel queue, and halts the controller */
2582 static int gfar_close(struct net_device *dev)
2583 {
2584         struct gfar_private *priv = netdev_priv(dev);
2585
2586         cancel_work_sync(&priv->reset_task);
2587         stop_gfar(dev);
2588
2589         /* Disconnect from the PHY */
2590         phy_disconnect(dev->phydev);
2591
2592         gfar_free_irq(priv);
2593
2594         return 0;
2595 }
2596
2597 /* Changes the mac address if the controller is not running. */
2598 static int gfar_set_mac_address(struct net_device *dev)
2599 {
2600         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2601
2602         return 0;
2603 }
2604
2605 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2606 {
2607         struct gfar_private *priv = netdev_priv(dev);
2608         int frame_size = new_mtu + ETH_HLEN;
2609
2610         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2611                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2612                 return -EINVAL;
2613         }
2614
2615         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2616                 cpu_relax();
2617
2618         if (dev->flags & IFF_UP)
2619                 stop_gfar(dev);
2620
2621         dev->mtu = new_mtu;
2622
2623         if (dev->flags & IFF_UP)
2624                 startup_gfar(dev);
2625
2626         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2627
2628         return 0;
2629 }
2630
2631 void reset_gfar(struct net_device *ndev)
2632 {
2633         struct gfar_private *priv = netdev_priv(ndev);
2634
2635         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2636                 cpu_relax();
2637
2638         stop_gfar(ndev);
2639         startup_gfar(ndev);
2640
2641         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2642 }
2643
2644 /* gfar_reset_task gets scheduled when a packet has not been
2645  * transmitted after a set amount of time.
2646  * For now, assume that clearing out all the structures, and
2647  * starting over will fix the problem.
2648  */
2649 static void gfar_reset_task(struct work_struct *work)
2650 {
2651         struct gfar_private *priv = container_of(work, struct gfar_private,
2652                                                  reset_task);
2653         reset_gfar(priv->ndev);
2654 }
2655
2656 static void gfar_timeout(struct net_device *dev)
2657 {
2658         struct gfar_private *priv = netdev_priv(dev);
2659
2660         dev->stats.tx_errors++;
2661         schedule_work(&priv->reset_task);
2662 }
2663
2664 /* Interrupt Handler for Transmit complete */
2665 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2666 {
2667         struct net_device *dev = tx_queue->dev;
2668         struct netdev_queue *txq;
2669         struct gfar_private *priv = netdev_priv(dev);
2670         struct txbd8 *bdp, *next = NULL;
2671         struct txbd8 *lbdp = NULL;
2672         struct txbd8 *base = tx_queue->tx_bd_base;
2673         struct sk_buff *skb;
2674         int skb_dirtytx;
2675         int tx_ring_size = tx_queue->tx_ring_size;
2676         int frags = 0, nr_txbds = 0;
2677         int i;
2678         int howmany = 0;
2679         int tqi = tx_queue->qindex;
2680         unsigned int bytes_sent = 0;
2681         u32 lstatus;
2682         size_t buflen;
2683
2684         txq = netdev_get_tx_queue(dev, tqi);
2685         bdp = tx_queue->dirty_tx;
2686         skb_dirtytx = tx_queue->skb_dirtytx;
2687
2688         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2689                 bool do_tstamp;
2690
2691                 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2692                             priv->hwts_tx_en;
2693
2694                 frags = skb_shinfo(skb)->nr_frags;
2695
2696                 /* When time stamping, one additional TxBD must be freed.
2697                  * Also, we need to dma_unmap_single() the TxPAL.
2698                  */
2699                 if (unlikely(do_tstamp))
2700                         nr_txbds = frags + 2;
2701                 else
2702                         nr_txbds = frags + 1;
2703
2704                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2705
2706                 lstatus = be32_to_cpu(lbdp->lstatus);
2707
2708                 /* Only clean completed frames */
2709                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2710                     (lstatus & BD_LENGTH_MASK))
2711                         break;
2712
2713                 if (unlikely(do_tstamp)) {
2714                         next = next_txbd(bdp, base, tx_ring_size);
2715                         buflen = be16_to_cpu(next->length) +
2716                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2717                 } else
2718                         buflen = be16_to_cpu(bdp->length);
2719
2720                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2721                                  buflen, DMA_TO_DEVICE);
2722
2723                 if (unlikely(do_tstamp)) {
2724                         struct skb_shared_hwtstamps shhwtstamps;
2725                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2726                                           ~0x7UL);
2727
2728                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2729                         shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2730                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2731                         skb_tstamp_tx(skb, &shhwtstamps);
2732                         gfar_clear_txbd_status(bdp);
2733                         bdp = next;
2734                 }
2735
2736                 gfar_clear_txbd_status(bdp);
2737                 bdp = next_txbd(bdp, base, tx_ring_size);
2738
2739                 for (i = 0; i < frags; i++) {
2740                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2741                                        be16_to_cpu(bdp->length),
2742                                        DMA_TO_DEVICE);
2743                         gfar_clear_txbd_status(bdp);
2744                         bdp = next_txbd(bdp, base, tx_ring_size);
2745                 }
2746
2747                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2748
2749                 dev_kfree_skb_any(skb);
2750
2751                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2752
2753                 skb_dirtytx = (skb_dirtytx + 1) &
2754                               TX_RING_MOD_MASK(tx_ring_size);
2755
2756                 howmany++;
2757                 spin_lock(&tx_queue->txlock);
2758                 tx_queue->num_txbdfree += nr_txbds;
2759                 spin_unlock(&tx_queue->txlock);
2760         }
2761
2762         /* If we freed a buffer, we can restart transmission, if necessary */
2763         if (tx_queue->num_txbdfree &&
2764             netif_tx_queue_stopped(txq) &&
2765             !(test_bit(GFAR_DOWN, &priv->state)))
2766                 netif_wake_subqueue(priv->ndev, tqi);
2767
2768         /* Update dirty indicators */
2769         tx_queue->skb_dirtytx = skb_dirtytx;
2770         tx_queue->dirty_tx = bdp;
2771
2772         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2773 }
2774
2775 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2776 {
2777         struct page *page;
2778         dma_addr_t addr;
2779
2780         page = dev_alloc_page();
2781         if (unlikely(!page))
2782                 return false;
2783
2784         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2785         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2786                 __free_page(page);
2787
2788                 return false;
2789         }
2790
2791         rxb->dma = addr;
2792         rxb->page = page;
2793         rxb->page_offset = 0;
2794
2795         return true;
2796 }
2797
2798 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2799 {
2800         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2801         struct gfar_extra_stats *estats = &priv->extra_stats;
2802
2803         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2804         atomic64_inc(&estats->rx_alloc_err);
2805 }
2806
2807 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2808                                 int alloc_cnt)
2809 {
2810         struct rxbd8 *bdp;
2811         struct gfar_rx_buff *rxb;
2812         int i;
2813
2814         i = rx_queue->next_to_use;
2815         bdp = &rx_queue->rx_bd_base[i];
2816         rxb = &rx_queue->rx_buff[i];
2817
2818         while (alloc_cnt--) {
2819                 /* try reuse page */
2820                 if (unlikely(!rxb->page)) {
2821                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2822                                 gfar_rx_alloc_err(rx_queue);
2823                                 break;
2824                         }
2825                 }
2826
2827                 /* Setup the new RxBD */
2828                 gfar_init_rxbdp(rx_queue, bdp,
2829                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2830
2831                 /* Update to the next pointer */
2832                 bdp++;
2833                 rxb++;
2834
2835                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2836                         i = 0;
2837                         bdp = rx_queue->rx_bd_base;
2838                         rxb = rx_queue->rx_buff;
2839                 }
2840         }
2841
2842         rx_queue->next_to_use = i;
2843         rx_queue->next_to_alloc = i;
2844 }
2845
2846 static void count_errors(u32 lstatus, struct net_device *ndev)
2847 {
2848         struct gfar_private *priv = netdev_priv(ndev);
2849         struct net_device_stats *stats = &ndev->stats;
2850         struct gfar_extra_stats *estats = &priv->extra_stats;
2851
2852         /* If the packet was truncated, none of the other errors matter */
2853         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2854                 stats->rx_length_errors++;
2855
2856                 atomic64_inc(&estats->rx_trunc);
2857
2858                 return;
2859         }
2860         /* Count the errors, if there were any */
2861         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2862                 stats->rx_length_errors++;
2863
2864                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2865                         atomic64_inc(&estats->rx_large);
2866                 else
2867                         atomic64_inc(&estats->rx_short);
2868         }
2869         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2870                 stats->rx_frame_errors++;
2871                 atomic64_inc(&estats->rx_nonoctet);
2872         }
2873         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2874                 atomic64_inc(&estats->rx_crcerr);
2875                 stats->rx_crc_errors++;
2876         }
2877         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2878                 atomic64_inc(&estats->rx_overrun);
2879                 stats->rx_over_errors++;
2880         }
2881 }
2882
2883 irqreturn_t gfar_receive(int irq, void *grp_id)
2884 {
2885         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2886         unsigned long flags;
2887         u32 imask, ievent;
2888
2889         ievent = gfar_read(&grp->regs->ievent);
2890
2891         if (unlikely(ievent & IEVENT_FGPI)) {
2892                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2893                 return IRQ_HANDLED;
2894         }
2895
2896         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2897                 spin_lock_irqsave(&grp->grplock, flags);
2898                 imask = gfar_read(&grp->regs->imask);
2899                 imask &= IMASK_RX_DISABLED;
2900                 gfar_write(&grp->regs->imask, imask);
2901                 spin_unlock_irqrestore(&grp->grplock, flags);
2902                 __napi_schedule(&grp->napi_rx);
2903         } else {
2904                 /* Clear IEVENT, so interrupts aren't called again
2905                  * because of the packets that have already arrived.
2906                  */
2907                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2908         }
2909
2910         return IRQ_HANDLED;
2911 }
2912
2913 /* Interrupt Handler for Transmit complete */
2914 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2915 {
2916         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2917         unsigned long flags;
2918         u32 imask;
2919
2920         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2921                 spin_lock_irqsave(&grp->grplock, flags);
2922                 imask = gfar_read(&grp->regs->imask);
2923                 imask &= IMASK_TX_DISABLED;
2924                 gfar_write(&grp->regs->imask, imask);
2925                 spin_unlock_irqrestore(&grp->grplock, flags);
2926                 __napi_schedule(&grp->napi_tx);
2927         } else {
2928                 /* Clear IEVENT, so interrupts aren't called again
2929                  * because of the packets that have already arrived.
2930                  */
2931                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2932         }
2933
2934         return IRQ_HANDLED;
2935 }
2936
2937 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2938                              struct sk_buff *skb, bool first)
2939 {
2940         int size = lstatus & BD_LENGTH_MASK;
2941         struct page *page = rxb->page;
2942
2943         if (likely(first)) {
2944                 skb_put(skb, size);
2945         } else {
2946                 /* the last fragments' length contains the full frame length */
2947                 if (lstatus & BD_LFLAG(RXBD_LAST))
2948                         size -= skb->len;
2949
2950                 WARN(size < 0, "gianfar: rx fragment size underflow");
2951                 if (size < 0)
2952                         return false;
2953
2954                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2955                                 rxb->page_offset + RXBUF_ALIGNMENT,
2956                                 size, GFAR_RXB_TRUESIZE);
2957         }
2958
2959         /* try reuse page */
2960         if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2961                 return false;
2962
2963         /* change offset to the other half */
2964         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2965
2966         page_ref_inc(page);
2967
2968         return true;
2969 }
2970
2971 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2972                                struct gfar_rx_buff *old_rxb)
2973 {
2974         struct gfar_rx_buff *new_rxb;
2975         u16 nta = rxq->next_to_alloc;
2976
2977         new_rxb = &rxq->rx_buff[nta];
2978
2979         /* find next buf that can reuse a page */
2980         nta++;
2981         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2982
2983         /* copy page reference */
2984         *new_rxb = *old_rxb;
2985
2986         /* sync for use by the device */
2987         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2988                                          old_rxb->page_offset,
2989                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2990 }
2991
2992 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2993                                             u32 lstatus, struct sk_buff *skb)
2994 {
2995         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2996         struct page *page = rxb->page;
2997         bool first = false;
2998
2999         if (likely(!skb)) {
3000                 void *buff_addr = page_address(page) + rxb->page_offset;
3001
3002                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
3003                 if (unlikely(!skb)) {
3004                         gfar_rx_alloc_err(rx_queue);
3005                         return NULL;
3006                 }
3007                 skb_reserve(skb, RXBUF_ALIGNMENT);
3008                 first = true;
3009         }
3010
3011         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
3012                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
3013
3014         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
3015                 /* reuse the free half of the page */
3016                 gfar_reuse_rx_page(rx_queue, rxb);
3017         } else {
3018                 /* page cannot be reused, unmap it */
3019                 dma_unmap_page(rx_queue->dev, rxb->dma,
3020                                PAGE_SIZE, DMA_FROM_DEVICE);
3021         }
3022
3023         /* clear rxb content */
3024         rxb->page = NULL;
3025
3026         return skb;
3027 }
3028
3029 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3030 {
3031         /* If valid headers were found, and valid sums
3032          * were verified, then we tell the kernel that no
3033          * checksumming is necessary.  Otherwise, it is [FIXME]
3034          */
3035         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3036             (RXFCB_CIP | RXFCB_CTU))
3037                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3038         else
3039                 skb_checksum_none_assert(skb);
3040 }
3041
3042 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3043 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3044 {
3045         struct gfar_private *priv = netdev_priv(ndev);
3046         struct rxfcb *fcb = NULL;
3047
3048         /* fcb is at the beginning if exists */
3049         fcb = (struct rxfcb *)skb->data;
3050
3051         /* Remove the FCB from the skb
3052          * Remove the padded bytes, if there are any
3053          */
3054         if (priv->uses_rxfcb)
3055                 skb_pull(skb, GMAC_FCB_LEN);
3056
3057         /* Get receive timestamp from the skb */
3058         if (priv->hwts_rx_en) {
3059                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3060                 u64 *ns = (u64 *) skb->data;
3061
3062                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3063                 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
3064         }
3065
3066         if (priv->padding)
3067                 skb_pull(skb, priv->padding);
3068
3069         /* Trim off the FCS */
3070         pskb_trim(skb, skb->len - ETH_FCS_LEN);
3071
3072         if (ndev->features & NETIF_F_RXCSUM)
3073                 gfar_rx_checksum(skb, fcb);
3074
3075         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3076          * Even if vlan rx accel is disabled, on some chips
3077          * RXFCB_VLN is pseudo randomly set.
3078          */
3079         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3080             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3081                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3082                                        be16_to_cpu(fcb->vlctl));
3083 }
3084
3085 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3086  * until the budget/quota has been reached. Returns the number
3087  * of frames handled
3088  */
3089 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3090 {
3091         struct net_device *ndev = rx_queue->ndev;
3092         struct gfar_private *priv = netdev_priv(ndev);
3093         struct rxbd8 *bdp;
3094         int i, howmany = 0;
3095         struct sk_buff *skb = rx_queue->skb;
3096         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3097         unsigned int total_bytes = 0, total_pkts = 0;
3098
3099         /* Get the first full descriptor */
3100         i = rx_queue->next_to_clean;
3101
3102         while (rx_work_limit--) {
3103                 u32 lstatus;
3104
3105                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3106                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3107                         cleaned_cnt = 0;
3108                 }
3109
3110                 bdp = &rx_queue->rx_bd_base[i];
3111                 lstatus = be32_to_cpu(bdp->lstatus);
3112                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3113                         break;
3114
3115                 /* lost RXBD_LAST descriptor due to overrun */
3116                 if (skb &&
3117                     (lstatus & BD_LFLAG(RXBD_FIRST))) {
3118                         /* discard faulty buffer */
3119                         dev_kfree_skb(skb);
3120                         skb = NULL;
3121                         rx_queue->stats.rx_dropped++;
3122
3123                         /* can continue normally */
3124                 }
3125
3126                 /* order rx buffer descriptor reads */
3127                 rmb();
3128
3129                 /* fetch next to clean buffer from the ring */
3130                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3131                 if (unlikely(!skb))
3132                         break;
3133
3134                 cleaned_cnt++;
3135                 howmany++;
3136
3137                 if (unlikely(++i == rx_queue->rx_ring_size))
3138                         i = 0;
3139
3140                 rx_queue->next_to_clean = i;
3141
3142                 /* fetch next buffer if not the last in frame */
3143                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3144                         continue;
3145
3146                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3147                         count_errors(lstatus, ndev);
3148
3149                         /* discard faulty buffer */
3150                         dev_kfree_skb(skb);
3151                         skb = NULL;
3152                         rx_queue->stats.rx_dropped++;
3153                         continue;
3154                 }
3155
3156                 gfar_process_frame(ndev, skb);
3157
3158                 /* Increment the number of packets */
3159                 total_pkts++;
3160                 total_bytes += skb->len;
3161
3162                 skb_record_rx_queue(skb, rx_queue->qindex);
3163
3164                 skb->protocol = eth_type_trans(skb, ndev);
3165
3166                 /* Send the packet up the stack */
3167                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3168
3169                 skb = NULL;
3170         }
3171
3172         /* Store incomplete frames for completion */
3173         rx_queue->skb = skb;
3174
3175         rx_queue->stats.rx_packets += total_pkts;
3176         rx_queue->stats.rx_bytes += total_bytes;
3177
3178         if (cleaned_cnt)
3179                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3180
3181         /* Update Last Free RxBD pointer for LFC */
3182         if (unlikely(priv->tx_actual_en)) {
3183                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3184
3185                 gfar_write(rx_queue->rfbptr, bdp_dma);
3186         }
3187
3188         return howmany;
3189 }
3190
3191 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3192 {
3193         struct gfar_priv_grp *gfargrp =
3194                 container_of(napi, struct gfar_priv_grp, napi_rx);
3195         struct gfar __iomem *regs = gfargrp->regs;
3196         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3197         int work_done = 0;
3198
3199         /* Clear IEVENT, so interrupts aren't called again
3200          * because of the packets that have already arrived
3201          */
3202         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3203
3204         work_done = gfar_clean_rx_ring(rx_queue, budget);
3205
3206         if (work_done < budget) {
3207                 u32 imask;
3208                 napi_complete(napi);
3209                 /* Clear the halt bit in RSTAT */
3210                 gfar_write(&regs->rstat, gfargrp->rstat);
3211
3212                 spin_lock_irq(&gfargrp->grplock);
3213                 imask = gfar_read(&regs->imask);
3214                 imask |= IMASK_RX_DEFAULT;
3215                 gfar_write(&regs->imask, imask);
3216                 spin_unlock_irq(&gfargrp->grplock);
3217         }
3218
3219         return work_done;
3220 }
3221
3222 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3223 {
3224         struct gfar_priv_grp *gfargrp =
3225                 container_of(napi, struct gfar_priv_grp, napi_tx);
3226         struct gfar __iomem *regs = gfargrp->regs;
3227         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3228         u32 imask;
3229
3230         /* Clear IEVENT, so interrupts aren't called again
3231          * because of the packets that have already arrived
3232          */
3233         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3234
3235         /* run Tx cleanup to completion */
3236         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3237                 gfar_clean_tx_ring(tx_queue);
3238
3239         napi_complete(napi);
3240
3241         spin_lock_irq(&gfargrp->grplock);
3242         imask = gfar_read(&regs->imask);
3243         imask |= IMASK_TX_DEFAULT;
3244         gfar_write(&regs->imask, imask);
3245         spin_unlock_irq(&gfargrp->grplock);
3246
3247         return 0;
3248 }
3249
3250 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3251 {
3252         struct gfar_priv_grp *gfargrp =
3253                 container_of(napi, struct gfar_priv_grp, napi_rx);
3254         struct gfar_private *priv = gfargrp->priv;
3255         struct gfar __iomem *regs = gfargrp->regs;
3256         struct gfar_priv_rx_q *rx_queue = NULL;
3257         int work_done = 0, work_done_per_q = 0;
3258         int i, budget_per_q = 0;
3259         unsigned long rstat_rxf;
3260         int num_act_queues;
3261
3262         /* Clear IEVENT, so interrupts aren't called again
3263          * because of the packets that have already arrived
3264          */
3265         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3266
3267         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3268
3269         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3270         if (num_act_queues)
3271                 budget_per_q = budget/num_act_queues;
3272
3273         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3274                 /* skip queue if not active */
3275                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3276                         continue;
3277
3278                 rx_queue = priv->rx_queue[i];
3279                 work_done_per_q =
3280                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3281                 work_done += work_done_per_q;
3282
3283                 /* finished processing this queue */
3284                 if (work_done_per_q < budget_per_q) {
3285                         /* clear active queue hw indication */
3286                         gfar_write(&regs->rstat,
3287                                    RSTAT_CLEAR_RXF0 >> i);
3288                         num_act_queues--;
3289
3290                         if (!num_act_queues)
3291                                 break;
3292                 }
3293         }
3294
3295         if (!num_act_queues) {
3296                 u32 imask;
3297                 napi_complete(napi);
3298
3299                 /* Clear the halt bit in RSTAT */
3300                 gfar_write(&regs->rstat, gfargrp->rstat);
3301
3302                 spin_lock_irq(&gfargrp->grplock);
3303                 imask = gfar_read(&regs->imask);
3304                 imask |= IMASK_RX_DEFAULT;
3305                 gfar_write(&regs->imask, imask);
3306                 spin_unlock_irq(&gfargrp->grplock);
3307         }
3308
3309         return work_done;
3310 }
3311
3312 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3313 {
3314         struct gfar_priv_grp *gfargrp =
3315                 container_of(napi, struct gfar_priv_grp, napi_tx);
3316         struct gfar_private *priv = gfargrp->priv;
3317         struct gfar __iomem *regs = gfargrp->regs;
3318         struct gfar_priv_tx_q *tx_queue = NULL;
3319         int has_tx_work = 0;
3320         int i;
3321
3322         /* Clear IEVENT, so interrupts aren't called again
3323          * because of the packets that have already arrived
3324          */
3325         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3326
3327         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3328                 tx_queue = priv->tx_queue[i];
3329                 /* run Tx cleanup to completion */
3330                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3331                         gfar_clean_tx_ring(tx_queue);
3332                         has_tx_work = 1;
3333                 }
3334         }
3335
3336         if (!has_tx_work) {
3337                 u32 imask;
3338                 napi_complete(napi);
3339
3340                 spin_lock_irq(&gfargrp->grplock);
3341                 imask = gfar_read(&regs->imask);
3342                 imask |= IMASK_TX_DEFAULT;
3343                 gfar_write(&regs->imask, imask);
3344                 spin_unlock_irq(&gfargrp->grplock);
3345         }
3346
3347         return 0;
3348 }
3349
3350
3351 #ifdef CONFIG_NET_POLL_CONTROLLER
3352 /* Polling 'interrupt' - used by things like netconsole to send skbs
3353  * without having to re-enable interrupts. It's not called while
3354  * the interrupt routine is executing.
3355  */
3356 static void gfar_netpoll(struct net_device *dev)
3357 {
3358         struct gfar_private *priv = netdev_priv(dev);
3359         int i;
3360
3361         /* If the device has multiple interrupts, run tx/rx */
3362         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3363                 for (i = 0; i < priv->num_grps; i++) {
3364                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3365
3366                         disable_irq(gfar_irq(grp, TX)->irq);
3367                         disable_irq(gfar_irq(grp, RX)->irq);
3368                         disable_irq(gfar_irq(grp, ER)->irq);
3369                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3370                         enable_irq(gfar_irq(grp, ER)->irq);
3371                         enable_irq(gfar_irq(grp, RX)->irq);
3372                         enable_irq(gfar_irq(grp, TX)->irq);
3373                 }
3374         } else {
3375                 for (i = 0; i < priv->num_grps; i++) {
3376                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3377
3378                         disable_irq(gfar_irq(grp, TX)->irq);
3379                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3380                         enable_irq(gfar_irq(grp, TX)->irq);
3381                 }
3382         }
3383 }
3384 #endif
3385
3386 /* The interrupt handler for devices with one interrupt */
3387 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3388 {
3389         struct gfar_priv_grp *gfargrp = grp_id;
3390
3391         /* Save ievent for future reference */
3392         u32 events = gfar_read(&gfargrp->regs->ievent);
3393
3394         /* Check for reception */
3395         if (events & IEVENT_RX_MASK)
3396                 gfar_receive(irq, grp_id);
3397
3398         /* Check for transmit completion */
3399         if (events & IEVENT_TX_MASK)
3400                 gfar_transmit(irq, grp_id);
3401
3402         /* Check for errors */
3403         if (events & IEVENT_ERR_MASK)
3404                 gfar_error(irq, grp_id);
3405
3406         return IRQ_HANDLED;
3407 }
3408
3409 /* Called every time the controller might need to be made
3410  * aware of new link state.  The PHY code conveys this
3411  * information through variables in the phydev structure, and this
3412  * function converts those variables into the appropriate
3413  * register values, and can bring down the device if needed.
3414  */
3415 static void adjust_link(struct net_device *dev)
3416 {
3417         struct gfar_private *priv = netdev_priv(dev);
3418         struct phy_device *phydev = dev->phydev;
3419
3420         if (unlikely(phydev->link != priv->oldlink ||
3421                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3422                                        phydev->speed != priv->oldspeed))))
3423                 gfar_update_link_state(priv);
3424 }
3425
3426 /* Update the hash table based on the current list of multicast
3427  * addresses we subscribe to.  Also, change the promiscuity of
3428  * the device based on the flags (this function is called
3429  * whenever dev->flags is changed
3430  */
3431 static void gfar_set_multi(struct net_device *dev)
3432 {
3433         struct netdev_hw_addr *ha;
3434         struct gfar_private *priv = netdev_priv(dev);
3435         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3436         u32 tempval;
3437
3438         if (dev->flags & IFF_PROMISC) {
3439                 /* Set RCTRL to PROM */
3440                 tempval = gfar_read(&regs->rctrl);
3441                 tempval |= RCTRL_PROM;
3442                 gfar_write(&regs->rctrl, tempval);
3443         } else {
3444                 /* Set RCTRL to not PROM */
3445                 tempval = gfar_read(&regs->rctrl);
3446                 tempval &= ~(RCTRL_PROM);
3447                 gfar_write(&regs->rctrl, tempval);
3448         }
3449
3450         if (dev->flags & IFF_ALLMULTI) {
3451                 /* Set the hash to rx all multicast frames */
3452                 gfar_write(&regs->igaddr0, 0xffffffff);
3453                 gfar_write(&regs->igaddr1, 0xffffffff);
3454                 gfar_write(&regs->igaddr2, 0xffffffff);
3455                 gfar_write(&regs->igaddr3, 0xffffffff);
3456                 gfar_write(&regs->igaddr4, 0xffffffff);
3457                 gfar_write(&regs->igaddr5, 0xffffffff);
3458                 gfar_write(&regs->igaddr6, 0xffffffff);
3459                 gfar_write(&regs->igaddr7, 0xffffffff);
3460                 gfar_write(&regs->gaddr0, 0xffffffff);
3461                 gfar_write(&regs->gaddr1, 0xffffffff);
3462                 gfar_write(&regs->gaddr2, 0xffffffff);
3463                 gfar_write(&regs->gaddr3, 0xffffffff);
3464                 gfar_write(&regs->gaddr4, 0xffffffff);
3465                 gfar_write(&regs->gaddr5, 0xffffffff);
3466                 gfar_write(&regs->gaddr6, 0xffffffff);
3467                 gfar_write(&regs->gaddr7, 0xffffffff);
3468         } else {
3469                 int em_num;
3470                 int idx;
3471
3472                 /* zero out the hash */
3473                 gfar_write(&regs->igaddr0, 0x0);
3474                 gfar_write(&regs->igaddr1, 0x0);
3475                 gfar_write(&regs->igaddr2, 0x0);
3476                 gfar_write(&regs->igaddr3, 0x0);
3477                 gfar_write(&regs->igaddr4, 0x0);
3478                 gfar_write(&regs->igaddr5, 0x0);
3479                 gfar_write(&regs->igaddr6, 0x0);
3480                 gfar_write(&regs->igaddr7, 0x0);
3481                 gfar_write(&regs->gaddr0, 0x0);
3482                 gfar_write(&regs->gaddr1, 0x0);
3483                 gfar_write(&regs->gaddr2, 0x0);
3484                 gfar_write(&regs->gaddr3, 0x0);
3485                 gfar_write(&regs->gaddr4, 0x0);
3486                 gfar_write(&regs->gaddr5, 0x0);
3487                 gfar_write(&regs->gaddr6, 0x0);
3488                 gfar_write(&regs->gaddr7, 0x0);
3489
3490                 /* If we have extended hash tables, we need to
3491                  * clear the exact match registers to prepare for
3492                  * setting them
3493                  */
3494                 if (priv->extended_hash) {
3495                         em_num = GFAR_EM_NUM + 1;
3496                         gfar_clear_exact_match(dev);
3497                         idx = 1;
3498                 } else {
3499                         idx = 0;
3500                         em_num = 0;
3501                 }
3502
3503                 if (netdev_mc_empty(dev))
3504                         return;
3505
3506                 /* Parse the list, and set the appropriate bits */
3507                 netdev_for_each_mc_addr(ha, dev) {
3508                         if (idx < em_num) {
3509                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3510                                 idx++;
3511                         } else
3512                                 gfar_set_hash_for_addr(dev, ha->addr);
3513                 }
3514         }
3515 }
3516
3517
3518 /* Clears each of the exact match registers to zero, so they
3519  * don't interfere with normal reception
3520  */
3521 static void gfar_clear_exact_match(struct net_device *dev)
3522 {
3523         int idx;
3524         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3525
3526         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3527                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3528 }
3529
3530 /* Set the appropriate hash bit for the given addr */
3531 /* The algorithm works like so:
3532  * 1) Take the Destination Address (ie the multicast address), and
3533  * do a CRC on it (little endian), and reverse the bits of the
3534  * result.
3535  * 2) Use the 8 most significant bits as a hash into a 256-entry
3536  * table.  The table is controlled through 8 32-bit registers:
3537  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3538  * gaddr7.  This means that the 3 most significant bits in the
3539  * hash index which gaddr register to use, and the 5 other bits
3540  * indicate which bit (assuming an IBM numbering scheme, which
3541  * for PowerPC (tm) is usually the case) in the register holds
3542  * the entry.
3543  */
3544 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3545 {
3546         u32 tempval;
3547         struct gfar_private *priv = netdev_priv(dev);
3548         u32 result = ether_crc(ETH_ALEN, addr);
3549         int width = priv->hash_width;
3550         u8 whichbit = (result >> (32 - width)) & 0x1f;
3551         u8 whichreg = result >> (32 - width + 5);
3552         u32 value = (1 << (31-whichbit));
3553
3554         tempval = gfar_read(priv->hash_regs[whichreg]);
3555         tempval |= value;
3556         gfar_write(priv->hash_regs[whichreg], tempval);
3557 }
3558
3559
3560 /* There are multiple MAC Address register pairs on some controllers
3561  * This function sets the numth pair to a given address
3562  */
3563 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3564                                   const u8 *addr)
3565 {
3566         struct gfar_private *priv = netdev_priv(dev);
3567         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3568         u32 tempval;
3569         u32 __iomem *macptr = &regs->macstnaddr1;
3570
3571         macptr += num*2;
3572
3573         /* For a station address of 0x12345678ABCD in transmission
3574          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3575          * MACnADDR2 is set to 0x34120000.
3576          */
3577         tempval = (addr[5] << 24) | (addr[4] << 16) |
3578                   (addr[3] << 8)  |  addr[2];
3579
3580         gfar_write(macptr, tempval);
3581
3582         tempval = (addr[1] << 24) | (addr[0] << 16);
3583
3584         gfar_write(macptr+1, tempval);
3585 }
3586
3587 /* GFAR error interrupt handler */
3588 static irqreturn_t gfar_error(int irq, void *grp_id)
3589 {
3590         struct gfar_priv_grp *gfargrp = grp_id;
3591         struct gfar __iomem *regs = gfargrp->regs;
3592         struct gfar_private *priv= gfargrp->priv;
3593         struct net_device *dev = priv->ndev;
3594
3595         /* Save ievent for future reference */
3596         u32 events = gfar_read(&regs->ievent);
3597
3598         /* Clear IEVENT */
3599         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3600
3601         /* Magic Packet is not an error. */
3602         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3603             (events & IEVENT_MAG))
3604                 events &= ~IEVENT_MAG;
3605
3606         /* Hmm... */
3607         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3608                 netdev_dbg(dev,
3609                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3610                            events, gfar_read(&regs->imask));
3611
3612         /* Update the error counters */
3613         if (events & IEVENT_TXE) {
3614                 dev->stats.tx_errors++;
3615
3616                 if (events & IEVENT_LC)
3617                         dev->stats.tx_window_errors++;
3618                 if (events & IEVENT_CRL)
3619                         dev->stats.tx_aborted_errors++;
3620                 if (events & IEVENT_XFUN) {
3621                         netif_dbg(priv, tx_err, dev,
3622                                   "TX FIFO underrun, packet dropped\n");
3623                         dev->stats.tx_dropped++;
3624                         atomic64_inc(&priv->extra_stats.tx_underrun);
3625
3626                         schedule_work(&priv->reset_task);
3627                 }
3628                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3629         }
3630         if (events & IEVENT_BSY) {
3631                 dev->stats.rx_over_errors++;
3632                 atomic64_inc(&priv->extra_stats.rx_bsy);
3633
3634                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3635                           gfar_read(&regs->rstat));
3636         }
3637         if (events & IEVENT_BABR) {
3638                 dev->stats.rx_errors++;
3639                 atomic64_inc(&priv->extra_stats.rx_babr);
3640
3641                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3642         }
3643         if (events & IEVENT_EBERR) {
3644                 atomic64_inc(&priv->extra_stats.eberr);
3645                 netif_dbg(priv, rx_err, dev, "bus error\n");
3646         }
3647         if (events & IEVENT_RXC)
3648                 netif_dbg(priv, rx_status, dev, "control frame\n");
3649
3650         if (events & IEVENT_BABT) {
3651                 atomic64_inc(&priv->extra_stats.tx_babt);
3652                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3653         }
3654         return IRQ_HANDLED;
3655 }
3656
3657 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3658 {
3659         struct net_device *ndev = priv->ndev;
3660         struct phy_device *phydev = ndev->phydev;
3661         u32 val = 0;
3662
3663         if (!phydev->duplex)
3664                 return val;
3665
3666         if (!priv->pause_aneg_en) {
3667                 if (priv->tx_pause_en)
3668                         val |= MACCFG1_TX_FLOW;
3669                 if (priv->rx_pause_en)
3670                         val |= MACCFG1_RX_FLOW;
3671         } else {
3672                 u16 lcl_adv, rmt_adv;
3673                 u8 flowctrl;
3674                 /* get link partner capabilities */
3675                 rmt_adv = 0;
3676                 if (phydev->pause)
3677                         rmt_adv = LPA_PAUSE_CAP;
3678                 if (phydev->asym_pause)
3679                         rmt_adv |= LPA_PAUSE_ASYM;
3680
3681                 lcl_adv = 0;
3682                 if (phydev->advertising & ADVERTISED_Pause)
3683                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3684                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3685                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3686
3687                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3688                 if (flowctrl & FLOW_CTRL_TX)
3689                         val |= MACCFG1_TX_FLOW;
3690                 if (flowctrl & FLOW_CTRL_RX)
3691                         val |= MACCFG1_RX_FLOW;
3692         }
3693
3694         return val;
3695 }
3696
3697 static noinline void gfar_update_link_state(struct gfar_private *priv)
3698 {
3699         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3700         struct net_device *ndev = priv->ndev;
3701         struct phy_device *phydev = ndev->phydev;
3702         struct gfar_priv_rx_q *rx_queue = NULL;
3703         int i;
3704
3705         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3706                 return;
3707
3708         if (phydev->link) {
3709                 u32 tempval1 = gfar_read(&regs->maccfg1);
3710                 u32 tempval = gfar_read(&regs->maccfg2);
3711                 u32 ecntrl = gfar_read(&regs->ecntrl);
3712                 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
3713
3714                 if (phydev->duplex != priv->oldduplex) {
3715                         if (!(phydev->duplex))
3716                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3717                         else
3718                                 tempval |= MACCFG2_FULL_DUPLEX;
3719
3720                         priv->oldduplex = phydev->duplex;
3721                 }
3722
3723                 if (phydev->speed != priv->oldspeed) {
3724                         switch (phydev->speed) {
3725                         case 1000:
3726                                 tempval =
3727                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3728
3729                                 ecntrl &= ~(ECNTRL_R100);
3730                                 break;
3731                         case 100:
3732                         case 10:
3733                                 tempval =
3734                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3735
3736                                 /* Reduced mode distinguishes
3737                                  * between 10 and 100
3738                                  */
3739                                 if (phydev->speed == SPEED_100)
3740                                         ecntrl |= ECNTRL_R100;
3741                                 else
3742                                         ecntrl &= ~(ECNTRL_R100);
3743                                 break;
3744                         default:
3745                                 netif_warn(priv, link, priv->ndev,
3746                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3747                                            phydev->speed);
3748                                 break;
3749                         }
3750
3751                         priv->oldspeed = phydev->speed;
3752                 }
3753
3754                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3755                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3756
3757                 /* Turn last free buffer recording on */
3758                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3759                         for (i = 0; i < priv->num_rx_queues; i++) {
3760                                 u32 bdp_dma;
3761
3762                                 rx_queue = priv->rx_queue[i];
3763                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3764                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3765                         }
3766
3767                         priv->tx_actual_en = 1;
3768                 }
3769
3770                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3771                         priv->tx_actual_en = 0;
3772
3773                 gfar_write(&regs->maccfg1, tempval1);
3774                 gfar_write(&regs->maccfg2, tempval);
3775                 gfar_write(&regs->ecntrl, ecntrl);
3776
3777                 if (!priv->oldlink)
3778                         priv->oldlink = 1;
3779
3780         } else if (priv->oldlink) {
3781                 priv->oldlink = 0;
3782                 priv->oldspeed = 0;
3783                 priv->oldduplex = -1;
3784         }
3785
3786         if (netif_msg_link(priv))
3787                 phy_print_status(phydev);
3788 }
3789
3790 static const struct of_device_id gfar_match[] =
3791 {
3792         {
3793                 .type = "network",
3794                 .compatible = "gianfar",
3795         },
3796         {
3797                 .compatible = "fsl,etsec2",
3798         },
3799         {},
3800 };
3801 MODULE_DEVICE_TABLE(of, gfar_match);
3802
3803 /* Structure for a device driver */
3804 static struct platform_driver gfar_driver = {
3805         .driver = {
3806                 .name = "fsl-gianfar",
3807                 .pm = GFAR_PM_OPS,
3808                 .of_match_table = gfar_match,
3809         },
3810         .probe = gfar_probe,
3811         .remove = gfar_remove,
3812 };
3813
3814 module_platform_driver(gfar_driver);