drivers/net/ethernet/freescale/ucc_geth.c

   1 /*
   2  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *         Li Yang <leoli@freescale.com>
   6  *
   7  * Description:
   8  * QE UCC Gigabit Ethernet Driver
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/slab.h>
  22 #include <linux/stddef.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/mm.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/mii.h>
  32 #include <linux/phy.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/of_address.h>
  35 #include <linux/of_irq.h>
  36 #include <linux/of_mdio.h>
  37 #include <linux/of_net.h>
  38 #include <linux/of_platform.h>
  39
  40 #include <asm/uaccess.h>
  41 #include <asm/irq.h>
  42 #include <asm/io.h>
  43 #include <soc/fsl/qe/immap_qe.h>
  44 #include <soc/fsl/qe/qe.h>
  45 #include <soc/fsl/qe/ucc.h>
  46 #include <soc/fsl/qe/ucc_fast.h>
  47 #include <asm/machdep.h>
  48 #include <net/sch_generic.h>
  49
  50 #include "ucc_geth.h"
  51
  52 #undef DEBUG
  53
  54 #define ugeth_printk(level, format, arg...)  \
  55         printk(level format "\n", ## arg)
  56
  57 #define ugeth_dbg(format, arg...)            \
  58         ugeth_printk(KERN_DEBUG , format , ## arg)
  59
  60 #ifdef UGETH_VERBOSE_DEBUG
  61 #define ugeth_vdbg ugeth_dbg
  62 #else
  63 #define ugeth_vdbg(fmt, args...) do { } while (0)
  64 #endif                          /* UGETH_VERBOSE_DEBUG */
  65 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
  66
  67
  68 static DEFINE_SPINLOCK(ugeth_lock);
  69
  70 static struct {
  71         u32 msg_enable;
  72 } debug = { -1 };
  73
  74 module_param_named(debug, debug.msg_enable, int, 0);
  75 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
  76
  77 static struct ucc_geth_info ugeth_primary_info = {
  78         .uf_info = {
  79                     .bd_mem_part = MEM_PART_SYSTEM,
  80                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
  81                     .max_rx_buf_length = 1536,
  82                     /* adjusted at startup if max-speed 1000 */
  83                     .urfs = UCC_GETH_URFS_INIT,
  84                     .urfet = UCC_GETH_URFET_INIT,
  85                     .urfset = UCC_GETH_URFSET_INIT,
  86                     .utfs = UCC_GETH_UTFS_INIT,
  87                     .utfet = UCC_GETH_UTFET_INIT,
  88                     .utftt = UCC_GETH_UTFTT_INIT,
  89                     .ufpt = 256,
  90                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
  91                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  92                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
  93                     .renc = UCC_FAST_RX_ENCODING_NRZ,
  94                     .tcrc = UCC_FAST_16_BIT_CRC,
  95                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  96                     },
  97         .numQueuesTx = 1,
  98         .numQueuesRx = 1,
  99         .extendedFilteringChainPointer = ((uint32_t) NULL),
 100         .typeorlen = 3072 /*1536 */ ,
 101         .nonBackToBackIfgPart1 = 0x40,
 102         .nonBackToBackIfgPart2 = 0x60,
 103         .miminumInterFrameGapEnforcement = 0x50,
 104         .backToBackInterFrameGap = 0x60,
 105         .mblinterval = 128,
 106         .nortsrbytetime = 5,
 107         .fracsiz = 1,
 108         .strictpriorityq = 0xff,
 109         .altBebTruncation = 0xa,
 110         .excessDefer = 1,
 111         .maxRetransmission = 0xf,
 112         .collisionWindow = 0x37,
 113         .receiveFlowControl = 1,
 114         .transmitFlowControl = 1,
 115         .maxGroupAddrInHash = 4,
 116         .maxIndAddrInHash = 4,
 117         .prel = 7,
 118         .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
 119         .minFrameLength = 64,
 120         .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
 121         .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
 122         .vlantype = 0x8100,
 123         .ecamptr = ((uint32_t) NULL),
 124         .eventRegMask = UCCE_OTHER,
 125         .pausePeriod = 0xf000,
 126         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
 127         .bdRingLenTx = {
 128                         TX_BD_RING_LEN,
 129                         TX_BD_RING_LEN,
 130                         TX_BD_RING_LEN,
 131                         TX_BD_RING_LEN,
 132                         TX_BD_RING_LEN,
 133                         TX_BD_RING_LEN,
 134                         TX_BD_RING_LEN,
 135                         TX_BD_RING_LEN},
 136
 137         .bdRingLenRx = {
 138                         RX_BD_RING_LEN,
 139                         RX_BD_RING_LEN,
 140                         RX_BD_RING_LEN,
 141                         RX_BD_RING_LEN,
 142                         RX_BD_RING_LEN,
 143                         RX_BD_RING_LEN,
 144                         RX_BD_RING_LEN,
 145                         RX_BD_RING_LEN},
 146
 147         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
 148         .largestexternallookupkeysize =
 149             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
 150         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
 151                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
 152                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
 153         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
 154         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
 155         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
 156         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
 157         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
 158         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
 159         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
 160         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 161         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 162 };
 163
 164 static struct ucc_geth_info ugeth_info[8];
 165
 166 #ifdef DEBUG
 167 static void mem_disp(u8 *addr, int size)
 168 {
 169         u8 *i;
 170         int size16Aling = (size >> 4) << 4;
 171         int size4Aling = (size >> 2) << 2;
 172         int notAlign = 0;
 173         if (size % 16)
 174                 notAlign = 1;
 175
 176         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
 177                 printk("0x%08x: %08x %08x %08x %08x\r\n",
 178                        (u32) i,
 179                        *((u32 *) (i)),
 180                        *((u32 *) (i + 4)),
 181                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
 182         if (notAlign == 1)
 183                 printk("0x%08x: ", (u32) i);
 184         for (; (u32) i < (u32) addr + size4Aling; i += 4)
 185                 printk("%08x ", *((u32 *) (i)));
 186         for (; (u32) i < (u32) addr + size; i++)
 187                 printk("%02x", *((i)));
 188         if (notAlign == 1)
 189                 printk("\r\n");
 190 }
 191 #endif /* DEBUG */
 192
 193 static struct list_head *dequeue(struct list_head *lh)
 194 {
 195         unsigned long flags;
 196
 197         spin_lock_irqsave(&ugeth_lock, flags);
 198         if (!list_empty(lh)) {
 199                 struct list_head *node = lh->next;
 200                 list_del(node);
 201                 spin_unlock_irqrestore(&ugeth_lock, flags);
 202                 return node;
 203         } else {
 204                 spin_unlock_irqrestore(&ugeth_lock, flags);
 205                 return NULL;
 206         }
 207 }
 208
 209 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
 210                 u8 __iomem *bd)
 211 {
 212         struct sk_buff *skb;
 213
 214         skb = netdev_alloc_skb(ugeth->ndev,
 215                                ugeth->ug_info->uf_info.max_rx_buf_length +
 216                                UCC_GETH_RX_DATA_BUF_ALIGNMENT);
 217         if (!skb)
 218                 return NULL;
 219
 220         /* We need the data buffer to be aligned properly.  We will reserve
 221          * as many bytes as needed to align the data properly
 222          */
 223         skb_reserve(skb,
 224                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 225                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 226                                               1)));
 227
 228         out_be32(&((struct qe_bd __iomem *)bd)->buf,
 229                       dma_map_single(ugeth->dev,
 230                                      skb->data,
 231                                      ugeth->ug_info->uf_info.max_rx_buf_length +
 232                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
 233                                      DMA_FROM_DEVICE));
 234
 235         out_be32((u32 __iomem *)bd,
 236                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
 237
 238         return skb;
 239 }
 240
 241 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
 242 {
 243         u8 __iomem *bd;
 244         u32 bd_status;
 245         struct sk_buff *skb;
 246         int i;
 247
 248         bd = ugeth->p_rx_bd_ring[rxQ];
 249         i = 0;
 250
 251         do {
 252                 bd_status = in_be32((u32 __iomem *)bd);
 253                 skb = get_new_skb(ugeth, bd);
 254
 255                 if (!skb)       /* If can not allocate data buffer,
 256                                 abort. Cleanup will be elsewhere */
 257                         return -ENOMEM;
 258
 259                 ugeth->rx_skbuff[rxQ][i] = skb;
 260
 261                 /* advance the BD pointer */
 262                 bd += sizeof(struct qe_bd);
 263                 i++;
 264         } while (!(bd_status & R_W));
 265
 266         return 0;
 267 }
 268
 269 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
 270                                   u32 *p_start,
 271                                   u8 num_entries,
 272                                   u32 thread_size,
 273                                   u32 thread_alignment,
 274                                   unsigned int risc,
 275                                   int skip_page_for_first_entry)
 276 {
 277         u32 init_enet_offset;
 278         u8 i;
 279         int snum;
 280
 281         for (i = 0; i < num_entries; i++) {
 282                 if ((snum = qe_get_snum()) < 0) {
 283                         if (netif_msg_ifup(ugeth))
 284                                 pr_err("Can not get SNUM\n");
 285                         return snum;
 286                 }
 287                 if ((i == 0) && skip_page_for_first_entry)
 288                 /* First entry of Rx does not have page */
 289                         init_enet_offset = 0;
 290                 else {
 291                         init_enet_offset =
 292                             qe_muram_alloc(thread_size, thread_alignment);
 293                         if (IS_ERR_VALUE(init_enet_offset)) {
 294                                 if (netif_msg_ifup(ugeth))
 295                                         pr_err("Can not allocate DPRAM memory\n");
 296                                 qe_put_snum((u8) snum);
 297                                 return -ENOMEM;
 298                         }
 299                 }
 300                 *(p_start++) =
 301                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
 302                     | risc;
 303         }
 304
 305         return 0;
 306 }
 307
 308 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
 309                                     u32 *p_start,
 310                                     u8 num_entries,
 311                                     unsigned int risc,
 312                                     int skip_page_for_first_entry)
 313 {
 314         u32 init_enet_offset;
 315         u8 i;
 316         int snum;
 317
 318         for (i = 0; i < num_entries; i++) {
 319                 u32 val = *p_start;
 320
 321                 /* Check that this entry was actually valid --
 322                 needed in case failed in allocations */
 323                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 324                         snum =
 325                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 326                             ENET_INIT_PARAM_SNUM_SHIFT;
 327                         qe_put_snum((u8) snum);
 328                         if (!((i == 0) && skip_page_for_first_entry)) {
 329                         /* First entry of Rx does not have page */
 330                                 init_enet_offset =
 331                                     (val & ENET_INIT_PARAM_PTR_MASK);
 332                                 qe_muram_free(init_enet_offset);
 333                         }
 334                         *p_start++ = 0;
 335                 }
 336         }
 337
 338         return 0;
 339 }
 340
 341 #ifdef DEBUG
 342 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
 343                                   u32 __iomem *p_start,
 344                                   u8 num_entries,
 345                                   u32 thread_size,
 346                                   unsigned int risc,
 347                                   int skip_page_for_first_entry)
 348 {
 349         u32 init_enet_offset;
 350         u8 i;
 351         int snum;
 352
 353         for (i = 0; i < num_entries; i++) {
 354                 u32 val = in_be32(p_start);
 355
 356                 /* Check that this entry was actually valid --
 357                 needed in case failed in allocations */
 358                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 359                         snum =
 360                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 361                             ENET_INIT_PARAM_SNUM_SHIFT;
 362                         qe_put_snum((u8) snum);
 363                         if (!((i == 0) && skip_page_for_first_entry)) {
 364                         /* First entry of Rx does not have page */
 365                                 init_enet_offset =
 366                                     (in_be32(p_start) &
 367                                      ENET_INIT_PARAM_PTR_MASK);
 368                                 pr_info("Init enet entry %d:\n", i);
 369                                 pr_info("Base address: 0x%08x\n",
 370                                         (u32)qe_muram_addr(init_enet_offset));
 371                                 mem_disp(qe_muram_addr(init_enet_offset),
 372                                          thread_size);
 373                         }
 374                         p_start++;
 375                 }
 376         }
 377
 378         return 0;
 379 }
 380 #endif
 381
 382 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
 383 {
 384         kfree(enet_addr_cont);
 385 }
 386
 387 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
 388 {
 389         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
 390         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
 391         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
 392 }
 393
 394 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
 395 {
 396         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 397
 398         if (paddr_num >= NUM_OF_PADDRS) {
 399                 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
 400                 return -EINVAL;
 401         }
 402
 403         p_82xx_addr_filt =
 404             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 405             addressfiltering;
 406
 407         /* Writing address ff.ff.ff.ff.ff.ff disables address
 408         recognition for this register */
 409         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
 410         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
 411         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
 412
 413         return 0;
 414 }
 415
 416 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
 417                                 u8 *p_enet_addr)
 418 {
 419         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 420         u32 cecr_subblock;
 421
 422         p_82xx_addr_filt =
 423             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 424             addressfiltering;
 425
 426         cecr_subblock =
 427             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
 428
 429         /* Ethernet frames are defined in Little Endian mode,
 430         therefore to insert */
 431         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
 432
 433         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
 434
 435         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
 436                      QE_CR_PROTOCOL_ETHERNET, 0);
 437 }
 438
 439 #ifdef DEBUG
 440 static void get_statistics(struct ucc_geth_private *ugeth,
 441                            struct ucc_geth_tx_firmware_statistics *
 442                            tx_firmware_statistics,
 443                            struct ucc_geth_rx_firmware_statistics *
 444                            rx_firmware_statistics,
 445                            struct ucc_geth_hardware_statistics *hardware_statistics)
 446 {
 447         struct ucc_fast __iomem *uf_regs;
 448         struct ucc_geth __iomem *ug_regs;
 449         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
 450         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
 451
 452         ug_regs = ugeth->ug_regs;
 453         uf_regs = (struct ucc_fast __iomem *) ug_regs;
 454         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
 455         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
 456
 457         /* Tx firmware only if user handed pointer and driver actually
 458         gathers Tx firmware statistics */
 459         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
 460                 tx_firmware_statistics->sicoltx =
 461                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
 462                 tx_firmware_statistics->mulcoltx =
 463                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
 464                 tx_firmware_statistics->latecoltxfr =
 465                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
 466                 tx_firmware_statistics->frabortduecol =
 467                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
 468                 tx_firmware_statistics->frlostinmactxer =
 469                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
 470                 tx_firmware_statistics->carriersenseertx =
 471                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
 472                 tx_firmware_statistics->frtxok =
 473                     in_be32(&p_tx_fw_statistics_pram->frtxok);
 474                 tx_firmware_statistics->txfrexcessivedefer =
 475                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
 476                 tx_firmware_statistics->txpkts256 =
 477                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
 478                 tx_firmware_statistics->txpkts512 =
 479                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
 480                 tx_firmware_statistics->txpkts1024 =
 481                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
 482                 tx_firmware_statistics->txpktsjumbo =
 483                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
 484         }
 485
 486         /* Rx firmware only if user handed pointer and driver actually
 487          * gathers Rx firmware statistics */
 488         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
 489                 int i;
 490                 rx_firmware_statistics->frrxfcser =
 491                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
 492                 rx_firmware_statistics->fraligner =
 493                     in_be32(&p_rx_fw_statistics_pram->fraligner);
 494                 rx_firmware_statistics->inrangelenrxer =
 495                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
 496                 rx_firmware_statistics->outrangelenrxer =
 497                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
 498                 rx_firmware_statistics->frtoolong =
 499                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
 500                 rx_firmware_statistics->runt =
 501                     in_be32(&p_rx_fw_statistics_pram->runt);
 502                 rx_firmware_statistics->verylongevent =
 503                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
 504                 rx_firmware_statistics->symbolerror =
 505                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
 506                 rx_firmware_statistics->dropbsy =
 507                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
 508                 for (i = 0; i < 0x8; i++)
 509                         rx_firmware_statistics->res0[i] =
 510                             p_rx_fw_statistics_pram->res0[i];
 511                 rx_firmware_statistics->mismatchdrop =
 512                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
 513                 rx_firmware_statistics->underpkts =
 514                     in_be32(&p_rx_fw_statistics_pram->underpkts);
 515                 rx_firmware_statistics->pkts256 =
 516                     in_be32(&p_rx_fw_statistics_pram->pkts256);
 517                 rx_firmware_statistics->pkts512 =
 518                     in_be32(&p_rx_fw_statistics_pram->pkts512);
 519                 rx_firmware_statistics->pkts1024 =
 520                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
 521                 rx_firmware_statistics->pktsjumbo =
 522                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
 523                 rx_firmware_statistics->frlossinmacer =
 524                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
 525                 rx_firmware_statistics->pausefr =
 526                     in_be32(&p_rx_fw_statistics_pram->pausefr);
 527                 for (i = 0; i < 0x4; i++)
 528                         rx_firmware_statistics->res1[i] =
 529                             p_rx_fw_statistics_pram->res1[i];
 530                 rx_firmware_statistics->removevlan =
 531                     in_be32(&p_rx_fw_statistics_pram->removevlan);
 532                 rx_firmware_statistics->replacevlan =
 533                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
 534                 rx_firmware_statistics->insertvlan =
 535                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
 536         }
 537
 538         /* Hardware only if user handed pointer and driver actually
 539         gathers hardware statistics */
 540         if (hardware_statistics &&
 541             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
 542                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
 543                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
 544                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
 545                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
 546                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
 547                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
 548                 hardware_statistics->txok = in_be32(&ug_regs->txok);
 549                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
 550                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
 551                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
 552                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
 553                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
 554                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
 555                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
 556                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
 557         }
 558 }
 559
 560 static void dump_bds(struct ucc_geth_private *ugeth)
 561 {
 562         int i;
 563         int length;
 564
 565         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 566                 if (ugeth->p_tx_bd_ring[i]) {
 567                         length =
 568                             (ugeth->ug_info->bdRingLenTx[i] *
 569                              sizeof(struct qe_bd));
 570                         pr_info("TX BDs[%d]\n", i);
 571                         mem_disp(ugeth->p_tx_bd_ring[i], length);
 572                 }
 573         }
 574         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 575                 if (ugeth->p_rx_bd_ring[i]) {
 576                         length =
 577                             (ugeth->ug_info->bdRingLenRx[i] *
 578                              sizeof(struct qe_bd));
 579                         pr_info("RX BDs[%d]\n", i);
 580                         mem_disp(ugeth->p_rx_bd_ring[i], length);
 581                 }
 582         }
 583 }
 584
 585 static void dump_regs(struct ucc_geth_private *ugeth)
 586 {
 587         int i;
 588
 589         pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
 590         pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
 591
 592         pr_info("maccfg1    : addr - 0x%08x, val - 0x%08x\n",
 593                 (u32)&ugeth->ug_regs->maccfg1,
 594                 in_be32(&ugeth->ug_regs->maccfg1));
 595         pr_info("maccfg2    : addr - 0x%08x, val - 0x%08x\n",
 596                 (u32)&ugeth->ug_regs->maccfg2,
 597                 in_be32(&ugeth->ug_regs->maccfg2));
 598         pr_info("ipgifg     : addr - 0x%08x, val - 0x%08x\n",
 599                 (u32)&ugeth->ug_regs->ipgifg,
 600                 in_be32(&ugeth->ug_regs->ipgifg));
 601         pr_info("hafdup     : addr - 0x%08x, val - 0x%08x\n",
 602                 (u32)&ugeth->ug_regs->hafdup,
 603                 in_be32(&ugeth->ug_regs->hafdup));
 604         pr_info("ifctl      : addr - 0x%08x, val - 0x%08x\n",
 605                 (u32)&ugeth->ug_regs->ifctl,
 606                 in_be32(&ugeth->ug_regs->ifctl));
 607         pr_info("ifstat     : addr - 0x%08x, val - 0x%08x\n",
 608                 (u32)&ugeth->ug_regs->ifstat,
 609                 in_be32(&ugeth->ug_regs->ifstat));
 610         pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
 611                 (u32)&ugeth->ug_regs->macstnaddr1,
 612                 in_be32(&ugeth->ug_regs->macstnaddr1));
 613         pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
 614                 (u32)&ugeth->ug_regs->macstnaddr2,
 615                 in_be32(&ugeth->ug_regs->macstnaddr2));
 616         pr_info("uempr      : addr - 0x%08x, val - 0x%08x\n",
 617                 (u32)&ugeth->ug_regs->uempr,
 618                 in_be32(&ugeth->ug_regs->uempr));
 619         pr_info("utbipar    : addr - 0x%08x, val - 0x%08x\n",
 620                 (u32)&ugeth->ug_regs->utbipar,
 621                 in_be32(&ugeth->ug_regs->utbipar));
 622         pr_info("uescr      : addr - 0x%08x, val - 0x%04x\n",
 623                 (u32)&ugeth->ug_regs->uescr,
 624                 in_be16(&ugeth->ug_regs->uescr));
 625         pr_info("tx64       : addr - 0x%08x, val - 0x%08x\n",
 626                 (u32)&ugeth->ug_regs->tx64,
 627                 in_be32(&ugeth->ug_regs->tx64));
 628         pr_info("tx127      : addr - 0x%08x, val - 0x%08x\n",
 629                 (u32)&ugeth->ug_regs->tx127,
 630                 in_be32(&ugeth->ug_regs->tx127));
 631         pr_info("tx255      : addr - 0x%08x, val - 0x%08x\n",
 632                 (u32)&ugeth->ug_regs->tx255,
 633                 in_be32(&ugeth->ug_regs->tx255));
 634         pr_info("rx64       : addr - 0x%08x, val - 0x%08x\n",
 635                 (u32)&ugeth->ug_regs->rx64,
 636                 in_be32(&ugeth->ug_regs->rx64));
 637         pr_info("rx127      : addr - 0x%08x, val - 0x%08x\n",
 638                 (u32)&ugeth->ug_regs->rx127,
 639                 in_be32(&ugeth->ug_regs->rx127));
 640         pr_info("rx255      : addr - 0x%08x, val - 0x%08x\n",
 641                 (u32)&ugeth->ug_regs->rx255,
 642                 in_be32(&ugeth->ug_regs->rx255));
 643         pr_info("txok       : addr - 0x%08x, val - 0x%08x\n",
 644                 (u32)&ugeth->ug_regs->txok,
 645                 in_be32(&ugeth->ug_regs->txok));
 646         pr_info("txcf       : addr - 0x%08x, val - 0x%04x\n",
 647                 (u32)&ugeth->ug_regs->txcf,
 648                 in_be16(&ugeth->ug_regs->txcf));
 649         pr_info("tmca       : addr - 0x%08x, val - 0x%08x\n",
 650                 (u32)&ugeth->ug_regs->tmca,
 651                 in_be32(&ugeth->ug_regs->tmca));
 652         pr_info("tbca       : addr - 0x%08x, val - 0x%08x\n",
 653                 (u32)&ugeth->ug_regs->tbca,
 654                 in_be32(&ugeth->ug_regs->tbca));
 655         pr_info("rxfok      : addr - 0x%08x, val - 0x%08x\n",
 656                 (u32)&ugeth->ug_regs->rxfok,
 657                 in_be32(&ugeth->ug_regs->rxfok));
 658         pr_info("rxbok      : addr - 0x%08x, val - 0x%08x\n",
 659                 (u32)&ugeth->ug_regs->rxbok,
 660                 in_be32(&ugeth->ug_regs->rxbok));
 661         pr_info("rbyt       : addr - 0x%08x, val - 0x%08x\n",
 662                 (u32)&ugeth->ug_regs->rbyt,
 663                 in_be32(&ugeth->ug_regs->rbyt));
 664         pr_info("rmca       : addr - 0x%08x, val - 0x%08x\n",
 665                 (u32)&ugeth->ug_regs->rmca,
 666                 in_be32(&ugeth->ug_regs->rmca));
 667         pr_info("rbca       : addr - 0x%08x, val - 0x%08x\n",
 668                 (u32)&ugeth->ug_regs->rbca,
 669                 in_be32(&ugeth->ug_regs->rbca));
 670         pr_info("scar       : addr - 0x%08x, val - 0x%08x\n",
 671                 (u32)&ugeth->ug_regs->scar,
 672                 in_be32(&ugeth->ug_regs->scar));
 673         pr_info("scam       : addr - 0x%08x, val - 0x%08x\n",
 674                 (u32)&ugeth->ug_regs->scam,
 675                 in_be32(&ugeth->ug_regs->scam));
 676
 677         if (ugeth->p_thread_data_tx) {
 678                 int numThreadsTxNumerical;
 679                 switch (ugeth->ug_info->numThreadsTx) {
 680                 case UCC_GETH_NUM_OF_THREADS_1:
 681                         numThreadsTxNumerical = 1;
 682                         break;
 683                 case UCC_GETH_NUM_OF_THREADS_2:
 684                         numThreadsTxNumerical = 2;
 685                         break;
 686                 case UCC_GETH_NUM_OF_THREADS_4:
 687                         numThreadsTxNumerical = 4;
 688                         break;
 689                 case UCC_GETH_NUM_OF_THREADS_6:
 690                         numThreadsTxNumerical = 6;
 691                         break;
 692                 case UCC_GETH_NUM_OF_THREADS_8:
 693                         numThreadsTxNumerical = 8;
 694                         break;
 695                 default:
 696                         numThreadsTxNumerical = 0;
 697                         break;
 698                 }
 699
 700                 pr_info("Thread data TXs:\n");
 701                 pr_info("Base address: 0x%08x\n",
 702                         (u32)ugeth->p_thread_data_tx);
 703                 for (i = 0; i < numThreadsTxNumerical; i++) {
 704                         pr_info("Thread data TX[%d]:\n", i);
 705                         pr_info("Base address: 0x%08x\n",
 706                                 (u32)&ugeth->p_thread_data_tx[i]);
 707                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
 708                                  sizeof(struct ucc_geth_thread_data_tx));
 709                 }
 710         }
 711         if (ugeth->p_thread_data_rx) {
 712                 int numThreadsRxNumerical;
 713                 switch (ugeth->ug_info->numThreadsRx) {
 714                 case UCC_GETH_NUM_OF_THREADS_1:
 715                         numThreadsRxNumerical = 1;
 716                         break;
 717                 case UCC_GETH_NUM_OF_THREADS_2:
 718                         numThreadsRxNumerical = 2;
 719                         break;
 720                 case UCC_GETH_NUM_OF_THREADS_4:
 721                         numThreadsRxNumerical = 4;
 722                         break;
 723                 case UCC_GETH_NUM_OF_THREADS_6:
 724                         numThreadsRxNumerical = 6;
 725                         break;
 726                 case UCC_GETH_NUM_OF_THREADS_8:
 727                         numThreadsRxNumerical = 8;
 728                         break;
 729                 default:
 730                         numThreadsRxNumerical = 0;
 731                         break;
 732                 }
 733
 734                 pr_info("Thread data RX:\n");
 735                 pr_info("Base address: 0x%08x\n",
 736                         (u32)ugeth->p_thread_data_rx);
 737                 for (i = 0; i < numThreadsRxNumerical; i++) {
 738                         pr_info("Thread data RX[%d]:\n", i);
 739                         pr_info("Base address: 0x%08x\n",
 740                                 (u32)&ugeth->p_thread_data_rx[i]);
 741                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
 742                                  sizeof(struct ucc_geth_thread_data_rx));
 743                 }
 744         }
 745         if (ugeth->p_exf_glbl_param) {
 746                 pr_info("EXF global param:\n");
 747                 pr_info("Base address: 0x%08x\n",
 748                         (u32)ugeth->p_exf_glbl_param);
 749                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
 750                          sizeof(*ugeth->p_exf_glbl_param));
 751         }
 752         if (ugeth->p_tx_glbl_pram) {
 753                 pr_info("TX global param:\n");
 754                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
 755                 pr_info("temoder      : addr - 0x%08x, val - 0x%04x\n",
 756                         (u32)&ugeth->p_tx_glbl_pram->temoder,
 757                         in_be16(&ugeth->p_tx_glbl_pram->temoder));
 758                pr_info("sqptr        : addr - 0x%08x, val - 0x%08x\n",
 759                         (u32)&ugeth->p_tx_glbl_pram->sqptr,
 760                         in_be32(&ugeth->p_tx_glbl_pram->sqptr));
 761                 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
 762                         (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
 763                         in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
 764                 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
 765                         (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
 766                         in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
 767                 pr_info("tstate       : addr - 0x%08x, val - 0x%08x\n",
 768                         (u32)&ugeth->p_tx_glbl_pram->tstate,
 769                         in_be32(&ugeth->p_tx_glbl_pram->tstate));
 770                 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
 771                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
 772                         ugeth->p_tx_glbl_pram->iphoffset[0]);
 773                 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
 774                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
 775                         ugeth->p_tx_glbl_pram->iphoffset[1]);
 776                 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
 777                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
 778                         ugeth->p_tx_glbl_pram->iphoffset[2]);
 779                 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
 780                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
 781                         ugeth->p_tx_glbl_pram->iphoffset[3]);
 782                 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
 783                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
 784                         ugeth->p_tx_glbl_pram->iphoffset[4]);
 785                 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
 786                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
 787                         ugeth->p_tx_glbl_pram->iphoffset[5]);
 788                 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
 789                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
 790                         ugeth->p_tx_glbl_pram->iphoffset[6]);
 791                 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
 792                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
 793                         ugeth->p_tx_glbl_pram->iphoffset[7]);
 794                 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
 795                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
 796                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
 797                 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
 798                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
 799                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
 800                 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
 801                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
 802                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
 803                 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
 804                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
 805                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
 806                 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
 807                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
 808                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
 809                 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
 810                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
 811                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
 812                 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
 813                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
 814                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
 815                 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
 816                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
 817                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
 818                 pr_info("tqptr        : addr - 0x%08x, val - 0x%08x\n",
 819                         (u32)&ugeth->p_tx_glbl_pram->tqptr,
 820                         in_be32(&ugeth->p_tx_glbl_pram->tqptr));
 821         }
 822         if (ugeth->p_rx_glbl_pram) {
 823                 pr_info("RX global param:\n");
 824                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
 825                 pr_info("remoder         : addr - 0x%08x, val - 0x%08x\n",
 826                         (u32)&ugeth->p_rx_glbl_pram->remoder,
 827                         in_be32(&ugeth->p_rx_glbl_pram->remoder));
 828                 pr_info("rqptr           : addr - 0x%08x, val - 0x%08x\n",
 829                         (u32)&ugeth->p_rx_glbl_pram->rqptr,
 830                         in_be32(&ugeth->p_rx_glbl_pram->rqptr));
 831                 pr_info("typeorlen       : addr - 0x%08x, val - 0x%04x\n",
 832                         (u32)&ugeth->p_rx_glbl_pram->typeorlen,
 833                         in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
 834                 pr_info("rxgstpack       : addr - 0x%08x, val - 0x%02x\n",
 835                         (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
 836                         ugeth->p_rx_glbl_pram->rxgstpack);
 837                 pr_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x\n",
 838                         (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
 839                         in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
 840                 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
 841                         (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
 842                         in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
 843                 pr_info("rstate          : addr - 0x%08x, val - 0x%02x\n",
 844                         (u32)&ugeth->p_rx_glbl_pram->rstate,
 845                         ugeth->p_rx_glbl_pram->rstate);
 846                 pr_info("mrblr           : addr - 0x%08x, val - 0x%04x\n",
 847                         (u32)&ugeth->p_rx_glbl_pram->mrblr,
 848                         in_be16(&ugeth->p_rx_glbl_pram->mrblr));
 849                 pr_info("rbdqptr         : addr - 0x%08x, val - 0x%08x\n",
 850                         (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
 851                         in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
 852                 pr_info("mflr            : addr - 0x%08x, val - 0x%04x\n",
 853                         (u32)&ugeth->p_rx_glbl_pram->mflr,
 854                         in_be16(&ugeth->p_rx_glbl_pram->mflr));
 855                 pr_info("minflr          : addr - 0x%08x, val - 0x%04x\n",
 856                         (u32)&ugeth->p_rx_glbl_pram->minflr,
 857                         in_be16(&ugeth->p_rx_glbl_pram->minflr));
 858                 pr_info("maxd1           : addr - 0x%08x, val - 0x%04x\n",
 859                         (u32)&ugeth->p_rx_glbl_pram->maxd1,
 860                         in_be16(&ugeth->p_rx_glbl_pram->maxd1));
 861                 pr_info("maxd2           : addr - 0x%08x, val - 0x%04x\n",
 862                         (u32)&ugeth->p_rx_glbl_pram->maxd2,
 863                         in_be16(&ugeth->p_rx_glbl_pram->maxd2));
 864                 pr_info("ecamptr         : addr - 0x%08x, val - 0x%08x\n",
 865                         (u32)&ugeth->p_rx_glbl_pram->ecamptr,
 866                         in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
 867                 pr_info("l2qt            : addr - 0x%08x, val - 0x%08x\n",
 868                         (u32)&ugeth->p_rx_glbl_pram->l2qt,
 869                         in_be32(&ugeth->p_rx_glbl_pram->l2qt));
 870                 pr_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x\n",
 871                         (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
 872                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
 873                 pr_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x\n",
 874                         (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
 875                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
 876                 pr_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x\n",
 877                         (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
 878                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
 879                 pr_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x\n",
 880                         (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
 881                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
 882                 pr_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x\n",
 883                         (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
 884                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
 885                 pr_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x\n",
 886                         (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
 887                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
 888                 pr_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x\n",
 889                         (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
 890                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
 891                 pr_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x\n",
 892                         (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
 893                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
 894                 pr_info("vlantype        : addr - 0x%08x, val - 0x%04x\n",
 895                         (u32)&ugeth->p_rx_glbl_pram->vlantype,
 896                         in_be16(&ugeth->p_rx_glbl_pram->vlantype));
 897                 pr_info("vlantci         : addr - 0x%08x, val - 0x%04x\n",
 898                         (u32)&ugeth->p_rx_glbl_pram->vlantci,
 899                         in_be16(&ugeth->p_rx_glbl_pram->vlantci));
 900                 for (i = 0; i < 64; i++)
 901                         pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
 902                                 i,
 903                                 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
 904                                 ugeth->p_rx_glbl_pram->addressfiltering[i]);
 905                 pr_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x\n",
 906                         (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
 907                         in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
 908         }
 909         if (ugeth->p_send_q_mem_reg) {
 910                 pr_info("Send Q memory registers:\n");
 911                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
 912                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 913                         pr_info("SQQD[%d]:\n", i);
 914                         pr_info("Base address: 0x%08x\n",
 915                                 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
 916                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
 917                                  sizeof(struct ucc_geth_send_queue_qd));
 918                 }
 919         }
 920         if (ugeth->p_scheduler) {
 921                 pr_info("Scheduler:\n");
 922                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
 923                 mem_disp((u8 *) ugeth->p_scheduler,
 924                          sizeof(*ugeth->p_scheduler));
 925         }
 926         if (ugeth->p_tx_fw_statistics_pram) {
 927                 pr_info("TX FW statistics pram:\n");
 928                 pr_info("Base address: 0x%08x\n",
 929                         (u32)ugeth->p_tx_fw_statistics_pram);
 930                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
 931                          sizeof(*ugeth->p_tx_fw_statistics_pram));
 932         }
 933         if (ugeth->p_rx_fw_statistics_pram) {
 934                 pr_info("RX FW statistics pram:\n");
 935                 pr_info("Base address: 0x%08x\n",
 936                         (u32)ugeth->p_rx_fw_statistics_pram);
 937                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
 938                          sizeof(*ugeth->p_rx_fw_statistics_pram));
 939         }
 940         if (ugeth->p_rx_irq_coalescing_tbl) {
 941                 pr_info("RX IRQ coalescing tables:\n");
 942                 pr_info("Base address: 0x%08x\n",
 943                         (u32)ugeth->p_rx_irq_coalescing_tbl);
 944                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 945                         pr_info("RX IRQ coalescing table entry[%d]:\n", i);
 946                         pr_info("Base address: 0x%08x\n",
 947                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 948                                 coalescingentry[i]);
 949                         pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
 950                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 951                                 coalescingentry[i].interruptcoalescingmaxvalue,
 952                                 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 953                                         coalescingentry[i].
 954                                         interruptcoalescingmaxvalue));
 955                         pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
 956                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 957                                 coalescingentry[i].interruptcoalescingcounter,
 958                                 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 959                                         coalescingentry[i].
 960                                         interruptcoalescingcounter));
 961                 }
 962         }
 963         if (ugeth->p_rx_bd_qs_tbl) {
 964                 pr_info("RX BD QS tables:\n");
 965                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
 966                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 967                         pr_info("RX BD QS table[%d]:\n", i);
 968                         pr_info("Base address: 0x%08x\n",
 969                                 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
 970                         pr_info("bdbaseptr        : addr - 0x%08x, val - 0x%08x\n",
 971                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
 972                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
 973                         pr_info("bdptr            : addr - 0x%08x, val - 0x%08x\n",
 974                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
 975                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
 976                         pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
 977                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
 978                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
 979                                         externalbdbaseptr));
 980                         pr_info("externalbdptr    : addr - 0x%08x, val - 0x%08x\n",
 981                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
 982                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
 983                         pr_info("ucode RX Prefetched BDs:\n");
 984                         pr_info("Base address: 0x%08x\n",
 985                                 (u32)qe_muram_addr(in_be32
 986                                                    (&ugeth->p_rx_bd_qs_tbl[i].
 987                                                     bdbaseptr)));
 988                         mem_disp((u8 *)
 989                                  qe_muram_addr(in_be32
 990                                                (&ugeth->p_rx_bd_qs_tbl[i].
 991                                                 bdbaseptr)),
 992                                  sizeof(struct ucc_geth_rx_prefetched_bds));
 993                 }
 994         }
 995         if (ugeth->p_init_enet_param_shadow) {
 996                 int size;
 997                 pr_info("Init enet param shadow:\n");
 998                 pr_info("Base address: 0x%08x\n",
 999                         (u32) ugeth->p_init_enet_param_shadow);
1000                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1001                          sizeof(*ugeth->p_init_enet_param_shadow));
1002
1003                 size = sizeof(struct ucc_geth_thread_rx_pram);
1004                 if (ugeth->ug_info->rxExtendedFiltering) {
1005                         size +=
1006                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1007                         if (ugeth->ug_info->largestexternallookupkeysize ==
1008                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1009                                 size +=
1010                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1011                         if (ugeth->ug_info->largestexternallookupkeysize ==
1012                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1013                                 size +=
1014                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1015                 }
1016
1017                 dump_init_enet_entries(ugeth,
1018                                        &(ugeth->p_init_enet_param_shadow->
1019                                          txthread[0]),
1020                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1021                                        sizeof(struct ucc_geth_thread_tx_pram),
1022                                        ugeth->ug_info->riscTx, 0);
1023                 dump_init_enet_entries(ugeth,
1024                                        &(ugeth->p_init_enet_param_shadow->
1025                                          rxthread[0]),
1026                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1027                                        ugeth->ug_info->riscRx, 1);
1028         }
1029 }
1030 #endif /* DEBUG */
1031
1032 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1033                                   u32 __iomem *maccfg1_register,
1034                                   u32 __iomem *maccfg2_register)
1035 {
1036         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1037         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1038         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1039 }
1040
1041 static int init_half_duplex_params(int alt_beb,
1042                                    int back_pressure_no_backoff,
1043                                    int no_backoff,
1044                                    int excess_defer,
1045                                    u8 alt_beb_truncation,
1046                                    u8 max_retransmissions,
1047                                    u8 collision_window,
1048                                    u32 __iomem *hafdup_register)
1049 {
1050         u32 value = 0;
1051
1052         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1053             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1054             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1055                 return -EINVAL;
1056
1057         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1058
1059         if (alt_beb)
1060                 value |= HALFDUP_ALT_BEB;
1061         if (back_pressure_no_backoff)
1062                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1063         if (no_backoff)
1064                 value |= HALFDUP_NO_BACKOFF;
1065         if (excess_defer)
1066                 value |= HALFDUP_EXCESSIVE_DEFER;
1067
1068         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1069
1070         value |= collision_window;
1071
1072         out_be32(hafdup_register, value);
1073         return 0;
1074 }
1075
1076 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1077                                        u8 non_btb_ipg,
1078                                        u8 min_ifg,
1079                                        u8 btb_ipg,
1080                                        u32 __iomem *ipgifg_register)
1081 {
1082         u32 value = 0;
1083
1084         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1085         IPG part 2 */
1086         if (non_btb_cs_ipg > non_btb_ipg)
1087                 return -EINVAL;
1088
1089         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1090             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1091             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1092             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1093                 return -EINVAL;
1094
1095         value |=
1096             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1097              IPGIFG_NBTB_CS_IPG_MASK);
1098         value |=
1099             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1100              IPGIFG_NBTB_IPG_MASK);
1101         value |=
1102             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1103              IPGIFG_MIN_IFG_MASK);
1104         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1105
1106         out_be32(ipgifg_register, value);
1107         return 0;
1108 }
1109
1110 int init_flow_control_params(u32 automatic_flow_control_mode,
1111                                     int rx_flow_control_enable,
1112                                     int tx_flow_control_enable,
1113                                     u16 pause_period,
1114                                     u16 extension_field,
1115                                     u32 __iomem *upsmr_register,
1116                                     u32 __iomem *uempr_register,
1117                                     u32 __iomem *maccfg1_register)
1118 {
1119         u32 value = 0;
1120
1121         /* Set UEMPR register */
1122         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1123         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1124         out_be32(uempr_register, value);
1125
1126         /* Set UPSMR register */
1127         setbits32(upsmr_register, automatic_flow_control_mode);
1128
1129         value = in_be32(maccfg1_register);
1130         if (rx_flow_control_enable)
1131                 value |= MACCFG1_FLOW_RX;
1132         if (tx_flow_control_enable)
1133                 value |= MACCFG1_FLOW_TX;
1134         out_be32(maccfg1_register, value);
1135
1136         return 0;
1137 }
1138
1139 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1140                                              int auto_zero_hardware_statistics,
1141                                              u32 __iomem *upsmr_register,
1142                                              u16 __iomem *uescr_register)
1143 {
1144         u16 uescr_value = 0;
1145
1146         /* Enable hardware statistics gathering if requested */
1147         if (enable_hardware_statistics)
1148                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1149
1150         /* Clear hardware statistics counters */
1151         uescr_value = in_be16(uescr_register);
1152         uescr_value |= UESCR_CLRCNT;
1153         /* Automatically zero hardware statistics counters on read,
1154         if requested */
1155         if (auto_zero_hardware_statistics)
1156                 uescr_value |= UESCR_AUTOZ;
1157         out_be16(uescr_register, uescr_value);
1158
1159         return 0;
1160 }
1161
1162 static int init_firmware_statistics_gathering_mode(int
1163                 enable_tx_firmware_statistics,
1164                 int enable_rx_firmware_statistics,
1165                 u32 __iomem *tx_rmon_base_ptr,
1166                 u32 tx_firmware_statistics_structure_address,
1167                 u32 __iomem *rx_rmon_base_ptr,
1168                 u32 rx_firmware_statistics_structure_address,
1169                 u16 __iomem *temoder_register,
1170                 u32 __iomem *remoder_register)
1171 {
1172         /* Note: this function does not check if */
1173         /* the parameters it receives are NULL   */
1174
1175         if (enable_tx_firmware_statistics) {
1176                 out_be32(tx_rmon_base_ptr,
1177                          tx_firmware_statistics_structure_address);
1178                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1179         }
1180
1181         if (enable_rx_firmware_statistics) {
1182                 out_be32(rx_rmon_base_ptr,
1183                          rx_firmware_statistics_structure_address);
1184                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int init_mac_station_addr_regs(u8 address_byte_0,
1191                                       u8 address_byte_1,
1192                                       u8 address_byte_2,
1193                                       u8 address_byte_3,
1194                                       u8 address_byte_4,
1195                                       u8 address_byte_5,
1196                                       u32 __iomem *macstnaddr1_register,
1197                                       u32 __iomem *macstnaddr2_register)
1198 {
1199         u32 value = 0;
1200
1201         /* Example: for a station address of 0x12345678ABCD, */
1202         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1203
1204         /* MACSTNADDR1 Register: */
1205
1206         /* 0                      7   8                      15  */
1207         /* station address byte 5     station address byte 4     */
1208         /* 16                     23  24                     31  */
1209         /* station address byte 3     station address byte 2     */
1210         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1211         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1212         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1213         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1214
1215         out_be32(macstnaddr1_register, value);
1216
1217         /* MACSTNADDR2 Register: */
1218
1219         /* 0                      7   8                      15  */
1220         /* station address byte 1     station address byte 0     */
1221         /* 16                     23  24                     31  */
1222         /*         reserved                   reserved           */
1223         value = 0;
1224         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1225         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1226
1227         out_be32(macstnaddr2_register, value);
1228
1229         return 0;
1230 }
1231
1232 static int init_check_frame_length_mode(int length_check,
1233                                         u32 __iomem *maccfg2_register)
1234 {
1235         u32 value = 0;
1236
1237         value = in_be32(maccfg2_register);
1238
1239         if (length_check)
1240                 value |= MACCFG2_LC;
1241         else
1242                 value &= ~MACCFG2_LC;
1243
1244         out_be32(maccfg2_register, value);
1245         return 0;
1246 }
1247
1248 static int init_preamble_length(u8 preamble_length,
1249                                 u32 __iomem *maccfg2_register)
1250 {
1251         if ((preamble_length < 3) || (preamble_length > 7))
1252                 return -EINVAL;
1253
1254         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1255                         preamble_length << MACCFG2_PREL_SHIFT);
1256
1257         return 0;
1258 }
1259
1260 static int init_rx_parameters(int reject_broadcast,
1261                               int receive_short_frames,
1262                               int promiscuous, u32 __iomem *upsmr_register)
1263 {
1264         u32 value = 0;
1265
1266         value = in_be32(upsmr_register);
1267
1268         if (reject_broadcast)
1269                 value |= UCC_GETH_UPSMR_BRO;
1270         else
1271                 value &= ~UCC_GETH_UPSMR_BRO;
1272
1273         if (receive_short_frames)
1274                 value |= UCC_GETH_UPSMR_RSH;
1275         else
1276                 value &= ~UCC_GETH_UPSMR_RSH;
1277
1278         if (promiscuous)
1279                 value |= UCC_GETH_UPSMR_PRO;
1280         else
1281                 value &= ~UCC_GETH_UPSMR_PRO;
1282
1283         out_be32(upsmr_register, value);
1284
1285         return 0;
1286 }
1287
1288 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1289                                 u16 __iomem *mrblr_register)
1290 {
1291         /* max_rx_buf_len value must be a multiple of 128 */
1292         if ((max_rx_buf_len == 0) ||
1293             (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1294                 return -EINVAL;
1295
1296         out_be16(mrblr_register, max_rx_buf_len);
1297         return 0;
1298 }
1299
1300 static int init_min_frame_len(u16 min_frame_length,
1301                               u16 __iomem *minflr_register,
1302                               u16 __iomem *mrblr_register)
1303 {
1304         u16 mrblr_value = 0;
1305
1306         mrblr_value = in_be16(mrblr_register);
1307         if (min_frame_length >= (mrblr_value - 4))
1308                 return -EINVAL;
1309
1310         out_be16(minflr_register, min_frame_length);
1311         return 0;
1312 }
1313
1314 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1315 {
1316         struct ucc_geth_info *ug_info;
1317         struct ucc_geth __iomem *ug_regs;
1318         struct ucc_fast __iomem *uf_regs;
1319         int ret_val;
1320         u32 upsmr, maccfg2;
1321         u16 value;
1322
1323         ugeth_vdbg("%s: IN", __func__);
1324
1325         ug_info = ugeth->ug_info;
1326         ug_regs = ugeth->ug_regs;
1327         uf_regs = ugeth->uccf->uf_regs;
1328
1329         /*                    Set MACCFG2                    */
1330         maccfg2 = in_be32(&ug_regs->maccfg2);
1331         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1332         if ((ugeth->max_speed == SPEED_10) ||
1333             (ugeth->max_speed == SPEED_100))
1334                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1335         else if (ugeth->max_speed == SPEED_1000)
1336                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1337         maccfg2 |= ug_info->padAndCrc;
1338         out_be32(&ug_regs->maccfg2, maccfg2);
1339
1340         /*                    Set UPSMR                      */
1341         upsmr = in_be32(&uf_regs->upsmr);
1342         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1343                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1344         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1345             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1346             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1347             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1348             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1349             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1350                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1351                         upsmr |= UCC_GETH_UPSMR_RPM;
1352                 switch (ugeth->max_speed) {
1353                 case SPEED_10:
1354                         upsmr |= UCC_GETH_UPSMR_R10M;
1355                         /* FALLTHROUGH */
1356                 case SPEED_100:
1357                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1358                                 upsmr |= UCC_GETH_UPSMR_RMM;
1359                 }
1360         }
1361         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1362             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1363                 upsmr |= UCC_GETH_UPSMR_TBIM;
1364         }
1365         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1366                 upsmr |= UCC_GETH_UPSMR_SGMM;
1367
1368         out_be32(&uf_regs->upsmr, upsmr);
1369
1370         /* Disable autonegotiation in tbi mode, because by default it
1371         comes up in autonegotiation mode. */
1372         /* Note that this depends on proper setting in utbipar register. */
1373         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1374             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1375                 struct ucc_geth_info *ug_info = ugeth->ug_info;
1376                 struct phy_device *tbiphy;
1377
1378                 if (!ug_info->tbi_node)
1379                         pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
1380
1381                 tbiphy = of_phy_find_device(ug_info->tbi_node);
1382                 if (!tbiphy)
1383                         pr_warn("Could not get TBI device\n");
1384
1385                 value = phy_read(tbiphy, ENET_TBI_MII_CR);
1386                 value &= ~0x1000;       /* Turn off autonegotiation */
1387                 phy_write(tbiphy, ENET_TBI_MII_CR, value);
1388
1389                 put_device(&tbiphy->mdio.dev);
1390         }
1391
1392         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1393
1394         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1395         if (ret_val != 0) {
1396                 if (netif_msg_probe(ugeth))
1397                         pr_err("Preamble length must be between 3 and 7 inclusive\n");
1398                 return ret_val;
1399         }
1400
1401         return 0;
1402 }
1403
1404 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1405 {
1406         struct ucc_fast_private *uccf;
1407         u32 cecr_subblock;
1408         u32 temp;
1409         int i = 10;
1410
1411         uccf = ugeth->uccf;
1412
1413         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1414         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1415         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1416
1417         /* Issue host command */
1418         cecr_subblock =
1419             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1420         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1421                      QE_CR_PROTOCOL_ETHERNET, 0);
1422
1423         /* Wait for command to complete */
1424         do {
1425                 msleep(10);
1426                 temp = in_be32(uccf->p_ucce);
1427         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1428
1429         uccf->stopped_tx = 1;
1430
1431         return 0;
1432 }
1433
1434 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1435 {
1436         struct ucc_fast_private *uccf;
1437         u32 cecr_subblock;
1438         u8 temp;
1439         int i = 10;
1440
1441         uccf = ugeth->uccf;
1442
1443         /* Clear acknowledge bit */
1444         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1445         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1446         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1447
1448         /* Keep issuing command and checking acknowledge bit until
1449         it is asserted, according to spec */
1450         do {
1451                 /* Issue host command */
1452                 cecr_subblock =
1453                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1454                                                 ucc_num);
1455                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1456                              QE_CR_PROTOCOL_ETHERNET, 0);
1457                 msleep(10);
1458                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1459         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1460
1461         uccf->stopped_rx = 1;
1462
1463         return 0;
1464 }
1465
1466 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1467 {
1468         struct ucc_fast_private *uccf;
1469         u32 cecr_subblock;
1470
1471         uccf = ugeth->uccf;
1472
1473         cecr_subblock =
1474             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1475         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1476         uccf->stopped_tx = 0;
1477
1478         return 0;
1479 }
1480
1481 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1482 {
1483         struct ucc_fast_private *uccf;
1484         u32 cecr_subblock;
1485
1486         uccf = ugeth->uccf;
1487
1488         cecr_subblock =
1489             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1490         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1491                      0);
1492         uccf->stopped_rx = 0;
1493
1494         return 0;
1495 }
1496
1497 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1498 {
1499         struct ucc_fast_private *uccf;
1500         int enabled_tx, enabled_rx;
1501
1502         uccf = ugeth->uccf;
1503
1504         /* check if the UCC number is in range. */
1505         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1506                 if (netif_msg_probe(ugeth))
1507                         pr_err("ucc_num out of range\n");
1508                 return -EINVAL;
1509         }
1510
1511         enabled_tx = uccf->enabled_tx;
1512         enabled_rx = uccf->enabled_rx;
1513
1514         /* Get Tx and Rx going again, in case this channel was actively
1515         disabled. */
1516         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1517                 ugeth_restart_tx(ugeth);
1518         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1519                 ugeth_restart_rx(ugeth);
1520
1521         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1522
1523         return 0;
1524
1525 }
1526
1527 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1528 {
1529         struct ucc_fast_private *uccf;
1530
1531         uccf = ugeth->uccf;
1532
1533         /* check if the UCC number is in range. */
1534         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1535                 if (netif_msg_probe(ugeth))
1536                         pr_err("ucc_num out of range\n");
1537                 return -EINVAL;
1538         }
1539
1540         /* Stop any transmissions */
1541         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1542                 ugeth_graceful_stop_tx(ugeth);
1543
1544         /* Stop any receptions */
1545         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1546                 ugeth_graceful_stop_rx(ugeth);
1547
1548         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1549
1550         return 0;
1551 }
1552
1553 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1554 {
1555         /* Prevent any further xmits */
1556         netif_tx_stop_all_queues(ugeth->ndev);
1557
1558         /* Disable the interrupt to avoid NAPI rescheduling. */
1559         disable_irq(ugeth->ug_info->uf_info.irq);
1560
1561         /* Stop NAPI, and possibly wait for its completion. */
1562         napi_disable(&ugeth->napi);
1563 }
1564
1565 static void ugeth_activate(struct ucc_geth_private *ugeth)
1566 {
1567         napi_enable(&ugeth->napi);
1568         enable_irq(ugeth->ug_info->uf_info.irq);
1569
1570         /* allow to xmit again  */
1571         netif_tx_wake_all_queues(ugeth->ndev);
1572         __netdev_watchdog_up(ugeth->ndev);
1573 }
1574
1575 /* Called every time the controller might need to be made
1576  * aware of new link state.  The PHY code conveys this
1577  * information through variables in the ugeth structure, and this
1578  * function converts those variables into the appropriate
1579  * register values, and can bring down the device if needed.
1580  */
1581
1582 static void adjust_link(struct net_device *dev)
1583 {
1584         struct ucc_geth_private *ugeth = netdev_priv(dev);
1585         struct ucc_geth __iomem *ug_regs;
1586         struct ucc_fast __iomem *uf_regs;
1587         struct phy_device *phydev = ugeth->phydev;
1588         int new_state = 0;
1589
1590         ug_regs = ugeth->ug_regs;
1591         uf_regs = ugeth->uccf->uf_regs;
1592
1593         if (phydev->link) {
1594                 u32 tempval = in_be32(&ug_regs->maccfg2);
1595                 u32 upsmr = in_be32(&uf_regs->upsmr);
1596                 /* Now we make sure that we can be in full duplex mode.
1597                  * If not, we operate in half-duplex mode. */
1598                 if (phydev->duplex != ugeth->oldduplex) {
1599                         new_state = 1;
1600                         if (!(phydev->duplex))
1601                                 tempval &= ~(MACCFG2_FDX);
1602                         else
1603                                 tempval |= MACCFG2_FDX;
1604                         ugeth->oldduplex = phydev->duplex;
1605                 }
1606
1607                 if (phydev->speed != ugeth->oldspeed) {
1608                         new_state = 1;
1609                         switch (phydev->speed) {
1610                         case SPEED_1000:
1611                                 tempval = ((tempval &
1612                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1613                                             MACCFG2_INTERFACE_MODE_BYTE);
1614                                 break;
1615                         case SPEED_100:
1616                         case SPEED_10:
1617                                 tempval = ((tempval &
1618                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1619                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1620                                 /* if reduced mode, re-set UPSMR.R10M */
1621                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1622                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1623                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1624                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1625                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1626                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1627                                         if (phydev->speed == SPEED_10)
1628                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1629                                         else
1630                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1631                                 }
1632                                 break;
1633                         default:
1634                                 if (netif_msg_link(ugeth))
1635                                         pr_warn(
1636                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1637                                                 dev->name, phydev->speed);
1638                                 break;
1639                         }
1640                         ugeth->oldspeed = phydev->speed;
1641                 }
1642
1643                 if (!ugeth->oldlink) {
1644                         new_state = 1;
1645                         ugeth->oldlink = 1;
1646                 }
1647
1648                 if (new_state) {
1649                         /*
1650                          * To change the MAC configuration we need to disable
1651                          * the controller. To do so, we have to either grab
1652                          * ugeth->lock, which is a bad idea since 'graceful
1653                          * stop' commands might take quite a while, or we can
1654                          * quiesce driver's activity.
1655                          */
1656                         ugeth_quiesce(ugeth);
1657                         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1658
1659                         out_be32(&ug_regs->maccfg2, tempval);
1660                         out_be32(&uf_regs->upsmr, upsmr);
1661
1662                         ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1663                         ugeth_activate(ugeth);
1664                 }
1665         } else if (ugeth->oldlink) {
1666                         new_state = 1;
1667                         ugeth->oldlink = 0;
1668                         ugeth->oldspeed = 0;
1669                         ugeth->oldduplex = -1;
1670         }
1671
1672         if (new_state && netif_msg_link(ugeth))
1673                 phy_print_status(phydev);
1674 }
1675
1676 /* Initialize TBI PHY interface for communicating with the
1677  * SERDES lynx PHY on the chip.  We communicate with this PHY
1678  * through the MDIO bus on each controller, treating it as a
1679  * "normal" PHY at the address found in the UTBIPA register.  We assume
1680  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1681  * it to a value that doesn't conflict with other PHYs on the bus, or the
1682  * value doesn't matter, as there are no other PHYs on the bus.
1683  */
1684 static void uec_configure_serdes(struct net_device *dev)
1685 {
1686         struct ucc_geth_private *ugeth = netdev_priv(dev);
1687         struct ucc_geth_info *ug_info = ugeth->ug_info;
1688         struct phy_device *tbiphy;
1689
1690         if (!ug_info->tbi_node) {
1691                 dev_warn(&dev->dev, "SGMII mode requires that the device "
1692                         "tree specify a tbi-handle\n");
1693                 return;
1694         }
1695
1696         tbiphy = of_phy_find_device(ug_info->tbi_node);
1697         if (!tbiphy) {
1698                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1699                 return;
1700         }
1701
1702         /*
1703          * If the link is already up, we must already be ok, and don't need to
1704          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1705          * everything for us?  Resetting it takes the link down and requires
1706          * several seconds for it to come back.
1707          */
1708         if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) {
1709                 put_device(&tbiphy->mdio.dev);
1710                 return;
1711         }
1712
1713         /* Single clk mode, mii mode off(for serdes communication) */
1714         phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1715
1716         phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1717
1718         phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1719
1720         put_device(&tbiphy->mdio.dev);
1721 }
1722
1723 /* Configure the PHY for dev.
1724  * returns 0 if success.  -1 if failure
1725  */
1726 static int init_phy(struct net_device *dev)
1727 {
1728         struct ucc_geth_private *priv = netdev_priv(dev);
1729         struct ucc_geth_info *ug_info = priv->ug_info;
1730         struct phy_device *phydev;
1731
1732         priv->oldlink = 0;
1733         priv->oldspeed = 0;
1734         priv->oldduplex = -1;
1735
1736         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1737                                 priv->phy_interface);
1738         if (!phydev) {
1739                 dev_err(&dev->dev, "Could not attach to PHY\n");
1740                 return -ENODEV;
1741         }
1742
1743         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1744                 uec_configure_serdes(dev);
1745
1746         phydev->supported &= (SUPPORTED_MII |
1747                               SUPPORTED_Autoneg |
1748                               ADVERTISED_10baseT_Half |
1749                               ADVERTISED_10baseT_Full |
1750                               ADVERTISED_100baseT_Half |
1751                               ADVERTISED_100baseT_Full);
1752
1753         if (priv->max_speed == SPEED_1000)
1754                 phydev->supported |= ADVERTISED_1000baseT_Full;
1755
1756         phydev->advertising = phydev->supported;
1757
1758         priv->phydev = phydev;
1759
1760         return 0;
1761 }
1762
1763 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1764 {
1765 #ifdef DEBUG
1766         ucc_fast_dump_regs(ugeth->uccf);
1767         dump_regs(ugeth);
1768         dump_bds(ugeth);
1769 #endif
1770 }
1771
1772 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1773                                                        ugeth,
1774                                                        enum enet_addr_type
1775                                                        enet_addr_type)
1776 {
1777         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1778         struct ucc_fast_private *uccf;
1779         enum comm_dir comm_dir;
1780         struct list_head *p_lh;
1781         u16 i, num;
1782         u32 __iomem *addr_h;
1783         u32 __iomem *addr_l;
1784         u8 *p_counter;
1785
1786         uccf = ugeth->uccf;
1787
1788         p_82xx_addr_filt =
1789             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1790             ugeth->p_rx_glbl_pram->addressfiltering;
1791
1792         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1793                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1794                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1795                 p_lh = &ugeth->group_hash_q;
1796                 p_counter = &(ugeth->numGroupAddrInHash);
1797         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1798                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1799                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1800                 p_lh = &ugeth->ind_hash_q;
1801                 p_counter = &(ugeth->numIndAddrInHash);
1802         } else
1803                 return -EINVAL;
1804
1805         comm_dir = 0;
1806         if (uccf->enabled_tx)
1807                 comm_dir |= COMM_DIR_TX;
1808         if (uccf->enabled_rx)
1809                 comm_dir |= COMM_DIR_RX;
1810         if (comm_dir)
1811                 ugeth_disable(ugeth, comm_dir);
1812
1813         /* Clear the hash table. */
1814         out_be32(addr_h, 0x00000000);
1815         out_be32(addr_l, 0x00000000);
1816
1817         if (!p_lh)
1818                 return 0;
1819
1820         num = *p_counter;
1821
1822         /* Delete all remaining CQ elements */
1823         for (i = 0; i < num; i++)
1824                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1825
1826         *p_counter = 0;
1827
1828         if (comm_dir)
1829                 ugeth_enable(ugeth, comm_dir);
1830
1831         return 0;
1832 }
1833
1834 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1835                                                     u8 paddr_num)
1836 {
1837         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1838         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1839 }
1840
1841 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1842 {
1843         struct ucc_geth_info *ug_info;
1844         struct ucc_fast_info *uf_info;
1845         u16 i, j;
1846         u8 __iomem *bd;
1847
1848
1849         ug_info = ugeth->ug_info;
1850         uf_info = &ug_info->uf_info;
1851
1852         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1853                 if (ugeth->p_rx_bd_ring[i]) {
1854                         /* Return existing data buffers in ring */
1855                         bd = ugeth->p_rx_bd_ring[i];
1856                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1857                                 if (ugeth->rx_skbuff[i][j]) {
1858                                         dma_unmap_single(ugeth->dev,
1859                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1860                                                 ugeth->ug_info->
1861                                                 uf_info.max_rx_buf_length +
1862                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1863                                                 DMA_FROM_DEVICE);
1864                                         dev_kfree_skb_any(
1865                                                 ugeth->rx_skbuff[i][j]);
1866                                         ugeth->rx_skbuff[i][j] = NULL;
1867                                 }
1868                                 bd += sizeof(struct qe_bd);
1869                         }
1870
1871                         kfree(ugeth->rx_skbuff[i]);
1872
1873                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1874                             MEM_PART_SYSTEM)
1875                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1876                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1877                                  MEM_PART_MURAM)
1878                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1879                         ugeth->p_rx_bd_ring[i] = NULL;
1880                 }
1881         }
1882
1883 }
1884
1885 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
1886 {
1887         struct ucc_geth_info *ug_info;
1888         struct ucc_fast_info *uf_info;
1889         u16 i, j;
1890         u8 __iomem *bd;
1891
1892         netdev_reset_queue(ugeth->ndev);
1893
1894         ug_info = ugeth->ug_info;
1895         uf_info = &ug_info->uf_info;
1896
1897         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1898                 bd = ugeth->p_tx_bd_ring[i];
1899                 if (!bd)
1900                         continue;
1901                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1902                         if (ugeth->tx_skbuff[i][j]) {
1903                                 dma_unmap_single(ugeth->dev,
1904                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1905                                                  (in_be32((u32 __iomem *)bd) &
1906                                                   BD_LENGTH_MASK),
1907                                                  DMA_TO_DEVICE);
1908                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1909                                 ugeth->tx_skbuff[i][j] = NULL;
1910                         }
1911                 }
1912
1913                 kfree(ugeth->tx_skbuff[i]);
1914
1915                 if (ugeth->p_tx_bd_ring[i]) {
1916                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1917                             MEM_PART_SYSTEM)
1918                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1919                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1920                                  MEM_PART_MURAM)
1921                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1922                         ugeth->p_tx_bd_ring[i] = NULL;
1923                 }
1924         }
1925
1926 }
1927
1928 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1929 {
1930         if (!ugeth)
1931                 return;
1932
1933         if (ugeth->uccf) {
1934                 ucc_fast_free(ugeth->uccf);
1935                 ugeth->uccf = NULL;
1936         }
1937
1938         if (ugeth->p_thread_data_tx) {
1939                 qe_muram_free(ugeth->thread_dat_tx_offset);
1940                 ugeth->p_thread_data_tx = NULL;
1941         }
1942         if (ugeth->p_thread_data_rx) {
1943                 qe_muram_free(ugeth->thread_dat_rx_offset);
1944                 ugeth->p_thread_data_rx = NULL;
1945         }
1946         if (ugeth->p_exf_glbl_param) {
1947                 qe_muram_free(ugeth->exf_glbl_param_offset);
1948                 ugeth->p_exf_glbl_param = NULL;
1949         }
1950         if (ugeth->p_rx_glbl_pram) {
1951                 qe_muram_free(ugeth->rx_glbl_pram_offset);
1952                 ugeth->p_rx_glbl_pram = NULL;
1953         }
1954         if (ugeth->p_tx_glbl_pram) {
1955                 qe_muram_free(ugeth->tx_glbl_pram_offset);
1956                 ugeth->p_tx_glbl_pram = NULL;
1957         }
1958         if (ugeth->p_send_q_mem_reg) {
1959                 qe_muram_free(ugeth->send_q_mem_reg_offset);
1960                 ugeth->p_send_q_mem_reg = NULL;
1961         }
1962         if (ugeth->p_scheduler) {
1963                 qe_muram_free(ugeth->scheduler_offset);
1964                 ugeth->p_scheduler = NULL;
1965         }
1966         if (ugeth->p_tx_fw_statistics_pram) {
1967                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1968                 ugeth->p_tx_fw_statistics_pram = NULL;
1969         }
1970         if (ugeth->p_rx_fw_statistics_pram) {
1971                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1972                 ugeth->p_rx_fw_statistics_pram = NULL;
1973         }
1974         if (ugeth->p_rx_irq_coalescing_tbl) {
1975                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1976                 ugeth->p_rx_irq_coalescing_tbl = NULL;
1977         }
1978         if (ugeth->p_rx_bd_qs_tbl) {
1979                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1980                 ugeth->p_rx_bd_qs_tbl = NULL;
1981         }
1982         if (ugeth->p_init_enet_param_shadow) {
1983                 return_init_enet_entries(ugeth,
1984                                          &(ugeth->p_init_enet_param_shadow->
1985                                            rxthread[0]),
1986                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1987                                          ugeth->ug_info->riscRx, 1);
1988                 return_init_enet_entries(ugeth,
1989                                          &(ugeth->p_init_enet_param_shadow->
1990                                            txthread[0]),
1991                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1992                                          ugeth->ug_info->riscTx, 0);
1993                 kfree(ugeth->p_init_enet_param_shadow);
1994                 ugeth->p_init_enet_param_shadow = NULL;
1995         }
1996         ucc_geth_free_tx(ugeth);
1997         ucc_geth_free_rx(ugeth);
1998         while (!list_empty(&ugeth->group_hash_q))
1999                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2000                                         (dequeue(&ugeth->group_hash_q)));
2001         while (!list_empty(&ugeth->ind_hash_q))
2002                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2003                                         (dequeue(&ugeth->ind_hash_q)));
2004         if (ugeth->ug_regs) {
2005                 iounmap(ugeth->ug_regs);
2006                 ugeth->ug_regs = NULL;
2007         }
2008 }
2009
2010 static void ucc_geth_set_multi(struct net_device *dev)
2011 {
2012         struct ucc_geth_private *ugeth;
2013         struct netdev_hw_addr *ha;
2014         struct ucc_fast __iomem *uf_regs;
2015         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2016
2017         ugeth = netdev_priv(dev);
2018
2019         uf_regs = ugeth->uccf->uf_regs;
2020
2021         if (dev->flags & IFF_PROMISC) {
2022                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2023         } else {
2024                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2025
2026                 p_82xx_addr_filt =
2027                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2028                     p_rx_glbl_pram->addressfiltering;
2029
2030                 if (dev->flags & IFF_ALLMULTI) {
2031                         /* Catch all multicast addresses, so set the
2032                          * filter to all 1's.
2033                          */
2034                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2035                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2036                 } else {
2037                         /* Clear filter and add the addresses in the list.
2038                          */
2039                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2040                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2041
2042                         netdev_for_each_mc_addr(ha, dev) {
2043                                 /* Ask CPM to run CRC and set bit in
2044                                  * filter mask.
2045                                  */
2046                                 hw_add_addr_in_hash(ugeth, ha->addr);
2047                         }
2048                 }
2049         }
2050 }
2051
2052 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2053 {
2054         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2055         struct phy_device *phydev = ugeth->phydev;
2056
2057         ugeth_vdbg("%s: IN", __func__);
2058
2059         /*
2060          * Tell the kernel the link is down.
2061          * Must be done before disabling the controller
2062          * or deadlock may happen.
2063          */
2064         phy_stop(phydev);
2065
2066         /* Disable the controller */
2067         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2068
2069         /* Mask all interrupts */
2070         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2071
2072         /* Clear all interrupts */
2073         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2074
2075         /* Disable Rx and Tx */
2076         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2077
2078         ucc_geth_memclean(ugeth);
2079 }
2080
2081 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2082 {
2083         struct ucc_geth_info *ug_info;
2084         struct ucc_fast_info *uf_info;
2085         int i;
2086
2087         ug_info = ugeth->ug_info;
2088         uf_info = &ug_info->uf_info;
2089
2090         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2091               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2092                 if (netif_msg_probe(ugeth))
2093                         pr_err("Bad memory partition value\n");
2094                 return -EINVAL;
2095         }
2096
2097         /* Rx BD lengths */
2098         for (i = 0; i < ug_info->numQueuesRx; i++) {
2099                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2100                     (ug_info->bdRingLenRx[i] %
2101                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2102                         if (netif_msg_probe(ugeth))
2103                                 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
2104                         return -EINVAL;
2105                 }
2106         }
2107
2108         /* Tx BD lengths */
2109         for (i = 0; i < ug_info->numQueuesTx; i++) {
2110                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2111                         if (netif_msg_probe(ugeth))
2112                                 pr_err("Tx BD ring length must be no smaller than 2\n");
2113                         return -EINVAL;
2114                 }
2115         }
2116
2117         /* mrblr */
2118         if ((uf_info->max_rx_buf_length == 0) ||
2119             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2120                 if (netif_msg_probe(ugeth))
2121                         pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
2122                 return -EINVAL;
2123         }
2124
2125         /* num Tx queues */
2126         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2127                 if (netif_msg_probe(ugeth))
2128                         pr_err("number of tx queues too large\n");
2129                 return -EINVAL;
2130         }
2131
2132         /* num Rx queues */
2133         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2134                 if (netif_msg_probe(ugeth))
2135                         pr_err("number of rx queues too large\n");
2136                 return -EINVAL;
2137         }
2138
2139         /* l2qt */
2140         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2141                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2142                         if (netif_msg_probe(ugeth))
2143                                 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
2144                         return -EINVAL;
2145                 }
2146         }
2147
2148         /* l3qt */
2149         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2150                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2151                         if (netif_msg_probe(ugeth))
2152                                 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
2153                         return -EINVAL;
2154                 }
2155         }
2156
2157         if (ug_info->cam && !ug_info->ecamptr) {
2158                 if (netif_msg_probe(ugeth))
2159                         pr_err("If cam mode is chosen, must supply cam ptr\n");
2160                 return -EINVAL;
2161         }
2162
2163         if ((ug_info->numStationAddresses !=
2164              UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2165             ug_info->rxExtendedFiltering) {
2166                 if (netif_msg_probe(ugeth))
2167                         pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
2168                 return -EINVAL;
2169         }
2170
2171         /* Generate uccm_mask for receive */
2172         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2173         for (i = 0; i < ug_info->numQueuesRx; i++)
2174                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2175
2176         for (i = 0; i < ug_info->numQueuesTx; i++)
2177                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2178         /* Initialize the general fast UCC block. */
2179         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2180                 if (netif_msg_probe(ugeth))
2181                         pr_err("Failed to init uccf\n");
2182                 return -ENOMEM;
2183         }
2184
2185         /* read the number of risc engines, update the riscTx and riscRx
2186          * if there are 4 riscs in QE
2187          */
2188         if (qe_get_num_of_risc() == 4) {
2189                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2190                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2191         }
2192
2193         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2194         if (!ugeth->ug_regs) {
2195                 if (netif_msg_probe(ugeth))
2196                         pr_err("Failed to ioremap regs\n");
2197                 return -ENOMEM;
2198         }
2199
2200         return 0;
2201 }
2202
2203 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2204 {
2205         struct ucc_geth_info *ug_info;
2206         struct ucc_fast_info *uf_info;
2207         int length;
2208         u16 i, j;
2209         u8 __iomem *bd;
2210
2211         ug_info = ugeth->ug_info;
2212         uf_info = &ug_info->uf_info;
2213
2214         /* Allocate Tx bds */
2215         for (j = 0; j < ug_info->numQueuesTx; j++) {
2216                 /* Allocate in multiple of
2217                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2218                    according to spec */
2219                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2220                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2221                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2222                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2223                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2224                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2225                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2226                         u32 align = 4;
2227                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2228                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2229                         ugeth->tx_bd_ring_offset[j] =
2230                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2231
2232                         if (ugeth->tx_bd_ring_offset[j] != 0)
2233                                 ugeth->p_tx_bd_ring[j] =
2234                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2235                                         align) & ~(align - 1));
2236                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2237                         ugeth->tx_bd_ring_offset[j] =
2238                             qe_muram_alloc(length,
2239                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2240                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2241                                 ugeth->p_tx_bd_ring[j] =
2242                                     (u8 __iomem *) qe_muram_addr(ugeth->
2243                                                          tx_bd_ring_offset[j]);
2244                 }
2245                 if (!ugeth->p_tx_bd_ring[j]) {
2246                         if (netif_msg_ifup(ugeth))
2247                                 pr_err("Can not allocate memory for Tx bd rings\n");
2248                         return -ENOMEM;
2249                 }
2250                 /* Zero unused end of bd ring, according to spec */
2251                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2252                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2253                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2254         }
2255
2256         /* Init Tx bds */
2257         for (j = 0; j < ug_info->numQueuesTx; j++) {
2258                 /* Setup the skbuff rings */
2259                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2260                                               ugeth->ug_info->bdRingLenTx[j],
2261                                               GFP_KERNEL);
2262
2263                 if (ugeth->tx_skbuff[j] == NULL) {
2264                         if (netif_msg_ifup(ugeth))
2265                                 pr_err("Could not allocate tx_skbuff\n");
2266                         return -ENOMEM;
2267                 }
2268
2269                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2270                         ugeth->tx_skbuff[j][i] = NULL;
2271
2272                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2273                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2274                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2275                         /* clear bd buffer */
2276                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2277                         /* set bd status and length */
2278                         out_be32((u32 __iomem *)bd, 0);
2279                         bd += sizeof(struct qe_bd);
2280                 }
2281                 bd -= sizeof(struct qe_bd);
2282                 /* set bd status and length */
2283                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2284         }
2285
2286         return 0;
2287 }
2288
2289 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2290 {
2291         struct ucc_geth_info *ug_info;
2292         struct ucc_fast_info *uf_info;
2293         int length;
2294         u16 i, j;
2295         u8 __iomem *bd;
2296
2297         ug_info = ugeth->ug_info;
2298         uf_info = &ug_info->uf_info;
2299
2300         /* Allocate Rx bds */
2301         for (j = 0; j < ug_info->numQueuesRx; j++) {
2302                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2303                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2304                         u32 align = 4;
2305                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2306                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2307                         ugeth->rx_bd_ring_offset[j] =
2308                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2309                         if (ugeth->rx_bd_ring_offset[j] != 0)
2310                                 ugeth->p_rx_bd_ring[j] =
2311                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2312                                         align) & ~(align - 1));
2313                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2314                         ugeth->rx_bd_ring_offset[j] =
2315                             qe_muram_alloc(length,
2316                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2317                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2318                                 ugeth->p_rx_bd_ring[j] =
2319                                     (u8 __iomem *) qe_muram_addr(ugeth->
2320                                                          rx_bd_ring_offset[j]);
2321                 }
2322                 if (!ugeth->p_rx_bd_ring[j]) {
2323                         if (netif_msg_ifup(ugeth))
2324                                 pr_err("Can not allocate memory for Rx bd rings\n");
2325                         return -ENOMEM;
2326                 }
2327         }
2328
2329         /* Init Rx bds */
2330         for (j = 0; j < ug_info->numQueuesRx; j++) {
2331                 /* Setup the skbuff rings */
2332                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2333                                               ugeth->ug_info->bdRingLenRx[j],
2334                                               GFP_KERNEL);
2335
2336                 if (ugeth->rx_skbuff[j] == NULL) {
2337                         if (netif_msg_ifup(ugeth))
2338                                 pr_err("Could not allocate rx_skbuff\n");
2339                         return -ENOMEM;
2340                 }
2341
2342                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2343                         ugeth->rx_skbuff[j][i] = NULL;
2344
2345                 ugeth->skb_currx[j] = 0;
2346                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2347                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2348                         /* set bd status and length */
2349                         out_be32((u32 __iomem *)bd, R_I);
2350                         /* clear bd buffer */
2351                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2352                         bd += sizeof(struct qe_bd);
2353                 }
2354                 bd -= sizeof(struct qe_bd);
2355                 /* set bd status and length */
2356                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2357         }
2358
2359         return 0;
2360 }
2361
2362 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2363 {
2364         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2365         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2366         struct ucc_fast_private *uccf;
2367         struct ucc_geth_info *ug_info;
2368         struct ucc_fast_info *uf_info;
2369         struct ucc_fast __iomem *uf_regs;
2370         struct ucc_geth __iomem *ug_regs;
2371         int ret_val = -EINVAL;
2372         u32 remoder = UCC_GETH_REMODER_INIT;
2373         u32 init_enet_pram_offset, cecr_subblock, command;
2374         u32 ifstat, i, j, size, l2qt, l3qt;
2375         u16 temoder = UCC_GETH_TEMODER_INIT;
2376         u16 test;
2377         u8 function_code = 0;
2378         u8 __iomem *endOfRing;
2379         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2380
2381         ugeth_vdbg("%s: IN", __func__);
2382         uccf = ugeth->uccf;
2383         ug_info = ugeth->ug_info;
2384         uf_info = &ug_info->uf_info;
2385         uf_regs = uccf->uf_regs;
2386         ug_regs = ugeth->ug_regs;
2387
2388         switch (ug_info->numThreadsRx) {
2389         case UCC_GETH_NUM_OF_THREADS_1:
2390                 numThreadsRxNumerical = 1;
2391                 break;
2392         case UCC_GETH_NUM_OF_THREADS_2:
2393                 numThreadsRxNumerical = 2;
2394                 break;
2395         case UCC_GETH_NUM_OF_THREADS_4:
2396                 numThreadsRxNumerical = 4;
2397                 break;
2398         case UCC_GETH_NUM_OF_THREADS_6:
2399                 numThreadsRxNumerical = 6;
2400                 break;
2401         case UCC_GETH_NUM_OF_THREADS_8:
2402                 numThreadsRxNumerical = 8;
2403                 break;
2404         default:
2405                 if (netif_msg_ifup(ugeth))
2406                         pr_err("Bad number of Rx threads value\n");
2407                 return -EINVAL;
2408         }
2409
2410         switch (ug_info->numThreadsTx) {
2411         case UCC_GETH_NUM_OF_THREADS_1:
2412                 numThreadsTxNumerical = 1;
2413                 break;
2414         case UCC_GETH_NUM_OF_THREADS_2:
2415                 numThreadsTxNumerical = 2;
2416                 break;
2417         case UCC_GETH_NUM_OF_THREADS_4:
2418                 numThreadsTxNumerical = 4;
2419                 break;
2420         case UCC_GETH_NUM_OF_THREADS_6:
2421                 numThreadsTxNumerical = 6;
2422                 break;
2423         case UCC_GETH_NUM_OF_THREADS_8:
2424                 numThreadsTxNumerical = 8;
2425                 break;
2426         default:
2427                 if (netif_msg_ifup(ugeth))
2428                         pr_err("Bad number of Tx threads value\n");
2429                 return -EINVAL;
2430         }
2431
2432         /* Calculate rx_extended_features */
2433         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2434             ug_info->ipAddressAlignment ||
2435             (ug_info->numStationAddresses !=
2436              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2437
2438         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2439                 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2440                 (ug_info->vlanOperationNonTagged !=
2441                  UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2442
2443         init_default_reg_vals(&uf_regs->upsmr,
2444                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2445
2446         /*                    Set UPSMR                      */
2447         /* For more details see the hardware spec.           */
2448         init_rx_parameters(ug_info->bro,
2449                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2450
2451         /* We're going to ignore other registers for now, */
2452         /* except as needed to get up and running         */
2453
2454         /*                    Set MACCFG1                    */
2455         /* For more details see the hardware spec.           */
2456         init_flow_control_params(ug_info->aufc,
2457                                  ug_info->receiveFlowControl,
2458                                  ug_info->transmitFlowControl,
2459                                  ug_info->pausePeriod,
2460                                  ug_info->extensionField,
2461                                  &uf_regs->upsmr,
2462                                  &ug_regs->uempr, &ug_regs->maccfg1);
2463
2464         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2465
2466         /*                    Set IPGIFG                     */
2467         /* For more details see the hardware spec.           */
2468         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2469                                               ug_info->nonBackToBackIfgPart2,
2470                                               ug_info->
2471                                               miminumInterFrameGapEnforcement,
2472                                               ug_info->backToBackInterFrameGap,
2473                                               &ug_regs->ipgifg);
2474         if (ret_val != 0) {
2475                 if (netif_msg_ifup(ugeth))
2476                         pr_err("IPGIFG initialization parameter too large\n");
2477                 return ret_val;
2478         }
2479
2480         /*                    Set HAFDUP                     */
2481         /* For more details see the hardware spec.           */
2482         ret_val = init_half_duplex_params(ug_info->altBeb,
2483                                           ug_info->backPressureNoBackoff,
2484                                           ug_info->noBackoff,
2485                                           ug_info->excessDefer,
2486                                           ug_info->altBebTruncation,
2487                                           ug_info->maxRetransmission,
2488                                           ug_info->collisionWindow,
2489                                           &ug_regs->hafdup);
2490         if (ret_val != 0) {
2491                 if (netif_msg_ifup(ugeth))
2492                         pr_err("Half Duplex initialization parameter too large\n");
2493                 return ret_val;
2494         }
2495
2496         /*                    Set IFSTAT                     */
2497         /* For more details see the hardware spec.           */
2498         /* Read only - resets upon read                      */
2499         ifstat = in_be32(&ug_regs->ifstat);
2500
2501         /*                    Clear UEMPR                    */
2502         /* For more details see the hardware spec.           */
2503         out_be32(&ug_regs->uempr, 0);
2504
2505         /*                    Set UESCR                      */
2506         /* For more details see the hardware spec.           */
2507         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2508                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2509                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2510
2511         ret_val = ucc_geth_alloc_tx(ugeth);
2512         if (ret_val != 0)
2513                 return ret_val;
2514
2515         ret_val = ucc_geth_alloc_rx(ugeth);
2516         if (ret_val != 0)
2517                 return ret_val;
2518
2519         /*
2520          * Global PRAM
2521          */
2522         /* Tx global PRAM */
2523         /* Allocate global tx parameter RAM page */
2524         ugeth->tx_glbl_pram_offset =
2525             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2526                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2527         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2528                 if (netif_msg_ifup(ugeth))
2529                         pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
2530                 return -ENOMEM;
2531         }
2532         ugeth->p_tx_glbl_pram =
2533             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2534                                                         tx_glbl_pram_offset);
2535         /* Zero out p_tx_glbl_pram */
2536         memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2537
2538         /* Fill global PRAM */
2539
2540         /* TQPTR */
2541         /* Size varies with number of Tx threads */
2542         ugeth->thread_dat_tx_offset =
2543             qe_muram_alloc(numThreadsTxNumerical *
2544                            sizeof(struct ucc_geth_thread_data_tx) +
2545                            32 * (numThreadsTxNumerical == 1),
2546                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2547         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2548                 if (netif_msg_ifup(ugeth))
2549                         pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
2550                 return -ENOMEM;
2551         }
2552
2553         ugeth->p_thread_data_tx =
2554             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2555                                                         thread_dat_tx_offset);
2556         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2557
2558         /* vtagtable */
2559         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2560                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2561                          ug_info->vtagtable[i]);
2562
2563         /* iphoffset */
2564         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2565                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2566                                 ug_info->iphoffset[i]);
2567
2568         /* SQPTR */
2569         /* Size varies with number of Tx queues */
2570         ugeth->send_q_mem_reg_offset =
2571             qe_muram_alloc(ug_info->numQueuesTx *
2572                            sizeof(struct ucc_geth_send_queue_qd),
2573                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2574         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2575                 if (netif_msg_ifup(ugeth))
2576                         pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
2577                 return -ENOMEM;
2578         }
2579
2580         ugeth->p_send_q_mem_reg =
2581             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2582                         send_q_mem_reg_offset);
2583         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2584
2585         /* Setup the table */
2586         /* Assume BD rings are already established */
2587         for (i = 0; i < ug_info->numQueuesTx; i++) {
2588                 endOfRing =
2589                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2590                                               1) * sizeof(struct qe_bd);
2591                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2592                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2593                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2594                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2595                                  last_bd_completed_address,
2596                                  (u32) virt_to_phys(endOfRing));
2597                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2598                            MEM_PART_MURAM) {
2599                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2600                                  (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
2601                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2602                                  last_bd_completed_address,
2603                                  (u32)qe_muram_dma(endOfRing));
2604                 }
2605         }
2606
2607         /* schedulerbasepointer */
2608
2609         if (ug_info->numQueuesTx > 1) {
2610         /* scheduler exists only if more than 1 tx queue */
2611                 ugeth->scheduler_offset =
2612                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2613                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2614                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2615                         if (netif_msg_ifup(ugeth))
2616                                 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
2617                         return -ENOMEM;
2618                 }
2619
2620                 ugeth->p_scheduler =
2621                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2622                                                            scheduler_offset);
2623                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2624                          ugeth->scheduler_offset);
2625                 /* Zero out p_scheduler */
2626                 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2627
2628                 /* Set values in scheduler */
2629                 out_be32(&ugeth->p_scheduler->mblinterval,
2630                          ug_info->mblinterval);
2631                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2632                          ug_info->nortsrbytetime);
2633                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2634                 out_8(&ugeth->p_scheduler->strictpriorityq,
2635                                 ug_info->strictpriorityq);
2636                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2637                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2638                 for (i = 0; i < NUM_TX_QUEUES; i++)
2639                         out_8(&ugeth->p_scheduler->weightfactor[i],
2640                             ug_info->weightfactor[i]);
2641
2642                 /* Set pointers to cpucount registers in scheduler */
2643                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2644                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2645                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2646                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2647                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2648                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2649                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2650                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2651         }
2652
2653         /* schedulerbasepointer */
2654         /* TxRMON_PTR (statistics) */
2655         if (ug_info->
2656             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2657                 ugeth->tx_fw_statistics_pram_offset =
2658                     qe_muram_alloc(sizeof
2659                                    (struct ucc_geth_tx_firmware_statistics_pram),
2660                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2661                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2662                         if (netif_msg_ifup(ugeth))
2663                                 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
2664                         return -ENOMEM;
2665                 }
2666                 ugeth->p_tx_fw_statistics_pram =
2667                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2668                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2669                 /* Zero out p_tx_fw_statistics_pram */
2670                 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2671                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2672         }
2673
2674         /* temoder */
2675         /* Already has speed set */
2676
2677         if (ug_info->numQueuesTx > 1)
2678                 temoder |= TEMODER_SCHEDULER_ENABLE;
2679         if (ug_info->ipCheckSumGenerate)
2680                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2681         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2682         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2683
2684         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2685
2686         /* Function code register value to be used later */
2687         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2688         /* Required for QE */
2689
2690         /* function code register */
2691         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2692
2693         /* Rx global PRAM */
2694         /* Allocate global rx parameter RAM page */
2695         ugeth->rx_glbl_pram_offset =
2696             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2697                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2698         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2699                 if (netif_msg_ifup(ugeth))
2700                         pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
2701                 return -ENOMEM;
2702         }
2703         ugeth->p_rx_glbl_pram =
2704             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2705                                                         rx_glbl_pram_offset);
2706         /* Zero out p_rx_glbl_pram */
2707         memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2708
2709         /* Fill global PRAM */
2710
2711         /* RQPTR */
2712         /* Size varies with number of Rx threads */
2713         ugeth->thread_dat_rx_offset =
2714             qe_muram_alloc(numThreadsRxNumerical *
2715                            sizeof(struct ucc_geth_thread_data_rx),
2716                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2717         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2718                 if (netif_msg_ifup(ugeth))
2719                         pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
2720                 return -ENOMEM;
2721         }
2722
2723         ugeth->p_thread_data_rx =
2724             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2725                                                         thread_dat_rx_offset);
2726         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2727
2728         /* typeorlen */
2729         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2730
2731         /* rxrmonbaseptr (statistics) */
2732         if (ug_info->
2733             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2734                 ugeth->rx_fw_statistics_pram_offset =
2735                     qe_muram_alloc(sizeof
2736                                    (struct ucc_geth_rx_firmware_statistics_pram),
2737                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2738                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2739                         if (netif_msg_ifup(ugeth))
2740                                 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
2741                         return -ENOMEM;
2742                 }
2743                 ugeth->p_rx_fw_statistics_pram =
2744                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2745                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2746                 /* Zero out p_rx_fw_statistics_pram */
2747                 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2748                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2749         }
2750
2751         /* intCoalescingPtr */
2752
2753         /* Size varies with number of Rx queues */
2754         ugeth->rx_irq_coalescing_tbl_offset =
2755             qe_muram_alloc(ug_info->numQueuesRx *
2756                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2757                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2758         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2759                 if (netif_msg_ifup(ugeth))
2760                         pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
2761                 return -ENOMEM;
2762         }
2763
2764         ugeth->p_rx_irq_coalescing_tbl =
2765             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2766             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2767         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2768                  ugeth->rx_irq_coalescing_tbl_offset);
2769
2770         /* Fill interrupt coalescing table */
2771         for (i = 0; i < ug_info->numQueuesRx; i++) {
2772                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2773                          interruptcoalescingmaxvalue,
2774                          ug_info->interruptcoalescingmaxvalue[i]);
2775                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2776                          interruptcoalescingcounter,
2777                          ug_info->interruptcoalescingmaxvalue[i]);
2778         }
2779
2780         /* MRBLR */
2781         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2782                              &ugeth->p_rx_glbl_pram->mrblr);
2783         /* MFLR */
2784         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2785         /* MINFLR */
2786         init_min_frame_len(ug_info->minFrameLength,
2787                            &ugeth->p_rx_glbl_pram->minflr,
2788                            &ugeth->p_rx_glbl_pram->mrblr);
2789         /* MAXD1 */
2790         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2791         /* MAXD2 */
2792         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2793
2794         /* l2qt */
2795         l2qt = 0;
2796         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2797                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2798         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2799
2800         /* l3qt */
2801         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2802                 l3qt = 0;
2803                 for (i = 0; i < 8; i++)
2804                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2805                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2806         }
2807
2808         /* vlantype */
2809         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2810
2811         /* vlantci */
2812         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2813
2814         /* ecamptr */
2815         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2816
2817         /* RBDQPTR */
2818         /* Size varies with number of Rx queues */
2819         ugeth->rx_bd_qs_tbl_offset =
2820             qe_muram_alloc(ug_info->numQueuesRx *
2821                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2822                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2823                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2824         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2825                 if (netif_msg_ifup(ugeth))
2826                         pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
2827                 return -ENOMEM;
2828         }
2829
2830         ugeth->p_rx_bd_qs_tbl =
2831             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2832                                     rx_bd_qs_tbl_offset);
2833         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2834         /* Zero out p_rx_bd_qs_tbl */
2835         memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2836                0,
2837                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2838                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
2839
2840         /* Setup the table */
2841         /* Assume BD rings are already established */
2842         for (i = 0; i < ug_info->numQueuesRx; i++) {
2843                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2844                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2845                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2846                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2847                            MEM_PART_MURAM) {
2848                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2849                                  (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
2850                 }
2851                 /* rest of fields handled by QE */
2852         }
2853
2854         /* remoder */
2855         /* Already has speed set */
2856
2857         if (ugeth->rx_extended_features)
2858                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2859         if (ug_info->rxExtendedFiltering)
2860                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2861         if (ug_info->dynamicMaxFrameLength)
2862                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2863         if (ug_info->dynamicMinFrameLength)
2864                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2865         remoder |=
2866             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2867         remoder |=
2868             ug_info->
2869             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2870         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2871         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2872         if (ug_info->ipCheckSumCheck)
2873                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2874         if (ug_info->ipAddressAlignment)
2875                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2876         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2877
2878         /* Note that this function must be called */
2879         /* ONLY AFTER p_tx_fw_statistics_pram */
2880         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2881         init_firmware_statistics_gathering_mode((ug_info->
2882                 statisticsMode &
2883                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2884                 (ug_info->statisticsMode &
2885                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2886                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2887                 ugeth->tx_fw_statistics_pram_offset,
2888                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2889                 ugeth->rx_fw_statistics_pram_offset,
2890                 &ugeth->p_tx_glbl_pram->temoder,
2891                 &ugeth->p_rx_glbl_pram->remoder);
2892
2893         /* function code register */
2894         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2895
2896         /* initialize extended filtering */
2897         if (ug_info->rxExtendedFiltering) {
2898                 if (!ug_info->extendedFilteringChainPointer) {
2899                         if (netif_msg_ifup(ugeth))
2900                                 pr_err("Null Extended Filtering Chain Pointer\n");
2901                         return -EINVAL;
2902                 }
2903
2904                 /* Allocate memory for extended filtering Mode Global
2905                 Parameters */
2906                 ugeth->exf_glbl_param_offset =
2907                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2908                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2909                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2910                         if (netif_msg_ifup(ugeth))
2911                                 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
2912                         return -ENOMEM;
2913                 }
2914
2915                 ugeth->p_exf_glbl_param =
2916                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2917                                  exf_glbl_param_offset);
2918                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2919                          ugeth->exf_glbl_param_offset);
2920                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2921                          (u32) ug_info->extendedFilteringChainPointer);
2922
2923         } else {                /* initialize 82xx style address filtering */
2924
2925                 /* Init individual address recognition registers to disabled */
2926
2927                 for (j = 0; j < NUM_OF_PADDRS; j++)
2928                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2929
2930                 p_82xx_addr_filt =
2931                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2932                     p_rx_glbl_pram->addressfiltering;
2933
2934                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2935                         ENET_ADDR_TYPE_GROUP);
2936                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2937                         ENET_ADDR_TYPE_INDIVIDUAL);
2938         }
2939
2940         /*
2941          * Initialize UCC at QE level
2942          */
2943
2944         command = QE_INIT_TX_RX;
2945
2946         /* Allocate shadow InitEnet command parameter structure.
2947          * This is needed because after the InitEnet command is executed,
2948          * the structure in DPRAM is released, because DPRAM is a premium
2949          * resource.
2950          * This shadow structure keeps a copy of what was done so that the
2951          * allocated resources can be released when the channel is freed.
2952          */
2953         if (!(ugeth->p_init_enet_param_shadow =
2954               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2955                 if (netif_msg_ifup(ugeth))
2956                         pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
2957                 return -ENOMEM;
2958         }
2959         /* Zero out *p_init_enet_param_shadow */
2960         memset((char *)ugeth->p_init_enet_param_shadow,
2961                0, sizeof(struct ucc_geth_init_pram));
2962
2963         /* Fill shadow InitEnet command parameter structure */
2964
2965         ugeth->p_init_enet_param_shadow->resinit1 =
2966             ENET_INIT_PARAM_MAGIC_RES_INIT1;
2967         ugeth->p_init_enet_param_shadow->resinit2 =
2968             ENET_INIT_PARAM_MAGIC_RES_INIT2;
2969         ugeth->p_init_enet_param_shadow->resinit3 =
2970             ENET_INIT_PARAM_MAGIC_RES_INIT3;
2971         ugeth->p_init_enet_param_shadow->resinit4 =
2972             ENET_INIT_PARAM_MAGIC_RES_INIT4;
2973         ugeth->p_init_enet_param_shadow->resinit5 =
2974             ENET_INIT_PARAM_MAGIC_RES_INIT5;
2975         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2976             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2977         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2978             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2979
2980         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2981             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2982         if ((ug_info->largestexternallookupkeysize !=
2983              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2984             (ug_info->largestexternallookupkeysize !=
2985              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2986             (ug_info->largestexternallookupkeysize !=
2987              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2988                 if (netif_msg_ifup(ugeth))
2989                         pr_err("Invalid largest External Lookup Key Size\n");
2990                 return -EINVAL;
2991         }
2992         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2993             ug_info->largestexternallookupkeysize;
2994         size = sizeof(struct ucc_geth_thread_rx_pram);
2995         if (ug_info->rxExtendedFiltering) {
2996                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2997                 if (ug_info->largestexternallookupkeysize ==
2998                     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2999                         size +=
3000                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3001                 if (ug_info->largestexternallookupkeysize ==
3002                     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3003                         size +=
3004                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3005         }
3006
3007         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3008                 p_init_enet_param_shadow->rxthread[0]),
3009                 (u8) (numThreadsRxNumerical + 1)
3010                 /* Rx needs one extra for terminator */
3011                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3012                 ug_info->riscRx, 1)) != 0) {
3013                 if (netif_msg_ifup(ugeth))
3014                         pr_err("Can not fill p_init_enet_param_shadow\n");
3015                 return ret_val;
3016         }
3017
3018         ugeth->p_init_enet_param_shadow->txglobal =
3019             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3020         if ((ret_val =
3021              fill_init_enet_entries(ugeth,
3022                                     &(ugeth->p_init_enet_param_shadow->
3023                                       txthread[0]), numThreadsTxNumerical,
3024                                     sizeof(struct ucc_geth_thread_tx_pram),
3025                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3026                                     ug_info->riscTx, 0)) != 0) {
3027                 if (netif_msg_ifup(ugeth))
3028                         pr_err("Can not fill p_init_enet_param_shadow\n");
3029                 return ret_val;
3030         }
3031
3032         /* Load Rx bds with buffers */
3033         for (i = 0; i < ug_info->numQueuesRx; i++) {
3034                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3035                         if (netif_msg_ifup(ugeth))
3036                                 pr_err("Can not fill Rx bds with buffers\n");
3037                         return ret_val;
3038                 }
3039         }
3040
3041         /* Allocate InitEnet command parameter structure */
3042         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3043         if (IS_ERR_VALUE(init_enet_pram_offset)) {
3044                 if (netif_msg_ifup(ugeth))
3045                         pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
3046                 return -ENOMEM;
3047         }
3048         p_init_enet_pram =
3049             (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3050
3051         /* Copy shadow InitEnet command parameter structure into PRAM */
3052         out_8(&p_init_enet_pram->resinit1,
3053                         ugeth->p_init_enet_param_shadow->resinit1);
3054         out_8(&p_init_enet_pram->resinit2,
3055                         ugeth->p_init_enet_param_shadow->resinit2);
3056         out_8(&p_init_enet_pram->resinit3,
3057                         ugeth->p_init_enet_param_shadow->resinit3);
3058         out_8(&p_init_enet_pram->resinit4,
3059                         ugeth->p_init_enet_param_shadow->resinit4);
3060         out_be16(&p_init_enet_pram->resinit5,
3061                  ugeth->p_init_enet_param_shadow->resinit5);
3062         out_8(&p_init_enet_pram->largestexternallookupkeysize,
3063             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3064         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3065                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3066         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3067                 out_be32(&p_init_enet_pram->rxthread[i],
3068                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3069         out_be32(&p_init_enet_pram->txglobal,
3070                  ugeth->p_init_enet_param_shadow->txglobal);
3071         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3072                 out_be32(&p_init_enet_pram->txthread[i],
3073                          ugeth->p_init_enet_param_shadow->txthread[i]);
3074
3075         /* Issue QE command */
3076         cecr_subblock =
3077             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3078         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3079                      init_enet_pram_offset);
3080
3081         /* Free InitEnet command parameter */
3082         qe_muram_free(init_enet_pram_offset);
3083
3084         return 0;
3085 }
3086
3087 /* This is called by the kernel when a frame is ready for transmission. */
3088 /* It is pointed to by the dev->hard_start_xmit function pointer */
3089 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3090 {
3091         struct ucc_geth_private *ugeth = netdev_priv(dev);
3092 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3093         struct ucc_fast_private *uccf;
3094 #endif
3095         u8 __iomem *bd;                 /* BD pointer */
3096         u32 bd_status;
3097         u8 txQ = 0;
3098         unsigned long flags;
3099
3100         ugeth_vdbg("%s: IN", __func__);
3101
3102         spin_lock_irqsave(&ugeth->lock, flags);
3103
3104         dev->stats.tx_bytes += skb->len;
3105
3106         /* Start from the next BD that should be filled */
3107         bd = ugeth->txBd[txQ];
3108         bd_status = in_be32((u32 __iomem *)bd);
3109         /* Save the skb pointer so we can free it later */
3110         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3111
3112         /* Update the current skb pointer (wrapping if this was the last) */
3113         ugeth->skb_curtx[txQ] =
3114             (ugeth->skb_curtx[txQ] +
3115              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3116
3117         /* set up the buffer descriptor */
3118         out_be32(&((struct qe_bd __iomem *)bd)->buf,
3119                       dma_map_single(ugeth->dev, skb->data,
3120                               skb->len, DMA_TO_DEVICE));
3121
3122         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3123
3124         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3125
3126         /* set bd status and length */
3127         out_be32((u32 __iomem *)bd, bd_status);
3128
3129         /* Move to next BD in the ring */
3130         if (!(bd_status & T_W))
3131                 bd += sizeof(struct qe_bd);
3132         else
3133                 bd = ugeth->p_tx_bd_ring[txQ];
3134
3135         /* If the next BD still needs to be cleaned up, then the bds
3136            are full.  We need to tell the kernel to stop sending us stuff. */
3137         if (bd == ugeth->confBd[txQ]) {
3138                 if (!netif_queue_stopped(dev))
3139                         netif_stop_queue(dev);
3140         }
3141
3142         ugeth->txBd[txQ] = bd;
3143
3144         skb_tx_timestamp(skb);
3145
3146         if (ugeth->p_scheduler) {
3147                 ugeth->cpucount[txQ]++;
3148                 /* Indicate to QE that there are more Tx bds ready for
3149                 transmission */
3150                 /* This is done by writing a running counter of the bd
3151                 count to the scheduler PRAM. */
3152                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3153         }
3154
3155 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3156         uccf = ugeth->uccf;
3157         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3158 #endif
3159         spin_unlock_irqrestore(&ugeth->lock, flags);
3160
3161         return NETDEV_TX_OK;
3162 }
3163
3164 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3165 {
3166         struct sk_buff *skb;
3167         u8 __iomem *bd;
3168         u16 length, howmany = 0;
3169         u32 bd_status;
3170         u8 *bdBuffer;
3171         struct net_device *dev;
3172
3173         ugeth_vdbg("%s: IN", __func__);
3174
3175         dev = ugeth->ndev;
3176
3177         /* collect received buffers */
3178         bd = ugeth->rxBd[rxQ];
3179
3180         bd_status = in_be32((u32 __iomem *)bd);
3181
3182         /* while there are received buffers and BD is full (~R_E) */
3183         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3184                 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3185                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3186                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3187
3188                 /* determine whether buffer is first, last, first and last
3189                 (single buffer frame) or middle (not first and not last) */
3190                 if (!skb ||
3191                     (!(bd_status & (R_F | R_L))) ||
3192                     (bd_status & R_ERRORS_FATAL)) {
3193                         if (netif_msg_rx_err(ugeth))
3194                                 pr_err("%d: ERROR!!! skb - 0x%08x\n",
3195                                        __LINE__, (u32)skb);
3196                         dev_kfree_skb(skb);
3197
3198                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3199                         dev->stats.rx_dropped++;
3200                 } else {
3201                         dev->stats.rx_packets++;
3202                         howmany++;
3203
3204                         /* Prep the skb for the packet */
3205                         skb_put(skb, length);
3206
3207                         /* Tell the skb what kind of packet this is */
3208                         skb->protocol = eth_type_trans(skb, ugeth->ndev);
3209
3210                         dev->stats.rx_bytes += length;
3211                         /* Send the packet up the stack */
3212                         netif_receive_skb(skb);
3213                 }
3214
3215                 skb = get_new_skb(ugeth, bd);
3216                 if (!skb) {
3217                         if (netif_msg_rx_err(ugeth))
3218                                 pr_warn("No Rx Data Buffer\n");
3219                         dev->stats.rx_dropped++;
3220                         break;
3221                 }
3222
3223                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3224
3225                 /* update to point at the next skb */
3226                 ugeth->skb_currx[rxQ] =
3227                     (ugeth->skb_currx[rxQ] +
3228                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3229
3230                 if (bd_status & R_W)
3231                         bd = ugeth->p_rx_bd_ring[rxQ];
3232                 else
3233                         bd += sizeof(struct qe_bd);
3234
3235                 bd_status = in_be32((u32 __iomem *)bd);
3236         }
3237
3238         ugeth->rxBd[rxQ] = bd;
3239         return howmany;
3240 }
3241
3242 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3243 {
3244         /* Start from the next BD that should be filled */
3245         struct ucc_geth_private *ugeth = netdev_priv(dev);
3246         u8 __iomem *bd;         /* BD pointer */
3247         u32 bd_status;
3248
3249         bd = ugeth->confBd[txQ];
3250         bd_status = in_be32((u32 __iomem *)bd);
3251
3252         /* Normal processing. */
3253         while ((bd_status & T_R) == 0) {
3254                 struct sk_buff *skb;
3255
3256                 /* BD contains already transmitted buffer.   */
3257                 /* Handle the transmitted buffer and release */
3258                 /* the BD to be used with the current frame  */
3259
3260                 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3261                 if (!skb)
3262                         break;
3263
3264                 dev->stats.tx_packets++;
3265
3266                 dev_consume_skb_any(skb);
3267
3268                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3269                 ugeth->skb_dirtytx[txQ] =
3270                     (ugeth->skb_dirtytx[txQ] +
3271                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3272
3273                 /* We freed a buffer, so now we can restart transmission */
3274                 if (netif_queue_stopped(dev))
3275                         netif_wake_queue(dev);
3276
3277                 /* Advance the confirmation BD pointer */
3278                 if (!(bd_status & T_W))
3279                         bd += sizeof(struct qe_bd);
3280                 else
3281                         bd = ugeth->p_tx_bd_ring[txQ];
3282                 bd_status = in_be32((u32 __iomem *)bd);
3283         }
3284         ugeth->confBd[txQ] = bd;
3285         return 0;
3286 }
3287
3288 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3289 {
3290         struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3291         struct ucc_geth_info *ug_info;
3292         int howmany, i;
3293
3294         ug_info = ugeth->ug_info;
3295
3296         /* Tx event processing */
3297         spin_lock(&ugeth->lock);
3298         for (i = 0; i < ug_info->numQueuesTx; i++)
3299                 ucc_geth_tx(ugeth->ndev, i);
3300         spin_unlock(&ugeth->lock);
3301
3302         howmany = 0;
3303         for (i = 0; i < ug_info->numQueuesRx; i++)
3304                 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3305
3306         if (howmany < budget) {
3307                 napi_complete(napi);
3308                 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3309         }
3310
3311         return howmany;
3312 }
3313
3314 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3315 {
3316         struct net_device *dev = info;
3317         struct ucc_geth_private *ugeth = netdev_priv(dev);
3318         struct ucc_fast_private *uccf;
3319         struct ucc_geth_info *ug_info;
3320         register u32 ucce;
3321         register u32 uccm;
3322
3323         ugeth_vdbg("%s: IN", __func__);
3324
3325         uccf = ugeth->uccf;
3326         ug_info = ugeth->ug_info;
3327
3328         /* read and clear events */
3329         ucce = (u32) in_be32(uccf->p_ucce);
3330         uccm = (u32) in_be32(uccf->p_uccm);
3331         ucce &= uccm;
3332         out_be32(uccf->p_ucce, ucce);
3333
3334         /* check for receive events that require processing */
3335         if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3336                 if (napi_schedule_prep(&ugeth->napi)) {
3337                         uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3338                         out_be32(uccf->p_uccm, uccm);
3339                         __napi_schedule(&ugeth->napi);
3340                 }
3341         }
3342
3343         /* Errors and other events */
3344         if (ucce & UCCE_OTHER) {
3345                 if (ucce & UCC_GETH_UCCE_BSY)
3346                         dev->stats.rx_errors++;
3347                 if (ucce & UCC_GETH_UCCE_TXE)
3348                         dev->stats.tx_errors++;
3349         }
3350
3351         return IRQ_HANDLED;
3352 }
3353
3354 #ifdef CONFIG_NET_POLL_CONTROLLER
3355 /*
3356  * Polling 'interrupt' - used by things like netconsole to send skbs
3357  * without having to re-enable interrupts. It's not called while
3358  * the interrupt routine is executing.
3359  */
3360 static void ucc_netpoll(struct net_device *dev)
3361 {
3362         struct ucc_geth_private *ugeth = netdev_priv(dev);
3363         int irq = ugeth->ug_info->uf_info.irq;
3364
3365         disable_irq(irq);
3366         ucc_geth_irq_handler(irq, dev);
3367         enable_irq(irq);
3368 }
3369 #endif /* CONFIG_NET_POLL_CONTROLLER */
3370
3371 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3372 {
3373         struct ucc_geth_private *ugeth = netdev_priv(dev);
3374         struct sockaddr *addr = p;
3375
3376         if (!is_valid_ether_addr(addr->sa_data))
3377                 return -EADDRNOTAVAIL;
3378
3379         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3380
3381         /*
3382          * If device is not running, we will set mac addr register
3383          * when opening the device.
3384          */
3385         if (!netif_running(dev))
3386                 return 0;
3387
3388         spin_lock_irq(&ugeth->lock);
3389         init_mac_station_addr_regs(dev->dev_addr[0],
3390                                    dev->dev_addr[1],
3391                                    dev->dev_addr[2],
3392                                    dev->dev_addr[3],
3393                                    dev->dev_addr[4],
3394                                    dev->dev_addr[5],
3395                                    &ugeth->ug_regs->macstnaddr1,
3396                                    &ugeth->ug_regs->macstnaddr2);
3397         spin_unlock_irq(&ugeth->lock);
3398
3399         return 0;
3400 }
3401
3402 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3403 {
3404         struct net_device *dev = ugeth->ndev;
3405         int err;
3406
3407         err = ucc_struct_init(ugeth);
3408         if (err) {
3409                 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
3410                 goto err;
3411         }
3412
3413         err = ucc_geth_startup(ugeth);
3414         if (err) {
3415                 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3416                 goto err;
3417         }
3418
3419         err = adjust_enet_interface(ugeth);
3420         if (err) {
3421                 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3422                 goto err;
3423         }
3424
3425         /*       Set MACSTNADDR1, MACSTNADDR2                */
3426         /* For more details see the hardware spec.           */
3427         init_mac_station_addr_regs(dev->dev_addr[0],
3428                                    dev->dev_addr[1],
3429                                    dev->dev_addr[2],
3430                                    dev->dev_addr[3],
3431                                    dev->dev_addr[4],
3432                                    dev->dev_addr[5],
3433                                    &ugeth->ug_regs->macstnaddr1,
3434                                    &ugeth->ug_regs->macstnaddr2);
3435
3436         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3437         if (err) {
3438                 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
3439                 goto err;
3440         }
3441
3442         return 0;
3443 err:
3444         ucc_geth_stop(ugeth);
3445         return err;
3446 }
3447
3448 /* Called when something needs to use the ethernet device */
3449 /* Returns 0 for success. */
3450 static int ucc_geth_open(struct net_device *dev)
3451 {
3452         struct ucc_geth_private *ugeth = netdev_priv(dev);
3453         int err;
3454
3455         ugeth_vdbg("%s: IN", __func__);
3456
3457         /* Test station address */
3458         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3459                 netif_err(ugeth, ifup, dev,
3460                           "Multicast address used for station address - is this what you wanted?\n");
3461                 return -EINVAL;
3462         }
3463
3464         err = init_phy(dev);
3465         if (err) {
3466                 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
3467                 return err;
3468         }
3469
3470         err = ucc_geth_init_mac(ugeth);
3471         if (err) {
3472                 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
3473                 goto err;
3474         }
3475
3476         err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3477                           0, "UCC Geth", dev);
3478         if (err) {
3479                 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
3480                 goto err;
3481         }
3482
3483         phy_start(ugeth->phydev);
3484         napi_enable(&ugeth->napi);
3485         netif_start_queue(dev);
3486
3487         device_set_wakeup_capable(&dev->dev,
3488                         qe_alive_during_sleep() || ugeth->phydev->irq);
3489         device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3490
3491         return err;
3492
3493 err:
3494         ucc_geth_stop(ugeth);
3495         return err;
3496 }
3497
3498 /* Stops the kernel queue, and halts the controller */
3499 static int ucc_geth_close(struct net_device *dev)
3500 {
3501         struct ucc_geth_private *ugeth = netdev_priv(dev);
3502
3503         ugeth_vdbg("%s: IN", __func__);
3504
3505         napi_disable(&ugeth->napi);
3506
3507         cancel_work_sync(&ugeth->timeout_work);
3508         ucc_geth_stop(ugeth);
3509         phy_disconnect(ugeth->phydev);
3510         ugeth->phydev = NULL;
3511
3512         free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3513
3514         netif_stop_queue(dev);
3515
3516         return 0;
3517 }
3518
3519 /* Reopen device. This will reset the MAC and PHY. */
3520 static void ucc_geth_timeout_work(struct work_struct *work)
3521 {
3522         struct ucc_geth_private *ugeth;
3523         struct net_device *dev;
3524
3525         ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3526         dev = ugeth->ndev;
3527
3528         ugeth_vdbg("%s: IN", __func__);
3529
3530         dev->stats.tx_errors++;
3531
3532         ugeth_dump_regs(ugeth);
3533
3534         if (dev->flags & IFF_UP) {
3535                 /*
3536                  * Must reset MAC *and* PHY. This is done by reopening
3537                  * the device.
3538                  */
3539                 netif_tx_stop_all_queues(dev);
3540                 ucc_geth_stop(ugeth);
3541                 ucc_geth_init_mac(ugeth);
3542                 /* Must start PHY here */
3543                 phy_start(ugeth->phydev);
3544                 netif_tx_start_all_queues(dev);
3545         }
3546
3547         netif_tx_schedule_all(dev);
3548 }
3549
3550 /*
3551  * ucc_geth_timeout gets called when a packet has not been
3552  * transmitted after a set amount of time.
3553  */
3554 static void ucc_geth_timeout(struct net_device *dev)
3555 {
3556         struct ucc_geth_private *ugeth = netdev_priv(dev);
3557
3558         schedule_work(&ugeth->timeout_work);
3559 }
3560
3561
3562 #ifdef CONFIG_PM
3563
3564 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
3565 {
3566         struct net_device *ndev = platform_get_drvdata(ofdev);
3567         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3568
3569         if (!netif_running(ndev))
3570                 return 0;
3571
3572         netif_device_detach(ndev);
3573         napi_disable(&ugeth->napi);
3574
3575         /*
3576          * Disable the controller, otherwise we'll wakeup on any network
3577          * activity.
3578          */
3579         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3580
3581         if (ugeth->wol_en & WAKE_MAGIC) {
3582                 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3583                 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3584                 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3585         } else if (!(ugeth->wol_en & WAKE_PHY)) {
3586                 phy_stop(ugeth->phydev);
3587         }
3588
3589         return 0;
3590 }
3591
3592 static int ucc_geth_resume(struct platform_device *ofdev)
3593 {
3594         struct net_device *ndev = platform_get_drvdata(ofdev);
3595         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3596         int err;
3597
3598         if (!netif_running(ndev))
3599                 return 0;
3600
3601         if (qe_alive_during_sleep()) {
3602                 if (ugeth->wol_en & WAKE_MAGIC) {
3603                         ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3604                         clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3605                         clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3606                 }
3607                 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3608         } else {
3609                 /*
3610                  * Full reinitialization is required if QE shuts down
3611                  * during sleep.
3612                  */
3613                 ucc_geth_memclean(ugeth);
3614
3615                 err = ucc_geth_init_mac(ugeth);
3616                 if (err) {
3617                         netdev_err(ndev, "Cannot initialize MAC, aborting\n");
3618                         return err;
3619                 }
3620         }
3621
3622         ugeth->oldlink = 0;
3623         ugeth->oldspeed = 0;
3624         ugeth->oldduplex = -1;
3625
3626         phy_stop(ugeth->phydev);
3627         phy_start(ugeth->phydev);
3628
3629         napi_enable(&ugeth->napi);
3630         netif_device_attach(ndev);
3631
3632         return 0;
3633 }
3634
3635 #else
3636 #define ucc_geth_suspend NULL
3637 #define ucc_geth_resume NULL
3638 #endif
3639
3640 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3641 {
3642         if (strcasecmp(phy_connection_type, "mii") == 0)
3643                 return PHY_INTERFACE_MODE_MII;
3644         if (strcasecmp(phy_connection_type, "gmii") == 0)
3645                 return PHY_INTERFACE_MODE_GMII;
3646         if (strcasecmp(phy_connection_type, "tbi") == 0)
3647                 return PHY_INTERFACE_MODE_TBI;
3648         if (strcasecmp(phy_connection_type, "rmii") == 0)
3649                 return PHY_INTERFACE_MODE_RMII;
3650         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3651                 return PHY_INTERFACE_MODE_RGMII;
3652         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3653                 return PHY_INTERFACE_MODE_RGMII_ID;
3654         if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3655                 return PHY_INTERFACE_MODE_RGMII_TXID;
3656         if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3657                 return PHY_INTERFACE_MODE_RGMII_RXID;
3658         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3659                 return PHY_INTERFACE_MODE_RTBI;
3660         if (strcasecmp(phy_connection_type, "sgmii") == 0)
3661                 return PHY_INTERFACE_MODE_SGMII;
3662
3663         return PHY_INTERFACE_MODE_MII;
3664 }
3665
3666 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3667 {
3668         struct ucc_geth_private *ugeth = netdev_priv(dev);
3669
3670         if (!netif_running(dev))
3671                 return -EINVAL;
3672
3673         if (!ugeth->phydev)
3674                 return -ENODEV;
3675
3676         return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3677 }
3678
3679 static const struct net_device_ops ucc_geth_netdev_ops = {
3680         .ndo_open               = ucc_geth_open,
3681         .ndo_stop               = ucc_geth_close,
3682         .ndo_start_xmit         = ucc_geth_start_xmit,
3683         .ndo_validate_addr      = eth_validate_addr,
3684         .ndo_set_mac_address    = ucc_geth_set_mac_addr,
3685         .ndo_change_mtu         = eth_change_mtu,
3686         .ndo_set_rx_mode        = ucc_geth_set_multi,
3687         .ndo_tx_timeout         = ucc_geth_timeout,
3688         .ndo_do_ioctl           = ucc_geth_ioctl,
3689 #ifdef CONFIG_NET_POLL_CONTROLLER
3690         .ndo_poll_controller    = ucc_netpoll,
3691 #endif
3692 };
3693
3694 static int ucc_geth_probe(struct platform_device* ofdev)
3695 {
3696         struct device *device = &ofdev->dev;
3697         struct device_node *np = ofdev->dev.of_node;
3698         struct net_device *dev = NULL;
3699         struct ucc_geth_private *ugeth = NULL;
3700         struct ucc_geth_info *ug_info;
3701         struct resource res;
3702         int err, ucc_num, max_speed = 0;
3703         const unsigned int *prop;
3704         const char *sprop;
3705         const void *mac_addr;
3706         phy_interface_t phy_interface;
3707         static const int enet_to_speed[] = {
3708                 SPEED_10, SPEED_10, SPEED_10,
3709                 SPEED_100, SPEED_100, SPEED_100,
3710                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3711         };
3712         static const phy_interface_t enet_to_phy_interface[] = {
3713                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3714                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3715                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3716                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3717                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3718                 PHY_INTERFACE_MODE_SGMII,
3719         };
3720
3721         ugeth_vdbg("%s: IN", __func__);
3722
3723         prop = of_get_property(np, "cell-index", NULL);
3724         if (!prop) {
3725                 prop = of_get_property(np, "device-id", NULL);
3726                 if (!prop)
3727                         return -ENODEV;
3728         }
3729
3730         ucc_num = *prop - 1;
3731         if ((ucc_num < 0) || (ucc_num > 7))
3732                 return -ENODEV;
3733
3734         ug_info = &ugeth_info[ucc_num];
3735         if (ug_info == NULL) {
3736                 if (netif_msg_probe(&debug))
3737                         pr_err("[%d] Missing additional data!\n", ucc_num);
3738                 return -ENODEV;
3739         }
3740
3741         ug_info->uf_info.ucc_num = ucc_num;
3742
3743         sprop = of_get_property(np, "rx-clock-name", NULL);
3744         if (sprop) {
3745                 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3746                 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3747                     (ug_info->uf_info.rx_clock > QE_CLK24)) {
3748                         pr_err("invalid rx-clock-name property\n");
3749                         return -EINVAL;
3750                 }
3751         } else {
3752                 prop = of_get_property(np, "rx-clock", NULL);
3753                 if (!prop) {
3754                         /* If both rx-clock-name and rx-clock are missing,
3755                            we want to tell people to use rx-clock-name. */
3756                         pr_err("missing rx-clock-name property\n");
3757                         return -EINVAL;
3758                 }
3759                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3760                         pr_err("invalid rx-clock property\n");
3761                         return -EINVAL;
3762                 }
3763                 ug_info->uf_info.rx_clock = *prop;
3764         }
3765
3766         sprop = of_get_property(np, "tx-clock-name", NULL);
3767         if (sprop) {
3768                 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3769                 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3770                     (ug_info->uf_info.tx_clock > QE_CLK24)) {
3771                         pr_err("invalid tx-clock-name property\n");
3772                         return -EINVAL;
3773                 }
3774         } else {
3775                 prop = of_get_property(np, "tx-clock", NULL);
3776                 if (!prop) {
3777                         pr_err("missing tx-clock-name property\n");
3778                         return -EINVAL;
3779                 }
3780                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3781                         pr_err("invalid tx-clock property\n");
3782                         return -EINVAL;
3783                 }
3784                 ug_info->uf_info.tx_clock = *prop;
3785         }
3786
3787         err = of_address_to_resource(np, 0, &res);
3788         if (err)
3789                 return -EINVAL;
3790
3791         ug_info->uf_info.regs = res.start;
3792         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3793
3794         ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3795         if (!ug_info->phy_node && of_phy_is_fixed_link(np)) {
3796                 /*
3797                  * In the case of a fixed PHY, the DT node associated
3798                  * to the PHY is the Ethernet MAC DT node.
3799                  */
3800                 err = of_phy_register_fixed_link(np);
3801                 if (err)
3802                         return err;
3803                 ug_info->phy_node = of_node_get(np);
3804         }
3805
3806         /* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3807         ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3808
3809         /* get the phy interface type, or default to MII */
3810         prop = of_get_property(np, "phy-connection-type", NULL);
3811         if (!prop) {
3812                 /* handle interface property present in old trees */
3813                 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3814                 if (prop != NULL) {
3815                         phy_interface = enet_to_phy_interface[*prop];
3816                         max_speed = enet_to_speed[*prop];
3817                 } else
3818                         phy_interface = PHY_INTERFACE_MODE_MII;
3819         } else {
3820                 phy_interface = to_phy_interface((const char *)prop);
3821         }
3822
3823         /* get speed, or derive from PHY interface */
3824         if (max_speed == 0)
3825                 switch (phy_interface) {
3826                 case PHY_INTERFACE_MODE_GMII:
3827                 case PHY_INTERFACE_MODE_RGMII:
3828                 case PHY_INTERFACE_MODE_RGMII_ID:
3829                 case PHY_INTERFACE_MODE_RGMII_RXID:
3830                 case PHY_INTERFACE_MODE_RGMII_TXID:
3831                 case PHY_INTERFACE_MODE_TBI:
3832                 case PHY_INTERFACE_MODE_RTBI:
3833                 case PHY_INTERFACE_MODE_SGMII:
3834                         max_speed = SPEED_1000;
3835                         break;
3836                 default:
3837                         max_speed = SPEED_100;
3838                         break;
3839                 }
3840
3841         if (max_speed == SPEED_1000) {
3842                 unsigned int snums = qe_get_num_of_snums();
3843
3844                 /* configure muram FIFOs for gigabit operation */
3845                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3846                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3847                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3848                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3849                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3850                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3851                 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3852
3853                 /* If QE's snum number is 46/76 which means we need to support
3854                  * 4 UECs at 1000Base-T simultaneously, we need to allocate
3855                  * more Threads to Rx.
3856                  */
3857                 if ((snums == 76) || (snums == 46))
3858                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3859                 else
3860                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3861         }
3862
3863         if (netif_msg_probe(&debug))
3864                 pr_info("UCC%1d at 0x%8x (irq = %d)\n",
3865                         ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3866                         ug_info->uf_info.irq);
3867
3868         /* Create an ethernet device instance */
3869         dev = alloc_etherdev(sizeof(*ugeth));
3870
3871         if (dev == NULL) {
3872                 err = -ENOMEM;
3873                 goto err_deregister_fixed_link;
3874         }
3875
3876         ugeth = netdev_priv(dev);
3877         spin_lock_init(&ugeth->lock);
3878
3879         /* Create CQs for hash tables */
3880         INIT_LIST_HEAD(&ugeth->group_hash_q);
3881         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3882
3883         dev_set_drvdata(device, dev);
3884
3885         /* Set the dev->base_addr to the gfar reg region */
3886         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3887
3888         SET_NETDEV_DEV(dev, device);
3889
3890         /* Fill in the dev structure */
3891         uec_set_ethtool_ops(dev);
3892         dev->netdev_ops = &ucc_geth_netdev_ops;
3893         dev->watchdog_timeo = TX_TIMEOUT;
3894         INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3895         netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3896         dev->mtu = 1500;
3897
3898         ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3899         ugeth->phy_interface = phy_interface;
3900         ugeth->max_speed = max_speed;
3901
3902         /* Carrier starts down, phylib will bring it up */
3903         netif_carrier_off(dev);
3904
3905         err = register_netdev(dev);
3906         if (err) {
3907                 if (netif_msg_probe(ugeth))
3908                         pr_err("%s: Cannot register net device, aborting\n",
3909                                dev->name);
3910                 goto err_free_netdev;
3911         }
3912
3913         mac_addr = of_get_mac_address(np);
3914         if (mac_addr)
3915                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
3916
3917         ugeth->ug_info = ug_info;
3918         ugeth->dev = device;
3919         ugeth->ndev = dev;
3920         ugeth->node = np;
3921
3922         return 0;
3923
3924 err_free_netdev:
3925         free_netdev(dev);
3926 err_deregister_fixed_link:
3927         if (of_phy_is_fixed_link(np))
3928                 of_phy_deregister_fixed_link(np);
3929         of_node_put(ug_info->tbi_node);
3930         of_node_put(ug_info->phy_node);
3931
3932         return err;
3933 }
3934
3935 static int ucc_geth_remove(struct platform_device* ofdev)
3936 {
3937         struct net_device *dev = platform_get_drvdata(ofdev);
3938         struct ucc_geth_private *ugeth = netdev_priv(dev);
3939         struct device_node *np = ofdev->dev.of_node;
3940
3941         unregister_netdev(dev);
3942         ucc_geth_memclean(ugeth);
3943         if (of_phy_is_fixed_link(np))
3944                 of_phy_deregister_fixed_link(np);
3945         of_node_put(ugeth->ug_info->tbi_node);
3946         of_node_put(ugeth->ug_info->phy_node);
3947         free_netdev(dev);
3948
3949         return 0;
3950 }
3951
3952 static const struct of_device_id ucc_geth_match[] = {
3953         {
3954                 .type = "network",
3955                 .compatible = "ucc_geth",
3956         },
3957         {},
3958 };
3959
3960 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3961
3962 static struct platform_driver ucc_geth_driver = {
3963         .driver = {
3964                 .name = DRV_NAME,
3965                 .of_match_table = ucc_geth_match,
3966         },
3967         .probe          = ucc_geth_probe,
3968         .remove         = ucc_geth_remove,
3969         .suspend        = ucc_geth_suspend,
3970         .resume         = ucc_geth_resume,
3971 };
3972
3973 static int __init ucc_geth_init(void)
3974 {
3975         int i, ret;
3976
3977         if (netif_msg_drv(&debug))
3978                 pr_info(DRV_DESC "\n");
3979         for (i = 0; i < 8; i++)
3980                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3981                        sizeof(ugeth_primary_info));
3982
3983         ret = platform_driver_register(&ucc_geth_driver);
3984
3985         return ret;
3986 }
3987
3988 static void __exit ucc_geth_exit(void)
3989 {
3990         platform_driver_unregister(&ucc_geth_driver);
3991 }
3992
3993 module_init(ucc_geth_init);
3994 module_exit(ucc_geth_exit);
3995
3996 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3997 MODULE_DESCRIPTION(DRV_DESC);
3998 MODULE_VERSION(DRV_VERSION);
3999 MODULE_LICENSE("GPL");