drivers/net/ethernet/freescale/ucc_geth.h

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *
   6  * Description:
   7  * Internal header file for UCC Gigabit Ethernet unit routines.
   8  *
   9  * Changelog:
  10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11  * - Rearrange code and style fixes
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18 #ifndef __UCC_GETH_H__
  19 #define __UCC_GETH_H__
  20
  21 #include <linux/kernel.h>
  22 #include <linux/list.h>
  23 #include <linux/if_ether.h>
  24
  25 #include <asm/immap_qe.h>
  26 #include <asm/qe.h>
  27
  28 #include <asm/ucc.h>
  29 #include <asm/ucc_fast.h>
  30
  31 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
  32 #define DRV_NAME "ucc_geth"
  33 #define DRV_VERSION "1.1"
  34
  35 #define NUM_TX_QUEUES                   8
  36 #define NUM_RX_QUEUES                   8
  37 #define NUM_BDS_IN_PREFETCHED_BDS       4
  38 #define TX_IP_OFFSET_ENTRY_MAX          8
  39 #define NUM_OF_PADDRS                   4
  40 #define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
  41 #define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
  42
  43 struct ucc_geth {
  44         struct ucc_fast uccf;
  45         u8 res0[0x100 - sizeof(struct ucc_fast)];
  46
  47         u32 maccfg1;            /* mac configuration reg. 1 */
  48         u32 maccfg2;            /* mac configuration reg. 2 */
  49         u32 ipgifg;             /* interframe gap reg.  */
  50         u32 hafdup;             /* half-duplex reg.  */
  51         u8 res1[0x10];
  52         u8 miimng[0x18];        /* MII management structure moved to _mii.h */
  53         u32 ifctl;              /* interface control reg */
  54         u32 ifstat;             /* interface statux reg */
  55         u32 macstnaddr1;        /* mac station address part 1 reg */
  56         u32 macstnaddr2;        /* mac station address part 2 reg */
  57         u8 res2[0x8];
  58         u32 uempr;              /* UCC Ethernet Mac parameter reg */
  59         u32 utbipar;            /* UCC tbi address reg */
  60         u16 uescr;              /* UCC Ethernet statistics control reg */
  61         u8 res3[0x180 - 0x15A];
  62         u32 tx64;               /* Total number of frames (including bad
  63                                    frames) transmitted that were exactly of the
  64                                    minimal length (64 for un tagged, 68 for
  65                                    tagged, or with length exactly equal to the
  66                                    parameter MINLength */
  67         u32 tx127;              /* Total number of frames (including bad
  68                                    frames) transmitted that were between
  69                                    MINLength (Including FCS length==4) and 127
  70                                    octets */
  71         u32 tx255;              /* Total number of frames (including bad
  72                                    frames) transmitted that were between 128
  73                                    (Including FCS length==4) and 255 octets */
  74         u32 rx64;               /* Total number of frames received including
  75                                    bad frames that were exactly of the mninimal
  76                                    length (64 bytes) */
  77         u32 rx127;              /* Total number of frames (including bad
  78                                    frames) received that were between MINLength
  79                                    (Including FCS length==4) and 127 octets */
  80         u32 rx255;              /* Total number of frames (including bad
  81                                    frames) received that were between 128
  82                                    (Including FCS length==4) and 255 octets */
  83         u32 txok;               /* Total number of octets residing in frames
  84                                    that where involved in successful
  85                                    transmission */
  86         u16 txcf;               /* Total number of PAUSE control frames
  87                                    transmitted by this MAC */
  88         u8 res4[0x2];
  89         u32 tmca;               /* Total number of frames that were transmitted
  90                                    successfully with the group address bit set
  91                                    that are not broadcast frames */
  92         u32 tbca;               /* Total number of frames transmitted
  93                                    successfully that had destination address
  94                                    field equal to the broadcast address */
  95         u32 rxfok;              /* Total number of frames received OK */
  96         u32 rxbok;              /* Total number of octets received OK */
  97         u32 rbyt;               /* Total number of octets received including
  98                                    octets in bad frames. Must be implemented in
  99                                    HW because it includes octets in frames that
 100                                    never even reach the UCC */
 101         u32 rmca;               /* Total number of frames that were received
 102                                    successfully with the group address bit set
 103                                    that are not broadcast frames */
 104         u32 rbca;               /* Total number of frames received successfully
 105                                    that had destination address equal to the
 106                                    broadcast address */
 107         u32 scar;               /* Statistics carry register */
 108         u32 scam;               /* Statistics caryy mask register */
 109         u8 res5[0x200 - 0x1c4];
 110 } __packed;
 111
 112 /* UCC GETH TEMODR Register */
 113 #define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100  /* enable Tx statistics
 114                                                          */
 115 #define TEMODER_SCHEDULER_ENABLE                0x2000  /* enable scheduler */
 116 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400  /* generate IPv4
 117                                                            checksums */
 118 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200  /* enable performance
 119                                                            optimization
 120                                                            enhancement (mode1) */
 121 #define TEMODER_RMON_STATISTICS                 0x0100  /* enable tx statistics
 122                                                          */
 123 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15) /* Number of queues <<
 124                                                            shift */
 125
 126 /* UCC GETH TEMODR Register */
 127 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000      /* enable Rx
 128                                                                    statistics */
 129 #define REMODER_RX_EXTENDED_FEATURES            0x80000000      /* enable
 130                                                                    extended
 131                                                                    features */
 132 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 ) /* vlan operation
 133                                                            tagged << shift */
 134 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
 135                                                            tagged << shift */
 136 #define REMODER_RX_QOS_MODE_SHIFT               (31-15) /* rx QoS mode << shift
 137                                                          */
 138 #define REMODER_RMON_STATISTICS                 0x00001000      /* enable rx
 139                                                                    statistics */
 140 #define REMODER_RX_EXTENDED_FILTERING           0x00000800      /* extended
 141                                                                    filtering
 142                                                                    vs.
 143                                                                    mpc82xx-like
 144                                                                    filtering */
 145 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23) /* Number of queues <<
 146                                                            shift */
 147 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008      /* enable
 148                                                                    dynamic max
 149                                                                    frame length
 150                                                                  */
 151 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004      /* enable
 152                                                                    dynamic min
 153                                                                    frame length
 154                                                                  */
 155 #define REMODER_IP_CHECKSUM_CHECK               0x00000002      /* check IPv4
 156                                                                    checksums */
 157 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001      /* align ip
 158                                                                    address to
 159                                                                    4-byte
 160                                                                    boundary */
 161
 162 /* UCC GETH Event Register */
 163 #define UCCE_TXB   (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
 164                     UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
 165                     UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
 166                     UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
 167
 168 #define UCCE_RXB   (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
 169                     UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
 170                     UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
 171                     UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
 172
 173 #define UCCE_RXF   (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
 174                     UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
 175                     UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
 176                     UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
 177
 178 #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
 179                     UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
 180                     UCC_GETH_UCCE_RXC  | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
 181
 182 #define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
 183 #define UCCE_TX_EVENTS  (UCCE_TXB | UCC_GETH_UCCE_TXE)
 184
 185 /* TBI defines */
 186 #define ENET_TBI_MII_CR         0x00    /* Control */
 187 #define ENET_TBI_MII_SR         0x01    /* Status */
 188 #define ENET_TBI_MII_ANA        0x04    /* AN advertisement */
 189 #define ENET_TBI_MII_ANLPBPA    0x05    /* AN link partner base page ability */
 190 #define ENET_TBI_MII_ANEX       0x06    /* AN expansion */
 191 #define ENET_TBI_MII_ANNPT      0x07    /* AN next page transmit */
 192 #define ENET_TBI_MII_ANLPANP    0x08    /* AN link partner ability next page */
 193 #define ENET_TBI_MII_EXST       0x0F    /* Extended status */
 194 #define ENET_TBI_MII_JD         0x10    /* Jitter diagnostics */
 195 #define ENET_TBI_MII_TBICON     0x11    /* TBI control */
 196
 197 /* TBI MDIO register bit fields*/
 198 #define TBISR_LSTATUS          0x0004
 199 #define TBICON_CLK_SELECT       0x0020
 200 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
 201 #define TBIANA_SYMMETRIC_PAUSE  0x0080
 202 #define TBIANA_HALF_DUPLEX      0x0040
 203 #define TBIANA_FULL_DUPLEX      0x0020
 204 #define TBICR_PHY_RESET         0x8000
 205 #define TBICR_ANEG_ENABLE       0x1000
 206 #define TBICR_RESTART_ANEG      0x0200
 207 #define TBICR_FULL_DUPLEX       0x0100
 208 #define TBICR_SPEED1_SET        0x0040
 209
 210 #define TBIANA_SETTINGS ( \
 211                 TBIANA_ASYMMETRIC_PAUSE \
 212                 | TBIANA_SYMMETRIC_PAUSE \
 213                 | TBIANA_FULL_DUPLEX \
 214                 )
 215 #define TBICR_SETTINGS ( \
 216                 TBICR_PHY_RESET \
 217                 | TBICR_ANEG_ENABLE \
 218                 | TBICR_FULL_DUPLEX \
 219                 | TBICR_SPEED1_SET \
 220                 )
 221
 222 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
 223 #define MACCFG1_FLOW_RX                         0x00000020      /* Flow Control
 224                                                                    Rx */
 225 #define MACCFG1_FLOW_TX                         0x00000010      /* Flow Control
 226                                                                    Tx */
 227 #define MACCFG1_ENABLE_SYNCHED_RX               0x00000008      /* Rx Enable
 228                                                                    synchronized
 229                                                                    to Rx stream
 230                                                                  */
 231 #define MACCFG1_ENABLE_RX                       0x00000004      /* Enable Rx */
 232 #define MACCFG1_ENABLE_SYNCHED_TX               0x00000002      /* Tx Enable
 233                                                                    synchronized
 234                                                                    to Tx stream
 235                                                                  */
 236 #define MACCFG1_ENABLE_TX                       0x00000001      /* Enable Tx */
 237
 238 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
 239 #define MACCFG2_PREL_SHIFT                      (31 - 19)       /* Preamble
 240                                                                    Length <<
 241                                                                    shift */
 242 #define MACCFG2_PREL_MASK                       0x0000f000      /* Preamble
 243                                                                    Length mask */
 244 #define MACCFG2_SRP                             0x00000080      /* Soft Receive
 245                                                                    Preamble */
 246 #define MACCFG2_STP                             0x00000040      /* Soft
 247                                                                    Transmit
 248                                                                    Preamble */
 249 #define MACCFG2_RESERVED_1                      0x00000020      /* Reserved -
 250                                                                    must be set
 251                                                                    to 1 */
 252 #define MACCFG2_LC                              0x00000010      /* Length Check
 253                                                                  */
 254 #define MACCFG2_MPE                             0x00000008      /* Magic packet
 255                                                                    detect */
 256 #define MACCFG2_FDX                             0x00000001      /* Full Duplex */
 257 #define MACCFG2_FDX_MASK                        0x00000001      /* Full Duplex
 258                                                                    mask */
 259 #define MACCFG2_PAD_CRC                         0x00000004
 260 #define MACCFG2_CRC_EN                          0x00000002
 261 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000      /* Neither
 262                                                                    Padding
 263                                                                    short frames
 264                                                                    nor CRC */
 265 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002      /* Append CRC
 266                                                                    only */
 267 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
 268 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100      /* nibble mode
 269                                                                    (MII/RMII/RGMII
 270                                                                    10/100bps) */
 271 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200      /* byte mode
 272                                                                    (GMII/TBI/RTB/RGMII
 273                                                                    1000bps ) */
 274 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300      /* mask
 275                                                                    covering all
 276                                                                    relevant
 277                                                                    bits */
 278
 279 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
 280 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)       /* Non
 281                                                                    back-to-back
 282                                                                    inter frame
 283                                                                    gap part 1.
 284                                                                    << shift */
 285 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)       /* Non
 286                                                                    back-to-back
 287                                                                    inter frame
 288                                                                    gap part 2.
 289                                                                    << shift */
 290 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)       /* Mimimum IFG
 291                                                                    Enforcement
 292                                                                    << shift */
 293 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)       /* back-to-back
 294                                                                    inter frame
 295                                                                    gap << shift
 296                                                                  */
 297 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127     /* Non back-to-back
 298                                                            inter frame gap part
 299                                                            1. max val */
 300 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127     /* Non back-to-back
 301                                                            inter frame gap part
 302                                                            2. max val */
 303 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255     /* Mimimum IFG
 304                                                            Enforcement max val */
 305 #define IPGIFG_BACK_TO_BACK_IFG_MAX             127     /* back-to-back inter
 306                                                            frame gap max val */
 307 #define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
 308 #define IPGIFG_NBTB_IPG_MASK                    0x007F0000
 309 #define IPGIFG_MIN_IFG_MASK                     0x0000FF00
 310 #define IPGIFG_BTB_IPG_MASK                     0x0000007F
 311
 312 /* UCC GETH HAFDUP (Half Duplex Register) */
 313 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)       /* Alternate
 314                                                                    Binary
 315                                                                    Exponential
 316                                                                    Backoff
 317                                                                    Truncation
 318                                                                    << shift */
 319 #define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf     /* Alternate Binary
 320                                                            Exponential Backoff
 321                                                            Truncation max val */
 322 #define HALFDUP_ALT_BEB                         0x00080000      /* Alternate
 323                                                                    Binary
 324                                                                    Exponential
 325                                                                    Backoff */
 326 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000      /* Back
 327                                                                    pressure no
 328                                                                    backoff */
 329 #define HALFDUP_NO_BACKOFF                      0x00020000      /* No Backoff */
 330 #define HALFDUP_EXCESSIVE_DEFER                 0x00010000      /* Excessive
 331                                                                    Defer */
 332 #define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)       /* Maximum
 333                                                                    Retransmission
 334                                                                    << shift */
 335 #define HALFDUP_MAX_RETRANSMISSION_MAX          0xf     /* Maximum
 336                                                            Retransmission max
 337                                                            val */
 338 #define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)       /* Collision
 339                                                                    Window <<
 340                                                                    shift */
 341 #define HALFDUP_COLLISION_WINDOW_MAX            0x3f    /* Collision Window max
 342                                                            val */
 343 #define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
 344 #define HALFDUP_RETRANS_MASK                    0x0000F000
 345 #define HALFDUP_COL_WINDOW_MASK                 0x0000003F
 346
 347 /* UCC GETH UCCS (Ethernet Status Register) */
 348 #define UCCS_BPR                                0x02    /* Back pressure (in
 349                                                            half duplex mode) */
 350 #define UCCS_PAU                                0x02    /* Pause state (in full
 351                                                            duplex mode) */
 352 #define UCCS_MPD                                0x01    /* Magic Packet
 353                                                            Detected */
 354
 355 /* UCC GETH IFSTAT (Interface Status Register) */
 356 #define IFSTAT_EXCESS_DEFER                     0x00000200      /* Excessive
 357                                                                    transmission
 358                                                                    defer */
 359
 360 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
 361 #define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)       /* Station
 362                                                                    address 6th
 363                                                                    octet <<
 364                                                                    shift */
 365 #define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)       /* Station
 366                                                                    address 5th
 367                                                                    octet <<
 368                                                                    shift */
 369 #define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)       /* Station
 370                                                                    address 4th
 371                                                                    octet <<
 372                                                                    shift */
 373 #define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)       /* Station
 374                                                                    address 3rd
 375                                                                    octet <<
 376                                                                    shift */
 377
 378 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
 379 #define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)       /* Station
 380                                                                    address 2nd
 381                                                                    octet <<
 382                                                                    shift */
 383 #define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)       /* Station
 384                                                                    address 1st
 385                                                                    octet <<
 386                                                                    shift */
 387
 388 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
 389 #define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)       /* Pause time
 390                                                                    value <<
 391                                                                    shift */
 392 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)       /* Extended
 393                                                                    pause time
 394                                                                    value <<
 395                                                                    shift */
 396
 397 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
 398 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)       /* Phy address
 399                                                                    << shift */
 400 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f      /* Phy address
 401                                                                    mask */
 402
 403 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
 404 #define UESCR_AUTOZ                             0x8000  /* Automatically zero
 405                                                            addressed
 406                                                            statistical counter
 407                                                            values */
 408 #define UESCR_CLRCNT                            0x4000  /* Clear all statistics
 409                                                            counters */
 410 #define UESCR_MAXCOV_SHIFT                      (15 -  7)       /* Max
 411                                                                    Coalescing
 412                                                                    Value <<
 413                                                                    shift */
 414 #define UESCR_SCOV_SHIFT                        (15 - 15)       /* Status
 415                                                                    Coalescing
 416                                                                    Value <<
 417                                                                    shift */
 418
 419 /* UCC GETH UDSR (Data Synchronization Register) */
 420 #define UDSR_MAGIC                              0x067E
 421
 422 struct ucc_geth_thread_data_tx {
 423         u8 res0[104];
 424 } __packed;
 425
 426 struct ucc_geth_thread_data_rx {
 427         u8 res0[40];
 428 } __packed;
 429
 430 /* Send Queue Queue-Descriptor */
 431 struct ucc_geth_send_queue_qd {
 432         u32 bd_ring_base;       /* pointer to BD ring base address */
 433         u8 res0[0x8];
 434         u32 last_bd_completed_address;/* initialize to last entry in BD ring */
 435         u8 res1[0x30];
 436 } __packed;
 437
 438 struct ucc_geth_send_queue_mem_region {
 439         struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
 440 } __packed;
 441
 442 struct ucc_geth_thread_tx_pram {
 443         u8 res0[64];
 444 } __packed;
 445
 446 struct ucc_geth_thread_rx_pram {
 447         u8 res0[128];
 448 } __packed;
 449
 450 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
 451 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
 452 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
 453
 454 struct ucc_geth_scheduler {
 455         u16 cpucount0;          /* CPU packet counter */
 456         u16 cpucount1;          /* CPU packet counter */
 457         u16 cecount0;           /* QE packet counter */
 458         u16 cecount1;           /* QE packet counter */
 459         u16 cpucount2;          /* CPU packet counter */
 460         u16 cpucount3;          /* CPU packet counter */
 461         u16 cecount2;           /* QE packet counter */
 462         u16 cecount3;           /* QE packet counter */
 463         u16 cpucount4;          /* CPU packet counter */
 464         u16 cpucount5;          /* CPU packet counter */
 465         u16 cecount4;           /* QE packet counter */
 466         u16 cecount5;           /* QE packet counter */
 467         u16 cpucount6;          /* CPU packet counter */
 468         u16 cpucount7;          /* CPU packet counter */
 469         u16 cecount6;           /* QE packet counter */
 470         u16 cecount7;           /* QE packet counter */
 471         u32 weightstatus[NUM_TX_QUEUES];        /* accumulated weight factor */
 472         u32 rtsrshadow;         /* temporary variable handled by QE */
 473         u32 time;               /* temporary variable handled by QE */
 474         u32 ttl;                /* temporary variable handled by QE */
 475         u32 mblinterval;        /* max burst length interval */
 476         u16 nortsrbytetime;     /* normalized value of byte time in tsr units */
 477         u8 fracsiz;             /* radix 2 log value of denom. of
 478                                    NorTSRByteTime */
 479         u8 res0[1];
 480         u8 strictpriorityq;     /* Strict Priority Mask register */
 481         u8 txasap;              /* Transmit ASAP register */
 482         u8 extrabw;             /* Extra BandWidth register */
 483         u8 oldwfqmask;          /* temporary variable handled by QE */
 484         u8 weightfactor[NUM_TX_QUEUES];
 485                                       /**< weight factor for queues   */
 486         u32 minw;               /* temporary variable handled by QE */
 487         u8 res1[0x70 - 0x64];
 488 } __packed;
 489
 490 struct ucc_geth_tx_firmware_statistics_pram {
 491         u32 sicoltx;            /* single collision */
 492         u32 mulcoltx;           /* multiple collision */
 493         u32 latecoltxfr;        /* late collision */
 494         u32 frabortduecol;      /* frames aborted due to transmit collision */
 495         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 496                                    transmission that are not counted on any
 497                                    other counter */
 498         u32 carriersenseertx;   /* carrier sense error */
 499         u32 frtxok;             /* frames transmitted OK */
 500         u32 txfrexcessivedefer; /* frames with defferal time greater than
 501                                    specified threshold */
 502         u32 txpkts256;          /* total packets (including bad) between 256
 503                                    and 511 octets */
 504         u32 txpkts512;          /* total packets (including bad) between 512
 505                                    and 1023 octets */
 506         u32 txpkts1024;         /* total packets (including bad) between 1024
 507                                    and 1518 octets */
 508         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 509                                    and MAXLength octets */
 510 } __packed;
 511
 512 struct ucc_geth_rx_firmware_statistics_pram {
 513         u32 frrxfcser;          /* frames with crc error */
 514         u32 fraligner;          /* frames with alignment error */
 515         u32 inrangelenrxer;     /* in range length error */
 516         u32 outrangelenrxer;    /* out of range length error */
 517         u32 frtoolong;          /* frame too long */
 518         u32 runt;               /* runt */
 519         u32 verylongevent;      /* very long event */
 520         u32 symbolerror;        /* symbol error */
 521         u32 dropbsy;            /* drop because of BD not ready */
 522         u8 res0[0x8];
 523         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 524                                    or type mismatch) */
 525         u32 underpkts;          /* total frames less than 64 octets */
 526         u32 pkts256;            /* total frames (including bad) between 256 and
 527                                    511 octets */
 528         u32 pkts512;            /* total frames (including bad) between 512 and
 529                                    1023 octets */
 530         u32 pkts1024;           /* total frames (including bad) between 1024
 531                                    and 1518 octets */
 532         u32 pktsjumbo;          /* total frames (including bad) between 1024
 533                                    and MAXLength octets */
 534         u32 frlossinmacer;      /* frames lost because of internal MAC error
 535                                    that is not counted in any other counter */
 536         u32 pausefr;            /* pause frames */
 537         u8 res1[0x4];
 538         u32 removevlan;         /* total frames that had their VLAN tag removed
 539                                  */
 540         u32 replacevlan;        /* total frames that had their VLAN tag
 541                                    replaced */
 542         u32 insertvlan;         /* total frames that had their VLAN tag
 543                                    inserted */
 544 } __packed;
 545
 546 struct ucc_geth_rx_interrupt_coalescing_entry {
 547         u32 interruptcoalescingmaxvalue;        /* interrupt coalescing max
 548                                                    value */
 549         u32 interruptcoalescingcounter; /* interrupt coalescing counter,
 550                                            initialize to
 551                                            interruptcoalescingmaxvalue */
 552 } __packed;
 553
 554 struct ucc_geth_rx_interrupt_coalescing_table {
 555         struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
 556                                        /**< interrupt coalescing entry */
 557 } __packed;
 558
 559 struct ucc_geth_rx_prefetched_bds {
 560         struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];     /* prefetched bd */
 561 } __packed;
 562
 563 struct ucc_geth_rx_bd_queues_entry {
 564         u32 bdbaseptr;          /* BD base pointer */
 565         u32 bdptr;              /* BD pointer */
 566         u32 externalbdbaseptr;  /* external BD base pointer */
 567         u32 externalbdptr;      /* external BD pointer */
 568 } __packed;
 569
 570 struct ucc_geth_tx_global_pram {
 571         u16 temoder;
 572         u8 res0[0x38 - 0x02];
 573         u32 sqptr;              /* a base pointer to send queue memory region */
 574         u32 schedulerbasepointer;       /* a base pointer to scheduler memory
 575                                            region */
 576         u32 txrmonbaseptr;      /* base pointer to Tx RMON statistics counter */
 577         u32 tstate;             /* tx internal state. High byte contains
 578                                    function code */
 579         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
 580         u32 vtagtable[0x8];     /* 8 4-byte VLAN tags */
 581         u32 tqptr;              /* a base pointer to the Tx Queues Memory
 582                                    Region */
 583         u8 res2[0x78 - 0x74];
 584         u64 snums_en;
 585         u32 l2l3baseptr;        /* top byte consists of a few other bit fields */
 586
 587         u16 mtu[8];
 588         u8 res3[0xa8 - 0x94];
 589         u32 wrrtablebase;       /* top byte is reserved */
 590         u8 res4[0xc0 - 0xac];
 591 } __packed;
 592
 593 /* structure representing Extended Filtering Global Parameters in PRAM */
 594 struct ucc_geth_exf_global_pram {
 595         u32 l2pcdptr;           /* individual address filter, high */
 596         u8 res0[0x10 - 0x04];
 597 } __packed;
 598
 599 struct ucc_geth_rx_global_pram {
 600         u32 remoder;            /* ethernet mode reg. */
 601         u32 rqptr;              /* base pointer to the Rx Queues Memory Region*/
 602         u32 res0[0x1];
 603         u8 res1[0x20 - 0xC];
 604         u16 typeorlen;          /* cutoff point less than which, type/len field
 605                                    is considered length */
 606         u8 res2[0x1];
 607         u8 rxgstpack;           /* acknowledgement on GRACEFUL STOP RX command*/
 608         u32 rxrmonbaseptr;      /* base pointer to Rx RMON statistics counter */
 609         u8 res3[0x30 - 0x28];
 610         u32 intcoalescingptr;   /* Interrupt coalescing table pointer */
 611         u8 res4[0x36 - 0x34];
 612         u8 rstate;              /* rx internal state. High byte contains
 613                                    function code */
 614         u8 res5[0x46 - 0x37];
 615         u16 mrblr;              /* max receive buffer length reg. */
 616         u32 rbdqptr;            /* base pointer to RxBD parameter table
 617                                    description */
 618         u16 mflr;               /* max frame length reg. */
 619         u16 minflr;             /* min frame length reg. */
 620         u16 maxd1;              /* max dma1 length reg. */
 621         u16 maxd2;              /* max dma2 length reg. */
 622         u32 ecamptr;            /* external CAM address */
 623         u32 l2qt;               /* VLAN priority mapping table. */
 624         u32 l3qt[0x8];          /* IP priority mapping table. */
 625         u16 vlantype;           /* vlan type */
 626         u16 vlantci;            /* default vlan tci */
 627         u8 addressfiltering[64];        /* address filtering data structure */
 628         u32 exfGlobalParam;     /* base address for extended filtering global
 629                                    parameters */
 630         u8 res6[0x100 - 0xC4];  /* Initialize to zero */
 631 } __packed;
 632
 633 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 634
 635 /* structure representing InitEnet command */
 636 struct ucc_geth_init_pram {
 637         u8 resinit1;
 638         u8 resinit2;
 639         u8 resinit3;
 640         u8 resinit4;
 641         u16 resinit5;
 642         u8 res1[0x1];
 643         u8 largestexternallookupkeysize;
 644         u32 rgftgfrxglobal;
 645         u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];   /* rx threads */
 646         u8 res2[0x38 - 0x30];
 647         u32 txglobal;           /* tx global */
 648         u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];   /* tx threads */
 649         u8 res3[0x1];
 650 } __packed;
 651
 652 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 653 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 654
 655 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 656 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 657 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 658 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 659
 660 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
 661 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
 662 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
 663 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
 664 #define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
 665
 666 /* structure representing 82xx Address Filtering Enet Address in PRAM */
 667 struct ucc_geth_82xx_enet_address {
 668         u8 res1[0x2];
 669         u16 h;                  /* address (MSB) */
 670         u16 m;                  /* address */
 671         u16 l;                  /* address (LSB) */
 672 } __packed;
 673
 674 /* structure representing 82xx Address Filtering PRAM */
 675 struct ucc_geth_82xx_address_filtering_pram {
 676         u32 iaddr_h;            /* individual address filter, high */
 677         u32 iaddr_l;            /* individual address filter, low */
 678         u32 gaddr_h;            /* group address filter, high */
 679         u32 gaddr_l;            /* group address filter, low */
 680         struct ucc_geth_82xx_enet_address __iomem taddr;
 681         struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
 682         u8 res0[0x40 - 0x38];
 683 } __packed;
 684
 685 /* GETH Tx firmware statistics structure, used when calling
 686    UCC_GETH_GetStatistics. */
 687 struct ucc_geth_tx_firmware_statistics {
 688         u32 sicoltx;            /* single collision */
 689         u32 mulcoltx;           /* multiple collision */
 690         u32 latecoltxfr;        /* late collision */
 691         u32 frabortduecol;      /* frames aborted due to transmit collision */
 692         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 693                                    transmission that are not counted on any
 694                                    other counter */
 695         u32 carriersenseertx;   /* carrier sense error */
 696         u32 frtxok;             /* frames transmitted OK */
 697         u32 txfrexcessivedefer; /* frames with defferal time greater than
 698                                    specified threshold */
 699         u32 txpkts256;          /* total packets (including bad) between 256
 700                                    and 511 octets */
 701         u32 txpkts512;          /* total packets (including bad) between 512
 702                                    and 1023 octets */
 703         u32 txpkts1024;         /* total packets (including bad) between 1024
 704                                    and 1518 octets */
 705         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 706                                    and MAXLength octets */
 707 } __packed;
 708
 709 /* GETH Rx firmware statistics structure, used when calling
 710    UCC_GETH_GetStatistics. */
 711 struct ucc_geth_rx_firmware_statistics {
 712         u32 frrxfcser;          /* frames with crc error */
 713         u32 fraligner;          /* frames with alignment error */
 714         u32 inrangelenrxer;     /* in range length error */
 715         u32 outrangelenrxer;    /* out of range length error */
 716         u32 frtoolong;          /* frame too long */
 717         u32 runt;               /* runt */
 718         u32 verylongevent;      /* very long event */
 719         u32 symbolerror;        /* symbol error */
 720         u32 dropbsy;            /* drop because of BD not ready */
 721         u8 res0[0x8];
 722         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 723                                    or type mismatch) */
 724         u32 underpkts;          /* total frames less than 64 octets */
 725         u32 pkts256;            /* total frames (including bad) between 256 and
 726                                    511 octets */
 727         u32 pkts512;            /* total frames (including bad) between 512 and
 728                                    1023 octets */
 729         u32 pkts1024;           /* total frames (including bad) between 1024
 730                                    and 1518 octets */
 731         u32 pktsjumbo;          /* total frames (including bad) between 1024
 732                                    and MAXLength octets */
 733         u32 frlossinmacer;      /* frames lost because of internal MAC error
 734                                    that is not counted in any other counter */
 735         u32 pausefr;            /* pause frames */
 736         u8 res1[0x4];
 737         u32 removevlan;         /* total frames that had their VLAN tag removed
 738                                  */
 739         u32 replacevlan;        /* total frames that had their VLAN tag
 740                                    replaced */
 741         u32 insertvlan;         /* total frames that had their VLAN tag
 742                                    inserted */
 743 } __packed;
 744
 745 /* GETH hardware statistics structure, used when calling
 746    UCC_GETH_GetStatistics. */
 747 struct ucc_geth_hardware_statistics {
 748         u32 tx64;               /* Total number of frames (including bad
 749                                    frames) transmitted that were exactly of the
 750                                    minimal length (64 for un tagged, 68 for
 751                                    tagged, or with length exactly equal to the
 752                                    parameter MINLength */
 753         u32 tx127;              /* Total number of frames (including bad
 754                                    frames) transmitted that were between
 755                                    MINLength (Including FCS length==4) and 127
 756                                    octets */
 757         u32 tx255;              /* Total number of frames (including bad
 758                                    frames) transmitted that were between 128
 759                                    (Including FCS length==4) and 255 octets */
 760         u32 rx64;               /* Total number of frames received including
 761                                    bad frames that were exactly of the mninimal
 762                                    length (64 bytes) */
 763         u32 rx127;              /* Total number of frames (including bad
 764                                    frames) received that were between MINLength
 765                                    (Including FCS length==4) and 127 octets */
 766         u32 rx255;              /* Total number of frames (including bad
 767                                    frames) received that were between 128
 768                                    (Including FCS length==4) and 255 octets */
 769         u32 txok;               /* Total number of octets residing in frames
 770                                    that where involved in successful
 771                                    transmission */
 772         u16 txcf;               /* Total number of PAUSE control frames
 773                                    transmitted by this MAC */
 774         u32 tmca;               /* Total number of frames that were transmitted
 775                                    successfully with the group address bit set
 776                                    that are not broadcast frames */
 777         u32 tbca;               /* Total number of frames transmitted
 778                                    successfully that had destination address
 779                                    field equal to the broadcast address */
 780         u32 rxfok;              /* Total number of frames received OK */
 781         u32 rxbok;              /* Total number of octets received OK */
 782         u32 rbyt;               /* Total number of octets received including
 783                                    octets in bad frames. Must be implemented in
 784                                    HW because it includes octets in frames that
 785                                    never even reach the UCC */
 786         u32 rmca;               /* Total number of frames that were received
 787                                    successfully with the group address bit set
 788                                    that are not broadcast frames */
 789         u32 rbca;               /* Total number of frames received successfully
 790                                    that had destination address equal to the
 791                                    broadcast address */
 792 } __packed;
 793
 794 /* UCC GETH Tx errors returned via TxConf callback */
 795 #define TX_ERRORS_DEF      0x0200
 796 #define TX_ERRORS_EXDEF    0x0100
 797 #define TX_ERRORS_LC       0x0080
 798 #define TX_ERRORS_RL       0x0040
 799 #define TX_ERRORS_RC_MASK  0x003C
 800 #define TX_ERRORS_RC_SHIFT 2
 801 #define TX_ERRORS_UN       0x0002
 802 #define TX_ERRORS_CSL      0x0001
 803
 804 /* UCC GETH Rx errors returned via RxStore callback */
 805 #define RX_ERRORS_CMR      0x0200
 806 #define RX_ERRORS_M        0x0100
 807 #define RX_ERRORS_BC       0x0080
 808 #define RX_ERRORS_MC       0x0040
 809
 810 /* Transmit BD. These are in addition to values defined in uccf. */
 811 #define T_VID      0x003c0000   /* insert VLAN id index mask. */
 812 #define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
 813 #define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
 814 #define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
 815 #define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
 816 #define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
 817 #define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
 818 #define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
 819 #define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
 820                 | T_UN | T_CSL) /* transmit errors to report */
 821
 822 /* Receive BD. These are in addition to values defined in uccf. */
 823 #define R_LG    0x00200000      /* Frame length violation.  */
 824 #define R_NO    0x00100000      /* Non-octet aligned frame.  */
 825 #define R_SH    0x00080000      /* Short frame.  */
 826 #define R_CR    0x00040000      /* CRC error.  */
 827 #define R_OV    0x00020000      /* Overrun.  */
 828 #define R_IPCH  0x00010000      /* IP checksum check failed. */
 829 #define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
 830 #define R_M     (((u32) RX_ERRORS_M    ) << 16)
 831 #define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
 832 #define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
 833 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)     /* receive errors to
 834                                                            report */
 835 #define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
 836                 R_OV | R_IPCH)  /* receive errors to discard */
 837
 838 /* Alignments */
 839 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT       256
 840 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
 841 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
 842 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
 843 #define UCC_GETH_THREAD_DATA_ALIGNMENT          256     /* spec gives values
 844                                                            based on num of
 845                                                            threads, but always
 846                                                            using the maximum is
 847                                                            easier */
 848 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT  32
 849 #define UCC_GETH_SCHEDULER_ALIGNMENT            8       /* This is a guess */
 850 #define UCC_GETH_TX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 851 #define UCC_GETH_RX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 852 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT      64
 853 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT         8       /* This is a guess */
 854 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT    128     /* This is a guess */
 855 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8    /* This
 856                                                                            is a
 857                                                                            guess
 858                                                                          */
 859 #define UCC_GETH_RX_BD_RING_ALIGNMENT           32
 860 #define UCC_GETH_TX_BD_RING_ALIGNMENT           32
 861 #define UCC_GETH_MRBLR_ALIGNMENT                128
 862 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT      4
 863 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT       32
 864 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT          64
 865
 866 #define UCC_GETH_TAD_EF                         0x80
 867 #define UCC_GETH_TAD_V                          0x40
 868 #define UCC_GETH_TAD_REJ                        0x20
 869 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
 870 #define UCC_GETH_TAD_VTAG_OP_SHIFT              6
 871 #define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
 872 #define UCC_GETH_TAD_RQOS_SHIFT                 0
 873 #define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
 874 #define UCC_GETH_TAD_CFI                        0x10
 875
 876 #define UCC_GETH_VLAN_PRIORITY_MAX              8
 877 #define UCC_GETH_IP_PRIORITY_MAX                64
 878 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
 879 #define UCC_GETH_RX_BD_RING_SIZE_MIN            8
 880 #define UCC_GETH_TX_BD_RING_SIZE_MIN            2
 881 #define UCC_GETH_BD_RING_SIZE_MAX               0xffff
 882
 883 #define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
 884
 885 /* Driver definitions */
 886 #define TX_BD_RING_LEN                          0x10
 887 #define RX_BD_RING_LEN                          0x20
 888
 889 #define TX_RING_MOD_MASK(size)                  (size-1)
 890 #define RX_RING_MOD_MASK(size)                  (size-1)
 891
 892 #define ENET_GROUP_ADDR                         0x01    /* Group address mask
 893                                                            for ethernet
 894                                                            addresses */
 895
 896 #define TX_TIMEOUT                              (1*HZ)
 897 #define SKB_ALLOC_TIMEOUT                       100000
 898 #define PHY_INIT_TIMEOUT                        100000
 899 #define PHY_CHANGE_TIME                         2
 900
 901 /* Fast Ethernet (10/100 Mbps) */
 902 #define UCC_GETH_URFS_INIT                      512     /* Rx virtual FIFO size
 903                                                          */
 904 #define UCC_GETH_URFET_INIT                     256     /* 1/2 urfs */
 905 #define UCC_GETH_URFSET_INIT                    384     /* 3/4 urfs */
 906 #define UCC_GETH_UTFS_INIT                      512     /* Tx virtual FIFO size
 907                                                          */
 908 #define UCC_GETH_UTFET_INIT                     256     /* 1/2 utfs */
 909 #define UCC_GETH_UTFTT_INIT                     256     /* 1/2 utfs
 910                                                            due to errata */
 911 /* Gigabit Ethernet (1000 Mbps) */
 912 #define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/    /* Rx virtual
 913                                                                    FIFO size */
 914 #define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/    /* 1/2 urfs */
 915 #define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/    /* 3/4 urfs */
 916 #define UCC_GETH_UTFS_GIGA_INIT                 4096/*2048*/    /* Tx virtual
 917                                                                    FIFO size */
 918 #define UCC_GETH_UTFET_GIGA_INIT                2048/*1024*/    /* 1/2 utfs */
 919 #define UCC_GETH_UTFTT_GIGA_INIT                4096/*0x40*/    /* Tx virtual
 920                                                                    FIFO size */
 921
 922 #define UCC_GETH_REMODER_INIT                   0       /* bits that must be
 923                                                            set */
 924 #define UCC_GETH_TEMODER_INIT                   0xC000  /* bits that must */
 925
 926 /* Initial value for UPSMR */
 927 #define UCC_GETH_UPSMR_INIT                     UCC_GETH_UPSMR_RES1
 928
 929 #define UCC_GETH_MACCFG1_INIT                   0
 930 #define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1)
 931
 932 /* Ethernet Address Type. */
 933 enum enet_addr_type {
 934         ENET_ADDR_TYPE_INDIVIDUAL,
 935         ENET_ADDR_TYPE_GROUP,
 936         ENET_ADDR_TYPE_BROADCAST
 937 };
 938
 939 /* UCC GETH 82xx Ethernet Address Recognition Location */
 940 enum ucc_geth_enet_address_recognition_location {
 941         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
 942                                                                       address */
 943         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
 944                                                                    station
 945                                                                    address
 946                                                                    paddr1 */
 947         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,      /* additional
 948                                                                    station
 949                                                                    address
 950                                                                    paddr2 */
 951         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,      /* additional
 952                                                                    station
 953                                                                    address
 954                                                                    paddr3 */
 955         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,  /* additional
 956                                                                    station
 957                                                                    address
 958                                                                    paddr4 */
 959         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,  /* group hash */
 960         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
 961                                                                       hash */
 962 };
 963
 964 /* UCC GETH vlan operation tagged */
 965 enum ucc_geth_vlan_operation_tagged {
 966         UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,       /* Tagged - nop */
 967         UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
 968                 = 0x1,  /* Tagged - replace vid portion of q tag */
 969         UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
 970                 = 0x2,  /* Tagged - if vid0 replace vid with default value  */
 971         UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
 972                 = 0x3   /* Tagged - extract q tag from frame */
 973 };
 974
 975 /* UCC GETH vlan operation non-tagged */
 976 enum ucc_geth_vlan_operation_non_tagged {
 977         UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,   /* Non tagged - nop */
 978         UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1   /* Non tagged -
 979                                                                    q tag insert
 980                                                                  */
 981 };
 982
 983 /* UCC GETH Rx Quality of Service Mode */
 984 enum ucc_geth_qos_mode {
 985         UCC_GETH_QOS_MODE_DEFAULT = 0x0,        /* default queue */
 986         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,     /* queue
 987                                                                    determined
 988                                                                    by L2
 989                                                                    criteria */
 990         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2      /* queue
 991                                                                    determined
 992                                                                    by L3
 993                                                                    criteria */
 994 };
 995
 996 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
 997    for combined functionality */
 998 enum ucc_geth_statistics_gathering_mode {
 999         UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,   /* No
1000                                                                    statistics
1001                                                                    gathering */
1002         UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
1003                                                                     hardware
1004                                                                     statistics
1005                                                                     gathering
1006                                                                   */
1007         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1008                                                                       firmware
1009                                                                       tx
1010                                                                       statistics
1011                                                                       gathering
1012                                                                      */
1013         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1014                                                                       firmware
1015                                                                       rx
1016                                                                       statistics
1017                                                                       gathering
1018                                                                     */
1019 };
1020
1021 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1022 enum ucc_geth_maccfg2_pad_and_crc_mode {
1023         UCC_GETH_PAD_AND_CRC_MODE_NONE
1024                 = MACCFG2_PAD_AND_CRC_MODE_NONE,        /* Neither Padding
1025                                                            short frames
1026                                                            nor CRC */
1027         UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1028                 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,    /* Append
1029                                                            CRC only */
1030         UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1031             MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1032 };
1033
1034 /* UCC GETH upsmr Flow Control Mode */
1035 enum ucc_geth_flow_control_mode {
1036         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,    /* No automatic
1037                                                                    flow control
1038                                                                  */
1039         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1040                 = 0x00004000    /* Send pause frame when RxFIFO reaches its
1041                                    emergency threshold */
1042 };
1043
1044 /* UCC GETH number of threads */
1045 enum ucc_geth_num_of_threads {
1046         UCC_GETH_NUM_OF_THREADS_1 = 0x1,        /* 1 */
1047         UCC_GETH_NUM_OF_THREADS_2 = 0x2,        /* 2 */
1048         UCC_GETH_NUM_OF_THREADS_4 = 0x0,        /* 4 */
1049         UCC_GETH_NUM_OF_THREADS_6 = 0x3,        /* 6 */
1050         UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1051 };
1052
1053 /* UCC GETH number of station addresses */
1054 enum ucc_geth_num_of_station_addresses {
1055         UCC_GETH_NUM_OF_STATION_ADDRESSES_1,    /* 1 */
1056         UCC_GETH_NUM_OF_STATION_ADDRESSES_5     /* 5 */
1057 };
1058
1059 /* UCC GETH 82xx Ethernet Address Container */
1060 struct enet_addr_container {
1061         u8 address[ETH_ALEN];   /* ethernet address */
1062         enum ucc_geth_enet_address_recognition_location location;       /* location in
1063                                                                    82xx address
1064                                                                    recognition
1065                                                                    hardware */
1066         struct list_head node;
1067 };
1068
1069 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1070
1071 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1072 struct ucc_geth_tad_params {
1073         int rx_non_dynamic_extended_features_mode;
1074         int reject_frame;
1075         enum ucc_geth_vlan_operation_tagged vtag_op;
1076         enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1077         enum ucc_geth_qos_mode rqos;
1078         u8 vpri;
1079         u16 vid;
1080 };
1081
1082 /* GETH protocol initialization structure */
1083 struct ucc_geth_info {
1084         struct ucc_fast_info uf_info;
1085         u8 numQueuesTx;
1086         u8 numQueuesRx;
1087         int ipCheckSumCheck;
1088         int ipCheckSumGenerate;
1089         int rxExtendedFiltering;
1090         u32 extendedFilteringChainPointer;
1091         u16 typeorlen;
1092         int dynamicMaxFrameLength;
1093         int dynamicMinFrameLength;
1094         u8 nonBackToBackIfgPart1;
1095         u8 nonBackToBackIfgPart2;
1096         u8 miminumInterFrameGapEnforcement;
1097         u8 backToBackInterFrameGap;
1098         int ipAddressAlignment;
1099         int lengthCheckRx;
1100         u32 mblinterval;
1101         u16 nortsrbytetime;
1102         u8 fracsiz;
1103         u8 strictpriorityq;
1104         u8 txasap;
1105         u8 extrabw;
1106         int miiPreambleSupress;
1107         u8 altBebTruncation;
1108         int altBeb;
1109         int backPressureNoBackoff;
1110         int noBackoff;
1111         int excessDefer;
1112         u8 maxRetransmission;
1113         u8 collisionWindow;
1114         int pro;
1115         int cap;
1116         int rsh;
1117         int rlpb;
1118         int cam;
1119         int bro;
1120         int ecm;
1121         int receiveFlowControl;
1122         int transmitFlowControl;
1123         u8 maxGroupAddrInHash;
1124         u8 maxIndAddrInHash;
1125         u8 prel;
1126         u16 maxFrameLength;
1127         u16 minFrameLength;
1128         u16 maxD1Length;
1129         u16 maxD2Length;
1130         u16 vlantype;
1131         u16 vlantci;
1132         u32 ecamptr;
1133         u32 eventRegMask;
1134         u16 pausePeriod;
1135         u16 extensionField;
1136         struct device_node *phy_node;
1137         struct device_node *tbi_node;
1138         u8 weightfactor[NUM_TX_QUEUES];
1139         u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1140         u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1141         u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1142         u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1143         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1144         u16 bdRingLenTx[NUM_TX_QUEUES];
1145         u16 bdRingLenRx[NUM_RX_QUEUES];
1146         enum ucc_geth_num_of_station_addresses numStationAddresses;
1147         enum qe_fltr_largest_external_tbl_lookup_key_size
1148             largestexternallookupkeysize;
1149         enum ucc_geth_statistics_gathering_mode statisticsMode;
1150         enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1151         enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1152         enum ucc_geth_qos_mode rxQoSMode;
1153         enum ucc_geth_flow_control_mode aufc;
1154         enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1155         enum ucc_geth_num_of_threads numThreadsTx;
1156         enum ucc_geth_num_of_threads numThreadsRx;
1157         unsigned int riscTx;
1158         unsigned int riscRx;
1159 };
1160
1161 /* structure representing UCC GETH */
1162 struct ucc_geth_private {
1163         struct ucc_geth_info *ug_info;
1164         struct ucc_fast_private *uccf;
1165         struct device *dev;
1166         struct net_device *ndev;
1167         struct napi_struct napi;
1168         struct work_struct timeout_work;
1169         struct ucc_geth __iomem *ug_regs;
1170         struct ucc_geth_init_pram *p_init_enet_param_shadow;
1171         struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1172         u32 exf_glbl_param_offset;
1173         struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1174         u32 rx_glbl_pram_offset;
1175         struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1176         u32 tx_glbl_pram_offset;
1177         struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1178         u32 send_q_mem_reg_offset;
1179         struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1180         u32 thread_dat_tx_offset;
1181         struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1182         u32 thread_dat_rx_offset;
1183         struct ucc_geth_scheduler __iomem *p_scheduler;
1184         u32 scheduler_offset;
1185         struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1186         u32 tx_fw_statistics_pram_offset;
1187         struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1188         u32 rx_fw_statistics_pram_offset;
1189         struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1190         u32 rx_irq_coalescing_tbl_offset;
1191         struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1192         u32 rx_bd_qs_tbl_offset;
1193         u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1194         u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1195         u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1196         u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1197         u8 __iomem *confBd[NUM_TX_QUEUES];
1198         u8 __iomem *txBd[NUM_TX_QUEUES];
1199         u8 __iomem *rxBd[NUM_RX_QUEUES];
1200         int badFrame[NUM_RX_QUEUES];
1201         u16 cpucount[NUM_TX_QUEUES];
1202         u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1203         int indAddrRegUsed[NUM_OF_PADDRS];
1204         u8 paddr[NUM_OF_PADDRS][ETH_ALEN];      /* ethernet address */
1205         u8 numGroupAddrInHash;
1206         u8 numIndAddrInHash;
1207         u8 numIndAddrInReg;
1208         int rx_extended_features;
1209         int rx_non_dynamic_extended_features;
1210         struct list_head conf_skbs;
1211         struct list_head group_hash_q;
1212         struct list_head ind_hash_q;
1213         u32 saved_uccm;
1214         spinlock_t lock;
1215         /* pointers to arrays of skbuffs for tx and rx */
1216         struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1217         struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1218         /* indices pointing to the next free sbk in skb arrays */
1219         u16 skb_curtx[NUM_TX_QUEUES];
1220         u16 skb_currx[NUM_RX_QUEUES];
1221         /* index of the first skb which hasn't been transmitted yet. */
1222         u16 skb_dirtytx[NUM_TX_QUEUES];
1223
1224         struct ugeth_mii_info *mii_info;
1225         struct phy_device *phydev;
1226         phy_interface_t phy_interface;
1227         int max_speed;
1228         uint32_t msg_enable;
1229         int oldspeed;
1230         int oldduplex;
1231         int oldlink;
1232         int wol_en;
1233
1234         struct device_node *node;
1235 };
1236
1237 void uec_set_ethtool_ops(struct net_device *netdev);
1238 int init_flow_control_params(u32 automatic_flow_control_mode,
1239                 int rx_flow_control_enable, int tx_flow_control_enable,
1240                 u16 pause_period, u16 extension_field,
1241                 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1242                 u32 __iomem *maccfg1_register);
1243
1244
1245 #endif                          /* __UCC_GETH_H__ */