drivers/net/ethernet/hisilicon/hip04_eth.c

   1
   2 /* Copyright (c) 2014 Linaro Ltd.
   3  * Copyright (c) 2014 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/ktime.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy.h>
  18 #include <linux/of_mdio.h>
  19 #include <linux/of_net.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <linux/regmap.h>
  22
  23 #define PPE_CFG_RX_ADDR                 0x100
  24 #define PPE_CFG_POOL_GRP                0x300
  25 #define PPE_CFG_RX_BUF_SIZE             0x400
  26 #define PPE_CFG_RX_FIFO_SIZE            0x500
  27 #define PPE_CURR_BUF_CNT                0xa200
  28
  29 #define GE_DUPLEX_TYPE                  0x08
  30 #define GE_MAX_FRM_SIZE_REG             0x3c
  31 #define GE_PORT_MODE                    0x40
  32 #define GE_PORT_EN                      0x44
  33 #define GE_SHORT_RUNTS_THR_REG          0x50
  34 #define GE_TX_LOCAL_PAGE_REG            0x5c
  35 #define GE_TRANSMIT_CONTROL_REG         0x60
  36 #define GE_CF_CRC_STRIP_REG             0x1b0
  37 #define GE_MODE_CHANGE_REG              0x1b4
  38 #define GE_RECV_CONTROL_REG             0x1e0
  39 #define GE_STATION_MAC_ADDRESS          0x210
  40 #define PPE_CFG_CPU_ADD_ADDR            0x580
  41 #define PPE_CFG_MAX_FRAME_LEN_REG       0x408
  42 #define PPE_CFG_BUS_CTRL_REG            0x424
  43 #define PPE_CFG_RX_CTRL_REG             0x428
  44 #define PPE_CFG_RX_PKT_MODE_REG         0x438
  45 #define PPE_CFG_QOS_VMID_GEN            0x500
  46 #define PPE_CFG_RX_PKT_INT              0x538
  47 #define PPE_INTEN                       0x600
  48 #define PPE_INTSTS                      0x608
  49 #define PPE_RINT                        0x604
  50 #define PPE_CFG_STS_MODE                0x700
  51 #define PPE_HIS_RX_PKT_CNT              0x804
  52
  53 /* REG_INTERRUPT */
  54 #define RCV_INT                         BIT(10)
  55 #define RCV_NOBUF                       BIT(8)
  56 #define RCV_DROP                        BIT(7)
  57 #define TX_DROP                         BIT(6)
  58 #define DEF_INT_ERR                     (RCV_NOBUF | RCV_DROP | TX_DROP)
  59 #define DEF_INT_MASK                    (RCV_INT | DEF_INT_ERR)
  60
  61 /* TX descriptor config */
  62 #define TX_FREE_MEM                     BIT(0)
  63 #define TX_READ_ALLOC_L3                BIT(1)
  64 #define TX_FINISH_CACHE_INV             BIT(2)
  65 #define TX_CLEAR_WB                     BIT(4)
  66 #define TX_L3_CHECKSUM                  BIT(5)
  67 #define TX_LOOP_BACK                    BIT(11)
  68
  69 /* RX error */
  70 #define RX_PKT_DROP                     BIT(0)
  71 #define RX_L2_ERR                       BIT(1)
  72 #define RX_PKT_ERR                      (RX_PKT_DROP | RX_L2_ERR)
  73
  74 #define SGMII_SPEED_1000                0x08
  75 #define SGMII_SPEED_100                 0x07
  76 #define SGMII_SPEED_10                  0x06
  77 #define MII_SPEED_100                   0x01
  78 #define MII_SPEED_10                    0x00
  79
  80 #define GE_DUPLEX_FULL                  BIT(0)
  81 #define GE_DUPLEX_HALF                  0x00
  82 #define GE_MODE_CHANGE_EN               BIT(0)
  83
  84 #define GE_TX_AUTO_NEG                  BIT(5)
  85 #define GE_TX_ADD_CRC                   BIT(6)
  86 #define GE_TX_SHORT_PAD_THROUGH         BIT(7)
  87
  88 #define GE_RX_STRIP_CRC                 BIT(0)
  89 #define GE_RX_STRIP_PAD                 BIT(3)
  90 #define GE_RX_PAD_EN                    BIT(4)
  91
  92 #define GE_AUTO_NEG_CTL                 BIT(0)
  93
  94 #define GE_RX_INT_THRESHOLD             BIT(6)
  95 #define GE_RX_TIMEOUT                   0x04
  96
  97 #define GE_RX_PORT_EN                   BIT(1)
  98 #define GE_TX_PORT_EN                   BIT(2)
  99
 100 #define PPE_CFG_STS_RX_PKT_CNT_RC       BIT(12)
 101
 102 #define PPE_CFG_RX_PKT_ALIGN            BIT(18)
 103 #define PPE_CFG_QOS_VMID_MODE           BIT(14)
 104 #define PPE_CFG_QOS_VMID_GRP_SHIFT      8
 105
 106 #define PPE_CFG_RX_FIFO_FSFU            BIT(11)
 107 #define PPE_CFG_RX_DEPTH_SHIFT          16
 108 #define PPE_CFG_RX_START_SHIFT          0
 109 #define PPE_CFG_RX_CTRL_ALIGN_SHIFT     11
 110
 111 #define PPE_CFG_BUS_LOCAL_REL           BIT(14)
 112 #define PPE_CFG_BUS_BIG_ENDIEN          BIT(0)
 113
 114 #define RX_DESC_NUM                     128
 115 #define TX_DESC_NUM                     256
 116 #define TX_NEXT(N)                      (((N) + 1) & (TX_DESC_NUM-1))
 117 #define RX_NEXT(N)                      (((N) + 1) & (RX_DESC_NUM-1))
 118
 119 #define GMAC_PPE_RX_PKT_MAX_LEN         379
 120 #define GMAC_MAX_PKT_LEN                1516
 121 #define GMAC_MIN_PKT_LEN                31
 122 #define RX_BUF_SIZE                     1600
 123 #define RESET_TIMEOUT                   1000
 124 #define TX_TIMEOUT                      (6 * HZ)
 125
 126 #define DRV_NAME                        "hip04-ether"
 127 #define DRV_VERSION                     "v1.0"
 128
 129 #define HIP04_MAX_TX_COALESCE_USECS     200
 130 #define HIP04_MIN_TX_COALESCE_USECS     100
 131 #define HIP04_MAX_TX_COALESCE_FRAMES    200
 132 #define HIP04_MIN_TX_COALESCE_FRAMES    100
 133
 134 struct tx_desc {
 135         u32 send_addr;
 136         u32 send_size;
 137         u32 next_addr;
 138         u32 cfg;
 139         u32 wb_addr;
 140 } __aligned(64);
 141
 142 struct rx_desc {
 143         u16 reserved_16;
 144         u16 pkt_len;
 145         u32 reserve1[3];
 146         u32 pkt_err;
 147         u32 reserve2[4];
 148 };
 149
 150 struct hip04_priv {
 151         void __iomem *base;
 152         int phy_mode;
 153         int chan;
 154         unsigned int port;
 155         unsigned int speed;
 156         unsigned int duplex;
 157         unsigned int reg_inten;
 158
 159         struct napi_struct napi;
 160         struct device *dev;
 161         struct net_device *ndev;
 162
 163         struct tx_desc *tx_desc;
 164         dma_addr_t tx_desc_dma;
 165         struct sk_buff *tx_skb[TX_DESC_NUM];
 166         dma_addr_t tx_phys[TX_DESC_NUM];
 167         unsigned int tx_head;
 168
 169         int tx_coalesce_frames;
 170         int tx_coalesce_usecs;
 171         struct hrtimer tx_coalesce_timer;
 172
 173         unsigned char *rx_buf[RX_DESC_NUM];
 174         dma_addr_t rx_phys[RX_DESC_NUM];
 175         unsigned int rx_head;
 176         unsigned int rx_buf_size;
 177         unsigned int rx_cnt_remaining;
 178
 179         struct device_node *phy_node;
 180         struct phy_device *phy;
 181         struct regmap *map;
 182         struct work_struct tx_timeout_task;
 183
 184         /* written only by tx cleanup */
 185         unsigned int tx_tail ____cacheline_aligned_in_smp;
 186 };
 187
 188 static inline unsigned int tx_count(unsigned int head, unsigned int tail)
 189 {
 190         return (head - tail) % TX_DESC_NUM;
 191 }
 192
 193 static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex)
 194 {
 195         struct hip04_priv *priv = netdev_priv(ndev);
 196         u32 val;
 197
 198         priv->speed = speed;
 199         priv->duplex = duplex;
 200
 201         switch (priv->phy_mode) {
 202         case PHY_INTERFACE_MODE_SGMII:
 203                 if (speed == SPEED_1000)
 204                         val = SGMII_SPEED_1000;
 205                 else if (speed == SPEED_100)
 206                         val = SGMII_SPEED_100;
 207                 else
 208                         val = SGMII_SPEED_10;
 209                 break;
 210         case PHY_INTERFACE_MODE_MII:
 211                 if (speed == SPEED_100)
 212                         val = MII_SPEED_100;
 213                 else
 214                         val = MII_SPEED_10;
 215                 break;
 216         default:
 217                 netdev_warn(ndev, "not supported mode\n");
 218                 val = MII_SPEED_10;
 219                 break;
 220         }
 221         writel_relaxed(val, priv->base + GE_PORT_MODE);
 222
 223         val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
 224         writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
 225
 226         val = GE_MODE_CHANGE_EN;
 227         writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
 228 }
 229
 230 static void hip04_reset_ppe(struct hip04_priv *priv)
 231 {
 232         u32 val, tmp, timeout = 0;
 233
 234         do {
 235                 regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
 236                 regmap_read(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, &tmp);
 237                 if (timeout++ > RESET_TIMEOUT)
 238                         break;
 239         } while (val & 0xfff);
 240 }
 241
 242 static void hip04_config_fifo(struct hip04_priv *priv)
 243 {
 244         u32 val;
 245
 246         val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
 247         val |= PPE_CFG_STS_RX_PKT_CNT_RC;
 248         writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
 249
 250         val = BIT(priv->port);
 251         regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);
 252
 253         val = priv->port << PPE_CFG_QOS_VMID_GRP_SHIFT;
 254         val |= PPE_CFG_QOS_VMID_MODE;
 255         writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
 256
 257         val = RX_BUF_SIZE;
 258         regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);
 259
 260         val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT;
 261         val |= PPE_CFG_RX_FIFO_FSFU;
 262         val |= priv->chan << PPE_CFG_RX_START_SHIFT;
 263         regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);
 264
 265         val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT;
 266         writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
 267
 268         val = PPE_CFG_RX_PKT_ALIGN;
 269         writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
 270
 271         val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN;
 272         writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
 273
 274         val = GMAC_PPE_RX_PKT_MAX_LEN;
 275         writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
 276
 277         val = GMAC_MAX_PKT_LEN;
 278         writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
 279
 280         val = GMAC_MIN_PKT_LEN;
 281         writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
 282
 283         val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
 284         val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH;
 285         writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
 286
 287         val = GE_RX_STRIP_CRC;
 288         writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
 289
 290         val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
 291         val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN;
 292         writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
 293
 294         val = GE_AUTO_NEG_CTL;
 295         writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
 296 }
 297
 298 static void hip04_mac_enable(struct net_device *ndev)
 299 {
 300         struct hip04_priv *priv = netdev_priv(ndev);
 301         u32 val;
 302
 303         /* enable tx & rx */
 304         val = readl_relaxed(priv->base + GE_PORT_EN);
 305         val |= GE_RX_PORT_EN | GE_TX_PORT_EN;
 306         writel_relaxed(val, priv->base + GE_PORT_EN);
 307
 308         /* clear rx int */
 309         val = RCV_INT;
 310         writel_relaxed(val, priv->base + PPE_RINT);
 311
 312         /* config recv int */
 313         val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT;
 314         writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
 315
 316         /* enable interrupt */
 317         priv->reg_inten = DEF_INT_MASK;
 318         writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
 319 }
 320
 321 static void hip04_mac_disable(struct net_device *ndev)
 322 {
 323         struct hip04_priv *priv = netdev_priv(ndev);
 324         u32 val;
 325
 326         /* disable int */
 327         priv->reg_inten &= ~(DEF_INT_MASK);
 328         writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
 329
 330         /* disable tx & rx */
 331         val = readl_relaxed(priv->base + GE_PORT_EN);
 332         val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN);
 333         writel_relaxed(val, priv->base + GE_PORT_EN);
 334 }
 335
 336 static void hip04_set_xmit_desc(struct hip04_priv *priv, dma_addr_t phys)
 337 {
 338         writel(phys, priv->base + PPE_CFG_CPU_ADD_ADDR);
 339 }
 340
 341 static void hip04_set_recv_desc(struct hip04_priv *priv, dma_addr_t phys)
 342 {
 343         regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, phys);
 344 }
 345
 346 static u32 hip04_recv_cnt(struct hip04_priv *priv)
 347 {
 348         return readl(priv->base + PPE_HIS_RX_PKT_CNT);
 349 }
 350
 351 static void hip04_update_mac_address(struct net_device *ndev)
 352 {
 353         struct hip04_priv *priv = netdev_priv(ndev);
 354
 355         writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),
 356                        priv->base + GE_STATION_MAC_ADDRESS);
 357         writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
 358                         (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5])),
 359                        priv->base + GE_STATION_MAC_ADDRESS + 4);
 360 }
 361
 362 static int hip04_set_mac_address(struct net_device *ndev, void *addr)
 363 {
 364         eth_mac_addr(ndev, addr);
 365         hip04_update_mac_address(ndev);
 366         return 0;
 367 }
 368
 369 static int hip04_tx_reclaim(struct net_device *ndev, bool force)
 370 {
 371         struct hip04_priv *priv = netdev_priv(ndev);
 372         unsigned tx_tail = priv->tx_tail;
 373         struct tx_desc *desc;
 374         unsigned int bytes_compl = 0, pkts_compl = 0;
 375         unsigned int count;
 376
 377         smp_rmb();
 378         count = tx_count(ACCESS_ONCE(priv->tx_head), tx_tail);
 379         if (count == 0)
 380                 goto out;
 381
 382         while (count) {
 383                 desc = &priv->tx_desc[tx_tail];
 384                 if (desc->send_addr != 0) {
 385                         if (force)
 386                                 desc->send_addr = 0;
 387                         else
 388                                 break;
 389                 }
 390
 391                 if (priv->tx_phys[tx_tail]) {
 392                         dma_unmap_single(priv->dev, priv->tx_phys[tx_tail],
 393                                          priv->tx_skb[tx_tail]->len,
 394                                          DMA_TO_DEVICE);
 395                         priv->tx_phys[tx_tail] = 0;
 396                 }
 397                 pkts_compl++;
 398                 bytes_compl += priv->tx_skb[tx_tail]->len;
 399                 dev_kfree_skb(priv->tx_skb[tx_tail]);
 400                 priv->tx_skb[tx_tail] = NULL;
 401                 tx_tail = TX_NEXT(tx_tail);
 402                 count--;
 403         }
 404
 405         priv->tx_tail = tx_tail;
 406         smp_wmb(); /* Ensure tx_tail visible to xmit */
 407
 408 out:
 409         if (pkts_compl || bytes_compl)
 410                 netdev_completed_queue(ndev, pkts_compl, bytes_compl);
 411
 412         if (unlikely(netif_queue_stopped(ndev)) && (count < (TX_DESC_NUM - 1)))
 413                 netif_wake_queue(ndev);
 414
 415         return count;
 416 }
 417
 418 static void hip04_start_tx_timer(struct hip04_priv *priv)
 419 {
 420         unsigned long ns = priv->tx_coalesce_usecs * NSEC_PER_USEC / 2;
 421
 422         /* allow timer to fire after half the time at the earliest */
 423         hrtimer_start_range_ns(&priv->tx_coalesce_timer, ns_to_ktime(ns),
 424                                ns, HRTIMER_MODE_REL);
 425 }
 426
 427 static int hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 428 {
 429         struct hip04_priv *priv = netdev_priv(ndev);
 430         struct net_device_stats *stats = &ndev->stats;
 431         unsigned int tx_head = priv->tx_head, count;
 432         struct tx_desc *desc = &priv->tx_desc[tx_head];
 433         dma_addr_t phys;
 434
 435         smp_rmb();
 436         count = tx_count(tx_head, ACCESS_ONCE(priv->tx_tail));
 437         if (count == (TX_DESC_NUM - 1)) {
 438                 netif_stop_queue(ndev);
 439                 return NETDEV_TX_BUSY;
 440         }
 441
 442         phys = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE);
 443         if (dma_mapping_error(priv->dev, phys)) {
 444                 dev_kfree_skb(skb);
 445                 return NETDEV_TX_OK;
 446         }
 447
 448         priv->tx_skb[tx_head] = skb;
 449         priv->tx_phys[tx_head] = phys;
 450         desc->send_addr = cpu_to_be32(phys);
 451         desc->send_size = cpu_to_be32(skb->len);
 452         desc->cfg = cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV);
 453         phys = priv->tx_desc_dma + tx_head * sizeof(struct tx_desc);
 454         desc->wb_addr = cpu_to_be32(phys);
 455         skb_tx_timestamp(skb);
 456
 457         hip04_set_xmit_desc(priv, phys);
 458         count++;
 459         netdev_sent_queue(ndev, skb->len);
 460         priv->tx_head = TX_NEXT(tx_head);
 461
 462         stats->tx_bytes += skb->len;
 463         stats->tx_packets++;
 464
 465         /* Ensure tx_head update visible to tx reclaim */
 466         smp_wmb();
 467
 468         /* queue is getting full, better start cleaning up now */
 469         if (count >= priv->tx_coalesce_frames) {
 470                 if (napi_schedule_prep(&priv->napi)) {
 471                         /* disable rx interrupt and timer */
 472                         priv->reg_inten &= ~(RCV_INT);
 473                         writel_relaxed(DEF_INT_MASK & ~RCV_INT,
 474                                        priv->base + PPE_INTEN);
 475                         hrtimer_cancel(&priv->tx_coalesce_timer);
 476                         __napi_schedule(&priv->napi);
 477                 }
 478         } else if (!hrtimer_is_queued(&priv->tx_coalesce_timer)) {
 479                 /* cleanup not pending yet, start a new timer */
 480                 hip04_start_tx_timer(priv);
 481         }
 482
 483         return NETDEV_TX_OK;
 484 }
 485
 486 static int hip04_rx_poll(struct napi_struct *napi, int budget)
 487 {
 488         struct hip04_priv *priv = container_of(napi, struct hip04_priv, napi);
 489         struct net_device *ndev = priv->ndev;
 490         struct net_device_stats *stats = &ndev->stats;
 491         struct rx_desc *desc;
 492         struct sk_buff *skb;
 493         unsigned char *buf;
 494         bool last = false;
 495         dma_addr_t phys;
 496         int rx = 0;
 497         int tx_remaining;
 498         u16 len;
 499         u32 err;
 500
 501         /* clean up tx descriptors */
 502         tx_remaining = hip04_tx_reclaim(ndev, false);
 503         priv->rx_cnt_remaining += hip04_recv_cnt(priv);
 504         while (priv->rx_cnt_remaining && !last) {
 505                 buf = priv->rx_buf[priv->rx_head];
 506                 skb = build_skb(buf, priv->rx_buf_size);
 507                 if (unlikely(!skb))
 508                         net_dbg_ratelimited("build_skb failed\n");
 509
 510                 dma_unmap_single(priv->dev, priv->rx_phys[priv->rx_head],
 511                                  RX_BUF_SIZE, DMA_FROM_DEVICE);
 512                 priv->rx_phys[priv->rx_head] = 0;
 513
 514                 desc = (struct rx_desc *)skb->data;
 515                 len = be16_to_cpu(desc->pkt_len);
 516                 err = be32_to_cpu(desc->pkt_err);
 517
 518                 if (0 == len) {
 519                         dev_kfree_skb_any(skb);
 520                         last = true;
 521                 } else if ((err & RX_PKT_ERR) || (len >= GMAC_MAX_PKT_LEN)) {
 522                         dev_kfree_skb_any(skb);
 523                         stats->rx_dropped++;
 524                         stats->rx_errors++;
 525                 } else {
 526                         skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
 527                         skb_put(skb, len);
 528                         skb->protocol = eth_type_trans(skb, ndev);
 529                         napi_gro_receive(&priv->napi, skb);
 530                         stats->rx_packets++;
 531                         stats->rx_bytes += len;
 532                         rx++;
 533                 }
 534
 535                 buf = netdev_alloc_frag(priv->rx_buf_size);
 536                 if (!buf)
 537                         goto done;
 538                 phys = dma_map_single(priv->dev, buf,
 539                                       RX_BUF_SIZE, DMA_FROM_DEVICE);
 540                 if (dma_mapping_error(priv->dev, phys))
 541                         goto done;
 542                 priv->rx_buf[priv->rx_head] = buf;
 543                 priv->rx_phys[priv->rx_head] = phys;
 544                 hip04_set_recv_desc(priv, phys);
 545
 546                 priv->rx_head = RX_NEXT(priv->rx_head);
 547                 if (rx >= budget) {
 548                         --priv->rx_cnt_remaining;
 549                         goto done;
 550                 }
 551
 552                 if (--priv->rx_cnt_remaining == 0)
 553                         priv->rx_cnt_remaining += hip04_recv_cnt(priv);
 554         }
 555
 556         if (!(priv->reg_inten & RCV_INT)) {
 557                 /* enable rx interrupt */
 558                 priv->reg_inten |= RCV_INT;
 559                 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
 560         }
 561         napi_complete(napi);
 562 done:
 563         /* start a new timer if necessary */
 564         if (rx < budget && tx_remaining)
 565                 hip04_start_tx_timer(priv);
 566
 567         return rx;
 568 }
 569
 570 static irqreturn_t hip04_mac_interrupt(int irq, void *dev_id)
 571 {
 572         struct net_device *ndev = (struct net_device *)dev_id;
 573         struct hip04_priv *priv = netdev_priv(ndev);
 574         struct net_device_stats *stats = &ndev->stats;
 575         u32 ists = readl_relaxed(priv->base + PPE_INTSTS);
 576
 577         if (!ists)
 578                 return IRQ_NONE;
 579
 580         writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
 581
 582         if (unlikely(ists & DEF_INT_ERR)) {
 583                 if (ists & (RCV_NOBUF | RCV_DROP)) {
 584                         stats->rx_errors++;
 585                         stats->rx_dropped++;
 586                         netdev_err(ndev, "rx drop\n");
 587                 }
 588                 if (ists & TX_DROP) {
 589                         stats->tx_dropped++;
 590                         netdev_err(ndev, "tx drop\n");
 591                 }
 592         }
 593
 594         if (ists & RCV_INT && napi_schedule_prep(&priv->napi)) {
 595                 /* disable rx interrupt */
 596                 priv->reg_inten &= ~(RCV_INT);
 597                 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
 598                 hrtimer_cancel(&priv->tx_coalesce_timer);
 599                 __napi_schedule(&priv->napi);
 600         }
 601
 602         return IRQ_HANDLED;
 603 }
 604
 605 enum hrtimer_restart tx_done(struct hrtimer *hrtimer)
 606 {
 607         struct hip04_priv *priv;
 608
 609         priv = container_of(hrtimer, struct hip04_priv, tx_coalesce_timer);
 610
 611         if (napi_schedule_prep(&priv->napi)) {
 612                 /* disable rx interrupt */
 613                 priv->reg_inten &= ~(RCV_INT);
 614                 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
 615                 __napi_schedule(&priv->napi);
 616         }
 617
 618         return HRTIMER_NORESTART;
 619 }
 620
 621 static void hip04_adjust_link(struct net_device *ndev)
 622 {
 623         struct hip04_priv *priv = netdev_priv(ndev);
 624         struct phy_device *phy = priv->phy;
 625
 626         if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
 627                 hip04_config_port(ndev, phy->speed, phy->duplex);
 628                 phy_print_status(phy);
 629         }
 630 }
 631
 632 static int hip04_mac_open(struct net_device *ndev)
 633 {
 634         struct hip04_priv *priv = netdev_priv(ndev);
 635         int i;
 636
 637         priv->rx_head = 0;
 638         priv->rx_cnt_remaining = 0;
 639         priv->tx_head = 0;
 640         priv->tx_tail = 0;
 641         hip04_reset_ppe(priv);
 642
 643         for (i = 0; i < RX_DESC_NUM; i++) {
 644                 dma_addr_t phys;
 645
 646                 phys = dma_map_single(priv->dev, priv->rx_buf[i],
 647                                       RX_BUF_SIZE, DMA_FROM_DEVICE);
 648                 if (dma_mapping_error(priv->dev, phys))
 649                         return -EIO;
 650
 651                 priv->rx_phys[i] = phys;
 652                 hip04_set_recv_desc(priv, phys);
 653         }
 654
 655         if (priv->phy)
 656                 phy_start(priv->phy);
 657
 658         netdev_reset_queue(ndev);
 659         netif_start_queue(ndev);
 660         hip04_mac_enable(ndev);
 661         napi_enable(&priv->napi);
 662
 663         return 0;
 664 }
 665
 666 static int hip04_mac_stop(struct net_device *ndev)
 667 {
 668         struct hip04_priv *priv = netdev_priv(ndev);
 669         int i;
 670
 671         napi_disable(&priv->napi);
 672         netif_stop_queue(ndev);
 673         hip04_mac_disable(ndev);
 674         hip04_tx_reclaim(ndev, true);
 675         hip04_reset_ppe(priv);
 676
 677         if (priv->phy)
 678                 phy_stop(priv->phy);
 679
 680         for (i = 0; i < RX_DESC_NUM; i++) {
 681                 if (priv->rx_phys[i]) {
 682                         dma_unmap_single(priv->dev, priv->rx_phys[i],
 683                                          RX_BUF_SIZE, DMA_FROM_DEVICE);
 684                         priv->rx_phys[i] = 0;
 685                 }
 686         }
 687
 688         return 0;
 689 }
 690
 691 static void hip04_timeout(struct net_device *ndev)
 692 {
 693         struct hip04_priv *priv = netdev_priv(ndev);
 694
 695         schedule_work(&priv->tx_timeout_task);
 696 }
 697
 698 static void hip04_tx_timeout_task(struct work_struct *work)
 699 {
 700         struct hip04_priv *priv;
 701
 702         priv = container_of(work, struct hip04_priv, tx_timeout_task);
 703         hip04_mac_stop(priv->ndev);
 704         hip04_mac_open(priv->ndev);
 705 }
 706
 707 static struct net_device_stats *hip04_get_stats(struct net_device *ndev)
 708 {
 709         return &ndev->stats;
 710 }
 711
 712 static int hip04_get_coalesce(struct net_device *netdev,
 713                               struct ethtool_coalesce *ec)
 714 {
 715         struct hip04_priv *priv = netdev_priv(netdev);
 716
 717         ec->tx_coalesce_usecs = priv->tx_coalesce_usecs;
 718         ec->tx_max_coalesced_frames = priv->tx_coalesce_frames;
 719
 720         return 0;
 721 }
 722
 723 static int hip04_set_coalesce(struct net_device *netdev,
 724                               struct ethtool_coalesce *ec)
 725 {
 726         struct hip04_priv *priv = netdev_priv(netdev);
 727
 728         /* Check not supported parameters  */
 729         if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
 730             (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
 731             (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
 732             (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
 733             (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) ||
 734             (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) ||
 735             (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) ||
 736             (ec->rx_max_coalesced_frames_high) || (ec->rx_coalesce_usecs) ||
 737             (ec->tx_max_coalesced_frames_irq) ||
 738             (ec->stats_block_coalesce_usecs) ||
 739             (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval))
 740                 return -EOPNOTSUPP;
 741
 742         if ((ec->tx_coalesce_usecs > HIP04_MAX_TX_COALESCE_USECS ||
 743              ec->tx_coalesce_usecs < HIP04_MIN_TX_COALESCE_USECS) ||
 744             (ec->tx_max_coalesced_frames > HIP04_MAX_TX_COALESCE_FRAMES ||
 745              ec->tx_max_coalesced_frames < HIP04_MIN_TX_COALESCE_FRAMES))
 746                 return -EINVAL;
 747
 748         priv->tx_coalesce_usecs = ec->tx_coalesce_usecs;
 749         priv->tx_coalesce_frames = ec->tx_max_coalesced_frames;
 750
 751         return 0;
 752 }
 753
 754 static void hip04_get_drvinfo(struct net_device *netdev,
 755                               struct ethtool_drvinfo *drvinfo)
 756 {
 757         strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
 758         strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
 759 }
 760
 761 static struct ethtool_ops hip04_ethtool_ops = {
 762         .get_coalesce           = hip04_get_coalesce,
 763         .set_coalesce           = hip04_set_coalesce,
 764         .get_drvinfo            = hip04_get_drvinfo,
 765 };
 766
 767 static struct net_device_ops hip04_netdev_ops = {
 768         .ndo_open               = hip04_mac_open,
 769         .ndo_stop               = hip04_mac_stop,
 770         .ndo_get_stats          = hip04_get_stats,
 771         .ndo_start_xmit         = hip04_mac_start_xmit,
 772         .ndo_set_mac_address    = hip04_set_mac_address,
 773         .ndo_tx_timeout         = hip04_timeout,
 774         .ndo_validate_addr      = eth_validate_addr,
 775         .ndo_change_mtu         = eth_change_mtu,
 776 };
 777
 778 static int hip04_alloc_ring(struct net_device *ndev, struct device *d)
 779 {
 780         struct hip04_priv *priv = netdev_priv(ndev);
 781         int i;
 782
 783         priv->tx_desc = dma_alloc_coherent(d,
 784                                            TX_DESC_NUM * sizeof(struct tx_desc),
 785                                            &priv->tx_desc_dma, GFP_KERNEL);
 786         if (!priv->tx_desc)
 787                 return -ENOMEM;
 788
 789         priv->rx_buf_size = RX_BUF_SIZE +
 790                             SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 791         for (i = 0; i < RX_DESC_NUM; i++) {
 792                 priv->rx_buf[i] = netdev_alloc_frag(priv->rx_buf_size);
 793                 if (!priv->rx_buf[i])
 794                         return -ENOMEM;
 795         }
 796
 797         return 0;
 798 }
 799
 800 static void hip04_free_ring(struct net_device *ndev, struct device *d)
 801 {
 802         struct hip04_priv *priv = netdev_priv(ndev);
 803         int i;
 804
 805         for (i = 0; i < RX_DESC_NUM; i++)
 806                 if (priv->rx_buf[i])
 807                         skb_free_frag(priv->rx_buf[i]);
 808
 809         for (i = 0; i < TX_DESC_NUM; i++)
 810                 if (priv->tx_skb[i])
 811                         dev_kfree_skb_any(priv->tx_skb[i]);
 812
 813         dma_free_coherent(d, TX_DESC_NUM * sizeof(struct tx_desc),
 814                           priv->tx_desc, priv->tx_desc_dma);
 815 }
 816
 817 static int hip04_mac_probe(struct platform_device *pdev)
 818 {
 819         struct device *d = &pdev->dev;
 820         struct device_node *node = d->of_node;
 821         struct of_phandle_args arg;
 822         struct net_device *ndev;
 823         struct hip04_priv *priv;
 824         struct resource *res;
 825         int irq;
 826         int ret;
 827
 828         ndev = alloc_etherdev(sizeof(struct hip04_priv));
 829         if (!ndev)
 830                 return -ENOMEM;
 831
 832         priv = netdev_priv(ndev);
 833         priv->dev = d;
 834         priv->ndev = ndev;
 835         platform_set_drvdata(pdev, ndev);
 836
 837         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 838         priv->base = devm_ioremap_resource(d, res);
 839         if (IS_ERR(priv->base)) {
 840                 ret = PTR_ERR(priv->base);
 841                 goto init_fail;
 842         }
 843
 844         ret = of_parse_phandle_with_fixed_args(node, "port-handle", 2, 0, &arg);
 845         if (ret < 0) {
 846                 dev_warn(d, "no port-handle\n");
 847                 goto init_fail;
 848         }
 849
 850         priv->port = arg.args[0];
 851         priv->chan = arg.args[1] * RX_DESC_NUM;
 852
 853         hrtimer_init(&priv->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 854
 855         /* BQL will try to keep the TX queue as short as possible, but it can't
 856          * be faster than tx_coalesce_usecs, so we need a fast timeout here,
 857          * but also long enough to gather up enough frames to ensure we don't
 858          * get more interrupts than necessary.
 859          * 200us is enough for 16 frames of 1500 bytes at gigabit ethernet rate
 860          */
 861         priv->tx_coalesce_frames = TX_DESC_NUM * 3 / 4;
 862         priv->tx_coalesce_usecs = 200;
 863         priv->tx_coalesce_timer.function = tx_done;
 864
 865         priv->map = syscon_node_to_regmap(arg.np);
 866         if (IS_ERR(priv->map)) {
 867                 dev_warn(d, "no syscon hisilicon,hip04-ppe\n");
 868                 ret = PTR_ERR(priv->map);
 869                 goto init_fail;
 870         }
 871
 872         priv->phy_mode = of_get_phy_mode(node);
 873         if (priv->phy_mode < 0) {
 874                 dev_warn(d, "not find phy-mode\n");
 875                 ret = -EINVAL;
 876                 goto init_fail;
 877         }
 878
 879         irq = platform_get_irq(pdev, 0);
 880         if (irq <= 0) {
 881                 ret = -EINVAL;
 882                 goto init_fail;
 883         }
 884
 885         ret = devm_request_irq(d, irq, hip04_mac_interrupt,
 886                                0, pdev->name, ndev);
 887         if (ret) {
 888                 netdev_err(ndev, "devm_request_irq failed\n");
 889                 goto init_fail;
 890         }
 891
 892         priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
 893         if (priv->phy_node) {
 894                 priv->phy = of_phy_connect(ndev, priv->phy_node,
 895                                            &hip04_adjust_link,
 896                                            0, priv->phy_mode);
 897                 if (!priv->phy) {
 898                         ret = -EPROBE_DEFER;
 899                         goto init_fail;
 900                 }
 901         }
 902
 903         INIT_WORK(&priv->tx_timeout_task, hip04_tx_timeout_task);
 904
 905         ether_setup(ndev);
 906         ndev->netdev_ops = &hip04_netdev_ops;
 907         ndev->ethtool_ops = &hip04_ethtool_ops;
 908         ndev->watchdog_timeo = TX_TIMEOUT;
 909         ndev->priv_flags |= IFF_UNICAST_FLT;
 910         ndev->irq = irq;
 911         netif_napi_add(ndev, &priv->napi, hip04_rx_poll, NAPI_POLL_WEIGHT);
 912         SET_NETDEV_DEV(ndev, &pdev->dev);
 913
 914         hip04_reset_ppe(priv);
 915         if (priv->phy_mode == PHY_INTERFACE_MODE_MII)
 916                 hip04_config_port(ndev, SPEED_100, DUPLEX_FULL);
 917
 918         hip04_config_fifo(priv);
 919         random_ether_addr(ndev->dev_addr);
 920         hip04_update_mac_address(ndev);
 921
 922         ret = hip04_alloc_ring(ndev, d);
 923         if (ret) {
 924                 netdev_err(ndev, "alloc ring fail\n");
 925                 goto alloc_fail;
 926         }
 927
 928         ret = register_netdev(ndev);
 929         if (ret)
 930                 goto alloc_fail;
 931
 932         return 0;
 933
 934 alloc_fail:
 935         hip04_free_ring(ndev, d);
 936 init_fail:
 937         of_node_put(priv->phy_node);
 938         free_netdev(ndev);
 939         return ret;
 940 }
 941
 942 static int hip04_remove(struct platform_device *pdev)
 943 {
 944         struct net_device *ndev = platform_get_drvdata(pdev);
 945         struct hip04_priv *priv = netdev_priv(ndev);
 946         struct device *d = &pdev->dev;
 947
 948         if (priv->phy)
 949                 phy_disconnect(priv->phy);
 950
 951         hip04_free_ring(ndev, d);
 952         unregister_netdev(ndev);
 953         of_node_put(priv->phy_node);
 954         cancel_work_sync(&priv->tx_timeout_task);
 955         free_netdev(ndev);
 956
 957         return 0;
 958 }
 959
 960 static const struct of_device_id hip04_mac_match[] = {
 961         { .compatible = "hisilicon,hip04-mac" },
 962         { }
 963 };
 964
 965 MODULE_DEVICE_TABLE(of, hip04_mac_match);
 966
 967 static struct platform_driver hip04_mac_driver = {
 968         .probe  = hip04_mac_probe,
 969         .remove = hip04_remove,
 970         .driver = {
 971                 .name           = DRV_NAME,
 972                 .of_match_table = hip04_mac_match,
 973         },
 974 };
 975 module_platform_driver(hip04_mac_driver);
 976
 977 MODULE_DESCRIPTION("HISILICON P04 Ethernet driver");
 978 MODULE_LICENSE("GPL");