drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include "hclge_main.h"
   5 #include "hclge_tm.h"
   6 #include "hnae3.h"
   7
   8 #define BW_PERCENT      100
   9
  10 static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev,
  11                                      struct ieee_ets *ets)
  12 {
  13         u8 i;
  14
  15         for (i = 0; i < HNAE3_MAX_TC; i++) {
  16                 switch (ets->tc_tsa[i]) {
  17                 case IEEE_8021QAZ_TSA_STRICT:
  18                         hdev->tm_info.tc_info[i].tc_sch_mode =
  19                                 HCLGE_SCH_MODE_SP;
  20                         hdev->tm_info.pg_info[0].tc_dwrr[i] = 0;
  21                         break;
  22                 case IEEE_8021QAZ_TSA_ETS:
  23                         hdev->tm_info.tc_info[i].tc_sch_mode =
  24                                 HCLGE_SCH_MODE_DWRR;
  25                         hdev->tm_info.pg_info[0].tc_dwrr[i] =
  26                                 ets->tc_tx_bw[i];
  27                         break;
  28                 default:
  29                         /* Hardware only supports SP (strict priority)
  30                          * or ETS (enhanced transmission selection)
  31                          * algorithms, if we receive some other value
  32                          * from dcbnl, then throw an error.
  33                          */
  34                         return -EINVAL;
  35                 }
  36         }
  37
  38         return hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);
  39 }
  40
  41 static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
  42                                       struct ieee_ets *ets)
  43 {
  44         u32 i;
  45
  46         memset(ets, 0, sizeof(*ets));
  47         ets->willing = 1;
  48         ets->ets_cap = hdev->tc_max;
  49
  50         for (i = 0; i < HNAE3_MAX_TC; i++) {
  51                 ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
  52                 ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
  53
  54                 if (hdev->tm_info.tc_info[i].tc_sch_mode ==
  55                     HCLGE_SCH_MODE_SP)
  56                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;
  57                 else
  58                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
  59         }
  60 }
  61
  62 /* IEEE std */
  63 static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)
  64 {
  65         struct hclge_vport *vport = hclge_get_vport(h);
  66         struct hclge_dev *hdev = vport->back;
  67
  68         hclge_tm_info_to_ieee_ets(hdev, ets);
  69
  70         return 0;
  71 }
  72
  73 static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
  74                               u8 *tc, bool *changed)
  75 {
  76         bool has_ets_tc = false;
  77         u32 total_ets_bw = 0;
  78         u8 max_tc = 0;
  79         u8 i;
  80
  81         for (i = 0; i < HNAE3_MAX_TC; i++) {
  82                 if (ets->prio_tc[i] >= hdev->tc_max ||
  83                     i >= hdev->tc_max)
  84                         return -EINVAL;
  85
  86                 if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
  87                         *changed = true;
  88
  89                 if (ets->prio_tc[i] > max_tc)
  90                         max_tc = ets->prio_tc[i];
  91
  92                 switch (ets->tc_tsa[i]) {
  93                 case IEEE_8021QAZ_TSA_STRICT:
  94                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
  95                                 HCLGE_SCH_MODE_SP)
  96                                 *changed = true;
  97                         break;
  98                 case IEEE_8021QAZ_TSA_ETS:
  99                         /* The hardware will switch to sp mode if bandwidth is
 100                          * 0, so limit ets bandwidth must be greater than 0.
 101                          */
 102                         if (!ets->tc_tx_bw[i]) {
 103                                 dev_err(&hdev->pdev->dev,
 104                                         "tc%u ets bw cannot be 0\n", i);
 105                                 return -EINVAL;
 106                         }
 107
 108                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
 109                                 HCLGE_SCH_MODE_DWRR)
 110                                 *changed = true;
 111
 112                         total_ets_bw += ets->tc_tx_bw[i];
 113                         has_ets_tc = true;
 114                         break;
 115                 default:
 116                         return -EINVAL;
 117                 }
 118         }
 119
 120         if (has_ets_tc && total_ets_bw != BW_PERCENT)
 121                 return -EINVAL;
 122
 123         *tc = max_tc + 1;
 124         if (*tc != hdev->tm_info.num_tc)
 125                 *changed = true;
 126
 127         return 0;
 128 }
 129
 130 static int hclge_map_update(struct hnae3_handle *h)
 131 {
 132         struct hclge_vport *vport = hclge_get_vport(h);
 133         struct hclge_dev *hdev = vport->back;
 134         int ret;
 135
 136         ret = hclge_tm_map_cfg(hdev);
 137         if (ret)
 138                 return ret;
 139
 140         ret = hclge_tm_schd_mode_hw(hdev);
 141         if (ret)
 142                 return ret;
 143
 144         ret = hclge_pause_setup_hw(hdev);
 145         if (ret)
 146                 return ret;
 147
 148         ret = hclge_buffer_alloc(hdev);
 149         if (ret)
 150                 return ret;
 151
 152         hclge_rss_indir_init_cfg(hdev);
 153
 154         return hclge_rss_init_hw(hdev);
 155 }
 156
 157 static int hclge_client_setup_tc(struct hclge_dev *hdev)
 158 {
 159         struct hclge_vport *vport = hdev->vport;
 160         struct hnae3_client *client;
 161         struct hnae3_handle *handle;
 162         int ret;
 163         u32 i;
 164
 165         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
 166                 handle = &vport[i].nic;
 167                 client = handle->client;
 168
 169                 if (!client || !client->ops || !client->ops->setup_tc)
 170                         continue;
 171
 172                 ret = client->ops->setup_tc(handle, hdev->tm_info.num_tc);
 173                 if (ret)
 174                         return ret;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
 181 {
 182         struct hclge_vport *vport = hclge_get_vport(h);
 183         struct hclge_dev *hdev = vport->back;
 184         bool map_changed = false;
 185         u8 num_tc = 0;
 186         int ret;
 187
 188         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 189             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 190                 return -EINVAL;
 191
 192         ret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed);
 193         if (ret)
 194                 return ret;
 195
 196         hclge_tm_schd_info_update(hdev, num_tc);
 197
 198         ret = hclge_ieee_ets_to_tm_info(hdev, ets);
 199         if (ret)
 200                 return ret;
 201
 202         if (map_changed) {
 203                 ret = hclge_client_setup_tc(hdev);
 204                 if (ret)
 205                         return ret;
 206         }
 207
 208         return hclge_tm_dwrr_cfg(hdev);
 209 }
 210
 211 static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 212 {
 213         u64 requests[HNAE3_MAX_TC], indications[HNAE3_MAX_TC];
 214         struct hclge_vport *vport = hclge_get_vport(h);
 215         struct hclge_dev *hdev = vport->back;
 216         int ret;
 217         u8 i;
 218
 219         memset(pfc, 0, sizeof(*pfc));
 220         pfc->pfc_cap = hdev->pfc_max;
 221         pfc->pfc_en = hdev->tm_info.pfc_en;
 222
 223         ret = hclge_pfc_tx_stats_get(hdev, requests);
 224         if (ret)
 225                 return ret;
 226
 227         ret = hclge_pfc_rx_stats_get(hdev, indications);
 228         if (ret)
 229                 return ret;
 230
 231         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
 232                 pfc->requests[i] = requests[i];
 233                 pfc->indications[i] = indications[i];
 234         }
 235         return 0;
 236 }
 237
 238 static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 239 {
 240         struct hclge_vport *vport = hclge_get_vport(h);
 241         struct hclge_dev *hdev = vport->back;
 242         u8 i, j, pfc_map, *prio_tc;
 243
 244         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 245             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 246                 return -EINVAL;
 247
 248         if (pfc->pfc_en == hdev->tm_info.pfc_en)
 249                 return 0;
 250
 251         prio_tc = hdev->tm_info.prio_tc;
 252         pfc_map = 0;
 253
 254         for (i = 0; i < hdev->tm_info.num_tc; i++) {
 255                 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
 256                         if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) {
 257                                 pfc_map |= BIT(i);
 258                                 break;
 259                         }
 260                 }
 261         }
 262
 263         hdev->tm_info.hw_pfc_map = pfc_map;
 264         hdev->tm_info.pfc_en = pfc->pfc_en;
 265
 266         return hclge_pause_setup_hw(hdev);
 267 }
 268
 269 /* DCBX configuration */
 270 static u8 hclge_getdcbx(struct hnae3_handle *h)
 271 {
 272         struct hclge_vport *vport = hclge_get_vport(h);
 273         struct hclge_dev *hdev = vport->back;
 274
 275         if (hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 276                 return 0;
 277
 278         return hdev->dcbx_cap;
 279 }
 280
 281 static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode)
 282 {
 283         struct hclge_vport *vport = hclge_get_vport(h);
 284         struct hclge_dev *hdev = vport->back;
 285
 286         /* No support for LLD_MANAGED modes or CEE */
 287         if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
 288             (mode & DCB_CAP_DCBX_VER_CEE) ||
 289             !(mode & DCB_CAP_DCBX_HOST))
 290                 return 1;
 291
 292         hdev->dcbx_cap = mode;
 293
 294         return 0;
 295 }
 296
 297 /* Set up TC for hardware offloaded mqprio in channel mode */
 298 static int hclge_setup_tc(struct hnae3_handle *h, u8 tc, u8 *prio_tc)
 299 {
 300         struct hclge_vport *vport = hclge_get_vport(h);
 301         struct hclge_dev *hdev = vport->back;
 302         int ret;
 303
 304         if (hdev->flag & HCLGE_FLAG_DCB_ENABLE)
 305                 return -EINVAL;
 306
 307         if (tc > hdev->tc_max) {
 308                 dev_err(&hdev->pdev->dev,
 309                         "setup tc failed, tc(%u) > tc_max(%u)\n",
 310                         tc, hdev->tc_max);
 311                 return -EINVAL;
 312         }
 313
 314         hclge_tm_schd_info_update(hdev, tc);
 315
 316         ret = hclge_tm_prio_tc_info_update(hdev, prio_tc);
 317         if (ret)
 318                 return ret;
 319
 320         ret = hclge_tm_init_hw(hdev);
 321         if (ret)
 322                 return ret;
 323
 324         hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
 325
 326         if (tc > 1)
 327                 hdev->flag |= HCLGE_FLAG_MQPRIO_ENABLE;
 328         else
 329                 hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE;
 330
 331         return 0;
 332 }
 333
 334 static const struct hnae3_dcb_ops hns3_dcb_ops = {
 335         .ieee_getets    = hclge_ieee_getets,
 336         .ieee_setets    = hclge_ieee_setets,
 337         .ieee_getpfc    = hclge_ieee_getpfc,
 338         .ieee_setpfc    = hclge_ieee_setpfc,
 339         .getdcbx        = hclge_getdcbx,
 340         .setdcbx        = hclge_setdcbx,
 341         .map_update     = hclge_map_update,
 342         .setup_tc       = hclge_setup_tc,
 343 };
 344
 345 void hclge_dcb_ops_set(struct hclge_dev *hdev)
 346 {
 347         struct hclge_vport *vport = hdev->vport;
 348         struct hnae3_knic_private_info *kinfo;
 349
 350         /* Hdev does not support DCB or vport is
 351          * not a pf, then dcb_ops is not set.
 352          */
 353         if (!hnae3_dev_dcb_supported(hdev) ||
 354             vport->vport_id != 0)
 355                 return;
 356
 357         kinfo = &vport->nic.kinfo;
 358         kinfo->dcb_ops = &hns3_dcb_ops;
 359         hdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST;
 360 }