drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c

   1 /*
   2  * Copyright (c) 2016~2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/etherdevice.h>
  11 #include <linux/kernel.h>
  12
  13 #include "hclge_cmd.h"
  14 #include "hclge_main.h"
  15 #include "hclge_mdio.h"
  16
  17 enum hclge_mdio_c22_op_seq {
  18         HCLGE_MDIO_C22_WRITE = 1,
  19         HCLGE_MDIO_C22_READ = 2
  20 };
  21
  22 #define HCLGE_MDIO_CTRL_START_B         0
  23 #define HCLGE_MDIO_CTRL_ST_S            1
  24 #define HCLGE_MDIO_CTRL_ST_M            (0x3 << HCLGE_MDIO_CTRL_ST_S)
  25 #define HCLGE_MDIO_CTRL_OP_S            3
  26 #define HCLGE_MDIO_CTRL_OP_M            (0x3 << HCLGE_MDIO_CTRL_OP_S)
  27
  28 #define HCLGE_MDIO_PHYID_S              0
  29 #define HCLGE_MDIO_PHYID_M              (0x1f << HCLGE_MDIO_PHYID_S)
  30
  31 #define HCLGE_MDIO_PHYREG_S             0
  32 #define HCLGE_MDIO_PHYREG_M             (0x1f << HCLGE_MDIO_PHYREG_S)
  33
  34 #define HCLGE_MDIO_STA_B                0
  35
  36 struct hclge_mdio_cfg_cmd {
  37         u8 ctrl_bit;
  38         u8 phyid;
  39         u8 phyad;
  40         u8 rsvd;
  41         __le16 reserve;
  42         __le16 data_wr;
  43         __le16 data_rd;
  44         __le16 sta;
  45 };
  46
  47 static int hclge_mdio_write(struct mii_bus *bus, int phyid, int regnum,
  48                             u16 data)
  49 {
  50         struct hclge_mdio_cfg_cmd *mdio_cmd;
  51         struct hclge_dev *hdev = bus->priv;
  52         struct hclge_desc desc;
  53         int ret;
  54
  55         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, false);
  56
  57         mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
  58
  59         hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
  60                        HCLGE_MDIO_PHYID_S, phyid);
  61         hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
  62                        HCLGE_MDIO_PHYREG_S, regnum);
  63
  64         hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
  65         hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
  66                        HCLGE_MDIO_CTRL_ST_S, 1);
  67         hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,
  68                        HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_WRITE);
  69
  70         mdio_cmd->data_wr = cpu_to_le16(data);
  71
  72         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
  73         if (ret) {
  74                 dev_err(&hdev->pdev->dev,
  75                         "mdio write fail when sending cmd, status is %d.\n",
  76                         ret);
  77                 return ret;
  78         }
  79
  80         return 0;
  81 }
  82
  83 static int hclge_mdio_read(struct mii_bus *bus, int phyid, int regnum)
  84 {
  85         struct hclge_mdio_cfg_cmd *mdio_cmd;
  86         struct hclge_dev *hdev = bus->priv;
  87         struct hclge_desc desc;
  88         int ret;
  89
  90         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, true);
  91
  92         mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
  93
  94         hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
  95                        HCLGE_MDIO_PHYID_S, phyid);
  96         hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
  97                        HCLGE_MDIO_PHYREG_S, regnum);
  98
  99         hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
 100         hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
 101                        HCLGE_MDIO_CTRL_ST_S, 1);
 102         hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,
 103                        HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_READ);
 104
 105         /* Read out phy data */
 106         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 107         if (ret) {
 108                 dev_err(&hdev->pdev->dev,
 109                         "mdio read fail when get data, status is %d.\n",
 110                         ret);
 111                 return ret;
 112         }
 113
 114         if (hnae_get_bit(le16_to_cpu(mdio_cmd->sta), HCLGE_MDIO_STA_B)) {
 115                 dev_err(&hdev->pdev->dev, "mdio read data error\n");
 116                 return -EIO;
 117         }
 118
 119         return le16_to_cpu(mdio_cmd->data_rd);
 120 }
 121
 122 int hclge_mac_mdio_config(struct hclge_dev *hdev)
 123 {
 124         struct hclge_mac *mac = &hdev->hw.mac;
 125         struct phy_device *phydev;
 126         struct mii_bus *mdio_bus;
 127         int ret;
 128
 129         if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR)
 130                 return 0;
 131
 132         mdio_bus = devm_mdiobus_alloc(&hdev->pdev->dev);
 133         if (!mdio_bus)
 134                 return -ENOMEM;
 135
 136         mdio_bus->name = "hisilicon MII bus";
 137         mdio_bus->read = hclge_mdio_read;
 138         mdio_bus->write = hclge_mdio_write;
 139         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii",
 140                  dev_name(&hdev->pdev->dev));
 141
 142         mdio_bus->parent = &hdev->pdev->dev;
 143         mdio_bus->priv = hdev;
 144         mdio_bus->phy_mask = ~(1 << mac->phy_addr);
 145         ret = mdiobus_register(mdio_bus);
 146         if (ret) {
 147                 dev_err(mdio_bus->parent,
 148                         "Failed to register MDIO bus ret = %#x\n", ret);
 149                 return ret;
 150         }
 151
 152         phydev = mdiobus_get_phy(mdio_bus, mac->phy_addr);
 153         if (!phydev) {
 154                 dev_err(mdio_bus->parent, "Failed to get phy device\n");
 155                 mdiobus_unregister(mdio_bus);
 156                 return -EIO;
 157         }
 158
 159         mac->phydev = phydev;
 160         mac->mdio_bus = mdio_bus;
 161
 162         return 0;
 163 }
 164
 165 static void hclge_mac_adjust_link(struct net_device *netdev)
 166 {
 167         struct hnae3_handle *h = *((void **)netdev_priv(netdev));
 168         struct hclge_vport *vport = hclge_get_vport(h);
 169         struct hclge_dev *hdev = vport->back;
 170         int duplex, speed;
 171         int ret;
 172
 173         speed = netdev->phydev->speed;
 174         duplex = netdev->phydev->duplex;
 175
 176         ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
 177         if (ret)
 178                 netdev_err(netdev, "failed to adjust link.\n");
 179 }
 180
 181 int hclge_mac_start_phy(struct hclge_dev *hdev)
 182 {
 183         struct net_device *netdev = hdev->vport[0].nic.netdev;
 184         struct phy_device *phydev = hdev->hw.mac.phydev;
 185         int ret;
 186
 187         if (!phydev)
 188                 return 0;
 189
 190         phydev->supported &= ~SUPPORTED_FIBRE;
 191
 192         ret = phy_connect_direct(netdev, phydev,
 193                                  hclge_mac_adjust_link,
 194                                  PHY_INTERFACE_MODE_SGMII);
 195         if (ret) {
 196                 netdev_err(netdev, "phy_connect_direct err.\n");
 197                 return ret;
 198         }
 199
 200         phy_start(phydev);
 201
 202         return 0;
 203 }
 204
 205 void hclge_mac_stop_phy(struct hclge_dev *hdev)
 206 {
 207         struct net_device *netdev = hdev->vport[0].nic.netdev;
 208         struct phy_device *phydev = netdev->phydev;
 209
 210         if (!phydev)
 211                 return;
 212
 213         phy_stop(phydev);
 214         phy_disconnect(phydev);
 215 }