2 * Copyright (c) 2016 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
15 extern const char hns3_driver_version[];
18 HNS3_NIC_STATE_TESTING,
19 HNS3_NIC_STATE_RESETTING,
20 HNS3_NIC_STATE_REINITING,
22 HNS3_NIC_STATE_DISABLED,
23 HNS3_NIC_STATE_REMOVING,
24 HNS3_NIC_STATE_SERVICE_INITED,
25 HNS3_NIC_STATE_SERVICE_SCHED,
26 HNS3_NIC_STATE2_RESET_REQUESTED,
30 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
31 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
32 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
33 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
34 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
35 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
36 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
37 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
39 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
40 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
41 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
42 #define HNS3_RING_TX_RING_BD_LEN_REG 0x0004C
43 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
44 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
45 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
46 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
47 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
49 #define HNS3_RING_PREFETCH_EN_REG 0x0007C
50 #define HNS3_RING_CFG_VF_NUM_REG 0x00080
51 #define HNS3_RING_ASID_REG 0x0008C
52 #define HNS3_RING_RX_VM_REG 0x00090
53 #define HNS3_RING_T0_BE_RST 0x00094
54 #define HNS3_RING_COULD_BE_RST 0x00098
55 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c
57 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0
58 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
59 #define HNS3_RX_RING_INT_STS_REG 0x000A8
60 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC
61 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
62 #define HNS3_TX_RING_INT_STS_REG 0x000B4
63 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
64 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
65 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
66 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
68 #define HNS3_RING_MB_CTRL_REG 0x00100
69 #define HNS3_RING_MB_DATA_BASE_REG 0x00200
71 #define HNS3_TX_REG_OFFSET 0x40
73 #define HNS3_RX_HEAD_SIZE 256
75 #define HNS3_TX_TIMEOUT (5 * HZ)
76 #define HNS3_RING_NAME_LEN 16
77 #define HNS3_BUFFER_SIZE_2048 2048
78 #define HNS3_RING_MAX_PENDING 32768
79 #define HNS3_MAX_MTU 9728
81 #define HNS3_BD_SIZE_512_TYPE 0
82 #define HNS3_BD_SIZE_1024_TYPE 1
83 #define HNS3_BD_SIZE_2048_TYPE 2
84 #define HNS3_BD_SIZE_4096_TYPE 3
86 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
87 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
88 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
89 #define HNS3_RX_FLAG_L4ID_UDP 0x0
90 #define HNS3_RX_FLAG_L4ID_TCP 0x1
92 #define HNS3_RXD_DMAC_S 0
93 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
94 #define HNS3_RXD_VLAN_S 2
95 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
96 #define HNS3_RXD_L3ID_S 4
97 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
98 #define HNS3_RXD_L4ID_S 8
99 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
100 #define HNS3_RXD_FRAG_B 12
101 #define HNS3_RXD_L2E_B 16
102 #define HNS3_RXD_L3E_B 17
103 #define HNS3_RXD_L4E_B 18
104 #define HNS3_RXD_TRUNCAT_B 19
105 #define HNS3_RXD_HOI_B 20
106 #define HNS3_RXD_DOI_B 21
107 #define HNS3_RXD_OL3E_B 22
108 #define HNS3_RXD_OL4E_B 23
110 #define HNS3_RXD_ODMAC_S 0
111 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
112 #define HNS3_RXD_OVLAN_S 2
113 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
114 #define HNS3_RXD_OL3ID_S 4
115 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
116 #define HNS3_RXD_OL4ID_S 8
117 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
118 #define HNS3_RXD_FBHI_S 12
119 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
120 #define HNS3_RXD_FBLI_S 14
121 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
123 #define HNS3_RXD_BDTYPE_S 0
124 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
125 #define HNS3_RXD_VLD_B 4
126 #define HNS3_RXD_UDP0_B 5
127 #define HNS3_RXD_EXTEND_B 7
128 #define HNS3_RXD_FE_B 8
129 #define HNS3_RXD_LUM_B 9
130 #define HNS3_RXD_CRCP_B 10
131 #define HNS3_RXD_L3L4P_B 11
132 #define HNS3_RXD_TSIND_S 12
133 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
134 #define HNS3_RXD_LKBK_B 15
135 #define HNS3_RXD_HDL_S 16
136 #define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S)
137 #define HNS3_RXD_HSIND_B 31
139 #define HNS3_TXD_L3T_S 0
140 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
141 #define HNS3_TXD_L4T_S 2
142 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
143 #define HNS3_TXD_L3CS_B 4
144 #define HNS3_TXD_L4CS_B 5
145 #define HNS3_TXD_VLAN_B 6
146 #define HNS3_TXD_TSO_B 7
148 #define HNS3_TXD_L2LEN_S 8
149 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
150 #define HNS3_TXD_L3LEN_S 16
151 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
152 #define HNS3_TXD_L4LEN_S 24
153 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
155 #define HNS3_TXD_OL3T_S 0
156 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
157 #define HNS3_TXD_OVLAN_B 2
158 #define HNS3_TXD_MACSEC_B 3
159 #define HNS3_TXD_TUNTYPE_S 4
160 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
162 #define HNS3_TXD_BDTYPE_S 0
163 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
164 #define HNS3_TXD_FE_B 4
165 #define HNS3_TXD_SC_S 5
166 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
167 #define HNS3_TXD_EXTEND_B 7
168 #define HNS3_TXD_VLD_B 8
169 #define HNS3_TXD_RI_B 9
170 #define HNS3_TXD_RA_B 10
171 #define HNS3_TXD_TSYN_B 11
172 #define HNS3_TXD_DECTTL_S 12
173 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
175 #define HNS3_TXD_MSS_S 0
176 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
178 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
179 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
181 #define HNS3_VECTOR_NOT_INITED 0
182 #define HNS3_VECTOR_INITED 1
184 #define HNS3_MAX_BD_SIZE 65535
185 #define HNS3_MAX_BD_PER_FRAG 8
186 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
188 #define HNS3_VECTOR_GL0_OFFSET 0x100
189 #define HNS3_VECTOR_GL1_OFFSET 0x200
190 #define HNS3_VECTOR_GL2_OFFSET 0x300
191 #define HNS3_VECTOR_RL_OFFSET 0x900
192 #define HNS3_VECTOR_RL_EN_B 6
194 enum hns3_pkt_l3t_type {
201 enum hns3_pkt_l4t_type {
208 enum hns3_pkt_ol3t_type {
211 HNS3_OL3T_IPV4_NO_CSUM,
215 enum hns3_pkt_tun_type {
222 /* hardware spec ring buffer format */
223 struct __packed hns3_desc {
230 __le32 type_cs_vlan_tso_len;
232 __u8 type_cs_vlan_tso;
238 __le16 outer_vlan_tag;
242 __le32 ol_type_vlan_len_msec;
244 __u8 ol_type_vlan_msec;
252 __le16 bdtp_fe_sc_vld_ra_ri;
268 __le16 o_dm_vlan_id_fb;
278 struct hns3_desc_cb {
279 dma_addr_t dma; /* dma address of this desc */
280 void *buf; /* cpu addr for a desc */
282 /* priv data for the desc, e.g. skb when use with ip stack*/
287 u16 length; /* length of the buffer */
289 /* desc type, used by the ring user to mark the type of the priv data */
293 enum hns3_pkt_l3type {
298 HNS3_L3_TYPE_IPV4_OPT,
299 HNS3_L3_TYPE_IPV6_EXT,
302 HNS3_L3_TYPE_MAC_PAUSE,
303 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
305 /* reserved for 0xA~0xB*/
307 HNS3_L3_TYPE_CNM = 0xc,
309 /* reserved for 0xD~0xE*/
311 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
314 enum hns3_pkt_l4type {
322 /* reserved for 0x6~0xE */
324 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
327 enum hns3_pkt_ol3type {
328 HNS3_OL3_TYPE_IPV4 = 0,
330 /* reserved for 0x2~0x3 */
331 HNS3_OL3_TYPE_IPV4_OPT = 4,
332 HNS3_OL3_TYPE_IPV6_EXT,
334 /* reserved for 0x6~0xE*/
336 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
339 enum hns3_pkt_ol4type {
340 HNS3_OL4_TYPE_NO_TUN,
341 HNS3_OL4_TYPE_MAC_IN_UDP,
343 HNS3_OL4_TYPE_UNKNOWN
372 struct hns3_enet_ring {
373 u8 __iomem *io_base; /* base io address for the ring */
374 struct hns3_desc *desc; /* dma map address space */
375 struct hns3_desc_cb *desc_cb;
376 struct hns3_enet_ring *next;
377 struct hns3_enet_tqp_vector *tqp_vector;
378 struct hnae3_queue *tqp;
379 char ring_name[HNS3_RING_NAME_LEN];
380 struct device *dev; /* will be used for DMA mapping of descriptors */
383 struct ring_stats stats;
384 struct u64_stats_sync syncp;
386 dma_addr_t desc_dma_addr;
387 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
388 u16 desc_num; /* total number of desc */
389 u16 max_desc_num_per_pkt;
390 u16 max_raw_data_sz_per_desc;
392 int next_to_use; /* idx of next spare desc */
394 /* idx of lastest sent desc, the ring is empty when equal to
399 u32 flag; /* ring attribute */
403 cpumask_t affinity_mask;
408 struct hns3_nic_ring_data {
409 struct hns3_enet_ring *ring;
410 struct napi_struct napi;
412 int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
413 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
414 void (*fini_process)(struct hns3_nic_ring_data *);
417 struct hns3_nic_ops {
418 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv,
419 int size, dma_addr_t dma, int frag_end,
420 enum hns_desc_type type);
421 int (*maybe_stop_tx)(struct sk_buff **out_skb,
422 int *bnum, struct hns3_enet_ring *ring);
423 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum);
426 enum hns3_flow_level_range {
433 enum hns3_link_mode_bits {
434 HNS3_LM_FIBRE_BIT = BIT(0),
435 HNS3_LM_AUTONEG_BIT = BIT(1),
436 HNS3_LM_TP_BIT = BIT(2),
437 HNS3_LM_PAUSE_BIT = BIT(3),
438 HNS3_LM_BACKPLANE_BIT = BIT(4),
439 HNS3_LM_10BASET_HALF_BIT = BIT(5),
440 HNS3_LM_10BASET_FULL_BIT = BIT(6),
441 HNS3_LM_100BASET_HALF_BIT = BIT(7),
442 HNS3_LM_100BASET_FULL_BIT = BIT(8),
443 HNS3_LM_1000BASET_FULL_BIT = BIT(9),
444 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
445 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
446 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
447 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
448 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
452 #define HNS3_INT_GL_50K 0x000A
453 #define HNS3_INT_GL_20K 0x0019
454 #define HNS3_INT_GL_18K 0x001B
455 #define HNS3_INT_GL_8K 0x003E
457 struct hns3_enet_ring_group {
458 /* array of pointers to rings */
459 struct hns3_enet_ring *ring;
460 u64 total_bytes; /* total bytes processed this group */
461 u64 total_packets; /* total packets processed this group */
463 enum hns3_flow_level_range flow_level;
467 struct hns3_enet_tqp_vector {
468 struct hnae3_handle *handle;
469 u8 __iomem *mask_addr;
473 u16 idx; /* index in the TQP vector array per handle. */
475 struct napi_struct napi;
477 struct hns3_enet_ring_group rx_group;
478 struct hns3_enet_ring_group tx_group;
480 u16 num_tqps; /* total number of tqps in TQP vector */
482 cpumask_t affinity_mask;
483 char name[HNAE3_INT_NAME_LEN];
485 /* when 0 should adjust interrupt coalesce parameter */
487 } ____cacheline_internodealigned_in_smp;
489 enum hns3_udp_tnl_type {
495 struct hns3_udp_tunnel {
500 struct hns3_nic_priv {
501 struct hnae3_handle *ae_handle;
504 struct net_device *netdev;
506 struct hns3_nic_ops ops;
509 * the cb for nic to manage the ring buffer, the first half of the
510 * array is for tx_ring and vice versa for the second half
512 struct hns3_nic_ring_data *ring_data;
513 struct hns3_enet_tqp_vector *tqp_vector;
516 /* The most recently read link state */
518 u64 tx_timeout_count;
522 struct timer_list service_timer;
524 struct work_struct service_task;
526 struct notifier_block notifier_block;
527 /* Vxlan/Geneve information */
528 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
543 /* the distance between [begin, end) in a ring buffer
544 * note: there is a unuse slot between the begin and the end
546 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
548 return (end - begin + ring->desc_num) % ring->desc_num;
551 static inline int ring_space(struct hns3_enet_ring *ring)
553 return ring->desc_num -
554 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
557 static inline int is_ring_empty(struct hns3_enet_ring *ring)
559 return ring->next_to_use == ring->next_to_clean;
562 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
564 u8 __iomem *reg_addr = READ_ONCE(base);
566 writel(value, reg_addr + reg);
569 #define hns3_write_dev(a, reg, value) \
570 hns3_write_reg((a)->io_base, (reg), (value))
572 #define hnae_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
573 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
575 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)
577 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
578 DMA_TO_DEVICE : DMA_FROM_DEVICE)
580 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
582 #define hnae_buf_size(_ring) ((_ring)->buf_size)
583 #define hnae_page_order(_ring) (get_order(hnae_buf_size(_ring)))
584 #define hnae_page_size(_ring) (PAGE_SIZE << hnae_page_order(_ring))
586 /* iterator for handling rings in ring group */
587 #define hns3_for_each_ring(pos, head) \
588 for (pos = (head).ring; pos; pos = pos->next)
590 void hns3_ethtool_set_ops(struct net_device *netdev);
592 int hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);