1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/device.h>
5 #include <linux/dma-direction.h>
6 #include <linux/dma-mapping.h>
9 #include <linux/slab.h>
10 #include "hclgevf_cmd.h"
11 #include "hclgevf_main.h"
14 #define hclgevf_is_csq(ring) ((ring)->flag & HCLGEVF_TYPE_CSQ)
15 #define hclgevf_ring_to_dma_dir(ring) (hclgevf_is_csq(ring) ? \
16 DMA_TO_DEVICE : DMA_FROM_DEVICE)
17 #define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev)
19 static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
21 int ntc = ring->next_to_clean;
22 int ntu = ring->next_to_use;
25 used = (ntu - ntc + ring->desc_num) % ring->desc_num;
27 return ring->desc_num - used - 1;
30 static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
32 struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
33 u16 ntc = csq->next_to_clean;
34 struct hclgevf_desc *desc;
38 desc = &csq->desc[ntc];
39 head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
41 memset(desc, 0, sizeof(*desc));
43 if (ntc == csq->desc_num)
45 desc = &csq->desc[ntc];
48 csq->next_to_clean = ntc;
53 static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
57 head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
59 return head == hw->cmq.csq.next_to_use;
62 static bool hclgevf_is_special_opcode(u16 opcode)
64 u16 spec_opcode[] = {0x30, 0x31, 0x32};
67 for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
68 if (spec_opcode[i] == opcode)
75 static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
77 int size = ring->desc_num * sizeof(struct hclgevf_desc);
79 ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
80 size, &ring->desc_dma_addr,
88 static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
90 int size = ring->desc_num * sizeof(struct hclgevf_desc);
93 dma_free_coherent(cmq_ring_to_dev(ring), size,
94 ring->desc, ring->desc_dma_addr);
99 static int hclgevf_init_cmd_queue(struct hclgevf_dev *hdev,
100 struct hclgevf_cmq_ring *ring)
102 struct hclgevf_hw *hw = &hdev->hw;
103 int ring_type = ring->flag;
107 ring->desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
108 spin_lock_init(&ring->lock);
109 ring->next_to_clean = 0;
110 ring->next_to_use = 0;
113 /* allocate CSQ/CRQ descriptor */
114 ret = hclgevf_alloc_cmd_desc(ring);
116 dev_err(&hdev->pdev->dev, "failed(%d) to alloc %s desc\n", ret,
117 (ring_type == HCLGEVF_TYPE_CSQ) ? "CSQ" : "CRQ");
121 /* initialize the hardware registers with csq/crq dma-address,
122 * descriptor number, head & tail pointers
125 case HCLGEVF_TYPE_CSQ:
126 reg_val = (u32)ring->desc_dma_addr;
127 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
128 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
129 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
131 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
132 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
133 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val);
135 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
136 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
138 case HCLGEVF_TYPE_CRQ:
139 reg_val = (u32)ring->desc_dma_addr;
140 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
141 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
142 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
144 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
145 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
146 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val);
148 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
149 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
156 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
157 enum hclgevf_opcode_type opcode, bool is_read)
159 memset(desc, 0, sizeof(struct hclgevf_desc));
160 desc->opcode = cpu_to_le16(opcode);
161 desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
162 HCLGEVF_CMD_FLAG_IN);
164 desc->flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_WR);
166 desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
169 /* hclgevf_cmd_send - send command to command queue
170 * @hw: pointer to the hw struct
171 * @desc: prefilled descriptor for describing the command
172 * @num : the number of descriptors to be sent
174 * This is the main send command for command queue, it
175 * sends the queue, cleans the queue, etc
177 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
179 struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
180 struct hclgevf_desc *desc_to_use;
181 bool complete = false;
189 spin_lock_bh(&hw->cmq.csq.lock);
191 if (num > hclgevf_ring_space(&hw->cmq.csq)) {
192 spin_unlock_bh(&hw->cmq.csq.lock);
196 /* Record the location of desc in the ring for this time
197 * which will be use for hardware to write back
199 ntc = hw->cmq.csq.next_to_use;
200 opcode = le16_to_cpu(desc[0].opcode);
201 while (handle < num) {
202 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
203 *desc_to_use = desc[handle];
204 (hw->cmq.csq.next_to_use)++;
205 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
206 hw->cmq.csq.next_to_use = 0;
210 /* Write to hardware */
211 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
212 hw->cmq.csq.next_to_use);
214 /* If the command is sync, wait for the firmware to write back,
215 * if multi descriptors to be sent, use the first one to check
217 if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
219 if (hclgevf_cmd_csq_done(hw))
223 } while (timeout < hw->cmq.tx_timeout);
226 if (hclgevf_cmd_csq_done(hw)) {
230 while (handle < num) {
231 /* Get the result of hardware write back */
232 desc_to_use = &hw->cmq.csq.desc[ntc];
233 desc[handle] = *desc_to_use;
235 if (likely(!hclgevf_is_special_opcode(opcode)))
236 retval = le16_to_cpu(desc[handle].retval);
238 retval = le16_to_cpu(desc[0].retval);
240 if ((enum hclgevf_cmd_return_status)retval ==
241 HCLGEVF_CMD_EXEC_SUCCESS)
245 hw->cmq.last_status = (enum hclgevf_cmd_status)retval;
248 if (ntc == hw->cmq.csq.desc_num)
256 /* Clean the command send queue */
257 handle = hclgevf_cmd_csq_clean(hw);
259 dev_warn(&hdev->pdev->dev,
260 "cleaned %d, need to clean %d\n", handle, num);
263 spin_unlock_bh(&hw->cmq.csq.lock);
268 static int hclgevf_cmd_query_firmware_version(struct hclgevf_hw *hw,
271 struct hclgevf_query_version_cmd *resp;
272 struct hclgevf_desc desc;
275 resp = (struct hclgevf_query_version_cmd *)desc.data;
277 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
278 status = hclgevf_cmd_send(hw, &desc, 1);
280 *version = le32_to_cpu(resp->firmware);
285 int hclgevf_cmd_init(struct hclgevf_dev *hdev)
290 /* setup Tx write back timeout */
291 hdev->hw.cmq.tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
293 /* setup queue CSQ/CRQ rings */
294 hdev->hw.cmq.csq.flag = HCLGEVF_TYPE_CSQ;
295 ret = hclgevf_init_cmd_queue(hdev, &hdev->hw.cmq.csq);
297 dev_err(&hdev->pdev->dev,
298 "failed(%d) to initialize CSQ ring\n", ret);
302 hdev->hw.cmq.crq.flag = HCLGEVF_TYPE_CRQ;
303 ret = hclgevf_init_cmd_queue(hdev, &hdev->hw.cmq.crq);
305 dev_err(&hdev->pdev->dev,
306 "failed(%d) to initialize CRQ ring\n", ret);
310 /* initialize the pointers of async rx queue of mailbox */
311 hdev->arq.hdev = hdev;
316 /* get firmware version */
317 ret = hclgevf_cmd_query_firmware_version(&hdev->hw, &version);
319 dev_err(&hdev->pdev->dev,
320 "failed(%d) to query firmware version\n", ret);
323 hdev->fw_version = version;
325 dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
329 hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
331 hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
336 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
338 hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
339 hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);