drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c

   1 /*
   2  * Huawei HiNIC PCI Express Linux driver
   3  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/device.h>
  20 #include <linux/errno.h>
  21 #include <linux/slab.h>
  22 #include <linux/bitops.h>
  23 #include <linux/delay.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/log2.h>
  26 #include <linux/err.h>
  27
  28 #include "hinic_hw_if.h"
  29 #include "hinic_hw_eqs.h"
  30 #include "hinic_hw_mgmt.h"
  31 #include "hinic_hw_qp_ctxt.h"
  32 #include "hinic_hw_qp.h"
  33 #include "hinic_hw_io.h"
  34 #include "hinic_hw_dev.h"
  35
  36 #define IO_STATUS_TIMEOUT               100
  37 #define OUTBOUND_STATE_TIMEOUT          100
  38 #define DB_STATE_TIMEOUT                100
  39
  40 #define MAX_IRQS(max_qps, num_aeqs, num_ceqs)   \
  41                  (2 * (max_qps) + (num_aeqs) + (num_ceqs))
  42
  43 #define ADDR_IN_4BYTES(addr)            ((addr) >> 2)
  44
  45 enum intr_type {
  46         INTR_MSIX_TYPE,
  47 };
  48
  49 enum io_status {
  50         IO_STOPPED = 0,
  51         IO_RUNNING = 1,
  52 };
  53
  54 enum hw_ioctxt_set_cmdq_depth {
  55         HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT,
  56 };
  57
  58 /* HW struct */
  59 struct hinic_dev_cap {
  60         u8      status;
  61         u8      version;
  62         u8      rsvd0[6];
  63
  64         u8      rsvd1[5];
  65         u8      intr_type;
  66         u8      rsvd2[66];
  67         u16     max_sqs;
  68         u16     max_rqs;
  69         u8      rsvd3[208];
  70 };
  71
  72 /**
  73  * get_capability - convert device capabilities to NIC capabilities
  74  * @hwdev: the HW device to set and convert device capabilities for
  75  * @dev_cap: device capabilities from FW
  76  *
  77  * Return 0 - Success, negative - Failure
  78  **/
  79 static int get_capability(struct hinic_hwdev *hwdev,
  80                           struct hinic_dev_cap *dev_cap)
  81 {
  82         struct hinic_cap *nic_cap = &hwdev->nic_cap;
  83         int num_aeqs, num_ceqs, num_irqs;
  84
  85         if (!HINIC_IS_PF(hwdev->hwif) && !HINIC_IS_PPF(hwdev->hwif))
  86                 return -EINVAL;
  87
  88         if (dev_cap->intr_type != INTR_MSIX_TYPE)
  89                 return -EFAULT;
  90
  91         num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif);
  92         num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif);
  93         num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif);
  94
  95         /* Each QP has its own (SQ + RQ) interrupts */
  96         nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2;
  97
  98         if (nic_cap->num_qps > HINIC_Q_CTXT_MAX)
  99                 nic_cap->num_qps = HINIC_Q_CTXT_MAX;
 100
 101         /* num_qps must be power of 2 */
 102         nic_cap->num_qps = BIT(fls(nic_cap->num_qps) - 1);
 103
 104         nic_cap->max_qps = dev_cap->max_sqs + 1;
 105         if (nic_cap->max_qps != (dev_cap->max_rqs + 1))
 106                 return -EFAULT;
 107
 108         if (nic_cap->num_qps > nic_cap->max_qps)
 109                 nic_cap->num_qps = nic_cap->max_qps;
 110
 111         return 0;
 112 }
 113
 114 /**
 115  * get_cap_from_fw - get device capabilities from FW
 116  * @pfhwdev: the PF HW device to get capabilities for
 117  *
 118  * Return 0 - Success, negative - Failure
 119  **/
 120 static int get_cap_from_fw(struct hinic_pfhwdev *pfhwdev)
 121 {
 122         struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
 123         struct hinic_hwif *hwif = hwdev->hwif;
 124         struct pci_dev *pdev = hwif->pdev;
 125         struct hinic_dev_cap dev_cap;
 126         u16 in_len, out_len;
 127         int err;
 128
 129         in_len = 0;
 130         out_len = sizeof(dev_cap);
 131
 132         err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_CFGM,
 133                                 HINIC_CFG_NIC_CAP, &dev_cap, in_len, &dev_cap,
 134                                 &out_len, HINIC_MGMT_MSG_SYNC);
 135         if (err) {
 136                 dev_err(&pdev->dev, "Failed to get capability from FW\n");
 137                 return err;
 138         }
 139
 140         return get_capability(hwdev, &dev_cap);
 141 }
 142
 143 /**
 144  * get_dev_cap - get device capabilities
 145  * @hwdev: the NIC HW device to get capabilities for
 146  *
 147  * Return 0 - Success, negative - Failure
 148  **/
 149 static int get_dev_cap(struct hinic_hwdev *hwdev)
 150 {
 151         struct hinic_hwif *hwif = hwdev->hwif;
 152         struct pci_dev *pdev = hwif->pdev;
 153         struct hinic_pfhwdev *pfhwdev;
 154         int err;
 155
 156         switch (HINIC_FUNC_TYPE(hwif)) {
 157         case HINIC_PPF:
 158         case HINIC_PF:
 159                 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 160
 161                 err = get_cap_from_fw(pfhwdev);
 162                 if (err) {
 163                         dev_err(&pdev->dev, "Failed to get capability from FW\n");
 164                         return err;
 165                 }
 166                 break;
 167
 168         default:
 169                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 170                 return -EINVAL;
 171         }
 172
 173         return 0;
 174 }
 175
 176 /**
 177  * init_msix - enable the msix and save the entries
 178  * @hwdev: the NIC HW device
 179  *
 180  * Return 0 - Success, negative - Failure
 181  **/
 182 static int init_msix(struct hinic_hwdev *hwdev)
 183 {
 184         struct hinic_hwif *hwif = hwdev->hwif;
 185         struct pci_dev *pdev = hwif->pdev;
 186         int nr_irqs, num_aeqs, num_ceqs;
 187         size_t msix_entries_size;
 188         int i, err;
 189
 190         num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
 191         num_ceqs = HINIC_HWIF_NUM_CEQS(hwif);
 192         nr_irqs = MAX_IRQS(HINIC_MAX_QPS, num_aeqs, num_ceqs);
 193         if (nr_irqs > HINIC_HWIF_NUM_IRQS(hwif))
 194                 nr_irqs = HINIC_HWIF_NUM_IRQS(hwif);
 195
 196         msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries);
 197         hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size,
 198                                            GFP_KERNEL);
 199         if (!hwdev->msix_entries)
 200                 return -ENOMEM;
 201
 202         for (i = 0; i < nr_irqs; i++)
 203                 hwdev->msix_entries[i].entry = i;
 204
 205         err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs);
 206         if (err) {
 207                 dev_err(&pdev->dev, "Failed to enable pci msix\n");
 208                 return err;
 209         }
 210
 211         return 0;
 212 }
 213
 214 /**
 215  * disable_msix - disable the msix
 216  * @hwdev: the NIC HW device
 217  **/
 218 static void disable_msix(struct hinic_hwdev *hwdev)
 219 {
 220         struct hinic_hwif *hwif = hwdev->hwif;
 221         struct pci_dev *pdev = hwif->pdev;
 222
 223         pci_disable_msix(pdev);
 224 }
 225
 226 /**
 227  * hinic_port_msg_cmd - send port msg to mgmt
 228  * @hwdev: the NIC HW device
 229  * @cmd: the port command
 230  * @buf_in: input buffer
 231  * @in_size: input size
 232  * @buf_out: output buffer
 233  * @out_size: returned output size
 234  *
 235  * Return 0 - Success, negative - Failure
 236  **/
 237 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
 238                        void *buf_in, u16 in_size, void *buf_out, u16 *out_size)
 239 {
 240         struct hinic_hwif *hwif = hwdev->hwif;
 241         struct pci_dev *pdev = hwif->pdev;
 242         struct hinic_pfhwdev *pfhwdev;
 243
 244         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 245                 dev_err(&pdev->dev, "unsupported PCI Function type\n");
 246                 return -EINVAL;
 247         }
 248
 249         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 250
 251         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, cmd,
 252                                  buf_in, in_size, buf_out, out_size,
 253                                  HINIC_MGMT_MSG_SYNC);
 254 }
 255
 256 /**
 257  * init_fw_ctxt- Init Firmware tables before network mgmt and io operations
 258  * @hwdev: the NIC HW device
 259  *
 260  * Return 0 - Success, negative - Failure
 261  **/
 262 static int init_fw_ctxt(struct hinic_hwdev *hwdev)
 263 {
 264         struct hinic_hwif *hwif = hwdev->hwif;
 265         struct pci_dev *pdev = hwif->pdev;
 266         struct hinic_cmd_fw_ctxt fw_ctxt;
 267         u16 out_size;
 268         int err;
 269
 270         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 271                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 272                 return -EINVAL;
 273         }
 274
 275         fw_ctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 276         fw_ctxt.rx_buf_sz = HINIC_RX_BUF_SZ;
 277
 278         err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT,
 279                                  &fw_ctxt, sizeof(fw_ctxt),
 280                                  &fw_ctxt, &out_size);
 281         if (err || (out_size != sizeof(fw_ctxt)) || fw_ctxt.status) {
 282                 dev_err(&pdev->dev, "Failed to init FW ctxt, ret = %d\n",
 283                         fw_ctxt.status);
 284                 return -EFAULT;
 285         }
 286
 287         return 0;
 288 }
 289
 290 /**
 291  * set_hw_ioctxt - set the shape of the IO queues in FW
 292  * @hwdev: the NIC HW device
 293  * @rq_depth: rq depth
 294  * @sq_depth: sq depth
 295  *
 296  * Return 0 - Success, negative - Failure
 297  **/
 298 static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int rq_depth,
 299                          unsigned int sq_depth)
 300 {
 301         struct hinic_hwif *hwif = hwdev->hwif;
 302         struct hinic_cmd_hw_ioctxt hw_ioctxt;
 303         struct pci_dev *pdev = hwif->pdev;
 304         struct hinic_pfhwdev *pfhwdev;
 305
 306         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 307                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 308                 return -EINVAL;
 309         }
 310
 311         hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 312         hw_ioctxt.ppf_idx = HINIC_HWIF_PPF_IDX(hwif);
 313
 314         hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT;
 315         hw_ioctxt.cmdq_depth = 0;
 316
 317         hw_ioctxt.rq_depth  = ilog2(rq_depth);
 318
 319         hw_ioctxt.rx_buf_sz_idx = HINIC_RX_BUF_SZ_IDX;
 320
 321         hw_ioctxt.sq_depth  = ilog2(sq_depth);
 322
 323         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 324
 325         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM,
 326                                  HINIC_COMM_CMD_HWCTXT_SET,
 327                                  &hw_ioctxt, sizeof(hw_ioctxt), NULL,
 328                                  NULL, HINIC_MGMT_MSG_SYNC);
 329 }
 330
 331 static int wait_for_outbound_state(struct hinic_hwdev *hwdev)
 332 {
 333         enum hinic_outbound_state outbound_state;
 334         struct hinic_hwif *hwif = hwdev->hwif;
 335         struct pci_dev *pdev = hwif->pdev;
 336         unsigned long end;
 337
 338         end = jiffies + msecs_to_jiffies(OUTBOUND_STATE_TIMEOUT);
 339         do {
 340                 outbound_state = hinic_outbound_state_get(hwif);
 341
 342                 if (outbound_state == HINIC_OUTBOUND_ENABLE)
 343                         return 0;
 344
 345                 msleep(20);
 346         } while (time_before(jiffies, end));
 347
 348         dev_err(&pdev->dev, "Wait for OUTBOUND - Timeout\n");
 349         return -EFAULT;
 350 }
 351
 352 static int wait_for_db_state(struct hinic_hwdev *hwdev)
 353 {
 354         struct hinic_hwif *hwif = hwdev->hwif;
 355         struct pci_dev *pdev = hwif->pdev;
 356         enum hinic_db_state db_state;
 357         unsigned long end;
 358
 359         end = jiffies + msecs_to_jiffies(DB_STATE_TIMEOUT);
 360         do {
 361                 db_state = hinic_db_state_get(hwif);
 362
 363                 if (db_state == HINIC_DB_ENABLE)
 364                         return 0;
 365
 366                 msleep(20);
 367         } while (time_before(jiffies, end));
 368
 369         dev_err(&pdev->dev, "Wait for DB - Timeout\n");
 370         return -EFAULT;
 371 }
 372
 373 /**
 374  * clear_io_resource - set the IO resources as not active in the NIC
 375  * @hwdev: the NIC HW device
 376  *
 377  * Return 0 - Success, negative - Failure
 378  **/
 379 static int clear_io_resources(struct hinic_hwdev *hwdev)
 380 {
 381         struct hinic_cmd_clear_io_res cmd_clear_io_res;
 382         struct hinic_hwif *hwif = hwdev->hwif;
 383         struct pci_dev *pdev = hwif->pdev;
 384         struct hinic_pfhwdev *pfhwdev;
 385         int err;
 386
 387         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 388                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 389                 return -EINVAL;
 390         }
 391
 392         /* sleep 100ms to wait for firmware stopping I/O */
 393         msleep(100);
 394
 395         cmd_clear_io_res.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 396
 397         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 398
 399         err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM,
 400                                 HINIC_COMM_CMD_IO_RES_CLEAR, &cmd_clear_io_res,
 401                                 sizeof(cmd_clear_io_res), NULL, NULL,
 402                                 HINIC_MGMT_MSG_SYNC);
 403         if (err) {
 404                 dev_err(&pdev->dev, "Failed to clear IO resources\n");
 405                 return err;
 406         }
 407
 408         return 0;
 409 }
 410
 411 /**
 412  * set_resources_state - set the state of the resources in the NIC
 413  * @hwdev: the NIC HW device
 414  * @state: the state to set
 415  *
 416  * Return 0 - Success, negative - Failure
 417  **/
 418 static int set_resources_state(struct hinic_hwdev *hwdev,
 419                                enum hinic_res_state state)
 420 {
 421         struct hinic_cmd_set_res_state res_state;
 422         struct hinic_hwif *hwif = hwdev->hwif;
 423         struct pci_dev *pdev = hwif->pdev;
 424         struct hinic_pfhwdev *pfhwdev;
 425
 426         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 427                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 428                 return -EINVAL;
 429         }
 430
 431         res_state.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 432         res_state.state = state;
 433
 434         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 435
 436         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt,
 437                                  HINIC_MOD_COMM,
 438                                  HINIC_COMM_CMD_RES_STATE_SET,
 439                                  &res_state, sizeof(res_state), NULL,
 440                                  NULL, HINIC_MGMT_MSG_SYNC);
 441 }
 442
 443 /**
 444  * get_base_qpn - get the first qp number
 445  * @hwdev: the NIC HW device
 446  * @base_qpn: returned qp number
 447  *
 448  * Return 0 - Success, negative - Failure
 449  **/
 450 static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn)
 451 {
 452         struct hinic_cmd_base_qpn cmd_base_qpn;
 453         struct hinic_hwif *hwif = hwdev->hwif;
 454         struct pci_dev *pdev = hwif->pdev;
 455         u16 out_size;
 456         int err;
 457
 458         cmd_base_qpn.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 459
 460         err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN,
 461                                  &cmd_base_qpn, sizeof(cmd_base_qpn),
 462                                  &cmd_base_qpn, &out_size);
 463         if (err || (out_size != sizeof(cmd_base_qpn)) || cmd_base_qpn.status) {
 464                 dev_err(&pdev->dev, "Failed to get base qpn, status = %d\n",
 465                         cmd_base_qpn.status);
 466                 return -EFAULT;
 467         }
 468
 469         *base_qpn = cmd_base_qpn.qpn;
 470         return 0;
 471 }
 472
 473 /**
 474  * hinic_hwdev_ifup - Preparing the HW for passing IO
 475  * @hwdev: the NIC HW device
 476  *
 477  * Return 0 - Success, negative - Failure
 478  **/
 479 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev)
 480 {
 481         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 482         struct hinic_cap *nic_cap = &hwdev->nic_cap;
 483         struct hinic_hwif *hwif = hwdev->hwif;
 484         int err, num_aeqs, num_ceqs, num_qps;
 485         struct msix_entry *ceq_msix_entries;
 486         struct msix_entry *sq_msix_entries;
 487         struct msix_entry *rq_msix_entries;
 488         struct pci_dev *pdev = hwif->pdev;
 489         u16 base_qpn;
 490
 491         err = get_base_qpn(hwdev, &base_qpn);
 492         if (err) {
 493                 dev_err(&pdev->dev, "Failed to get global base qp number\n");
 494                 return err;
 495         }
 496
 497         num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
 498         num_ceqs = HINIC_HWIF_NUM_CEQS(hwif);
 499
 500         ceq_msix_entries = &hwdev->msix_entries[num_aeqs];
 501
 502         err = hinic_io_init(func_to_io, hwif, nic_cap->max_qps, num_ceqs,
 503                             ceq_msix_entries);
 504         if (err) {
 505                 dev_err(&pdev->dev, "Failed to init IO channel\n");
 506                 return err;
 507         }
 508
 509         num_qps = nic_cap->num_qps;
 510         sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs];
 511         rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps];
 512
 513         err = hinic_io_create_qps(func_to_io, base_qpn, num_qps,
 514                                   sq_msix_entries, rq_msix_entries);
 515         if (err) {
 516                 dev_err(&pdev->dev, "Failed to create QPs\n");
 517                 goto err_create_qps;
 518         }
 519
 520         err = wait_for_db_state(hwdev);
 521         if (err) {
 522                 dev_warn(&pdev->dev, "db - disabled, try again\n");
 523                 hinic_db_state_set(hwif, HINIC_DB_ENABLE);
 524         }
 525
 526         err = set_hw_ioctxt(hwdev, HINIC_SQ_DEPTH, HINIC_RQ_DEPTH);
 527         if (err) {
 528                 dev_err(&pdev->dev, "Failed to set HW IO ctxt\n");
 529                 goto err_hw_ioctxt;
 530         }
 531
 532         return 0;
 533
 534 err_hw_ioctxt:
 535         hinic_io_destroy_qps(func_to_io, num_qps);
 536
 537 err_create_qps:
 538         hinic_io_free(func_to_io);
 539         return err;
 540 }
 541
 542 /**
 543  * hinic_hwdev_ifdown - Closing the HW for passing IO
 544  * @hwdev: the NIC HW device
 545  *
 546  **/
 547 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev)
 548 {
 549         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 550         struct hinic_cap *nic_cap = &hwdev->nic_cap;
 551
 552         clear_io_resources(hwdev);
 553
 554         hinic_io_destroy_qps(func_to_io, nic_cap->num_qps);
 555         hinic_io_free(func_to_io);
 556 }
 557
 558 /**
 559  * hinic_hwdev_cb_register - register callback handler for MGMT events
 560  * @hwdev: the NIC HW device
 561  * @cmd: the mgmt event
 562  * @handle: private data for the handler
 563  * @handler: event handler
 564  **/
 565 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
 566                              enum hinic_mgmt_msg_cmd cmd, void *handle,
 567                              void (*handler)(void *handle, void *buf_in,
 568                                              u16 in_size, void *buf_out,
 569                                              u16 *out_size))
 570 {
 571         struct hinic_hwif *hwif = hwdev->hwif;
 572         struct pci_dev *pdev = hwif->pdev;
 573         struct hinic_pfhwdev *pfhwdev;
 574         struct hinic_nic_cb *nic_cb;
 575         u8 cmd_cb;
 576
 577         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 578                 dev_err(&pdev->dev, "unsupported PCI Function type\n");
 579                 return;
 580         }
 581
 582         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 583
 584         cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
 585         nic_cb = &pfhwdev->nic_cb[cmd_cb];
 586
 587         nic_cb->handler = handler;
 588         nic_cb->handle = handle;
 589         nic_cb->cb_state = HINIC_CB_ENABLED;
 590 }
 591
 592 /**
 593  * hinic_hwdev_cb_unregister - unregister callback handler for MGMT events
 594  * @hwdev: the NIC HW device
 595  * @cmd: the mgmt event
 596  **/
 597 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
 598                                enum hinic_mgmt_msg_cmd cmd)
 599 {
 600         struct hinic_hwif *hwif = hwdev->hwif;
 601         struct pci_dev *pdev = hwif->pdev;
 602         struct hinic_pfhwdev *pfhwdev;
 603         struct hinic_nic_cb *nic_cb;
 604         u8 cmd_cb;
 605
 606         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 607                 dev_err(&pdev->dev, "unsupported PCI Function type\n");
 608                 return;
 609         }
 610
 611         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 612
 613         cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
 614         nic_cb = &pfhwdev->nic_cb[cmd_cb];
 615
 616         nic_cb->cb_state &= ~HINIC_CB_ENABLED;
 617
 618         while (nic_cb->cb_state & HINIC_CB_RUNNING)
 619                 schedule();
 620
 621         nic_cb->handler = NULL;
 622 }
 623
 624 /**
 625  * nic_mgmt_msg_handler - nic mgmt event handler
 626  * @handle: private data for the handler
 627  * @buf_in: input buffer
 628  * @in_size: input size
 629  * @buf_out: output buffer
 630  * @out_size: returned output size
 631  **/
 632 static void nic_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in,
 633                                  u16 in_size, void *buf_out, u16 *out_size)
 634 {
 635         struct hinic_pfhwdev *pfhwdev = handle;
 636         enum hinic_cb_state cb_state;
 637         struct hinic_nic_cb *nic_cb;
 638         struct hinic_hwdev *hwdev;
 639         struct hinic_hwif *hwif;
 640         struct pci_dev *pdev;
 641         u8 cmd_cb;
 642
 643         hwdev = &pfhwdev->hwdev;
 644         hwif = hwdev->hwif;
 645         pdev = hwif->pdev;
 646
 647         if ((cmd < HINIC_MGMT_MSG_CMD_BASE) ||
 648             (cmd >= HINIC_MGMT_MSG_CMD_MAX)) {
 649                 dev_err(&pdev->dev, "unknown L2NIC event, cmd = %d\n", cmd);
 650                 return;
 651         }
 652
 653         cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
 654
 655         nic_cb = &pfhwdev->nic_cb[cmd_cb];
 656
 657         cb_state = cmpxchg(&nic_cb->cb_state,
 658                            HINIC_CB_ENABLED,
 659                            HINIC_CB_ENABLED | HINIC_CB_RUNNING);
 660
 661         if ((cb_state == HINIC_CB_ENABLED) && (nic_cb->handler))
 662                 nic_cb->handler(nic_cb->handle, buf_in,
 663                                 in_size, buf_out, out_size);
 664         else
 665                 dev_err(&pdev->dev, "Unhandled NIC Event %d\n", cmd);
 666
 667         nic_cb->cb_state &= ~HINIC_CB_RUNNING;
 668 }
 669
 670 /**
 671  * init_pfhwdev - Initialize the extended components of PF
 672  * @pfhwdev: the HW device for PF
 673  *
 674  * Return 0 - success, negative - failure
 675  **/
 676 static int init_pfhwdev(struct hinic_pfhwdev *pfhwdev)
 677 {
 678         struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
 679         struct hinic_hwif *hwif = hwdev->hwif;
 680         struct pci_dev *pdev = hwif->pdev;
 681         int err;
 682
 683         err = hinic_pf_to_mgmt_init(&pfhwdev->pf_to_mgmt, hwif);
 684         if (err) {
 685                 dev_err(&pdev->dev, "Failed to initialize PF to MGMT channel\n");
 686                 return err;
 687         }
 688
 689         hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC,
 690                                    pfhwdev, nic_mgmt_msg_handler);
 691
 692         hinic_set_pf_action(hwif, HINIC_PF_MGMT_ACTIVE);
 693         return 0;
 694 }
 695
 696 /**
 697  * free_pfhwdev - Free the extended components of PF
 698  * @pfhwdev: the HW device for PF
 699  **/
 700 static void free_pfhwdev(struct hinic_pfhwdev *pfhwdev)
 701 {
 702         struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
 703
 704         hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT);
 705
 706         hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC);
 707
 708         hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt);
 709 }
 710
 711 /**
 712  * hinic_init_hwdev - Initialize the NIC HW
 713  * @pdev: the NIC pci device
 714  *
 715  * Return initialized NIC HW device
 716  *
 717  * Initialize the NIC HW device and return a pointer to it
 718  **/
 719 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev)
 720 {
 721         struct hinic_pfhwdev *pfhwdev;
 722         struct hinic_hwdev *hwdev;
 723         struct hinic_hwif *hwif;
 724         int err, num_aeqs;
 725
 726         hwif = devm_kzalloc(&pdev->dev, sizeof(*hwif), GFP_KERNEL);
 727         if (!hwif)
 728                 return ERR_PTR(-ENOMEM);
 729
 730         err = hinic_init_hwif(hwif, pdev);
 731         if (err) {
 732                 dev_err(&pdev->dev, "Failed to init HW interface\n");
 733                 return ERR_PTR(err);
 734         }
 735
 736         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 737                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 738                 err = -EFAULT;
 739                 goto err_func_type;
 740         }
 741
 742         pfhwdev = devm_kzalloc(&pdev->dev, sizeof(*pfhwdev), GFP_KERNEL);
 743         if (!pfhwdev) {
 744                 err = -ENOMEM;
 745                 goto err_pfhwdev_alloc;
 746         }
 747
 748         hwdev = &pfhwdev->hwdev;
 749         hwdev->hwif = hwif;
 750
 751         err = init_msix(hwdev);
 752         if (err) {
 753                 dev_err(&pdev->dev, "Failed to init msix\n");
 754                 goto err_init_msix;
 755         }
 756
 757         err = wait_for_outbound_state(hwdev);
 758         if (err) {
 759                 dev_warn(&pdev->dev, "outbound - disabled, try again\n");
 760                 hinic_outbound_state_set(hwif, HINIC_OUTBOUND_ENABLE);
 761         }
 762
 763         num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
 764
 765         err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs,
 766                               HINIC_DEFAULT_AEQ_LEN, HINIC_EQ_PAGE_SIZE,
 767                               hwdev->msix_entries);
 768         if (err) {
 769                 dev_err(&pdev->dev, "Failed to init async event queues\n");
 770                 goto err_aeqs_init;
 771         }
 772
 773         err = init_pfhwdev(pfhwdev);
 774         if (err) {
 775                 dev_err(&pdev->dev, "Failed to init PF HW device\n");
 776                 goto err_init_pfhwdev;
 777         }
 778
 779         err = get_dev_cap(hwdev);
 780         if (err) {
 781                 dev_err(&pdev->dev, "Failed to get device capabilities\n");
 782                 goto err_dev_cap;
 783         }
 784
 785         err = init_fw_ctxt(hwdev);
 786         if (err) {
 787                 dev_err(&pdev->dev, "Failed to init function table\n");
 788                 goto err_init_fw_ctxt;
 789         }
 790
 791         err = set_resources_state(hwdev, HINIC_RES_ACTIVE);
 792         if (err) {
 793                 dev_err(&pdev->dev, "Failed to set resources state\n");
 794                 goto err_resources_state;
 795         }
 796
 797         return hwdev;
 798
 799 err_resources_state:
 800 err_init_fw_ctxt:
 801 err_dev_cap:
 802         free_pfhwdev(pfhwdev);
 803
 804 err_init_pfhwdev:
 805         hinic_aeqs_free(&hwdev->aeqs);
 806
 807 err_aeqs_init:
 808         disable_msix(hwdev);
 809
 810 err_init_msix:
 811 err_pfhwdev_alloc:
 812 err_func_type:
 813         hinic_free_hwif(hwif);
 814         return ERR_PTR(err);
 815 }
 816
 817 /**
 818  * hinic_free_hwdev - Free the NIC HW device
 819  * @hwdev: the NIC HW device
 820  **/
 821 void hinic_free_hwdev(struct hinic_hwdev *hwdev)
 822 {
 823         struct hinic_pfhwdev *pfhwdev = container_of(hwdev,
 824                                                      struct hinic_pfhwdev,
 825                                                      hwdev);
 826
 827         set_resources_state(hwdev, HINIC_RES_CLEAN);
 828
 829         free_pfhwdev(pfhwdev);
 830
 831         hinic_aeqs_free(&hwdev->aeqs);
 832
 833         disable_msix(hwdev);
 834
 835         hinic_free_hwif(hwdev->hwif);
 836 }
 837
 838 /**
 839  * hinic_hwdev_num_qps - return the number QPs available for use
 840  * @hwdev: the NIC HW device
 841  *
 842  * Return number QPs available for use
 843  **/
 844 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev)
 845 {
 846         struct hinic_cap *nic_cap = &hwdev->nic_cap;
 847
 848         return nic_cap->num_qps;
 849 }
 850
 851 /**
 852  * hinic_hwdev_get_sq - get SQ
 853  * @hwdev: the NIC HW device
 854  * @i: the position of the SQ
 855  *
 856  * Return: the SQ in the i position
 857  **/
 858 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i)
 859 {
 860         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 861         struct hinic_qp *qp = &func_to_io->qps[i];
 862
 863         if (i >= hinic_hwdev_num_qps(hwdev))
 864                 return NULL;
 865
 866         return &qp->sq;
 867 }
 868
 869 /**
 870  * hinic_hwdev_get_sq - get RQ
 871  * @hwdev: the NIC HW device
 872  * @i: the position of the RQ
 873  *
 874  * Return: the RQ in the i position
 875  **/
 876 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i)
 877 {
 878         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 879         struct hinic_qp *qp = &func_to_io->qps[i];
 880
 881         if (i >= hinic_hwdev_num_qps(hwdev))
 882                 return NULL;
 883
 884         return &qp->rq;
 885 }
 886
 887 /**
 888  * hinic_hwdev_msix_cnt_set - clear message attribute counters for msix entry
 889  * @hwdev: the NIC HW device
 890  * @msix_index: msix_index
 891  *
 892  * Return 0 - Success, negative - Failure
 893  **/
 894 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index)
 895 {
 896         return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index);
 897 }
 898
 899 /**
 900  * hinic_hwdev_msix_set - set message attribute for msix entry
 901  * @hwdev: the NIC HW device
 902  * @msix_index: msix_index
 903  * @pending_limit: the maximum pending interrupt events (unit 8)
 904  * @coalesc_timer: coalesc period for interrupt (unit 8 us)
 905  * @lli_timer: replenishing period for low latency credit (unit 8 us)
 906  * @lli_credit_limit: maximum credits for low latency msix messages (unit 8)
 907  * @resend_timer: maximum wait for resending msix (unit coalesc period)
 908  *
 909  * Return 0 - Success, negative - Failure
 910  **/
 911 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
 912                          u8 pending_limit, u8 coalesc_timer,
 913                          u8 lli_timer_cfg, u8 lli_credit_limit,
 914                          u8 resend_timer)
 915 {
 916         return hinic_msix_attr_set(hwdev->hwif, msix_index,
 917                                    pending_limit, coalesc_timer,
 918                                    lli_timer_cfg, lli_credit_limit,
 919                                    resend_timer);
 920 }
 921
 922 /**
 923  * hinic_hwdev_hw_ci_addr_set - set cons idx addr and attributes in HW for sq
 924  * @hwdev: the NIC HW device
 925  * @sq: send queue
 926  * @pending_limit: the maximum pending update ci events (unit 8)
 927  * @coalesc_timer: coalesc period for update ci (unit 8 us)
 928  *
 929  * Return 0 - Success, negative - Failure
 930  **/
 931 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
 932                                u8 pending_limit, u8 coalesc_timer)
 933 {
 934         struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
 935         struct hinic_hwif *hwif = hwdev->hwif;
 936         struct pci_dev *pdev = hwif->pdev;
 937         struct hinic_pfhwdev *pfhwdev;
 938         struct hinic_cmd_hw_ci hw_ci;
 939
 940         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 941                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 942                 return -EINVAL;
 943         }
 944
 945         hw_ci.dma_attr_off  = 0;
 946         hw_ci.pending_limit = pending_limit;
 947         hw_ci.coalesc_timer = coalesc_timer;
 948
 949         hw_ci.msix_en = 1;
 950         hw_ci.msix_entry_idx = sq->msix_entry;
 951
 952         hw_ci.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 953
 954         hw_ci.sq_id = qp->q_id;
 955
 956         hw_ci.ci_addr = ADDR_IN_4BYTES(sq->hw_ci_dma_addr);
 957
 958         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 959         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt,
 960                                  HINIC_MOD_COMM,
 961                                  HINIC_COMM_CMD_SQ_HI_CI_SET,
 962                                  &hw_ci, sizeof(hw_ci), NULL,
 963                                  NULL, HINIC_MGMT_MSG_SYNC);
 964 }