drivers/net/ethernet/intel/e1000e/82571.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 /* 82571EB Gigabit Ethernet Controller
   5  * 82571EB Gigabit Ethernet Controller (Copper)
   6  * 82571EB Gigabit Ethernet Controller (Fiber)
   7  * 82571EB Dual Port Gigabit Mezzanine Adapter
   8  * 82571EB Quad Port Gigabit Mezzanine Adapter
   9  * 82571PT Gigabit PT Quad Port Server ExpressModule
  10  * 82572EI Gigabit Ethernet Controller (Copper)
  11  * 82572EI Gigabit Ethernet Controller (Fiber)
  12  * 82572EI Gigabit Ethernet Controller
  13  * 82573V Gigabit Ethernet Controller (Copper)
  14  * 82573E Gigabit Ethernet Controller (Copper)
  15  * 82573L Gigabit Ethernet Controller
  16  * 82574L Gigabit Network Connection
  17  * 82583V Gigabit Network Connection
  18  */
  19
  20 #include "e1000.h"
  21
  22 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  23 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  24 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  25 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  26 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  27                                       u16 words, u16 *data);
  28 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  29 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  30 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  31 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  32 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  33 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  34 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  35 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  36 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  37 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  38 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
  39 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
  40
  41 /**
  42  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  43  *  @hw: pointer to the HW structure
  44  **/
  45 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  46 {
  47         struct e1000_phy_info *phy = &hw->phy;
  48         s32 ret_val;
  49
  50         if (hw->phy.media_type != e1000_media_type_copper) {
  51                 phy->type = e1000_phy_none;
  52                 return 0;
  53         }
  54
  55         phy->addr = 1;
  56         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  57         phy->reset_delay_us = 100;
  58
  59         phy->ops.power_up = e1000_power_up_phy_copper;
  60         phy->ops.power_down = e1000_power_down_phy_copper_82571;
  61
  62         switch (hw->mac.type) {
  63         case e1000_82571:
  64         case e1000_82572:
  65                 phy->type = e1000_phy_igp_2;
  66                 break;
  67         case e1000_82573:
  68                 phy->type = e1000_phy_m88;
  69                 break;
  70         case e1000_82574:
  71         case e1000_82583:
  72                 phy->type = e1000_phy_bm;
  73                 phy->ops.acquire = e1000_get_hw_semaphore_82574;
  74                 phy->ops.release = e1000_put_hw_semaphore_82574;
  75                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
  76                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
  77                 break;
  78         default:
  79                 return -E1000_ERR_PHY;
  80         }
  81
  82         /* This can only be done after all function pointers are setup. */
  83         ret_val = e1000_get_phy_id_82571(hw);
  84         if (ret_val) {
  85                 e_dbg("Error getting PHY ID\n");
  86                 return ret_val;
  87         }
  88
  89         /* Verify phy id */
  90         switch (hw->mac.type) {
  91         case e1000_82571:
  92         case e1000_82572:
  93                 if (phy->id != IGP01E1000_I_PHY_ID)
  94                         ret_val = -E1000_ERR_PHY;
  95                 break;
  96         case e1000_82573:
  97                 if (phy->id != M88E1111_I_PHY_ID)
  98                         ret_val = -E1000_ERR_PHY;
  99                 break;
 100         case e1000_82574:
 101         case e1000_82583:
 102                 if (phy->id != BME1000_E_PHY_ID_R2)
 103                         ret_val = -E1000_ERR_PHY;
 104                 break;
 105         default:
 106                 ret_val = -E1000_ERR_PHY;
 107                 break;
 108         }
 109
 110         if (ret_val)
 111                 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
 112
 113         return ret_val;
 114 }
 115
 116 /**
 117  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 118  *  @hw: pointer to the HW structure
 119  **/
 120 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 121 {
 122         struct e1000_nvm_info *nvm = &hw->nvm;
 123         u32 eecd = er32(EECD);
 124         u16 size;
 125
 126         nvm->opcode_bits = 8;
 127         nvm->delay_usec = 1;
 128         switch (nvm->override) {
 129         case e1000_nvm_override_spi_large:
 130                 nvm->page_size = 32;
 131                 nvm->address_bits = 16;
 132                 break;
 133         case e1000_nvm_override_spi_small:
 134                 nvm->page_size = 8;
 135                 nvm->address_bits = 8;
 136                 break;
 137         default:
 138                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 139                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 140                 break;
 141         }
 142
 143         switch (hw->mac.type) {
 144         case e1000_82573:
 145         case e1000_82574:
 146         case e1000_82583:
 147                 if (((eecd >> 15) & 0x3) == 0x3) {
 148                         nvm->type = e1000_nvm_flash_hw;
 149                         nvm->word_size = 2048;
 150                         /* Autonomous Flash update bit must be cleared due
 151                          * to Flash update issue.
 152                          */
 153                         eecd &= ~E1000_EECD_AUPDEN;
 154                         ew32(EECD, eecd);
 155                         break;
 156                 }
 157                 /* Fall Through */
 158         default:
 159                 nvm->type = e1000_nvm_eeprom_spi;
 160                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 161                              E1000_EECD_SIZE_EX_SHIFT);
 162                 /* Added to a constant, "size" becomes the left-shift value
 163                  * for setting word_size.
 164                  */
 165                 size += NVM_WORD_SIZE_BASE_SHIFT;
 166
 167                 /* EEPROM access above 16k is unsupported */
 168                 if (size > 14)
 169                         size = 14;
 170                 nvm->word_size = BIT(size);
 171                 break;
 172         }
 173
 174         /* Function Pointers */
 175         switch (hw->mac.type) {
 176         case e1000_82574:
 177         case e1000_82583:
 178                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 179                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 180                 break;
 181         default:
 182                 break;
 183         }
 184
 185         return 0;
 186 }
 187
 188 /**
 189  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 190  *  @hw: pointer to the HW structure
 191  **/
 192 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 193 {
 194         struct e1000_mac_info *mac = &hw->mac;
 195         u32 swsm = 0;
 196         u32 swsm2 = 0;
 197         bool force_clear_smbi = false;
 198
 199         /* Set media type and media-dependent function pointers */
 200         switch (hw->adapter->pdev->device) {
 201         case E1000_DEV_ID_82571EB_FIBER:
 202         case E1000_DEV_ID_82572EI_FIBER:
 203         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 204                 hw->phy.media_type = e1000_media_type_fiber;
 205                 mac->ops.setup_physical_interface =
 206                     e1000_setup_fiber_serdes_link_82571;
 207                 mac->ops.check_for_link = e1000e_check_for_fiber_link;
 208                 mac->ops.get_link_up_info =
 209                     e1000e_get_speed_and_duplex_fiber_serdes;
 210                 break;
 211         case E1000_DEV_ID_82571EB_SERDES:
 212         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 213         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 214         case E1000_DEV_ID_82572EI_SERDES:
 215                 hw->phy.media_type = e1000_media_type_internal_serdes;
 216                 mac->ops.setup_physical_interface =
 217                     e1000_setup_fiber_serdes_link_82571;
 218                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 219                 mac->ops.get_link_up_info =
 220                     e1000e_get_speed_and_duplex_fiber_serdes;
 221                 break;
 222         default:
 223                 hw->phy.media_type = e1000_media_type_copper;
 224                 mac->ops.setup_physical_interface =
 225                     e1000_setup_copper_link_82571;
 226                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 227                 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
 228                 break;
 229         }
 230
 231         /* Set mta register count */
 232         mac->mta_reg_count = 128;
 233         /* Set rar entry count */
 234         mac->rar_entry_count = E1000_RAR_ENTRIES;
 235         /* Adaptive IFS supported */
 236         mac->adaptive_ifs = true;
 237
 238         /* MAC-specific function pointers */
 239         switch (hw->mac.type) {
 240         case e1000_82573:
 241                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 242                 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 243                 mac->ops.led_on = e1000e_led_on_generic;
 244                 mac->ops.blink_led = e1000e_blink_led_generic;
 245
 246                 /* FWSM register */
 247                 mac->has_fwsm = true;
 248                 /* ARC supported; valid only if manageability features are
 249                  * enabled.
 250                  */
 251                 mac->arc_subsystem_valid = !!(er32(FWSM) &
 252                                               E1000_FWSM_MODE_MASK);
 253                 break;
 254         case e1000_82574:
 255         case e1000_82583:
 256                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 257                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 258                 mac->ops.led_on = e1000_led_on_82574;
 259                 break;
 260         default:
 261                 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 262                 mac->ops.led_on = e1000e_led_on_generic;
 263                 mac->ops.blink_led = e1000e_blink_led_generic;
 264
 265                 /* FWSM register */
 266                 mac->has_fwsm = true;
 267                 break;
 268         }
 269
 270         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 271          * first NVM or PHY access. This should be done for single-port
 272          * devices, and for one port only on dual-port devices so that
 273          * for those devices we can still use the SMBI lock to synchronize
 274          * inter-port accesses to the PHY & NVM.
 275          */
 276         switch (hw->mac.type) {
 277         case e1000_82571:
 278         case e1000_82572:
 279                 swsm2 = er32(SWSM2);
 280
 281                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 282                         /* Only do this for the first interface on this card */
 283                         ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
 284                         force_clear_smbi = true;
 285                 } else {
 286                         force_clear_smbi = false;
 287                 }
 288                 break;
 289         default:
 290                 force_clear_smbi = true;
 291                 break;
 292         }
 293
 294         if (force_clear_smbi) {
 295                 /* Make sure SWSM.SMBI is clear */
 296                 swsm = er32(SWSM);
 297                 if (swsm & E1000_SWSM_SMBI) {
 298                         /* This bit should not be set on a first interface, and
 299                          * indicates that the bootagent or EFI code has
 300                          * improperly left this bit enabled
 301                          */
 302                         e_dbg("Please update your 82571 Bootagent\n");
 303                 }
 304                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 305         }
 306
 307         /* Initialize device specific counter of SMBI acquisition timeouts. */
 308         hw->dev_spec.e82571.smb_counter = 0;
 309
 310         return 0;
 311 }
 312
 313 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 314 {
 315         struct e1000_hw *hw = &adapter->hw;
 316         static int global_quad_port_a;  /* global port a indication */
 317         struct pci_dev *pdev = adapter->pdev;
 318         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 319         s32 rc;
 320
 321         rc = e1000_init_mac_params_82571(hw);
 322         if (rc)
 323                 return rc;
 324
 325         rc = e1000_init_nvm_params_82571(hw);
 326         if (rc)
 327                 return rc;
 328
 329         rc = e1000_init_phy_params_82571(hw);
 330         if (rc)
 331                 return rc;
 332
 333         /* tag quad port adapters first, it's used below */
 334         switch (pdev->device) {
 335         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 336         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 337         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 338         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 339                 adapter->flags |= FLAG_IS_QUAD_PORT;
 340                 /* mark the first port */
 341                 if (global_quad_port_a == 0)
 342                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 343                 /* Reset for multiple quad port adapters */
 344                 global_quad_port_a++;
 345                 if (global_quad_port_a == 4)
 346                         global_quad_port_a = 0;
 347                 break;
 348         default:
 349                 break;
 350         }
 351
 352         switch (adapter->hw.mac.type) {
 353         case e1000_82571:
 354                 /* these dual ports don't have WoL on port B at all */
 355                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 356                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 357                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 358                     (is_port_b))
 359                         adapter->flags &= ~FLAG_HAS_WOL;
 360                 /* quad ports only support WoL on port A */
 361                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 362                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 363                         adapter->flags &= ~FLAG_HAS_WOL;
 364                 /* Does not support WoL on any port */
 365                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 366                         adapter->flags &= ~FLAG_HAS_WOL;
 367                 break;
 368         case e1000_82573:
 369                 if (pdev->device == E1000_DEV_ID_82573L) {
 370                         adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 371                         adapter->max_hw_frame_size = DEFAULT_JUMBO;
 372                 }
 373                 break;
 374         default:
 375                 break;
 376         }
 377
 378         return 0;
 379 }
 380
 381 /**
 382  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 383  *  @hw: pointer to the HW structure
 384  *
 385  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 386  *  revision in the hardware structure.
 387  **/
 388 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 389 {
 390         struct e1000_phy_info *phy = &hw->phy;
 391         s32 ret_val;
 392         u16 phy_id = 0;
 393
 394         switch (hw->mac.type) {
 395         case e1000_82571:
 396         case e1000_82572:
 397                 /* The 82571 firmware may still be configuring the PHY.
 398                  * In this case, we cannot access the PHY until the
 399                  * configuration is done.  So we explicitly set the
 400                  * PHY ID.
 401                  */
 402                 phy->id = IGP01E1000_I_PHY_ID;
 403                 break;
 404         case e1000_82573:
 405                 return e1000e_get_phy_id(hw);
 406         case e1000_82574:
 407         case e1000_82583:
 408                 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
 409                 if (ret_val)
 410                         return ret_val;
 411
 412                 phy->id = (u32)(phy_id << 16);
 413                 usleep_range(20, 40);
 414                 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
 415                 if (ret_val)
 416                         return ret_val;
 417
 418                 phy->id |= (u32)(phy_id);
 419                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 420                 break;
 421         default:
 422                 return -E1000_ERR_PHY;
 423         }
 424
 425         return 0;
 426 }
 427
 428 /**
 429  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 430  *  @hw: pointer to the HW structure
 431  *
 432  *  Acquire the HW semaphore to access the PHY or NVM
 433  **/
 434 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 435 {
 436         u32 swsm;
 437         s32 sw_timeout = hw->nvm.word_size + 1;
 438         s32 fw_timeout = hw->nvm.word_size + 1;
 439         s32 i = 0;
 440
 441         /* If we have timedout 3 times on trying to acquire
 442          * the inter-port SMBI semaphore, there is old code
 443          * operating on the other port, and it is not
 444          * releasing SMBI. Modify the number of times that
 445          * we try for the semaphore to interwork with this
 446          * older code.
 447          */
 448         if (hw->dev_spec.e82571.smb_counter > 2)
 449                 sw_timeout = 1;
 450
 451         /* Get the SW semaphore */
 452         while (i < sw_timeout) {
 453                 swsm = er32(SWSM);
 454                 if (!(swsm & E1000_SWSM_SMBI))
 455                         break;
 456
 457                 usleep_range(50, 100);
 458                 i++;
 459         }
 460
 461         if (i == sw_timeout) {
 462                 e_dbg("Driver can't access device - SMBI bit is set.\n");
 463                 hw->dev_spec.e82571.smb_counter++;
 464         }
 465         /* Get the FW semaphore. */
 466         for (i = 0; i < fw_timeout; i++) {
 467                 swsm = er32(SWSM);
 468                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 469
 470                 /* Semaphore acquired if bit latched */
 471                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 472                         break;
 473
 474                 usleep_range(50, 100);
 475         }
 476
 477         if (i == fw_timeout) {
 478                 /* Release semaphores */
 479                 e1000_put_hw_semaphore_82571(hw);
 480                 e_dbg("Driver can't access the NVM\n");
 481                 return -E1000_ERR_NVM;
 482         }
 483
 484         return 0;
 485 }
 486
 487 /**
 488  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 489  *  @hw: pointer to the HW structure
 490  *
 491  *  Release hardware semaphore used to access the PHY or NVM
 492  **/
 493 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 494 {
 495         u32 swsm;
 496
 497         swsm = er32(SWSM);
 498         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 499         ew32(SWSM, swsm);
 500 }
 501
 502 /**
 503  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 504  *  @hw: pointer to the HW structure
 505  *
 506  *  Acquire the HW semaphore during reset.
 507  *
 508  **/
 509 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 510 {
 511         u32 extcnf_ctrl;
 512         s32 i = 0;
 513
 514         extcnf_ctrl = er32(EXTCNF_CTRL);
 515         do {
 516                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 517                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 518                 extcnf_ctrl = er32(EXTCNF_CTRL);
 519
 520                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 521                         break;
 522
 523                 usleep_range(2000, 4000);
 524                 i++;
 525         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 526
 527         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 528                 /* Release semaphores */
 529                 e1000_put_hw_semaphore_82573(hw);
 530                 e_dbg("Driver can't access the PHY\n");
 531                 return -E1000_ERR_PHY;
 532         }
 533
 534         return 0;
 535 }
 536
 537 /**
 538  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 539  *  @hw: pointer to the HW structure
 540  *
 541  *  Release hardware semaphore used during reset.
 542  *
 543  **/
 544 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 545 {
 546         u32 extcnf_ctrl;
 547
 548         extcnf_ctrl = er32(EXTCNF_CTRL);
 549         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 550         ew32(EXTCNF_CTRL, extcnf_ctrl);
 551 }
 552
 553 static DEFINE_MUTEX(swflag_mutex);
 554
 555 /**
 556  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 557  *  @hw: pointer to the HW structure
 558  *
 559  *  Acquire the HW semaphore to access the PHY or NVM.
 560  *
 561  **/
 562 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 563 {
 564         s32 ret_val;
 565
 566         mutex_lock(&swflag_mutex);
 567         ret_val = e1000_get_hw_semaphore_82573(hw);
 568         if (ret_val)
 569                 mutex_unlock(&swflag_mutex);
 570         return ret_val;
 571 }
 572
 573 /**
 574  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 575  *  @hw: pointer to the HW structure
 576  *
 577  *  Release hardware semaphore used to access the PHY or NVM
 578  *
 579  **/
 580 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 581 {
 582         e1000_put_hw_semaphore_82573(hw);
 583         mutex_unlock(&swflag_mutex);
 584 }
 585
 586 /**
 587  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 588  *  @hw: pointer to the HW structure
 589  *  @active: true to enable LPLU, false to disable
 590  *
 591  *  Sets the LPLU D0 state according to the active flag.
 592  *  LPLU will not be activated unless the
 593  *  device autonegotiation advertisement meets standards of
 594  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 595  *  This is a function pointer entry point only called by
 596  *  PHY setup routines.
 597  **/
 598 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 599 {
 600         u32 data = er32(POEMB);
 601
 602         if (active)
 603                 data |= E1000_PHY_CTRL_D0A_LPLU;
 604         else
 605                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 606
 607         ew32(POEMB, data);
 608         return 0;
 609 }
 610
 611 /**
 612  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 613  *  @hw: pointer to the HW structure
 614  *  @active: boolean used to enable/disable lplu
 615  *
 616  *  The low power link up (lplu) state is set to the power management level D3
 617  *  when active is true, else clear lplu for D3. LPLU
 618  *  is used during Dx states where the power conservation is most important.
 619  *  During driver activity, SmartSpeed should be enabled so performance is
 620  *  maintained.
 621  **/
 622 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 623 {
 624         u32 data = er32(POEMB);
 625
 626         if (!active) {
 627                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 628         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 629                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 630                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 631                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 632         }
 633
 634         ew32(POEMB, data);
 635         return 0;
 636 }
 637
 638 /**
 639  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 640  *  @hw: pointer to the HW structure
 641  *
 642  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 643  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 644  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 645  *  hardware semaphore.
 646  **/
 647 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 648 {
 649         s32 ret_val;
 650
 651         ret_val = e1000_get_hw_semaphore_82571(hw);
 652         if (ret_val)
 653                 return ret_val;
 654
 655         switch (hw->mac.type) {
 656         case e1000_82573:
 657                 break;
 658         default:
 659                 ret_val = e1000e_acquire_nvm(hw);
 660                 break;
 661         }
 662
 663         if (ret_val)
 664                 e1000_put_hw_semaphore_82571(hw);
 665
 666         return ret_val;
 667 }
 668
 669 /**
 670  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 671  *  @hw: pointer to the HW structure
 672  *
 673  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 674  **/
 675 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 676 {
 677         e1000e_release_nvm(hw);
 678         e1000_put_hw_semaphore_82571(hw);
 679 }
 680
 681 /**
 682  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 683  *  @hw: pointer to the HW structure
 684  *  @offset: offset within the EEPROM to be written to
 685  *  @words: number of words to write
 686  *  @data: 16 bit word(s) to be written to the EEPROM
 687  *
 688  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 689  *
 690  *  If e1000e_update_nvm_checksum is not called after this function, the
 691  *  EEPROM will most likely contain an invalid checksum.
 692  **/
 693 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 694                                  u16 *data)
 695 {
 696         s32 ret_val;
 697
 698         switch (hw->mac.type) {
 699         case e1000_82573:
 700         case e1000_82574:
 701         case e1000_82583:
 702                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 703                 break;
 704         case e1000_82571:
 705         case e1000_82572:
 706                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 707                 break;
 708         default:
 709                 ret_val = -E1000_ERR_NVM;
 710                 break;
 711         }
 712
 713         return ret_val;
 714 }
 715
 716 /**
 717  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 718  *  @hw: pointer to the HW structure
 719  *
 720  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 721  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 722  *  value to the EEPROM.
 723  **/
 724 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 725 {
 726         u32 eecd;
 727         s32 ret_val;
 728         u16 i;
 729
 730         ret_val = e1000e_update_nvm_checksum_generic(hw);
 731         if (ret_val)
 732                 return ret_val;
 733
 734         /* If our nvm is an EEPROM, then we're done
 735          * otherwise, commit the checksum to the flash NVM.
 736          */
 737         if (hw->nvm.type != e1000_nvm_flash_hw)
 738                 return 0;
 739
 740         /* Check for pending operations. */
 741         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 742                 usleep_range(1000, 2000);
 743                 if (!(er32(EECD) & E1000_EECD_FLUPD))
 744                         break;
 745         }
 746
 747         if (i == E1000_FLASH_UPDATES)
 748                 return -E1000_ERR_NVM;
 749
 750         /* Reset the firmware if using STM opcode. */
 751         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 752                 /* The enabling of and the actual reset must be done
 753                  * in two write cycles.
 754                  */
 755                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 756                 e1e_flush();
 757                 ew32(HICR, E1000_HICR_FW_RESET);
 758         }
 759
 760         /* Commit the write to flash */
 761         eecd = er32(EECD) | E1000_EECD_FLUPD;
 762         ew32(EECD, eecd);
 763
 764         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 765                 usleep_range(1000, 2000);
 766                 if (!(er32(EECD) & E1000_EECD_FLUPD))
 767                         break;
 768         }
 769
 770         if (i == E1000_FLASH_UPDATES)
 771                 return -E1000_ERR_NVM;
 772
 773         return 0;
 774 }
 775
 776 /**
 777  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 778  *  @hw: pointer to the HW structure
 779  *
 780  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 781  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 782  **/
 783 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 784 {
 785         if (hw->nvm.type == e1000_nvm_flash_hw)
 786                 e1000_fix_nvm_checksum_82571(hw);
 787
 788         return e1000e_validate_nvm_checksum_generic(hw);
 789 }
 790
 791 /**
 792  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 793  *  @hw: pointer to the HW structure
 794  *  @offset: offset within the EEPROM to be written to
 795  *  @words: number of words to write
 796  *  @data: 16 bit word(s) to be written to the EEPROM
 797  *
 798  *  After checking for invalid values, poll the EEPROM to ensure the previous
 799  *  command has completed before trying to write the next word.  After write
 800  *  poll for completion.
 801  *
 802  *  If e1000e_update_nvm_checksum is not called after this function, the
 803  *  EEPROM will most likely contain an invalid checksum.
 804  **/
 805 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 806                                       u16 words, u16 *data)
 807 {
 808         struct e1000_nvm_info *nvm = &hw->nvm;
 809         u32 i, eewr = 0;
 810         s32 ret_val = 0;
 811
 812         /* A check for invalid values:  offset too large, too many words,
 813          * and not enough words.
 814          */
 815         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 816             (words == 0)) {
 817                 e_dbg("nvm parameter(s) out of bounds\n");
 818                 return -E1000_ERR_NVM;
 819         }
 820
 821         for (i = 0; i < words; i++) {
 822                 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 823                         ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 824                         E1000_NVM_RW_REG_START);
 825
 826                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 827                 if (ret_val)
 828                         break;
 829
 830                 ew32(EEWR, eewr);
 831
 832                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 833                 if (ret_val)
 834                         break;
 835         }
 836
 837         return ret_val;
 838 }
 839
 840 /**
 841  *  e1000_get_cfg_done_82571 - Poll for configuration done
 842  *  @hw: pointer to the HW structure
 843  *
 844  *  Reads the management control register for the config done bit to be set.
 845  **/
 846 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 847 {
 848         s32 timeout = PHY_CFG_TIMEOUT;
 849
 850         while (timeout) {
 851                 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
 852                         break;
 853                 usleep_range(1000, 2000);
 854                 timeout--;
 855         }
 856         if (!timeout) {
 857                 e_dbg("MNG configuration cycle has not completed.\n");
 858                 return -E1000_ERR_RESET;
 859         }
 860
 861         return 0;
 862 }
 863
 864 /**
 865  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 866  *  @hw: pointer to the HW structure
 867  *  @active: true to enable LPLU, false to disable
 868  *
 869  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 870  *  this function also disables smart speed and vice versa.  LPLU will not be
 871  *  activated unless the device autonegotiation advertisement meets standards
 872  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 873  *  pointer entry point only called by PHY setup routines.
 874  **/
 875 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 876 {
 877         struct e1000_phy_info *phy = &hw->phy;
 878         s32 ret_val;
 879         u16 data;
 880
 881         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 882         if (ret_val)
 883                 return ret_val;
 884
 885         if (active) {
 886                 data |= IGP02E1000_PM_D0_LPLU;
 887                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 888                 if (ret_val)
 889                         return ret_val;
 890
 891                 /* When LPLU is enabled, we should disable SmartSpeed */
 892                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 893                 if (ret_val)
 894                         return ret_val;
 895                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 896                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 897                 if (ret_val)
 898                         return ret_val;
 899         } else {
 900                 data &= ~IGP02E1000_PM_D0_LPLU;
 901                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 902                 if (ret_val)
 903                         return ret_val;
 904                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 905                  * during Dx states where the power conservation is most
 906                  * important.  During driver activity we should enable
 907                  * SmartSpeed, so performance is maintained.
 908                  */
 909                 if (phy->smart_speed == e1000_smart_speed_on) {
 910                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 911                                            &data);
 912                         if (ret_val)
 913                                 return ret_val;
 914
 915                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 916                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 917                                            data);
 918                         if (ret_val)
 919                                 return ret_val;
 920                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 921                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 922                                            &data);
 923                         if (ret_val)
 924                                 return ret_val;
 925
 926                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 927                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 928                                            data);
 929                         if (ret_val)
 930                                 return ret_val;
 931                 }
 932         }
 933
 934         return 0;
 935 }
 936
 937 /**
 938  *  e1000_reset_hw_82571 - Reset hardware
 939  *  @hw: pointer to the HW structure
 940  *
 941  *  This resets the hardware into a known state.
 942  **/
 943 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 944 {
 945         u32 ctrl, ctrl_ext, eecd, tctl;
 946         s32 ret_val;
 947
 948         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 949          * on the last TLP read/write transaction when MAC is reset.
 950          */
 951         ret_val = e1000e_disable_pcie_master(hw);
 952         if (ret_val)
 953                 e_dbg("PCI-E Master disable polling has failed.\n");
 954
 955         e_dbg("Masking off all interrupts\n");
 956         ew32(IMC, 0xffffffff);
 957
 958         ew32(RCTL, 0);
 959         tctl = er32(TCTL);
 960         tctl &= ~E1000_TCTL_EN;
 961         ew32(TCTL, tctl);
 962         e1e_flush();
 963
 964         usleep_range(10000, 20000);
 965
 966         /* Must acquire the MDIO ownership before MAC reset.
 967          * Ownership defaults to firmware after a reset.
 968          */
 969         switch (hw->mac.type) {
 970         case e1000_82573:
 971                 ret_val = e1000_get_hw_semaphore_82573(hw);
 972                 break;
 973         case e1000_82574:
 974         case e1000_82583:
 975                 ret_val = e1000_get_hw_semaphore_82574(hw);
 976                 break;
 977         default:
 978                 break;
 979         }
 980
 981         ctrl = er32(CTRL);
 982
 983         e_dbg("Issuing a global reset to MAC\n");
 984         ew32(CTRL, ctrl | E1000_CTRL_RST);
 985
 986         /* Must release MDIO ownership and mutex after MAC reset. */
 987         switch (hw->mac.type) {
 988         case e1000_82573:
 989                 /* Release mutex only if the hw semaphore is acquired */
 990                 if (!ret_val)
 991                         e1000_put_hw_semaphore_82573(hw);
 992                 break;
 993         case e1000_82574:
 994         case e1000_82583:
 995                 /* Release mutex only if the hw semaphore is acquired */
 996                 if (!ret_val)
 997                         e1000_put_hw_semaphore_82574(hw);
 998                 break;
 999         default:
1000                 break;
1001         }
1002
1003         if (hw->nvm.type == e1000_nvm_flash_hw) {
1004                 usleep_range(10, 20);
1005                 ctrl_ext = er32(CTRL_EXT);
1006                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1007                 ew32(CTRL_EXT, ctrl_ext);
1008                 e1e_flush();
1009         }
1010
1011         ret_val = e1000e_get_auto_rd_done(hw);
1012         if (ret_val)
1013                 /* We don't want to continue accessing MAC registers. */
1014                 return ret_val;
1015
1016         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1017          * Need to wait for Phy configuration completion before accessing
1018          * NVM and Phy.
1019          */
1020
1021         switch (hw->mac.type) {
1022         case e1000_82571:
1023         case e1000_82572:
1024                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1025                  * to access the EEPROM.
1026                  */
1027                 eecd = er32(EECD);
1028                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1029                 ew32(EECD, eecd);
1030                 break;
1031         case e1000_82573:
1032         case e1000_82574:
1033         case e1000_82583:
1034                 msleep(25);
1035                 break;
1036         default:
1037                 break;
1038         }
1039
1040         /* Clear any pending interrupt events. */
1041         ew32(IMC, 0xffffffff);
1042         er32(ICR);
1043
1044         if (hw->mac.type == e1000_82571) {
1045                 /* Install any alternate MAC address into RAR0 */
1046                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1047                 if (ret_val)
1048                         return ret_val;
1049
1050                 e1000e_set_laa_state_82571(hw, true);
1051         }
1052
1053         /* Reinitialize the 82571 serdes link state machine */
1054         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1055                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1056
1057         return 0;
1058 }
1059
1060 /**
1061  *  e1000_init_hw_82571 - Initialize hardware
1062  *  @hw: pointer to the HW structure
1063  *
1064  *  This inits the hardware readying it for operation.
1065  **/
1066 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1067 {
1068         struct e1000_mac_info *mac = &hw->mac;
1069         u32 reg_data;
1070         s32 ret_val;
1071         u16 i, rar_count = mac->rar_entry_count;
1072
1073         e1000_initialize_hw_bits_82571(hw);
1074
1075         /* Initialize identification LED */
1076         ret_val = mac->ops.id_led_init(hw);
1077         /* An error is not fatal and we should not stop init due to this */
1078         if (ret_val)
1079                 e_dbg("Error initializing identification LED\n");
1080
1081         /* Disabling VLAN filtering */
1082         e_dbg("Initializing the IEEE VLAN\n");
1083         mac->ops.clear_vfta(hw);
1084
1085         /* Setup the receive address.
1086          * If, however, a locally administered address was assigned to the
1087          * 82571, we must reserve a RAR for it to work around an issue where
1088          * resetting one port will reload the MAC on the other port.
1089          */
1090         if (e1000e_get_laa_state_82571(hw))
1091                 rar_count--;
1092         e1000e_init_rx_addrs(hw, rar_count);
1093
1094         /* Zero out the Multicast HASH table */
1095         e_dbg("Zeroing the MTA\n");
1096         for (i = 0; i < mac->mta_reg_count; i++)
1097                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1098
1099         /* Setup link and flow control */
1100         ret_val = mac->ops.setup_link(hw);
1101
1102         /* Set the transmit descriptor write-back policy */
1103         reg_data = er32(TXDCTL(0));
1104         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1105                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1106         ew32(TXDCTL(0), reg_data);
1107
1108         /* ...for both queues. */
1109         switch (mac->type) {
1110         case e1000_82573:
1111                 e1000e_enable_tx_pkt_filtering(hw);
1112                 /* fall through */
1113         case e1000_82574:
1114         case e1000_82583:
1115                 reg_data = er32(GCR);
1116                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1117                 ew32(GCR, reg_data);
1118                 break;
1119         default:
1120                 reg_data = er32(TXDCTL(1));
1121                 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1122                             E1000_TXDCTL_FULL_TX_DESC_WB |
1123                             E1000_TXDCTL_COUNT_DESC);
1124                 ew32(TXDCTL(1), reg_data);
1125                 break;
1126         }
1127
1128         /* Clear all of the statistics registers (clear on read).  It is
1129          * important that we do this after we have tried to establish link
1130          * because the symbol error count will increment wildly if there
1131          * is no link.
1132          */
1133         e1000_clear_hw_cntrs_82571(hw);
1134
1135         return ret_val;
1136 }
1137
1138 /**
1139  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1140  *  @hw: pointer to the HW structure
1141  *
1142  *  Initializes required hardware-dependent bits needed for normal operation.
1143  **/
1144 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1145 {
1146         u32 reg;
1147
1148         /* Transmit Descriptor Control 0 */
1149         reg = er32(TXDCTL(0));
1150         reg |= BIT(22);
1151         ew32(TXDCTL(0), reg);
1152
1153         /* Transmit Descriptor Control 1 */
1154         reg = er32(TXDCTL(1));
1155         reg |= BIT(22);
1156         ew32(TXDCTL(1), reg);
1157
1158         /* Transmit Arbitration Control 0 */
1159         reg = er32(TARC(0));
1160         reg &= ~(0xF << 27);    /* 30:27 */
1161         switch (hw->mac.type) {
1162         case e1000_82571:
1163         case e1000_82572:
1164                 reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);
1165                 break;
1166         case e1000_82574:
1167         case e1000_82583:
1168                 reg |= BIT(26);
1169                 break;
1170         default:
1171                 break;
1172         }
1173         ew32(TARC(0), reg);
1174
1175         /* Transmit Arbitration Control 1 */
1176         reg = er32(TARC(1));
1177         switch (hw->mac.type) {
1178         case e1000_82571:
1179         case e1000_82572:
1180                 reg &= ~(BIT(29) | BIT(30));
1181                 reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);
1182                 if (er32(TCTL) & E1000_TCTL_MULR)
1183                         reg &= ~BIT(28);
1184                 else
1185                         reg |= BIT(28);
1186                 ew32(TARC(1), reg);
1187                 break;
1188         default:
1189                 break;
1190         }
1191
1192         /* Device Control */
1193         switch (hw->mac.type) {
1194         case e1000_82573:
1195         case e1000_82574:
1196         case e1000_82583:
1197                 reg = er32(CTRL);
1198                 reg &= ~BIT(29);
1199                 ew32(CTRL, reg);
1200                 break;
1201         default:
1202                 break;
1203         }
1204
1205         /* Extended Device Control */
1206         switch (hw->mac.type) {
1207         case e1000_82573:
1208         case e1000_82574:
1209         case e1000_82583:
1210                 reg = er32(CTRL_EXT);
1211                 reg &= ~BIT(23);
1212                 reg |= BIT(22);
1213                 ew32(CTRL_EXT, reg);
1214                 break;
1215         default:
1216                 break;
1217         }
1218
1219         if (hw->mac.type == e1000_82571) {
1220                 reg = er32(PBA_ECC);
1221                 reg |= E1000_PBA_ECC_CORR_EN;
1222                 ew32(PBA_ECC, reg);
1223         }
1224
1225         /* Workaround for hardware errata.
1226          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1227          */
1228         if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1229                 reg = er32(CTRL_EXT);
1230                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1231                 ew32(CTRL_EXT, reg);
1232         }
1233
1234         /* Disable IPv6 extension header parsing because some malformed
1235          * IPv6 headers can hang the Rx.
1236          */
1237         if (hw->mac.type <= e1000_82573) {
1238                 reg = er32(RFCTL);
1239                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1240                 ew32(RFCTL, reg);
1241         }
1242
1243         /* PCI-Ex Control Registers */
1244         switch (hw->mac.type) {
1245         case e1000_82574:
1246         case e1000_82583:
1247                 reg = er32(GCR);
1248                 reg |= BIT(22);
1249                 ew32(GCR, reg);
1250
1251                 /* Workaround for hardware errata.
1252                  * apply workaround for hardware errata documented in errata
1253                  * docs Fixes issue where some error prone or unreliable PCIe
1254                  * completions are occurring, particularly with ASPM enabled.
1255                  * Without fix, issue can cause Tx timeouts.
1256                  */
1257                 reg = er32(GCR2);
1258                 reg |= 1;
1259                 ew32(GCR2, reg);
1260                 break;
1261         default:
1262                 break;
1263         }
1264 }
1265
1266 /**
1267  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1268  *  @hw: pointer to the HW structure
1269  *
1270  *  Clears the register array which contains the VLAN filter table by
1271  *  setting all the values to 0.
1272  **/
1273 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1274 {
1275         u32 offset;
1276         u32 vfta_value = 0;
1277         u32 vfta_offset = 0;
1278         u32 vfta_bit_in_reg = 0;
1279
1280         switch (hw->mac.type) {
1281         case e1000_82573:
1282         case e1000_82574:
1283         case e1000_82583:
1284                 if (hw->mng_cookie.vlan_id != 0) {
1285                         /* The VFTA is a 4096b bit-field, each identifying
1286                          * a single VLAN ID.  The following operations
1287                          * determine which 32b entry (i.e. offset) into the
1288                          * array we want to set the VLAN ID (i.e. bit) of
1289                          * the manageability unit.
1290                          */
1291                         vfta_offset = (hw->mng_cookie.vlan_id >>
1292                                        E1000_VFTA_ENTRY_SHIFT) &
1293                             E1000_VFTA_ENTRY_MASK;
1294                         vfta_bit_in_reg =
1295                             BIT(hw->mng_cookie.vlan_id &
1296                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1297                 }
1298                 break;
1299         default:
1300                 break;
1301         }
1302         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1303                 /* If the offset we want to clear is the same offset of the
1304                  * manageability VLAN ID, then clear all bits except that of
1305                  * the manageability unit.
1306                  */
1307                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1308                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1309                 e1e_flush();
1310         }
1311 }
1312
1313 /**
1314  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1315  *  @hw: pointer to the HW structure
1316  *
1317  *  Reads the NVM Initialization Control Word 2 and returns true
1318  *  (>0) if any manageability is enabled, else false (0).
1319  **/
1320 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1321 {
1322         u16 data;
1323
1324         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1325         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1326 }
1327
1328 /**
1329  *  e1000_led_on_82574 - Turn LED on
1330  *  @hw: pointer to the HW structure
1331  *
1332  *  Turn LED on.
1333  **/
1334 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1335 {
1336         u32 ctrl;
1337         u32 i;
1338
1339         ctrl = hw->mac.ledctl_mode2;
1340         if (!(E1000_STATUS_LU & er32(STATUS))) {
1341                 /* If no link, then turn LED on by setting the invert bit
1342                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1343                  */
1344                 for (i = 0; i < 4; i++)
1345                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1346                             E1000_LEDCTL_MODE_LED_ON)
1347                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1348         }
1349         ew32(LEDCTL, ctrl);
1350
1351         return 0;
1352 }
1353
1354 /**
1355  *  e1000_check_phy_82574 - check 82574 phy hung state
1356  *  @hw: pointer to the HW structure
1357  *
1358  *  Returns whether phy is hung or not
1359  **/
1360 bool e1000_check_phy_82574(struct e1000_hw *hw)
1361 {
1362         u16 status_1kbt = 0;
1363         u16 receive_errors = 0;
1364         s32 ret_val;
1365
1366         /* Read PHY Receive Error counter first, if its is max - all F's then
1367          * read the Base1000T status register If both are max then PHY is hung.
1368          */
1369         ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1370         if (ret_val)
1371                 return false;
1372         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1373                 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1374                 if (ret_val)
1375                         return false;
1376                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1377                     E1000_IDLE_ERROR_COUNT_MASK)
1378                         return true;
1379         }
1380
1381         return false;
1382 }
1383
1384 /**
1385  *  e1000_setup_link_82571 - Setup flow control and link settings
1386  *  @hw: pointer to the HW structure
1387  *
1388  *  Determines which flow control settings to use, then configures flow
1389  *  control.  Calls the appropriate media-specific link configuration
1390  *  function.  Assuming the adapter has a valid link partner, a valid link
1391  *  should be established.  Assumes the hardware has previously been reset
1392  *  and the transmitter and receiver are not enabled.
1393  **/
1394 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1395 {
1396         /* 82573 does not have a word in the NVM to determine
1397          * the default flow control setting, so we explicitly
1398          * set it to full.
1399          */
1400         switch (hw->mac.type) {
1401         case e1000_82573:
1402         case e1000_82574:
1403         case e1000_82583:
1404                 if (hw->fc.requested_mode == e1000_fc_default)
1405                         hw->fc.requested_mode = e1000_fc_full;
1406                 break;
1407         default:
1408                 break;
1409         }
1410
1411         return e1000e_setup_link_generic(hw);
1412 }
1413
1414 /**
1415  *  e1000_setup_copper_link_82571 - Configure copper link settings
1416  *  @hw: pointer to the HW structure
1417  *
1418  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1419  *  for link, once link is established calls to configure collision distance
1420  *  and flow control are called.
1421  **/
1422 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1423 {
1424         u32 ctrl;
1425         s32 ret_val;
1426
1427         ctrl = er32(CTRL);
1428         ctrl |= E1000_CTRL_SLU;
1429         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1430         ew32(CTRL, ctrl);
1431
1432         switch (hw->phy.type) {
1433         case e1000_phy_m88:
1434         case e1000_phy_bm:
1435                 ret_val = e1000e_copper_link_setup_m88(hw);
1436                 break;
1437         case e1000_phy_igp_2:
1438                 ret_val = e1000e_copper_link_setup_igp(hw);
1439                 break;
1440         default:
1441                 return -E1000_ERR_PHY;
1442         }
1443
1444         if (ret_val)
1445                 return ret_val;
1446
1447         return e1000e_setup_copper_link(hw);
1448 }
1449
1450 /**
1451  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1452  *  @hw: pointer to the HW structure
1453  *
1454  *  Configures collision distance and flow control for fiber and serdes links.
1455  *  Upon successful setup, poll for link.
1456  **/
1457 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1458 {
1459         switch (hw->mac.type) {
1460         case e1000_82571:
1461         case e1000_82572:
1462                 /* If SerDes loopback mode is entered, there is no form
1463                  * of reset to take the adapter out of that mode.  So we
1464                  * have to explicitly take the adapter out of loopback
1465                  * mode.  This prevents drivers from twiddling their thumbs
1466                  * if another tool failed to take it out of loopback mode.
1467                  */
1468                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1469                 break;
1470         default:
1471                 break;
1472         }
1473
1474         return e1000e_setup_fiber_serdes_link(hw);
1475 }
1476
1477 /**
1478  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1479  *  @hw: pointer to the HW structure
1480  *
1481  *  Reports the link state as up or down.
1482  *
1483  *  If autonegotiation is supported by the link partner, the link state is
1484  *  determined by the result of autonegotiation. This is the most likely case.
1485  *  If autonegotiation is not supported by the link partner, and the link
1486  *  has a valid signal, force the link up.
1487  *
1488  *  The link state is represented internally here by 4 states:
1489  *
1490  *  1) down
1491  *  2) autoneg_progress
1492  *  3) autoneg_complete (the link successfully autonegotiated)
1493  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1494  *
1495  **/
1496 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1497 {
1498         struct e1000_mac_info *mac = &hw->mac;
1499         u32 rxcw;
1500         u32 ctrl;
1501         u32 status;
1502         u32 txcw;
1503         u32 i;
1504         s32 ret_val = 0;
1505
1506         ctrl = er32(CTRL);
1507         status = er32(STATUS);
1508         er32(RXCW);
1509         /* SYNCH bit and IV bit are sticky */
1510         usleep_range(10, 20);
1511         rxcw = er32(RXCW);
1512
1513         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1514                 /* Receiver is synchronized with no invalid bits.  */
1515                 switch (mac->serdes_link_state) {
1516                 case e1000_serdes_link_autoneg_complete:
1517                         if (!(status & E1000_STATUS_LU)) {
1518                                 /* We have lost link, retry autoneg before
1519                                  * reporting link failure
1520                                  */
1521                                 mac->serdes_link_state =
1522                                     e1000_serdes_link_autoneg_progress;
1523                                 mac->serdes_has_link = false;
1524                                 e_dbg("AN_UP     -> AN_PROG\n");
1525                         } else {
1526                                 mac->serdes_has_link = true;
1527                         }
1528                         break;
1529
1530                 case e1000_serdes_link_forced_up:
1531                         /* If we are receiving /C/ ordered sets, re-enable
1532                          * auto-negotiation in the TXCW register and disable
1533                          * forced link in the Device Control register in an
1534                          * attempt to auto-negotiate with our link partner.
1535                          */
1536                         if (rxcw & E1000_RXCW_C) {
1537                                 /* Enable autoneg, and unforce link up */
1538                                 ew32(TXCW, mac->txcw);
1539                                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1540                                 mac->serdes_link_state =
1541                                     e1000_serdes_link_autoneg_progress;
1542                                 mac->serdes_has_link = false;
1543                                 e_dbg("FORCED_UP -> AN_PROG\n");
1544                         } else {
1545                                 mac->serdes_has_link = true;
1546                         }
1547                         break;
1548
1549                 case e1000_serdes_link_autoneg_progress:
1550                         if (rxcw & E1000_RXCW_C) {
1551                                 /* We received /C/ ordered sets, meaning the
1552                                  * link partner has autonegotiated, and we can
1553                                  * trust the Link Up (LU) status bit.
1554                                  */
1555                                 if (status & E1000_STATUS_LU) {
1556                                         mac->serdes_link_state =
1557                                             e1000_serdes_link_autoneg_complete;
1558                                         e_dbg("AN_PROG   -> AN_UP\n");
1559                                         mac->serdes_has_link = true;
1560                                 } else {
1561                                         /* Autoneg completed, but failed. */
1562                                         mac->serdes_link_state =
1563                                             e1000_serdes_link_down;
1564                                         e_dbg("AN_PROG   -> DOWN\n");
1565                                 }
1566                         } else {
1567                                 /* The link partner did not autoneg.
1568                                  * Force link up and full duplex, and change
1569                                  * state to forced.
1570                                  */
1571                                 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1572                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1573                                 ew32(CTRL, ctrl);
1574
1575                                 /* Configure Flow Control after link up. */
1576                                 ret_val = e1000e_config_fc_after_link_up(hw);
1577                                 if (ret_val) {
1578                                         e_dbg("Error config flow control\n");
1579                                         break;
1580                                 }
1581                                 mac->serdes_link_state =
1582                                     e1000_serdes_link_forced_up;
1583                                 mac->serdes_has_link = true;
1584                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1585                         }
1586                         break;
1587
1588                 case e1000_serdes_link_down:
1589                 default:
1590                         /* The link was down but the receiver has now gained
1591                          * valid sync, so lets see if we can bring the link
1592                          * up.
1593                          */
1594                         ew32(TXCW, mac->txcw);
1595                         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1596                         mac->serdes_link_state =
1597                             e1000_serdes_link_autoneg_progress;
1598                         mac->serdes_has_link = false;
1599                         e_dbg("DOWN      -> AN_PROG\n");
1600                         break;
1601                 }
1602         } else {
1603                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1604                         mac->serdes_has_link = false;
1605                         mac->serdes_link_state = e1000_serdes_link_down;
1606                         e_dbg("ANYSTATE  -> DOWN\n");
1607                 } else {
1608                         /* Check several times, if SYNCH bit and CONFIG
1609                          * bit both are consistently 1 then simply ignore
1610                          * the IV bit and restart Autoneg
1611                          */
1612                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1613                                 usleep_range(10, 20);
1614                                 rxcw = er32(RXCW);
1615                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1616                                     (rxcw & E1000_RXCW_C))
1617                                         continue;
1618
1619                                 if (rxcw & E1000_RXCW_IV) {
1620                                         mac->serdes_has_link = false;
1621                                         mac->serdes_link_state =
1622                                             e1000_serdes_link_down;
1623                                         e_dbg("ANYSTATE  -> DOWN\n");
1624                                         break;
1625                                 }
1626                         }
1627
1628                         if (i == AN_RETRY_COUNT) {
1629                                 txcw = er32(TXCW);
1630                                 txcw |= E1000_TXCW_ANE;
1631                                 ew32(TXCW, txcw);
1632                                 mac->serdes_link_state =
1633                                     e1000_serdes_link_autoneg_progress;
1634                                 mac->serdes_has_link = false;
1635                                 e_dbg("ANYSTATE  -> AN_PROG\n");
1636                         }
1637                 }
1638         }
1639
1640         return ret_val;
1641 }
1642
1643 /**
1644  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1645  *  @hw: pointer to the HW structure
1646  *  @data: pointer to the NVM (EEPROM)
1647  *
1648  *  Read the EEPROM for the current default LED configuration.  If the
1649  *  LED configuration is not valid, set to a valid LED configuration.
1650  **/
1651 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1652 {
1653         s32 ret_val;
1654
1655         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1656         if (ret_val) {
1657                 e_dbg("NVM Read Error\n");
1658                 return ret_val;
1659         }
1660
1661         switch (hw->mac.type) {
1662         case e1000_82573:
1663         case e1000_82574:
1664         case e1000_82583:
1665                 if (*data == ID_LED_RESERVED_F746)
1666                         *data = ID_LED_DEFAULT_82573;
1667                 break;
1668         default:
1669                 if (*data == ID_LED_RESERVED_0000 ||
1670                     *data == ID_LED_RESERVED_FFFF)
1671                         *data = ID_LED_DEFAULT;
1672                 break;
1673         }
1674
1675         return 0;
1676 }
1677
1678 /**
1679  *  e1000e_get_laa_state_82571 - Get locally administered address state
1680  *  @hw: pointer to the HW structure
1681  *
1682  *  Retrieve and return the current locally administered address state.
1683  **/
1684 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1685 {
1686         if (hw->mac.type != e1000_82571)
1687                 return false;
1688
1689         return hw->dev_spec.e82571.laa_is_present;
1690 }
1691
1692 /**
1693  *  e1000e_set_laa_state_82571 - Set locally administered address state
1694  *  @hw: pointer to the HW structure
1695  *  @state: enable/disable locally administered address
1696  *
1697  *  Enable/Disable the current locally administered address state.
1698  **/
1699 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1700 {
1701         if (hw->mac.type != e1000_82571)
1702                 return;
1703
1704         hw->dev_spec.e82571.laa_is_present = state;
1705
1706         /* If workaround is activated... */
1707         if (state)
1708                 /* Hold a copy of the LAA in RAR[14] This is done so that
1709                  * between the time RAR[0] gets clobbered and the time it
1710                  * gets fixed, the actual LAA is in one of the RARs and no
1711                  * incoming packets directed to this port are dropped.
1712                  * Eventually the LAA will be in RAR[0] and RAR[14].
1713                  */
1714                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1715                                     hw->mac.rar_entry_count - 1);
1716 }
1717
1718 /**
1719  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1720  *  @hw: pointer to the HW structure
1721  *
1722  *  Verifies that the EEPROM has completed the update.  After updating the
1723  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1724  *  the checksum fix is not implemented, we need to set the bit and update
1725  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1726  *  we need to return bad checksum.
1727  **/
1728 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1729 {
1730         struct e1000_nvm_info *nvm = &hw->nvm;
1731         s32 ret_val;
1732         u16 data;
1733
1734         if (nvm->type != e1000_nvm_flash_hw)
1735                 return 0;
1736
1737         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1738          * 10h-12h.  Checksum may need to be fixed.
1739          */
1740         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1741         if (ret_val)
1742                 return ret_val;
1743
1744         if (!(data & 0x10)) {
1745                 /* Read 0x23 and check bit 15.  This bit is a 1
1746                  * when the checksum has already been fixed.  If
1747                  * the checksum is still wrong and this bit is a
1748                  * 1, we need to return bad checksum.  Otherwise,
1749                  * we need to set this bit to a 1 and update the
1750                  * checksum.
1751                  */
1752                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1753                 if (ret_val)
1754                         return ret_val;
1755
1756                 if (!(data & 0x8000)) {
1757                         data |= 0x8000;
1758                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1759                         if (ret_val)
1760                                 return ret_val;
1761                         ret_val = e1000e_update_nvm_checksum(hw);
1762                         if (ret_val)
1763                                 return ret_val;
1764                 }
1765         }
1766
1767         return 0;
1768 }
1769
1770 /**
1771  *  e1000_read_mac_addr_82571 - Read device MAC address
1772  *  @hw: pointer to the HW structure
1773  **/
1774 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1775 {
1776         if (hw->mac.type == e1000_82571) {
1777                 s32 ret_val;
1778
1779                 /* If there's an alternate MAC address place it in RAR0
1780                  * so that it will override the Si installed default perm
1781                  * address.
1782                  */
1783                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1784                 if (ret_val)
1785                         return ret_val;
1786         }
1787
1788         return e1000_read_mac_addr_generic(hw);
1789 }
1790
1791 /**
1792  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1793  * @hw: pointer to the HW structure
1794  *
1795  * In the case of a PHY power down to save power, or to turn off link during a
1796  * driver unload, or wake on lan is not enabled, remove the link.
1797  **/
1798 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1799 {
1800         struct e1000_phy_info *phy = &hw->phy;
1801         struct e1000_mac_info *mac = &hw->mac;
1802
1803         if (!phy->ops.check_reset_block)
1804                 return;
1805
1806         /* If the management interface is not enabled, then power down */
1807         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1808                 e1000_power_down_phy_copper(hw);
1809 }
1810
1811 /**
1812  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1813  *  @hw: pointer to the HW structure
1814  *
1815  *  Clears the hardware counters by reading the counter registers.
1816  **/
1817 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1818 {
1819         e1000e_clear_hw_cntrs_base(hw);
1820
1821         er32(PRC64);
1822         er32(PRC127);
1823         er32(PRC255);
1824         er32(PRC511);
1825         er32(PRC1023);
1826         er32(PRC1522);
1827         er32(PTC64);
1828         er32(PTC127);
1829         er32(PTC255);
1830         er32(PTC511);
1831         er32(PTC1023);
1832         er32(PTC1522);
1833
1834         er32(ALGNERRC);
1835         er32(RXERRC);
1836         er32(TNCRS);
1837         er32(CEXTERR);
1838         er32(TSCTC);
1839         er32(TSCTFC);
1840
1841         er32(MGTPRC);
1842         er32(MGTPDC);
1843         er32(MGTPTC);
1844
1845         er32(IAC);
1846         er32(ICRXOC);
1847
1848         er32(ICRXPTC);
1849         er32(ICRXATC);
1850         er32(ICTXPTC);
1851         er32(ICTXATC);
1852         er32(ICTXQEC);
1853         er32(ICTXQMTC);
1854         er32(ICRXDMTC);
1855 }
1856
1857 static const struct e1000_mac_operations e82571_mac_ops = {
1858         /* .check_mng_mode: mac type dependent */
1859         /* .check_for_link: media type dependent */
1860         .id_led_init            = e1000e_id_led_init_generic,
1861         .cleanup_led            = e1000e_cleanup_led_generic,
1862         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1863         .get_bus_info           = e1000e_get_bus_info_pcie,
1864         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1865         /* .get_link_up_info: media type dependent */
1866         /* .led_on: mac type dependent */
1867         .led_off                = e1000e_led_off_generic,
1868         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1869         .write_vfta             = e1000_write_vfta_generic,
1870         .clear_vfta             = e1000_clear_vfta_82571,
1871         .reset_hw               = e1000_reset_hw_82571,
1872         .init_hw                = e1000_init_hw_82571,
1873         .setup_link             = e1000_setup_link_82571,
1874         /* .setup_physical_interface: media type dependent */
1875         .setup_led              = e1000e_setup_led_generic,
1876         .config_collision_dist  = e1000e_config_collision_dist_generic,
1877         .read_mac_addr          = e1000_read_mac_addr_82571,
1878         .rar_set                = e1000e_rar_set_generic,
1879         .rar_get_count          = e1000e_rar_get_count_generic,
1880 };
1881
1882 static const struct e1000_phy_operations e82_phy_ops_igp = {
1883         .acquire                = e1000_get_hw_semaphore_82571,
1884         .check_polarity         = e1000_check_polarity_igp,
1885         .check_reset_block      = e1000e_check_reset_block_generic,
1886         .commit                 = NULL,
1887         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1888         .get_cfg_done           = e1000_get_cfg_done_82571,
1889         .get_cable_length       = e1000e_get_cable_length_igp_2,
1890         .get_info               = e1000e_get_phy_info_igp,
1891         .read_reg               = e1000e_read_phy_reg_igp,
1892         .release                = e1000_put_hw_semaphore_82571,
1893         .reset                  = e1000e_phy_hw_reset_generic,
1894         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1895         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1896         .write_reg              = e1000e_write_phy_reg_igp,
1897         .cfg_on_link_up         = NULL,
1898 };
1899
1900 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1901         .acquire                = e1000_get_hw_semaphore_82571,
1902         .check_polarity         = e1000_check_polarity_m88,
1903         .check_reset_block      = e1000e_check_reset_block_generic,
1904         .commit                 = e1000e_phy_sw_reset,
1905         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1906         .get_cfg_done           = e1000e_get_cfg_done_generic,
1907         .get_cable_length       = e1000e_get_cable_length_m88,
1908         .get_info               = e1000e_get_phy_info_m88,
1909         .read_reg               = e1000e_read_phy_reg_m88,
1910         .release                = e1000_put_hw_semaphore_82571,
1911         .reset                  = e1000e_phy_hw_reset_generic,
1912         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1913         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1914         .write_reg              = e1000e_write_phy_reg_m88,
1915         .cfg_on_link_up         = NULL,
1916 };
1917
1918 static const struct e1000_phy_operations e82_phy_ops_bm = {
1919         .acquire                = e1000_get_hw_semaphore_82571,
1920         .check_polarity         = e1000_check_polarity_m88,
1921         .check_reset_block      = e1000e_check_reset_block_generic,
1922         .commit                 = e1000e_phy_sw_reset,
1923         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1924         .get_cfg_done           = e1000e_get_cfg_done_generic,
1925         .get_cable_length       = e1000e_get_cable_length_m88,
1926         .get_info               = e1000e_get_phy_info_m88,
1927         .read_reg               = e1000e_read_phy_reg_bm2,
1928         .release                = e1000_put_hw_semaphore_82571,
1929         .reset                  = e1000e_phy_hw_reset_generic,
1930         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1931         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1932         .write_reg              = e1000e_write_phy_reg_bm2,
1933         .cfg_on_link_up         = NULL,
1934 };
1935
1936 static const struct e1000_nvm_operations e82571_nvm_ops = {
1937         .acquire                = e1000_acquire_nvm_82571,
1938         .read                   = e1000e_read_nvm_eerd,
1939         .release                = e1000_release_nvm_82571,
1940         .reload                 = e1000e_reload_nvm_generic,
1941         .update                 = e1000_update_nvm_checksum_82571,
1942         .valid_led_default      = e1000_valid_led_default_82571,
1943         .validate               = e1000_validate_nvm_checksum_82571,
1944         .write                  = e1000_write_nvm_82571,
1945 };
1946
1947 const struct e1000_info e1000_82571_info = {
1948         .mac                    = e1000_82571,
1949         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1950                                   | FLAG_HAS_JUMBO_FRAMES
1951                                   | FLAG_HAS_WOL
1952                                   | FLAG_APME_IN_CTRL3
1953                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1954                                   | FLAG_HAS_SMART_POWER_DOWN
1955                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1956                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1957                                   | FLAG_APME_CHECK_PORT_B,
1958         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1959                                   | FLAG2_DMA_BURST,
1960         .pba                    = 38,
1961         .max_hw_frame_size      = DEFAULT_JUMBO,
1962         .get_variants           = e1000_get_variants_82571,
1963         .mac_ops                = &e82571_mac_ops,
1964         .phy_ops                = &e82_phy_ops_igp,
1965         .nvm_ops                = &e82571_nvm_ops,
1966 };
1967
1968 const struct e1000_info e1000_82572_info = {
1969         .mac                    = e1000_82572,
1970         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1971                                   | FLAG_HAS_JUMBO_FRAMES
1972                                   | FLAG_HAS_WOL
1973                                   | FLAG_APME_IN_CTRL3
1974                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1975                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1976         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1977                                   | FLAG2_DMA_BURST,
1978         .pba                    = 38,
1979         .max_hw_frame_size      = DEFAULT_JUMBO,
1980         .get_variants           = e1000_get_variants_82571,
1981         .mac_ops                = &e82571_mac_ops,
1982         .phy_ops                = &e82_phy_ops_igp,
1983         .nvm_ops                = &e82571_nvm_ops,
1984 };
1985
1986 const struct e1000_info e1000_82573_info = {
1987         .mac                    = e1000_82573,
1988         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1989                                   | FLAG_HAS_WOL
1990                                   | FLAG_APME_IN_CTRL3
1991                                   | FLAG_HAS_SMART_POWER_DOWN
1992                                   | FLAG_HAS_AMT
1993                                   | FLAG_HAS_SWSM_ON_LOAD,
1994         .flags2                 = FLAG2_DISABLE_ASPM_L1
1995                                   | FLAG2_DISABLE_ASPM_L0S,
1996         .pba                    = 20,
1997         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
1998         .get_variants           = e1000_get_variants_82571,
1999         .mac_ops                = &e82571_mac_ops,
2000         .phy_ops                = &e82_phy_ops_m88,
2001         .nvm_ops                = &e82571_nvm_ops,
2002 };
2003
2004 const struct e1000_info e1000_82574_info = {
2005         .mac                    = e1000_82574,
2006         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2007                                   | FLAG_HAS_MSIX
2008                                   | FLAG_HAS_JUMBO_FRAMES
2009                                   | FLAG_HAS_WOL
2010                                   | FLAG_HAS_HW_TIMESTAMP
2011                                   | FLAG_APME_IN_CTRL3
2012                                   | FLAG_HAS_SMART_POWER_DOWN
2013                                   | FLAG_HAS_AMT
2014                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2015         .flags2                  = FLAG2_CHECK_PHY_HANG
2016                                   | FLAG2_DISABLE_ASPM_L0S
2017                                   | FLAG2_DISABLE_ASPM_L1
2018                                   | FLAG2_NO_DISABLE_RX
2019                                   | FLAG2_DMA_BURST
2020                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
2021         .pba                    = 32,
2022         .max_hw_frame_size      = DEFAULT_JUMBO,
2023         .get_variants           = e1000_get_variants_82571,
2024         .mac_ops                = &e82571_mac_ops,
2025         .phy_ops                = &e82_phy_ops_bm,
2026         .nvm_ops                = &e82571_nvm_ops,
2027 };
2028
2029 const struct e1000_info e1000_82583_info = {
2030         .mac                    = e1000_82583,
2031         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2032                                   | FLAG_HAS_WOL
2033                                   | FLAG_HAS_HW_TIMESTAMP
2034                                   | FLAG_APME_IN_CTRL3
2035                                   | FLAG_HAS_SMART_POWER_DOWN
2036                                   | FLAG_HAS_AMT
2037                                   | FLAG_HAS_JUMBO_FRAMES
2038                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2039         .flags2                 = FLAG2_DISABLE_ASPM_L0S
2040                                   | FLAG2_DISABLE_ASPM_L1
2041                                   | FLAG2_NO_DISABLE_RX
2042                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
2043         .pba                    = 32,
2044         .max_hw_frame_size      = DEFAULT_JUMBO,
2045         .get_variants           = e1000_get_variants_82571,
2046         .mac_ops                = &e82571_mac_ops,
2047         .phy_ops                = &e82_phy_ops_bm,
2048         .nvm_ops                = &e82571_nvm_ops,
2049 };