drivers/net/ethernet/intel/e1000e/82571.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82571EB Gigabit Ethernet Controller
  23  * 82571EB Gigabit Ethernet Controller (Copper)
  24  * 82571EB Gigabit Ethernet Controller (Fiber)
  25  * 82571EB Dual Port Gigabit Mezzanine Adapter
  26  * 82571EB Quad Port Gigabit Mezzanine Adapter
  27  * 82571PT Gigabit PT Quad Port Server ExpressModule
  28  * 82572EI Gigabit Ethernet Controller (Copper)
  29  * 82572EI Gigabit Ethernet Controller (Fiber)
  30  * 82572EI Gigabit Ethernet Controller
  31  * 82573V Gigabit Ethernet Controller (Copper)
  32  * 82573E Gigabit Ethernet Controller (Copper)
  33  * 82573L Gigabit Ethernet Controller
  34  * 82574L Gigabit Network Connection
  35  * 82583V Gigabit Network Connection
  36  */
  37
  38 #include "e1000.h"
  39
  40 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  41 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  42 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  43 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  44 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  45                                       u16 words, u16 *data);
  46 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  47 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  48 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  49 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  50 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  51 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  52 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  53 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  54 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  55 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  56 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
  57 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
  58
  59 /**
  60  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  61  *  @hw: pointer to the HW structure
  62  **/
  63 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  64 {
  65         struct e1000_phy_info *phy = &hw->phy;
  66         s32 ret_val;
  67
  68         if (hw->phy.media_type != e1000_media_type_copper) {
  69                 phy->type = e1000_phy_none;
  70                 return 0;
  71         }
  72
  73         phy->addr = 1;
  74         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  75         phy->reset_delay_us = 100;
  76
  77         phy->ops.power_up = e1000_power_up_phy_copper;
  78         phy->ops.power_down = e1000_power_down_phy_copper_82571;
  79
  80         switch (hw->mac.type) {
  81         case e1000_82571:
  82         case e1000_82572:
  83                 phy->type = e1000_phy_igp_2;
  84                 break;
  85         case e1000_82573:
  86                 phy->type = e1000_phy_m88;
  87                 break;
  88         case e1000_82574:
  89         case e1000_82583:
  90                 phy->type = e1000_phy_bm;
  91                 phy->ops.acquire = e1000_get_hw_semaphore_82574;
  92                 phy->ops.release = e1000_put_hw_semaphore_82574;
  93                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
  94                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
  95                 break;
  96         default:
  97                 return -E1000_ERR_PHY;
  98         }
  99
 100         /* This can only be done after all function pointers are setup. */
 101         ret_val = e1000_get_phy_id_82571(hw);
 102         if (ret_val) {
 103                 e_dbg("Error getting PHY ID\n");
 104                 return ret_val;
 105         }
 106
 107         /* Verify phy id */
 108         switch (hw->mac.type) {
 109         case e1000_82571:
 110         case e1000_82572:
 111                 if (phy->id != IGP01E1000_I_PHY_ID)
 112                         ret_val = -E1000_ERR_PHY;
 113                 break;
 114         case e1000_82573:
 115                 if (phy->id != M88E1111_I_PHY_ID)
 116                         ret_val = -E1000_ERR_PHY;
 117                 break;
 118         case e1000_82574:
 119         case e1000_82583:
 120                 if (phy->id != BME1000_E_PHY_ID_R2)
 121                         ret_val = -E1000_ERR_PHY;
 122                 break;
 123         default:
 124                 ret_val = -E1000_ERR_PHY;
 125                 break;
 126         }
 127
 128         if (ret_val)
 129                 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
 130
 131         return ret_val;
 132 }
 133
 134 /**
 135  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 136  *  @hw: pointer to the HW structure
 137  **/
 138 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 139 {
 140         struct e1000_nvm_info *nvm = &hw->nvm;
 141         u32 eecd = er32(EECD);
 142         u16 size;
 143
 144         nvm->opcode_bits = 8;
 145         nvm->delay_usec = 1;
 146         switch (nvm->override) {
 147         case e1000_nvm_override_spi_large:
 148                 nvm->page_size = 32;
 149                 nvm->address_bits = 16;
 150                 break;
 151         case e1000_nvm_override_spi_small:
 152                 nvm->page_size = 8;
 153                 nvm->address_bits = 8;
 154                 break;
 155         default:
 156                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 157                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 158                 break;
 159         }
 160
 161         switch (hw->mac.type) {
 162         case e1000_82573:
 163         case e1000_82574:
 164         case e1000_82583:
 165                 if (((eecd >> 15) & 0x3) == 0x3) {
 166                         nvm->type = e1000_nvm_flash_hw;
 167                         nvm->word_size = 2048;
 168                         /* Autonomous Flash update bit must be cleared due
 169                          * to Flash update issue.
 170                          */
 171                         eecd &= ~E1000_EECD_AUPDEN;
 172                         ew32(EECD, eecd);
 173                         break;
 174                 }
 175                 /* Fall Through */
 176         default:
 177                 nvm->type = e1000_nvm_eeprom_spi;
 178                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 179                              E1000_EECD_SIZE_EX_SHIFT);
 180                 /* Added to a constant, "size" becomes the left-shift value
 181                  * for setting word_size.
 182                  */
 183                 size += NVM_WORD_SIZE_BASE_SHIFT;
 184
 185                 /* EEPROM access above 16k is unsupported */
 186                 if (size > 14)
 187                         size = 14;
 188                 nvm->word_size = BIT(size);
 189                 break;
 190         }
 191
 192         /* Function Pointers */
 193         switch (hw->mac.type) {
 194         case e1000_82574:
 195         case e1000_82583:
 196                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 197                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 198                 break;
 199         default:
 200                 break;
 201         }
 202
 203         return 0;
 204 }
 205
 206 /**
 207  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 208  *  @hw: pointer to the HW structure
 209  **/
 210 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 211 {
 212         struct e1000_mac_info *mac = &hw->mac;
 213         u32 swsm = 0;
 214         u32 swsm2 = 0;
 215         bool force_clear_smbi = false;
 216
 217         /* Set media type and media-dependent function pointers */
 218         switch (hw->adapter->pdev->device) {
 219         case E1000_DEV_ID_82571EB_FIBER:
 220         case E1000_DEV_ID_82572EI_FIBER:
 221         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 222                 hw->phy.media_type = e1000_media_type_fiber;
 223                 mac->ops.setup_physical_interface =
 224                     e1000_setup_fiber_serdes_link_82571;
 225                 mac->ops.check_for_link = e1000e_check_for_fiber_link;
 226                 mac->ops.get_link_up_info =
 227                     e1000e_get_speed_and_duplex_fiber_serdes;
 228                 break;
 229         case E1000_DEV_ID_82571EB_SERDES:
 230         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 231         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 232         case E1000_DEV_ID_82572EI_SERDES:
 233                 hw->phy.media_type = e1000_media_type_internal_serdes;
 234                 mac->ops.setup_physical_interface =
 235                     e1000_setup_fiber_serdes_link_82571;
 236                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 237                 mac->ops.get_link_up_info =
 238                     e1000e_get_speed_and_duplex_fiber_serdes;
 239                 break;
 240         default:
 241                 hw->phy.media_type = e1000_media_type_copper;
 242                 mac->ops.setup_physical_interface =
 243                     e1000_setup_copper_link_82571;
 244                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 245                 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
 246                 break;
 247         }
 248
 249         /* Set mta register count */
 250         mac->mta_reg_count = 128;
 251         /* Set rar entry count */
 252         mac->rar_entry_count = E1000_RAR_ENTRIES;
 253         /* Adaptive IFS supported */
 254         mac->adaptive_ifs = true;
 255
 256         /* MAC-specific function pointers */
 257         switch (hw->mac.type) {
 258         case e1000_82573:
 259                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 260                 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 261                 mac->ops.led_on = e1000e_led_on_generic;
 262                 mac->ops.blink_led = e1000e_blink_led_generic;
 263
 264                 /* FWSM register */
 265                 mac->has_fwsm = true;
 266                 /* ARC supported; valid only if manageability features are
 267                  * enabled.
 268                  */
 269                 mac->arc_subsystem_valid = !!(er32(FWSM) &
 270                                               E1000_FWSM_MODE_MASK);
 271                 break;
 272         case e1000_82574:
 273         case e1000_82583:
 274                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 275                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 276                 mac->ops.led_on = e1000_led_on_82574;
 277                 break;
 278         default:
 279                 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 280                 mac->ops.led_on = e1000e_led_on_generic;
 281                 mac->ops.blink_led = e1000e_blink_led_generic;
 282
 283                 /* FWSM register */
 284                 mac->has_fwsm = true;
 285                 break;
 286         }
 287
 288         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 289          * first NVM or PHY access. This should be done for single-port
 290          * devices, and for one port only on dual-port devices so that
 291          * for those devices we can still use the SMBI lock to synchronize
 292          * inter-port accesses to the PHY & NVM.
 293          */
 294         switch (hw->mac.type) {
 295         case e1000_82571:
 296         case e1000_82572:
 297                 swsm2 = er32(SWSM2);
 298
 299                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 300                         /* Only do this for the first interface on this card */
 301                         ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
 302                         force_clear_smbi = true;
 303                 } else {
 304                         force_clear_smbi = false;
 305                 }
 306                 break;
 307         default:
 308                 force_clear_smbi = true;
 309                 break;
 310         }
 311
 312         if (force_clear_smbi) {
 313                 /* Make sure SWSM.SMBI is clear */
 314                 swsm = er32(SWSM);
 315                 if (swsm & E1000_SWSM_SMBI) {
 316                         /* This bit should not be set on a first interface, and
 317                          * indicates that the bootagent or EFI code has
 318                          * improperly left this bit enabled
 319                          */
 320                         e_dbg("Please update your 82571 Bootagent\n");
 321                 }
 322                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 323         }
 324
 325         /* Initialize device specific counter of SMBI acquisition timeouts. */
 326         hw->dev_spec.e82571.smb_counter = 0;
 327
 328         return 0;
 329 }
 330
 331 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 332 {
 333         struct e1000_hw *hw = &adapter->hw;
 334         static int global_quad_port_a;  /* global port a indication */
 335         struct pci_dev *pdev = adapter->pdev;
 336         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 337         s32 rc;
 338
 339         rc = e1000_init_mac_params_82571(hw);
 340         if (rc)
 341                 return rc;
 342
 343         rc = e1000_init_nvm_params_82571(hw);
 344         if (rc)
 345                 return rc;
 346
 347         rc = e1000_init_phy_params_82571(hw);
 348         if (rc)
 349                 return rc;
 350
 351         /* tag quad port adapters first, it's used below */
 352         switch (pdev->device) {
 353         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 354         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 355         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 356         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 357                 adapter->flags |= FLAG_IS_QUAD_PORT;
 358                 /* mark the first port */
 359                 if (global_quad_port_a == 0)
 360                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 361                 /* Reset for multiple quad port adapters */
 362                 global_quad_port_a++;
 363                 if (global_quad_port_a == 4)
 364                         global_quad_port_a = 0;
 365                 break;
 366         default:
 367                 break;
 368         }
 369
 370         switch (adapter->hw.mac.type) {
 371         case e1000_82571:
 372                 /* these dual ports don't have WoL on port B at all */
 373                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 374                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 375                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 376                     (is_port_b))
 377                         adapter->flags &= ~FLAG_HAS_WOL;
 378                 /* quad ports only support WoL on port A */
 379                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 380                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 381                         adapter->flags &= ~FLAG_HAS_WOL;
 382                 /* Does not support WoL on any port */
 383                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 384                         adapter->flags &= ~FLAG_HAS_WOL;
 385                 break;
 386         case e1000_82573:
 387                 if (pdev->device == E1000_DEV_ID_82573L) {
 388                         adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 389                         adapter->max_hw_frame_size = DEFAULT_JUMBO;
 390                 }
 391                 break;
 392         default:
 393                 break;
 394         }
 395
 396         return 0;
 397 }
 398
 399 /**
 400  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 401  *  @hw: pointer to the HW structure
 402  *
 403  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 404  *  revision in the hardware structure.
 405  **/
 406 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 407 {
 408         struct e1000_phy_info *phy = &hw->phy;
 409         s32 ret_val;
 410         u16 phy_id = 0;
 411
 412         switch (hw->mac.type) {
 413         case e1000_82571:
 414         case e1000_82572:
 415                 /* The 82571 firmware may still be configuring the PHY.
 416                  * In this case, we cannot access the PHY until the
 417                  * configuration is done.  So we explicitly set the
 418                  * PHY ID.
 419                  */
 420                 phy->id = IGP01E1000_I_PHY_ID;
 421                 break;
 422         case e1000_82573:
 423                 return e1000e_get_phy_id(hw);
 424         case e1000_82574:
 425         case e1000_82583:
 426                 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
 427                 if (ret_val)
 428                         return ret_val;
 429
 430                 phy->id = (u32)(phy_id << 16);
 431                 usleep_range(20, 40);
 432                 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
 433                 if (ret_val)
 434                         return ret_val;
 435
 436                 phy->id |= (u32)(phy_id);
 437                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 438                 break;
 439         default:
 440                 return -E1000_ERR_PHY;
 441         }
 442
 443         return 0;
 444 }
 445
 446 /**
 447  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 448  *  @hw: pointer to the HW structure
 449  *
 450  *  Acquire the HW semaphore to access the PHY or NVM
 451  **/
 452 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 453 {
 454         u32 swsm;
 455         s32 sw_timeout = hw->nvm.word_size + 1;
 456         s32 fw_timeout = hw->nvm.word_size + 1;
 457         s32 i = 0;
 458
 459         /* If we have timedout 3 times on trying to acquire
 460          * the inter-port SMBI semaphore, there is old code
 461          * operating on the other port, and it is not
 462          * releasing SMBI. Modify the number of times that
 463          * we try for the semaphore to interwork with this
 464          * older code.
 465          */
 466         if (hw->dev_spec.e82571.smb_counter > 2)
 467                 sw_timeout = 1;
 468
 469         /* Get the SW semaphore */
 470         while (i < sw_timeout) {
 471                 swsm = er32(SWSM);
 472                 if (!(swsm & E1000_SWSM_SMBI))
 473                         break;
 474
 475                 usleep_range(50, 100);
 476                 i++;
 477         }
 478
 479         if (i == sw_timeout) {
 480                 e_dbg("Driver can't access device - SMBI bit is set.\n");
 481                 hw->dev_spec.e82571.smb_counter++;
 482         }
 483         /* Get the FW semaphore. */
 484         for (i = 0; i < fw_timeout; i++) {
 485                 swsm = er32(SWSM);
 486                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 487
 488                 /* Semaphore acquired if bit latched */
 489                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 490                         break;
 491
 492                 usleep_range(50, 100);
 493         }
 494
 495         if (i == fw_timeout) {
 496                 /* Release semaphores */
 497                 e1000_put_hw_semaphore_82571(hw);
 498                 e_dbg("Driver can't access the NVM\n");
 499                 return -E1000_ERR_NVM;
 500         }
 501
 502         return 0;
 503 }
 504
 505 /**
 506  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 507  *  @hw: pointer to the HW structure
 508  *
 509  *  Release hardware semaphore used to access the PHY or NVM
 510  **/
 511 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 512 {
 513         u32 swsm;
 514
 515         swsm = er32(SWSM);
 516         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 517         ew32(SWSM, swsm);
 518 }
 519
 520 /**
 521  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 522  *  @hw: pointer to the HW structure
 523  *
 524  *  Acquire the HW semaphore during reset.
 525  *
 526  **/
 527 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 528 {
 529         u32 extcnf_ctrl;
 530         s32 i = 0;
 531
 532         extcnf_ctrl = er32(EXTCNF_CTRL);
 533         do {
 534                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 535                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 536                 extcnf_ctrl = er32(EXTCNF_CTRL);
 537
 538                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 539                         break;
 540
 541                 usleep_range(2000, 4000);
 542                 i++;
 543         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 544
 545         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 546                 /* Release semaphores */
 547                 e1000_put_hw_semaphore_82573(hw);
 548                 e_dbg("Driver can't access the PHY\n");
 549                 return -E1000_ERR_PHY;
 550         }
 551
 552         return 0;
 553 }
 554
 555 /**
 556  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 557  *  @hw: pointer to the HW structure
 558  *
 559  *  Release hardware semaphore used during reset.
 560  *
 561  **/
 562 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 563 {
 564         u32 extcnf_ctrl;
 565
 566         extcnf_ctrl = er32(EXTCNF_CTRL);
 567         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 568         ew32(EXTCNF_CTRL, extcnf_ctrl);
 569 }
 570
 571 static DEFINE_MUTEX(swflag_mutex);
 572
 573 /**
 574  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 575  *  @hw: pointer to the HW structure
 576  *
 577  *  Acquire the HW semaphore to access the PHY or NVM.
 578  *
 579  **/
 580 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 581 {
 582         s32 ret_val;
 583
 584         mutex_lock(&swflag_mutex);
 585         ret_val = e1000_get_hw_semaphore_82573(hw);
 586         if (ret_val)
 587                 mutex_unlock(&swflag_mutex);
 588         return ret_val;
 589 }
 590
 591 /**
 592  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 593  *  @hw: pointer to the HW structure
 594  *
 595  *  Release hardware semaphore used to access the PHY or NVM
 596  *
 597  **/
 598 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 599 {
 600         e1000_put_hw_semaphore_82573(hw);
 601         mutex_unlock(&swflag_mutex);
 602 }
 603
 604 /**
 605  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 606  *  @hw: pointer to the HW structure
 607  *  @active: true to enable LPLU, false to disable
 608  *
 609  *  Sets the LPLU D0 state according to the active flag.
 610  *  LPLU will not be activated unless the
 611  *  device autonegotiation advertisement meets standards of
 612  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 613  *  This is a function pointer entry point only called by
 614  *  PHY setup routines.
 615  **/
 616 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 617 {
 618         u32 data = er32(POEMB);
 619
 620         if (active)
 621                 data |= E1000_PHY_CTRL_D0A_LPLU;
 622         else
 623                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 624
 625         ew32(POEMB, data);
 626         return 0;
 627 }
 628
 629 /**
 630  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 631  *  @hw: pointer to the HW structure
 632  *  @active: boolean used to enable/disable lplu
 633  *
 634  *  The low power link up (lplu) state is set to the power management level D3
 635  *  when active is true, else clear lplu for D3. LPLU
 636  *  is used during Dx states where the power conservation is most important.
 637  *  During driver activity, SmartSpeed should be enabled so performance is
 638  *  maintained.
 639  **/
 640 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 641 {
 642         u32 data = er32(POEMB);
 643
 644         if (!active) {
 645                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 646         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 647                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 648                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 649                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 650         }
 651
 652         ew32(POEMB, data);
 653         return 0;
 654 }
 655
 656 /**
 657  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 658  *  @hw: pointer to the HW structure
 659  *
 660  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 661  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 662  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 663  *  hardware semaphore.
 664  **/
 665 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 666 {
 667         s32 ret_val;
 668
 669         ret_val = e1000_get_hw_semaphore_82571(hw);
 670         if (ret_val)
 671                 return ret_val;
 672
 673         switch (hw->mac.type) {
 674         case e1000_82573:
 675                 break;
 676         default:
 677                 ret_val = e1000e_acquire_nvm(hw);
 678                 break;
 679         }
 680
 681         if (ret_val)
 682                 e1000_put_hw_semaphore_82571(hw);
 683
 684         return ret_val;
 685 }
 686
 687 /**
 688  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 689  *  @hw: pointer to the HW structure
 690  *
 691  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 692  **/
 693 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 694 {
 695         e1000e_release_nvm(hw);
 696         e1000_put_hw_semaphore_82571(hw);
 697 }
 698
 699 /**
 700  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 701  *  @hw: pointer to the HW structure
 702  *  @offset: offset within the EEPROM to be written to
 703  *  @words: number of words to write
 704  *  @data: 16 bit word(s) to be written to the EEPROM
 705  *
 706  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 707  *
 708  *  If e1000e_update_nvm_checksum is not called after this function, the
 709  *  EEPROM will most likely contain an invalid checksum.
 710  **/
 711 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 712                                  u16 *data)
 713 {
 714         s32 ret_val;
 715
 716         switch (hw->mac.type) {
 717         case e1000_82573:
 718         case e1000_82574:
 719         case e1000_82583:
 720                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 721                 break;
 722         case e1000_82571:
 723         case e1000_82572:
 724                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 725                 break;
 726         default:
 727                 ret_val = -E1000_ERR_NVM;
 728                 break;
 729         }
 730
 731         return ret_val;
 732 }
 733
 734 /**
 735  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 736  *  @hw: pointer to the HW structure
 737  *
 738  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 739  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 740  *  value to the EEPROM.
 741  **/
 742 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 743 {
 744         u32 eecd;
 745         s32 ret_val;
 746         u16 i;
 747
 748         ret_val = e1000e_update_nvm_checksum_generic(hw);
 749         if (ret_val)
 750                 return ret_val;
 751
 752         /* If our nvm is an EEPROM, then we're done
 753          * otherwise, commit the checksum to the flash NVM.
 754          */
 755         if (hw->nvm.type != e1000_nvm_flash_hw)
 756                 return 0;
 757
 758         /* Check for pending operations. */
 759         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 760                 usleep_range(1000, 2000);
 761                 if (!(er32(EECD) & E1000_EECD_FLUPD))
 762                         break;
 763         }
 764
 765         if (i == E1000_FLASH_UPDATES)
 766                 return -E1000_ERR_NVM;
 767
 768         /* Reset the firmware if using STM opcode. */
 769         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 770                 /* The enabling of and the actual reset must be done
 771                  * in two write cycles.
 772                  */
 773                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 774                 e1e_flush();
 775                 ew32(HICR, E1000_HICR_FW_RESET);
 776         }
 777
 778         /* Commit the write to flash */
 779         eecd = er32(EECD) | E1000_EECD_FLUPD;
 780         ew32(EECD, eecd);
 781
 782         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 783                 usleep_range(1000, 2000);
 784                 if (!(er32(EECD) & E1000_EECD_FLUPD))
 785                         break;
 786         }
 787
 788         if (i == E1000_FLASH_UPDATES)
 789                 return -E1000_ERR_NVM;
 790
 791         return 0;
 792 }
 793
 794 /**
 795  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 796  *  @hw: pointer to the HW structure
 797  *
 798  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 799  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 800  **/
 801 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 802 {
 803         if (hw->nvm.type == e1000_nvm_flash_hw)
 804                 e1000_fix_nvm_checksum_82571(hw);
 805
 806         return e1000e_validate_nvm_checksum_generic(hw);
 807 }
 808
 809 /**
 810  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 811  *  @hw: pointer to the HW structure
 812  *  @offset: offset within the EEPROM to be written to
 813  *  @words: number of words to write
 814  *  @data: 16 bit word(s) to be written to the EEPROM
 815  *
 816  *  After checking for invalid values, poll the EEPROM to ensure the previous
 817  *  command has completed before trying to write the next word.  After write
 818  *  poll for completion.
 819  *
 820  *  If e1000e_update_nvm_checksum is not called after this function, the
 821  *  EEPROM will most likely contain an invalid checksum.
 822  **/
 823 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 824                                       u16 words, u16 *data)
 825 {
 826         struct e1000_nvm_info *nvm = &hw->nvm;
 827         u32 i, eewr = 0;
 828         s32 ret_val = 0;
 829
 830         /* A check for invalid values:  offset too large, too many words,
 831          * and not enough words.
 832          */
 833         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 834             (words == 0)) {
 835                 e_dbg("nvm parameter(s) out of bounds\n");
 836                 return -E1000_ERR_NVM;
 837         }
 838
 839         for (i = 0; i < words; i++) {
 840                 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 841                         ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 842                         E1000_NVM_RW_REG_START);
 843
 844                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 845                 if (ret_val)
 846                         break;
 847
 848                 ew32(EEWR, eewr);
 849
 850                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 851                 if (ret_val)
 852                         break;
 853         }
 854
 855         return ret_val;
 856 }
 857
 858 /**
 859  *  e1000_get_cfg_done_82571 - Poll for configuration done
 860  *  @hw: pointer to the HW structure
 861  *
 862  *  Reads the management control register for the config done bit to be set.
 863  **/
 864 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 865 {
 866         s32 timeout = PHY_CFG_TIMEOUT;
 867
 868         while (timeout) {
 869                 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
 870                         break;
 871                 usleep_range(1000, 2000);
 872                 timeout--;
 873         }
 874         if (!timeout) {
 875                 e_dbg("MNG configuration cycle has not completed.\n");
 876                 return -E1000_ERR_RESET;
 877         }
 878
 879         return 0;
 880 }
 881
 882 /**
 883  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 884  *  @hw: pointer to the HW structure
 885  *  @active: true to enable LPLU, false to disable
 886  *
 887  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 888  *  this function also disables smart speed and vice versa.  LPLU will not be
 889  *  activated unless the device autonegotiation advertisement meets standards
 890  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 891  *  pointer entry point only called by PHY setup routines.
 892  **/
 893 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 894 {
 895         struct e1000_phy_info *phy = &hw->phy;
 896         s32 ret_val;
 897         u16 data;
 898
 899         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 900         if (ret_val)
 901                 return ret_val;
 902
 903         if (active) {
 904                 data |= IGP02E1000_PM_D0_LPLU;
 905                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 906                 if (ret_val)
 907                         return ret_val;
 908
 909                 /* When LPLU is enabled, we should disable SmartSpeed */
 910                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 911                 if (ret_val)
 912                         return ret_val;
 913                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 914                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 915                 if (ret_val)
 916                         return ret_val;
 917         } else {
 918                 data &= ~IGP02E1000_PM_D0_LPLU;
 919                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 920                 if (ret_val)
 921                         return ret_val;
 922                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 923                  * during Dx states where the power conservation is most
 924                  * important.  During driver activity we should enable
 925                  * SmartSpeed, so performance is maintained.
 926                  */
 927                 if (phy->smart_speed == e1000_smart_speed_on) {
 928                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 929                                            &data);
 930                         if (ret_val)
 931                                 return ret_val;
 932
 933                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 934                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 935                                            data);
 936                         if (ret_val)
 937                                 return ret_val;
 938                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 939                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 940                                            &data);
 941                         if (ret_val)
 942                                 return ret_val;
 943
 944                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 945                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 946                                            data);
 947                         if (ret_val)
 948                                 return ret_val;
 949                 }
 950         }
 951
 952         return 0;
 953 }
 954
 955 /**
 956  *  e1000_reset_hw_82571 - Reset hardware
 957  *  @hw: pointer to the HW structure
 958  *
 959  *  This resets the hardware into a known state.
 960  **/
 961 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 962 {
 963         u32 ctrl, ctrl_ext, eecd, tctl;
 964         s32 ret_val;
 965
 966         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 967          * on the last TLP read/write transaction when MAC is reset.
 968          */
 969         ret_val = e1000e_disable_pcie_master(hw);
 970         if (ret_val)
 971                 e_dbg("PCI-E Master disable polling has failed.\n");
 972
 973         e_dbg("Masking off all interrupts\n");
 974         ew32(IMC, 0xffffffff);
 975
 976         ew32(RCTL, 0);
 977         tctl = er32(TCTL);
 978         tctl &= ~E1000_TCTL_EN;
 979         ew32(TCTL, tctl);
 980         e1e_flush();
 981
 982         usleep_range(10000, 20000);
 983
 984         /* Must acquire the MDIO ownership before MAC reset.
 985          * Ownership defaults to firmware after a reset.
 986          */
 987         switch (hw->mac.type) {
 988         case e1000_82573:
 989                 ret_val = e1000_get_hw_semaphore_82573(hw);
 990                 break;
 991         case e1000_82574:
 992         case e1000_82583:
 993                 ret_val = e1000_get_hw_semaphore_82574(hw);
 994                 break;
 995         default:
 996                 break;
 997         }
 998
 999         ctrl = er32(CTRL);
1000
1001         e_dbg("Issuing a global reset to MAC\n");
1002         ew32(CTRL, ctrl | E1000_CTRL_RST);
1003
1004         /* Must release MDIO ownership and mutex after MAC reset. */
1005         switch (hw->mac.type) {
1006         case e1000_82573:
1007                 /* Release mutex only if the hw semaphore is acquired */
1008                 if (!ret_val)
1009                         e1000_put_hw_semaphore_82573(hw);
1010                 break;
1011         case e1000_82574:
1012         case e1000_82583:
1013                 /* Release mutex only if the hw semaphore is acquired */
1014                 if (!ret_val)
1015                         e1000_put_hw_semaphore_82574(hw);
1016                 break;
1017         default:
1018                 break;
1019         }
1020
1021         if (hw->nvm.type == e1000_nvm_flash_hw) {
1022                 usleep_range(10, 20);
1023                 ctrl_ext = er32(CTRL_EXT);
1024                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1025                 ew32(CTRL_EXT, ctrl_ext);
1026                 e1e_flush();
1027         }
1028
1029         ret_val = e1000e_get_auto_rd_done(hw);
1030         if (ret_val)
1031                 /* We don't want to continue accessing MAC registers. */
1032                 return ret_val;
1033
1034         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1035          * Need to wait for Phy configuration completion before accessing
1036          * NVM and Phy.
1037          */
1038
1039         switch (hw->mac.type) {
1040         case e1000_82571:
1041         case e1000_82572:
1042                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1043                  * to access the EEPROM.
1044                  */
1045                 eecd = er32(EECD);
1046                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1047                 ew32(EECD, eecd);
1048                 break;
1049         case e1000_82573:
1050         case e1000_82574:
1051         case e1000_82583:
1052                 msleep(25);
1053                 break;
1054         default:
1055                 break;
1056         }
1057
1058         /* Clear any pending interrupt events. */
1059         ew32(IMC, 0xffffffff);
1060         er32(ICR);
1061
1062         if (hw->mac.type == e1000_82571) {
1063                 /* Install any alternate MAC address into RAR0 */
1064                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1065                 if (ret_val)
1066                         return ret_val;
1067
1068                 e1000e_set_laa_state_82571(hw, true);
1069         }
1070
1071         /* Reinitialize the 82571 serdes link state machine */
1072         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1073                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1074
1075         return 0;
1076 }
1077
1078 /**
1079  *  e1000_init_hw_82571 - Initialize hardware
1080  *  @hw: pointer to the HW structure
1081  *
1082  *  This inits the hardware readying it for operation.
1083  **/
1084 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1085 {
1086         struct e1000_mac_info *mac = &hw->mac;
1087         u32 reg_data;
1088         s32 ret_val;
1089         u16 i, rar_count = mac->rar_entry_count;
1090
1091         e1000_initialize_hw_bits_82571(hw);
1092
1093         /* Initialize identification LED */
1094         ret_val = mac->ops.id_led_init(hw);
1095         /* An error is not fatal and we should not stop init due to this */
1096         if (ret_val)
1097                 e_dbg("Error initializing identification LED\n");
1098
1099         /* Disabling VLAN filtering */
1100         e_dbg("Initializing the IEEE VLAN\n");
1101         mac->ops.clear_vfta(hw);
1102
1103         /* Setup the receive address.
1104          * If, however, a locally administered address was assigned to the
1105          * 82571, we must reserve a RAR for it to work around an issue where
1106          * resetting one port will reload the MAC on the other port.
1107          */
1108         if (e1000e_get_laa_state_82571(hw))
1109                 rar_count--;
1110         e1000e_init_rx_addrs(hw, rar_count);
1111
1112         /* Zero out the Multicast HASH table */
1113         e_dbg("Zeroing the MTA\n");
1114         for (i = 0; i < mac->mta_reg_count; i++)
1115                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1116
1117         /* Setup link and flow control */
1118         ret_val = mac->ops.setup_link(hw);
1119
1120         /* Set the transmit descriptor write-back policy */
1121         reg_data = er32(TXDCTL(0));
1122         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1123                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1124         ew32(TXDCTL(0), reg_data);
1125
1126         /* ...for both queues. */
1127         switch (mac->type) {
1128         case e1000_82573:
1129                 e1000e_enable_tx_pkt_filtering(hw);
1130                 /* fall through */
1131         case e1000_82574:
1132         case e1000_82583:
1133                 reg_data = er32(GCR);
1134                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1135                 ew32(GCR, reg_data);
1136                 break;
1137         default:
1138                 reg_data = er32(TXDCTL(1));
1139                 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1140                             E1000_TXDCTL_FULL_TX_DESC_WB |
1141                             E1000_TXDCTL_COUNT_DESC);
1142                 ew32(TXDCTL(1), reg_data);
1143                 break;
1144         }
1145
1146         /* Clear all of the statistics registers (clear on read).  It is
1147          * important that we do this after we have tried to establish link
1148          * because the symbol error count will increment wildly if there
1149          * is no link.
1150          */
1151         e1000_clear_hw_cntrs_82571(hw);
1152
1153         return ret_val;
1154 }
1155
1156 /**
1157  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1158  *  @hw: pointer to the HW structure
1159  *
1160  *  Initializes required hardware-dependent bits needed for normal operation.
1161  **/
1162 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1163 {
1164         u32 reg;
1165
1166         /* Transmit Descriptor Control 0 */
1167         reg = er32(TXDCTL(0));
1168         reg |= BIT(22);
1169         ew32(TXDCTL(0), reg);
1170
1171         /* Transmit Descriptor Control 1 */
1172         reg = er32(TXDCTL(1));
1173         reg |= BIT(22);
1174         ew32(TXDCTL(1), reg);
1175
1176         /* Transmit Arbitration Control 0 */
1177         reg = er32(TARC(0));
1178         reg &= ~(0xF << 27);    /* 30:27 */
1179         switch (hw->mac.type) {
1180         case e1000_82571:
1181         case e1000_82572:
1182                 reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);
1183                 break;
1184         case e1000_82574:
1185         case e1000_82583:
1186                 reg |= BIT(26);
1187                 break;
1188         default:
1189                 break;
1190         }
1191         ew32(TARC(0), reg);
1192
1193         /* Transmit Arbitration Control 1 */
1194         reg = er32(TARC(1));
1195         switch (hw->mac.type) {
1196         case e1000_82571:
1197         case e1000_82572:
1198                 reg &= ~(BIT(29) | BIT(30));
1199                 reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);
1200                 if (er32(TCTL) & E1000_TCTL_MULR)
1201                         reg &= ~BIT(28);
1202                 else
1203                         reg |= BIT(28);
1204                 ew32(TARC(1), reg);
1205                 break;
1206         default:
1207                 break;
1208         }
1209
1210         /* Device Control */
1211         switch (hw->mac.type) {
1212         case e1000_82573:
1213         case e1000_82574:
1214         case e1000_82583:
1215                 reg = er32(CTRL);
1216                 reg &= ~BIT(29);
1217                 ew32(CTRL, reg);
1218                 break;
1219         default:
1220                 break;
1221         }
1222
1223         /* Extended Device Control */
1224         switch (hw->mac.type) {
1225         case e1000_82573:
1226         case e1000_82574:
1227         case e1000_82583:
1228                 reg = er32(CTRL_EXT);
1229                 reg &= ~BIT(23);
1230                 reg |= BIT(22);
1231                 ew32(CTRL_EXT, reg);
1232                 break;
1233         default:
1234                 break;
1235         }
1236
1237         if (hw->mac.type == e1000_82571) {
1238                 reg = er32(PBA_ECC);
1239                 reg |= E1000_PBA_ECC_CORR_EN;
1240                 ew32(PBA_ECC, reg);
1241         }
1242
1243         /* Workaround for hardware errata.
1244          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1245          */
1246         if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1247                 reg = er32(CTRL_EXT);
1248                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1249                 ew32(CTRL_EXT, reg);
1250         }
1251
1252         /* Disable IPv6 extension header parsing because some malformed
1253          * IPv6 headers can hang the Rx.
1254          */
1255         if (hw->mac.type <= e1000_82573) {
1256                 reg = er32(RFCTL);
1257                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1258                 ew32(RFCTL, reg);
1259         }
1260
1261         /* PCI-Ex Control Registers */
1262         switch (hw->mac.type) {
1263         case e1000_82574:
1264         case e1000_82583:
1265                 reg = er32(GCR);
1266                 reg |= BIT(22);
1267                 ew32(GCR, reg);
1268
1269                 /* Workaround for hardware errata.
1270                  * apply workaround for hardware errata documented in errata
1271                  * docs Fixes issue where some error prone or unreliable PCIe
1272                  * completions are occurring, particularly with ASPM enabled.
1273                  * Without fix, issue can cause Tx timeouts.
1274                  */
1275                 reg = er32(GCR2);
1276                 reg |= 1;
1277                 ew32(GCR2, reg);
1278                 break;
1279         default:
1280                 break;
1281         }
1282 }
1283
1284 /**
1285  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1286  *  @hw: pointer to the HW structure
1287  *
1288  *  Clears the register array which contains the VLAN filter table by
1289  *  setting all the values to 0.
1290  **/
1291 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1292 {
1293         u32 offset;
1294         u32 vfta_value = 0;
1295         u32 vfta_offset = 0;
1296         u32 vfta_bit_in_reg = 0;
1297
1298         switch (hw->mac.type) {
1299         case e1000_82573:
1300         case e1000_82574:
1301         case e1000_82583:
1302                 if (hw->mng_cookie.vlan_id != 0) {
1303                         /* The VFTA is a 4096b bit-field, each identifying
1304                          * a single VLAN ID.  The following operations
1305                          * determine which 32b entry (i.e. offset) into the
1306                          * array we want to set the VLAN ID (i.e. bit) of
1307                          * the manageability unit.
1308                          */
1309                         vfta_offset = (hw->mng_cookie.vlan_id >>
1310                                        E1000_VFTA_ENTRY_SHIFT) &
1311                             E1000_VFTA_ENTRY_MASK;
1312                         vfta_bit_in_reg =
1313                             BIT(hw->mng_cookie.vlan_id &
1314                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1315                 }
1316                 break;
1317         default:
1318                 break;
1319         }
1320         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1321                 /* If the offset we want to clear is the same offset of the
1322                  * manageability VLAN ID, then clear all bits except that of
1323                  * the manageability unit.
1324                  */
1325                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1326                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1327                 e1e_flush();
1328         }
1329 }
1330
1331 /**
1332  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1333  *  @hw: pointer to the HW structure
1334  *
1335  *  Reads the NVM Initialization Control Word 2 and returns true
1336  *  (>0) if any manageability is enabled, else false (0).
1337  **/
1338 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1339 {
1340         u16 data;
1341
1342         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1343         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1344 }
1345
1346 /**
1347  *  e1000_led_on_82574 - Turn LED on
1348  *  @hw: pointer to the HW structure
1349  *
1350  *  Turn LED on.
1351  **/
1352 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1353 {
1354         u32 ctrl;
1355         u32 i;
1356
1357         ctrl = hw->mac.ledctl_mode2;
1358         if (!(E1000_STATUS_LU & er32(STATUS))) {
1359                 /* If no link, then turn LED on by setting the invert bit
1360                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1361                  */
1362                 for (i = 0; i < 4; i++)
1363                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1364                             E1000_LEDCTL_MODE_LED_ON)
1365                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1366         }
1367         ew32(LEDCTL, ctrl);
1368
1369         return 0;
1370 }
1371
1372 /**
1373  *  e1000_check_phy_82574 - check 82574 phy hung state
1374  *  @hw: pointer to the HW structure
1375  *
1376  *  Returns whether phy is hung or not
1377  **/
1378 bool e1000_check_phy_82574(struct e1000_hw *hw)
1379 {
1380         u16 status_1kbt = 0;
1381         u16 receive_errors = 0;
1382         s32 ret_val;
1383
1384         /* Read PHY Receive Error counter first, if its is max - all F's then
1385          * read the Base1000T status register If both are max then PHY is hung.
1386          */
1387         ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1388         if (ret_val)
1389                 return false;
1390         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1391                 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1392                 if (ret_val)
1393                         return false;
1394                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1395                     E1000_IDLE_ERROR_COUNT_MASK)
1396                         return true;
1397         }
1398
1399         return false;
1400 }
1401
1402 /**
1403  *  e1000_setup_link_82571 - Setup flow control and link settings
1404  *  @hw: pointer to the HW structure
1405  *
1406  *  Determines which flow control settings to use, then configures flow
1407  *  control.  Calls the appropriate media-specific link configuration
1408  *  function.  Assuming the adapter has a valid link partner, a valid link
1409  *  should be established.  Assumes the hardware has previously been reset
1410  *  and the transmitter and receiver are not enabled.
1411  **/
1412 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1413 {
1414         /* 82573 does not have a word in the NVM to determine
1415          * the default flow control setting, so we explicitly
1416          * set it to full.
1417          */
1418         switch (hw->mac.type) {
1419         case e1000_82573:
1420         case e1000_82574:
1421         case e1000_82583:
1422                 if (hw->fc.requested_mode == e1000_fc_default)
1423                         hw->fc.requested_mode = e1000_fc_full;
1424                 break;
1425         default:
1426                 break;
1427         }
1428
1429         return e1000e_setup_link_generic(hw);
1430 }
1431
1432 /**
1433  *  e1000_setup_copper_link_82571 - Configure copper link settings
1434  *  @hw: pointer to the HW structure
1435  *
1436  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1437  *  for link, once link is established calls to configure collision distance
1438  *  and flow control are called.
1439  **/
1440 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1441 {
1442         u32 ctrl;
1443         s32 ret_val;
1444
1445         ctrl = er32(CTRL);
1446         ctrl |= E1000_CTRL_SLU;
1447         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1448         ew32(CTRL, ctrl);
1449
1450         switch (hw->phy.type) {
1451         case e1000_phy_m88:
1452         case e1000_phy_bm:
1453                 ret_val = e1000e_copper_link_setup_m88(hw);
1454                 break;
1455         case e1000_phy_igp_2:
1456                 ret_val = e1000e_copper_link_setup_igp(hw);
1457                 break;
1458         default:
1459                 return -E1000_ERR_PHY;
1460         }
1461
1462         if (ret_val)
1463                 return ret_val;
1464
1465         return e1000e_setup_copper_link(hw);
1466 }
1467
1468 /**
1469  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1470  *  @hw: pointer to the HW structure
1471  *
1472  *  Configures collision distance and flow control for fiber and serdes links.
1473  *  Upon successful setup, poll for link.
1474  **/
1475 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1476 {
1477         switch (hw->mac.type) {
1478         case e1000_82571:
1479         case e1000_82572:
1480                 /* If SerDes loopback mode is entered, there is no form
1481                  * of reset to take the adapter out of that mode.  So we
1482                  * have to explicitly take the adapter out of loopback
1483                  * mode.  This prevents drivers from twiddling their thumbs
1484                  * if another tool failed to take it out of loopback mode.
1485                  */
1486                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1487                 break;
1488         default:
1489                 break;
1490         }
1491
1492         return e1000e_setup_fiber_serdes_link(hw);
1493 }
1494
1495 /**
1496  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1497  *  @hw: pointer to the HW structure
1498  *
1499  *  Reports the link state as up or down.
1500  *
1501  *  If autonegotiation is supported by the link partner, the link state is
1502  *  determined by the result of autonegotiation. This is the most likely case.
1503  *  If autonegotiation is not supported by the link partner, and the link
1504  *  has a valid signal, force the link up.
1505  *
1506  *  The link state is represented internally here by 4 states:
1507  *
1508  *  1) down
1509  *  2) autoneg_progress
1510  *  3) autoneg_complete (the link successfully autonegotiated)
1511  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1512  *
1513  **/
1514 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1515 {
1516         struct e1000_mac_info *mac = &hw->mac;
1517         u32 rxcw;
1518         u32 ctrl;
1519         u32 status;
1520         u32 txcw;
1521         u32 i;
1522         s32 ret_val = 0;
1523
1524         ctrl = er32(CTRL);
1525         status = er32(STATUS);
1526         er32(RXCW);
1527         /* SYNCH bit and IV bit are sticky */
1528         usleep_range(10, 20);
1529         rxcw = er32(RXCW);
1530
1531         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1532                 /* Receiver is synchronized with no invalid bits.  */
1533                 switch (mac->serdes_link_state) {
1534                 case e1000_serdes_link_autoneg_complete:
1535                         if (!(status & E1000_STATUS_LU)) {
1536                                 /* We have lost link, retry autoneg before
1537                                  * reporting link failure
1538                                  */
1539                                 mac->serdes_link_state =
1540                                     e1000_serdes_link_autoneg_progress;
1541                                 mac->serdes_has_link = false;
1542                                 e_dbg("AN_UP     -> AN_PROG\n");
1543                         } else {
1544                                 mac->serdes_has_link = true;
1545                         }
1546                         break;
1547
1548                 case e1000_serdes_link_forced_up:
1549                         /* If we are receiving /C/ ordered sets, re-enable
1550                          * auto-negotiation in the TXCW register and disable
1551                          * forced link in the Device Control register in an
1552                          * attempt to auto-negotiate with our link partner.
1553                          */
1554                         if (rxcw & E1000_RXCW_C) {
1555                                 /* Enable autoneg, and unforce link up */
1556                                 ew32(TXCW, mac->txcw);
1557                                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1558                                 mac->serdes_link_state =
1559                                     e1000_serdes_link_autoneg_progress;
1560                                 mac->serdes_has_link = false;
1561                                 e_dbg("FORCED_UP -> AN_PROG\n");
1562                         } else {
1563                                 mac->serdes_has_link = true;
1564                         }
1565                         break;
1566
1567                 case e1000_serdes_link_autoneg_progress:
1568                         if (rxcw & E1000_RXCW_C) {
1569                                 /* We received /C/ ordered sets, meaning the
1570                                  * link partner has autonegotiated, and we can
1571                                  * trust the Link Up (LU) status bit.
1572                                  */
1573                                 if (status & E1000_STATUS_LU) {
1574                                         mac->serdes_link_state =
1575                                             e1000_serdes_link_autoneg_complete;
1576                                         e_dbg("AN_PROG   -> AN_UP\n");
1577                                         mac->serdes_has_link = true;
1578                                 } else {
1579                                         /* Autoneg completed, but failed. */
1580                                         mac->serdes_link_state =
1581                                             e1000_serdes_link_down;
1582                                         e_dbg("AN_PROG   -> DOWN\n");
1583                                 }
1584                         } else {
1585                                 /* The link partner did not autoneg.
1586                                  * Force link up and full duplex, and change
1587                                  * state to forced.
1588                                  */
1589                                 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1590                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1591                                 ew32(CTRL, ctrl);
1592
1593                                 /* Configure Flow Control after link up. */
1594                                 ret_val = e1000e_config_fc_after_link_up(hw);
1595                                 if (ret_val) {
1596                                         e_dbg("Error config flow control\n");
1597                                         break;
1598                                 }
1599                                 mac->serdes_link_state =
1600                                     e1000_serdes_link_forced_up;
1601                                 mac->serdes_has_link = true;
1602                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1603                         }
1604                         break;
1605
1606                 case e1000_serdes_link_down:
1607                 default:
1608                         /* The link was down but the receiver has now gained
1609                          * valid sync, so lets see if we can bring the link
1610                          * up.
1611                          */
1612                         ew32(TXCW, mac->txcw);
1613                         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1614                         mac->serdes_link_state =
1615                             e1000_serdes_link_autoneg_progress;
1616                         mac->serdes_has_link = false;
1617                         e_dbg("DOWN      -> AN_PROG\n");
1618                         break;
1619                 }
1620         } else {
1621                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1622                         mac->serdes_has_link = false;
1623                         mac->serdes_link_state = e1000_serdes_link_down;
1624                         e_dbg("ANYSTATE  -> DOWN\n");
1625                 } else {
1626                         /* Check several times, if SYNCH bit and CONFIG
1627                          * bit both are consistently 1 then simply ignore
1628                          * the IV bit and restart Autoneg
1629                          */
1630                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1631                                 usleep_range(10, 20);
1632                                 rxcw = er32(RXCW);
1633                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1634                                     (rxcw & E1000_RXCW_C))
1635                                         continue;
1636
1637                                 if (rxcw & E1000_RXCW_IV) {
1638                                         mac->serdes_has_link = false;
1639                                         mac->serdes_link_state =
1640                                             e1000_serdes_link_down;
1641                                         e_dbg("ANYSTATE  -> DOWN\n");
1642                                         break;
1643                                 }
1644                         }
1645
1646                         if (i == AN_RETRY_COUNT) {
1647                                 txcw = er32(TXCW);
1648                                 txcw |= E1000_TXCW_ANE;
1649                                 ew32(TXCW, txcw);
1650                                 mac->serdes_link_state =
1651                                     e1000_serdes_link_autoneg_progress;
1652                                 mac->serdes_has_link = false;
1653                                 e_dbg("ANYSTATE  -> AN_PROG\n");
1654                         }
1655                 }
1656         }
1657
1658         return ret_val;
1659 }
1660
1661 /**
1662  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1663  *  @hw: pointer to the HW structure
1664  *  @data: pointer to the NVM (EEPROM)
1665  *
1666  *  Read the EEPROM for the current default LED configuration.  If the
1667  *  LED configuration is not valid, set to a valid LED configuration.
1668  **/
1669 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1670 {
1671         s32 ret_val;
1672
1673         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1674         if (ret_val) {
1675                 e_dbg("NVM Read Error\n");
1676                 return ret_val;
1677         }
1678
1679         switch (hw->mac.type) {
1680         case e1000_82573:
1681         case e1000_82574:
1682         case e1000_82583:
1683                 if (*data == ID_LED_RESERVED_F746)
1684                         *data = ID_LED_DEFAULT_82573;
1685                 break;
1686         default:
1687                 if (*data == ID_LED_RESERVED_0000 ||
1688                     *data == ID_LED_RESERVED_FFFF)
1689                         *data = ID_LED_DEFAULT;
1690                 break;
1691         }
1692
1693         return 0;
1694 }
1695
1696 /**
1697  *  e1000e_get_laa_state_82571 - Get locally administered address state
1698  *  @hw: pointer to the HW structure
1699  *
1700  *  Retrieve and return the current locally administered address state.
1701  **/
1702 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1703 {
1704         if (hw->mac.type != e1000_82571)
1705                 return false;
1706
1707         return hw->dev_spec.e82571.laa_is_present;
1708 }
1709
1710 /**
1711  *  e1000e_set_laa_state_82571 - Set locally administered address state
1712  *  @hw: pointer to the HW structure
1713  *  @state: enable/disable locally administered address
1714  *
1715  *  Enable/Disable the current locally administered address state.
1716  **/
1717 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1718 {
1719         if (hw->mac.type != e1000_82571)
1720                 return;
1721
1722         hw->dev_spec.e82571.laa_is_present = state;
1723
1724         /* If workaround is activated... */
1725         if (state)
1726                 /* Hold a copy of the LAA in RAR[14] This is done so that
1727                  * between the time RAR[0] gets clobbered and the time it
1728                  * gets fixed, the actual LAA is in one of the RARs and no
1729                  * incoming packets directed to this port are dropped.
1730                  * Eventually the LAA will be in RAR[0] and RAR[14].
1731                  */
1732                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1733                                     hw->mac.rar_entry_count - 1);
1734 }
1735
1736 /**
1737  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1738  *  @hw: pointer to the HW structure
1739  *
1740  *  Verifies that the EEPROM has completed the update.  After updating the
1741  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1742  *  the checksum fix is not implemented, we need to set the bit and update
1743  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1744  *  we need to return bad checksum.
1745  **/
1746 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1747 {
1748         struct e1000_nvm_info *nvm = &hw->nvm;
1749         s32 ret_val;
1750         u16 data;
1751
1752         if (nvm->type != e1000_nvm_flash_hw)
1753                 return 0;
1754
1755         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1756          * 10h-12h.  Checksum may need to be fixed.
1757          */
1758         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1759         if (ret_val)
1760                 return ret_val;
1761
1762         if (!(data & 0x10)) {
1763                 /* Read 0x23 and check bit 15.  This bit is a 1
1764                  * when the checksum has already been fixed.  If
1765                  * the checksum is still wrong and this bit is a
1766                  * 1, we need to return bad checksum.  Otherwise,
1767                  * we need to set this bit to a 1 and update the
1768                  * checksum.
1769                  */
1770                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1771                 if (ret_val)
1772                         return ret_val;
1773
1774                 if (!(data & 0x8000)) {
1775                         data |= 0x8000;
1776                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1777                         if (ret_val)
1778                                 return ret_val;
1779                         ret_val = e1000e_update_nvm_checksum(hw);
1780                         if (ret_val)
1781                                 return ret_val;
1782                 }
1783         }
1784
1785         return 0;
1786 }
1787
1788 /**
1789  *  e1000_read_mac_addr_82571 - Read device MAC address
1790  *  @hw: pointer to the HW structure
1791  **/
1792 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1793 {
1794         if (hw->mac.type == e1000_82571) {
1795                 s32 ret_val;
1796
1797                 /* If there's an alternate MAC address place it in RAR0
1798                  * so that it will override the Si installed default perm
1799                  * address.
1800                  */
1801                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1802                 if (ret_val)
1803                         return ret_val;
1804         }
1805
1806         return e1000_read_mac_addr_generic(hw);
1807 }
1808
1809 /**
1810  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1811  * @hw: pointer to the HW structure
1812  *
1813  * In the case of a PHY power down to save power, or to turn off link during a
1814  * driver unload, or wake on lan is not enabled, remove the link.
1815  **/
1816 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1817 {
1818         struct e1000_phy_info *phy = &hw->phy;
1819         struct e1000_mac_info *mac = &hw->mac;
1820
1821         if (!phy->ops.check_reset_block)
1822                 return;
1823
1824         /* If the management interface is not enabled, then power down */
1825         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1826                 e1000_power_down_phy_copper(hw);
1827 }
1828
1829 /**
1830  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1831  *  @hw: pointer to the HW structure
1832  *
1833  *  Clears the hardware counters by reading the counter registers.
1834  **/
1835 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1836 {
1837         e1000e_clear_hw_cntrs_base(hw);
1838
1839         er32(PRC64);
1840         er32(PRC127);
1841         er32(PRC255);
1842         er32(PRC511);
1843         er32(PRC1023);
1844         er32(PRC1522);
1845         er32(PTC64);
1846         er32(PTC127);
1847         er32(PTC255);
1848         er32(PTC511);
1849         er32(PTC1023);
1850         er32(PTC1522);
1851
1852         er32(ALGNERRC);
1853         er32(RXERRC);
1854         er32(TNCRS);
1855         er32(CEXTERR);
1856         er32(TSCTC);
1857         er32(TSCTFC);
1858
1859         er32(MGTPRC);
1860         er32(MGTPDC);
1861         er32(MGTPTC);
1862
1863         er32(IAC);
1864         er32(ICRXOC);
1865
1866         er32(ICRXPTC);
1867         er32(ICRXATC);
1868         er32(ICTXPTC);
1869         er32(ICTXATC);
1870         er32(ICTXQEC);
1871         er32(ICTXQMTC);
1872         er32(ICRXDMTC);
1873 }
1874
1875 static const struct e1000_mac_operations e82571_mac_ops = {
1876         /* .check_mng_mode: mac type dependent */
1877         /* .check_for_link: media type dependent */
1878         .id_led_init            = e1000e_id_led_init_generic,
1879         .cleanup_led            = e1000e_cleanup_led_generic,
1880         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1881         .get_bus_info           = e1000e_get_bus_info_pcie,
1882         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1883         /* .get_link_up_info: media type dependent */
1884         /* .led_on: mac type dependent */
1885         .led_off                = e1000e_led_off_generic,
1886         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1887         .write_vfta             = e1000_write_vfta_generic,
1888         .clear_vfta             = e1000_clear_vfta_82571,
1889         .reset_hw               = e1000_reset_hw_82571,
1890         .init_hw                = e1000_init_hw_82571,
1891         .setup_link             = e1000_setup_link_82571,
1892         /* .setup_physical_interface: media type dependent */
1893         .setup_led              = e1000e_setup_led_generic,
1894         .config_collision_dist  = e1000e_config_collision_dist_generic,
1895         .read_mac_addr          = e1000_read_mac_addr_82571,
1896         .rar_set                = e1000e_rar_set_generic,
1897         .rar_get_count          = e1000e_rar_get_count_generic,
1898 };
1899
1900 static const struct e1000_phy_operations e82_phy_ops_igp = {
1901         .acquire                = e1000_get_hw_semaphore_82571,
1902         .check_polarity         = e1000_check_polarity_igp,
1903         .check_reset_block      = e1000e_check_reset_block_generic,
1904         .commit                 = NULL,
1905         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1906         .get_cfg_done           = e1000_get_cfg_done_82571,
1907         .get_cable_length       = e1000e_get_cable_length_igp_2,
1908         .get_info               = e1000e_get_phy_info_igp,
1909         .read_reg               = e1000e_read_phy_reg_igp,
1910         .release                = e1000_put_hw_semaphore_82571,
1911         .reset                  = e1000e_phy_hw_reset_generic,
1912         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1913         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1914         .write_reg              = e1000e_write_phy_reg_igp,
1915         .cfg_on_link_up         = NULL,
1916 };
1917
1918 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1919         .acquire                = e1000_get_hw_semaphore_82571,
1920         .check_polarity         = e1000_check_polarity_m88,
1921         .check_reset_block      = e1000e_check_reset_block_generic,
1922         .commit                 = e1000e_phy_sw_reset,
1923         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1924         .get_cfg_done           = e1000e_get_cfg_done_generic,
1925         .get_cable_length       = e1000e_get_cable_length_m88,
1926         .get_info               = e1000e_get_phy_info_m88,
1927         .read_reg               = e1000e_read_phy_reg_m88,
1928         .release                = e1000_put_hw_semaphore_82571,
1929         .reset                  = e1000e_phy_hw_reset_generic,
1930         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1931         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1932         .write_reg              = e1000e_write_phy_reg_m88,
1933         .cfg_on_link_up         = NULL,
1934 };
1935
1936 static const struct e1000_phy_operations e82_phy_ops_bm = {
1937         .acquire                = e1000_get_hw_semaphore_82571,
1938         .check_polarity         = e1000_check_polarity_m88,
1939         .check_reset_block      = e1000e_check_reset_block_generic,
1940         .commit                 = e1000e_phy_sw_reset,
1941         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1942         .get_cfg_done           = e1000e_get_cfg_done_generic,
1943         .get_cable_length       = e1000e_get_cable_length_m88,
1944         .get_info               = e1000e_get_phy_info_m88,
1945         .read_reg               = e1000e_read_phy_reg_bm2,
1946         .release                = e1000_put_hw_semaphore_82571,
1947         .reset                  = e1000e_phy_hw_reset_generic,
1948         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1949         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1950         .write_reg              = e1000e_write_phy_reg_bm2,
1951         .cfg_on_link_up         = NULL,
1952 };
1953
1954 static const struct e1000_nvm_operations e82571_nvm_ops = {
1955         .acquire                = e1000_acquire_nvm_82571,
1956         .read                   = e1000e_read_nvm_eerd,
1957         .release                = e1000_release_nvm_82571,
1958         .reload                 = e1000e_reload_nvm_generic,
1959         .update                 = e1000_update_nvm_checksum_82571,
1960         .valid_led_default      = e1000_valid_led_default_82571,
1961         .validate               = e1000_validate_nvm_checksum_82571,
1962         .write                  = e1000_write_nvm_82571,
1963 };
1964
1965 const struct e1000_info e1000_82571_info = {
1966         .mac                    = e1000_82571,
1967         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1968                                   | FLAG_HAS_JUMBO_FRAMES
1969                                   | FLAG_HAS_WOL
1970                                   | FLAG_APME_IN_CTRL3
1971                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1972                                   | FLAG_HAS_SMART_POWER_DOWN
1973                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1974                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1975                                   | FLAG_APME_CHECK_PORT_B,
1976         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1977                                   | FLAG2_DMA_BURST,
1978         .pba                    = 38,
1979         .max_hw_frame_size      = DEFAULT_JUMBO,
1980         .get_variants           = e1000_get_variants_82571,
1981         .mac_ops                = &e82571_mac_ops,
1982         .phy_ops                = &e82_phy_ops_igp,
1983         .nvm_ops                = &e82571_nvm_ops,
1984 };
1985
1986 const struct e1000_info e1000_82572_info = {
1987         .mac                    = e1000_82572,
1988         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1989                                   | FLAG_HAS_JUMBO_FRAMES
1990                                   | FLAG_HAS_WOL
1991                                   | FLAG_APME_IN_CTRL3
1992                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1993                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1994         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1995                                   | FLAG2_DMA_BURST,
1996         .pba                    = 38,
1997         .max_hw_frame_size      = DEFAULT_JUMBO,
1998         .get_variants           = e1000_get_variants_82571,
1999         .mac_ops                = &e82571_mac_ops,
2000         .phy_ops                = &e82_phy_ops_igp,
2001         .nvm_ops                = &e82571_nvm_ops,
2002 };
2003
2004 const struct e1000_info e1000_82573_info = {
2005         .mac                    = e1000_82573,
2006         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2007                                   | FLAG_HAS_WOL
2008                                   | FLAG_APME_IN_CTRL3
2009                                   | FLAG_HAS_SMART_POWER_DOWN
2010                                   | FLAG_HAS_AMT
2011                                   | FLAG_HAS_SWSM_ON_LOAD,
2012         .flags2                 = FLAG2_DISABLE_ASPM_L1
2013                                   | FLAG2_DISABLE_ASPM_L0S,
2014         .pba                    = 20,
2015         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
2016         .get_variants           = e1000_get_variants_82571,
2017         .mac_ops                = &e82571_mac_ops,
2018         .phy_ops                = &e82_phy_ops_m88,
2019         .nvm_ops                = &e82571_nvm_ops,
2020 };
2021
2022 const struct e1000_info e1000_82574_info = {
2023         .mac                    = e1000_82574,
2024         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2025                                   | FLAG_HAS_MSIX
2026                                   | FLAG_HAS_JUMBO_FRAMES
2027                                   | FLAG_HAS_WOL
2028                                   | FLAG_HAS_HW_TIMESTAMP
2029                                   | FLAG_APME_IN_CTRL3
2030                                   | FLAG_HAS_SMART_POWER_DOWN
2031                                   | FLAG_HAS_AMT
2032                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2033         .flags2                  = FLAG2_CHECK_PHY_HANG
2034                                   | FLAG2_DISABLE_ASPM_L0S
2035                                   | FLAG2_DISABLE_ASPM_L1
2036                                   | FLAG2_NO_DISABLE_RX
2037                                   | FLAG2_DMA_BURST
2038                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
2039         .pba                    = 32,
2040         .max_hw_frame_size      = DEFAULT_JUMBO,
2041         .get_variants           = e1000_get_variants_82571,
2042         .mac_ops                = &e82571_mac_ops,
2043         .phy_ops                = &e82_phy_ops_bm,
2044         .nvm_ops                = &e82571_nvm_ops,
2045 };
2046
2047 const struct e1000_info e1000_82583_info = {
2048         .mac                    = e1000_82583,
2049         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2050                                   | FLAG_HAS_WOL
2051                                   | FLAG_HAS_HW_TIMESTAMP
2052                                   | FLAG_APME_IN_CTRL3
2053                                   | FLAG_HAS_SMART_POWER_DOWN
2054                                   | FLAG_HAS_AMT
2055                                   | FLAG_HAS_JUMBO_FRAMES
2056                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2057         .flags2                 = FLAG2_DISABLE_ASPM_L0S
2058                                   | FLAG2_DISABLE_ASPM_L1
2059                                   | FLAG2_NO_DISABLE_RX
2060                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
2061         .pba                    = 32,
2062         .max_hw_frame_size      = DEFAULT_JUMBO,
2063         .get_variants           = e1000_get_variants_82571,
2064         .mac_ops                = &e82571_mac_ops,
2065         .phy_ops                = &e82_phy_ops_bm,
2066         .nvm_ops                = &e82571_nvm_ops,
2067 };