drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82562G 10/100 Network Connection
  23  * 82562G-2 10/100 Network Connection
  24  * 82562GT 10/100 Network Connection
  25  * 82562GT-2 10/100 Network Connection
  26  * 82562V 10/100 Network Connection
  27  * 82562V-2 10/100 Network Connection
  28  * 82566DC-2 Gigabit Network Connection
  29  * 82566DC Gigabit Network Connection
  30  * 82566DM-2 Gigabit Network Connection
  31  * 82566DM Gigabit Network Connection
  32  * 82566MC Gigabit Network Connection
  33  * 82566MM Gigabit Network Connection
  34  * 82567LM Gigabit Network Connection
  35  * 82567LF Gigabit Network Connection
  36  * 82567V Gigabit Network Connection
  37  * 82567LM-2 Gigabit Network Connection
  38  * 82567LF-2 Gigabit Network Connection
  39  * 82567V-2 Gigabit Network Connection
  40  * 82567LF-3 Gigabit Network Connection
  41  * 82567LM-3 Gigabit Network Connection
  42  * 82567LM-4 Gigabit Network Connection
  43  * 82577LM Gigabit Network Connection
  44  * 82577LC Gigabit Network Connection
  45  * 82578DM Gigabit Network Connection
  46  * 82578DC Gigabit Network Connection
  47  * 82579LM Gigabit Network Connection
  48  * 82579V Gigabit Network Connection
  49  * Ethernet Connection I217-LM
  50  * Ethernet Connection I217-V
  51  * Ethernet Connection I218-V
  52  * Ethernet Connection I218-LM
  53  * Ethernet Connection (2) I218-LM
  54  * Ethernet Connection (2) I218-V
  55  * Ethernet Connection (3) I218-LM
  56  * Ethernet Connection (3) I218-V
  57  */
  58
  59 #include "e1000.h"
  60
  61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  62 /* Offset 04h HSFSTS */
  63 union ich8_hws_flash_status {
  64         struct ich8_hsfsts {
  65                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  66                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  67                 u16 dael:1;     /* bit 2 Direct Access error Log */
  68                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  69                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  70                 u16 reserved1:2;        /* bit 13:6 Reserved */
  71                 u16 reserved2:6;        /* bit 13:6 Reserved */
  72                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  73                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  74         } hsf_status;
  75         u16 regval;
  76 };
  77
  78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  79 /* Offset 06h FLCTL */
  80 union ich8_hws_flash_ctrl {
  81         struct ich8_hsflctl {
  82                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  83                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  84                 u16 reserved:5; /* 7:3 Reserved  */
  85                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  86                 u16 flockdn:6;  /* 15:10 Reserved */
  87         } hsf_ctrl;
  88         u16 regval;
  89 };
  90
  91 /* ICH Flash Region Access Permissions */
  92 union ich8_hws_flash_regacc {
  93         struct ich8_flracc {
  94                 u32 grra:8;     /* 0:7 GbE region Read Access */
  95                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  96                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  97                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  98         } hsf_flregacc;
  99         u16 regval;
 100 };
 101
 102 /* ICH Flash Protected Region */
 103 union ich8_flash_protected_range {
 104         struct ich8_pr {
 105                 u32 base:13;    /* 0:12 Protected Range Base */
 106                 u32 reserved1:2;        /* 13:14 Reserved */
 107                 u32 rpe:1;      /* 15 Read Protection Enable */
 108                 u32 limit:13;   /* 16:28 Protected Range Limit */
 109                 u32 reserved2:2;        /* 29:30 Reserved */
 110                 u32 wpe:1;      /* 31 Write Protection Enable */
 111         } range;
 112         u32 regval;
 113 };
 114
 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 119                                                 u32 offset, u8 byte);
 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 121                                          u8 *data);
 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                          u16 *data);
 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 125                                          u8 size, u16 *data);
 126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                            u32 *data);
 128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u32 *data);
 130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 131                                             u32 offset, u32 data);
 132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 133                                                  u32 offset, u32 dword);
 134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 158
 159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 160 {
 161         return readw(hw->flash_address + reg);
 162 }
 163
 164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 165 {
 166         return readl(hw->flash_address + reg);
 167 }
 168
 169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 170 {
 171         writew(val, hw->flash_address + reg);
 172 }
 173
 174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 175 {
 176         writel(val, hw->flash_address + reg);
 177 }
 178
 179 #define er16flash(reg)          __er16flash(hw, (reg))
 180 #define er32flash(reg)          __er32flash(hw, (reg))
 181 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 182 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 183
 184 /**
 185  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 186  *  @hw: pointer to the HW structure
 187  *
 188  *  Test access to the PHY registers by reading the PHY ID registers.  If
 189  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 190  *  otherwise assume the read PHY ID is correct if it is valid.
 191  *
 192  *  Assumes the sw/fw/hw semaphore is already acquired.
 193  **/
 194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 195 {
 196         u16 phy_reg = 0;
 197         u32 phy_id = 0;
 198         s32 ret_val = 0;
 199         u16 retry_count;
 200         u32 mac_reg = 0;
 201
 202         for (retry_count = 0; retry_count < 2; retry_count++) {
 203                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 204                 if (ret_val || (phy_reg == 0xFFFF))
 205                         continue;
 206                 phy_id = (u32)(phy_reg << 16);
 207
 208                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 209                 if (ret_val || (phy_reg == 0xFFFF)) {
 210                         phy_id = 0;
 211                         continue;
 212                 }
 213                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 214                 break;
 215         }
 216
 217         if (hw->phy.id) {
 218                 if (hw->phy.id == phy_id)
 219                         goto out;
 220         } else if (phy_id) {
 221                 hw->phy.id = phy_id;
 222                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 223                 goto out;
 224         }
 225
 226         /* In case the PHY needs to be in mdio slow mode,
 227          * set slow mode and try to get the PHY id again.
 228          */
 229         if (hw->mac.type < e1000_pch_lpt) {
 230                 hw->phy.ops.release(hw);
 231                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 232                 if (!ret_val)
 233                         ret_val = e1000e_get_phy_id(hw);
 234                 hw->phy.ops.acquire(hw);
 235         }
 236
 237         if (ret_val)
 238                 return false;
 239 out:
 240         if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
 241                 /* Only unforce SMBus if ME is not active */
 242                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 243                         /* Unforce SMBus mode in PHY */
 244                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 245                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 246                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 247
 248                         /* Unforce SMBus mode in MAC */
 249                         mac_reg = er32(CTRL_EXT);
 250                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 251                         ew32(CTRL_EXT, mac_reg);
 252                 }
 253         }
 254
 255         return true;
 256 }
 257
 258 /**
 259  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 260  *  @hw: pointer to the HW structure
 261  *
 262  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 263  *  used to reset the PHY to a quiescent state when necessary.
 264  **/
 265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 266 {
 267         u32 mac_reg;
 268
 269         /* Set Phy Config Counter to 50msec */
 270         mac_reg = er32(FEXTNVM3);
 271         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 272         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 273         ew32(FEXTNVM3, mac_reg);
 274
 275         /* Toggle LANPHYPC Value bit */
 276         mac_reg = er32(CTRL);
 277         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 278         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 279         ew32(CTRL, mac_reg);
 280         e1e_flush();
 281         usleep_range(10, 20);
 282         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 283         ew32(CTRL, mac_reg);
 284         e1e_flush();
 285
 286         if (hw->mac.type < e1000_pch_lpt) {
 287                 msleep(50);
 288         } else {
 289                 u16 count = 20;
 290
 291                 do {
 292                         usleep_range(5000, 10000);
 293                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 294
 295                 msleep(30);
 296         }
 297 }
 298
 299 /**
 300  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Workarounds/flow necessary for PHY initialization during driver load
 304  *  and resume paths.
 305  **/
 306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 307 {
 308         struct e1000_adapter *adapter = hw->adapter;
 309         u32 mac_reg, fwsm = er32(FWSM);
 310         s32 ret_val;
 311
 312         /* Gate automatic PHY configuration by hardware on managed and
 313          * non-managed 82579 and newer adapters.
 314          */
 315         e1000_gate_hw_phy_config_ich8lan(hw, true);
 316
 317         /* It is not possible to be certain of the current state of ULP
 318          * so forcibly disable it.
 319          */
 320         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 321         e1000_disable_ulp_lpt_lp(hw, true);
 322
 323         ret_val = hw->phy.ops.acquire(hw);
 324         if (ret_val) {
 325                 e_dbg("Failed to initialize PHY flow\n");
 326                 goto out;
 327         }
 328
 329         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 330          * inaccessible and resetting the PHY is not blocked, toggle the
 331          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 332          */
 333         switch (hw->mac.type) {
 334         case e1000_pch_lpt:
 335         case e1000_pch_spt:
 336                 if (e1000_phy_is_accessible_pchlan(hw))
 337                         break;
 338
 339                 /* Before toggling LANPHYPC, see if PHY is accessible by
 340                  * forcing MAC to SMBus mode first.
 341                  */
 342                 mac_reg = er32(CTRL_EXT);
 343                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 344                 ew32(CTRL_EXT, mac_reg);
 345
 346                 /* Wait 50 milliseconds for MAC to finish any retries
 347                  * that it might be trying to perform from previous
 348                  * attempts to acknowledge any phy read requests.
 349                  */
 350                 msleep(50);
 351
 352                 /* fall-through */
 353         case e1000_pch2lan:
 354                 if (e1000_phy_is_accessible_pchlan(hw))
 355                         break;
 356
 357                 /* fall-through */
 358         case e1000_pchlan:
 359                 if ((hw->mac.type == e1000_pchlan) &&
 360                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 361                         break;
 362
 363                 if (hw->phy.ops.check_reset_block(hw)) {
 364                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 365                         ret_val = -E1000_ERR_PHY;
 366                         break;
 367                 }
 368
 369                 /* Toggle LANPHYPC Value bit */
 370                 e1000_toggle_lanphypc_pch_lpt(hw);
 371                 if (hw->mac.type >= e1000_pch_lpt) {
 372                         if (e1000_phy_is_accessible_pchlan(hw))
 373                                 break;
 374
 375                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 376                          * so ensure that the MAC is also out of SMBus mode
 377                          */
 378                         mac_reg = er32(CTRL_EXT);
 379                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 380                         ew32(CTRL_EXT, mac_reg);
 381
 382                         if (e1000_phy_is_accessible_pchlan(hw))
 383                                 break;
 384
 385                         ret_val = -E1000_ERR_PHY;
 386                 }
 387                 break;
 388         default:
 389                 break;
 390         }
 391
 392         hw->phy.ops.release(hw);
 393         if (!ret_val) {
 394
 395                 /* Check to see if able to reset PHY.  Print error if not */
 396                 if (hw->phy.ops.check_reset_block(hw)) {
 397                         e_err("Reset blocked by ME\n");
 398                         goto out;
 399                 }
 400
 401                 /* Reset the PHY before any access to it.  Doing so, ensures
 402                  * that the PHY is in a known good state before we read/write
 403                  * PHY registers.  The generic reset is sufficient here,
 404                  * because we haven't determined the PHY type yet.
 405                  */
 406                 ret_val = e1000e_phy_hw_reset_generic(hw);
 407                 if (ret_val)
 408                         goto out;
 409
 410                 /* On a successful reset, possibly need to wait for the PHY
 411                  * to quiesce to an accessible state before returning control
 412                  * to the calling function.  If the PHY does not quiesce, then
 413                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 414                  *  the PHY is in.
 415                  */
 416                 ret_val = hw->phy.ops.check_reset_block(hw);
 417                 if (ret_val)
 418                         e_err("ME blocked access to PHY after reset\n");
 419         }
 420
 421 out:
 422         /* Ungate automatic PHY configuration on non-managed 82579 */
 423         if ((hw->mac.type == e1000_pch2lan) &&
 424             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 425                 usleep_range(10000, 20000);
 426                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 427         }
 428
 429         return ret_val;
 430 }
 431
 432 /**
 433  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 434  *  @hw: pointer to the HW structure
 435  *
 436  *  Initialize family-specific PHY parameters and function pointers.
 437  **/
 438 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 439 {
 440         struct e1000_phy_info *phy = &hw->phy;
 441         s32 ret_val;
 442
 443         phy->addr = 1;
 444         phy->reset_delay_us = 100;
 445
 446         phy->ops.set_page = e1000_set_page_igp;
 447         phy->ops.read_reg = e1000_read_phy_reg_hv;
 448         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 449         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 450         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 451         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 452         phy->ops.write_reg = e1000_write_phy_reg_hv;
 453         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 454         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 455         phy->ops.power_up = e1000_power_up_phy_copper;
 456         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 457         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458
 459         phy->id = e1000_phy_unknown;
 460
 461         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 462         if (ret_val)
 463                 return ret_val;
 464
 465         if (phy->id == e1000_phy_unknown)
 466                 switch (hw->mac.type) {
 467                 default:
 468                         ret_val = e1000e_get_phy_id(hw);
 469                         if (ret_val)
 470                                 return ret_val;
 471                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 472                                 break;
 473                         /* fall-through */
 474                 case e1000_pch2lan:
 475                 case e1000_pch_lpt:
 476                 case e1000_pch_spt:
 477                         /* In case the PHY needs to be in mdio slow mode,
 478                          * set slow mode and try to get the PHY id again.
 479                          */
 480                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 481                         if (ret_val)
 482                                 return ret_val;
 483                         ret_val = e1000e_get_phy_id(hw);
 484                         if (ret_val)
 485                                 return ret_val;
 486                         break;
 487                 }
 488         phy->type = e1000e_get_phy_type_from_id(phy->id);
 489
 490         switch (phy->type) {
 491         case e1000_phy_82577:
 492         case e1000_phy_82579:
 493         case e1000_phy_i217:
 494                 phy->ops.check_polarity = e1000_check_polarity_82577;
 495                 phy->ops.force_speed_duplex =
 496                     e1000_phy_force_speed_duplex_82577;
 497                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 498                 phy->ops.get_info = e1000_get_phy_info_82577;
 499                 phy->ops.commit = e1000e_phy_sw_reset;
 500                 break;
 501         case e1000_phy_82578:
 502                 phy->ops.check_polarity = e1000_check_polarity_m88;
 503                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 504                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 505                 phy->ops.get_info = e1000e_get_phy_info_m88;
 506                 break;
 507         default:
 508                 ret_val = -E1000_ERR_PHY;
 509                 break;
 510         }
 511
 512         return ret_val;
 513 }
 514
 515 /**
 516  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 517  *  @hw: pointer to the HW structure
 518  *
 519  *  Initialize family-specific PHY parameters and function pointers.
 520  **/
 521 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 522 {
 523         struct e1000_phy_info *phy = &hw->phy;
 524         s32 ret_val;
 525         u16 i = 0;
 526
 527         phy->addr = 1;
 528         phy->reset_delay_us = 100;
 529
 530         phy->ops.power_up = e1000_power_up_phy_copper;
 531         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 532
 533         /* We may need to do this twice - once for IGP and if that fails,
 534          * we'll set BM func pointers and try again
 535          */
 536         ret_val = e1000e_determine_phy_address(hw);
 537         if (ret_val) {
 538                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 539                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 540                 ret_val = e1000e_determine_phy_address(hw);
 541                 if (ret_val) {
 542                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 543                         return ret_val;
 544                 }
 545         }
 546
 547         phy->id = 0;
 548         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 549                (i++ < 100)) {
 550                 usleep_range(1000, 2000);
 551                 ret_val = e1000e_get_phy_id(hw);
 552                 if (ret_val)
 553                         return ret_val;
 554         }
 555
 556         /* Verify phy id */
 557         switch (phy->id) {
 558         case IGP03E1000_E_PHY_ID:
 559                 phy->type = e1000_phy_igp_3;
 560                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 561                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 562                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 563                 phy->ops.get_info = e1000e_get_phy_info_igp;
 564                 phy->ops.check_polarity = e1000_check_polarity_igp;
 565                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 566                 break;
 567         case IFE_E_PHY_ID:
 568         case IFE_PLUS_E_PHY_ID:
 569         case IFE_C_E_PHY_ID:
 570                 phy->type = e1000_phy_ife;
 571                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 572                 phy->ops.get_info = e1000_get_phy_info_ife;
 573                 phy->ops.check_polarity = e1000_check_polarity_ife;
 574                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 575                 break;
 576         case BME1000_E_PHY_ID:
 577                 phy->type = e1000_phy_bm;
 578                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 579                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 580                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 581                 phy->ops.commit = e1000e_phy_sw_reset;
 582                 phy->ops.get_info = e1000e_get_phy_info_m88;
 583                 phy->ops.check_polarity = e1000_check_polarity_m88;
 584                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 585                 break;
 586         default:
 587                 return -E1000_ERR_PHY;
 588         }
 589
 590         return 0;
 591 }
 592
 593 /**
 594  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 595  *  @hw: pointer to the HW structure
 596  *
 597  *  Initialize family-specific NVM parameters and function
 598  *  pointers.
 599  **/
 600 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 601 {
 602         struct e1000_nvm_info *nvm = &hw->nvm;
 603         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 604         u32 gfpreg, sector_base_addr, sector_end_addr;
 605         u16 i;
 606         u32 nvm_size;
 607
 608         nvm->type = e1000_nvm_flash_sw;
 609
 610         if (hw->mac.type == e1000_pch_spt) {
 611                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 612                  * STRAP register. This is because in SPT the GbE Flash region
 613                  * is no longer accessed through the flash registers. Instead,
 614                  * the mechanism has changed, and the Flash region access
 615                  * registers are now implemented in GbE memory space.
 616                  */
 617                 nvm->flash_base_addr = 0;
 618                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 619                     * NVM_SIZE_MULTIPLIER;
 620                 nvm->flash_bank_size = nvm_size / 2;
 621                 /* Adjust to word count */
 622                 nvm->flash_bank_size /= sizeof(u16);
 623                 /* Set the base address for flash register access */
 624                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 625         } else {
 626                 /* Can't read flash registers if register set isn't mapped. */
 627                 if (!hw->flash_address) {
 628                         e_dbg("ERROR: Flash registers not mapped\n");
 629                         return -E1000_ERR_CONFIG;
 630                 }
 631
 632                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 633
 634                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 635                  * Add 1 to sector_end_addr since this sector is included in
 636                  * the overall size.
 637                  */
 638                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 639                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 640
 641                 /* flash_base_addr is byte-aligned */
 642                 nvm->flash_base_addr = sector_base_addr
 643                     << FLASH_SECTOR_ADDR_SHIFT;
 644
 645                 /* find total size of the NVM, then cut in half since the total
 646                  * size represents two separate NVM banks.
 647                  */
 648                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 649                                         << FLASH_SECTOR_ADDR_SHIFT);
 650                 nvm->flash_bank_size /= 2;
 651                 /* Adjust to word count */
 652                 nvm->flash_bank_size /= sizeof(u16);
 653         }
 654
 655         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 656
 657         /* Clear shadow ram */
 658         for (i = 0; i < nvm->word_size; i++) {
 659                 dev_spec->shadow_ram[i].modified = false;
 660                 dev_spec->shadow_ram[i].value = 0xFFFF;
 661         }
 662
 663         return 0;
 664 }
 665
 666 /**
 667  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 668  *  @hw: pointer to the HW structure
 669  *
 670  *  Initialize family-specific MAC parameters and function
 671  *  pointers.
 672  **/
 673 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 674 {
 675         struct e1000_mac_info *mac = &hw->mac;
 676
 677         /* Set media type function pointer */
 678         hw->phy.media_type = e1000_media_type_copper;
 679
 680         /* Set mta register count */
 681         mac->mta_reg_count = 32;
 682         /* Set rar entry count */
 683         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 684         if (mac->type == e1000_ich8lan)
 685                 mac->rar_entry_count--;
 686         /* FWSM register */
 687         mac->has_fwsm = true;
 688         /* ARC subsystem not supported */
 689         mac->arc_subsystem_valid = false;
 690         /* Adaptive IFS supported */
 691         mac->adaptive_ifs = true;
 692
 693         /* LED and other operations */
 694         switch (mac->type) {
 695         case e1000_ich8lan:
 696         case e1000_ich9lan:
 697         case e1000_ich10lan:
 698                 /* check management mode */
 699                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 700                 /* ID LED init */
 701                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 702                 /* blink LED */
 703                 mac->ops.blink_led = e1000e_blink_led_generic;
 704                 /* setup LED */
 705                 mac->ops.setup_led = e1000e_setup_led_generic;
 706                 /* cleanup LED */
 707                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 708                 /* turn on/off LED */
 709                 mac->ops.led_on = e1000_led_on_ich8lan;
 710                 mac->ops.led_off = e1000_led_off_ich8lan;
 711                 break;
 712         case e1000_pch2lan:
 713                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 714                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 715                 /* fall-through */
 716         case e1000_pch_lpt:
 717         case e1000_pch_spt:
 718         case e1000_pchlan:
 719                 /* check management mode */
 720                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 721                 /* ID LED init */
 722                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 723                 /* setup LED */
 724                 mac->ops.setup_led = e1000_setup_led_pchlan;
 725                 /* cleanup LED */
 726                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 727                 /* turn on/off LED */
 728                 mac->ops.led_on = e1000_led_on_pchlan;
 729                 mac->ops.led_off = e1000_led_off_pchlan;
 730                 break;
 731         default:
 732                 break;
 733         }
 734
 735         if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) {
 736                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 737                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 738                 mac->ops.setup_physical_interface =
 739                     e1000_setup_copper_link_pch_lpt;
 740                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 741         }
 742
 743         /* Enable PCS Lock-loss workaround for ICH8 */
 744         if (mac->type == e1000_ich8lan)
 745                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 746
 747         return 0;
 748 }
 749
 750 /**
 751  *  __e1000_access_emi_reg_locked - Read/write EMI register
 752  *  @hw: pointer to the HW structure
 753  *  @addr: EMI address to program
 754  *  @data: pointer to value to read/write from/to the EMI address
 755  *  @read: boolean flag to indicate read or write
 756  *
 757  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 758  **/
 759 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 760                                          u16 *data, bool read)
 761 {
 762         s32 ret_val;
 763
 764         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 765         if (ret_val)
 766                 return ret_val;
 767
 768         if (read)
 769                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 770         else
 771                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 772
 773         return ret_val;
 774 }
 775
 776 /**
 777  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 778  *  @hw: pointer to the HW structure
 779  *  @addr: EMI address to program
 780  *  @data: value to be read from the EMI address
 781  *
 782  *  Assumes the SW/FW/HW Semaphore is already acquired.
 783  **/
 784 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 785 {
 786         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 787 }
 788
 789 /**
 790  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 791  *  @hw: pointer to the HW structure
 792  *  @addr: EMI address to program
 793  *  @data: value to be written to the EMI address
 794  *
 795  *  Assumes the SW/FW/HW Semaphore is already acquired.
 796  **/
 797 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 798 {
 799         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 800 }
 801
 802 /**
 803  *  e1000_set_eee_pchlan - Enable/disable EEE support
 804  *  @hw: pointer to the HW structure
 805  *
 806  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 807  *  the link and the EEE capabilities of the link partner.  The LPI Control
 808  *  register bits will remain set only if/when link is up.
 809  *
 810  *  EEE LPI must not be asserted earlier than one second after link is up.
 811  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 812  *  can be link issues with some switches.  Other devices can have EEE LPI
 813  *  enabled immediately upon link up since they have a timer in hardware which
 814  *  prevents LPI from being asserted too early.
 815  **/
 816 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 817 {
 818         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 819         s32 ret_val;
 820         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 821
 822         switch (hw->phy.type) {
 823         case e1000_phy_82579:
 824                 lpa = I82579_EEE_LP_ABILITY;
 825                 pcs_status = I82579_EEE_PCS_STATUS;
 826                 adv_addr = I82579_EEE_ADVERTISEMENT;
 827                 break;
 828         case e1000_phy_i217:
 829                 lpa = I217_EEE_LP_ABILITY;
 830                 pcs_status = I217_EEE_PCS_STATUS;
 831                 adv_addr = I217_EEE_ADVERTISEMENT;
 832                 break;
 833         default:
 834                 return 0;
 835         }
 836
 837         ret_val = hw->phy.ops.acquire(hw);
 838         if (ret_val)
 839                 return ret_val;
 840
 841         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 842         if (ret_val)
 843                 goto release;
 844
 845         /* Clear bits that enable EEE in various speeds */
 846         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 847
 848         /* Enable EEE if not disabled by user */
 849         if (!dev_spec->eee_disable) {
 850                 /* Save off link partner's EEE ability */
 851                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 852                                                     &dev_spec->eee_lp_ability);
 853                 if (ret_val)
 854                         goto release;
 855
 856                 /* Read EEE advertisement */
 857                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 858                 if (ret_val)
 859                         goto release;
 860
 861                 /* Enable EEE only for speeds in which the link partner is
 862                  * EEE capable and for which we advertise EEE.
 863                  */
 864                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 865                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 866
 867                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 868                         e1e_rphy_locked(hw, MII_LPA, &data);
 869                         if (data & LPA_100FULL)
 870                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 871                         else
 872                                 /* EEE is not supported in 100Half, so ignore
 873                                  * partner's EEE in 100 ability if full-duplex
 874                                  * is not advertised.
 875                                  */
 876                                 dev_spec->eee_lp_ability &=
 877                                     ~I82579_EEE_100_SUPPORTED;
 878                 }
 879         }
 880
 881         if (hw->phy.type == e1000_phy_82579) {
 882                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 883                                                     &data);
 884                 if (ret_val)
 885                         goto release;
 886
 887                 data &= ~I82579_LPI_100_PLL_SHUT;
 888                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 889                                                      data);
 890         }
 891
 892         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 893         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 894         if (ret_val)
 895                 goto release;
 896
 897         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 898 release:
 899         hw->phy.ops.release(hw);
 900
 901         return ret_val;
 902 }
 903
 904 /**
 905  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 906  *  @hw:   pointer to the HW structure
 907  *  @link: link up bool flag
 908  *
 909  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 910  *  preventing further DMA write requests.  Workaround the issue by disabling
 911  *  the de-assertion of the clock request when in 1Gpbs mode.
 912  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 913  *  speeds in order to avoid Tx hangs.
 914  **/
 915 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 916 {
 917         u32 fextnvm6 = er32(FEXTNVM6);
 918         u32 status = er32(STATUS);
 919         s32 ret_val = 0;
 920         u16 reg;
 921
 922         if (link && (status & E1000_STATUS_SPEED_1000)) {
 923                 ret_val = hw->phy.ops.acquire(hw);
 924                 if (ret_val)
 925                         return ret_val;
 926
 927                 ret_val =
 928                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 929                                                 &reg);
 930                 if (ret_val)
 931                         goto release;
 932
 933                 ret_val =
 934                     e1000e_write_kmrn_reg_locked(hw,
 935                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 936                                                  reg &
 937                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 938                 if (ret_val)
 939                         goto release;
 940
 941                 usleep_range(10, 20);
 942
 943                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 944
 945                 ret_val =
 946                     e1000e_write_kmrn_reg_locked(hw,
 947                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 948                                                  reg);
 949 release:
 950                 hw->phy.ops.release(hw);
 951         } else {
 952                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 953                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 954
 955                 if ((hw->phy.revision > 5) || !link ||
 956                     ((status & E1000_STATUS_SPEED_100) &&
 957                      (status & E1000_STATUS_FD)))
 958                         goto update_fextnvm6;
 959
 960                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 961                 if (ret_val)
 962                         return ret_val;
 963
 964                 /* Clear link status transmit timeout */
 965                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 966
 967                 if (status & E1000_STATUS_SPEED_100) {
 968                         /* Set inband Tx timeout to 5x10us for 100Half */
 969                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 970
 971                         /* Do not extend the K1 entry latency for 100Half */
 972                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 973                 } else {
 974                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 975                         reg |= 50 <<
 976                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 977
 978                         /* Extend the K1 entry latency for 10 Mbps */
 979                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 980                 }
 981
 982                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 983                 if (ret_val)
 984                         return ret_val;
 985
 986 update_fextnvm6:
 987                 ew32(FEXTNVM6, fextnvm6);
 988         }
 989
 990         return ret_val;
 991 }
 992
 993 /**
 994  *  e1000_platform_pm_pch_lpt - Set platform power management values
 995  *  @hw: pointer to the HW structure
 996  *  @link: bool indicating link status
 997  *
 998  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 999  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1000  *  when link is up (which must not exceed the maximum latency supported
1001  *  by the platform), otherwise specify there is no LTR requirement.
1002  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1003  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1004  *  Capability register set, on this device LTR is set by writing the
1005  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1006  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1007  *  message to the PMC.
1008  **/
1009 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1010 {
1011         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1012             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1013         u32 max_ltr_enc_d = 0;  /* maximum LTR decoded by platform */
1014         u32 lat_enc_d = 0;      /* latency decoded */
1015         u16 lat_enc = 0;        /* latency encoded */
1016
1017         if (link) {
1018                 u16 speed, duplex, scale = 0;
1019                 u16 max_snoop, max_nosnoop;
1020                 u16 max_ltr_enc;        /* max LTR latency encoded */
1021                 u64 value;
1022                 u32 rxa;
1023
1024                 if (!hw->adapter->max_frame_size) {
1025                         e_dbg("max_frame_size not set.\n");
1026                         return -E1000_ERR_CONFIG;
1027                 }
1028
1029                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1030                 if (!speed) {
1031                         e_dbg("Speed not set.\n");
1032                         return -E1000_ERR_CONFIG;
1033                 }
1034
1035                 /* Rx Packet Buffer Allocation size (KB) */
1036                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1037
1038                 /* Determine the maximum latency tolerated by the device.
1039                  *
1040                  * Per the PCIe spec, the tolerated latencies are encoded as
1041                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1042                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1043                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1044                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1045                  */
1046                 rxa *= 512;
1047                 value = (rxa > hw->adapter->max_frame_size) ?
1048                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1049                         0;
1050
1051                 while (value > PCI_LTR_VALUE_MASK) {
1052                         scale++;
1053                         value = DIV_ROUND_UP(value, BIT(5));
1054                 }
1055                 if (scale > E1000_LTRV_SCALE_MAX) {
1056                         e_dbg("Invalid LTR latency scale %d\n", scale);
1057                         return -E1000_ERR_CONFIG;
1058                 }
1059                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1060
1061                 /* Determine the maximum latency tolerated by the platform */
1062                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1063                                      &max_snoop);
1064                 pci_read_config_word(hw->adapter->pdev,
1065                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1066                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1067
1068                 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1069                              (1U << (E1000_LTRV_SCALE_FACTOR *
1070                              ((lat_enc & E1000_LTRV_SCALE_MASK)
1071                              >> E1000_LTRV_SCALE_SHIFT)));
1072
1073                 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1074                                  (1U << (E1000_LTRV_SCALE_FACTOR *
1075                                  ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1076                                  >> E1000_LTRV_SCALE_SHIFT)));
1077
1078                 if (lat_enc_d > max_ltr_enc_d)
1079                         lat_enc = max_ltr_enc;
1080         }
1081
1082         /* Set Snoop and No-Snoop latencies the same */
1083         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1084         ew32(LTRV, reg);
1085
1086         return 0;
1087 }
1088
1089 /**
1090  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1091  *  @hw: pointer to the HW structure
1092  *  @to_sx: boolean indicating a system power state transition to Sx
1093  *
1094  *  When link is down, configure ULP mode to significantly reduce the power
1095  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1096  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1097  *  system, configure the ULP mode by software.
1098  */
1099 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1100 {
1101         u32 mac_reg;
1102         s32 ret_val = 0;
1103         u16 phy_reg;
1104         u16 oem_reg = 0;
1105
1106         if ((hw->mac.type < e1000_pch_lpt) ||
1107             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1108             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1109             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1110             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1111             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1112                 return 0;
1113
1114         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1115                 /* Request ME configure ULP mode in the PHY */
1116                 mac_reg = er32(H2ME);
1117                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1118                 ew32(H2ME, mac_reg);
1119
1120                 goto out;
1121         }
1122
1123         if (!to_sx) {
1124                 int i = 0;
1125
1126                 /* Poll up to 5 seconds for Cable Disconnected indication */
1127                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1128                         /* Bail if link is re-acquired */
1129                         if (er32(STATUS) & E1000_STATUS_LU)
1130                                 return -E1000_ERR_PHY;
1131
1132                         if (i++ == 100)
1133                                 break;
1134
1135                         msleep(50);
1136                 }
1137                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1138                       (er32(FEXT) &
1139                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1140         }
1141
1142         ret_val = hw->phy.ops.acquire(hw);
1143         if (ret_val)
1144                 goto out;
1145
1146         /* Force SMBus mode in PHY */
1147         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1148         if (ret_val)
1149                 goto release;
1150         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1151         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1152
1153         /* Force SMBus mode in MAC */
1154         mac_reg = er32(CTRL_EXT);
1155         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1156         ew32(CTRL_EXT, mac_reg);
1157
1158         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1159          * LPLU and disable Gig speed when entering ULP
1160          */
1161         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1162                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1163                                                        &oem_reg);
1164                 if (ret_val)
1165                         goto release;
1166
1167                 phy_reg = oem_reg;
1168                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1169
1170                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1171                                                         phy_reg);
1172
1173                 if (ret_val)
1174                         goto release;
1175         }
1176
1177         /* Set Inband ULP Exit, Reset to SMBus mode and
1178          * Disable SMBus Release on PERST# in PHY
1179          */
1180         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1181         if (ret_val)
1182                 goto release;
1183         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1184                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1185         if (to_sx) {
1186                 if (er32(WUFC) & E1000_WUFC_LNKC)
1187                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1188                 else
1189                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1190
1191                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1192                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1193         } else {
1194                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1195                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1196                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1197         }
1198         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1199
1200         /* Set Disable SMBus Release on PERST# in MAC */
1201         mac_reg = er32(FEXTNVM7);
1202         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1203         ew32(FEXTNVM7, mac_reg);
1204
1205         /* Commit ULP changes in PHY by starting auto ULP configuration */
1206         phy_reg |= I218_ULP_CONFIG1_START;
1207         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1208
1209         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1210             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1211                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1212                                                         oem_reg);
1213                 if (ret_val)
1214                         goto release;
1215         }
1216
1217 release:
1218         hw->phy.ops.release(hw);
1219 out:
1220         if (ret_val)
1221                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1222         else
1223                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1224
1225         return ret_val;
1226 }
1227
1228 /**
1229  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1230  *  @hw: pointer to the HW structure
1231  *  @force: boolean indicating whether or not to force disabling ULP
1232  *
1233  *  Un-configure ULP mode when link is up, the system is transitioned from
1234  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1235  *  system, poll for an indication from ME that ULP has been un-configured.
1236  *  If not on an ME enabled system, un-configure the ULP mode by software.
1237  *
1238  *  During nominal operation, this function is called when link is acquired
1239  *  to disable ULP mode (force=false); otherwise, for example when unloading
1240  *  the driver or during Sx->S0 transitions, this is called with force=true
1241  *  to forcibly disable ULP.
1242  */
1243 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1244 {
1245         s32 ret_val = 0;
1246         u32 mac_reg;
1247         u16 phy_reg;
1248         int i = 0;
1249
1250         if ((hw->mac.type < e1000_pch_lpt) ||
1251             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1252             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1253             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1254             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1255             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1256                 return 0;
1257
1258         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1259                 if (force) {
1260                         /* Request ME un-configure ULP mode in the PHY */
1261                         mac_reg = er32(H2ME);
1262                         mac_reg &= ~E1000_H2ME_ULP;
1263                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1264                         ew32(H2ME, mac_reg);
1265                 }
1266
1267                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1268                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1269                         if (i++ == 30) {
1270                                 ret_val = -E1000_ERR_PHY;
1271                                 goto out;
1272                         }
1273
1274                         usleep_range(10000, 20000);
1275                 }
1276                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1277
1278                 if (force) {
1279                         mac_reg = er32(H2ME);
1280                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1281                         ew32(H2ME, mac_reg);
1282                 } else {
1283                         /* Clear H2ME.ULP after ME ULP configuration */
1284                         mac_reg = er32(H2ME);
1285                         mac_reg &= ~E1000_H2ME_ULP;
1286                         ew32(H2ME, mac_reg);
1287                 }
1288
1289                 goto out;
1290         }
1291
1292         ret_val = hw->phy.ops.acquire(hw);
1293         if (ret_val)
1294                 goto out;
1295
1296         if (force)
1297                 /* Toggle LANPHYPC Value bit */
1298                 e1000_toggle_lanphypc_pch_lpt(hw);
1299
1300         /* Unforce SMBus mode in PHY */
1301         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1302         if (ret_val) {
1303                 /* The MAC might be in PCIe mode, so temporarily force to
1304                  * SMBus mode in order to access the PHY.
1305                  */
1306                 mac_reg = er32(CTRL_EXT);
1307                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1308                 ew32(CTRL_EXT, mac_reg);
1309
1310                 msleep(50);
1311
1312                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1313                                                        &phy_reg);
1314                 if (ret_val)
1315                         goto release;
1316         }
1317         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1318         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1319
1320         /* Unforce SMBus mode in MAC */
1321         mac_reg = er32(CTRL_EXT);
1322         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1323         ew32(CTRL_EXT, mac_reg);
1324
1325         /* When ULP mode was previously entered, K1 was disabled by the
1326          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1327          */
1328         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1329         if (ret_val)
1330                 goto release;
1331         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1332         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1333
1334         /* Clear ULP enabled configuration */
1335         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1336         if (ret_val)
1337                 goto release;
1338         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1339                      I218_ULP_CONFIG1_STICKY_ULP |
1340                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1341                      I218_ULP_CONFIG1_WOL_HOST |
1342                      I218_ULP_CONFIG1_INBAND_EXIT |
1343                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1344                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1345                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1346         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1347
1348         /* Commit ULP changes by starting auto ULP configuration */
1349         phy_reg |= I218_ULP_CONFIG1_START;
1350         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1351
1352         /* Clear Disable SMBus Release on PERST# in MAC */
1353         mac_reg = er32(FEXTNVM7);
1354         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1355         ew32(FEXTNVM7, mac_reg);
1356
1357 release:
1358         hw->phy.ops.release(hw);
1359         if (force) {
1360                 e1000_phy_hw_reset(hw);
1361                 msleep(50);
1362         }
1363 out:
1364         if (ret_val)
1365                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1366         else
1367                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1368
1369         return ret_val;
1370 }
1371
1372 /**
1373  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1374  *  @hw: pointer to the HW structure
1375  *
1376  *  Checks to see of the link status of the hardware has changed.  If a
1377  *  change in link status has been detected, then we read the PHY registers
1378  *  to get the current speed/duplex if link exists.
1379  **/
1380 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1381 {
1382         struct e1000_mac_info *mac = &hw->mac;
1383         s32 ret_val, tipg_reg = 0;
1384         u16 emi_addr, emi_val = 0;
1385         bool link;
1386         u16 phy_reg;
1387
1388         /* We only want to go out to the PHY registers to see if Auto-Neg
1389          * has completed and/or if our link status has changed.  The
1390          * get_link_status flag is set upon receiving a Link Status
1391          * Change or Rx Sequence Error interrupt.
1392          */
1393         if (!mac->get_link_status)
1394                 return 0;
1395         mac->get_link_status = false;
1396
1397         /* First we want to see if the MII Status Register reports
1398          * link.  If so, then we want to get the current speed/duplex
1399          * of the PHY.
1400          */
1401         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1402         if (ret_val)
1403                 goto out;
1404
1405         if (hw->mac.type == e1000_pchlan) {
1406                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1407                 if (ret_val)
1408                         goto out;
1409         }
1410
1411         /* When connected at 10Mbps half-duplex, some parts are excessively
1412          * aggressive resulting in many collisions. To avoid this, increase
1413          * the IPG and reduce Rx latency in the PHY.
1414          */
1415         if (((hw->mac.type == e1000_pch2lan) ||
1416              (hw->mac.type == e1000_pch_lpt) ||
1417              (hw->mac.type == e1000_pch_spt)) && link) {
1418                 u16 speed, duplex;
1419
1420                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1421                 tipg_reg = er32(TIPG);
1422                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1423
1424                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1425                         tipg_reg |= 0xFF;
1426                         /* Reduce Rx latency in analog PHY */
1427                         emi_val = 0;
1428                 } else if (hw->mac.type == e1000_pch_spt &&
1429                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1430                         tipg_reg |= 0xC;
1431                         emi_val = 1;
1432                 } else {
1433
1434                         /* Roll back the default values */
1435                         tipg_reg |= 0x08;
1436                         emi_val = 1;
1437                 }
1438
1439                 ew32(TIPG, tipg_reg);
1440
1441                 ret_val = hw->phy.ops.acquire(hw);
1442                 if (ret_val)
1443                         goto out;
1444
1445                 if (hw->mac.type == e1000_pch2lan)
1446                         emi_addr = I82579_RX_CONFIG;
1447                 else
1448                         emi_addr = I217_RX_CONFIG;
1449                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1450
1451                 if (hw->mac.type == e1000_pch_lpt ||
1452                     hw->mac.type == e1000_pch_spt) {
1453                         u16 phy_reg;
1454
1455                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1456                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1457                         if (speed == SPEED_100 || speed == SPEED_10)
1458                                 phy_reg |= 0x3E8;
1459                         else
1460                                 phy_reg |= 0xFA;
1461                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1462
1463                         if (speed == SPEED_1000) {
1464                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1465                                                             &phy_reg);
1466
1467                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1468
1469                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1470                                                              phy_reg);
1471                         }
1472                 }
1473                 hw->phy.ops.release(hw);
1474
1475                 if (ret_val)
1476                         goto out;
1477
1478                 if (hw->mac.type == e1000_pch_spt) {
1479                         u16 data;
1480                         u16 ptr_gap;
1481
1482                         if (speed == SPEED_1000) {
1483                                 ret_val = hw->phy.ops.acquire(hw);
1484                                 if (ret_val)
1485                                         goto out;
1486
1487                                 ret_val = e1e_rphy_locked(hw,
1488                                                           PHY_REG(776, 20),
1489                                                           &data);
1490                                 if (ret_val) {
1491                                         hw->phy.ops.release(hw);
1492                                         goto out;
1493                                 }
1494
1495                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1496                                 if (ptr_gap < 0x18) {
1497                                         data &= ~(0x3FF << 2);
1498                                         data |= (0x18 << 2);
1499                                         ret_val =
1500                                             e1e_wphy_locked(hw,
1501                                                             PHY_REG(776, 20),
1502                                                             data);
1503                                 }
1504                                 hw->phy.ops.release(hw);
1505                                 if (ret_val)
1506                                         goto out;
1507                         } else {
1508                                 ret_val = hw->phy.ops.acquire(hw);
1509                                 if (ret_val)
1510                                         goto out;
1511
1512                                 ret_val = e1e_wphy_locked(hw,
1513                                                           PHY_REG(776, 20),
1514                                                           0xC023);
1515                                 hw->phy.ops.release(hw);
1516                                 if (ret_val)
1517                                         goto out;
1518
1519                         }
1520                 }
1521         }
1522
1523         /* I217 Packet Loss issue:
1524          * ensure that FEXTNVM4 Beacon Duration is set correctly
1525          * on power up.
1526          * Set the Beacon Duration for I217 to 8 usec
1527          */
1528         if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
1529                 u32 mac_reg;
1530
1531                 mac_reg = er32(FEXTNVM4);
1532                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1533                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1534                 ew32(FEXTNVM4, mac_reg);
1535         }
1536
1537         /* Work-around I218 hang issue */
1538         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1539             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1540             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1541             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1542                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1543                 if (ret_val)
1544                         goto out;
1545         }
1546         if ((hw->mac.type == e1000_pch_lpt) ||
1547             (hw->mac.type == e1000_pch_spt)) {
1548                 /* Set platform power management values for
1549                  * Latency Tolerance Reporting (LTR)
1550                  */
1551                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1552                 if (ret_val)
1553                         goto out;
1554         }
1555
1556         /* Clear link partner's EEE ability */
1557         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1558
1559         /* FEXTNVM6 K1-off workaround */
1560         if (hw->mac.type == e1000_pch_spt) {
1561                 u32 pcieanacfg = er32(PCIEANACFG);
1562                 u32 fextnvm6 = er32(FEXTNVM6);
1563
1564                 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1565                         fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1566                 else
1567                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1568
1569                 ew32(FEXTNVM6, fextnvm6);
1570         }
1571
1572         if (!link)
1573                 goto out;
1574
1575         switch (hw->mac.type) {
1576         case e1000_pch2lan:
1577                 ret_val = e1000_k1_workaround_lv(hw);
1578                 if (ret_val)
1579                         return ret_val;
1580                 /* fall-thru */
1581         case e1000_pchlan:
1582                 if (hw->phy.type == e1000_phy_82578) {
1583                         ret_val = e1000_link_stall_workaround_hv(hw);
1584                         if (ret_val)
1585                                 return ret_val;
1586                 }
1587
1588                 /* Workaround for PCHx parts in half-duplex:
1589                  * Set the number of preambles removed from the packet
1590                  * when it is passed from the PHY to the MAC to prevent
1591                  * the MAC from misinterpreting the packet type.
1592                  */
1593                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1594                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1595
1596                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1597                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1598
1599                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1600                 break;
1601         default:
1602                 break;
1603         }
1604
1605         /* Check if there was DownShift, must be checked
1606          * immediately after link-up
1607          */
1608         e1000e_check_downshift(hw);
1609
1610         /* Enable/Disable EEE after link up */
1611         if (hw->phy.type > e1000_phy_82579) {
1612                 ret_val = e1000_set_eee_pchlan(hw);
1613                 if (ret_val)
1614                         return ret_val;
1615         }
1616
1617         /* If we are forcing speed/duplex, then we simply return since
1618          * we have already determined whether we have link or not.
1619          */
1620         if (!mac->autoneg)
1621                 return -E1000_ERR_CONFIG;
1622
1623         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1624          * of MAC speed/duplex configuration.  So we only need to
1625          * configure Collision Distance in the MAC.
1626          */
1627         mac->ops.config_collision_dist(hw);
1628
1629         /* Configure Flow Control now that Auto-Neg has completed.
1630          * First, we need to restore the desired flow control
1631          * settings because we may have had to re-autoneg with a
1632          * different link partner.
1633          */
1634         ret_val = e1000e_config_fc_after_link_up(hw);
1635         if (ret_val)
1636                 e_dbg("Error configuring flow control\n");
1637
1638         return ret_val;
1639
1640 out:
1641         mac->get_link_status = true;
1642         return ret_val;
1643 }
1644
1645 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1646 {
1647         struct e1000_hw *hw = &adapter->hw;
1648         s32 rc;
1649
1650         rc = e1000_init_mac_params_ich8lan(hw);
1651         if (rc)
1652                 return rc;
1653
1654         rc = e1000_init_nvm_params_ich8lan(hw);
1655         if (rc)
1656                 return rc;
1657
1658         switch (hw->mac.type) {
1659         case e1000_ich8lan:
1660         case e1000_ich9lan:
1661         case e1000_ich10lan:
1662                 rc = e1000_init_phy_params_ich8lan(hw);
1663                 break;
1664         case e1000_pchlan:
1665         case e1000_pch2lan:
1666         case e1000_pch_lpt:
1667         case e1000_pch_spt:
1668                 rc = e1000_init_phy_params_pchlan(hw);
1669                 break;
1670         default:
1671                 break;
1672         }
1673         if (rc)
1674                 return rc;
1675
1676         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1677          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1678          */
1679         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1680             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1681              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1682                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1683                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1684
1685                 hw->mac.ops.blink_led = NULL;
1686         }
1687
1688         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1689             (adapter->hw.phy.type != e1000_phy_ife))
1690                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1691
1692         /* Enable workaround for 82579 w/ ME enabled */
1693         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1694             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1695                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1696
1697         return 0;
1698 }
1699
1700 static DEFINE_MUTEX(nvm_mutex);
1701
1702 /**
1703  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1704  *  @hw: pointer to the HW structure
1705  *
1706  *  Acquires the mutex for performing NVM operations.
1707  **/
1708 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1709 {
1710         mutex_lock(&nvm_mutex);
1711
1712         return 0;
1713 }
1714
1715 /**
1716  *  e1000_release_nvm_ich8lan - Release NVM mutex
1717  *  @hw: pointer to the HW structure
1718  *
1719  *  Releases the mutex used while performing NVM operations.
1720  **/
1721 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1722 {
1723         mutex_unlock(&nvm_mutex);
1724 }
1725
1726 /**
1727  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1728  *  @hw: pointer to the HW structure
1729  *
1730  *  Acquires the software control flag for performing PHY and select
1731  *  MAC CSR accesses.
1732  **/
1733 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1734 {
1735         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1736         s32 ret_val = 0;
1737
1738         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1739                              &hw->adapter->state)) {
1740                 e_dbg("contention for Phy access\n");
1741                 return -E1000_ERR_PHY;
1742         }
1743
1744         while (timeout) {
1745                 extcnf_ctrl = er32(EXTCNF_CTRL);
1746                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1747                         break;
1748
1749                 mdelay(1);
1750                 timeout--;
1751         }
1752
1753         if (!timeout) {
1754                 e_dbg("SW has already locked the resource.\n");
1755                 ret_val = -E1000_ERR_CONFIG;
1756                 goto out;
1757         }
1758
1759         timeout = SW_FLAG_TIMEOUT;
1760
1761         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1762         ew32(EXTCNF_CTRL, extcnf_ctrl);
1763
1764         while (timeout) {
1765                 extcnf_ctrl = er32(EXTCNF_CTRL);
1766                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1767                         break;
1768
1769                 mdelay(1);
1770                 timeout--;
1771         }
1772
1773         if (!timeout) {
1774                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1775                       er32(FWSM), extcnf_ctrl);
1776                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1777                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1778                 ret_val = -E1000_ERR_CONFIG;
1779                 goto out;
1780         }
1781
1782 out:
1783         if (ret_val)
1784                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1785
1786         return ret_val;
1787 }
1788
1789 /**
1790  *  e1000_release_swflag_ich8lan - Release software control flag
1791  *  @hw: pointer to the HW structure
1792  *
1793  *  Releases the software control flag for performing PHY and select
1794  *  MAC CSR accesses.
1795  **/
1796 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1797 {
1798         u32 extcnf_ctrl;
1799
1800         extcnf_ctrl = er32(EXTCNF_CTRL);
1801
1802         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1803                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1804                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1805         } else {
1806                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1807         }
1808
1809         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1810 }
1811
1812 /**
1813  *  e1000_check_mng_mode_ich8lan - Checks management mode
1814  *  @hw: pointer to the HW structure
1815  *
1816  *  This checks if the adapter has any manageability enabled.
1817  *  This is a function pointer entry point only called by read/write
1818  *  routines for the PHY and NVM parts.
1819  **/
1820 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1821 {
1822         u32 fwsm;
1823
1824         fwsm = er32(FWSM);
1825         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1826                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1827                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1828 }
1829
1830 /**
1831  *  e1000_check_mng_mode_pchlan - Checks management mode
1832  *  @hw: pointer to the HW structure
1833  *
1834  *  This checks if the adapter has iAMT enabled.
1835  *  This is a function pointer entry point only called by read/write
1836  *  routines for the PHY and NVM parts.
1837  **/
1838 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1839 {
1840         u32 fwsm;
1841
1842         fwsm = er32(FWSM);
1843         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1844             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1845 }
1846
1847 /**
1848  *  e1000_rar_set_pch2lan - Set receive address register
1849  *  @hw: pointer to the HW structure
1850  *  @addr: pointer to the receive address
1851  *  @index: receive address array register
1852  *
1853  *  Sets the receive address array register at index to the address passed
1854  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1855  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1856  *  Use SHRA[0-3] in place of those reserved for ME.
1857  **/
1858 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1859 {
1860         u32 rar_low, rar_high;
1861
1862         /* HW expects these in little endian so we reverse the byte order
1863          * from network order (big endian) to little endian
1864          */
1865         rar_low = ((u32)addr[0] |
1866                    ((u32)addr[1] << 8) |
1867                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1868
1869         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1870
1871         /* If MAC address zero, no need to set the AV bit */
1872         if (rar_low || rar_high)
1873                 rar_high |= E1000_RAH_AV;
1874
1875         if (index == 0) {
1876                 ew32(RAL(index), rar_low);
1877                 e1e_flush();
1878                 ew32(RAH(index), rar_high);
1879                 e1e_flush();
1880                 return 0;
1881         }
1882
1883         /* RAR[1-6] are owned by manageability.  Skip those and program the
1884          * next address into the SHRA register array.
1885          */
1886         if (index < (u32)(hw->mac.rar_entry_count)) {
1887                 s32 ret_val;
1888
1889                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1890                 if (ret_val)
1891                         goto out;
1892
1893                 ew32(SHRAL(index - 1), rar_low);
1894                 e1e_flush();
1895                 ew32(SHRAH(index - 1), rar_high);
1896                 e1e_flush();
1897
1898                 e1000_release_swflag_ich8lan(hw);
1899
1900                 /* verify the register updates */
1901                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1902                     (er32(SHRAH(index - 1)) == rar_high))
1903                         return 0;
1904
1905                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1906                       (index - 1), er32(FWSM));
1907         }
1908
1909 out:
1910         e_dbg("Failed to write receive address at index %d\n", index);
1911         return -E1000_ERR_CONFIG;
1912 }
1913
1914 /**
1915  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1916  *  @hw: pointer to the HW structure
1917  *
1918  *  Get the number of available receive registers that the Host can
1919  *  program. SHRA[0-10] are the shared receive address registers
1920  *  that are shared between the Host and manageability engine (ME).
1921  *  ME can reserve any number of addresses and the host needs to be
1922  *  able to tell how many available registers it has access to.
1923  **/
1924 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1925 {
1926         u32 wlock_mac;
1927         u32 num_entries;
1928
1929         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1930         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1931
1932         switch (wlock_mac) {
1933         case 0:
1934                 /* All SHRA[0..10] and RAR[0] available */
1935                 num_entries = hw->mac.rar_entry_count;
1936                 break;
1937         case 1:
1938                 /* Only RAR[0] available */
1939                 num_entries = 1;
1940                 break;
1941         default:
1942                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1943                 num_entries = wlock_mac + 1;
1944                 break;
1945         }
1946
1947         return num_entries;
1948 }
1949
1950 /**
1951  *  e1000_rar_set_pch_lpt - Set receive address registers
1952  *  @hw: pointer to the HW structure
1953  *  @addr: pointer to the receive address
1954  *  @index: receive address array register
1955  *
1956  *  Sets the receive address register array at index to the address passed
1957  *  in by addr. For LPT, RAR[0] is the base address register that is to
1958  *  contain the MAC address. SHRA[0-10] are the shared receive address
1959  *  registers that are shared between the Host and manageability engine (ME).
1960  **/
1961 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1962 {
1963         u32 rar_low, rar_high;
1964         u32 wlock_mac;
1965
1966         /* HW expects these in little endian so we reverse the byte order
1967          * from network order (big endian) to little endian
1968          */
1969         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1970                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1971
1972         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1973
1974         /* If MAC address zero, no need to set the AV bit */
1975         if (rar_low || rar_high)
1976                 rar_high |= E1000_RAH_AV;
1977
1978         if (index == 0) {
1979                 ew32(RAL(index), rar_low);
1980                 e1e_flush();
1981                 ew32(RAH(index), rar_high);
1982                 e1e_flush();
1983                 return 0;
1984         }
1985
1986         /* The manageability engine (ME) can lock certain SHRAR registers that
1987          * it is using - those registers are unavailable for use.
1988          */
1989         if (index < hw->mac.rar_entry_count) {
1990                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1991                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1992
1993                 /* Check if all SHRAR registers are locked */
1994                 if (wlock_mac == 1)
1995                         goto out;
1996
1997                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1998                         s32 ret_val;
1999
2000                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2001
2002                         if (ret_val)
2003                                 goto out;
2004
2005                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2006                         e1e_flush();
2007                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2008                         e1e_flush();
2009
2010                         e1000_release_swflag_ich8lan(hw);
2011
2012                         /* verify the register updates */
2013                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2014                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2015                                 return 0;
2016                 }
2017         }
2018
2019 out:
2020         e_dbg("Failed to write receive address at index %d\n", index);
2021         return -E1000_ERR_CONFIG;
2022 }
2023
2024 /**
2025  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2026  *  @hw: pointer to the HW structure
2027  *
2028  *  Checks if firmware is blocking the reset of the PHY.
2029  *  This is a function pointer entry point only called by
2030  *  reset routines.
2031  **/
2032 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2033 {
2034         bool blocked = false;
2035         int i = 0;
2036
2037         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2038                (i++ < 30))
2039                 usleep_range(10000, 20000);
2040         return blocked ? E1000_BLK_PHY_RESET : 0;
2041 }
2042
2043 /**
2044  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2045  *  @hw: pointer to the HW structure
2046  *
2047  *  Assumes semaphore already acquired.
2048  *
2049  **/
2050 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2051 {
2052         u16 phy_data;
2053         u32 strap = er32(STRAP);
2054         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2055             E1000_STRAP_SMT_FREQ_SHIFT;
2056         s32 ret_val;
2057
2058         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2059
2060         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2061         if (ret_val)
2062                 return ret_val;
2063
2064         phy_data &= ~HV_SMB_ADDR_MASK;
2065         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2066         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2067
2068         if (hw->phy.type == e1000_phy_i217) {
2069                 /* Restore SMBus frequency */
2070                 if (freq--) {
2071                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2072                         phy_data |= (freq & BIT(0)) <<
2073                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2074                         phy_data |= (freq & BIT(1)) <<
2075                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2076                 } else {
2077                         e_dbg("Unsupported SMB frequency in PHY\n");
2078                 }
2079         }
2080
2081         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2082 }
2083
2084 /**
2085  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2086  *  @hw:   pointer to the HW structure
2087  *
2088  *  SW should configure the LCD from the NVM extended configuration region
2089  *  as a workaround for certain parts.
2090  **/
2091 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2092 {
2093         struct e1000_phy_info *phy = &hw->phy;
2094         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2095         s32 ret_val = 0;
2096         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2097
2098         /* Initialize the PHY from the NVM on ICH platforms.  This
2099          * is needed due to an issue where the NVM configuration is
2100          * not properly autoloaded after power transitions.
2101          * Therefore, after each PHY reset, we will load the
2102          * configuration data out of the NVM manually.
2103          */
2104         switch (hw->mac.type) {
2105         case e1000_ich8lan:
2106                 if (phy->type != e1000_phy_igp_3)
2107                         return ret_val;
2108
2109                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2110                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2111                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2112                         break;
2113                 }
2114                 /* Fall-thru */
2115         case e1000_pchlan:
2116         case e1000_pch2lan:
2117         case e1000_pch_lpt:
2118         case e1000_pch_spt:
2119                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2120                 break;
2121         default:
2122                 return ret_val;
2123         }
2124
2125         ret_val = hw->phy.ops.acquire(hw);
2126         if (ret_val)
2127                 return ret_val;
2128
2129         data = er32(FEXTNVM);
2130         if (!(data & sw_cfg_mask))
2131                 goto release;
2132
2133         /* Make sure HW does not configure LCD from PHY
2134          * extended configuration before SW configuration
2135          */
2136         data = er32(EXTCNF_CTRL);
2137         if ((hw->mac.type < e1000_pch2lan) &&
2138             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2139                 goto release;
2140
2141         cnf_size = er32(EXTCNF_SIZE);
2142         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2143         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2144         if (!cnf_size)
2145                 goto release;
2146
2147         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2148         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2149
2150         if (((hw->mac.type == e1000_pchlan) &&
2151              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2152             (hw->mac.type > e1000_pchlan)) {
2153                 /* HW configures the SMBus address and LEDs when the
2154                  * OEM and LCD Write Enable bits are set in the NVM.
2155                  * When both NVM bits are cleared, SW will configure
2156                  * them instead.
2157                  */
2158                 ret_val = e1000_write_smbus_addr(hw);
2159                 if (ret_val)
2160                         goto release;
2161
2162                 data = er32(LEDCTL);
2163                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2164                                                         (u16)data);
2165                 if (ret_val)
2166                         goto release;
2167         }
2168
2169         /* Configure LCD from extended configuration region. */
2170
2171         /* cnf_base_addr is in DWORD */
2172         word_addr = (u16)(cnf_base_addr << 1);
2173
2174         for (i = 0; i < cnf_size; i++) {
2175                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2176                 if (ret_val)
2177                         goto release;
2178
2179                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2180                                          1, &reg_addr);
2181                 if (ret_val)
2182                         goto release;
2183
2184                 /* Save off the PHY page for future writes. */
2185                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2186                         phy_page = reg_data;
2187                         continue;
2188                 }
2189
2190                 reg_addr &= PHY_REG_MASK;
2191                 reg_addr |= phy_page;
2192
2193                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2194                 if (ret_val)
2195                         goto release;
2196         }
2197
2198 release:
2199         hw->phy.ops.release(hw);
2200         return ret_val;
2201 }
2202
2203 /**
2204  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2205  *  @hw:   pointer to the HW structure
2206  *  @link: link up bool flag
2207  *
2208  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2209  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2210  *  If link is down, the function will restore the default K1 setting located
2211  *  in the NVM.
2212  **/
2213 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2214 {
2215         s32 ret_val = 0;
2216         u16 status_reg = 0;
2217         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2218
2219         if (hw->mac.type != e1000_pchlan)
2220                 return 0;
2221
2222         /* Wrap the whole flow with the sw flag */
2223         ret_val = hw->phy.ops.acquire(hw);
2224         if (ret_val)
2225                 return ret_val;
2226
2227         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2228         if (link) {
2229                 if (hw->phy.type == e1000_phy_82578) {
2230                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2231                                                   &status_reg);
2232                         if (ret_val)
2233                                 goto release;
2234
2235                         status_reg &= (BM_CS_STATUS_LINK_UP |
2236                                        BM_CS_STATUS_RESOLVED |
2237                                        BM_CS_STATUS_SPEED_MASK);
2238
2239                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2240                                            BM_CS_STATUS_RESOLVED |
2241                                            BM_CS_STATUS_SPEED_1000))
2242                                 k1_enable = false;
2243                 }
2244
2245                 if (hw->phy.type == e1000_phy_82577) {
2246                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2247                         if (ret_val)
2248                                 goto release;
2249
2250                         status_reg &= (HV_M_STATUS_LINK_UP |
2251                                        HV_M_STATUS_AUTONEG_COMPLETE |
2252                                        HV_M_STATUS_SPEED_MASK);
2253
2254                         if (status_reg == (HV_M_STATUS_LINK_UP |
2255                                            HV_M_STATUS_AUTONEG_COMPLETE |
2256                                            HV_M_STATUS_SPEED_1000))
2257                                 k1_enable = false;
2258                 }
2259
2260                 /* Link stall fix for link up */
2261                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2262                 if (ret_val)
2263                         goto release;
2264
2265         } else {
2266                 /* Link stall fix for link down */
2267                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2268                 if (ret_val)
2269                         goto release;
2270         }
2271
2272         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2273
2274 release:
2275         hw->phy.ops.release(hw);
2276
2277         return ret_val;
2278 }
2279
2280 /**
2281  *  e1000_configure_k1_ich8lan - Configure K1 power state
2282  *  @hw: pointer to the HW structure
2283  *  @enable: K1 state to configure
2284  *
2285  *  Configure the K1 power state based on the provided parameter.
2286  *  Assumes semaphore already acquired.
2287  *
2288  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2289  **/
2290 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2291 {
2292         s32 ret_val;
2293         u32 ctrl_reg = 0;
2294         u32 ctrl_ext = 0;
2295         u32 reg = 0;
2296         u16 kmrn_reg = 0;
2297
2298         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2299                                               &kmrn_reg);
2300         if (ret_val)
2301                 return ret_val;
2302
2303         if (k1_enable)
2304                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2305         else
2306                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2307
2308         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2309                                                kmrn_reg);
2310         if (ret_val)
2311                 return ret_val;
2312
2313         usleep_range(20, 40);
2314         ctrl_ext = er32(CTRL_EXT);
2315         ctrl_reg = er32(CTRL);
2316
2317         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2318         reg |= E1000_CTRL_FRCSPD;
2319         ew32(CTRL, reg);
2320
2321         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2322         e1e_flush();
2323         usleep_range(20, 40);
2324         ew32(CTRL, ctrl_reg);
2325         ew32(CTRL_EXT, ctrl_ext);
2326         e1e_flush();
2327         usleep_range(20, 40);
2328
2329         return 0;
2330 }
2331
2332 /**
2333  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2334  *  @hw:       pointer to the HW structure
2335  *  @d0_state: boolean if entering d0 or d3 device state
2336  *
2337  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2338  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2339  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2340  **/
2341 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2342 {
2343         s32 ret_val = 0;
2344         u32 mac_reg;
2345         u16 oem_reg;
2346
2347         if (hw->mac.type < e1000_pchlan)
2348                 return ret_val;
2349
2350         ret_val = hw->phy.ops.acquire(hw);
2351         if (ret_val)
2352                 return ret_val;
2353
2354         if (hw->mac.type == e1000_pchlan) {
2355                 mac_reg = er32(EXTCNF_CTRL);
2356                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2357                         goto release;
2358         }
2359
2360         mac_reg = er32(FEXTNVM);
2361         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2362                 goto release;
2363
2364         mac_reg = er32(PHY_CTRL);
2365
2366         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2367         if (ret_val)
2368                 goto release;
2369
2370         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2371
2372         if (d0_state) {
2373                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2374                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2375
2376                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2377                         oem_reg |= HV_OEM_BITS_LPLU;
2378         } else {
2379                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2380                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2381                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2382
2383                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2384                                E1000_PHY_CTRL_NOND0A_LPLU))
2385                         oem_reg |= HV_OEM_BITS_LPLU;
2386         }
2387
2388         /* Set Restart auto-neg to activate the bits */
2389         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2390             !hw->phy.ops.check_reset_block(hw))
2391                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2392
2393         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2394
2395 release:
2396         hw->phy.ops.release(hw);
2397
2398         return ret_val;
2399 }
2400
2401 /**
2402  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2403  *  @hw:   pointer to the HW structure
2404  **/
2405 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2406 {
2407         s32 ret_val;
2408         u16 data;
2409
2410         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2411         if (ret_val)
2412                 return ret_val;
2413
2414         data |= HV_KMRN_MDIO_SLOW;
2415
2416         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2417
2418         return ret_val;
2419 }
2420
2421 /**
2422  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2423  *  done after every PHY reset.
2424  **/
2425 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2426 {
2427         s32 ret_val = 0;
2428         u16 phy_data;
2429
2430         if (hw->mac.type != e1000_pchlan)
2431                 return 0;
2432
2433         /* Set MDIO slow mode before any other MDIO access */
2434         if (hw->phy.type == e1000_phy_82577) {
2435                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2436                 if (ret_val)
2437                         return ret_val;
2438         }
2439
2440         if (((hw->phy.type == e1000_phy_82577) &&
2441              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2442             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2443                 /* Disable generation of early preamble */
2444                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2445                 if (ret_val)
2446                         return ret_val;
2447
2448                 /* Preamble tuning for SSC */
2449                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2450                 if (ret_val)
2451                         return ret_val;
2452         }
2453
2454         if (hw->phy.type == e1000_phy_82578) {
2455                 /* Return registers to default by doing a soft reset then
2456                  * writing 0x3140 to the control register.
2457                  */
2458                 if (hw->phy.revision < 2) {
2459                         e1000e_phy_sw_reset(hw);
2460                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2461                 }
2462         }
2463
2464         /* Select page 0 */
2465         ret_val = hw->phy.ops.acquire(hw);
2466         if (ret_val)
2467                 return ret_val;
2468
2469         hw->phy.addr = 1;
2470         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2471         hw->phy.ops.release(hw);
2472         if (ret_val)
2473                 return ret_val;
2474
2475         /* Configure the K1 Si workaround during phy reset assuming there is
2476          * link so that it disables K1 if link is in 1Gbps.
2477          */
2478         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2479         if (ret_val)
2480                 return ret_val;
2481
2482         /* Workaround for link disconnects on a busy hub in half duplex */
2483         ret_val = hw->phy.ops.acquire(hw);
2484         if (ret_val)
2485                 return ret_val;
2486         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2487         if (ret_val)
2488                 goto release;
2489         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2490         if (ret_val)
2491                 goto release;
2492
2493         /* set MSE higher to enable link to stay up when noise is high */
2494         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2495 release:
2496         hw->phy.ops.release(hw);
2497
2498         return ret_val;
2499 }
2500
2501 /**
2502  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2503  *  @hw:   pointer to the HW structure
2504  **/
2505 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2506 {
2507         u32 mac_reg;
2508         u16 i, phy_reg = 0;
2509         s32 ret_val;
2510
2511         ret_val = hw->phy.ops.acquire(hw);
2512         if (ret_val)
2513                 return;
2514         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2515         if (ret_val)
2516                 goto release;
2517
2518         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2519         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2520                 mac_reg = er32(RAL(i));
2521                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2522                                            (u16)(mac_reg & 0xFFFF));
2523                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2524                                            (u16)((mac_reg >> 16) & 0xFFFF));
2525
2526                 mac_reg = er32(RAH(i));
2527                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2528                                            (u16)(mac_reg & 0xFFFF));
2529                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2530                                            (u16)((mac_reg & E1000_RAH_AV)
2531                                                  >> 16));
2532         }
2533
2534         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2535
2536 release:
2537         hw->phy.ops.release(hw);
2538 }
2539
2540 /**
2541  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2542  *  with 82579 PHY
2543  *  @hw: pointer to the HW structure
2544  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2545  **/
2546 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2547 {
2548         s32 ret_val = 0;
2549         u16 phy_reg, data;
2550         u32 mac_reg;
2551         u16 i;
2552
2553         if (hw->mac.type < e1000_pch2lan)
2554                 return 0;
2555
2556         /* disable Rx path while enabling/disabling workaround */
2557         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2558         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2559         if (ret_val)
2560                 return ret_val;
2561
2562         if (enable) {
2563                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2564                  * SHRAL/H) and initial CRC values to the MAC
2565                  */
2566                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2567                         u8 mac_addr[ETH_ALEN] = { 0 };
2568                         u32 addr_high, addr_low;
2569
2570                         addr_high = er32(RAH(i));
2571                         if (!(addr_high & E1000_RAH_AV))
2572                                 continue;
2573                         addr_low = er32(RAL(i));
2574                         mac_addr[0] = (addr_low & 0xFF);
2575                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2576                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2577                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2578                         mac_addr[4] = (addr_high & 0xFF);
2579                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2580
2581                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2582                 }
2583
2584                 /* Write Rx addresses to the PHY */
2585                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2586
2587                 /* Enable jumbo frame workaround in the MAC */
2588                 mac_reg = er32(FFLT_DBG);
2589                 mac_reg &= ~BIT(14);
2590                 mac_reg |= (7 << 15);
2591                 ew32(FFLT_DBG, mac_reg);
2592
2593                 mac_reg = er32(RCTL);
2594                 mac_reg |= E1000_RCTL_SECRC;
2595                 ew32(RCTL, mac_reg);
2596
2597                 ret_val = e1000e_read_kmrn_reg(hw,
2598                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2599                                                &data);
2600                 if (ret_val)
2601                         return ret_val;
2602                 ret_val = e1000e_write_kmrn_reg(hw,
2603                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2604                                                 data | BIT(0));
2605                 if (ret_val)
2606                         return ret_val;
2607                 ret_val = e1000e_read_kmrn_reg(hw,
2608                                                E1000_KMRNCTRLSTA_HD_CTRL,
2609                                                &data);
2610                 if (ret_val)
2611                         return ret_val;
2612                 data &= ~(0xF << 8);
2613                 data |= (0xB << 8);
2614                 ret_val = e1000e_write_kmrn_reg(hw,
2615                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2616                                                 data);
2617                 if (ret_val)
2618                         return ret_val;
2619
2620                 /* Enable jumbo frame workaround in the PHY */
2621                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2622                 data &= ~(0x7F << 5);
2623                 data |= (0x37 << 5);
2624                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2625                 if (ret_val)
2626                         return ret_val;
2627                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2628                 data &= ~BIT(13);
2629                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2630                 if (ret_val)
2631                         return ret_val;
2632                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2633                 data &= ~(0x3FF << 2);
2634                 data |= (E1000_TX_PTR_GAP << 2);
2635                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2636                 if (ret_val)
2637                         return ret_val;
2638                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2639                 if (ret_val)
2640                         return ret_val;
2641                 e1e_rphy(hw, HV_PM_CTRL, &data);
2642                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2643                 if (ret_val)
2644                         return ret_val;
2645         } else {
2646                 /* Write MAC register values back to h/w defaults */
2647                 mac_reg = er32(FFLT_DBG);
2648                 mac_reg &= ~(0xF << 14);
2649                 ew32(FFLT_DBG, mac_reg);
2650
2651                 mac_reg = er32(RCTL);
2652                 mac_reg &= ~E1000_RCTL_SECRC;
2653                 ew32(RCTL, mac_reg);
2654
2655                 ret_val = e1000e_read_kmrn_reg(hw,
2656                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2657                                                &data);
2658                 if (ret_val)
2659                         return ret_val;
2660                 ret_val = e1000e_write_kmrn_reg(hw,
2661                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2662                                                 data & ~BIT(0));
2663                 if (ret_val)
2664                         return ret_val;
2665                 ret_val = e1000e_read_kmrn_reg(hw,
2666                                                E1000_KMRNCTRLSTA_HD_CTRL,
2667                                                &data);
2668                 if (ret_val)
2669                         return ret_val;
2670                 data &= ~(0xF << 8);
2671                 data |= (0xB << 8);
2672                 ret_val = e1000e_write_kmrn_reg(hw,
2673                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2674                                                 data);
2675                 if (ret_val)
2676                         return ret_val;
2677
2678                 /* Write PHY register values back to h/w defaults */
2679                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2680                 data &= ~(0x7F << 5);
2681                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2682                 if (ret_val)
2683                         return ret_val;
2684                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2685                 data |= BIT(13);
2686                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2687                 if (ret_val)
2688                         return ret_val;
2689                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2690                 data &= ~(0x3FF << 2);
2691                 data |= (0x8 << 2);
2692                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2693                 if (ret_val)
2694                         return ret_val;
2695                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2696                 if (ret_val)
2697                         return ret_val;
2698                 e1e_rphy(hw, HV_PM_CTRL, &data);
2699                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2700                 if (ret_val)
2701                         return ret_val;
2702         }
2703
2704         /* re-enable Rx path after enabling/disabling workaround */
2705         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2706 }
2707
2708 /**
2709  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2710  *  done after every PHY reset.
2711  **/
2712 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2713 {
2714         s32 ret_val = 0;
2715
2716         if (hw->mac.type != e1000_pch2lan)
2717                 return 0;
2718
2719         /* Set MDIO slow mode before any other MDIO access */
2720         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2721         if (ret_val)
2722                 return ret_val;
2723
2724         ret_val = hw->phy.ops.acquire(hw);
2725         if (ret_val)
2726                 return ret_val;
2727         /* set MSE higher to enable link to stay up when noise is high */
2728         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2729         if (ret_val)
2730                 goto release;
2731         /* drop link after 5 times MSE threshold was reached */
2732         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2733 release:
2734         hw->phy.ops.release(hw);
2735
2736         return ret_val;
2737 }
2738
2739 /**
2740  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2741  *  @hw:   pointer to the HW structure
2742  *
2743  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2744  *  Disable K1 in 1000Mbps and 100Mbps
2745  **/
2746 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2747 {
2748         s32 ret_val = 0;
2749         u16 status_reg = 0;
2750
2751         if (hw->mac.type != e1000_pch2lan)
2752                 return 0;
2753
2754         /* Set K1 beacon duration based on 10Mbs speed */
2755         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2756         if (ret_val)
2757                 return ret_val;
2758
2759         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2760             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2761                 if (status_reg &
2762                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2763                         u16 pm_phy_reg;
2764
2765                         /* LV 1G/100 Packet drop issue wa  */
2766                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2767                         if (ret_val)
2768                                 return ret_val;
2769                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2770                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2771                         if (ret_val)
2772                                 return ret_val;
2773                 } else {
2774                         u32 mac_reg;
2775
2776                         mac_reg = er32(FEXTNVM4);
2777                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2778                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2779                         ew32(FEXTNVM4, mac_reg);
2780                 }
2781         }
2782
2783         return ret_val;
2784 }
2785
2786 /**
2787  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2788  *  @hw:   pointer to the HW structure
2789  *  @gate: boolean set to true to gate, false to ungate
2790  *
2791  *  Gate/ungate the automatic PHY configuration via hardware; perform
2792  *  the configuration via software instead.
2793  **/
2794 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2795 {
2796         u32 extcnf_ctrl;
2797
2798         if (hw->mac.type < e1000_pch2lan)
2799                 return;
2800
2801         extcnf_ctrl = er32(EXTCNF_CTRL);
2802
2803         if (gate)
2804                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2805         else
2806                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2807
2808         ew32(EXTCNF_CTRL, extcnf_ctrl);
2809 }
2810
2811 /**
2812  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2813  *  @hw: pointer to the HW structure
2814  *
2815  *  Check the appropriate indication the MAC has finished configuring the
2816  *  PHY after a software reset.
2817  **/
2818 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2819 {
2820         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2821
2822         /* Wait for basic configuration completes before proceeding */
2823         do {
2824                 data = er32(STATUS);
2825                 data &= E1000_STATUS_LAN_INIT_DONE;
2826                 usleep_range(100, 200);
2827         } while ((!data) && --loop);
2828
2829         /* If basic configuration is incomplete before the above loop
2830          * count reaches 0, loading the configuration from NVM will
2831          * leave the PHY in a bad state possibly resulting in no link.
2832          */
2833         if (loop == 0)
2834                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2835
2836         /* Clear the Init Done bit for the next init event */
2837         data = er32(STATUS);
2838         data &= ~E1000_STATUS_LAN_INIT_DONE;
2839         ew32(STATUS, data);
2840 }
2841
2842 /**
2843  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2844  *  @hw: pointer to the HW structure
2845  **/
2846 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2847 {
2848         s32 ret_val = 0;
2849         u16 reg;
2850
2851         if (hw->phy.ops.check_reset_block(hw))
2852                 return 0;
2853
2854         /* Allow time for h/w to get to quiescent state after reset */
2855         usleep_range(10000, 20000);
2856
2857         /* Perform any necessary post-reset workarounds */
2858         switch (hw->mac.type) {
2859         case e1000_pchlan:
2860                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2861                 if (ret_val)
2862                         return ret_val;
2863                 break;
2864         case e1000_pch2lan:
2865                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2866                 if (ret_val)
2867                         return ret_val;
2868                 break;
2869         default:
2870                 break;
2871         }
2872
2873         /* Clear the host wakeup bit after lcd reset */
2874         if (hw->mac.type >= e1000_pchlan) {
2875                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2876                 reg &= ~BM_WUC_HOST_WU_BIT;
2877                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2878         }
2879
2880         /* Configure the LCD with the extended configuration region in NVM */
2881         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2882         if (ret_val)
2883                 return ret_val;
2884
2885         /* Configure the LCD with the OEM bits in NVM */
2886         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2887
2888         if (hw->mac.type == e1000_pch2lan) {
2889                 /* Ungate automatic PHY configuration on non-managed 82579 */
2890                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2891                         usleep_range(10000, 20000);
2892                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2893                 }
2894
2895                 /* Set EEE LPI Update Timer to 200usec */
2896                 ret_val = hw->phy.ops.acquire(hw);
2897                 if (ret_val)
2898                         return ret_val;
2899                 ret_val = e1000_write_emi_reg_locked(hw,
2900                                                      I82579_LPI_UPDATE_TIMER,
2901                                                      0x1387);
2902                 hw->phy.ops.release(hw);
2903         }
2904
2905         return ret_val;
2906 }
2907
2908 /**
2909  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2910  *  @hw: pointer to the HW structure
2911  *
2912  *  Resets the PHY
2913  *  This is a function pointer entry point called by drivers
2914  *  or other shared routines.
2915  **/
2916 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2917 {
2918         s32 ret_val = 0;
2919
2920         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2921         if ((hw->mac.type == e1000_pch2lan) &&
2922             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2923                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2924
2925         ret_val = e1000e_phy_hw_reset_generic(hw);
2926         if (ret_val)
2927                 return ret_val;
2928
2929         return e1000_post_phy_reset_ich8lan(hw);
2930 }
2931
2932 /**
2933  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2934  *  @hw: pointer to the HW structure
2935  *  @active: true to enable LPLU, false to disable
2936  *
2937  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2938  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2939  *  the phy speed. This function will manually set the LPLU bit and restart
2940  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2941  *  since it configures the same bit.
2942  **/
2943 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2944 {
2945         s32 ret_val;
2946         u16 oem_reg;
2947
2948         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2949         if (ret_val)
2950                 return ret_val;
2951
2952         if (active)
2953                 oem_reg |= HV_OEM_BITS_LPLU;
2954         else
2955                 oem_reg &= ~HV_OEM_BITS_LPLU;
2956
2957         if (!hw->phy.ops.check_reset_block(hw))
2958                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2959
2960         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2961 }
2962
2963 /**
2964  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2965  *  @hw: pointer to the HW structure
2966  *  @active: true to enable LPLU, false to disable
2967  *
2968  *  Sets the LPLU D0 state according to the active flag.  When
2969  *  activating LPLU this function also disables smart speed
2970  *  and vice versa.  LPLU will not be activated unless the
2971  *  device autonegotiation advertisement meets standards of
2972  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2973  *  This is a function pointer entry point only called by
2974  *  PHY setup routines.
2975  **/
2976 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2977 {
2978         struct e1000_phy_info *phy = &hw->phy;
2979         u32 phy_ctrl;
2980         s32 ret_val = 0;
2981         u16 data;
2982
2983         if (phy->type == e1000_phy_ife)
2984                 return 0;
2985
2986         phy_ctrl = er32(PHY_CTRL);
2987
2988         if (active) {
2989                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2990                 ew32(PHY_CTRL, phy_ctrl);
2991
2992                 if (phy->type != e1000_phy_igp_3)
2993                         return 0;
2994
2995                 /* Call gig speed drop workaround on LPLU before accessing
2996                  * any PHY registers
2997                  */
2998                 if (hw->mac.type == e1000_ich8lan)
2999                         e1000e_gig_downshift_workaround_ich8lan(hw);
3000
3001                 /* When LPLU is enabled, we should disable SmartSpeed */
3002                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3003                 if (ret_val)
3004                         return ret_val;
3005                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3006                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3007                 if (ret_val)
3008                         return ret_val;
3009         } else {
3010                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3011                 ew32(PHY_CTRL, phy_ctrl);
3012
3013                 if (phy->type != e1000_phy_igp_3)
3014                         return 0;
3015
3016                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3017                  * during Dx states where the power conservation is most
3018                  * important.  During driver activity we should enable
3019                  * SmartSpeed, so performance is maintained.
3020                  */
3021                 if (phy->smart_speed == e1000_smart_speed_on) {
3022                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3023                                            &data);
3024                         if (ret_val)
3025                                 return ret_val;
3026
3027                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3028                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3029                                            data);
3030                         if (ret_val)
3031                                 return ret_val;
3032                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3033                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3034                                            &data);
3035                         if (ret_val)
3036                                 return ret_val;
3037
3038                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3039                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3040                                            data);
3041                         if (ret_val)
3042                                 return ret_val;
3043                 }
3044         }
3045
3046         return 0;
3047 }
3048
3049 /**
3050  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3051  *  @hw: pointer to the HW structure
3052  *  @active: true to enable LPLU, false to disable
3053  *
3054  *  Sets the LPLU D3 state according to the active flag.  When
3055  *  activating LPLU this function also disables smart speed
3056  *  and vice versa.  LPLU will not be activated unless the
3057  *  device autonegotiation advertisement meets standards of
3058  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3059  *  This is a function pointer entry point only called by
3060  *  PHY setup routines.
3061  **/
3062 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3063 {
3064         struct e1000_phy_info *phy = &hw->phy;
3065         u32 phy_ctrl;
3066         s32 ret_val = 0;
3067         u16 data;
3068
3069         phy_ctrl = er32(PHY_CTRL);
3070
3071         if (!active) {
3072                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3073                 ew32(PHY_CTRL, phy_ctrl);
3074
3075                 if (phy->type != e1000_phy_igp_3)
3076                         return 0;
3077
3078                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3079                  * during Dx states where the power conservation is most
3080                  * important.  During driver activity we should enable
3081                  * SmartSpeed, so performance is maintained.
3082                  */
3083                 if (phy->smart_speed == e1000_smart_speed_on) {
3084                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3085                                            &data);
3086                         if (ret_val)
3087                                 return ret_val;
3088
3089                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3090                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3091                                            data);
3092                         if (ret_val)
3093                                 return ret_val;
3094                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3095                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3096                                            &data);
3097                         if (ret_val)
3098                                 return ret_val;
3099
3100                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3101                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3102                                            data);
3103                         if (ret_val)
3104                                 return ret_val;
3105                 }
3106         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3107                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3108                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3109                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3110                 ew32(PHY_CTRL, phy_ctrl);
3111
3112                 if (phy->type != e1000_phy_igp_3)
3113                         return 0;
3114
3115                 /* Call gig speed drop workaround on LPLU before accessing
3116                  * any PHY registers
3117                  */
3118                 if (hw->mac.type == e1000_ich8lan)
3119                         e1000e_gig_downshift_workaround_ich8lan(hw);
3120
3121                 /* When LPLU is enabled, we should disable SmartSpeed */
3122                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3123                 if (ret_val)
3124                         return ret_val;
3125
3126                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3127                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3128         }
3129
3130         return ret_val;
3131 }
3132
3133 /**
3134  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3135  *  @hw: pointer to the HW structure
3136  *  @bank:  pointer to the variable that returns the active bank
3137  *
3138  *  Reads signature byte from the NVM using the flash access registers.
3139  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3140  **/
3141 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3142 {
3143         u32 eecd;
3144         struct e1000_nvm_info *nvm = &hw->nvm;
3145         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3146         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3147         u32 nvm_dword = 0;
3148         u8 sig_byte = 0;
3149         s32 ret_val;
3150
3151         switch (hw->mac.type) {
3152         case e1000_pch_spt:
3153                 bank1_offset = nvm->flash_bank_size;
3154                 act_offset = E1000_ICH_NVM_SIG_WORD;
3155
3156                 /* set bank to 0 in case flash read fails */
3157                 *bank = 0;
3158
3159                 /* Check bank 0 */
3160                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3161                                                          &nvm_dword);
3162                 if (ret_val)
3163                         return ret_val;
3164                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3165                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3166                     E1000_ICH_NVM_SIG_VALUE) {
3167                         *bank = 0;
3168                         return 0;
3169                 }
3170
3171                 /* Check bank 1 */
3172                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3173                                                          bank1_offset,
3174                                                          &nvm_dword);
3175                 if (ret_val)
3176                         return ret_val;
3177                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3178                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3179                     E1000_ICH_NVM_SIG_VALUE) {
3180                         *bank = 1;
3181                         return 0;
3182                 }
3183
3184                 e_dbg("ERROR: No valid NVM bank present\n");
3185                 return -E1000_ERR_NVM;
3186         case e1000_ich8lan:
3187         case e1000_ich9lan:
3188                 eecd = er32(EECD);
3189                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3190                     E1000_EECD_SEC1VAL_VALID_MASK) {
3191                         if (eecd & E1000_EECD_SEC1VAL)
3192                                 *bank = 1;
3193                         else
3194                                 *bank = 0;
3195
3196                         return 0;
3197                 }
3198                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3199                 /* fall-thru */
3200         default:
3201                 /* set bank to 0 in case flash read fails */
3202                 *bank = 0;
3203
3204                 /* Check bank 0 */
3205                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3206                                                         &sig_byte);
3207                 if (ret_val)
3208                         return ret_val;
3209                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3210                     E1000_ICH_NVM_SIG_VALUE) {
3211                         *bank = 0;
3212                         return 0;
3213                 }
3214
3215                 /* Check bank 1 */
3216                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3217                                                         bank1_offset,
3218                                                         &sig_byte);
3219                 if (ret_val)
3220                         return ret_val;
3221                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3222                     E1000_ICH_NVM_SIG_VALUE) {
3223                         *bank = 1;
3224                         return 0;
3225                 }
3226
3227                 e_dbg("ERROR: No valid NVM bank present\n");
3228                 return -E1000_ERR_NVM;
3229         }
3230 }
3231
3232 /**
3233  *  e1000_read_nvm_spt - NVM access for SPT
3234  *  @hw: pointer to the HW structure
3235  *  @offset: The offset (in bytes) of the word(s) to read.
3236  *  @words: Size of data to read in words.
3237  *  @data: pointer to the word(s) to read at offset.
3238  *
3239  *  Reads a word(s) from the NVM
3240  **/
3241 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3242                               u16 *data)
3243 {
3244         struct e1000_nvm_info *nvm = &hw->nvm;
3245         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3246         u32 act_offset;
3247         s32 ret_val = 0;
3248         u32 bank = 0;
3249         u32 dword = 0;
3250         u16 offset_to_read;
3251         u16 i;
3252
3253         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3254             (words == 0)) {
3255                 e_dbg("nvm parameter(s) out of bounds\n");
3256                 ret_val = -E1000_ERR_NVM;
3257                 goto out;
3258         }
3259
3260         nvm->ops.acquire(hw);
3261
3262         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3263         if (ret_val) {
3264                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3265                 bank = 0;
3266         }
3267
3268         act_offset = (bank) ? nvm->flash_bank_size : 0;
3269         act_offset += offset;
3270
3271         ret_val = 0;
3272
3273         for (i = 0; i < words; i += 2) {
3274                 if (words - i == 1) {
3275                         if (dev_spec->shadow_ram[offset + i].modified) {
3276                                 data[i] =
3277                                     dev_spec->shadow_ram[offset + i].value;
3278                         } else {
3279                                 offset_to_read = act_offset + i -
3280                                     ((act_offset + i) % 2);
3281                                 ret_val =
3282                                   e1000_read_flash_dword_ich8lan(hw,
3283                                                                  offset_to_read,
3284                                                                  &dword);
3285                                 if (ret_val)
3286                                         break;
3287                                 if ((act_offset + i) % 2 == 0)
3288                                         data[i] = (u16)(dword & 0xFFFF);
3289                                 else
3290                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3291                         }
3292                 } else {
3293                         offset_to_read = act_offset + i;
3294                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3295                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3296                                 ret_val =
3297                                   e1000_read_flash_dword_ich8lan(hw,
3298                                                                  offset_to_read,
3299                                                                  &dword);
3300                                 if (ret_val)
3301                                         break;
3302                         }
3303                         if (dev_spec->shadow_ram[offset + i].modified)
3304                                 data[i] =
3305                                     dev_spec->shadow_ram[offset + i].value;
3306                         else
3307                                 data[i] = (u16)(dword & 0xFFFF);
3308                         if (dev_spec->shadow_ram[offset + i].modified)
3309                                 data[i + 1] =
3310                                     dev_spec->shadow_ram[offset + i + 1].value;
3311                         else
3312                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3313                 }
3314         }
3315
3316         nvm->ops.release(hw);
3317
3318 out:
3319         if (ret_val)
3320                 e_dbg("NVM read error: %d\n", ret_val);
3321
3322         return ret_val;
3323 }
3324
3325 /**
3326  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3327  *  @hw: pointer to the HW structure
3328  *  @offset: The offset (in bytes) of the word(s) to read.
3329  *  @words: Size of data to read in words
3330  *  @data: Pointer to the word(s) to read at offset.
3331  *
3332  *  Reads a word(s) from the NVM using the flash access registers.
3333  **/
3334 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3335                                   u16 *data)
3336 {
3337         struct e1000_nvm_info *nvm = &hw->nvm;
3338         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3339         u32 act_offset;
3340         s32 ret_val = 0;
3341         u32 bank = 0;
3342         u16 i, word;
3343
3344         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3345             (words == 0)) {
3346                 e_dbg("nvm parameter(s) out of bounds\n");
3347                 ret_val = -E1000_ERR_NVM;
3348                 goto out;
3349         }
3350
3351         nvm->ops.acquire(hw);
3352
3353         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3354         if (ret_val) {
3355                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3356                 bank = 0;
3357         }
3358
3359         act_offset = (bank) ? nvm->flash_bank_size : 0;
3360         act_offset += offset;
3361
3362         ret_val = 0;
3363         for (i = 0; i < words; i++) {
3364                 if (dev_spec->shadow_ram[offset + i].modified) {
3365                         data[i] = dev_spec->shadow_ram[offset + i].value;
3366                 } else {
3367                         ret_val = e1000_read_flash_word_ich8lan(hw,
3368                                                                 act_offset + i,
3369                                                                 &word);
3370                         if (ret_val)
3371                                 break;
3372                         data[i] = word;
3373                 }
3374         }
3375
3376         nvm->ops.release(hw);
3377
3378 out:
3379         if (ret_val)
3380                 e_dbg("NVM read error: %d\n", ret_val);
3381
3382         return ret_val;
3383 }
3384
3385 /**
3386  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3387  *  @hw: pointer to the HW structure
3388  *
3389  *  This function does initial flash setup so that a new read/write/erase cycle
3390  *  can be started.
3391  **/
3392 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3393 {
3394         union ich8_hws_flash_status hsfsts;
3395         s32 ret_val = -E1000_ERR_NVM;
3396
3397         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3398
3399         /* Check if the flash descriptor is valid */
3400         if (!hsfsts.hsf_status.fldesvalid) {
3401                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3402                 return -E1000_ERR_NVM;
3403         }
3404
3405         /* Clear FCERR and DAEL in hw status by writing 1 */
3406         hsfsts.hsf_status.flcerr = 1;
3407         hsfsts.hsf_status.dael = 1;
3408         if (hw->mac.type == e1000_pch_spt)
3409                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3410         else
3411                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3412
3413         /* Either we should have a hardware SPI cycle in progress
3414          * bit to check against, in order to start a new cycle or
3415          * FDONE bit should be changed in the hardware so that it
3416          * is 1 after hardware reset, which can then be used as an
3417          * indication whether a cycle is in progress or has been
3418          * completed.
3419          */
3420
3421         if (!hsfsts.hsf_status.flcinprog) {
3422                 /* There is no cycle running at present,
3423                  * so we can start a cycle.
3424                  * Begin by setting Flash Cycle Done.
3425                  */
3426                 hsfsts.hsf_status.flcdone = 1;
3427                 if (hw->mac.type == e1000_pch_spt)
3428                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3429                 else
3430                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3431                 ret_val = 0;
3432         } else {
3433                 s32 i;
3434
3435                 /* Otherwise poll for sometime so the current
3436                  * cycle has a chance to end before giving up.
3437                  */
3438                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3439                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3440                         if (!hsfsts.hsf_status.flcinprog) {
3441                                 ret_val = 0;
3442                                 break;
3443                         }
3444                         udelay(1);
3445                 }
3446                 if (!ret_val) {
3447                         /* Successful in waiting for previous cycle to timeout,
3448                          * now set the Flash Cycle Done.
3449                          */
3450                         hsfsts.hsf_status.flcdone = 1;
3451                         if (hw->mac.type == e1000_pch_spt)
3452                                 ew32flash(ICH_FLASH_HSFSTS,
3453                                           hsfsts.regval & 0xFFFF);
3454                         else
3455                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3456                 } else {
3457                         e_dbg("Flash controller busy, cannot get access\n");
3458                 }
3459         }
3460
3461         return ret_val;
3462 }
3463
3464 /**
3465  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3466  *  @hw: pointer to the HW structure
3467  *  @timeout: maximum time to wait for completion
3468  *
3469  *  This function starts a flash cycle and waits for its completion.
3470  **/
3471 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3472 {
3473         union ich8_hws_flash_ctrl hsflctl;
3474         union ich8_hws_flash_status hsfsts;
3475         u32 i = 0;
3476
3477         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3478         if (hw->mac.type == e1000_pch_spt)
3479                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3480         else
3481                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3482         hsflctl.hsf_ctrl.flcgo = 1;
3483
3484         if (hw->mac.type == e1000_pch_spt)
3485                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3486         else
3487                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3488
3489         /* wait till FDONE bit is set to 1 */
3490         do {
3491                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3492                 if (hsfsts.hsf_status.flcdone)
3493                         break;
3494                 udelay(1);
3495         } while (i++ < timeout);
3496
3497         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3498                 return 0;
3499
3500         return -E1000_ERR_NVM;
3501 }
3502
3503 /**
3504  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3505  *  @hw: pointer to the HW structure
3506  *  @offset: offset to data location
3507  *  @data: pointer to the location for storing the data
3508  *
3509  *  Reads the flash dword at offset into data.  Offset is converted
3510  *  to bytes before read.
3511  **/
3512 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3513                                           u32 *data)
3514 {
3515         /* Must convert word offset into bytes. */
3516         offset <<= 1;
3517         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3518 }
3519
3520 /**
3521  *  e1000_read_flash_word_ich8lan - Read word from flash
3522  *  @hw: pointer to the HW structure
3523  *  @offset: offset to data location
3524  *  @data: pointer to the location for storing the data
3525  *
3526  *  Reads the flash word at offset into data.  Offset is converted
3527  *  to bytes before read.
3528  **/
3529 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3530                                          u16 *data)
3531 {
3532         /* Must convert offset into bytes. */
3533         offset <<= 1;
3534
3535         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3536 }
3537
3538 /**
3539  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3540  *  @hw: pointer to the HW structure
3541  *  @offset: The offset of the byte to read.
3542  *  @data: Pointer to a byte to store the value read.
3543  *
3544  *  Reads a single byte from the NVM using the flash access registers.
3545  **/
3546 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3547                                          u8 *data)
3548 {
3549         s32 ret_val;
3550         u16 word = 0;
3551
3552         /* In SPT, only 32 bits access is supported,
3553          * so this function should not be called.
3554          */
3555         if (hw->mac.type == e1000_pch_spt)
3556                 return -E1000_ERR_NVM;
3557         else
3558                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3559
3560         if (ret_val)
3561                 return ret_val;
3562
3563         *data = (u8)word;
3564
3565         return 0;
3566 }
3567
3568 /**
3569  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3570  *  @hw: pointer to the HW structure
3571  *  @offset: The offset (in bytes) of the byte or word to read.
3572  *  @size: Size of data to read, 1=byte 2=word
3573  *  @data: Pointer to the word to store the value read.
3574  *
3575  *  Reads a byte or word from the NVM using the flash access registers.
3576  **/
3577 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3578                                          u8 size, u16 *data)
3579 {
3580         union ich8_hws_flash_status hsfsts;
3581         union ich8_hws_flash_ctrl hsflctl;
3582         u32 flash_linear_addr;
3583         u32 flash_data = 0;
3584         s32 ret_val = -E1000_ERR_NVM;
3585         u8 count = 0;
3586
3587         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3588                 return -E1000_ERR_NVM;
3589
3590         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3591                              hw->nvm.flash_base_addr);
3592
3593         do {
3594                 udelay(1);
3595                 /* Steps */
3596                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3597                 if (ret_val)
3598                         break;
3599
3600                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3601                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3602                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3603                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3604                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3605
3606                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3607
3608                 ret_val =
3609                     e1000_flash_cycle_ich8lan(hw,
3610                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3611
3612                 /* Check if FCERR is set to 1, if set to 1, clear it
3613                  * and try the whole sequence a few more times, else
3614                  * read in (shift in) the Flash Data0, the order is
3615                  * least significant byte first msb to lsb
3616                  */
3617                 if (!ret_val) {
3618                         flash_data = er32flash(ICH_FLASH_FDATA0);
3619                         if (size == 1)
3620                                 *data = (u8)(flash_data & 0x000000FF);
3621                         else if (size == 2)
3622                                 *data = (u16)(flash_data & 0x0000FFFF);
3623                         break;
3624                 } else {
3625                         /* If we've gotten here, then things are probably
3626                          * completely hosed, but if the error condition is
3627                          * detected, it won't hurt to give it another try...
3628                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3629                          */
3630                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3631                         if (hsfsts.hsf_status.flcerr) {
3632                                 /* Repeat for some time before giving up. */
3633                                 continue;
3634                         } else if (!hsfsts.hsf_status.flcdone) {
3635                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3636                                 break;
3637                         }
3638                 }
3639         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3640
3641         return ret_val;
3642 }
3643
3644 /**
3645  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3646  *  @hw: pointer to the HW structure
3647  *  @offset: The offset (in bytes) of the dword to read.
3648  *  @data: Pointer to the dword to store the value read.
3649  *
3650  *  Reads a byte or word from the NVM using the flash access registers.
3651  **/
3652
3653 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3654                                            u32 *data)
3655 {
3656         union ich8_hws_flash_status hsfsts;
3657         union ich8_hws_flash_ctrl hsflctl;
3658         u32 flash_linear_addr;
3659         s32 ret_val = -E1000_ERR_NVM;
3660         u8 count = 0;
3661
3662         if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3663             hw->mac.type != e1000_pch_spt)
3664                 return -E1000_ERR_NVM;
3665         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3666                              hw->nvm.flash_base_addr);
3667
3668         do {
3669                 udelay(1);
3670                 /* Steps */
3671                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3672                 if (ret_val)
3673                         break;
3674                 /* In SPT, This register is in Lan memory space, not flash.
3675                  * Therefore, only 32 bit access is supported
3676                  */
3677                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3678
3679                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3680                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3681                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3682                 /* In SPT, This register is in Lan memory space, not flash.
3683                  * Therefore, only 32 bit access is supported
3684                  */
3685                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3686                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3687
3688                 ret_val =
3689                    e1000_flash_cycle_ich8lan(hw,
3690                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3691
3692                 /* Check if FCERR is set to 1, if set to 1, clear it
3693                  * and try the whole sequence a few more times, else
3694                  * read in (shift in) the Flash Data0, the order is
3695                  * least significant byte first msb to lsb
3696                  */
3697                 if (!ret_val) {
3698                         *data = er32flash(ICH_FLASH_FDATA0);
3699                         break;
3700                 } else {
3701                         /* If we've gotten here, then things are probably
3702                          * completely hosed, but if the error condition is
3703                          * detected, it won't hurt to give it another try...
3704                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3705                          */
3706                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3707                         if (hsfsts.hsf_status.flcerr) {
3708                                 /* Repeat for some time before giving up. */
3709                                 continue;
3710                         } else if (!hsfsts.hsf_status.flcdone) {
3711                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3712                                 break;
3713                         }
3714                 }
3715         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3716
3717         return ret_val;
3718 }
3719
3720 /**
3721  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3722  *  @hw: pointer to the HW structure
3723  *  @offset: The offset (in bytes) of the word(s) to write.
3724  *  @words: Size of data to write in words
3725  *  @data: Pointer to the word(s) to write at offset.
3726  *
3727  *  Writes a byte or word to the NVM using the flash access registers.
3728  **/
3729 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3730                                    u16 *data)
3731 {
3732         struct e1000_nvm_info *nvm = &hw->nvm;
3733         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3734         u16 i;
3735
3736         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3737             (words == 0)) {
3738                 e_dbg("nvm parameter(s) out of bounds\n");
3739                 return -E1000_ERR_NVM;
3740         }
3741
3742         nvm->ops.acquire(hw);
3743
3744         for (i = 0; i < words; i++) {
3745                 dev_spec->shadow_ram[offset + i].modified = true;
3746                 dev_spec->shadow_ram[offset + i].value = data[i];
3747         }
3748
3749         nvm->ops.release(hw);
3750
3751         return 0;
3752 }
3753
3754 /**
3755  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3756  *  @hw: pointer to the HW structure
3757  *
3758  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3759  *  which writes the checksum to the shadow ram.  The changes in the shadow
3760  *  ram are then committed to the EEPROM by processing each bank at a time
3761  *  checking for the modified bit and writing only the pending changes.
3762  *  After a successful commit, the shadow ram is cleared and is ready for
3763  *  future writes.
3764  **/
3765 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3766 {
3767         struct e1000_nvm_info *nvm = &hw->nvm;
3768         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3769         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3770         s32 ret_val;
3771         u32 dword = 0;
3772
3773         ret_val = e1000e_update_nvm_checksum_generic(hw);
3774         if (ret_val)
3775                 goto out;
3776
3777         if (nvm->type != e1000_nvm_flash_sw)
3778                 goto out;
3779
3780         nvm->ops.acquire(hw);
3781
3782         /* We're writing to the opposite bank so if we're on bank 1,
3783          * write to bank 0 etc.  We also need to erase the segment that
3784          * is going to be written
3785          */
3786         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3787         if (ret_val) {
3788                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3789                 bank = 0;
3790         }
3791
3792         if (bank == 0) {
3793                 new_bank_offset = nvm->flash_bank_size;
3794                 old_bank_offset = 0;
3795                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3796                 if (ret_val)
3797                         goto release;
3798         } else {
3799                 old_bank_offset = nvm->flash_bank_size;
3800                 new_bank_offset = 0;
3801                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3802                 if (ret_val)
3803                         goto release;
3804         }
3805         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3806                 /* Determine whether to write the value stored
3807                  * in the other NVM bank or a modified value stored
3808                  * in the shadow RAM
3809                  */
3810                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3811                                                          i + old_bank_offset,
3812                                                          &dword);
3813
3814                 if (dev_spec->shadow_ram[i].modified) {
3815                         dword &= 0xffff0000;
3816                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3817                 }
3818                 if (dev_spec->shadow_ram[i + 1].modified) {
3819                         dword &= 0x0000ffff;
3820                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3821                                   << 16);
3822                 }
3823                 if (ret_val)
3824                         break;
3825
3826                 /* If the word is 0x13, then make sure the signature bits
3827                  * (15:14) are 11b until the commit has completed.
3828                  * This will allow us to write 10b which indicates the
3829                  * signature is valid.  We want to do this after the write
3830                  * has completed so that we don't mark the segment valid
3831                  * while the write is still in progress
3832                  */
3833                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3834                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3835
3836                 /* Convert offset to bytes. */
3837                 act_offset = (i + new_bank_offset) << 1;
3838
3839                 usleep_range(100, 200);
3840
3841                 /* Write the data to the new bank. Offset in words */
3842                 act_offset = i + new_bank_offset;
3843                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3844                                                                 dword);
3845                 if (ret_val)
3846                         break;
3847         }
3848
3849         /* Don't bother writing the segment valid bits if sector
3850          * programming failed.
3851          */
3852         if (ret_val) {
3853                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3854                 e_dbg("Flash commit failed.\n");
3855                 goto release;
3856         }
3857
3858         /* Finally validate the new segment by setting bit 15:14
3859          * to 10b in word 0x13 , this can be done without an
3860          * erase as well since these bits are 11 to start with
3861          * and we need to change bit 14 to 0b
3862          */
3863         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3864
3865         /*offset in words but we read dword */
3866         --act_offset;
3867         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3868
3869         if (ret_val)
3870                 goto release;
3871
3872         dword &= 0xBFFFFFFF;
3873         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3874
3875         if (ret_val)
3876                 goto release;
3877
3878         /* And invalidate the previously valid segment by setting
3879          * its signature word (0x13) high_byte to 0b. This can be
3880          * done without an erase because flash erase sets all bits
3881          * to 1's. We can write 1's to 0's without an erase
3882          */
3883         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3884
3885         /* offset in words but we read dword */
3886         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3887         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3888
3889         if (ret_val)
3890                 goto release;
3891
3892         dword &= 0x00FFFFFF;
3893         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3894
3895         if (ret_val)
3896                 goto release;
3897
3898         /* Great!  Everything worked, we can now clear the cached entries. */
3899         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3900                 dev_spec->shadow_ram[i].modified = false;
3901                 dev_spec->shadow_ram[i].value = 0xFFFF;
3902         }
3903
3904 release:
3905         nvm->ops.release(hw);
3906
3907         /* Reload the EEPROM, or else modifications will not appear
3908          * until after the next adapter reset.
3909          */
3910         if (!ret_val) {
3911                 nvm->ops.reload(hw);
3912                 usleep_range(10000, 20000);
3913         }
3914
3915 out:
3916         if (ret_val)
3917                 e_dbg("NVM update error: %d\n", ret_val);
3918
3919         return ret_val;
3920 }
3921
3922 /**
3923  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3924  *  @hw: pointer to the HW structure
3925  *
3926  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3927  *  which writes the checksum to the shadow ram.  The changes in the shadow
3928  *  ram are then committed to the EEPROM by processing each bank at a time
3929  *  checking for the modified bit and writing only the pending changes.
3930  *  After a successful commit, the shadow ram is cleared and is ready for
3931  *  future writes.
3932  **/
3933 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3934 {
3935         struct e1000_nvm_info *nvm = &hw->nvm;
3936         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3937         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3938         s32 ret_val;
3939         u16 data = 0;
3940
3941         ret_val = e1000e_update_nvm_checksum_generic(hw);
3942         if (ret_val)
3943                 goto out;
3944
3945         if (nvm->type != e1000_nvm_flash_sw)
3946                 goto out;
3947
3948         nvm->ops.acquire(hw);
3949
3950         /* We're writing to the opposite bank so if we're on bank 1,
3951          * write to bank 0 etc.  We also need to erase the segment that
3952          * is going to be written
3953          */
3954         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3955         if (ret_val) {
3956                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3957                 bank = 0;
3958         }
3959
3960         if (bank == 0) {
3961                 new_bank_offset = nvm->flash_bank_size;
3962                 old_bank_offset = 0;
3963                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3964                 if (ret_val)
3965                         goto release;
3966         } else {
3967                 old_bank_offset = nvm->flash_bank_size;
3968                 new_bank_offset = 0;
3969                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3970                 if (ret_val)
3971                         goto release;
3972         }
3973         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3974                 if (dev_spec->shadow_ram[i].modified) {
3975                         data = dev_spec->shadow_ram[i].value;
3976                 } else {
3977                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3978                                                                 old_bank_offset,
3979                                                                 &data);
3980                         if (ret_val)
3981                                 break;
3982                 }
3983
3984                 /* If the word is 0x13, then make sure the signature bits
3985                  * (15:14) are 11b until the commit has completed.
3986                  * This will allow us to write 10b which indicates the
3987                  * signature is valid.  We want to do this after the write
3988                  * has completed so that we don't mark the segment valid
3989                  * while the write is still in progress
3990                  */
3991                 if (i == E1000_ICH_NVM_SIG_WORD)
3992                         data |= E1000_ICH_NVM_SIG_MASK;
3993
3994                 /* Convert offset to bytes. */
3995                 act_offset = (i + new_bank_offset) << 1;
3996
3997                 usleep_range(100, 200);
3998                 /* Write the bytes to the new bank. */
3999                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4000                                                                act_offset,
4001                                                                (u8)data);
4002                 if (ret_val)
4003                         break;
4004
4005                 usleep_range(100, 200);
4006                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4007                                                                act_offset + 1,
4008                                                                (u8)(data >> 8));
4009                 if (ret_val)
4010                         break;
4011         }
4012
4013         /* Don't bother writing the segment valid bits if sector
4014          * programming failed.
4015          */
4016         if (ret_val) {
4017                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4018                 e_dbg("Flash commit failed.\n");
4019                 goto release;
4020         }
4021
4022         /* Finally validate the new segment by setting bit 15:14
4023          * to 10b in word 0x13 , this can be done without an
4024          * erase as well since these bits are 11 to start with
4025          * and we need to change bit 14 to 0b
4026          */
4027         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4028         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4029         if (ret_val)
4030                 goto release;
4031
4032         data &= 0xBFFF;
4033         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4034                                                        act_offset * 2 + 1,
4035                                                        (u8)(data >> 8));
4036         if (ret_val)
4037                 goto release;
4038
4039         /* And invalidate the previously valid segment by setting
4040          * its signature word (0x13) high_byte to 0b. This can be
4041          * done without an erase because flash erase sets all bits
4042          * to 1's. We can write 1's to 0's without an erase
4043          */
4044         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4045         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4046         if (ret_val)
4047                 goto release;
4048
4049         /* Great!  Everything worked, we can now clear the cached entries. */
4050         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4051                 dev_spec->shadow_ram[i].modified = false;
4052                 dev_spec->shadow_ram[i].value = 0xFFFF;
4053         }
4054
4055 release:
4056         nvm->ops.release(hw);
4057
4058         /* Reload the EEPROM, or else modifications will not appear
4059          * until after the next adapter reset.
4060          */
4061         if (!ret_val) {
4062                 nvm->ops.reload(hw);
4063                 usleep_range(10000, 20000);
4064         }
4065
4066 out:
4067         if (ret_val)
4068                 e_dbg("NVM update error: %d\n", ret_val);
4069
4070         return ret_val;
4071 }
4072
4073 /**
4074  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4075  *  @hw: pointer to the HW structure
4076  *
4077  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4078  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4079  *  calculated, in which case we need to calculate the checksum and set bit 6.
4080  **/
4081 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4082 {
4083         s32 ret_val;
4084         u16 data;
4085         u16 word;
4086         u16 valid_csum_mask;
4087
4088         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4089          * the checksum needs to be fixed.  This bit is an indication that
4090          * the NVM was prepared by OEM software and did not calculate
4091          * the checksum...a likely scenario.
4092          */
4093         switch (hw->mac.type) {
4094         case e1000_pch_lpt:
4095         case e1000_pch_spt:
4096                 word = NVM_COMPAT;
4097                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4098                 break;
4099         default:
4100                 word = NVM_FUTURE_INIT_WORD1;
4101                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4102                 break;
4103         }
4104
4105         ret_val = e1000_read_nvm(hw, word, 1, &data);
4106         if (ret_val)
4107                 return ret_val;
4108
4109         if (!(data & valid_csum_mask)) {
4110                 data |= valid_csum_mask;
4111                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4112                 if (ret_val)
4113                         return ret_val;
4114                 ret_val = e1000e_update_nvm_checksum(hw);
4115                 if (ret_val)
4116                         return ret_val;
4117         }
4118
4119         return e1000e_validate_nvm_checksum_generic(hw);
4120 }
4121
4122 /**
4123  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4124  *  @hw: pointer to the HW structure
4125  *
4126  *  To prevent malicious write/erase of the NVM, set it to be read-only
4127  *  so that the hardware ignores all write/erase cycles of the NVM via
4128  *  the flash control registers.  The shadow-ram copy of the NVM will
4129  *  still be updated, however any updates to this copy will not stick
4130  *  across driver reloads.
4131  **/
4132 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4133 {
4134         struct e1000_nvm_info *nvm = &hw->nvm;
4135         union ich8_flash_protected_range pr0;
4136         union ich8_hws_flash_status hsfsts;
4137         u32 gfpreg;
4138
4139         nvm->ops.acquire(hw);
4140
4141         gfpreg = er32flash(ICH_FLASH_GFPREG);
4142
4143         /* Write-protect GbE Sector of NVM */
4144         pr0.regval = er32flash(ICH_FLASH_PR0);
4145         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4146         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4147         pr0.range.wpe = true;
4148         ew32flash(ICH_FLASH_PR0, pr0.regval);
4149
4150         /* Lock down a subset of GbE Flash Control Registers, e.g.
4151          * PR0 to prevent the write-protection from being lifted.
4152          * Once FLOCKDN is set, the registers protected by it cannot
4153          * be written until FLOCKDN is cleared by a hardware reset.
4154          */
4155         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4156         hsfsts.hsf_status.flockdn = true;
4157         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4158
4159         nvm->ops.release(hw);
4160 }
4161
4162 /**
4163  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4164  *  @hw: pointer to the HW structure
4165  *  @offset: The offset (in bytes) of the byte/word to read.
4166  *  @size: Size of data to read, 1=byte 2=word
4167  *  @data: The byte(s) to write to the NVM.
4168  *
4169  *  Writes one/two bytes to the NVM using the flash access registers.
4170  **/
4171 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4172                                           u8 size, u16 data)
4173 {
4174         union ich8_hws_flash_status hsfsts;
4175         union ich8_hws_flash_ctrl hsflctl;
4176         u32 flash_linear_addr;
4177         u32 flash_data = 0;
4178         s32 ret_val;
4179         u8 count = 0;
4180
4181         if (hw->mac.type == e1000_pch_spt) {
4182                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4183                         return -E1000_ERR_NVM;
4184         } else {
4185                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4186                         return -E1000_ERR_NVM;
4187         }
4188
4189         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4190                              hw->nvm.flash_base_addr);
4191
4192         do {
4193                 udelay(1);
4194                 /* Steps */
4195                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4196                 if (ret_val)
4197                         break;
4198                 /* In SPT, This register is in Lan memory space, not
4199                  * flash.  Therefore, only 32 bit access is supported
4200                  */
4201                 if (hw->mac.type == e1000_pch_spt)
4202                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4203                 else
4204                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4205
4206                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4207                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4208                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4209                 /* In SPT, This register is in Lan memory space,
4210                  * not flash.  Therefore, only 32 bit access is
4211                  * supported
4212                  */
4213                 if (hw->mac.type == e1000_pch_spt)
4214                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4215                 else
4216                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4217
4218                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4219
4220                 if (size == 1)
4221                         flash_data = (u32)data & 0x00FF;
4222                 else
4223                         flash_data = (u32)data;
4224
4225                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4226
4227                 /* check if FCERR is set to 1 , if set to 1, clear it
4228                  * and try the whole sequence a few more times else done
4229                  */
4230                 ret_val =
4231                     e1000_flash_cycle_ich8lan(hw,
4232                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4233                 if (!ret_val)
4234                         break;
4235
4236                 /* If we're here, then things are most likely
4237                  * completely hosed, but if the error condition
4238                  * is detected, it won't hurt to give it another
4239                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4240                  */
4241                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4242                 if (hsfsts.hsf_status.flcerr)
4243                         /* Repeat for some time before giving up. */
4244                         continue;
4245                 if (!hsfsts.hsf_status.flcdone) {
4246                         e_dbg("Timeout error - flash cycle did not complete.\n");
4247                         break;
4248                 }
4249         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4250
4251         return ret_val;
4252 }
4253
4254 /**
4255 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4256 *  @hw: pointer to the HW structure
4257 *  @offset: The offset (in bytes) of the dwords to read.
4258 *  @data: The 4 bytes to write to the NVM.
4259 *
4260 *  Writes one/two/four bytes to the NVM using the flash access registers.
4261 **/
4262 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4263                                             u32 data)
4264 {
4265         union ich8_hws_flash_status hsfsts;
4266         union ich8_hws_flash_ctrl hsflctl;
4267         u32 flash_linear_addr;
4268         s32 ret_val;
4269         u8 count = 0;
4270
4271         if (hw->mac.type == e1000_pch_spt) {
4272                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4273                         return -E1000_ERR_NVM;
4274         }
4275         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4276                              hw->nvm.flash_base_addr);
4277         do {
4278                 udelay(1);
4279                 /* Steps */
4280                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4281                 if (ret_val)
4282                         break;
4283
4284                 /* In SPT, This register is in Lan memory space, not
4285                  * flash.  Therefore, only 32 bit access is supported
4286                  */
4287                 if (hw->mac.type == e1000_pch_spt)
4288                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4289                             >> 16;
4290                 else
4291                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4292
4293                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4294                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4295
4296                 /* In SPT, This register is in Lan memory space,
4297                  * not flash.  Therefore, only 32 bit access is
4298                  * supported
4299                  */
4300                 if (hw->mac.type == e1000_pch_spt)
4301                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4302                 else
4303                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4304
4305                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4306
4307                 ew32flash(ICH_FLASH_FDATA0, data);
4308
4309                 /* check if FCERR is set to 1 , if set to 1, clear it
4310                  * and try the whole sequence a few more times else done
4311                  */
4312                 ret_val =
4313                    e1000_flash_cycle_ich8lan(hw,
4314                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4315
4316                 if (!ret_val)
4317                         break;
4318
4319                 /* If we're here, then things are most likely
4320                  * completely hosed, but if the error condition
4321                  * is detected, it won't hurt to give it another
4322                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4323                  */
4324                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4325
4326                 if (hsfsts.hsf_status.flcerr)
4327                         /* Repeat for some time before giving up. */
4328                         continue;
4329                 if (!hsfsts.hsf_status.flcdone) {
4330                         e_dbg("Timeout error - flash cycle did not complete.\n");
4331                         break;
4332                 }
4333         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4334
4335         return ret_val;
4336 }
4337
4338 /**
4339  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4340  *  @hw: pointer to the HW structure
4341  *  @offset: The index of the byte to read.
4342  *  @data: The byte to write to the NVM.
4343  *
4344  *  Writes a single byte to the NVM using the flash access registers.
4345  **/
4346 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4347                                           u8 data)
4348 {
4349         u16 word = (u16)data;
4350
4351         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4352 }
4353
4354 /**
4355 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4356 *  @hw: pointer to the HW structure
4357 *  @offset: The offset of the word to write.
4358 *  @dword: The dword to write to the NVM.
4359 *
4360 *  Writes a single dword to the NVM using the flash access registers.
4361 *  Goes through a retry algorithm before giving up.
4362 **/
4363 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4364                                                  u32 offset, u32 dword)
4365 {
4366         s32 ret_val;
4367         u16 program_retries;
4368
4369         /* Must convert word offset into bytes. */
4370         offset <<= 1;
4371         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4372
4373         if (!ret_val)
4374                 return ret_val;
4375         for (program_retries = 0; program_retries < 100; program_retries++) {
4376                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4377                 usleep_range(100, 200);
4378                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4379                 if (!ret_val)
4380                         break;
4381         }
4382         if (program_retries == 100)
4383                 return -E1000_ERR_NVM;
4384
4385         return 0;
4386 }
4387
4388 /**
4389  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4390  *  @hw: pointer to the HW structure
4391  *  @offset: The offset of the byte to write.
4392  *  @byte: The byte to write to the NVM.
4393  *
4394  *  Writes a single byte to the NVM using the flash access registers.
4395  *  Goes through a retry algorithm before giving up.
4396  **/
4397 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4398                                                 u32 offset, u8 byte)
4399 {
4400         s32 ret_val;
4401         u16 program_retries;
4402
4403         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4404         if (!ret_val)
4405                 return ret_val;
4406
4407         for (program_retries = 0; program_retries < 100; program_retries++) {
4408                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4409                 usleep_range(100, 200);
4410                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4411                 if (!ret_val)
4412                         break;
4413         }
4414         if (program_retries == 100)
4415                 return -E1000_ERR_NVM;
4416
4417         return 0;
4418 }
4419
4420 /**
4421  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4422  *  @hw: pointer to the HW structure
4423  *  @bank: 0 for first bank, 1 for second bank, etc.
4424  *
4425  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4426  *  bank N is 4096 * N + flash_reg_addr.
4427  **/
4428 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4429 {
4430         struct e1000_nvm_info *nvm = &hw->nvm;
4431         union ich8_hws_flash_status hsfsts;
4432         union ich8_hws_flash_ctrl hsflctl;
4433         u32 flash_linear_addr;
4434         /* bank size is in 16bit words - adjust to bytes */
4435         u32 flash_bank_size = nvm->flash_bank_size * 2;
4436         s32 ret_val;
4437         s32 count = 0;
4438         s32 j, iteration, sector_size;
4439
4440         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4441
4442         /* Determine HW Sector size: Read BERASE bits of hw flash status
4443          * register
4444          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4445          *     consecutive sectors.  The start index for the nth Hw sector
4446          *     can be calculated as = bank * 4096 + n * 256
4447          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4448          *     The start index for the nth Hw sector can be calculated
4449          *     as = bank * 4096
4450          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4451          *     (ich9 only, otherwise error condition)
4452          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4453          */
4454         switch (hsfsts.hsf_status.berasesz) {
4455         case 0:
4456                 /* Hw sector size 256 */
4457                 sector_size = ICH_FLASH_SEG_SIZE_256;
4458                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4459                 break;
4460         case 1:
4461                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4462                 iteration = 1;
4463                 break;
4464         case 2:
4465                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4466                 iteration = 1;
4467                 break;
4468         case 3:
4469                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4470                 iteration = 1;
4471                 break;
4472         default:
4473                 return -E1000_ERR_NVM;
4474         }
4475
4476         /* Start with the base address, then add the sector offset. */
4477         flash_linear_addr = hw->nvm.flash_base_addr;
4478         flash_linear_addr += (bank) ? flash_bank_size : 0;
4479
4480         for (j = 0; j < iteration; j++) {
4481                 do {
4482                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4483
4484                         /* Steps */
4485                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4486                         if (ret_val)
4487                                 return ret_val;
4488
4489                         /* Write a value 11 (block Erase) in Flash
4490                          * Cycle field in hw flash control
4491                          */
4492                         if (hw->mac.type == e1000_pch_spt)
4493                                 hsflctl.regval =
4494                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4495                         else
4496                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4497
4498                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4499                         if (hw->mac.type == e1000_pch_spt)
4500                                 ew32flash(ICH_FLASH_HSFSTS,
4501                                           hsflctl.regval << 16);
4502                         else
4503                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4504
4505                         /* Write the last 24 bits of an index within the
4506                          * block into Flash Linear address field in Flash
4507                          * Address.
4508                          */
4509                         flash_linear_addr += (j * sector_size);
4510                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4511
4512                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4513                         if (!ret_val)
4514                                 break;
4515
4516                         /* Check if FCERR is set to 1.  If 1,
4517                          * clear it and try the whole sequence
4518                          * a few more times else Done
4519                          */
4520                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4521                         if (hsfsts.hsf_status.flcerr)
4522                                 /* repeat for some time before giving up */
4523                                 continue;
4524                         else if (!hsfsts.hsf_status.flcdone)
4525                                 return ret_val;
4526                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4527         }
4528
4529         return 0;
4530 }
4531
4532 /**
4533  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4534  *  @hw: pointer to the HW structure
4535  *  @data: Pointer to the LED settings
4536  *
4537  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4538  *  settings is all 0's or F's, set the LED default to a valid LED default
4539  *  setting.
4540  **/
4541 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4542 {
4543         s32 ret_val;
4544
4545         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4546         if (ret_val) {
4547                 e_dbg("NVM Read Error\n");
4548                 return ret_val;
4549         }
4550
4551         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4552                 *data = ID_LED_DEFAULT_ICH8LAN;
4553
4554         return 0;
4555 }
4556
4557 /**
4558  *  e1000_id_led_init_pchlan - store LED configurations
4559  *  @hw: pointer to the HW structure
4560  *
4561  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4562  *  the PHY LED configuration register.
4563  *
4564  *  PCH also does not have an "always on" or "always off" mode which
4565  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4566  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4567  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4568  *  link based on logic in e1000_led_[on|off]_pchlan().
4569  **/
4570 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4571 {
4572         struct e1000_mac_info *mac = &hw->mac;
4573         s32 ret_val;
4574         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4575         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4576         u16 data, i, temp, shift;
4577
4578         /* Get default ID LED modes */
4579         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4580         if (ret_val)
4581                 return ret_val;
4582
4583         mac->ledctl_default = er32(LEDCTL);
4584         mac->ledctl_mode1 = mac->ledctl_default;
4585         mac->ledctl_mode2 = mac->ledctl_default;
4586
4587         for (i = 0; i < 4; i++) {
4588                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4589                 shift = (i * 5);
4590                 switch (temp) {
4591                 case ID_LED_ON1_DEF2:
4592                 case ID_LED_ON1_ON2:
4593                 case ID_LED_ON1_OFF2:
4594                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4595                         mac->ledctl_mode1 |= (ledctl_on << shift);
4596                         break;
4597                 case ID_LED_OFF1_DEF2:
4598                 case ID_LED_OFF1_ON2:
4599                 case ID_LED_OFF1_OFF2:
4600                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4601                         mac->ledctl_mode1 |= (ledctl_off << shift);
4602                         break;
4603                 default:
4604                         /* Do nothing */
4605                         break;
4606                 }
4607                 switch (temp) {
4608                 case ID_LED_DEF1_ON2:
4609                 case ID_LED_ON1_ON2:
4610                 case ID_LED_OFF1_ON2:
4611                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4612                         mac->ledctl_mode2 |= (ledctl_on << shift);
4613                         break;
4614                 case ID_LED_DEF1_OFF2:
4615                 case ID_LED_ON1_OFF2:
4616                 case ID_LED_OFF1_OFF2:
4617                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4618                         mac->ledctl_mode2 |= (ledctl_off << shift);
4619                         break;
4620                 default:
4621                         /* Do nothing */
4622                         break;
4623                 }
4624         }
4625
4626         return 0;
4627 }
4628
4629 /**
4630  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4631  *  @hw: pointer to the HW structure
4632  *
4633  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4634  *  register, so the the bus width is hard coded.
4635  **/
4636 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4637 {
4638         struct e1000_bus_info *bus = &hw->bus;
4639         s32 ret_val;
4640
4641         ret_val = e1000e_get_bus_info_pcie(hw);
4642
4643         /* ICH devices are "PCI Express"-ish.  They have
4644          * a configuration space, but do not contain
4645          * PCI Express Capability registers, so bus width
4646          * must be hardcoded.
4647          */
4648         if (bus->width == e1000_bus_width_unknown)
4649                 bus->width = e1000_bus_width_pcie_x1;
4650
4651         return ret_val;
4652 }
4653
4654 /**
4655  *  e1000_reset_hw_ich8lan - Reset the hardware
4656  *  @hw: pointer to the HW structure
4657  *
4658  *  Does a full reset of the hardware which includes a reset of the PHY and
4659  *  MAC.
4660  **/
4661 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4662 {
4663         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4664         u16 kum_cfg;
4665         u32 ctrl, reg;
4666         s32 ret_val;
4667
4668         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4669          * on the last TLP read/write transaction when MAC is reset.
4670          */
4671         ret_val = e1000e_disable_pcie_master(hw);
4672         if (ret_val)
4673                 e_dbg("PCI-E Master disable polling has failed.\n");
4674
4675         e_dbg("Masking off all interrupts\n");
4676         ew32(IMC, 0xffffffff);
4677
4678         /* Disable the Transmit and Receive units.  Then delay to allow
4679          * any pending transactions to complete before we hit the MAC
4680          * with the global reset.
4681          */
4682         ew32(RCTL, 0);
4683         ew32(TCTL, E1000_TCTL_PSP);
4684         e1e_flush();
4685
4686         usleep_range(10000, 20000);
4687
4688         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4689         if (hw->mac.type == e1000_ich8lan) {
4690                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4691                 ew32(PBA, E1000_PBA_8K);
4692                 /* Set Packet Buffer Size to 16k. */
4693                 ew32(PBS, E1000_PBS_16K);
4694         }
4695
4696         if (hw->mac.type == e1000_pchlan) {
4697                 /* Save the NVM K1 bit setting */
4698                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4699                 if (ret_val)
4700                         return ret_val;
4701
4702                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4703                         dev_spec->nvm_k1_enabled = true;
4704                 else
4705                         dev_spec->nvm_k1_enabled = false;
4706         }
4707
4708         ctrl = er32(CTRL);
4709
4710         if (!hw->phy.ops.check_reset_block(hw)) {
4711                 /* Full-chip reset requires MAC and PHY reset at the same
4712                  * time to make sure the interface between MAC and the
4713                  * external PHY is reset.
4714                  */
4715                 ctrl |= E1000_CTRL_PHY_RST;
4716
4717                 /* Gate automatic PHY configuration by hardware on
4718                  * non-managed 82579
4719                  */
4720                 if ((hw->mac.type == e1000_pch2lan) &&
4721                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4722                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4723         }
4724         ret_val = e1000_acquire_swflag_ich8lan(hw);
4725         e_dbg("Issuing a global reset to ich8lan\n");
4726         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4727         /* cannot issue a flush here because it hangs the hardware */
4728         msleep(20);
4729
4730         /* Set Phy Config Counter to 50msec */
4731         if (hw->mac.type == e1000_pch2lan) {
4732                 reg = er32(FEXTNVM3);
4733                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4734                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4735                 ew32(FEXTNVM3, reg);
4736         }
4737
4738         if (!ret_val)
4739                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4740
4741         if (ctrl & E1000_CTRL_PHY_RST) {
4742                 ret_val = hw->phy.ops.get_cfg_done(hw);
4743                 if (ret_val)
4744                         return ret_val;
4745
4746                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4747                 if (ret_val)
4748                         return ret_val;
4749         }
4750
4751         /* For PCH, this write will make sure that any noise
4752          * will be detected as a CRC error and be dropped rather than show up
4753          * as a bad packet to the DMA engine.
4754          */
4755         if (hw->mac.type == e1000_pchlan)
4756                 ew32(CRC_OFFSET, 0x65656565);
4757
4758         ew32(IMC, 0xffffffff);
4759         er32(ICR);
4760
4761         reg = er32(KABGTXD);
4762         reg |= E1000_KABGTXD_BGSQLBIAS;
4763         ew32(KABGTXD, reg);
4764
4765         return 0;
4766 }
4767
4768 /**
4769  *  e1000_init_hw_ich8lan - Initialize the hardware
4770  *  @hw: pointer to the HW structure
4771  *
4772  *  Prepares the hardware for transmit and receive by doing the following:
4773  *   - initialize hardware bits
4774  *   - initialize LED identification
4775  *   - setup receive address registers
4776  *   - setup flow control
4777  *   - setup transmit descriptors
4778  *   - clear statistics
4779  **/
4780 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4781 {
4782         struct e1000_mac_info *mac = &hw->mac;
4783         u32 ctrl_ext, txdctl, snoop;
4784         s32 ret_val;
4785         u16 i;
4786
4787         e1000_initialize_hw_bits_ich8lan(hw);
4788
4789         /* Initialize identification LED */
4790         ret_val = mac->ops.id_led_init(hw);
4791         /* An error is not fatal and we should not stop init due to this */
4792         if (ret_val)
4793                 e_dbg("Error initializing identification LED\n");
4794
4795         /* Setup the receive address. */
4796         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4797
4798         /* Zero out the Multicast HASH table */
4799         e_dbg("Zeroing the MTA\n");
4800         for (i = 0; i < mac->mta_reg_count; i++)
4801                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4802
4803         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4804          * the ME.  Disable wakeup by clearing the host wakeup bit.
4805          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4806          */
4807         if (hw->phy.type == e1000_phy_82578) {
4808                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4809                 i &= ~BM_WUC_HOST_WU_BIT;
4810                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4811                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4812                 if (ret_val)
4813                         return ret_val;
4814         }
4815
4816         /* Setup link and flow control */
4817         ret_val = mac->ops.setup_link(hw);
4818
4819         /* Set the transmit descriptor write-back policy for both queues */
4820         txdctl = er32(TXDCTL(0));
4821         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4822                   E1000_TXDCTL_FULL_TX_DESC_WB);
4823         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4824                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4825         ew32(TXDCTL(0), txdctl);
4826         txdctl = er32(TXDCTL(1));
4827         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4828                   E1000_TXDCTL_FULL_TX_DESC_WB);
4829         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4830                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4831         ew32(TXDCTL(1), txdctl);
4832
4833         /* ICH8 has opposite polarity of no_snoop bits.
4834          * By default, we should use snoop behavior.
4835          */
4836         if (mac->type == e1000_ich8lan)
4837                 snoop = PCIE_ICH8_SNOOP_ALL;
4838         else
4839                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4840         e1000e_set_pcie_no_snoop(hw, snoop);
4841
4842         ctrl_ext = er32(CTRL_EXT);
4843         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4844         ew32(CTRL_EXT, ctrl_ext);
4845
4846         /* Clear all of the statistics registers (clear on read).  It is
4847          * important that we do this after we have tried to establish link
4848          * because the symbol error count will increment wildly if there
4849          * is no link.
4850          */
4851         e1000_clear_hw_cntrs_ich8lan(hw);
4852
4853         return ret_val;
4854 }
4855
4856 /**
4857  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4858  *  @hw: pointer to the HW structure
4859  *
4860  *  Sets/Clears required hardware bits necessary for correctly setting up the
4861  *  hardware for transmit and receive.
4862  **/
4863 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4864 {
4865         u32 reg;
4866
4867         /* Extended Device Control */
4868         reg = er32(CTRL_EXT);
4869         reg |= BIT(22);
4870         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4871         if (hw->mac.type >= e1000_pchlan)
4872                 reg |= E1000_CTRL_EXT_PHYPDEN;
4873         ew32(CTRL_EXT, reg);
4874
4875         /* Transmit Descriptor Control 0 */
4876         reg = er32(TXDCTL(0));
4877         reg |= BIT(22);
4878         ew32(TXDCTL(0), reg);
4879
4880         /* Transmit Descriptor Control 1 */
4881         reg = er32(TXDCTL(1));
4882         reg |= BIT(22);
4883         ew32(TXDCTL(1), reg);
4884
4885         /* Transmit Arbitration Control 0 */
4886         reg = er32(TARC(0));
4887         if (hw->mac.type == e1000_ich8lan)
4888                 reg |= BIT(28) | BIT(29);
4889         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4890         ew32(TARC(0), reg);
4891
4892         /* Transmit Arbitration Control 1 */
4893         reg = er32(TARC(1));
4894         if (er32(TCTL) & E1000_TCTL_MULR)
4895                 reg &= ~BIT(28);
4896         else
4897                 reg |= BIT(28);
4898         reg |= BIT(24) | BIT(26) | BIT(30);
4899         ew32(TARC(1), reg);
4900
4901         /* Device Status */
4902         if (hw->mac.type == e1000_ich8lan) {
4903                 reg = er32(STATUS);
4904                 reg &= ~BIT(31);
4905                 ew32(STATUS, reg);
4906         }
4907
4908         /* work-around descriptor data corruption issue during nfs v2 udp
4909          * traffic, just disable the nfs filtering capability
4910          */
4911         reg = er32(RFCTL);
4912         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4913
4914         /* Disable IPv6 extension header parsing because some malformed
4915          * IPv6 headers can hang the Rx.
4916          */
4917         if (hw->mac.type == e1000_ich8lan)
4918                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4919         ew32(RFCTL, reg);
4920
4921         /* Enable ECC on Lynxpoint */
4922         if ((hw->mac.type == e1000_pch_lpt) ||
4923             (hw->mac.type == e1000_pch_spt)) {
4924                 reg = er32(PBECCSTS);
4925                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4926                 ew32(PBECCSTS, reg);
4927
4928                 reg = er32(CTRL);
4929                 reg |= E1000_CTRL_MEHE;
4930                 ew32(CTRL, reg);
4931         }
4932 }
4933
4934 /**
4935  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4936  *  @hw: pointer to the HW structure
4937  *
4938  *  Determines which flow control settings to use, then configures flow
4939  *  control.  Calls the appropriate media-specific link configuration
4940  *  function.  Assuming the adapter has a valid link partner, a valid link
4941  *  should be established.  Assumes the hardware has previously been reset
4942  *  and the transmitter and receiver are not enabled.
4943  **/
4944 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4945 {
4946         s32 ret_val;
4947
4948         if (hw->phy.ops.check_reset_block(hw))
4949                 return 0;
4950
4951         /* ICH parts do not have a word in the NVM to determine
4952          * the default flow control setting, so we explicitly
4953          * set it to full.
4954          */
4955         if (hw->fc.requested_mode == e1000_fc_default) {
4956                 /* Workaround h/w hang when Tx flow control enabled */
4957                 if (hw->mac.type == e1000_pchlan)
4958                         hw->fc.requested_mode = e1000_fc_rx_pause;
4959                 else
4960                         hw->fc.requested_mode = e1000_fc_full;
4961         }
4962
4963         /* Save off the requested flow control mode for use later.  Depending
4964          * on the link partner's capabilities, we may or may not use this mode.
4965          */
4966         hw->fc.current_mode = hw->fc.requested_mode;
4967
4968         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4969
4970         /* Continue to configure the copper link. */
4971         ret_val = hw->mac.ops.setup_physical_interface(hw);
4972         if (ret_val)
4973                 return ret_val;
4974
4975         ew32(FCTTV, hw->fc.pause_time);
4976         if ((hw->phy.type == e1000_phy_82578) ||
4977             (hw->phy.type == e1000_phy_82579) ||
4978             (hw->phy.type == e1000_phy_i217) ||
4979             (hw->phy.type == e1000_phy_82577)) {
4980                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4981
4982                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4983                                    hw->fc.pause_time);
4984                 if (ret_val)
4985                         return ret_val;
4986         }
4987
4988         return e1000e_set_fc_watermarks(hw);
4989 }
4990
4991 /**
4992  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4993  *  @hw: pointer to the HW structure
4994  *
4995  *  Configures the kumeran interface to the PHY to wait the appropriate time
4996  *  when polling the PHY, then call the generic setup_copper_link to finish
4997  *  configuring the copper link.
4998  **/
4999 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5000 {
5001         u32 ctrl;
5002         s32 ret_val;
5003         u16 reg_data;
5004
5005         ctrl = er32(CTRL);
5006         ctrl |= E1000_CTRL_SLU;
5007         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5008         ew32(CTRL, ctrl);
5009
5010         /* Set the mac to wait the maximum time between each iteration
5011          * and increase the max iterations when polling the phy;
5012          * this fixes erroneous timeouts at 10Mbps.
5013          */
5014         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5015         if (ret_val)
5016                 return ret_val;
5017         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5018                                        &reg_data);
5019         if (ret_val)
5020                 return ret_val;
5021         reg_data |= 0x3F;
5022         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5023                                         reg_data);
5024         if (ret_val)
5025                 return ret_val;
5026
5027         switch (hw->phy.type) {
5028         case e1000_phy_igp_3:
5029                 ret_val = e1000e_copper_link_setup_igp(hw);
5030                 if (ret_val)
5031                         return ret_val;
5032                 break;
5033         case e1000_phy_bm:
5034         case e1000_phy_82578:
5035                 ret_val = e1000e_copper_link_setup_m88(hw);
5036                 if (ret_val)
5037                         return ret_val;
5038                 break;
5039         case e1000_phy_82577:
5040         case e1000_phy_82579:
5041                 ret_val = e1000_copper_link_setup_82577(hw);
5042                 if (ret_val)
5043                         return ret_val;
5044                 break;
5045         case e1000_phy_ife:
5046                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5047                 if (ret_val)
5048                         return ret_val;
5049
5050                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5051
5052                 switch (hw->phy.mdix) {
5053                 case 1:
5054                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5055                         break;
5056                 case 2:
5057                         reg_data |= IFE_PMC_FORCE_MDIX;
5058                         break;
5059                 case 0:
5060                 default:
5061                         reg_data |= IFE_PMC_AUTO_MDIX;
5062                         break;
5063                 }
5064                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5065                 if (ret_val)
5066                         return ret_val;
5067                 break;
5068         default:
5069                 break;
5070         }
5071
5072         return e1000e_setup_copper_link(hw);
5073 }
5074
5075 /**
5076  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5077  *  @hw: pointer to the HW structure
5078  *
5079  *  Calls the PHY specific link setup function and then calls the
5080  *  generic setup_copper_link to finish configuring the link for
5081  *  Lynxpoint PCH devices
5082  **/
5083 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5084 {
5085         u32 ctrl;
5086         s32 ret_val;
5087
5088         ctrl = er32(CTRL);
5089         ctrl |= E1000_CTRL_SLU;
5090         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5091         ew32(CTRL, ctrl);
5092
5093         ret_val = e1000_copper_link_setup_82577(hw);
5094         if (ret_val)
5095                 return ret_val;
5096
5097         return e1000e_setup_copper_link(hw);
5098 }
5099
5100 /**
5101  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5102  *  @hw: pointer to the HW structure
5103  *  @speed: pointer to store current link speed
5104  *  @duplex: pointer to store the current link duplex
5105  *
5106  *  Calls the generic get_speed_and_duplex to retrieve the current link
5107  *  information and then calls the Kumeran lock loss workaround for links at
5108  *  gigabit speeds.
5109  **/
5110 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5111                                           u16 *duplex)
5112 {
5113         s32 ret_val;
5114
5115         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5116         if (ret_val)
5117                 return ret_val;
5118
5119         if ((hw->mac.type == e1000_ich8lan) &&
5120             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5121                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5122         }
5123
5124         return ret_val;
5125 }
5126
5127 /**
5128  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5129  *  @hw: pointer to the HW structure
5130  *
5131  *  Work-around for 82566 Kumeran PCS lock loss:
5132  *  On link status change (i.e. PCI reset, speed change) and link is up and
5133  *  speed is gigabit-
5134  *    0) if workaround is optionally disabled do nothing
5135  *    1) wait 1ms for Kumeran link to come up
5136  *    2) check Kumeran Diagnostic register PCS lock loss bit
5137  *    3) if not set the link is locked (all is good), otherwise...
5138  *    4) reset the PHY
5139  *    5) repeat up to 10 times
5140  *  Note: this is only called for IGP3 copper when speed is 1gb.
5141  **/
5142 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5143 {
5144         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5145         u32 phy_ctrl;
5146         s32 ret_val;
5147         u16 i, data;
5148         bool link;
5149
5150         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5151                 return 0;
5152
5153         /* Make sure link is up before proceeding.  If not just return.
5154          * Attempting this while link is negotiating fouled up link
5155          * stability
5156          */
5157         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5158         if (!link)
5159                 return 0;
5160
5161         for (i = 0; i < 10; i++) {
5162                 /* read once to clear */
5163                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5164                 if (ret_val)
5165                         return ret_val;
5166                 /* and again to get new status */
5167                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5168                 if (ret_val)
5169                         return ret_val;
5170
5171                 /* check for PCS lock */
5172                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5173                         return 0;
5174
5175                 /* Issue PHY reset */
5176                 e1000_phy_hw_reset(hw);
5177                 mdelay(5);
5178         }
5179         /* Disable GigE link negotiation */
5180         phy_ctrl = er32(PHY_CTRL);
5181         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5182                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5183         ew32(PHY_CTRL, phy_ctrl);
5184
5185         /* Call gig speed drop workaround on Gig disable before accessing
5186          * any PHY registers
5187          */
5188         e1000e_gig_downshift_workaround_ich8lan(hw);
5189
5190         /* unable to acquire PCS lock */
5191         return -E1000_ERR_PHY;
5192 }
5193
5194 /**
5195  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5196  *  @hw: pointer to the HW structure
5197  *  @state: boolean value used to set the current Kumeran workaround state
5198  *
5199  *  If ICH8, set the current Kumeran workaround state (enabled - true
5200  *  /disabled - false).
5201  **/
5202 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5203                                                   bool state)
5204 {
5205         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5206
5207         if (hw->mac.type != e1000_ich8lan) {
5208                 e_dbg("Workaround applies to ICH8 only.\n");
5209                 return;
5210         }
5211
5212         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5213 }
5214
5215 /**
5216  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5217  *  @hw: pointer to the HW structure
5218  *
5219  *  Workaround for 82566 power-down on D3 entry:
5220  *    1) disable gigabit link
5221  *    2) write VR power-down enable
5222  *    3) read it back
5223  *  Continue if successful, else issue LCD reset and repeat
5224  **/
5225 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5226 {
5227         u32 reg;
5228         u16 data;
5229         u8 retry = 0;
5230
5231         if (hw->phy.type != e1000_phy_igp_3)
5232                 return;
5233
5234         /* Try the workaround twice (if needed) */
5235         do {
5236                 /* Disable link */
5237                 reg = er32(PHY_CTRL);
5238                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5239                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5240                 ew32(PHY_CTRL, reg);
5241
5242                 /* Call gig speed drop workaround on Gig disable before
5243                  * accessing any PHY registers
5244                  */
5245                 if (hw->mac.type == e1000_ich8lan)
5246                         e1000e_gig_downshift_workaround_ich8lan(hw);
5247
5248                 /* Write VR power-down enable */
5249                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5250                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5251                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5252
5253                 /* Read it back and test */
5254                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5255                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5256                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5257                         break;
5258
5259                 /* Issue PHY reset and repeat at most one more time */
5260                 reg = er32(CTRL);
5261                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5262                 retry++;
5263         } while (retry);
5264 }
5265
5266 /**
5267  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5268  *  @hw: pointer to the HW structure
5269  *
5270  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5271  *  LPLU, Gig disable, MDIC PHY reset):
5272  *    1) Set Kumeran Near-end loopback
5273  *    2) Clear Kumeran Near-end loopback
5274  *  Should only be called for ICH8[m] devices with any 1G Phy.
5275  **/
5276 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5277 {
5278         s32 ret_val;
5279         u16 reg_data;
5280
5281         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5282                 return;
5283
5284         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5285                                        &reg_data);
5286         if (ret_val)
5287                 return;
5288         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5289         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5290                                         reg_data);
5291         if (ret_val)
5292                 return;
5293         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5294         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5295 }
5296
5297 /**
5298  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5299  *  @hw: pointer to the HW structure
5300  *
5301  *  During S0 to Sx transition, it is possible the link remains at gig
5302  *  instead of negotiating to a lower speed.  Before going to Sx, set
5303  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5304  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5305  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5306  *  needs to be written.
5307  *  Parts that support (and are linked to a partner which support) EEE in
5308  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5309  *  than 10Mbps w/o EEE.
5310  **/
5311 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5312 {
5313         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5314         u32 phy_ctrl;
5315         s32 ret_val;
5316
5317         phy_ctrl = er32(PHY_CTRL);
5318         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5319
5320         if (hw->phy.type == e1000_phy_i217) {
5321                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5322
5323                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5324                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5325                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5326                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5327                     (hw->mac.type == e1000_pch_spt)) {
5328                         u32 fextnvm6 = er32(FEXTNVM6);
5329
5330                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5331                 }
5332
5333                 ret_val = hw->phy.ops.acquire(hw);
5334                 if (ret_val)
5335                         goto out;
5336
5337                 if (!dev_spec->eee_disable) {
5338                         u16 eee_advert;
5339
5340                         ret_val =
5341                             e1000_read_emi_reg_locked(hw,
5342                                                       I217_EEE_ADVERTISEMENT,
5343                                                       &eee_advert);
5344                         if (ret_val)
5345                                 goto release;
5346
5347                         /* Disable LPLU if both link partners support 100BaseT
5348                          * EEE and 100Full is advertised on both ends of the
5349                          * link, and enable Auto Enable LPI since there will
5350                          * be no driver to enable LPI while in Sx.
5351                          */
5352                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5353                             (dev_spec->eee_lp_ability &
5354                              I82579_EEE_100_SUPPORTED) &&
5355                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5356                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5357                                               E1000_PHY_CTRL_NOND0A_LPLU);
5358
5359                                 /* Set Auto Enable LPI after link up */
5360                                 e1e_rphy_locked(hw,
5361                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5362                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5363                                 e1e_wphy_locked(hw,
5364                                                 I217_LPI_GPIO_CTRL, phy_reg);
5365                         }
5366                 }
5367
5368                 /* For i217 Intel Rapid Start Technology support,
5369                  * when the system is going into Sx and no manageability engine
5370                  * is present, the driver must configure proxy to reset only on
5371                  * power good.  LPI (Low Power Idle) state must also reset only
5372                  * on power good, as well as the MTA (Multicast table array).
5373                  * The SMBus release must also be disabled on LCD reset.
5374                  */
5375                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5376                         /* Enable proxy to reset only on power good. */
5377                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5378                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5379                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5380
5381                         /* Set bit enable LPI (EEE) to reset only on
5382                          * power good.
5383                          */
5384                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5385                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5386                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5387
5388                         /* Disable the SMB release on LCD reset. */
5389                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5390                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5391                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5392                 }
5393
5394                 /* Enable MTA to reset for Intel Rapid Start Technology
5395                  * Support
5396                  */
5397                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5398                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5399                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5400
5401 release:
5402                 hw->phy.ops.release(hw);
5403         }
5404 out:
5405         ew32(PHY_CTRL, phy_ctrl);
5406
5407         if (hw->mac.type == e1000_ich8lan)
5408                 e1000e_gig_downshift_workaround_ich8lan(hw);
5409
5410         if (hw->mac.type >= e1000_pchlan) {
5411                 e1000_oem_bits_config_ich8lan(hw, false);
5412
5413                 /* Reset PHY to activate OEM bits on 82577/8 */
5414                 if (hw->mac.type == e1000_pchlan)
5415                         e1000e_phy_hw_reset_generic(hw);
5416
5417                 ret_val = hw->phy.ops.acquire(hw);
5418                 if (ret_val)
5419                         return;
5420                 e1000_write_smbus_addr(hw);
5421                 hw->phy.ops.release(hw);
5422         }
5423 }
5424
5425 /**
5426  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5427  *  @hw: pointer to the HW structure
5428  *
5429  *  During Sx to S0 transitions on non-managed devices or managed devices
5430  *  on which PHY resets are not blocked, if the PHY registers cannot be
5431  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5432  *  the PHY.
5433  *  On i217, setup Intel Rapid Start Technology.
5434  **/
5435 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5436 {
5437         s32 ret_val;
5438
5439         if (hw->mac.type < e1000_pch2lan)
5440                 return;
5441
5442         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5443         if (ret_val) {
5444                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5445                 return;
5446         }
5447
5448         /* For i217 Intel Rapid Start Technology support when the system
5449          * is transitioning from Sx and no manageability engine is present
5450          * configure SMBus to restore on reset, disable proxy, and enable
5451          * the reset on MTA (Multicast table array).
5452          */
5453         if (hw->phy.type == e1000_phy_i217) {
5454                 u16 phy_reg;
5455
5456                 ret_val = hw->phy.ops.acquire(hw);
5457                 if (ret_val) {
5458                         e_dbg("Failed to setup iRST\n");
5459                         return;
5460                 }
5461
5462                 /* Clear Auto Enable LPI after link up */
5463                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5464                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5465                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5466
5467                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5468                         /* Restore clear on SMB if no manageability engine
5469                          * is present
5470                          */
5471                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5472                         if (ret_val)
5473                                 goto release;
5474                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5475                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5476
5477                         /* Disable Proxy */
5478                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5479                 }
5480                 /* Enable reset on MTA */
5481                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5482                 if (ret_val)
5483                         goto release;
5484                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5485                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5486 release:
5487                 if (ret_val)
5488                         e_dbg("Error %d in resume workarounds\n", ret_val);
5489                 hw->phy.ops.release(hw);
5490         }
5491 }
5492
5493 /**
5494  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5495  *  @hw: pointer to the HW structure
5496  *
5497  *  Return the LED back to the default configuration.
5498  **/
5499 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5500 {
5501         if (hw->phy.type == e1000_phy_ife)
5502                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5503
5504         ew32(LEDCTL, hw->mac.ledctl_default);
5505         return 0;
5506 }
5507
5508 /**
5509  *  e1000_led_on_ich8lan - Turn LEDs on
5510  *  @hw: pointer to the HW structure
5511  *
5512  *  Turn on the LEDs.
5513  **/
5514 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5515 {
5516         if (hw->phy.type == e1000_phy_ife)
5517                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5518                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5519
5520         ew32(LEDCTL, hw->mac.ledctl_mode2);
5521         return 0;
5522 }
5523
5524 /**
5525  *  e1000_led_off_ich8lan - Turn LEDs off
5526  *  @hw: pointer to the HW structure
5527  *
5528  *  Turn off the LEDs.
5529  **/
5530 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5531 {
5532         if (hw->phy.type == e1000_phy_ife)
5533                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5534                                 (IFE_PSCL_PROBE_MODE |
5535                                  IFE_PSCL_PROBE_LEDS_OFF));
5536
5537         ew32(LEDCTL, hw->mac.ledctl_mode1);
5538         return 0;
5539 }
5540
5541 /**
5542  *  e1000_setup_led_pchlan - Configures SW controllable LED
5543  *  @hw: pointer to the HW structure
5544  *
5545  *  This prepares the SW controllable LED for use.
5546  **/
5547 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5548 {
5549         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5550 }
5551
5552 /**
5553  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5554  *  @hw: pointer to the HW structure
5555  *
5556  *  Return the LED back to the default configuration.
5557  **/
5558 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5559 {
5560         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5561 }
5562
5563 /**
5564  *  e1000_led_on_pchlan - Turn LEDs on
5565  *  @hw: pointer to the HW structure
5566  *
5567  *  Turn on the LEDs.
5568  **/
5569 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5570 {
5571         u16 data = (u16)hw->mac.ledctl_mode2;
5572         u32 i, led;
5573
5574         /* If no link, then turn LED on by setting the invert bit
5575          * for each LED that's mode is "link_up" in ledctl_mode2.
5576          */
5577         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5578                 for (i = 0; i < 3; i++) {
5579                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5580                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5581                             E1000_LEDCTL_MODE_LINK_UP)
5582                                 continue;
5583                         if (led & E1000_PHY_LED0_IVRT)
5584                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5585                         else
5586                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5587                 }
5588         }
5589
5590         return e1e_wphy(hw, HV_LED_CONFIG, data);
5591 }
5592
5593 /**
5594  *  e1000_led_off_pchlan - Turn LEDs off
5595  *  @hw: pointer to the HW structure
5596  *
5597  *  Turn off the LEDs.
5598  **/
5599 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5600 {
5601         u16 data = (u16)hw->mac.ledctl_mode1;
5602         u32 i, led;
5603
5604         /* If no link, then turn LED off by clearing the invert bit
5605          * for each LED that's mode is "link_up" in ledctl_mode1.
5606          */
5607         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5608                 for (i = 0; i < 3; i++) {
5609                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5610                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5611                             E1000_LEDCTL_MODE_LINK_UP)
5612                                 continue;
5613                         if (led & E1000_PHY_LED0_IVRT)
5614                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5615                         else
5616                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5617                 }
5618         }
5619
5620         return e1e_wphy(hw, HV_LED_CONFIG, data);
5621 }
5622
5623 /**
5624  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5625  *  @hw: pointer to the HW structure
5626  *
5627  *  Read appropriate register for the config done bit for completion status
5628  *  and configure the PHY through s/w for EEPROM-less parts.
5629  *
5630  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5631  *  config done bit, so only an error is logged and continues.  If we were
5632  *  to return with error, EEPROM-less silicon would not be able to be reset
5633  *  or change link.
5634  **/
5635 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5636 {
5637         s32 ret_val = 0;
5638         u32 bank = 0;
5639         u32 status;
5640
5641         e1000e_get_cfg_done_generic(hw);
5642
5643         /* Wait for indication from h/w that it has completed basic config */
5644         if (hw->mac.type >= e1000_ich10lan) {
5645                 e1000_lan_init_done_ich8lan(hw);
5646         } else {
5647                 ret_val = e1000e_get_auto_rd_done(hw);
5648                 if (ret_val) {
5649                         /* When auto config read does not complete, do not
5650                          * return with an error. This can happen in situations
5651                          * where there is no eeprom and prevents getting link.
5652                          */
5653                         e_dbg("Auto Read Done did not complete\n");
5654                         ret_val = 0;
5655                 }
5656         }
5657
5658         /* Clear PHY Reset Asserted bit */
5659         status = er32(STATUS);
5660         if (status & E1000_STATUS_PHYRA)
5661                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5662         else
5663                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5664
5665         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5666         if (hw->mac.type <= e1000_ich9lan) {
5667                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5668                     (hw->phy.type == e1000_phy_igp_3)) {
5669                         e1000e_phy_init_script_igp3(hw);
5670                 }
5671         } else {
5672                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5673                         /* Maybe we should do a basic PHY config */
5674                         e_dbg("EEPROM not present\n");
5675                         ret_val = -E1000_ERR_CONFIG;
5676                 }
5677         }
5678
5679         return ret_val;
5680 }
5681
5682 /**
5683  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5684  * @hw: pointer to the HW structure
5685  *
5686  * In the case of a PHY power down to save power, or to turn off link during a
5687  * driver unload, or wake on lan is not enabled, remove the link.
5688  **/
5689 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5690 {
5691         /* If the management interface is not enabled, then power down */
5692         if (!(hw->mac.ops.check_mng_mode(hw) ||
5693               hw->phy.ops.check_reset_block(hw)))
5694                 e1000_power_down_phy_copper(hw);
5695 }
5696
5697 /**
5698  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5699  *  @hw: pointer to the HW structure
5700  *
5701  *  Clears hardware counters specific to the silicon family and calls
5702  *  clear_hw_cntrs_generic to clear all general purpose counters.
5703  **/
5704 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5705 {
5706         u16 phy_data;
5707         s32 ret_val;
5708
5709         e1000e_clear_hw_cntrs_base(hw);
5710
5711         er32(ALGNERRC);
5712         er32(RXERRC);
5713         er32(TNCRS);
5714         er32(CEXTERR);
5715         er32(TSCTC);
5716         er32(TSCTFC);
5717
5718         er32(MGTPRC);
5719         er32(MGTPDC);
5720         er32(MGTPTC);
5721
5722         er32(IAC);
5723         er32(ICRXOC);
5724
5725         /* Clear PHY statistics registers */
5726         if ((hw->phy.type == e1000_phy_82578) ||
5727             (hw->phy.type == e1000_phy_82579) ||
5728             (hw->phy.type == e1000_phy_i217) ||
5729             (hw->phy.type == e1000_phy_82577)) {
5730                 ret_val = hw->phy.ops.acquire(hw);
5731                 if (ret_val)
5732                         return;
5733                 ret_val = hw->phy.ops.set_page(hw,
5734                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5735                 if (ret_val)
5736                         goto release;
5737                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5738                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5739                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5740                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5741                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5742                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5743                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5744                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5745                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5746                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5747                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5748                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5749                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5750                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5751 release:
5752                 hw->phy.ops.release(hw);
5753         }
5754 }
5755
5756 static const struct e1000_mac_operations ich8_mac_ops = {
5757         /* check_mng_mode dependent on mac type */
5758         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5759         /* cleanup_led dependent on mac type */
5760         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5761         .get_bus_info           = e1000_get_bus_info_ich8lan,
5762         .set_lan_id             = e1000_set_lan_id_single_port,
5763         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5764         /* led_on dependent on mac type */
5765         /* led_off dependent on mac type */
5766         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5767         .reset_hw               = e1000_reset_hw_ich8lan,
5768         .init_hw                = e1000_init_hw_ich8lan,
5769         .setup_link             = e1000_setup_link_ich8lan,
5770         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5771         /* id_led_init dependent on mac type */
5772         .config_collision_dist  = e1000e_config_collision_dist_generic,
5773         .rar_set                = e1000e_rar_set_generic,
5774         .rar_get_count          = e1000e_rar_get_count_generic,
5775 };
5776
5777 static const struct e1000_phy_operations ich8_phy_ops = {
5778         .acquire                = e1000_acquire_swflag_ich8lan,
5779         .check_reset_block      = e1000_check_reset_block_ich8lan,
5780         .commit                 = NULL,
5781         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5782         .get_cable_length       = e1000e_get_cable_length_igp_2,
5783         .read_reg               = e1000e_read_phy_reg_igp,
5784         .release                = e1000_release_swflag_ich8lan,
5785         .reset                  = e1000_phy_hw_reset_ich8lan,
5786         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5787         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5788         .write_reg              = e1000e_write_phy_reg_igp,
5789 };
5790
5791 static const struct e1000_nvm_operations ich8_nvm_ops = {
5792         .acquire                = e1000_acquire_nvm_ich8lan,
5793         .read                   = e1000_read_nvm_ich8lan,
5794         .release                = e1000_release_nvm_ich8lan,
5795         .reload                 = e1000e_reload_nvm_generic,
5796         .update                 = e1000_update_nvm_checksum_ich8lan,
5797         .valid_led_default      = e1000_valid_led_default_ich8lan,
5798         .validate               = e1000_validate_nvm_checksum_ich8lan,
5799         .write                  = e1000_write_nvm_ich8lan,
5800 };
5801
5802 static const struct e1000_nvm_operations spt_nvm_ops = {
5803         .acquire                = e1000_acquire_nvm_ich8lan,
5804         .release                = e1000_release_nvm_ich8lan,
5805         .read                   = e1000_read_nvm_spt,
5806         .update                 = e1000_update_nvm_checksum_spt,
5807         .reload                 = e1000e_reload_nvm_generic,
5808         .valid_led_default      = e1000_valid_led_default_ich8lan,
5809         .validate               = e1000_validate_nvm_checksum_ich8lan,
5810         .write                  = e1000_write_nvm_ich8lan,
5811 };
5812
5813 const struct e1000_info e1000_ich8_info = {
5814         .mac                    = e1000_ich8lan,
5815         .flags                  = FLAG_HAS_WOL
5816                                   | FLAG_IS_ICH
5817                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5818                                   | FLAG_HAS_AMT
5819                                   | FLAG_HAS_FLASH
5820                                   | FLAG_APME_IN_WUC,
5821         .pba                    = 8,
5822         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5823         .get_variants           = e1000_get_variants_ich8lan,
5824         .mac_ops                = &ich8_mac_ops,
5825         .phy_ops                = &ich8_phy_ops,
5826         .nvm_ops                = &ich8_nvm_ops,
5827 };
5828
5829 const struct e1000_info e1000_ich9_info = {
5830         .mac                    = e1000_ich9lan,
5831         .flags                  = FLAG_HAS_JUMBO_FRAMES
5832                                   | FLAG_IS_ICH
5833                                   | FLAG_HAS_WOL
5834                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5835                                   | FLAG_HAS_AMT
5836                                   | FLAG_HAS_FLASH
5837                                   | FLAG_APME_IN_WUC,
5838         .pba                    = 18,
5839         .max_hw_frame_size      = DEFAULT_JUMBO,
5840         .get_variants           = e1000_get_variants_ich8lan,
5841         .mac_ops                = &ich8_mac_ops,
5842         .phy_ops                = &ich8_phy_ops,
5843         .nvm_ops                = &ich8_nvm_ops,
5844 };
5845
5846 const struct e1000_info e1000_ich10_info = {
5847         .mac                    = e1000_ich10lan,
5848         .flags                  = FLAG_HAS_JUMBO_FRAMES
5849                                   | FLAG_IS_ICH
5850                                   | FLAG_HAS_WOL
5851                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5852                                   | FLAG_HAS_AMT
5853                                   | FLAG_HAS_FLASH
5854                                   | FLAG_APME_IN_WUC,
5855         .pba                    = 18,
5856         .max_hw_frame_size      = DEFAULT_JUMBO,
5857         .get_variants           = e1000_get_variants_ich8lan,
5858         .mac_ops                = &ich8_mac_ops,
5859         .phy_ops                = &ich8_phy_ops,
5860         .nvm_ops                = &ich8_nvm_ops,
5861 };
5862
5863 const struct e1000_info e1000_pch_info = {
5864         .mac                    = e1000_pchlan,
5865         .flags                  = FLAG_IS_ICH
5866                                   | FLAG_HAS_WOL
5867                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5868                                   | FLAG_HAS_AMT
5869                                   | FLAG_HAS_FLASH
5870                                   | FLAG_HAS_JUMBO_FRAMES
5871                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5872                                   | FLAG_APME_IN_WUC,
5873         .flags2                 = FLAG2_HAS_PHY_STATS,
5874         .pba                    = 26,
5875         .max_hw_frame_size      = 4096,
5876         .get_variants           = e1000_get_variants_ich8lan,
5877         .mac_ops                = &ich8_mac_ops,
5878         .phy_ops                = &ich8_phy_ops,
5879         .nvm_ops                = &ich8_nvm_ops,
5880 };
5881
5882 const struct e1000_info e1000_pch2_info = {
5883         .mac                    = e1000_pch2lan,
5884         .flags                  = FLAG_IS_ICH
5885                                   | FLAG_HAS_WOL
5886                                   | FLAG_HAS_HW_TIMESTAMP
5887                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5888                                   | FLAG_HAS_AMT
5889                                   | FLAG_HAS_FLASH
5890                                   | FLAG_HAS_JUMBO_FRAMES
5891                                   | FLAG_APME_IN_WUC,
5892         .flags2                 = FLAG2_HAS_PHY_STATS
5893                                   | FLAG2_HAS_EEE,
5894         .pba                    = 26,
5895         .max_hw_frame_size      = 9022,
5896         .get_variants           = e1000_get_variants_ich8lan,
5897         .mac_ops                = &ich8_mac_ops,
5898         .phy_ops                = &ich8_phy_ops,
5899         .nvm_ops                = &ich8_nvm_ops,
5900 };
5901
5902 const struct e1000_info e1000_pch_lpt_info = {
5903         .mac                    = e1000_pch_lpt,
5904         .flags                  = FLAG_IS_ICH
5905                                   | FLAG_HAS_WOL
5906                                   | FLAG_HAS_HW_TIMESTAMP
5907                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5908                                   | FLAG_HAS_AMT
5909                                   | FLAG_HAS_FLASH
5910                                   | FLAG_HAS_JUMBO_FRAMES
5911                                   | FLAG_APME_IN_WUC,
5912         .flags2                 = FLAG2_HAS_PHY_STATS
5913                                   | FLAG2_HAS_EEE
5914                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5915         .pba                    = 26,
5916         .max_hw_frame_size      = 9022,
5917         .get_variants           = e1000_get_variants_ich8lan,
5918         .mac_ops                = &ich8_mac_ops,
5919         .phy_ops                = &ich8_phy_ops,
5920         .nvm_ops                = &ich8_nvm_ops,
5921 };
5922
5923 const struct e1000_info e1000_pch_spt_info = {
5924         .mac                    = e1000_pch_spt,
5925         .flags                  = FLAG_IS_ICH
5926                                   | FLAG_HAS_WOL
5927                                   | FLAG_HAS_HW_TIMESTAMP
5928                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5929                                   | FLAG_HAS_AMT
5930                                   | FLAG_HAS_FLASH
5931                                   | FLAG_HAS_JUMBO_FRAMES
5932                                   | FLAG_APME_IN_WUC,
5933         .flags2                 = FLAG2_HAS_PHY_STATS
5934                                   | FLAG2_HAS_EEE,
5935         .pba                    = 26,
5936         .max_hw_frame_size      = 9022,
5937         .get_variants           = e1000_get_variants_ich8lan,
5938         .mac_ops                = &ich8_mac_ops,
5939         .phy_ops                = &ich8_phy_ops,
5940         .nvm_ops                = &spt_nvm_ops,
5941 };