drivers/net/ethernet/intel/i40e/i40e_nvm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #include "i40e_prototype.h"
   5
   6 /**
   7  * i40e_init_nvm_ops - Initialize NVM function pointers
   8  * @hw: pointer to the HW structure
   9  *
  10  * Setup the function pointers and the NVM info structure. Should be called
  11  * once per NVM initialization, e.g. inside the i40e_init_shared_code().
  12  * Please notice that the NVM term is used here (& in all methods covered
  13  * in this file) as an equivalent of the FLASH part mapped into the SR.
  14  * We are accessing FLASH always thru the Shadow RAM.
  15  **/
  16 i40e_status i40e_init_nvm(struct i40e_hw *hw)
  17 {
  18         struct i40e_nvm_info *nvm = &hw->nvm;
  19         i40e_status ret_code = 0;
  20         u32 fla, gens;
  21         u8 sr_size;
  22
  23         /* The SR size is stored regardless of the nvm programming mode
  24          * as the blank mode may be used in the factory line.
  25          */
  26         gens = rd32(hw, I40E_GLNVM_GENS);
  27         sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
  28                            I40E_GLNVM_GENS_SR_SIZE_SHIFT);
  29         /* Switching to words (sr_size contains power of 2KB) */
  30         nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
  31
  32         /* Check if we are in the normal or blank NVM programming mode */
  33         fla = rd32(hw, I40E_GLNVM_FLA);
  34         if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
  35                 /* Max NVM timeout */
  36                 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
  37                 nvm->blank_nvm_mode = false;
  38         } else { /* Blank programming mode */
  39                 nvm->blank_nvm_mode = true;
  40                 ret_code = I40E_ERR_NVM_BLANK_MODE;
  41                 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
  42         }
  43
  44         return ret_code;
  45 }
  46
  47 /**
  48  * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
  49  * @hw: pointer to the HW structure
  50  * @access: NVM access type (read or write)
  51  *
  52  * This function will request NVM ownership for reading
  53  * via the proper Admin Command.
  54  **/
  55 i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
  56                                        enum i40e_aq_resource_access_type access)
  57 {
  58         i40e_status ret_code = 0;
  59         u64 gtime, timeout;
  60         u64 time_left = 0;
  61
  62         if (hw->nvm.blank_nvm_mode)
  63                 goto i40e_i40e_acquire_nvm_exit;
  64
  65         ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
  66                                             0, &time_left, NULL);
  67         /* Reading the Global Device Timer */
  68         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
  69
  70         /* Store the timeout */
  71         hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
  72
  73         if (ret_code)
  74                 i40e_debug(hw, I40E_DEBUG_NVM,
  75                            "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
  76                            access, time_left, ret_code, hw->aq.asq_last_status);
  77
  78         if (ret_code && time_left) {
  79                 /* Poll until the current NVM owner timeouts */
  80                 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
  81                 while ((gtime < timeout) && time_left) {
  82                         usleep_range(10000, 20000);
  83                         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
  84                         ret_code = i40e_aq_request_resource(hw,
  85                                                         I40E_NVM_RESOURCE_ID,
  86                                                         access, 0, &time_left,
  87                                                         NULL);
  88                         if (!ret_code) {
  89                                 hw->nvm.hw_semaphore_timeout =
  90                                             I40E_MS_TO_GTIME(time_left) + gtime;
  91                                 break;
  92                         }
  93                 }
  94                 if (ret_code) {
  95                         hw->nvm.hw_semaphore_timeout = 0;
  96                         i40e_debug(hw, I40E_DEBUG_NVM,
  97                                    "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
  98                                    time_left, ret_code, hw->aq.asq_last_status);
  99                 }
 100         }
 101
 102 i40e_i40e_acquire_nvm_exit:
 103         return ret_code;
 104 }
 105
 106 /**
 107  * i40e_release_nvm - Generic request for releasing the NVM ownership
 108  * @hw: pointer to the HW structure
 109  *
 110  * This function will release NVM resource via the proper Admin Command.
 111  **/
 112 void i40e_release_nvm(struct i40e_hw *hw)
 113 {
 114         i40e_status ret_code = I40E_SUCCESS;
 115         u32 total_delay = 0;
 116
 117         if (hw->nvm.blank_nvm_mode)
 118                 return;
 119
 120         ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
 121
 122         /* there are some rare cases when trying to release the resource
 123          * results in an admin Q timeout, so handle them correctly
 124          */
 125         while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
 126                (total_delay < hw->aq.asq_cmd_timeout)) {
 127                 usleep_range(1000, 2000);
 128                 ret_code = i40e_aq_release_resource(hw,
 129                                                     I40E_NVM_RESOURCE_ID,
 130                                                     0, NULL);
 131                 total_delay++;
 132         }
 133 }
 134
 135 /**
 136  * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
 137  * @hw: pointer to the HW structure
 138  *
 139  * Polls the SRCTL Shadow RAM register done bit.
 140  **/
 141 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
 142 {
 143         i40e_status ret_code = I40E_ERR_TIMEOUT;
 144         u32 srctl, wait_cnt;
 145
 146         /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
 147         for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
 148                 srctl = rd32(hw, I40E_GLNVM_SRCTL);
 149                 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
 150                         ret_code = 0;
 151                         break;
 152                 }
 153                 udelay(5);
 154         }
 155         if (ret_code == I40E_ERR_TIMEOUT)
 156                 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
 157         return ret_code;
 158 }
 159
 160 /**
 161  * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
 162  * @hw: pointer to the HW structure
 163  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 164  * @data: word read from the Shadow RAM
 165  *
 166  * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
 167  **/
 168 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
 169                                             u16 *data)
 170 {
 171         i40e_status ret_code = I40E_ERR_TIMEOUT;
 172         u32 sr_reg;
 173
 174         if (offset >= hw->nvm.sr_size) {
 175                 i40e_debug(hw, I40E_DEBUG_NVM,
 176                            "NVM read error: offset %d beyond Shadow RAM limit %d\n",
 177                            offset, hw->nvm.sr_size);
 178                 ret_code = I40E_ERR_PARAM;
 179                 goto read_nvm_exit;
 180         }
 181
 182         /* Poll the done bit first */
 183         ret_code = i40e_poll_sr_srctl_done_bit(hw);
 184         if (!ret_code) {
 185                 /* Write the address and start reading */
 186                 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
 187                          BIT(I40E_GLNVM_SRCTL_START_SHIFT);
 188                 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
 189
 190                 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
 191                 ret_code = i40e_poll_sr_srctl_done_bit(hw);
 192                 if (!ret_code) {
 193                         sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
 194                         *data = (u16)((sr_reg &
 195                                        I40E_GLNVM_SRDATA_RDDATA_MASK)
 196                                     >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
 197                 }
 198         }
 199         if (ret_code)
 200                 i40e_debug(hw, I40E_DEBUG_NVM,
 201                            "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
 202                            offset);
 203
 204 read_nvm_exit:
 205         return ret_code;
 206 }
 207
 208 /**
 209  * i40e_read_nvm_aq - Read Shadow RAM.
 210  * @hw: pointer to the HW structure.
 211  * @module_pointer: module pointer location in words from the NVM beginning
 212  * @offset: offset in words from module start
 213  * @words: number of words to write
 214  * @data: buffer with words to write to the Shadow RAM
 215  * @last_command: tells the AdminQ that this is the last command
 216  *
 217  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 218  **/
 219 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw,
 220                                     u8 module_pointer, u32 offset,
 221                                     u16 words, void *data,
 222                                     bool last_command)
 223 {
 224         i40e_status ret_code = I40E_ERR_NVM;
 225         struct i40e_asq_cmd_details cmd_details;
 226
 227         memset(&cmd_details, 0, sizeof(cmd_details));
 228         cmd_details.wb_desc = &hw->nvm_wb_desc;
 229
 230         /* Here we are checking the SR limit only for the flat memory model.
 231          * We cannot do it for the module-based model, as we did not acquire
 232          * the NVM resource yet (we cannot get the module pointer value).
 233          * Firmware will check the module-based model.
 234          */
 235         if ((offset + words) > hw->nvm.sr_size)
 236                 i40e_debug(hw, I40E_DEBUG_NVM,
 237                            "NVM write error: offset %d beyond Shadow RAM limit %d\n",
 238                            (offset + words), hw->nvm.sr_size);
 239         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 240                 /* We can write only up to 4KB (one sector), in one AQ write */
 241                 i40e_debug(hw, I40E_DEBUG_NVM,
 242                            "NVM write fail error: tried to write %d words, limit is %d.\n",
 243                            words, I40E_SR_SECTOR_SIZE_IN_WORDS);
 244         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 245                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 246                 /* A single write cannot spread over two sectors */
 247                 i40e_debug(hw, I40E_DEBUG_NVM,
 248                            "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
 249                            offset, words);
 250         else
 251                 ret_code = i40e_aq_read_nvm(hw, module_pointer,
 252                                             2 * offset,  /*bytes*/
 253                                             2 * words,   /*bytes*/
 254                                             data, last_command, &cmd_details);
 255
 256         return ret_code;
 257 }
 258
 259 /**
 260  * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
 261  * @hw: pointer to the HW structure
 262  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 263  * @data: word read from the Shadow RAM
 264  *
 265  * Reads one 16 bit word from the Shadow RAM using the AdminQ
 266  **/
 267 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
 268                                          u16 *data)
 269 {
 270         i40e_status ret_code = I40E_ERR_TIMEOUT;
 271
 272         ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
 273         *data = le16_to_cpu(*(__le16 *)data);
 274
 275         return ret_code;
 276 }
 277
 278 /**
 279  * __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking
 280  * @hw: pointer to the HW structure
 281  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 282  * @data: word read from the Shadow RAM
 283  *
 284  * Reads one 16 bit word from the Shadow RAM.
 285  *
 286  * Do not use this function except in cases where the nvm lock is already
 287  * taken via i40e_acquire_nvm().
 288  **/
 289 static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw,
 290                                         u16 offset, u16 *data)
 291 {
 292         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
 293                 return i40e_read_nvm_word_aq(hw, offset, data);
 294
 295         return i40e_read_nvm_word_srctl(hw, offset, data);
 296 }
 297
 298 /**
 299  * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary
 300  * @hw: pointer to the HW structure
 301  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 302  * @data: word read from the Shadow RAM
 303  *
 304  * Reads one 16 bit word from the Shadow RAM.
 305  **/
 306 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
 307                                u16 *data)
 308 {
 309         i40e_status ret_code = 0;
 310
 311         if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
 312                 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 313         if (ret_code)
 314                 return ret_code;
 315
 316         ret_code = __i40e_read_nvm_word(hw, offset, data);
 317
 318         if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
 319                 i40e_release_nvm(hw);
 320
 321         return ret_code;
 322 }
 323
 324 /**
 325  * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
 326  * @hw: pointer to the HW structure
 327  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 328  * @words: (in) number of words to read; (out) number of words actually read
 329  * @data: words read from the Shadow RAM
 330  *
 331  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 332  * method. The buffer read is preceded by the NVM ownership take
 333  * and followed by the release.
 334  **/
 335 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
 336                                               u16 *words, u16 *data)
 337 {
 338         i40e_status ret_code = 0;
 339         u16 index, word;
 340
 341         /* Loop thru the selected region */
 342         for (word = 0; word < *words; word++) {
 343                 index = offset + word;
 344                 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
 345                 if (ret_code)
 346                         break;
 347         }
 348
 349         /* Update the number of words read from the Shadow RAM */
 350         *words = word;
 351
 352         return ret_code;
 353 }
 354
 355 /**
 356  * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
 357  * @hw: pointer to the HW structure
 358  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 359  * @words: (in) number of words to read; (out) number of words actually read
 360  * @data: words read from the Shadow RAM
 361  *
 362  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
 363  * method. The buffer read is preceded by the NVM ownership take
 364  * and followed by the release.
 365  **/
 366 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
 367                                            u16 *words, u16 *data)
 368 {
 369         i40e_status ret_code;
 370         u16 read_size;
 371         bool last_cmd = false;
 372         u16 words_read = 0;
 373         u16 i = 0;
 374
 375         do {
 376                 /* Calculate number of bytes we should read in this step.
 377                  * FVL AQ do not allow to read more than one page at a time or
 378                  * to cross page boundaries.
 379                  */
 380                 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
 381                         read_size = min(*words,
 382                                         (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
 383                                       (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
 384                 else
 385                         read_size = min((*words - words_read),
 386                                         I40E_SR_SECTOR_SIZE_IN_WORDS);
 387
 388                 /* Check if this is last command, if so set proper flag */
 389                 if ((words_read + read_size) >= *words)
 390                         last_cmd = true;
 391
 392                 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
 393                                             data + words_read, last_cmd);
 394                 if (ret_code)
 395                         goto read_nvm_buffer_aq_exit;
 396
 397                 /* Increment counter for words already read and move offset to
 398                  * new read location
 399                  */
 400                 words_read += read_size;
 401                 offset += read_size;
 402         } while (words_read < *words);
 403
 404         for (i = 0; i < *words; i++)
 405                 data[i] = le16_to_cpu(((__le16 *)data)[i]);
 406
 407 read_nvm_buffer_aq_exit:
 408         *words = words_read;
 409         return ret_code;
 410 }
 411
 412 /**
 413  * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock
 414  * @hw: pointer to the HW structure
 415  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 416  * @words: (in) number of words to read; (out) number of words actually read
 417  * @data: words read from the Shadow RAM
 418  *
 419  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 420  * method.
 421  **/
 422 static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
 423                                           u16 offset, u16 *words,
 424                                           u16 *data)
 425 {
 426         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
 427                 return i40e_read_nvm_buffer_aq(hw, offset, words, data);
 428
 429         return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
 430 }
 431
 432 /**
 433  * i40e_write_nvm_aq - Writes Shadow RAM.
 434  * @hw: pointer to the HW structure.
 435  * @module_pointer: module pointer location in words from the NVM beginning
 436  * @offset: offset in words from module start
 437  * @words: number of words to write
 438  * @data: buffer with words to write to the Shadow RAM
 439  * @last_command: tells the AdminQ that this is the last command
 440  *
 441  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 442  **/
 443 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
 444                                      u32 offset, u16 words, void *data,
 445                                      bool last_command)
 446 {
 447         i40e_status ret_code = I40E_ERR_NVM;
 448         struct i40e_asq_cmd_details cmd_details;
 449
 450         memset(&cmd_details, 0, sizeof(cmd_details));
 451         cmd_details.wb_desc = &hw->nvm_wb_desc;
 452
 453         /* Here we are checking the SR limit only for the flat memory model.
 454          * We cannot do it for the module-based model, as we did not acquire
 455          * the NVM resource yet (we cannot get the module pointer value).
 456          * Firmware will check the module-based model.
 457          */
 458         if ((offset + words) > hw->nvm.sr_size)
 459                 i40e_debug(hw, I40E_DEBUG_NVM,
 460                            "NVM write error: offset %d beyond Shadow RAM limit %d\n",
 461                            (offset + words), hw->nvm.sr_size);
 462         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 463                 /* We can write only up to 4KB (one sector), in one AQ write */
 464                 i40e_debug(hw, I40E_DEBUG_NVM,
 465                            "NVM write fail error: tried to write %d words, limit is %d.\n",
 466                            words, I40E_SR_SECTOR_SIZE_IN_WORDS);
 467         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 468                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 469                 /* A single write cannot spread over two sectors */
 470                 i40e_debug(hw, I40E_DEBUG_NVM,
 471                            "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
 472                            offset, words);
 473         else
 474                 ret_code = i40e_aq_update_nvm(hw, module_pointer,
 475                                               2 * offset,  /*bytes*/
 476                                               2 * words,   /*bytes*/
 477                                               data, last_command, 0,
 478                                               &cmd_details);
 479
 480         return ret_code;
 481 }
 482
 483 /**
 484  * i40e_calc_nvm_checksum - Calculates and returns the checksum
 485  * @hw: pointer to hardware structure
 486  * @checksum: pointer to the checksum
 487  *
 488  * This function calculates SW Checksum that covers the whole 64kB shadow RAM
 489  * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
 490  * is customer specific and unknown. Therefore, this function skips all maximum
 491  * possible size of VPD (1kB).
 492  **/
 493 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
 494                                                     u16 *checksum)
 495 {
 496         i40e_status ret_code;
 497         struct i40e_virt_mem vmem;
 498         u16 pcie_alt_module = 0;
 499         u16 checksum_local = 0;
 500         u16 vpd_module = 0;
 501         u16 *data;
 502         u16 i = 0;
 503
 504         ret_code = i40e_allocate_virt_mem(hw, &vmem,
 505                                     I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
 506         if (ret_code)
 507                 goto i40e_calc_nvm_checksum_exit;
 508         data = (u16 *)vmem.va;
 509
 510         /* read pointer to VPD area */
 511         ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
 512         if (ret_code) {
 513                 ret_code = I40E_ERR_NVM_CHECKSUM;
 514                 goto i40e_calc_nvm_checksum_exit;
 515         }
 516
 517         /* read pointer to PCIe Alt Auto-load module */
 518         ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
 519                                         &pcie_alt_module);
 520         if (ret_code) {
 521                 ret_code = I40E_ERR_NVM_CHECKSUM;
 522                 goto i40e_calc_nvm_checksum_exit;
 523         }
 524
 525         /* Calculate SW checksum that covers the whole 64kB shadow RAM
 526          * except the VPD and PCIe ALT Auto-load modules
 527          */
 528         for (i = 0; i < hw->nvm.sr_size; i++) {
 529                 /* Read SR page */
 530                 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
 531                         u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
 532
 533                         ret_code = __i40e_read_nvm_buffer(hw, i, &words, data);
 534                         if (ret_code) {
 535                                 ret_code = I40E_ERR_NVM_CHECKSUM;
 536                                 goto i40e_calc_nvm_checksum_exit;
 537                         }
 538                 }
 539
 540                 /* Skip Checksum word */
 541                 if (i == I40E_SR_SW_CHECKSUM_WORD)
 542                         continue;
 543                 /* Skip VPD module (convert byte size to word count) */
 544                 if ((i >= (u32)vpd_module) &&
 545                     (i < ((u32)vpd_module +
 546                      (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
 547                         continue;
 548                 }
 549                 /* Skip PCIe ALT module (convert byte size to word count) */
 550                 if ((i >= (u32)pcie_alt_module) &&
 551                     (i < ((u32)pcie_alt_module +
 552                      (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
 553                         continue;
 554                 }
 555
 556                 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
 557         }
 558
 559         *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
 560
 561 i40e_calc_nvm_checksum_exit:
 562         i40e_free_virt_mem(hw, &vmem);
 563         return ret_code;
 564 }
 565
 566 /**
 567  * i40e_update_nvm_checksum - Updates the NVM checksum
 568  * @hw: pointer to hardware structure
 569  *
 570  * NVM ownership must be acquired before calling this function and released
 571  * on ARQ completion event reception by caller.
 572  * This function will commit SR to NVM.
 573  **/
 574 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
 575 {
 576         i40e_status ret_code;
 577         u16 checksum;
 578         __le16 le_sum;
 579
 580         ret_code = i40e_calc_nvm_checksum(hw, &checksum);
 581         if (!ret_code) {
 582                 le_sum = cpu_to_le16(checksum);
 583                 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
 584                                              1, &le_sum, true);
 585         }
 586
 587         return ret_code;
 588 }
 589
 590 /**
 591  * i40e_validate_nvm_checksum - Validate EEPROM checksum
 592  * @hw: pointer to hardware structure
 593  * @checksum: calculated checksum
 594  *
 595  * Performs checksum calculation and validates the NVM SW checksum. If the
 596  * caller does not need checksum, the value can be NULL.
 597  **/
 598 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
 599                                                  u16 *checksum)
 600 {
 601         i40e_status ret_code = 0;
 602         u16 checksum_sr = 0;
 603         u16 checksum_local = 0;
 604
 605         /* We must acquire the NVM lock in order to correctly synchronize the
 606          * NVM accesses across multiple PFs. Without doing so it is possible
 607          * for one of the PFs to read invalid data potentially indicating that
 608          * the checksum is invalid.
 609          */
 610         ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 611         if (ret_code)
 612                 return ret_code;
 613         ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
 614         __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
 615         i40e_release_nvm(hw);
 616         if (ret_code)
 617                 return ret_code;
 618
 619         /* Verify read checksum from EEPROM is the same as
 620          * calculated checksum
 621          */
 622         if (checksum_local != checksum_sr)
 623                 ret_code = I40E_ERR_NVM_CHECKSUM;
 624
 625         /* If the user cares, return the calculated checksum */
 626         if (checksum)
 627                 *checksum = checksum_local;
 628
 629         return ret_code;
 630 }
 631
 632 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
 633                                           struct i40e_nvm_access *cmd,
 634                                           u8 *bytes, int *perrno);
 635 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
 636                                              struct i40e_nvm_access *cmd,
 637                                              u8 *bytes, int *perrno);
 638 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
 639                                              struct i40e_nvm_access *cmd,
 640                                              u8 *bytes, int *errno);
 641 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
 642                                                 struct i40e_nvm_access *cmd,
 643                                                 int *perrno);
 644 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
 645                                          struct i40e_nvm_access *cmd,
 646                                          int *perrno);
 647 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
 648                                          struct i40e_nvm_access *cmd,
 649                                          u8 *bytes, int *perrno);
 650 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
 651                                         struct i40e_nvm_access *cmd,
 652                                         u8 *bytes, int *perrno);
 653 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
 654                                        struct i40e_nvm_access *cmd,
 655                                        u8 *bytes, int *perrno);
 656 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
 657                                              struct i40e_nvm_access *cmd,
 658                                              u8 *bytes, int *perrno);
 659 static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
 660                                             struct i40e_nvm_access *cmd,
 661                                             u8 *bytes, int *perrno);
 662 static inline u8 i40e_nvmupd_get_module(u32 val)
 663 {
 664         return (u8)(val & I40E_NVM_MOD_PNT_MASK);
 665 }
 666 static inline u8 i40e_nvmupd_get_transaction(u32 val)
 667 {
 668         return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
 669 }
 670
 671 static inline u8 i40e_nvmupd_get_preservation_flags(u32 val)
 672 {
 673         return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >>
 674                     I40E_NVM_PRESERVATION_FLAGS_SHIFT);
 675 }
 676
 677 static const char * const i40e_nvm_update_state_str[] = {
 678         "I40E_NVMUPD_INVALID",
 679         "I40E_NVMUPD_READ_CON",
 680         "I40E_NVMUPD_READ_SNT",
 681         "I40E_NVMUPD_READ_LCB",
 682         "I40E_NVMUPD_READ_SA",
 683         "I40E_NVMUPD_WRITE_ERA",
 684         "I40E_NVMUPD_WRITE_CON",
 685         "I40E_NVMUPD_WRITE_SNT",
 686         "I40E_NVMUPD_WRITE_LCB",
 687         "I40E_NVMUPD_WRITE_SA",
 688         "I40E_NVMUPD_CSUM_CON",
 689         "I40E_NVMUPD_CSUM_SA",
 690         "I40E_NVMUPD_CSUM_LCB",
 691         "I40E_NVMUPD_STATUS",
 692         "I40E_NVMUPD_EXEC_AQ",
 693         "I40E_NVMUPD_GET_AQ_RESULT",
 694         "I40E_NVMUPD_GET_AQ_EVENT",
 695 };
 696
 697 /**
 698  * i40e_nvmupd_command - Process an NVM update command
 699  * @hw: pointer to hardware structure
 700  * @cmd: pointer to nvm update command
 701  * @bytes: pointer to the data buffer
 702  * @perrno: pointer to return error code
 703  *
 704  * Dispatches command depending on what update state is current
 705  **/
 706 i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
 707                                 struct i40e_nvm_access *cmd,
 708                                 u8 *bytes, int *perrno)
 709 {
 710         i40e_status status;
 711         enum i40e_nvmupd_cmd upd_cmd;
 712
 713         /* assume success */
 714         *perrno = 0;
 715
 716         /* early check for status command and debug msgs */
 717         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 718
 719         i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n",
 720                    i40e_nvm_update_state_str[upd_cmd],
 721                    hw->nvmupd_state,
 722                    hw->nvm_release_on_done, hw->nvm_wait_opcode,
 723                    cmd->command, cmd->config, cmd->offset, cmd->data_size);
 724
 725         if (upd_cmd == I40E_NVMUPD_INVALID) {
 726                 *perrno = -EFAULT;
 727                 i40e_debug(hw, I40E_DEBUG_NVM,
 728                            "i40e_nvmupd_validate_command returns %d errno %d\n",
 729                            upd_cmd, *perrno);
 730         }
 731
 732         /* a status request returns immediately rather than
 733          * going into the state machine
 734          */
 735         if (upd_cmd == I40E_NVMUPD_STATUS) {
 736                 if (!cmd->data_size) {
 737                         *perrno = -EFAULT;
 738                         return I40E_ERR_BUF_TOO_SHORT;
 739                 }
 740
 741                 bytes[0] = hw->nvmupd_state;
 742
 743                 if (cmd->data_size >= 4) {
 744                         bytes[1] = 0;
 745                         *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
 746                 }
 747
 748                 /* Clear error status on read */
 749                 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
 750                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 751
 752                 return 0;
 753         }
 754
 755         /* Clear status even it is not read and log */
 756         if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
 757                 i40e_debug(hw, I40E_DEBUG_NVM,
 758                            "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
 759                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 760         }
 761
 762         /* Acquire lock to prevent race condition where adminq_task
 763          * can execute after i40e_nvmupd_nvm_read/write but before state
 764          * variables (nvm_wait_opcode, nvm_release_on_done) are updated.
 765          *
 766          * During NVMUpdate, it is observed that lock could be held for
 767          * ~5ms for most commands. However lock is held for ~60ms for
 768          * NVMUPD_CSUM_LCB command.
 769          */
 770         mutex_lock(&hw->aq.arq_mutex);
 771         switch (hw->nvmupd_state) {
 772         case I40E_NVMUPD_STATE_INIT:
 773                 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
 774                 break;
 775
 776         case I40E_NVMUPD_STATE_READING:
 777                 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
 778                 break;
 779
 780         case I40E_NVMUPD_STATE_WRITING:
 781                 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
 782                 break;
 783
 784         case I40E_NVMUPD_STATE_INIT_WAIT:
 785         case I40E_NVMUPD_STATE_WRITE_WAIT:
 786                 /* if we need to stop waiting for an event, clear
 787                  * the wait info and return before doing anything else
 788                  */
 789                 if (cmd->offset == 0xffff) {
 790                         i40e_nvmupd_clear_wait_state(hw);
 791                         status = 0;
 792                         break;
 793                 }
 794
 795                 status = I40E_ERR_NOT_READY;
 796                 *perrno = -EBUSY;
 797                 break;
 798
 799         default:
 800                 /* invalid state, should never happen */
 801                 i40e_debug(hw, I40E_DEBUG_NVM,
 802                            "NVMUPD: no such state %d\n", hw->nvmupd_state);
 803                 status = I40E_NOT_SUPPORTED;
 804                 *perrno = -ESRCH;
 805                 break;
 806         }
 807
 808         mutex_unlock(&hw->aq.arq_mutex);
 809         return status;
 810 }
 811
 812 /**
 813  * i40e_nvmupd_state_init - Handle NVM update state Init
 814  * @hw: pointer to hardware structure
 815  * @cmd: pointer to nvm update command buffer
 816  * @bytes: pointer to the data buffer
 817  * @perrno: pointer to return error code
 818  *
 819  * Process legitimate commands of the Init state and conditionally set next
 820  * state. Reject all other commands.
 821  **/
 822 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
 823                                           struct i40e_nvm_access *cmd,
 824                                           u8 *bytes, int *perrno)
 825 {
 826         i40e_status status = 0;
 827         enum i40e_nvmupd_cmd upd_cmd;
 828
 829         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 830
 831         switch (upd_cmd) {
 832         case I40E_NVMUPD_READ_SA:
 833                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 834                 if (status) {
 835                         *perrno = i40e_aq_rc_to_posix(status,
 836                                                      hw->aq.asq_last_status);
 837                 } else {
 838                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 839                         i40e_release_nvm(hw);
 840                 }
 841                 break;
 842
 843         case I40E_NVMUPD_READ_SNT:
 844                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 845                 if (status) {
 846                         *perrno = i40e_aq_rc_to_posix(status,
 847                                                      hw->aq.asq_last_status);
 848                 } else {
 849                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 850                         if (status)
 851                                 i40e_release_nvm(hw);
 852                         else
 853                                 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
 854                 }
 855                 break;
 856
 857         case I40E_NVMUPD_WRITE_ERA:
 858                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 859                 if (status) {
 860                         *perrno = i40e_aq_rc_to_posix(status,
 861                                                      hw->aq.asq_last_status);
 862                 } else {
 863                         status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
 864                         if (status) {
 865                                 i40e_release_nvm(hw);
 866                         } else {
 867                                 hw->nvm_release_on_done = true;
 868                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase;
 869                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 870                         }
 871                 }
 872                 break;
 873
 874         case I40E_NVMUPD_WRITE_SA:
 875                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 876                 if (status) {
 877                         *perrno = i40e_aq_rc_to_posix(status,
 878                                                      hw->aq.asq_last_status);
 879                 } else {
 880                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 881                         if (status) {
 882                                 i40e_release_nvm(hw);
 883                         } else {
 884                                 hw->nvm_release_on_done = true;
 885                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 886                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 887                         }
 888                 }
 889                 break;
 890
 891         case I40E_NVMUPD_WRITE_SNT:
 892                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 893                 if (status) {
 894                         *perrno = i40e_aq_rc_to_posix(status,
 895                                                      hw->aq.asq_last_status);
 896                 } else {
 897                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 898                         if (status) {
 899                                 i40e_release_nvm(hw);
 900                         } else {
 901                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 902                                 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
 903                         }
 904                 }
 905                 break;
 906
 907         case I40E_NVMUPD_CSUM_SA:
 908                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 909                 if (status) {
 910                         *perrno = i40e_aq_rc_to_posix(status,
 911                                                      hw->aq.asq_last_status);
 912                 } else {
 913                         status = i40e_update_nvm_checksum(hw);
 914                         if (status) {
 915                                 *perrno = hw->aq.asq_last_status ?
 916                                    i40e_aq_rc_to_posix(status,
 917                                                        hw->aq.asq_last_status) :
 918                                    -EIO;
 919                                 i40e_release_nvm(hw);
 920                         } else {
 921                                 hw->nvm_release_on_done = true;
 922                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 923                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 924                         }
 925                 }
 926                 break;
 927
 928         case I40E_NVMUPD_EXEC_AQ:
 929                 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
 930                 break;
 931
 932         case I40E_NVMUPD_GET_AQ_RESULT:
 933                 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
 934                 break;
 935
 936         case I40E_NVMUPD_GET_AQ_EVENT:
 937                 status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno);
 938                 break;
 939
 940         default:
 941                 i40e_debug(hw, I40E_DEBUG_NVM,
 942                            "NVMUPD: bad cmd %s in init state\n",
 943                            i40e_nvm_update_state_str[upd_cmd]);
 944                 status = I40E_ERR_NVM;
 945                 *perrno = -ESRCH;
 946                 break;
 947         }
 948         return status;
 949 }
 950
 951 /**
 952  * i40e_nvmupd_state_reading - Handle NVM update state Reading
 953  * @hw: pointer to hardware structure
 954  * @cmd: pointer to nvm update command buffer
 955  * @bytes: pointer to the data buffer
 956  * @perrno: pointer to return error code
 957  *
 958  * NVM ownership is already held.  Process legitimate commands and set any
 959  * change in state; reject all other commands.
 960  **/
 961 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
 962                                              struct i40e_nvm_access *cmd,
 963                                              u8 *bytes, int *perrno)
 964 {
 965         i40e_status status = 0;
 966         enum i40e_nvmupd_cmd upd_cmd;
 967
 968         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 969
 970         switch (upd_cmd) {
 971         case I40E_NVMUPD_READ_SA:
 972         case I40E_NVMUPD_READ_CON:
 973                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 974                 break;
 975
 976         case I40E_NVMUPD_READ_LCB:
 977                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 978                 i40e_release_nvm(hw);
 979                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 980                 break;
 981
 982         default:
 983                 i40e_debug(hw, I40E_DEBUG_NVM,
 984                            "NVMUPD: bad cmd %s in reading state.\n",
 985                            i40e_nvm_update_state_str[upd_cmd]);
 986                 status = I40E_NOT_SUPPORTED;
 987                 *perrno = -ESRCH;
 988                 break;
 989         }
 990         return status;
 991 }
 992
 993 /**
 994  * i40e_nvmupd_state_writing - Handle NVM update state Writing
 995  * @hw: pointer to hardware structure
 996  * @cmd: pointer to nvm update command buffer
 997  * @bytes: pointer to the data buffer
 998  * @perrno: pointer to return error code
 999  *
1000  * NVM ownership is already held.  Process legitimate commands and set any
1001  * change in state; reject all other commands
1002  **/
1003 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
1004                                              struct i40e_nvm_access *cmd,
1005                                              u8 *bytes, int *perrno)
1006 {
1007         i40e_status status = 0;
1008         enum i40e_nvmupd_cmd upd_cmd;
1009         bool retry_attempt = false;
1010
1011         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1012
1013 retry:
1014         switch (upd_cmd) {
1015         case I40E_NVMUPD_WRITE_CON:
1016                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1017                 if (!status) {
1018                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1019                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1020                 }
1021                 break;
1022
1023         case I40E_NVMUPD_WRITE_LCB:
1024                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1025                 if (status) {
1026                         *perrno = hw->aq.asq_last_status ?
1027                                    i40e_aq_rc_to_posix(status,
1028                                                        hw->aq.asq_last_status) :
1029                                    -EIO;
1030                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1031                 } else {
1032                         hw->nvm_release_on_done = true;
1033                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1034                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1035                 }
1036                 break;
1037
1038         case I40E_NVMUPD_CSUM_CON:
1039                 /* Assumes the caller has acquired the nvm */
1040                 status = i40e_update_nvm_checksum(hw);
1041                 if (status) {
1042                         *perrno = hw->aq.asq_last_status ?
1043                                    i40e_aq_rc_to_posix(status,
1044                                                        hw->aq.asq_last_status) :
1045                                    -EIO;
1046                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1047                 } else {
1048                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1049                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1050                 }
1051                 break;
1052
1053         case I40E_NVMUPD_CSUM_LCB:
1054                 /* Assumes the caller has acquired the nvm */
1055                 status = i40e_update_nvm_checksum(hw);
1056                 if (status) {
1057                         *perrno = hw->aq.asq_last_status ?
1058                                    i40e_aq_rc_to_posix(status,
1059                                                        hw->aq.asq_last_status) :
1060                                    -EIO;
1061                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1062                 } else {
1063                         hw->nvm_release_on_done = true;
1064                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1065                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1066                 }
1067                 break;
1068
1069         default:
1070                 i40e_debug(hw, I40E_DEBUG_NVM,
1071                            "NVMUPD: bad cmd %s in writing state.\n",
1072                            i40e_nvm_update_state_str[upd_cmd]);
1073                 status = I40E_NOT_SUPPORTED;
1074                 *perrno = -ESRCH;
1075                 break;
1076         }
1077
1078         /* In some circumstances, a multi-write transaction takes longer
1079          * than the default 3 minute timeout on the write semaphore.  If
1080          * the write failed with an EBUSY status, this is likely the problem,
1081          * so here we try to reacquire the semaphore then retry the write.
1082          * We only do one retry, then give up.
1083          */
1084         if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1085             !retry_attempt) {
1086                 i40e_status old_status = status;
1087                 u32 old_asq_status = hw->aq.asq_last_status;
1088                 u32 gtime;
1089
1090                 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1091                 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1092                         i40e_debug(hw, I40E_DEBUG_ALL,
1093                                    "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1094                                    gtime, hw->nvm.hw_semaphore_timeout);
1095                         i40e_release_nvm(hw);
1096                         status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1097                         if (status) {
1098                                 i40e_debug(hw, I40E_DEBUG_ALL,
1099                                            "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1100                                            hw->aq.asq_last_status);
1101                                 status = old_status;
1102                                 hw->aq.asq_last_status = old_asq_status;
1103                         } else {
1104                                 retry_attempt = true;
1105                                 goto retry;
1106                         }
1107                 }
1108         }
1109
1110         return status;
1111 }
1112
1113 /**
1114  * i40e_nvmupd_clear_wait_state - clear wait state on hw
1115  * @hw: pointer to the hardware structure
1116  **/
1117 void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw)
1118 {
1119         i40e_debug(hw, I40E_DEBUG_NVM,
1120                    "NVMUPD: clearing wait on opcode 0x%04x\n",
1121                    hw->nvm_wait_opcode);
1122
1123         if (hw->nvm_release_on_done) {
1124                 i40e_release_nvm(hw);
1125                 hw->nvm_release_on_done = false;
1126         }
1127         hw->nvm_wait_opcode = 0;
1128
1129         if (hw->aq.arq_last_status) {
1130                 hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
1131                 return;
1132         }
1133
1134         switch (hw->nvmupd_state) {
1135         case I40E_NVMUPD_STATE_INIT_WAIT:
1136                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1137                 break;
1138
1139         case I40E_NVMUPD_STATE_WRITE_WAIT:
1140                 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1141                 break;
1142
1143         default:
1144                 break;
1145         }
1146 }
1147
1148 /**
1149  * i40e_nvmupd_check_wait_event - handle NVM update operation events
1150  * @hw: pointer to the hardware structure
1151  * @opcode: the event that just happened
1152  * @desc: AdminQ descriptor
1153  **/
1154 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode,
1155                                   struct i40e_aq_desc *desc)
1156 {
1157         u32 aq_desc_len = sizeof(struct i40e_aq_desc);
1158
1159         if (opcode == hw->nvm_wait_opcode) {
1160                 memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len);
1161                 i40e_nvmupd_clear_wait_state(hw);
1162         }
1163 }
1164
1165 /**
1166  * i40e_nvmupd_validate_command - Validate given command
1167  * @hw: pointer to hardware structure
1168  * @cmd: pointer to nvm update command buffer
1169  * @perrno: pointer to return error code
1170  *
1171  * Return one of the valid command types or I40E_NVMUPD_INVALID
1172  **/
1173 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1174                                                  struct i40e_nvm_access *cmd,
1175                                                  int *perrno)
1176 {
1177         enum i40e_nvmupd_cmd upd_cmd;
1178         u8 module, transaction;
1179
1180         /* anything that doesn't match a recognized case is an error */
1181         upd_cmd = I40E_NVMUPD_INVALID;
1182
1183         transaction = i40e_nvmupd_get_transaction(cmd->config);
1184         module = i40e_nvmupd_get_module(cmd->config);
1185
1186         /* limits on data size */
1187         if ((cmd->data_size < 1) ||
1188             (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1189                 i40e_debug(hw, I40E_DEBUG_NVM,
1190                            "i40e_nvmupd_validate_command data_size %d\n",
1191                            cmd->data_size);
1192                 *perrno = -EFAULT;
1193                 return I40E_NVMUPD_INVALID;
1194         }
1195
1196         switch (cmd->command) {
1197         case I40E_NVM_READ:
1198                 switch (transaction) {
1199                 case I40E_NVM_CON:
1200                         upd_cmd = I40E_NVMUPD_READ_CON;
1201                         break;
1202                 case I40E_NVM_SNT:
1203                         upd_cmd = I40E_NVMUPD_READ_SNT;
1204                         break;
1205                 case I40E_NVM_LCB:
1206                         upd_cmd = I40E_NVMUPD_READ_LCB;
1207                         break;
1208                 case I40E_NVM_SA:
1209                         upd_cmd = I40E_NVMUPD_READ_SA;
1210                         break;
1211                 case I40E_NVM_EXEC:
1212                         if (module == 0xf)
1213                                 upd_cmd = I40E_NVMUPD_STATUS;
1214                         else if (module == 0)
1215                                 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1216                         break;
1217                 case I40E_NVM_AQE:
1218                         upd_cmd = I40E_NVMUPD_GET_AQ_EVENT;
1219                         break;
1220                 }
1221                 break;
1222
1223         case I40E_NVM_WRITE:
1224                 switch (transaction) {
1225                 case I40E_NVM_CON:
1226                         upd_cmd = I40E_NVMUPD_WRITE_CON;
1227                         break;
1228                 case I40E_NVM_SNT:
1229                         upd_cmd = I40E_NVMUPD_WRITE_SNT;
1230                         break;
1231                 case I40E_NVM_LCB:
1232                         upd_cmd = I40E_NVMUPD_WRITE_LCB;
1233                         break;
1234                 case I40E_NVM_SA:
1235                         upd_cmd = I40E_NVMUPD_WRITE_SA;
1236                         break;
1237                 case I40E_NVM_ERA:
1238                         upd_cmd = I40E_NVMUPD_WRITE_ERA;
1239                         break;
1240                 case I40E_NVM_CSUM:
1241                         upd_cmd = I40E_NVMUPD_CSUM_CON;
1242                         break;
1243                 case (I40E_NVM_CSUM|I40E_NVM_SA):
1244                         upd_cmd = I40E_NVMUPD_CSUM_SA;
1245                         break;
1246                 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1247                         upd_cmd = I40E_NVMUPD_CSUM_LCB;
1248                         break;
1249                 case I40E_NVM_EXEC:
1250                         if (module == 0)
1251                                 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1252                         break;
1253                 }
1254                 break;
1255         }
1256
1257         return upd_cmd;
1258 }
1259
1260 /**
1261  * i40e_nvmupd_exec_aq - Run an AQ command
1262  * @hw: pointer to hardware structure
1263  * @cmd: pointer to nvm update command buffer
1264  * @bytes: pointer to the data buffer
1265  * @perrno: pointer to return error code
1266  *
1267  * cmd structure contains identifiers and data buffer
1268  **/
1269 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1270                                        struct i40e_nvm_access *cmd,
1271                                        u8 *bytes, int *perrno)
1272 {
1273         struct i40e_asq_cmd_details cmd_details;
1274         i40e_status status;
1275         struct i40e_aq_desc *aq_desc;
1276         u32 buff_size = 0;
1277         u8 *buff = NULL;
1278         u32 aq_desc_len;
1279         u32 aq_data_len;
1280
1281         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1282         if (cmd->offset == 0xffff)
1283                 return 0;
1284
1285         memset(&cmd_details, 0, sizeof(cmd_details));
1286         cmd_details.wb_desc = &hw->nvm_wb_desc;
1287
1288         aq_desc_len = sizeof(struct i40e_aq_desc);
1289         memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1290
1291         /* get the aq descriptor */
1292         if (cmd->data_size < aq_desc_len) {
1293                 i40e_debug(hw, I40E_DEBUG_NVM,
1294                            "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1295                            cmd->data_size, aq_desc_len);
1296                 *perrno = -EINVAL;
1297                 return I40E_ERR_PARAM;
1298         }
1299         aq_desc = (struct i40e_aq_desc *)bytes;
1300
1301         /* if data buffer needed, make sure it's ready */
1302         aq_data_len = cmd->data_size - aq_desc_len;
1303         buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen));
1304         if (buff_size) {
1305                 if (!hw->nvm_buff.va) {
1306                         status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1307                                                         hw->aq.asq_buf_size);
1308                         if (status)
1309                                 i40e_debug(hw, I40E_DEBUG_NVM,
1310                                            "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1311                                            status);
1312                 }
1313
1314                 if (hw->nvm_buff.va) {
1315                         buff = hw->nvm_buff.va;
1316                         memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1317                 }
1318         }
1319
1320         if (cmd->offset)
1321                 memset(&hw->nvm_aq_event_desc, 0, aq_desc_len);
1322
1323         /* and away we go! */
1324         status = i40e_asq_send_command(hw, aq_desc, buff,
1325                                        buff_size, &cmd_details);
1326         if (status) {
1327                 i40e_debug(hw, I40E_DEBUG_NVM,
1328                            "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1329                            i40e_stat_str(hw, status),
1330                            i40e_aq_str(hw, hw->aq.asq_last_status));
1331                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1332                 return status;
1333         }
1334
1335         /* should we wait for a followup event? */
1336         if (cmd->offset) {
1337                 hw->nvm_wait_opcode = cmd->offset;
1338                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1339         }
1340
1341         return status;
1342 }
1343
1344 /**
1345  * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1346  * @hw: pointer to hardware structure
1347  * @cmd: pointer to nvm update command buffer
1348  * @bytes: pointer to the data buffer
1349  * @perrno: pointer to return error code
1350  *
1351  * cmd structure contains identifiers and data buffer
1352  **/
1353 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1354                                              struct i40e_nvm_access *cmd,
1355                                              u8 *bytes, int *perrno)
1356 {
1357         u32 aq_total_len;
1358         u32 aq_desc_len;
1359         int remainder;
1360         u8 *buff;
1361
1362         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1363
1364         aq_desc_len = sizeof(struct i40e_aq_desc);
1365         aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
1366
1367         /* check offset range */
1368         if (cmd->offset > aq_total_len) {
1369                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1370                            __func__, cmd->offset, aq_total_len);
1371                 *perrno = -EINVAL;
1372                 return I40E_ERR_PARAM;
1373         }
1374
1375         /* check copylength range */
1376         if (cmd->data_size > (aq_total_len - cmd->offset)) {
1377                 int new_len = aq_total_len - cmd->offset;
1378
1379                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1380                            __func__, cmd->data_size, new_len);
1381                 cmd->data_size = new_len;
1382         }
1383
1384         remainder = cmd->data_size;
1385         if (cmd->offset < aq_desc_len) {
1386                 u32 len = aq_desc_len - cmd->offset;
1387
1388                 len = min(len, cmd->data_size);
1389                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1390                            __func__, cmd->offset, cmd->offset + len);
1391
1392                 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1393                 memcpy(bytes, buff, len);
1394
1395                 bytes += len;
1396                 remainder -= len;
1397                 buff = hw->nvm_buff.va;
1398         } else {
1399                 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1400         }
1401
1402         if (remainder > 0) {
1403                 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1404
1405                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1406                            __func__, start_byte, start_byte + remainder);
1407                 memcpy(bytes, buff, remainder);
1408         }
1409
1410         return 0;
1411 }
1412
1413 /**
1414  * i40e_nvmupd_get_aq_event - Get the Admin Queue event from previous exec_aq
1415  * @hw: pointer to hardware structure
1416  * @cmd: pointer to nvm update command buffer
1417  * @bytes: pointer to the data buffer
1418  * @perrno: pointer to return error code
1419  *
1420  * cmd structure contains identifiers and data buffer
1421  **/
1422 static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
1423                                             struct i40e_nvm_access *cmd,
1424                                             u8 *bytes, int *perrno)
1425 {
1426         u32 aq_total_len;
1427         u32 aq_desc_len;
1428
1429         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1430
1431         aq_desc_len = sizeof(struct i40e_aq_desc);
1432         aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_aq_event_desc.datalen);
1433
1434         /* check copylength range */
1435         if (cmd->data_size > aq_total_len) {
1436                 i40e_debug(hw, I40E_DEBUG_NVM,
1437                            "%s: copy length %d too big, trimming to %d\n",
1438                            __func__, cmd->data_size, aq_total_len);
1439                 cmd->data_size = aq_total_len;
1440         }
1441
1442         memcpy(bytes, &hw->nvm_aq_event_desc, cmd->data_size);
1443
1444         return 0;
1445 }
1446
1447 /**
1448  * i40e_nvmupd_nvm_read - Read NVM
1449  * @hw: pointer to hardware structure
1450  * @cmd: pointer to nvm update command buffer
1451  * @bytes: pointer to the data buffer
1452  * @perrno: pointer to return error code
1453  *
1454  * cmd structure contains identifiers and data buffer
1455  **/
1456 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1457                                         struct i40e_nvm_access *cmd,
1458                                         u8 *bytes, int *perrno)
1459 {
1460         struct i40e_asq_cmd_details cmd_details;
1461         i40e_status status;
1462         u8 module, transaction;
1463         bool last;
1464
1465         transaction = i40e_nvmupd_get_transaction(cmd->config);
1466         module = i40e_nvmupd_get_module(cmd->config);
1467         last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1468
1469         memset(&cmd_details, 0, sizeof(cmd_details));
1470         cmd_details.wb_desc = &hw->nvm_wb_desc;
1471
1472         status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1473                                   bytes, last, &cmd_details);
1474         if (status) {
1475                 i40e_debug(hw, I40E_DEBUG_NVM,
1476                            "i40e_nvmupd_nvm_read mod 0x%x  off 0x%x  len 0x%x\n",
1477                            module, cmd->offset, cmd->data_size);
1478                 i40e_debug(hw, I40E_DEBUG_NVM,
1479                            "i40e_nvmupd_nvm_read status %d aq %d\n",
1480                            status, hw->aq.asq_last_status);
1481                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1482         }
1483
1484         return status;
1485 }
1486
1487 /**
1488  * i40e_nvmupd_nvm_erase - Erase an NVM module
1489  * @hw: pointer to hardware structure
1490  * @cmd: pointer to nvm update command buffer
1491  * @perrno: pointer to return error code
1492  *
1493  * module, offset, data_size and data are in cmd structure
1494  **/
1495 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1496                                          struct i40e_nvm_access *cmd,
1497                                          int *perrno)
1498 {
1499         i40e_status status = 0;
1500         struct i40e_asq_cmd_details cmd_details;
1501         u8 module, transaction;
1502         bool last;
1503
1504         transaction = i40e_nvmupd_get_transaction(cmd->config);
1505         module = i40e_nvmupd_get_module(cmd->config);
1506         last = (transaction & I40E_NVM_LCB);
1507
1508         memset(&cmd_details, 0, sizeof(cmd_details));
1509         cmd_details.wb_desc = &hw->nvm_wb_desc;
1510
1511         status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1512                                    last, &cmd_details);
1513         if (status) {
1514                 i40e_debug(hw, I40E_DEBUG_NVM,
1515                            "i40e_nvmupd_nvm_erase mod 0x%x  off 0x%x len 0x%x\n",
1516                            module, cmd->offset, cmd->data_size);
1517                 i40e_debug(hw, I40E_DEBUG_NVM,
1518                            "i40e_nvmupd_nvm_erase status %d aq %d\n",
1519                            status, hw->aq.asq_last_status);
1520                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1521         }
1522
1523         return status;
1524 }
1525
1526 /**
1527  * i40e_nvmupd_nvm_write - Write NVM
1528  * @hw: pointer to hardware structure
1529  * @cmd: pointer to nvm update command buffer
1530  * @bytes: pointer to the data buffer
1531  * @perrno: pointer to return error code
1532  *
1533  * module, offset, data_size and data are in cmd structure
1534  **/
1535 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1536                                          struct i40e_nvm_access *cmd,
1537                                          u8 *bytes, int *perrno)
1538 {
1539         i40e_status status = 0;
1540         struct i40e_asq_cmd_details cmd_details;
1541         u8 module, transaction;
1542         u8 preservation_flags;
1543         bool last;
1544
1545         transaction = i40e_nvmupd_get_transaction(cmd->config);
1546         module = i40e_nvmupd_get_module(cmd->config);
1547         last = (transaction & I40E_NVM_LCB);
1548         preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config);
1549
1550         memset(&cmd_details, 0, sizeof(cmd_details));
1551         cmd_details.wb_desc = &hw->nvm_wb_desc;
1552
1553         status = i40e_aq_update_nvm(hw, module, cmd->offset,
1554                                     (u16)cmd->data_size, bytes, last,
1555                                     preservation_flags, &cmd_details);
1556         if (status) {
1557                 i40e_debug(hw, I40E_DEBUG_NVM,
1558                            "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1559                            module, cmd->offset, cmd->data_size);
1560                 i40e_debug(hw, I40E_DEBUG_NVM,
1561                            "i40e_nvmupd_nvm_write status %d aq %d\n",
1562                            status, hw->aq.asq_last_status);
1563                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1564         }
1565
1566         return status;
1567 }