drivers/net/ethernet/intel/i40evf/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36 #include "i40e_devids.h"
  37
  38 /* I40E_MASK is a macro used on 32 bit registers */
  39 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
  40
  41 #define I40E_MAX_VSI_QP                 16
  42 #define I40E_MAX_VF_VSI                 3
  43 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  45
  46 /* Max default timeout in ms, */
  47 #define I40E_MAX_NVM_TIMEOUT            18000
  48
  49 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  50 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  51
  52 /* forward declaration */
  53 struct i40e_hw;
  54 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  55
  56 /* Data type manipulation macros. */
  57
  58 #define I40E_DESC_UNUSED(R)     \
  59         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  60         (R)->next_to_clean - (R)->next_to_use - 1)
  61
  62 /* bitfields for Tx queue mapping in QTX_CTL */
  63 #define I40E_QTX_CTL_VF_QUEUE   0x0
  64 #define I40E_QTX_CTL_VM_QUEUE   0x1
  65 #define I40E_QTX_CTL_PF_QUEUE   0x2
  66
  67 /* debug masks - set these bits in hw->debug_mask to control output */
  68 enum i40e_debug_mask {
  69         I40E_DEBUG_INIT                 = 0x00000001,
  70         I40E_DEBUG_RELEASE              = 0x00000002,
  71
  72         I40E_DEBUG_LINK                 = 0x00000010,
  73         I40E_DEBUG_PHY                  = 0x00000020,
  74         I40E_DEBUG_HMC                  = 0x00000040,
  75         I40E_DEBUG_NVM                  = 0x00000080,
  76         I40E_DEBUG_LAN                  = 0x00000100,
  77         I40E_DEBUG_FLOW                 = 0x00000200,
  78         I40E_DEBUG_DCB                  = 0x00000400,
  79         I40E_DEBUG_DIAG                 = 0x00000800,
  80         I40E_DEBUG_FD                   = 0x00001000,
  81         I40E_DEBUG_PACKAGE              = 0x00002000,
  82
  83         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  84         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  85         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  86         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  87         I40E_DEBUG_AQ                   = 0x0F000000,
  88
  89         I40E_DEBUG_USER                 = 0xF0000000,
  90
  91         I40E_DEBUG_ALL                  = 0xFFFFFFFF
  92 };
  93
  94 /* These are structs for managing the hardware information and the operations.
  95  * The structures of function pointers are filled out at init time when we
  96  * know for sure exactly which hardware we're working with.  This gives us the
  97  * flexibility of using the same main driver code but adapting to slightly
  98  * different hardware needs as new parts are developed.  For this architecture,
  99  * the Firmware and AdminQ are intended to insulate the driver from most of the
 100  * future changes, but these structures will also do part of the job.
 101  */
 102 enum i40e_mac_type {
 103         I40E_MAC_UNKNOWN = 0,
 104         I40E_MAC_XL710,
 105         I40E_MAC_VF,
 106         I40E_MAC_X722,
 107         I40E_MAC_X722_VF,
 108         I40E_MAC_GENERIC,
 109 };
 110
 111 enum i40e_media_type {
 112         I40E_MEDIA_TYPE_UNKNOWN = 0,
 113         I40E_MEDIA_TYPE_FIBER,
 114         I40E_MEDIA_TYPE_BASET,
 115         I40E_MEDIA_TYPE_BACKPLANE,
 116         I40E_MEDIA_TYPE_CX4,
 117         I40E_MEDIA_TYPE_DA,
 118         I40E_MEDIA_TYPE_VIRTUAL
 119 };
 120
 121 enum i40e_fc_mode {
 122         I40E_FC_NONE = 0,
 123         I40E_FC_RX_PAUSE,
 124         I40E_FC_TX_PAUSE,
 125         I40E_FC_FULL,
 126         I40E_FC_PFC,
 127         I40E_FC_DEFAULT
 128 };
 129
 130 enum i40e_set_fc_aq_failures {
 131         I40E_SET_FC_AQ_FAIL_NONE = 0,
 132         I40E_SET_FC_AQ_FAIL_GET = 1,
 133         I40E_SET_FC_AQ_FAIL_SET = 2,
 134         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 135         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 136 };
 137
 138 enum i40e_vsi_type {
 139         I40E_VSI_MAIN   = 0,
 140         I40E_VSI_VMDQ1  = 1,
 141         I40E_VSI_VMDQ2  = 2,
 142         I40E_VSI_CTRL   = 3,
 143         I40E_VSI_FCOE   = 4,
 144         I40E_VSI_MIRROR = 5,
 145         I40E_VSI_SRIOV  = 6,
 146         I40E_VSI_FDIR   = 7,
 147         I40E_VSI_TYPE_UNKNOWN
 148 };
 149
 150 enum i40e_queue_type {
 151         I40E_QUEUE_TYPE_RX = 0,
 152         I40E_QUEUE_TYPE_TX,
 153         I40E_QUEUE_TYPE_PE_CEQ,
 154         I40E_QUEUE_TYPE_UNKNOWN
 155 };
 156
 157 struct i40e_link_status {
 158         enum i40e_aq_phy_type phy_type;
 159         enum i40e_aq_link_speed link_speed;
 160         u8 link_info;
 161         u8 an_info;
 162         u8 req_fec_info;
 163         u8 fec_info;
 164         u8 ext_info;
 165         u8 loopback;
 166         /* is Link Status Event notification to SW enabled */
 167         bool lse_enable;
 168         u16 max_frame_size;
 169         bool crc_enable;
 170         u8 pacing;
 171         u8 requested_speeds;
 172         u8 module_type[3];
 173         /* 1st byte: module identifier */
 174 #define I40E_MODULE_TYPE_SFP            0x03
 175 #define I40E_MODULE_TYPE_QSFP           0x0D
 176         /* 2nd byte: ethernet compliance codes for 10/40G */
 177 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 178 #define I40E_MODULE_TYPE_40G_LR4        0x02
 179 #define I40E_MODULE_TYPE_40G_SR4        0x04
 180 #define I40E_MODULE_TYPE_40G_CR4        0x08
 181 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 182 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 183 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 184 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 185         /* 3rd byte: ethernet compliance codes for 1G */
 186 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 187 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 188 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 189 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 190 };
 191
 192 struct i40e_phy_info {
 193         struct i40e_link_status link_info;
 194         struct i40e_link_status link_info_old;
 195         bool get_link_info;
 196         enum i40e_media_type media_type;
 197         /* all the phy types the NVM is capable of */
 198         u64 phy_types;
 199 };
 200
 201 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 202 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 203 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 204 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 205 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 206 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 207 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 208 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 209 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 210 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 211 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 212 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 213 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 214 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 215 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 216 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 217 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 218 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 219 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 220 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 221 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 222 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 223 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 224 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 225 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 226 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 227 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 228                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 229 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 230 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 231  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 232  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 233  * a shift is needed to adjust for this with values larger than 31. The
 234  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 235  */
 236 #define I40E_PHY_TYPE_OFFSET 1
 237 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 238                                              I40E_PHY_TYPE_OFFSET)
 239 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 240                                              I40E_PHY_TYPE_OFFSET)
 241 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 242                                              I40E_PHY_TYPE_OFFSET)
 243 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 244                                              I40E_PHY_TYPE_OFFSET)
 245 #define I40E_HW_CAP_MAX_GPIO                    30
 246 /* Capabilities of a PF or a VF or the whole device */
 247 struct i40e_hw_capabilities {
 248         u32  switch_mode;
 249 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 250 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 251 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 252
 253         u32  management_mode;
 254         u32  mng_protocols_over_mctp;
 255 #define I40E_MNG_PROTOCOL_PLDM          0x2
 256 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 257 #define I40E_MNG_PROTOCOL_NCSI          0x8
 258         u32  npar_enable;
 259         u32  os2bmc;
 260         u32  valid_functions;
 261         bool sr_iov_1_1;
 262         bool vmdq;
 263         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 264         bool evb_802_1_qbh; /* Bridge Port Extension */
 265         bool dcb;
 266         bool fcoe;
 267         bool iscsi; /* Indicates iSCSI enabled */
 268         bool flex10_enable;
 269         bool flex10_capable;
 270         u32  flex10_mode;
 271 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 272 #define I40E_FLEX10_MODE_DCC            0x1
 273 #define I40E_FLEX10_MODE_DCI            0x2
 274
 275         u32 flex10_status;
 276 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 277 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 278
 279         bool sec_rev_disabled;
 280         bool update_disabled;
 281 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 282 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 283
 284         bool mgmt_cem;
 285         bool ieee_1588;
 286         bool iwarp;
 287         bool fd;
 288         u32 fd_filters_guaranteed;
 289         u32 fd_filters_best_effort;
 290         bool rss;
 291         u32 rss_table_size;
 292         u32 rss_table_entry_width;
 293         bool led[I40E_HW_CAP_MAX_GPIO];
 294         bool sdp[I40E_HW_CAP_MAX_GPIO];
 295         u32 nvm_image_type;
 296         u32 num_flow_director_filters;
 297         u32 num_vfs;
 298         u32 vf_base_id;
 299         u32 num_vsis;
 300         u32 num_rx_qp;
 301         u32 num_tx_qp;
 302         u32 base_queue;
 303         u32 num_msix_vectors;
 304         u32 num_msix_vectors_vf;
 305         u32 led_pin_num;
 306         u32 sdp_pin_num;
 307         u32 mdio_port_num;
 308         u32 mdio_port_mode;
 309         u8 rx_buf_chain_len;
 310         u32 enabled_tcmap;
 311         u32 maxtc;
 312         u64 wr_csr_prot;
 313 };
 314
 315 struct i40e_mac_info {
 316         enum i40e_mac_type type;
 317         u8 addr[ETH_ALEN];
 318         u8 perm_addr[ETH_ALEN];
 319         u8 san_addr[ETH_ALEN];
 320         u16 max_fcoeq;
 321 };
 322
 323 enum i40e_aq_resources_ids {
 324         I40E_NVM_RESOURCE_ID = 1
 325 };
 326
 327 enum i40e_aq_resource_access_type {
 328         I40E_RESOURCE_READ = 1,
 329         I40E_RESOURCE_WRITE
 330 };
 331
 332 struct i40e_nvm_info {
 333         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 334         u32 timeout;              /* [ms] */
 335         u16 sr_size;              /* Shadow RAM size in words */
 336         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 337         u16 version;              /* NVM package version */
 338         u32 eetrack;              /* NVM data version */
 339         u32 oem_ver;              /* OEM version info */
 340 };
 341
 342 /* definitions used in NVM update support */
 343
 344 enum i40e_nvmupd_cmd {
 345         I40E_NVMUPD_INVALID,
 346         I40E_NVMUPD_READ_CON,
 347         I40E_NVMUPD_READ_SNT,
 348         I40E_NVMUPD_READ_LCB,
 349         I40E_NVMUPD_READ_SA,
 350         I40E_NVMUPD_WRITE_ERA,
 351         I40E_NVMUPD_WRITE_CON,
 352         I40E_NVMUPD_WRITE_SNT,
 353         I40E_NVMUPD_WRITE_LCB,
 354         I40E_NVMUPD_WRITE_SA,
 355         I40E_NVMUPD_CSUM_CON,
 356         I40E_NVMUPD_CSUM_SA,
 357         I40E_NVMUPD_CSUM_LCB,
 358         I40E_NVMUPD_STATUS,
 359         I40E_NVMUPD_EXEC_AQ,
 360         I40E_NVMUPD_GET_AQ_RESULT,
 361 };
 362
 363 enum i40e_nvmupd_state {
 364         I40E_NVMUPD_STATE_INIT,
 365         I40E_NVMUPD_STATE_READING,
 366         I40E_NVMUPD_STATE_WRITING,
 367         I40E_NVMUPD_STATE_INIT_WAIT,
 368         I40E_NVMUPD_STATE_WRITE_WAIT,
 369         I40E_NVMUPD_STATE_ERROR
 370 };
 371
 372 /* nvm_access definition and its masks/shifts need to be accessible to
 373  * application, core driver, and shared code.  Where is the right file?
 374  */
 375 #define I40E_NVM_READ   0xB
 376 #define I40E_NVM_WRITE  0xC
 377
 378 #define I40E_NVM_MOD_PNT_MASK 0xFF
 379
 380 #define I40E_NVM_TRANS_SHIFT    8
 381 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 382 #define I40E_NVM_CON            0x0
 383 #define I40E_NVM_SNT            0x1
 384 #define I40E_NVM_LCB            0x2
 385 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 386 #define I40E_NVM_ERA            0x4
 387 #define I40E_NVM_CSUM           0x8
 388 #define I40E_NVM_EXEC           0xf
 389
 390 #define I40E_NVM_ADAPT_SHIFT    16
 391 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 392
 393 #define I40E_NVMUPD_MAX_DATA    4096
 394 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 395
 396 struct i40e_nvm_access {
 397         u32 command;
 398         u32 config;
 399         u32 offset;     /* in bytes */
 400         u32 data_size;  /* in bytes */
 401         u8 data[1];
 402 };
 403
 404 /* PCI bus types */
 405 enum i40e_bus_type {
 406         i40e_bus_type_unknown = 0,
 407         i40e_bus_type_pci,
 408         i40e_bus_type_pcix,
 409         i40e_bus_type_pci_express,
 410         i40e_bus_type_reserved
 411 };
 412
 413 /* PCI bus speeds */
 414 enum i40e_bus_speed {
 415         i40e_bus_speed_unknown  = 0,
 416         i40e_bus_speed_33       = 33,
 417         i40e_bus_speed_66       = 66,
 418         i40e_bus_speed_100      = 100,
 419         i40e_bus_speed_120      = 120,
 420         i40e_bus_speed_133      = 133,
 421         i40e_bus_speed_2500     = 2500,
 422         i40e_bus_speed_5000     = 5000,
 423         i40e_bus_speed_8000     = 8000,
 424         i40e_bus_speed_reserved
 425 };
 426
 427 /* PCI bus widths */
 428 enum i40e_bus_width {
 429         i40e_bus_width_unknown  = 0,
 430         i40e_bus_width_pcie_x1  = 1,
 431         i40e_bus_width_pcie_x2  = 2,
 432         i40e_bus_width_pcie_x4  = 4,
 433         i40e_bus_width_pcie_x8  = 8,
 434         i40e_bus_width_32       = 32,
 435         i40e_bus_width_64       = 64,
 436         i40e_bus_width_reserved
 437 };
 438
 439 /* Bus parameters */
 440 struct i40e_bus_info {
 441         enum i40e_bus_speed speed;
 442         enum i40e_bus_width width;
 443         enum i40e_bus_type type;
 444
 445         u16 func;
 446         u16 device;
 447         u16 lan_id;
 448         u16 bus_id;
 449 };
 450
 451 /* Flow control (FC) parameters */
 452 struct i40e_fc_info {
 453         enum i40e_fc_mode current_mode; /* FC mode in effect */
 454         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 455 };
 456
 457 #define I40E_MAX_TRAFFIC_CLASS          8
 458 #define I40E_MAX_USER_PRIORITY          8
 459 #define I40E_DCBX_MAX_APPS              32
 460 #define I40E_LLDPDU_SIZE                1500
 461
 462 /* IEEE 802.1Qaz ETS Configuration data */
 463 struct i40e_ieee_ets_config {
 464         u8 willing;
 465         u8 cbs;
 466         u8 maxtcs;
 467         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 468         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 469         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 470 };
 471
 472 /* IEEE 802.1Qaz ETS Recommendation data */
 473 struct i40e_ieee_ets_recommend {
 474         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 475         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 476         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 477 };
 478
 479 /* IEEE 802.1Qaz PFC Configuration data */
 480 struct i40e_ieee_pfc_config {
 481         u8 willing;
 482         u8 mbc;
 483         u8 pfccap;
 484         u8 pfcenable;
 485 };
 486
 487 /* IEEE 802.1Qaz Application Priority data */
 488 struct i40e_ieee_app_priority_table {
 489         u8  priority;
 490         u8  selector;
 491         u16 protocolid;
 492 };
 493
 494 struct i40e_dcbx_config {
 495         u32 numapps;
 496         u32 tlv_status; /* CEE mode TLV status */
 497         struct i40e_ieee_ets_config etscfg;
 498         struct i40e_ieee_ets_recommend etsrec;
 499         struct i40e_ieee_pfc_config pfc;
 500         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 501 };
 502
 503 /* Port hardware description */
 504 struct i40e_hw {
 505         u8 __iomem *hw_addr;
 506         void *back;
 507
 508         /* subsystem structs */
 509         struct i40e_phy_info phy;
 510         struct i40e_mac_info mac;
 511         struct i40e_bus_info bus;
 512         struct i40e_nvm_info nvm;
 513         struct i40e_fc_info fc;
 514
 515         /* pci info */
 516         u16 device_id;
 517         u16 vendor_id;
 518         u16 subsystem_device_id;
 519         u16 subsystem_vendor_id;
 520         u8 revision_id;
 521         u8 port;
 522         bool adapter_stopped;
 523
 524         /* capabilities for entire device and PCI func */
 525         struct i40e_hw_capabilities dev_caps;
 526         struct i40e_hw_capabilities func_caps;
 527
 528         /* Flow Director shared filter space */
 529         u16 fdir_shared_filter_count;
 530
 531         /* device profile info */
 532         u8  pf_id;
 533         u16 main_vsi_seid;
 534
 535         /* for multi-function MACs */
 536         u16 partition_id;
 537         u16 num_partitions;
 538         u16 num_ports;
 539
 540         /* Closest numa node to the device */
 541         u16 numa_node;
 542
 543         /* Admin Queue info */
 544         struct i40e_adminq_info aq;
 545
 546         /* state of nvm update process */
 547         enum i40e_nvmupd_state nvmupd_state;
 548         struct i40e_aq_desc nvm_wb_desc;
 549         struct i40e_virt_mem nvm_buff;
 550         bool nvm_release_on_done;
 551         u16 nvm_wait_opcode;
 552
 553         /* HMC info */
 554         struct i40e_hmc_info hmc; /* HMC info struct */
 555
 556         /* LLDP/DCBX Status */
 557         u16 dcbx_status;
 558
 559         /* DCBX info */
 560         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 561         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 562         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 563
 564         /* debug mask */
 565         u32 debug_mask;
 566         char err_str[16];
 567 };
 568
 569 static inline bool i40e_is_vf(struct i40e_hw *hw)
 570 {
 571         return (hw->mac.type == I40E_MAC_VF ||
 572                 hw->mac.type == I40E_MAC_X722_VF);
 573 }
 574
 575 struct i40e_driver_version {
 576         u8 major_version;
 577         u8 minor_version;
 578         u8 build_version;
 579         u8 subbuild_version;
 580         u8 driver_string[32];
 581 };
 582
 583 /* RX Descriptors */
 584 union i40e_16byte_rx_desc {
 585         struct {
 586                 __le64 pkt_addr; /* Packet buffer address */
 587                 __le64 hdr_addr; /* Header buffer address */
 588         } read;
 589         struct {
 590                 struct {
 591                         struct {
 592                                 union {
 593                                         __le16 mirroring_status;
 594                                         __le16 fcoe_ctx_id;
 595                                 } mirr_fcoe;
 596                                 __le16 l2tag1;
 597                         } lo_dword;
 598                         union {
 599                                 __le32 rss; /* RSS Hash */
 600                                 __le32 fd_id; /* Flow director filter id */
 601                                 __le32 fcoe_param; /* FCoE DDP Context id */
 602                         } hi_dword;
 603                 } qword0;
 604                 struct {
 605                         /* ext status/error/pktype/length */
 606                         __le64 status_error_len;
 607                 } qword1;
 608         } wb;  /* writeback */
 609 };
 610
 611 union i40e_32byte_rx_desc {
 612         struct {
 613                 __le64  pkt_addr; /* Packet buffer address */
 614                 __le64  hdr_addr; /* Header buffer address */
 615                         /* bit 0 of hdr_buffer_addr is DD bit */
 616                 __le64  rsvd1;
 617                 __le64  rsvd2;
 618         } read;
 619         struct {
 620                 struct {
 621                         struct {
 622                                 union {
 623                                         __le16 mirroring_status;
 624                                         __le16 fcoe_ctx_id;
 625                                 } mirr_fcoe;
 626                                 __le16 l2tag1;
 627                         } lo_dword;
 628                         union {
 629                                 __le32 rss; /* RSS Hash */
 630                                 __le32 fcoe_param; /* FCoE DDP Context id */
 631                                 /* Flow director filter id in case of
 632                                  * Programming status desc WB
 633                                  */
 634                                 __le32 fd_id;
 635                         } hi_dword;
 636                 } qword0;
 637                 struct {
 638                         /* status/error/pktype/length */
 639                         __le64 status_error_len;
 640                 } qword1;
 641                 struct {
 642                         __le16 ext_status; /* extended status */
 643                         __le16 rsvd;
 644                         __le16 l2tag2_1;
 645                         __le16 l2tag2_2;
 646                 } qword2;
 647                 struct {
 648                         union {
 649                                 __le32 flex_bytes_lo;
 650                                 __le32 pe_status;
 651                         } lo_dword;
 652                         union {
 653                                 __le32 flex_bytes_hi;
 654                                 __le32 fd_id;
 655                         } hi_dword;
 656                 } qword3;
 657         } wb;  /* writeback */
 658 };
 659
 660 enum i40e_rx_desc_status_bits {
 661         /* Note: These are predefined bit offsets */
 662         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 663         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 664         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 665         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 666         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 667         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 668         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 669         /* Note: Bit 8 is reserved in X710 and XL710 */
 670         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 671         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 672         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 673         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 674         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 675         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 676         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 677         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 678          * UDP header
 679          */
 680         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 681         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 682 };
 683
 684 #define I40E_RXD_QW1_STATUS_SHIFT       0
 685 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 686                                          << I40E_RXD_QW1_STATUS_SHIFT)
 687
 688 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 689 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 690                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 691
 692 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 693 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 694                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 695
 696 enum i40e_rx_desc_fltstat_values {
 697         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 698         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 699         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 700         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 701 };
 702
 703 #define I40E_RXD_QW1_ERROR_SHIFT        19
 704 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 705
 706 enum i40e_rx_desc_error_bits {
 707         /* Note: These are predefined bit offsets */
 708         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 709         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 710         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 711         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 712         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 713         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 714         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 715         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 716         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 717 };
 718
 719 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 720         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 721         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 722         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 723         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 724         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 725 };
 726
 727 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 728 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 729
 730 /* Packet type non-ip values */
 731 enum i40e_rx_l2_ptype {
 732         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 733         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 734         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 735         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 736         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 737         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 738         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 739         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 740         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 741         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 742         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 743         I40E_RX_PTYPE_L2_ARP                            = 11,
 744         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 745         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 746         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 747         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 748         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 749         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 750         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 751         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 752         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 753         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 754         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 755         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 756         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 757         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 758 };
 759
 760 struct i40e_rx_ptype_decoded {
 761         u32 ptype:8;
 762         u32 known:1;
 763         u32 outer_ip:1;
 764         u32 outer_ip_ver:1;
 765         u32 outer_frag:1;
 766         u32 tunnel_type:3;
 767         u32 tunnel_end_prot:2;
 768         u32 tunnel_end_frag:1;
 769         u32 inner_prot:4;
 770         u32 payload_layer:3;
 771 };
 772
 773 enum i40e_rx_ptype_outer_ip {
 774         I40E_RX_PTYPE_OUTER_L2  = 0,
 775         I40E_RX_PTYPE_OUTER_IP  = 1
 776 };
 777
 778 enum i40e_rx_ptype_outer_ip_ver {
 779         I40E_RX_PTYPE_OUTER_NONE        = 0,
 780         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 781         I40E_RX_PTYPE_OUTER_IPV6        = 1
 782 };
 783
 784 enum i40e_rx_ptype_outer_fragmented {
 785         I40E_RX_PTYPE_NOT_FRAG  = 0,
 786         I40E_RX_PTYPE_FRAG      = 1
 787 };
 788
 789 enum i40e_rx_ptype_tunnel_type {
 790         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 791         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 792         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 793         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 794         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 795 };
 796
 797 enum i40e_rx_ptype_tunnel_end_prot {
 798         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 799         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 800         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 801 };
 802
 803 enum i40e_rx_ptype_inner_prot {
 804         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 805         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 806         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 807         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 808         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 809         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 810 };
 811
 812 enum i40e_rx_ptype_payload_layer {
 813         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 814         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 815         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 816         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 817 };
 818
 819 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 820 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 821                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 822
 823 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 824 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 825                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 826
 827 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 828 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 829
 830 enum i40e_rx_desc_ext_status_bits {
 831         /* Note: These are predefined bit offsets */
 832         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 833         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 834         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 835         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 836         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 837         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 838         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 839 };
 840
 841 enum i40e_rx_desc_pe_status_bits {
 842         /* Note: These are predefined bit offsets */
 843         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 844         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 845         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 846         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 847         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 848         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 849         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 850         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 851         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 852 };
 853
 854 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 855 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 856
 857 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 858 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 859                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 860
 861 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 862 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 863                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 864
 865 enum i40e_rx_prog_status_desc_status_bits {
 866         /* Note: These are predefined bit offsets */
 867         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 868         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 869 };
 870
 871 enum i40e_rx_prog_status_desc_prog_id_masks {
 872         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 873         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 874         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 875 };
 876
 877 enum i40e_rx_prog_status_desc_error_bits {
 878         /* Note: These are predefined bit offsets */
 879         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 880         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 881         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 882         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 883 };
 884
 885 /* TX Descriptor */
 886 struct i40e_tx_desc {
 887         __le64 buffer_addr; /* Address of descriptor's data buf */
 888         __le64 cmd_type_offset_bsz;
 889 };
 890
 891 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 892 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 893
 894 enum i40e_tx_desc_dtype_value {
 895         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 896         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 897         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 898         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 899         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 900         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 901         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 902         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 903         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 904         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 905 };
 906
 907 #define I40E_TXD_QW1_CMD_SHIFT  4
 908 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 909
 910 enum i40e_tx_desc_cmd_bits {
 911         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 912         I40E_TX_DESC_CMD_RS                     = 0x0002,
 913         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 914         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 915         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 916         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 917         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 918         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 919         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 920         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 921         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 922         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 923         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 924         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 925         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 926         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 927         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 928         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 929 };
 930
 931 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 932 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 933                                          I40E_TXD_QW1_OFFSET_SHIFT)
 934
 935 enum i40e_tx_desc_length_fields {
 936         /* Note: These are predefined bit offsets */
 937         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 938         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 939         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 940 };
 941
 942 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 943 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 944                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 945
 946 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 947 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 948
 949 /* Context descriptors */
 950 struct i40e_tx_context_desc {
 951         __le32 tunneling_params;
 952         __le16 l2tag2;
 953         __le16 rsvd;
 954         __le64 type_cmd_tso_mss;
 955 };
 956
 957 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 958 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 959
 960 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 961 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 962
 963 enum i40e_tx_ctx_desc_cmd_bits {
 964         I40E_TX_CTX_DESC_TSO            = 0x01,
 965         I40E_TX_CTX_DESC_TSYN           = 0x02,
 966         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 967         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 968         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 969         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 970         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 971         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 972         I40E_TX_CTX_DESC_SWPE           = 0x40
 973 };
 974
 975 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 976 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 977                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 978
 979 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 980 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 981                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 982
 983 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 984 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 985
 986 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 987 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 988                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 989
 990 enum i40e_tx_ctx_desc_eipt_offload {
 991         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 992         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 993         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 994         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 995 };
 996
 997 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 998 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 999                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1000
1001 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1002 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1003
1004 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1005 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1006
1007 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1008 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1009                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1010
1011 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1012
1013 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1014 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1015                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1016
1017 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1018 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1019                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1020
1021 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1022 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1023 struct i40e_filter_program_desc {
1024         __le32 qindex_flex_ptype_vsi;
1025         __le32 rsvd;
1026         __le32 dtype_cmd_cntindex;
1027         __le32 fd_id;
1028 };
1029 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1030 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1031                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1032 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1033 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1034                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1035 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1036 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1037                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1038
1039 /* Packet Classifier Types for filters */
1040 enum i40e_filter_pctype {
1041         /* Note: Values 0-28 are reserved for future use.
1042          * Value 29, 30, 32 are not supported on XL710 and X710.
1043          */
1044         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1045         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1046         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1047         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1048         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1049         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1050         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1051         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1052         /* Note: Values 37-38 are reserved for future use.
1053          * Value 39, 40, 42 are not supported on XL710 and X710.
1054          */
1055         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1056         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1057         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1058         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1059         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1060         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1061         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1062         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1063         /* Note: Value 47 is reserved for future use */
1064         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1065         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1066         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1067         /* Note: Values 51-62 are reserved for future use */
1068         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1069 };
1070
1071 enum i40e_filter_program_desc_dest {
1072         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1073         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1074         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1075 };
1076
1077 enum i40e_filter_program_desc_fd_status {
1078         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1079         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1080         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1081         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1082 };
1083
1084 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1085 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1086                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1087
1088 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1089 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1090                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1091
1092 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1093 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1094
1095 enum i40e_filter_program_desc_pcmd {
1096         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1097         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1098 };
1099
1100 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1101 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1102
1103 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1104 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1105
1106 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1107                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1108 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1109                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1110
1111 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1112 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1113                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1114
1115 enum i40e_filter_type {
1116         I40E_FLOW_DIRECTOR_FLTR = 0,
1117         I40E_PE_QUAD_HASH_FLTR = 1,
1118         I40E_ETHERTYPE_FLTR,
1119         I40E_FCOE_CTX_FLTR,
1120         I40E_MAC_VLAN_FLTR,
1121         I40E_HASH_FLTR
1122 };
1123
1124 struct i40e_vsi_context {
1125         u16 seid;
1126         u16 uplink_seid;
1127         u16 vsi_number;
1128         u16 vsis_allocated;
1129         u16 vsis_unallocated;
1130         u16 flags;
1131         u8 pf_num;
1132         u8 vf_num;
1133         u8 connection_type;
1134         struct i40e_aqc_vsi_properties_data info;
1135 };
1136
1137 struct i40e_veb_context {
1138         u16 seid;
1139         u16 uplink_seid;
1140         u16 veb_number;
1141         u16 vebs_allocated;
1142         u16 vebs_unallocated;
1143         u16 flags;
1144         struct i40e_aqc_get_veb_parameters_completion info;
1145 };
1146
1147 /* Statistics collected by each port, VSI, VEB, and S-channel */
1148 struct i40e_eth_stats {
1149         u64 rx_bytes;                   /* gorc */
1150         u64 rx_unicast;                 /* uprc */
1151         u64 rx_multicast;               /* mprc */
1152         u64 rx_broadcast;               /* bprc */
1153         u64 rx_discards;                /* rdpc */
1154         u64 rx_unknown_protocol;        /* rupp */
1155         u64 tx_bytes;                   /* gotc */
1156         u64 tx_unicast;                 /* uptc */
1157         u64 tx_multicast;               /* mptc */
1158         u64 tx_broadcast;               /* bptc */
1159         u64 tx_discards;                /* tdpc */
1160         u64 tx_errors;                  /* tepc */
1161 };
1162
1163 /* Statistics collected per VEB per TC */
1164 struct i40e_veb_tc_stats {
1165         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1166         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1167         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1168         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1169 };
1170
1171 /* Statistics collected by the MAC */
1172 struct i40e_hw_port_stats {
1173         /* eth stats collected by the port */
1174         struct i40e_eth_stats eth;
1175
1176         /* additional port specific stats */
1177         u64 tx_dropped_link_down;       /* tdold */
1178         u64 crc_errors;                 /* crcerrs */
1179         u64 illegal_bytes;              /* illerrc */
1180         u64 error_bytes;                /* errbc */
1181         u64 mac_local_faults;           /* mlfc */
1182         u64 mac_remote_faults;          /* mrfc */
1183         u64 rx_length_errors;           /* rlec */
1184         u64 link_xon_rx;                /* lxonrxc */
1185         u64 link_xoff_rx;               /* lxoffrxc */
1186         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1187         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1188         u64 link_xon_tx;                /* lxontxc */
1189         u64 link_xoff_tx;               /* lxofftxc */
1190         u64 priority_xon_tx[8];         /* pxontxc[8] */
1191         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1192         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1193         u64 rx_size_64;                 /* prc64 */
1194         u64 rx_size_127;                /* prc127 */
1195         u64 rx_size_255;                /* prc255 */
1196         u64 rx_size_511;                /* prc511 */
1197         u64 rx_size_1023;               /* prc1023 */
1198         u64 rx_size_1522;               /* prc1522 */
1199         u64 rx_size_big;                /* prc9522 */
1200         u64 rx_undersize;               /* ruc */
1201         u64 rx_fragments;               /* rfc */
1202         u64 rx_oversize;                /* roc */
1203         u64 rx_jabber;                  /* rjc */
1204         u64 tx_size_64;                 /* ptc64 */
1205         u64 tx_size_127;                /* ptc127 */
1206         u64 tx_size_255;                /* ptc255 */
1207         u64 tx_size_511;                /* ptc511 */
1208         u64 tx_size_1023;               /* ptc1023 */
1209         u64 tx_size_1522;               /* ptc1522 */
1210         u64 tx_size_big;                /* ptc9522 */
1211         u64 mac_short_packet_dropped;   /* mspdc */
1212         u64 checksum_error;             /* xec */
1213         /* flow director stats */
1214         u64 fd_atr_match;
1215         u64 fd_sb_match;
1216         u64 fd_atr_tunnel_match;
1217         u32 fd_atr_status;
1218         u32 fd_sb_status;
1219         /* EEE LPI */
1220         u32 tx_lpi_status;
1221         u32 rx_lpi_status;
1222         u64 tx_lpi_count;               /* etlpic */
1223         u64 rx_lpi_count;               /* erlpic */
1224 };
1225
1226 /* Checksum and Shadow RAM pointers */
1227 #define I40E_SR_NVM_CONTROL_WORD                0x00
1228 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1229 #define I40E_NVM_OEM_VER_OFF                    0x83
1230 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1231 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1232 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1233 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1234 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1235 #define I40E_SR_VPD_PTR                         0x2F
1236 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1237 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1238
1239 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1240 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1241 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1242 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1243 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1244
1245 /* Shadow RAM related */
1246 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1247 #define I40E_SR_WORDS_IN_1KB            512
1248 /* Checksum should be calculated such that after adding all the words,
1249  * including the checksum word itself, the sum should be 0xBABA.
1250  */
1251 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1252
1253 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1254
1255 enum i40e_switch_element_types {
1256         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1257         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1258         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1259         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1260         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1261         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1262         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1263         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1264         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1265 };
1266
1267 /* Supported EtherType filters */
1268 enum i40e_ether_type_index {
1269         I40E_ETHER_TYPE_1588            = 0,
1270         I40E_ETHER_TYPE_FIP             = 1,
1271         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1272         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1273         I40E_ETHER_TYPE_LLDP            = 4,
1274         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1275         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1276         I40E_ETHER_TYPE_QCN_CNM         = 7,
1277         I40E_ETHER_TYPE_8021X           = 8,
1278         I40E_ETHER_TYPE_ARP             = 9,
1279         I40E_ETHER_TYPE_RSV1            = 10,
1280         I40E_ETHER_TYPE_RSV2            = 11,
1281 };
1282
1283 /* Filter context base size is 1K */
1284 #define I40E_HASH_FILTER_BASE_SIZE      1024
1285 /* Supported Hash filter values */
1286 enum i40e_hash_filter_size {
1287         I40E_HASH_FILTER_SIZE_1K        = 0,
1288         I40E_HASH_FILTER_SIZE_2K        = 1,
1289         I40E_HASH_FILTER_SIZE_4K        = 2,
1290         I40E_HASH_FILTER_SIZE_8K        = 3,
1291         I40E_HASH_FILTER_SIZE_16K       = 4,
1292         I40E_HASH_FILTER_SIZE_32K       = 5,
1293         I40E_HASH_FILTER_SIZE_64K       = 6,
1294         I40E_HASH_FILTER_SIZE_128K      = 7,
1295         I40E_HASH_FILTER_SIZE_256K      = 8,
1296         I40E_HASH_FILTER_SIZE_512K      = 9,
1297         I40E_HASH_FILTER_SIZE_1M        = 10,
1298 };
1299
1300 /* DMA context base size is 0.5K */
1301 #define I40E_DMA_CNTX_BASE_SIZE         512
1302 /* Supported DMA context values */
1303 enum i40e_dma_cntx_size {
1304         I40E_DMA_CNTX_SIZE_512          = 0,
1305         I40E_DMA_CNTX_SIZE_1K           = 1,
1306         I40E_DMA_CNTX_SIZE_2K           = 2,
1307         I40E_DMA_CNTX_SIZE_4K           = 3,
1308         I40E_DMA_CNTX_SIZE_8K           = 4,
1309         I40E_DMA_CNTX_SIZE_16K          = 5,
1310         I40E_DMA_CNTX_SIZE_32K          = 6,
1311         I40E_DMA_CNTX_SIZE_64K          = 7,
1312         I40E_DMA_CNTX_SIZE_128K         = 8,
1313         I40E_DMA_CNTX_SIZE_256K         = 9,
1314 };
1315
1316 /* Supported Hash look up table (LUT) sizes */
1317 enum i40e_hash_lut_size {
1318         I40E_HASH_LUT_SIZE_128          = 0,
1319         I40E_HASH_LUT_SIZE_512          = 1,
1320 };
1321
1322 /* Structure to hold a per PF filter control settings */
1323 struct i40e_filter_control_settings {
1324         /* number of PE Quad Hash filter buckets */
1325         enum i40e_hash_filter_size pe_filt_num;
1326         /* number of PE Quad Hash contexts */
1327         enum i40e_dma_cntx_size pe_cntx_num;
1328         /* number of FCoE filter buckets */
1329         enum i40e_hash_filter_size fcoe_filt_num;
1330         /* number of FCoE DDP contexts */
1331         enum i40e_dma_cntx_size fcoe_cntx_num;
1332         /* size of the Hash LUT */
1333         enum i40e_hash_lut_size hash_lut_size;
1334         /* enable FDIR filters for PF and its VFs */
1335         bool enable_fdir;
1336         /* enable Ethertype filters for PF and its VFs */
1337         bool enable_ethtype;
1338         /* enable MAC/VLAN filters for PF and its VFs */
1339         bool enable_macvlan;
1340 };
1341
1342 /* Structure to hold device level control filter counts */
1343 struct i40e_control_filter_stats {
1344         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1345         u16 etype_used;       /* Used perfect EtherType filters */
1346         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1347         u16 etype_free;       /* Un-used perfect EtherType filters */
1348 };
1349
1350 enum i40e_reset_type {
1351         I40E_RESET_POR          = 0,
1352         I40E_RESET_CORER        = 1,
1353         I40E_RESET_GLOBR        = 2,
1354         I40E_RESET_EMPR         = 3,
1355 };
1356
1357 /* RSS Hash Table Size */
1358 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1359
1360 /* INPUT SET MASK for RSS, flow director and flexible payload */
1361 #define I40E_FD_INSET_L3_SRC_SHIFT              47
1362 #define I40E_FD_INSET_L3_SRC_WORD_MASK          (0x3ULL << \
1363                                                  I40E_FD_INSET_L3_SRC_SHIFT)
1364 #define I40E_FD_INSET_L3_DST_SHIFT              35
1365 #define I40E_FD_INSET_L3_DST_WORD_MASK          (0x3ULL << \
1366                                                  I40E_FD_INSET_L3_DST_SHIFT)
1367 #define I40E_FD_INSET_L4_SRC_SHIFT              34
1368 #define I40E_FD_INSET_L4_SRC_WORD_MASK          (0x1ULL << \
1369                                                  I40E_FD_INSET_L4_SRC_SHIFT)
1370 #define I40E_FD_INSET_L4_DST_SHIFT              33
1371 #define I40E_FD_INSET_L4_DST_WORD_MASK          (0x1ULL << \
1372                                                  I40E_FD_INSET_L4_DST_SHIFT)
1373 #define I40E_FD_INSET_VERIFY_TAG_SHIFT          31
1374 #define I40E_FD_INSET_VERIFY_TAG_WORD_MASK      (0x3ULL << \
1375                                                  I40E_FD_INSET_VERIFY_TAG_SHIFT)
1376
1377 #define I40E_FD_INSET_FLEX_WORD50_SHIFT         17
1378 #define I40E_FD_INSET_FLEX_WORD50_MASK          (0x1ULL << \
1379                                         I40E_FD_INSET_FLEX_WORD50_SHIFT)
1380 #define I40E_FD_INSET_FLEX_WORD51_SHIFT         16
1381 #define I40E_FD_INSET_FLEX_WORD51_MASK          (0x1ULL << \
1382                                         I40E_FD_INSET_FLEX_WORD51_SHIFT)
1383 #define I40E_FD_INSET_FLEX_WORD52_SHIFT         15
1384 #define I40E_FD_INSET_FLEX_WORD52_MASK          (0x1ULL << \
1385                                         I40E_FD_INSET_FLEX_WORD52_SHIFT)
1386 #define I40E_FD_INSET_FLEX_WORD53_SHIFT         14
1387 #define I40E_FD_INSET_FLEX_WORD53_MASK          (0x1ULL << \
1388                                         I40E_FD_INSET_FLEX_WORD53_SHIFT)
1389 #define I40E_FD_INSET_FLEX_WORD54_SHIFT         13
1390 #define I40E_FD_INSET_FLEX_WORD54_MASK          (0x1ULL << \
1391                                         I40E_FD_INSET_FLEX_WORD54_SHIFT)
1392 #define I40E_FD_INSET_FLEX_WORD55_SHIFT         12
1393 #define I40E_FD_INSET_FLEX_WORD55_MASK          (0x1ULL << \
1394                                         I40E_FD_INSET_FLEX_WORD55_SHIFT)
1395 #define I40E_FD_INSET_FLEX_WORD56_SHIFT         11
1396 #define I40E_FD_INSET_FLEX_WORD56_MASK          (0x1ULL << \
1397                                         I40E_FD_INSET_FLEX_WORD56_SHIFT)
1398 #define I40E_FD_INSET_FLEX_WORD57_SHIFT         10
1399 #define I40E_FD_INSET_FLEX_WORD57_MASK          (0x1ULL << \
1400                                         I40E_FD_INSET_FLEX_WORD57_SHIFT)
1401
1402 /* Version format for PPP */
1403 struct i40e_ppp_version {
1404         u8 major;
1405         u8 minor;
1406         u8 update;
1407         u8 draft;
1408 };
1409
1410 #define I40E_PPP_NAME_SIZE      32
1411
1412 /* Package header */
1413 struct i40e_package_header {
1414         struct i40e_ppp_version version;
1415         u32 segment_count;
1416         u32 segment_offset[1];
1417 };
1418
1419 /* Generic segment header */
1420 struct i40e_generic_seg_header {
1421 #define SEGMENT_TYPE_METADATA   0x00000001
1422 #define SEGMENT_TYPE_NOTES      0x00000002
1423 #define SEGMENT_TYPE_I40E       0x00000011
1424 #define SEGMENT_TYPE_X722       0x00000012
1425         u32 type;
1426         struct i40e_ppp_version version;
1427         u32 size;
1428         char name[I40E_PPP_NAME_SIZE];
1429 };
1430
1431 struct i40e_metadata_segment {
1432         struct i40e_generic_seg_header header;
1433         struct i40e_ppp_version version;
1434         u32 track_id;
1435         char name[I40E_PPP_NAME_SIZE];
1436 };
1437
1438 struct i40e_device_id_entry {
1439         u32 vendor_dev_id;
1440         u32 sub_vendor_dev_id;
1441 };
1442
1443 struct i40e_profile_segment {
1444         struct i40e_generic_seg_header header;
1445         struct i40e_ppp_version version;
1446         char name[I40E_PPP_NAME_SIZE];
1447         u32 device_table_count;
1448         struct i40e_device_id_entry device_table[1];
1449 };
1450
1451 struct i40e_section_table {
1452         u32 section_count;
1453         u32 section_offset[1];
1454 };
1455
1456 struct i40e_profile_section_header {
1457         u16 tbl_size;
1458         u16 data_end;
1459         struct {
1460 #define SECTION_TYPE_INFO       0x00000010
1461 #define SECTION_TYPE_MMIO       0x00000800
1462 #define SECTION_TYPE_AQ         0x00000801
1463 #define SECTION_TYPE_NOTE       0x80000000
1464 #define SECTION_TYPE_NAME       0x80000001
1465                 u32 type;
1466                 u32 offset;
1467                 u32 size;
1468         } section;
1469 };
1470
1471 struct i40e_profile_info {
1472         u32 track_id;
1473         struct i40e_ppp_version version;
1474         u8 op;
1475 #define I40E_PPP_ADD_TRACKID            0x01
1476 #define I40E_PPP_REMOVE_TRACKID 0x02
1477         u8 reserved[7];
1478         u8 name[I40E_PPP_NAME_SIZE];
1479 };
1480 #endif /* _I40E_TYPE_H_ */