drivers/net/ethernet/intel/iavf/i40e_type.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #ifndef _I40E_TYPE_H_
   5 #define _I40E_TYPE_H_
   6
   7 #include "i40e_status.h"
   8 #include "i40e_osdep.h"
   9 #include "i40e_register.h"
  10 #include "i40e_adminq.h"
  11 #include "i40e_devids.h"
  12
  13 #define I40E_RXQ_CTX_DBUFF_SHIFT 7
  14
  15 /* I40E_MASK is a macro used on 32 bit registers */
  16 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
  17
  18 #define I40E_MAX_VSI_QP                 16
  19 #define I40E_MAX_VF_VSI                 3
  20 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  21
  22 /* forward declaration */
  23 struct i40e_hw;
  24 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  25
  26 /* Data type manipulation macros. */
  27
  28 #define I40E_DESC_UNUSED(R)     \
  29         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  30         (R)->next_to_clean - (R)->next_to_use - 1)
  31
  32 /* bitfields for Tx queue mapping in QTX_CTL */
  33 #define I40E_QTX_CTL_VF_QUEUE   0x0
  34 #define I40E_QTX_CTL_VM_QUEUE   0x1
  35 #define I40E_QTX_CTL_PF_QUEUE   0x2
  36
  37 /* debug masks - set these bits in hw->debug_mask to control output */
  38 enum i40e_debug_mask {
  39         I40E_DEBUG_INIT                 = 0x00000001,
  40         I40E_DEBUG_RELEASE              = 0x00000002,
  41
  42         I40E_DEBUG_LINK                 = 0x00000010,
  43         I40E_DEBUG_PHY                  = 0x00000020,
  44         I40E_DEBUG_HMC                  = 0x00000040,
  45         I40E_DEBUG_NVM                  = 0x00000080,
  46         I40E_DEBUG_LAN                  = 0x00000100,
  47         I40E_DEBUG_FLOW                 = 0x00000200,
  48         I40E_DEBUG_DCB                  = 0x00000400,
  49         I40E_DEBUG_DIAG                 = 0x00000800,
  50         I40E_DEBUG_FD                   = 0x00001000,
  51         I40E_DEBUG_PACKAGE              = 0x00002000,
  52
  53         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  54         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  55         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  56         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  57         I40E_DEBUG_AQ                   = 0x0F000000,
  58
  59         I40E_DEBUG_USER                 = 0xF0000000,
  60
  61         I40E_DEBUG_ALL                  = 0xFFFFFFFF
  62 };
  63
  64 /* These are structs for managing the hardware information and the operations.
  65  * The structures of function pointers are filled out at init time when we
  66  * know for sure exactly which hardware we're working with.  This gives us the
  67  * flexibility of using the same main driver code but adapting to slightly
  68  * different hardware needs as new parts are developed.  For this architecture,
  69  * the Firmware and AdminQ are intended to insulate the driver from most of the
  70  * future changes, but these structures will also do part of the job.
  71  */
  72 enum i40e_mac_type {
  73         I40E_MAC_UNKNOWN = 0,
  74         I40E_MAC_XL710,
  75         I40E_MAC_VF,
  76         I40E_MAC_X722,
  77         I40E_MAC_X722_VF,
  78         I40E_MAC_GENERIC,
  79 };
  80
  81 enum i40e_vsi_type {
  82         I40E_VSI_MAIN   = 0,
  83         I40E_VSI_VMDQ1  = 1,
  84         I40E_VSI_VMDQ2  = 2,
  85         I40E_VSI_CTRL   = 3,
  86         I40E_VSI_FCOE   = 4,
  87         I40E_VSI_MIRROR = 5,
  88         I40E_VSI_SRIOV  = 6,
  89         I40E_VSI_FDIR   = 7,
  90         I40E_VSI_TYPE_UNKNOWN
  91 };
  92
  93 enum i40e_queue_type {
  94         I40E_QUEUE_TYPE_RX = 0,
  95         I40E_QUEUE_TYPE_TX,
  96         I40E_QUEUE_TYPE_PE_CEQ,
  97         I40E_QUEUE_TYPE_UNKNOWN
  98 };
  99
 100 #define I40E_HW_CAP_MAX_GPIO            30
 101 /* Capabilities of a PF or a VF or the whole device */
 102 struct i40e_hw_capabilities {
 103         bool dcb;
 104         bool fcoe;
 105         u32 num_vsis;
 106         u32 num_rx_qp;
 107         u32 num_tx_qp;
 108         u32 base_queue;
 109         u32 num_msix_vectors_vf;
 110 };
 111
 112 struct i40e_mac_info {
 113         enum i40e_mac_type type;
 114         u8 addr[ETH_ALEN];
 115         u8 perm_addr[ETH_ALEN];
 116         u8 san_addr[ETH_ALEN];
 117         u16 max_fcoeq;
 118 };
 119
 120 /* PCI bus types */
 121 enum i40e_bus_type {
 122         i40e_bus_type_unknown = 0,
 123         i40e_bus_type_pci,
 124         i40e_bus_type_pcix,
 125         i40e_bus_type_pci_express,
 126         i40e_bus_type_reserved
 127 };
 128
 129 /* PCI bus speeds */
 130 enum i40e_bus_speed {
 131         i40e_bus_speed_unknown  = 0,
 132         i40e_bus_speed_33       = 33,
 133         i40e_bus_speed_66       = 66,
 134         i40e_bus_speed_100      = 100,
 135         i40e_bus_speed_120      = 120,
 136         i40e_bus_speed_133      = 133,
 137         i40e_bus_speed_2500     = 2500,
 138         i40e_bus_speed_5000     = 5000,
 139         i40e_bus_speed_8000     = 8000,
 140         i40e_bus_speed_reserved
 141 };
 142
 143 /* PCI bus widths */
 144 enum i40e_bus_width {
 145         i40e_bus_width_unknown  = 0,
 146         i40e_bus_width_pcie_x1  = 1,
 147         i40e_bus_width_pcie_x2  = 2,
 148         i40e_bus_width_pcie_x4  = 4,
 149         i40e_bus_width_pcie_x8  = 8,
 150         i40e_bus_width_32       = 32,
 151         i40e_bus_width_64       = 64,
 152         i40e_bus_width_reserved
 153 };
 154
 155 /* Bus parameters */
 156 struct i40e_bus_info {
 157         enum i40e_bus_speed speed;
 158         enum i40e_bus_width width;
 159         enum i40e_bus_type type;
 160
 161         u16 func;
 162         u16 device;
 163         u16 lan_id;
 164         u16 bus_id;
 165 };
 166
 167 #define I40E_MAX_TRAFFIC_CLASS          8
 168 #define I40E_MAX_USER_PRIORITY          8
 169 /* Port hardware description */
 170 struct i40e_hw {
 171         u8 __iomem *hw_addr;
 172         void *back;
 173
 174         /* subsystem structs */
 175         struct i40e_mac_info mac;
 176         struct i40e_bus_info bus;
 177
 178         /* pci info */
 179         u16 device_id;
 180         u16 vendor_id;
 181         u16 subsystem_device_id;
 182         u16 subsystem_vendor_id;
 183         u8 revision_id;
 184
 185         /* capabilities for entire device and PCI func */
 186         struct i40e_hw_capabilities dev_caps;
 187
 188         /* Admin Queue info */
 189         struct i40e_adminq_info aq;
 190
 191         /* debug mask */
 192         u32 debug_mask;
 193         char err_str[16];
 194 };
 195
 196 static inline bool i40e_is_vf(struct i40e_hw *hw)
 197 {
 198         return (hw->mac.type == I40E_MAC_VF ||
 199                 hw->mac.type == I40E_MAC_X722_VF);
 200 }
 201
 202 struct i40e_driver_version {
 203         u8 major_version;
 204         u8 minor_version;
 205         u8 build_version;
 206         u8 subbuild_version;
 207         u8 driver_string[32];
 208 };
 209
 210 /* RX Descriptors */
 211 union i40e_16byte_rx_desc {
 212         struct {
 213                 __le64 pkt_addr; /* Packet buffer address */
 214                 __le64 hdr_addr; /* Header buffer address */
 215         } read;
 216         struct {
 217                 struct {
 218                         struct {
 219                                 union {
 220                                         __le16 mirroring_status;
 221                                         __le16 fcoe_ctx_id;
 222                                 } mirr_fcoe;
 223                                 __le16 l2tag1;
 224                         } lo_dword;
 225                         union {
 226                                 __le32 rss; /* RSS Hash */
 227                                 __le32 fd_id; /* Flow director filter id */
 228                                 __le32 fcoe_param; /* FCoE DDP Context id */
 229                         } hi_dword;
 230                 } qword0;
 231                 struct {
 232                         /* ext status/error/pktype/length */
 233                         __le64 status_error_len;
 234                 } qword1;
 235         } wb;  /* writeback */
 236 };
 237
 238 union i40e_32byte_rx_desc {
 239         struct {
 240                 __le64  pkt_addr; /* Packet buffer address */
 241                 __le64  hdr_addr; /* Header buffer address */
 242                         /* bit 0 of hdr_buffer_addr is DD bit */
 243                 __le64  rsvd1;
 244                 __le64  rsvd2;
 245         } read;
 246         struct {
 247                 struct {
 248                         struct {
 249                                 union {
 250                                         __le16 mirroring_status;
 251                                         __le16 fcoe_ctx_id;
 252                                 } mirr_fcoe;
 253                                 __le16 l2tag1;
 254                         } lo_dword;
 255                         union {
 256                                 __le32 rss; /* RSS Hash */
 257                                 __le32 fcoe_param; /* FCoE DDP Context id */
 258                                 /* Flow director filter id in case of
 259                                  * Programming status desc WB
 260                                  */
 261                                 __le32 fd_id;
 262                         } hi_dword;
 263                 } qword0;
 264                 struct {
 265                         /* status/error/pktype/length */
 266                         __le64 status_error_len;
 267                 } qword1;
 268                 struct {
 269                         __le16 ext_status; /* extended status */
 270                         __le16 rsvd;
 271                         __le16 l2tag2_1;
 272                         __le16 l2tag2_2;
 273                 } qword2;
 274                 struct {
 275                         union {
 276                                 __le32 flex_bytes_lo;
 277                                 __le32 pe_status;
 278                         } lo_dword;
 279                         union {
 280                                 __le32 flex_bytes_hi;
 281                                 __le32 fd_id;
 282                         } hi_dword;
 283                 } qword3;
 284         } wb;  /* writeback */
 285 };
 286
 287 enum i40e_rx_desc_status_bits {
 288         /* Note: These are predefined bit offsets */
 289         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 290         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 291         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 292         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 293         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 294         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 295         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 296         /* Note: Bit 8 is reserved in X710 and XL710 */
 297         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 298         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 299         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 300         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 301         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 302         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 303         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 304         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 305          * UDP header
 306          */
 307         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 308         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 309 };
 310
 311 #define I40E_RXD_QW1_STATUS_SHIFT       0
 312 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 313                                          << I40E_RXD_QW1_STATUS_SHIFT)
 314
 315 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 316 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 317                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 318
 319 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 320 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 321                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 322
 323 enum i40e_rx_desc_fltstat_values {
 324         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 325         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 326         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 327         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 328 };
 329
 330 #define I40E_RXD_QW1_ERROR_SHIFT        19
 331 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 332
 333 enum i40e_rx_desc_error_bits {
 334         /* Note: These are predefined bit offsets */
 335         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 336         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 337         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 338         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 339         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 340         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 341         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 342         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 343         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 344 };
 345
 346 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 347         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 348         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 349         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 350         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 351         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 352 };
 353
 354 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 355 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 356
 357 /* Packet type non-ip values */
 358 enum i40e_rx_l2_ptype {
 359         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 360         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 361         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 362         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 363         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 364         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 365         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 366         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 367         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 368         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 369         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 370         I40E_RX_PTYPE_L2_ARP                            = 11,
 371         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 372         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 373         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 374         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 375         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 376         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 377         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 378         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 379         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 380         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 381         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 382         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 383         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 384         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 385 };
 386
 387 struct i40e_rx_ptype_decoded {
 388         u32 ptype:8;
 389         u32 known:1;
 390         u32 outer_ip:1;
 391         u32 outer_ip_ver:1;
 392         u32 outer_frag:1;
 393         u32 tunnel_type:3;
 394         u32 tunnel_end_prot:2;
 395         u32 tunnel_end_frag:1;
 396         u32 inner_prot:4;
 397         u32 payload_layer:3;
 398 };
 399
 400 enum i40e_rx_ptype_outer_ip {
 401         I40E_RX_PTYPE_OUTER_L2  = 0,
 402         I40E_RX_PTYPE_OUTER_IP  = 1
 403 };
 404
 405 enum i40e_rx_ptype_outer_ip_ver {
 406         I40E_RX_PTYPE_OUTER_NONE        = 0,
 407         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 408         I40E_RX_PTYPE_OUTER_IPV6        = 1
 409 };
 410
 411 enum i40e_rx_ptype_outer_fragmented {
 412         I40E_RX_PTYPE_NOT_FRAG  = 0,
 413         I40E_RX_PTYPE_FRAG      = 1
 414 };
 415
 416 enum i40e_rx_ptype_tunnel_type {
 417         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 418         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 419         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 420         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 421         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 422 };
 423
 424 enum i40e_rx_ptype_tunnel_end_prot {
 425         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 426         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 427         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 428 };
 429
 430 enum i40e_rx_ptype_inner_prot {
 431         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 432         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 433         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 434         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 435         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 436         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 437 };
 438
 439 enum i40e_rx_ptype_payload_layer {
 440         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 441         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 442         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 443         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 444 };
 445
 446 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 447 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 448                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 449
 450 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 451 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 452                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 453
 454 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 455 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 456
 457 enum i40e_rx_desc_ext_status_bits {
 458         /* Note: These are predefined bit offsets */
 459         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 460         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 461         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 462         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 463         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 464         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 465         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 466 };
 467
 468 enum i40e_rx_desc_pe_status_bits {
 469         /* Note: These are predefined bit offsets */
 470         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 471         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 472         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 473         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 474         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 475         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 476         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 477         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 478         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 479 };
 480
 481 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 482 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 483
 484 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 485 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 486                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 487
 488 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 489 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 490                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 491
 492 enum i40e_rx_prog_status_desc_status_bits {
 493         /* Note: These are predefined bit offsets */
 494         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 495         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 496 };
 497
 498 enum i40e_rx_prog_status_desc_prog_id_masks {
 499         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 500         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 501         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 502 };
 503
 504 enum i40e_rx_prog_status_desc_error_bits {
 505         /* Note: These are predefined bit offsets */
 506         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 507         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 508         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 509         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 510 };
 511
 512 /* TX Descriptor */
 513 struct i40e_tx_desc {
 514         __le64 buffer_addr; /* Address of descriptor's data buf */
 515         __le64 cmd_type_offset_bsz;
 516 };
 517
 518 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 519 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 520
 521 enum i40e_tx_desc_dtype_value {
 522         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 523         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 524         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 525         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 526         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 527         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 528         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 529         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 530         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 531         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 532 };
 533
 534 #define I40E_TXD_QW1_CMD_SHIFT  4
 535 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 536
 537 enum i40e_tx_desc_cmd_bits {
 538         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 539         I40E_TX_DESC_CMD_RS                     = 0x0002,
 540         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 541         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 542         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 543         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 544         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 545         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 546         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 547         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 548         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 549         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 550         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 551         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 552         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 553         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 554         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 555         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 556 };
 557
 558 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 559 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 560                                          I40E_TXD_QW1_OFFSET_SHIFT)
 561
 562 enum i40e_tx_desc_length_fields {
 563         /* Note: These are predefined bit offsets */
 564         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 565         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 566         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 567 };
 568
 569 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 570 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 571                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 572
 573 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 574 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 575
 576 /* Context descriptors */
 577 struct i40e_tx_context_desc {
 578         __le32 tunneling_params;
 579         __le16 l2tag2;
 580         __le16 rsvd;
 581         __le64 type_cmd_tso_mss;
 582 };
 583
 584 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 585 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 586
 587 enum i40e_tx_ctx_desc_cmd_bits {
 588         I40E_TX_CTX_DESC_TSO            = 0x01,
 589         I40E_TX_CTX_DESC_TSYN           = 0x02,
 590         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 591         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 592         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 593         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 594         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 595         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 596         I40E_TX_CTX_DESC_SWPE           = 0x40
 597 };
 598
 599 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 600 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 601                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 602
 603 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 604 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 605                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 606
 607 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 608 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 609
 610 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 611 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 612                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 613
 614 enum i40e_tx_ctx_desc_eipt_offload {
 615         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 616         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 617         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 618         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 619 };
 620
 621 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 622 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 623                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 624
 625 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 626 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 627
 628 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
 629 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 630
 631 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 632 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
 633                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 634
 635 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 636
 637 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 638 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 639                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 640
 641 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 642 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 643                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 644
 645 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
 646 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
 647
 648 /* Packet Classifier Types for filters */
 649 enum i40e_filter_pctype {
 650         /* Note: Values 0-28 are reserved for future use.
 651          * Value 29, 30, 32 are not supported on XL710 and X710.
 652          */
 653         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 654         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 655         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 656         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
 657         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 658         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 659         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 660         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 661         /* Note: Values 37-38 are reserved for future use.
 662          * Value 39, 40, 42 are not supported on XL710 and X710.
 663          */
 664         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
 665         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
 666         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 667         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
 668         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 669         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 670         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 671         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 672         /* Note: Value 47 is reserved for future use */
 673         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 674         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 675         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 676         /* Note: Values 51-62 are reserved for future use */
 677         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 678 };
 679
 680
 681 struct i40e_vsi_context {
 682         u16 seid;
 683         u16 uplink_seid;
 684         u16 vsi_number;
 685         u16 vsis_allocated;
 686         u16 vsis_unallocated;
 687         u16 flags;
 688         u8 pf_num;
 689         u8 vf_num;
 690         u8 connection_type;
 691         struct i40e_aqc_vsi_properties_data info;
 692 };
 693
 694 struct i40e_veb_context {
 695         u16 seid;
 696         u16 uplink_seid;
 697         u16 veb_number;
 698         u16 vebs_allocated;
 699         u16 vebs_unallocated;
 700         u16 flags;
 701         struct i40e_aqc_get_veb_parameters_completion info;
 702 };
 703
 704 /* Statistics collected by each port, VSI, VEB, and S-channel */
 705 struct i40e_eth_stats {
 706         u64 rx_bytes;                   /* gorc */
 707         u64 rx_unicast;                 /* uprc */
 708         u64 rx_multicast;               /* mprc */
 709         u64 rx_broadcast;               /* bprc */
 710         u64 rx_discards;                /* rdpc */
 711         u64 rx_unknown_protocol;        /* rupp */
 712         u64 tx_bytes;                   /* gotc */
 713         u64 tx_unicast;                 /* uptc */
 714         u64 tx_multicast;               /* mptc */
 715         u64 tx_broadcast;               /* bptc */
 716         u64 tx_discards;                /* tdpc */
 717         u64 tx_errors;                  /* tepc */
 718 };
 719 #endif /* _I40E_TYPE_H_ */