1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
4 #ifndef _E1000_DEFINES_H_
5 #define _E1000_DEFINES_H_
7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
8 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
9 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
11 /* Definitions for power management and wakeup registers */
13 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
15 /* Wake Up Filter Control */
16 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
17 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
18 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
19 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
20 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
23 #define E1000_WUS_EX 0x00000004 /* Directed Exact */
24 #define E1000_WUS_ARPD 0x00000020 /* Directed ARP Request */
25 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 */
26 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 */
27 #define E1000_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */
29 /* Packet types that are enabled for wake packet delivery */
30 #define WAKE_PKT_WUS ( \
37 /* Wake Up Packet Length */
38 #define E1000_WUPL_MASK 0x00000FFF
40 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
41 #define E1000_WUPM_BYTES 128
43 /* Extended Device Control */
44 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */
45 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
46 #define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
47 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */
49 /* Physical Func Reset Done Indication */
50 #define E1000_CTRL_EXT_PFRSTD 0x00004000
51 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
52 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
53 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
54 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
55 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
56 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
57 #define E1000_CTRL_EXT_EIAME 0x01000000
58 #define E1000_CTRL_EXT_IRCA 0x00000001
59 /* Interrupt delay cancellation */
60 /* Driver loaded bit for FW */
61 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000
62 /* Interrupt acknowledge Auto-mask */
63 /* Clear Interrupt timers after IMS clear */
64 /* packet buffer parity error detection enabled */
65 /* descriptor FIFO parity error detection enable */
66 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
67 #define E1000_CTRL_EXT_PHYPDEN 0x00100000
68 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
69 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
70 #define E1000_I2CCMD_OPCODE_READ 0x08000000
71 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
72 #define E1000_I2CCMD_READY 0x20000000
73 #define E1000_I2CCMD_ERROR 0x80000000
74 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
75 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
76 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
77 #define E1000_I2CCMD_PHY_TIMEOUT 200
78 #define E1000_IVAR_VALID 0x80
79 #define E1000_GPIE_NSICR 0x00000001
80 #define E1000_GPIE_MSIX_MODE 0x00000010
81 #define E1000_GPIE_EIAME 0x40000000
82 #define E1000_GPIE_PBA 0x80000000
84 /* Receive Descriptor bit definitions */
85 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
86 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
87 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
88 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
89 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
90 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
91 #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
93 #define E1000_RXDEXT_STATERR_LB 0x00040000
94 #define E1000_RXDEXT_STATERR_CE 0x01000000
95 #define E1000_RXDEXT_STATERR_SE 0x02000000
96 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
97 #define E1000_RXDEXT_STATERR_CXE 0x10000000
98 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
99 #define E1000_RXDEXT_STATERR_IPE 0x40000000
100 #define E1000_RXDEXT_STATERR_RXE 0x80000000
102 /* Same mask, but for extended and packet split descriptors */
103 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
104 E1000_RXDEXT_STATERR_CE | \
105 E1000_RXDEXT_STATERR_SE | \
106 E1000_RXDEXT_STATERR_SEQ | \
107 E1000_RXDEXT_STATERR_CXE | \
108 E1000_RXDEXT_STATERR_RXE)
110 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
111 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
112 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
113 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
114 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
117 /* Management Control */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
120 #define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */
121 /* Enable Neighbor Discovery Filtering */
122 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
123 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
124 /* Enable MAC address filtering */
125 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
127 /* Receive Control */
128 #define E1000_RCTL_EN 0x00000002 /* enable */
129 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
130 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
131 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
132 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
133 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
134 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
135 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
136 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
137 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
138 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
139 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
140 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
141 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
142 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */
143 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
144 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
146 /* Use byte values for the following shift parameters
148 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
149 * E1000_PSRCTL_BSIZE0_MASK) |
150 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
151 * E1000_PSRCTL_BSIZE1_MASK) |
152 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
153 * E1000_PSRCTL_BSIZE2_MASK) |
154 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
155 * E1000_PSRCTL_BSIZE3_MASK))
156 * where value0 = [128..16256], default=256
157 * value1 = [1024..64512], default=4096
158 * value2 = [0..64512], default=4096
159 * value3 = [0..64512], default=0
162 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
163 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
164 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
165 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
167 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
168 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
169 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
170 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
172 /* SWFW_SYNC Definitions */
173 #define E1000_SWFW_EEP_SM 0x1
174 #define E1000_SWFW_PHY0_SM 0x2
175 #define E1000_SWFW_PHY1_SM 0x4
176 #define E1000_SWFW_PHY2_SM 0x20
177 #define E1000_SWFW_PHY3_SM 0x40
179 /* FACTPS Definitions */
181 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
182 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
183 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
187 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
188 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
189 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
190 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
191 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
192 /* Defined polarity of Dock/Undock indication in SDP[0] */
193 /* Reset both PHY ports, through PHYRST_N pin */
194 /* enable link status from external LINK_0 and LINK_1 pins */
195 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
196 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
197 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
198 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
199 #define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
200 #define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
201 #define E1000_CTRL_RST 0x04000000 /* Global reset */
202 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
203 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
204 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
205 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
206 /* Initiate an interrupt to manageability engine */
207 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
209 /* Bit definitions for the Management Data IO (MDIO) and Management Data
210 * Clock (MDC) pins in the Device Control Register.
213 #define E1000_CONNSW_ENRGSRC 0x4
214 #define E1000_CONNSW_PHYSD 0x400
215 #define E1000_CONNSW_PHY_PDN 0x800
216 #define E1000_CONNSW_SERDESD 0x200
217 #define E1000_CONNSW_AUTOSENSE_CONF 0x2
218 #define E1000_CONNSW_AUTOSENSE_EN 0x1
219 #define E1000_PCS_CFG_PCS_EN 8
220 #define E1000_PCS_LCTL_FLV_LINK_UP 1
221 #define E1000_PCS_LCTL_FSV_100 2
222 #define E1000_PCS_LCTL_FSV_1000 4
223 #define E1000_PCS_LCTL_FDV_FULL 8
224 #define E1000_PCS_LCTL_FSD 0x10
225 #define E1000_PCS_LCTL_FORCE_LINK 0x20
226 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
227 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
228 #define E1000_PCS_LCTL_AN_RESTART 0x20000
229 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
230 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
232 #define E1000_PCS_LSTS_LINK_OK 1
233 #define E1000_PCS_LSTS_SPEED_100 2
234 #define E1000_PCS_LSTS_SPEED_1000 4
235 #define E1000_PCS_LSTS_DUPLEX_FULL 8
236 #define E1000_PCS_LSTS_SYNK_OK 0x10
239 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
240 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
241 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
242 #define E1000_STATUS_FUNC_SHIFT 2
243 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
244 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
245 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
246 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
247 /* Change in Dock/Undock state. Clear on write '0'. */
248 /* Status of Master requests. */
249 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
250 /* BMC external code execution disabled */
252 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
253 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
257 #define SPEED_100 100
258 #define SPEED_1000 1000
259 #define SPEED_2500 2500
260 #define HALF_DUPLEX 1
261 #define FULL_DUPLEX 2
264 #define ADVERTISE_10_HALF 0x0001
265 #define ADVERTISE_10_FULL 0x0002
266 #define ADVERTISE_100_HALF 0x0004
267 #define ADVERTISE_100_FULL 0x0008
268 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
269 #define ADVERTISE_1000_FULL 0x0020
271 /* 1000/H is not supported, nor spec-compliant. */
272 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
273 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
275 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
276 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
277 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
278 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
279 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
281 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
283 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
286 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
287 #define E1000_LEDCTL_LED0_BLINK 0x00000080
288 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
289 #define E1000_LEDCTL_LED0_IVRT 0x00000040
291 #define E1000_LEDCTL_MODE_LED_ON 0xE
292 #define E1000_LEDCTL_MODE_LED_OFF 0xF
294 /* Transmit Descriptor bit definitions */
295 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
296 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
297 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
298 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
299 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
300 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
301 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
302 /* Extended desc bits for Linksec and timesync */
304 /* Transmit Control */
305 #define E1000_TCTL_EN 0x00000002 /* enable tx */
306 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
307 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
308 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
309 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
311 /* DMA Coalescing register fields */
312 #define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coal Watchdog Timer */
313 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coal Rx Threshold */
314 #define E1000_DMACR_DMACTHR_SHIFT 16
315 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe trans */
316 #define E1000_DMACR_DMAC_LX_SHIFT 28
317 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
318 /* DMA Coalescing BMC-to-OS Watchdog Enable */
319 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
321 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */
323 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
325 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate Thresh */
326 #define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx pkt rate curr window */
328 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Current Cnt */
330 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* FC Rx Thresh High val */
331 #define E1000_FCRTC_RTH_COAL_SHIFT 4
332 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */
334 /* Timestamp in Rx buffer */
335 #define E1000_RXPBS_CFG_TS_EN 0x80000000
337 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
338 #define I210_RXPBSIZE_MASK 0x0000003F
339 #define I210_RXPBSIZE_PB_32KB 0x00000020
340 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
341 #define I210_TXPBSIZE_MASK 0xC0FFFFFF
342 #define I210_TXPBSIZE_PB0_8KB (8 << 0)
343 #define I210_TXPBSIZE_PB1_8KB (8 << 6)
344 #define I210_TXPBSIZE_PB2_4KB (4 << 12)
345 #define I210_TXPBSIZE_PB3_4KB (4 << 18)
347 #define I210_DTXMXPKTSZ_DEFAULT 0x00000098
349 #define I210_SR_QUEUES_NUM 2
352 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
354 /* Receive Checksum Control */
355 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
356 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
357 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
358 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
360 /* Header split receive */
361 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
362 #define E1000_RFCTL_LEF 0x00040000
364 /* Collision related configuration parameters */
365 #define E1000_COLLISION_THRESHOLD 15
366 #define E1000_CT_SHIFT 4
367 #define E1000_COLLISION_DISTANCE 63
368 #define E1000_COLD_SHIFT 12
370 /* Ethertype field values */
371 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
373 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
374 #define MAX_JUMBO_FRAME_SIZE 0x2600
375 #define MAX_STD_JUMBO_FRAME_SIZE 9216
378 #define E1000_PBA_34K 0x0022
379 #define E1000_PBA_64K 0x0040 /* 64KB */
381 /* SW Semaphore Register */
382 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
383 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
385 /* Interrupt Cause Read */
386 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
387 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
388 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
389 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
390 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
391 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
392 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
393 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
394 /* If this bit asserted, the driver should claim the interrupt */
395 #define E1000_ICR_INT_ASSERTED 0x80000000
396 /* LAN connected device generates an interrupt */
397 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
399 /* Extended Interrupt Cause Read */
400 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
401 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
402 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
403 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
404 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
405 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
406 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
407 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
408 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
411 /* This defines the bits that are set in the Interrupt Mask
412 * Set/Read Register. Each bit is documented below:
413 * o RXT0 = Receiver Timer Interrupt (ring 0)
414 * o TXDW = Transmit Descriptor Written Back
415 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
416 * o RXSEQ = Receive Sequence Error
417 * o LSC = Link Status Change
419 #define IMS_ENABLE_MASK ( \
427 /* Interrupt Mask Set */
428 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
429 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
430 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
431 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
432 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
433 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
434 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
435 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
436 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
438 /* Extended Interrupt Mask Set */
439 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
441 /* Interrupt Cause Set */
442 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
443 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
444 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
446 /* Extended Interrupt Cause Set */
447 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
448 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
451 /* Transmit Descriptor Control */
452 /* Enable the counting of descriptors still to be processed. */
454 /* Flow Control Constants */
455 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
456 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
457 #define FLOW_CONTROL_TYPE 0x8808
459 /* Transmit Config Word */
460 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
461 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
463 /* 802.1q VLAN Packet Size */
464 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
465 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
467 /* Receive Address */
468 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
469 * Registers) holds the directed and multicast addresses that we monitor.
470 * Technically, we have 16 spots. However, we reserve one of these spots
471 * (RAR[15]) for our directed address used by controllers with
472 * manageability enabled, allowing us room for 15 multicast addresses.
474 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
475 #define E1000_RAH_ASEL_SRC_ADDR 0x00010000
476 #define E1000_RAH_QSEL_ENABLE 0x10000000
477 #define E1000_RAL_MAC_ADDR_LEN 4
478 #define E1000_RAH_MAC_ADDR_LEN 2
479 #define E1000_RAH_POOL_MASK 0x03FC0000
480 #define E1000_RAH_POOL_1 0x00040000
483 #define E1000_ERR_NVM 1
484 #define E1000_ERR_PHY 2
485 #define E1000_ERR_CONFIG 3
486 #define E1000_ERR_PARAM 4
487 #define E1000_ERR_MAC_INIT 5
488 #define E1000_ERR_RESET 9
489 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
490 #define E1000_BLK_PHY_RESET 12
491 #define E1000_ERR_SWFW_SYNC 13
492 #define E1000_NOT_IMPLEMENTED 14
493 #define E1000_ERR_MBX 15
494 #define E1000_ERR_INVALID_ARGUMENT 16
495 #define E1000_ERR_NO_SPACE 17
496 #define E1000_ERR_NVM_PBA_SECTION 18
497 #define E1000_ERR_INVM_VALUE_NOT_FOUND 19
498 #define E1000_ERR_I2C 20
500 /* Loop limit on how long we wait for auto-negotiation to complete */
501 #define COPPER_LINK_UP_LIMIT 10
502 #define PHY_AUTO_NEG_LIMIT 45
503 #define PHY_FORCE_LIMIT 20
504 /* Number of 100 microseconds we wait for PCI Express master disable */
505 #define MASTER_DISABLE_TIMEOUT 800
506 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
507 #define PHY_CFG_TIMEOUT 100
508 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
509 /* Number of milliseconds for NVM auto read done after MAC reset. */
510 #define AUTO_READ_DONE_TIMEOUT 10
513 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
515 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */
516 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */
518 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */
519 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */
520 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
521 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
522 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
523 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
524 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
525 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */
527 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
528 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
529 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
530 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
531 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
532 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
534 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
535 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
536 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
537 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
538 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
539 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
540 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
541 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
542 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
543 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
544 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
546 #define E1000_TIMINCA_16NS_SHIFT 24
548 /* Time Sync Interrupt Cause/Mask Register Bits */
550 #define TSINTR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
551 #define TSINTR_TXTS BIT(1) /* Transmit Timestamp. */
552 #define TSINTR_RXTS BIT(2) /* Receive Timestamp. */
553 #define TSINTR_TT0 BIT(3) /* Target Time 0 Trigger. */
554 #define TSINTR_TT1 BIT(4) /* Target Time 1 Trigger. */
555 #define TSINTR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */
556 #define TSINTR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
557 #define TSINTR_TADJ BIT(7) /* Time Adjust Done. */
559 #define TSYNC_INTERRUPTS TSINTR_TXTS
560 #define E1000_TSICR_TXTS TSINTR_TXTS
562 /* TSAUXC Configuration Bits */
563 #define TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
564 #define TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
565 #define TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
566 #define TSAUXC_SAMP_AUT0 BIT(3) /* Latch SYSTIML/H into AUXSTMPL/0. */
567 #define TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */
568 #define TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
569 #define TSAUXC_SAMP_AUT1 BIT(6) /* Latch SYSTIML/H into AUXSTMPL/1. */
570 #define TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
571 #define TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
572 #define TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */
573 #define TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
574 #define TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */
575 #define TSAUXC_PLSG BIT(17) /* Generate a pulse. */
576 #define TSAUXC_DISABLE BIT(31) /* Disable SYSTIM Count Operation. */
578 /* SDP Configuration Bits */
579 #define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
580 #define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
581 #define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
582 #define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
583 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
584 #define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
585 #define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
586 #define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
587 #define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
588 #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
589 #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
590 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
591 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
592 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
593 #define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
594 #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
595 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
596 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
597 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
598 #define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
599 #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
600 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
601 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
602 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
603 #define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
604 #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
605 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
606 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
607 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
608 #define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
610 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
611 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
612 #define E1000_MDICNFG_PHY_MASK 0x03E00000
613 #define E1000_MDICNFG_PHY_SHIFT 21
615 #define E1000_MEDIA_PORT_COPPER 1
616 #define E1000_MEDIA_PORT_OTHER 2
617 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
618 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
619 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
620 #define E1000_M88E1112_MAC_CTRL_1 0x10
621 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
622 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
623 #define E1000_M88E1112_PAGE_ADDR 0x16
624 #define E1000_M88E1112_STATUS 0x01
625 #define E1000_M88E1512_CFG_REG_1 0x0010
626 #define E1000_M88E1512_CFG_REG_2 0x0011
627 #define E1000_M88E1512_CFG_REG_3 0x0007
628 #define E1000_M88E1512_MODE 0x0014
630 /* PCI Express Control */
631 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
632 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
633 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
634 #define E1000_GCR_CAP_VER2 0x00040000
636 /* mPHY Address Control and Data Registers */
637 #define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */
638 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
639 #define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */
641 /* mPHY PCS CLK Register */
642 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */
643 /* mPHY Near End Digital Loopback Override Bit */
644 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
646 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
647 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
649 /* PHY Control Register */
650 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
651 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
652 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
653 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
654 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
655 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
656 #define MII_CR_SPEED_1000 0x0040
657 #define MII_CR_SPEED_100 0x2000
658 #define MII_CR_SPEED_10 0x0000
660 /* PHY Status Register */
661 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
662 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
664 /* Autoneg Advertisement Register */
665 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
666 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
667 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
668 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
669 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
670 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
672 /* Link Partner Ability Register (Base Page) */
673 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
674 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
676 /* Autoneg Expansion Register */
678 /* 1000BASE-T Control Register */
679 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
680 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
681 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
682 /* 0=Configure PHY as Slave */
683 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
684 /* 0=Automatic Master/Slave config */
686 /* 1000BASE-T Status Register */
687 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
688 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
691 /* PHY 1000 MII Register/Bit Definitions */
692 /* PHY Registers defined by IEEE */
693 #define PHY_CONTROL 0x00 /* Control Register */
694 #define PHY_STATUS 0x01 /* Status Register */
695 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
696 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
697 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
698 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
699 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
700 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
703 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
704 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
705 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
706 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
707 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
708 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
709 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
710 /* NVM Addressing bits based on type 0=small, 1=large */
711 #define E1000_EECD_ADDR_BITS 0x00000400
712 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
713 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
714 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
715 #define E1000_EECD_SIZE_EX_SHIFT 11
716 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
717 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
718 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
719 #define E1000_FLUDONE_ATTEMPTS 20000
720 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
721 #define E1000_I210_FIFO_SEL_RX 0x00
722 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
723 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
724 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
725 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
726 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
727 /* Secure FLASH mode requires removing MSb */
728 #define E1000_I210_FW_PTR_MASK 0x7FFF
729 /* Firmware code revision field word offset*/
730 #define E1000_I210_FW_VER_OFFSET 328
731 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
732 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
733 #define E1000_FLUDONE_ATTEMPTS 20000
734 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
735 #define E1000_I210_FIFO_SEL_RX 0x00
736 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
737 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
738 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
739 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
742 /* Offset to data in NVM read/write registers */
743 #define E1000_NVM_RW_REG_DATA 16
744 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
745 #define E1000_NVM_RW_REG_START 1 /* Start operation */
746 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
747 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
749 /* NVM Word Offsets */
750 #define NVM_COMPAT 0x0003
751 #define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */
752 #define NVM_VERSION 0x0005
753 #define NVM_INIT_CONTROL2_REG 0x000F
754 #define NVM_INIT_CONTROL3_PORT_B 0x0014
755 #define NVM_INIT_CONTROL3_PORT_A 0x0024
756 #define NVM_ALT_MAC_ADDR_PTR 0x0037
757 #define NVM_CHECKSUM_REG 0x003F
758 #define NVM_COMPATIBILITY_REG_3 0x0003
759 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
760 #define NVM_MAC_ADDR 0x0000
761 #define NVM_SUB_DEV_ID 0x000B
762 #define NVM_SUB_VEN_ID 0x000C
763 #define NVM_DEV_ID 0x000D
764 #define NVM_VEN_ID 0x000E
765 #define NVM_INIT_CTRL_2 0x000F
766 #define NVM_INIT_CTRL_4 0x0013
767 #define NVM_LED_1_CFG 0x001C
768 #define NVM_LED_0_2_CFG 0x001F
769 #define NVM_ETRACK_WORD 0x0042
770 #define NVM_ETRACK_HIWORD 0x0043
771 #define NVM_COMB_VER_OFF 0x0083
772 #define NVM_COMB_VER_PTR 0x003d
774 /* NVM version defines */
775 #define NVM_MAJOR_MASK 0xF000
776 #define NVM_MINOR_MASK 0x0FF0
777 #define NVM_IMAGE_ID_MASK 0x000F
778 #define NVM_COMB_VER_MASK 0x00FF
779 #define NVM_MAJOR_SHIFT 12
780 #define NVM_MINOR_SHIFT 4
781 #define NVM_COMB_VER_SHFT 8
782 #define NVM_VER_INVALID 0xFFFF
783 #define NVM_ETRACK_SHIFT 16
784 #define NVM_ETRACK_VALID 0x8000
785 #define NVM_NEW_DEC_MASK 0x0F00
786 #define NVM_HEX_CONV 16
787 #define NVM_HEX_TENS 10
789 #define NVM_ETS_CFG 0x003E
790 #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0
791 #define NVM_ETS_LTHRES_DELTA_SHIFT 6
792 #define NVM_ETS_TYPE_MASK 0x0038
793 #define NVM_ETS_TYPE_SHIFT 3
794 #define NVM_ETS_TYPE_EMC 0x000
795 #define NVM_ETS_NUM_SENSORS_MASK 0x0007
796 #define NVM_ETS_DATA_LOC_MASK 0x3C00
797 #define NVM_ETS_DATA_LOC_SHIFT 10
798 #define NVM_ETS_DATA_INDEX_MASK 0x0300
799 #define NVM_ETS_DATA_INDEX_SHIFT 8
800 #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF
802 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
803 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
804 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
805 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
807 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
809 /* Mask bits for fields in Word 0x24 of the NVM */
810 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
811 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */
813 /* Mask bits for fields in Word 0x0f of the NVM */
814 #define NVM_WORD0F_PAUSE_MASK 0x3000
815 #define NVM_WORD0F_ASM_DIR 0x2000
817 /* Mask bits for fields in Word 0x1a of the NVM */
819 /* length of string needed to store part num */
820 #define E1000_PBANUM_LENGTH 11
822 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
823 #define NVM_SUM 0xBABA
825 #define NVM_PBA_OFFSET_0 8
826 #define NVM_PBA_OFFSET_1 9
827 #define NVM_RESERVED_WORD 0xFFFF
828 #define NVM_PBA_PTR_GUARD 0xFAFA
829 #define NVM_WORD_SIZE_BASE_SHIFT 6
831 /* NVM Commands - Microwire */
833 /* NVM Commands - SPI */
834 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
835 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
836 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
837 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
838 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
839 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
841 /* SPI NVM Status Register */
842 #define NVM_STATUS_RDY_SPI 0x01
844 /* Word definitions for ID LED Settings */
845 #define ID_LED_RESERVED_0000 0x0000
846 #define ID_LED_RESERVED_FFFF 0xFFFF
847 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
848 (ID_LED_OFF1_OFF2 << 8) | \
849 (ID_LED_DEF1_DEF2 << 4) | \
851 #define ID_LED_DEF1_DEF2 0x1
852 #define ID_LED_DEF1_ON2 0x2
853 #define ID_LED_DEF1_OFF2 0x3
854 #define ID_LED_ON1_DEF2 0x4
855 #define ID_LED_ON1_ON2 0x5
856 #define ID_LED_ON1_OFF2 0x6
857 #define ID_LED_OFF1_DEF2 0x7
858 #define ID_LED_OFF1_ON2 0x8
859 #define ID_LED_OFF1_OFF2 0x9
861 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
862 #define IGP_ACTIVITY_LED_ENABLE 0x0300
863 #define IGP_LED3_MODE 0x07000000
865 /* PCI/PCI-X/PCI-EX Config space */
866 #define PCIE_DEVICE_CONTROL2 0x28
867 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
869 #define PHY_REVISION_MASK 0xFFFFFFF0
870 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
871 #define MAX_PHY_MULTI_PAGE_REG 0xF
873 /* Bit definitions for valid PHY IDs. */
877 #define M88E1111_I_PHY_ID 0x01410CC0
878 #define M88E1112_E_PHY_ID 0x01410C90
879 #define I347AT4_E_PHY_ID 0x01410DC0
880 #define IGP03E1000_E_PHY_ID 0x02A80390
881 #define I82580_I_PHY_ID 0x015403A0
882 #define I350_I_PHY_ID 0x015403B0
883 #define M88_VENDOR 0x0141
884 #define I210_I_PHY_ID 0x01410C00
885 #define M88E1543_E_PHY_ID 0x01410EA0
886 #define M88E1512_E_PHY_ID 0x01410DD0
887 #define BCM54616_E_PHY_ID 0x03625D10
889 /* M88E1000 Specific Registers */
890 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
891 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
892 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
894 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
895 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
897 /* M88E1000 PHY Specific Control Register */
898 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
899 /* 1=CLK125 low, 0=CLK125 toggling */
900 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
901 /* Manual MDI configuration */
902 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
903 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
904 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
905 /* Auto crossover enabled all speeds */
906 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
907 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
908 * 0=Normal 10BASE-T Rx Threshold
910 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
911 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
913 /* M88E1000 PHY Specific Status Register */
914 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
915 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
916 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
923 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
924 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
925 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
927 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
929 /* M88E1000 Extended PHY Specific Control Register */
930 /* 1 = Lost lock detect enabled.
931 * Will assert lost lock and bring
932 * link down if idle not seen
933 * within 1ms in 1000BASE-T
935 /* Number of times we will attempt to autonegotiate before downshifting if we
938 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
939 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
940 /* Number of times we will attempt to autonegotiate before downshifting if we
943 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
944 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
945 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
947 /* Intel i347-AT4 Registers */
949 #define I347AT4_PCDL0 0x10 /* Pair 0 PHY Cable Diagnostics Length */
950 #define I347AT4_PCDL1 0x11 /* Pair 1 PHY Cable Diagnostics Length */
951 #define I347AT4_PCDL2 0x12 /* Pair 2 PHY Cable Diagnostics Length */
952 #define I347AT4_PCDL3 0x13 /* Pair 3 PHY Cable Diagnostics Length */
953 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
954 #define I347AT4_PAGE_SELECT 0x16
956 /* i347-AT4 Extended PHY Specific Control Register */
958 /* Number of times we will attempt to autonegotiate before downshifting if we
961 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
962 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
963 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
964 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
965 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
966 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
967 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
968 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
969 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
970 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
972 /* i347-AT4 PHY Cable Diagnostics Control */
973 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
975 /* Marvell 1112 only registers */
976 #define M88E1112_VCT_DSP_DISTANCE 0x001A
978 /* M88EC018 Rev 2 specific DownShift settings */
979 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
980 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
983 #define E1000_MDIC_DATA_MASK 0x0000FFFF
984 #define E1000_MDIC_REG_MASK 0x001F0000
985 #define E1000_MDIC_REG_SHIFT 16
986 #define E1000_MDIC_PHY_MASK 0x03E00000
987 #define E1000_MDIC_PHY_SHIFT 21
988 #define E1000_MDIC_OP_WRITE 0x04000000
989 #define E1000_MDIC_OP_READ 0x08000000
990 #define E1000_MDIC_READY 0x10000000
991 #define E1000_MDIC_INT_EN 0x20000000
992 #define E1000_MDIC_ERROR 0x40000000
993 #define E1000_MDIC_DEST 0x80000000
996 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
997 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */
999 /* Energy Efficient Ethernet */
1000 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */
1001 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */
1002 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
1003 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */
1004 #define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */
1005 #define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */
1006 #define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */
1007 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
1008 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
1009 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
1010 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
1011 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
1012 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
1013 #define E1000_M88E1543_EEE_CTRL_1 0x0
1014 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
1015 #define E1000_M88E1543_FIBER_CTRL 0x0
1016 #define E1000_EEE_ADV_DEV_I354 7
1017 #define E1000_EEE_ADV_ADDR_I354 60
1018 #define E1000_EEE_ADV_100_SUPPORTED BIT(1) /* 100BaseTx EEE Supported */
1019 #define E1000_EEE_ADV_1000_SUPPORTED BIT(2) /* 1000BaseT EEE Supported */
1020 #define E1000_PCS_STATUS_DEV_I354 3
1021 #define E1000_PCS_STATUS_ADDR_I354 1
1022 #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */
1023 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
1024 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
1026 /* SerDes Control */
1027 #define E1000_GEN_CTL_READY 0x80000000
1028 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1029 #define E1000_GEN_POLL_TIMEOUT 640
1031 #define E1000_VFTA_ENTRY_SHIFT 5
1032 #define E1000_VFTA_ENTRY_MASK 0x7F
1033 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
1035 /* DMA Coalescing register fields */
1036 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */
1038 /* Tx Rate-Scheduler Config fields */
1039 #define E1000_RTTBCNRC_RS_ENA 0x80000000
1040 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1041 #define E1000_RTTBCNRC_RF_INT_SHIFT 14
1042 #define E1000_RTTBCNRC_RF_INT_MASK \
1043 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1045 #define E1000_VLAPQF_QUEUE_SEL(_n, q_idx) (q_idx << ((_n) * 4))
1046 #define E1000_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4))
1047 #define E1000_VLAPQF_QUEUE_MASK 0x03
1049 /* TX Qav Control fields */
1050 #define E1000_TQAVCTRL_XMIT_MODE BIT(0)
1051 #define E1000_TQAVCTRL_DATAFETCHARB BIT(4)
1052 #define E1000_TQAVCTRL_DATATRANARB BIT(8)
1053 #define E1000_TQAVCTRL_DATATRANTIM BIT(9)
1054 #define E1000_TQAVCTRL_SP_WAIT_SR BIT(10)
1055 /* Fetch Time Delta - bits 31:16
1057 * This field holds the value to be reduced from the launch time for
1058 * fetch time decision. The FetchTimeDelta value is defined in 32 ns
1061 * This field is 16 bits wide, and so the maximum value is:
1063 * 65535 * 32 = 2097120 ~= 2.1 msec
1065 * XXX: We are configuring the max value here since we couldn't come up
1066 * with a reason for not doing so.
1068 #define E1000_TQAVCTRL_FETCHTIME_DELTA (0xFFFF << 16)
1070 /* TX Qav Credit Control fields */
1071 #define E1000_TQAVCC_IDLESLOPE_MASK 0xFFFF
1072 #define E1000_TQAVCC_QUEUEMODE BIT(31)
1074 /* Transmit Descriptor Control fields */
1075 #define E1000_TXDCTL_PRIORITY BIT(27)
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