drivers/net/ethernet/intel/igb/igb_ptp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */
   3
   4 #include <linux/module.h>
   5 #include <linux/device.h>
   6 #include <linux/pci.h>
   7 #include <linux/ptp_classify.h>
   8
   9 #include "igb.h"
  10
  11 #define INCVALUE_MASK           0x7fffffff
  12 #define ISGN                    0x80000000
  13
  14 /* The 82580 timesync updates the system timer every 8ns by 8ns,
  15  * and this update value cannot be reprogrammed.
  16  *
  17  * Neither the 82576 nor the 82580 offer registers wide enough to hold
  18  * nanoseconds time values for very long. For the 82580, SYSTIM always
  19  * counts nanoseconds, but the upper 24 bits are not available. The
  20  * frequency is adjusted by changing the 32 bit fractional nanoseconds
  21  * register, TIMINCA.
  22  *
  23  * For the 82576, the SYSTIM register time unit is affect by the
  24  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
  25  * field are needed to provide the nominal 16 nanosecond period,
  26  * leaving 19 bits for fractional nanoseconds.
  27  *
  28  * We scale the NIC clock cycle by a large factor so that relatively
  29  * small clock corrections can be added or subtracted at each clock
  30  * tick. The drawbacks of a large factor are a) that the clock
  31  * register overflows more quickly (not such a big deal) and b) that
  32  * the increment per tick has to fit into 24 bits.  As a result we
  33  * need to use a shift of 19 so we can fit a value of 16 into the
  34  * TIMINCA register.
  35  *
  36  *
  37  *             SYSTIMH            SYSTIML
  38  *        +--------------+   +---+---+------+
  39  *  82576 |      32      |   | 8 | 5 |  19  |
  40  *        +--------------+   +---+---+------+
  41  *         \________ 45 bits _______/  fract
  42  *
  43  *        +----------+---+   +--------------+
  44  *  82580 |    24    | 8 |   |      32      |
  45  *        +----------+---+   +--------------+
  46  *          reserved  \______ 40 bits _____/
  47  *
  48  *
  49  * The 45 bit 82576 SYSTIM overflows every
  50  *   2^45 * 10^-9 / 3600 = 9.77 hours.
  51  *
  52  * The 40 bit 82580 SYSTIM overflows every
  53  *   2^40 * 10^-9 /  60  = 18.3 minutes.
  54  *
  55  * SYSTIM is converted to real time using a timecounter. As
  56  * timecounter_cyc2time() allows old timestamps, the timecounter
  57  * needs to be updated at least once per half of the SYSTIM interval.
  58  * Scheduling of delayed work is not very accurate, so we aim for 8
  59  * minutes to be sure the actual interval is shorter than 9.16 minutes.
  60  */
  61
  62 #define IGB_SYSTIM_OVERFLOW_PERIOD      (HZ * 60 * 8)
  63 #define IGB_PTP_TX_TIMEOUT              (HZ * 15)
  64 #define INCPERIOD_82576                 BIT(E1000_TIMINCA_16NS_SHIFT)
  65 #define INCVALUE_82576_MASK             GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
  66 #define INCVALUE_82576                  (16u << IGB_82576_TSYNC_SHIFT)
  67 #define IGB_NBITS_82580                 40
  68
  69 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
  70
  71 /* SYSTIM read access for the 82576 */
  72 static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
  73 {
  74         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
  75         struct e1000_hw *hw = &igb->hw;
  76         u64 val;
  77         u32 lo, hi;
  78
  79         lo = rd32(E1000_SYSTIML);
  80         hi = rd32(E1000_SYSTIMH);
  81
  82         val = ((u64) hi) << 32;
  83         val |= lo;
  84
  85         return val;
  86 }
  87
  88 /* SYSTIM read access for the 82580 */
  89 static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
  90 {
  91         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
  92         struct e1000_hw *hw = &igb->hw;
  93         u32 lo, hi;
  94         u64 val;
  95
  96         /* The timestamp latches on lowest register read. For the 82580
  97          * the lowest register is SYSTIMR instead of SYSTIML.  However we only
  98          * need to provide nanosecond resolution, so we just ignore it.
  99          */
 100         rd32(E1000_SYSTIMR);
 101         lo = rd32(E1000_SYSTIML);
 102         hi = rd32(E1000_SYSTIMH);
 103
 104         val = ((u64) hi) << 32;
 105         val |= lo;
 106
 107         return val;
 108 }
 109
 110 /* SYSTIM read access for I210/I211 */
 111 static void igb_ptp_read_i210(struct igb_adapter *adapter,
 112                               struct timespec64 *ts)
 113 {
 114         struct e1000_hw *hw = &adapter->hw;
 115         u32 sec, nsec;
 116
 117         /* The timestamp latches on lowest register read. For I210/I211, the
 118          * lowest register is SYSTIMR. Since we only need to provide nanosecond
 119          * resolution, we can ignore it.
 120          */
 121         rd32(E1000_SYSTIMR);
 122         nsec = rd32(E1000_SYSTIML);
 123         sec = rd32(E1000_SYSTIMH);
 124
 125         ts->tv_sec = sec;
 126         ts->tv_nsec = nsec;
 127 }
 128
 129 static void igb_ptp_write_i210(struct igb_adapter *adapter,
 130                                const struct timespec64 *ts)
 131 {
 132         struct e1000_hw *hw = &adapter->hw;
 133
 134         /* Writing the SYSTIMR register is not necessary as it only provides
 135          * sub-nanosecond resolution.
 136          */
 137         wr32(E1000_SYSTIML, ts->tv_nsec);
 138         wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
 139 }
 140
 141 /**
 142  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
 143  * @adapter: board private structure
 144  * @hwtstamps: timestamp structure to update
 145  * @systim: unsigned 64bit system time value.
 146  *
 147  * We need to convert the system time value stored in the RX/TXSTMP registers
 148  * into a hwtstamp which can be used by the upper level timestamping functions.
 149  *
 150  * The 'tmreg_lock' spinlock is used to protect the consistency of the
 151  * system time value. This is needed because reading the 64 bit time
 152  * value involves reading two (or three) 32 bit registers. The first
 153  * read latches the value. Ditto for writing.
 154  *
 155  * In addition, here have extended the system time with an overflow
 156  * counter in software.
 157  **/
 158 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
 159                                        struct skb_shared_hwtstamps *hwtstamps,
 160                                        u64 systim)
 161 {
 162         unsigned long flags;
 163         u64 ns;
 164
 165         switch (adapter->hw.mac.type) {
 166         case e1000_82576:
 167         case e1000_82580:
 168         case e1000_i354:
 169         case e1000_i350:
 170                 spin_lock_irqsave(&adapter->tmreg_lock, flags);
 171
 172                 ns = timecounter_cyc2time(&adapter->tc, systim);
 173
 174                 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 175
 176                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 177                 hwtstamps->hwtstamp = ns_to_ktime(ns);
 178                 break;
 179         case e1000_i210:
 180         case e1000_i211:
 181                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 182                 /* Upper 32 bits contain s, lower 32 bits contain ns. */
 183                 hwtstamps->hwtstamp = ktime_set(systim >> 32,
 184                                                 systim & 0xFFFFFFFF);
 185                 break;
 186         default:
 187                 break;
 188         }
 189 }
 190
 191 /* PTP clock operations */
 192 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
 193 {
 194         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 195                                                ptp_caps);
 196         struct e1000_hw *hw = &igb->hw;
 197         int neg_adj = 0;
 198         u64 rate;
 199         u32 incvalue;
 200
 201         if (ppb < 0) {
 202                 neg_adj = 1;
 203                 ppb = -ppb;
 204         }
 205         rate = ppb;
 206         rate <<= 14;
 207         rate = div_u64(rate, 1953125);
 208
 209         incvalue = 16 << IGB_82576_TSYNC_SHIFT;
 210
 211         if (neg_adj)
 212                 incvalue -= rate;
 213         else
 214                 incvalue += rate;
 215
 216         wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
 217
 218         return 0;
 219 }
 220
 221 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
 222 {
 223         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 224                                                ptp_caps);
 225         struct e1000_hw *hw = &igb->hw;
 226         int neg_adj = 0;
 227         u64 rate;
 228         u32 inca;
 229
 230         if (scaled_ppm < 0) {
 231                 neg_adj = 1;
 232                 scaled_ppm = -scaled_ppm;
 233         }
 234         rate = scaled_ppm;
 235         rate <<= 13;
 236         rate = div_u64(rate, 15625);
 237
 238         inca = rate & INCVALUE_MASK;
 239         if (neg_adj)
 240                 inca |= ISGN;
 241
 242         wr32(E1000_TIMINCA, inca);
 243
 244         return 0;
 245 }
 246
 247 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
 248 {
 249         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 250                                                ptp_caps);
 251         unsigned long flags;
 252
 253         spin_lock_irqsave(&igb->tmreg_lock, flags);
 254         timecounter_adjtime(&igb->tc, delta);
 255         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 256
 257         return 0;
 258 }
 259
 260 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
 261 {
 262         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 263                                                ptp_caps);
 264         unsigned long flags;
 265         struct timespec64 now, then = ns_to_timespec64(delta);
 266
 267         spin_lock_irqsave(&igb->tmreg_lock, flags);
 268
 269         igb_ptp_read_i210(igb, &now);
 270         now = timespec64_add(now, then);
 271         igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
 272
 273         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 274
 275         return 0;
 276 }
 277
 278 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
 279                                  struct timespec64 *ts)
 280 {
 281         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 282                                                ptp_caps);
 283         unsigned long flags;
 284         u64 ns;
 285
 286         spin_lock_irqsave(&igb->tmreg_lock, flags);
 287
 288         ns = timecounter_read(&igb->tc);
 289
 290         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 291
 292         *ts = ns_to_timespec64(ns);
 293
 294         return 0;
 295 }
 296
 297 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
 298                                 struct timespec64 *ts)
 299 {
 300         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 301                                                ptp_caps);
 302         unsigned long flags;
 303
 304         spin_lock_irqsave(&igb->tmreg_lock, flags);
 305
 306         igb_ptp_read_i210(igb, ts);
 307
 308         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 309
 310         return 0;
 311 }
 312
 313 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
 314                                  const struct timespec64 *ts)
 315 {
 316         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 317                                                ptp_caps);
 318         unsigned long flags;
 319         u64 ns;
 320
 321         ns = timespec64_to_ns(ts);
 322
 323         spin_lock_irqsave(&igb->tmreg_lock, flags);
 324
 325         timecounter_init(&igb->tc, &igb->cc, ns);
 326
 327         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 328
 329         return 0;
 330 }
 331
 332 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
 333                                 const struct timespec64 *ts)
 334 {
 335         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 336                                                ptp_caps);
 337         unsigned long flags;
 338
 339         spin_lock_irqsave(&igb->tmreg_lock, flags);
 340
 341         igb_ptp_write_i210(igb, ts);
 342
 343         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 344
 345         return 0;
 346 }
 347
 348 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
 349 {
 350         u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
 351         static const u32 mask[IGB_N_SDP] = {
 352                 E1000_CTRL_SDP0_DIR,
 353                 E1000_CTRL_SDP1_DIR,
 354                 E1000_CTRL_EXT_SDP2_DIR,
 355                 E1000_CTRL_EXT_SDP3_DIR,
 356         };
 357
 358         if (input)
 359                 *ptr &= ~mask[pin];
 360         else
 361                 *ptr |= mask[pin];
 362 }
 363
 364 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
 365 {
 366         static const u32 aux0_sel_sdp[IGB_N_SDP] = {
 367                 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
 368         };
 369         static const u32 aux1_sel_sdp[IGB_N_SDP] = {
 370                 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
 371         };
 372         static const u32 ts_sdp_en[IGB_N_SDP] = {
 373                 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
 374         };
 375         struct e1000_hw *hw = &igb->hw;
 376         u32 ctrl, ctrl_ext, tssdp = 0;
 377
 378         ctrl = rd32(E1000_CTRL);
 379         ctrl_ext = rd32(E1000_CTRL_EXT);
 380         tssdp = rd32(E1000_TSSDP);
 381
 382         igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
 383
 384         /* Make sure this pin is not enabled as an output. */
 385         tssdp &= ~ts_sdp_en[pin];
 386
 387         if (chan == 1) {
 388                 tssdp &= ~AUX1_SEL_SDP3;
 389                 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
 390         } else {
 391                 tssdp &= ~AUX0_SEL_SDP3;
 392                 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
 393         }
 394
 395         wr32(E1000_TSSDP, tssdp);
 396         wr32(E1000_CTRL, ctrl);
 397         wr32(E1000_CTRL_EXT, ctrl_ext);
 398 }
 399
 400 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
 401 {
 402         static const u32 aux0_sel_sdp[IGB_N_SDP] = {
 403                 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
 404         };
 405         static const u32 aux1_sel_sdp[IGB_N_SDP] = {
 406                 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
 407         };
 408         static const u32 ts_sdp_en[IGB_N_SDP] = {
 409                 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
 410         };
 411         static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
 412                 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
 413                 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
 414         };
 415         static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
 416                 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
 417                 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
 418         };
 419         static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
 420                 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
 421                 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
 422         };
 423         static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
 424                 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
 425                 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
 426         };
 427         static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
 428                 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
 429                 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
 430         };
 431         struct e1000_hw *hw = &igb->hw;
 432         u32 ctrl, ctrl_ext, tssdp = 0;
 433
 434         ctrl = rd32(E1000_CTRL);
 435         ctrl_ext = rd32(E1000_CTRL_EXT);
 436         tssdp = rd32(E1000_TSSDP);
 437
 438         igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
 439
 440         /* Make sure this pin is not enabled as an input. */
 441         if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
 442                 tssdp &= ~AUX0_TS_SDP_EN;
 443
 444         if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
 445                 tssdp &= ~AUX1_TS_SDP_EN;
 446
 447         tssdp &= ~ts_sdp_sel_clr[pin];
 448         if (freq) {
 449                 if (chan == 1)
 450                         tssdp |= ts_sdp_sel_fc1[pin];
 451                 else
 452                         tssdp |= ts_sdp_sel_fc0[pin];
 453         } else {
 454                 if (chan == 1)
 455                         tssdp |= ts_sdp_sel_tt1[pin];
 456                 else
 457                         tssdp |= ts_sdp_sel_tt0[pin];
 458         }
 459         tssdp |= ts_sdp_en[pin];
 460
 461         wr32(E1000_TSSDP, tssdp);
 462         wr32(E1000_CTRL, ctrl);
 463         wr32(E1000_CTRL_EXT, ctrl_ext);
 464 }
 465
 466 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
 467                                        struct ptp_clock_request *rq, int on)
 468 {
 469         struct igb_adapter *igb =
 470                 container_of(ptp, struct igb_adapter, ptp_caps);
 471         struct e1000_hw *hw = &igb->hw;
 472         u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
 473         unsigned long flags;
 474         struct timespec64 ts;
 475         int use_freq = 0, pin = -1;
 476         s64 ns;
 477
 478         switch (rq->type) {
 479         case PTP_CLK_REQ_EXTTS:
 480                 if (on) {
 481                         pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
 482                                            rq->extts.index);
 483                         if (pin < 0)
 484                                 return -EBUSY;
 485                 }
 486                 if (rq->extts.index == 1) {
 487                         tsauxc_mask = TSAUXC_EN_TS1;
 488                         tsim_mask = TSINTR_AUTT1;
 489                 } else {
 490                         tsauxc_mask = TSAUXC_EN_TS0;
 491                         tsim_mask = TSINTR_AUTT0;
 492                 }
 493                 spin_lock_irqsave(&igb->tmreg_lock, flags);
 494                 tsauxc = rd32(E1000_TSAUXC);
 495                 tsim = rd32(E1000_TSIM);
 496                 if (on) {
 497                         igb_pin_extts(igb, rq->extts.index, pin);
 498                         tsauxc |= tsauxc_mask;
 499                         tsim |= tsim_mask;
 500                 } else {
 501                         tsauxc &= ~tsauxc_mask;
 502                         tsim &= ~tsim_mask;
 503                 }
 504                 wr32(E1000_TSAUXC, tsauxc);
 505                 wr32(E1000_TSIM, tsim);
 506                 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 507                 return 0;
 508
 509         case PTP_CLK_REQ_PEROUT:
 510                 if (on) {
 511                         pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
 512                                            rq->perout.index);
 513                         if (pin < 0)
 514                                 return -EBUSY;
 515                 }
 516                 ts.tv_sec = rq->perout.period.sec;
 517                 ts.tv_nsec = rq->perout.period.nsec;
 518                 ns = timespec64_to_ns(&ts);
 519                 ns = ns >> 1;
 520                 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
 521                            (ns == 250000000LL) || (ns == 500000000LL))) {
 522                         if (ns < 8LL)
 523                                 return -EINVAL;
 524                         use_freq = 1;
 525                 }
 526                 ts = ns_to_timespec64(ns);
 527                 if (rq->perout.index == 1) {
 528                         if (use_freq) {
 529                                 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
 530                                 tsim_mask = 0;
 531                         } else {
 532                                 tsauxc_mask = TSAUXC_EN_TT1;
 533                                 tsim_mask = TSINTR_TT1;
 534                         }
 535                         trgttiml = E1000_TRGTTIML1;
 536                         trgttimh = E1000_TRGTTIMH1;
 537                         freqout = E1000_FREQOUT1;
 538                 } else {
 539                         if (use_freq) {
 540                                 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
 541                                 tsim_mask = 0;
 542                         } else {
 543                                 tsauxc_mask = TSAUXC_EN_TT0;
 544                                 tsim_mask = TSINTR_TT0;
 545                         }
 546                         trgttiml = E1000_TRGTTIML0;
 547                         trgttimh = E1000_TRGTTIMH0;
 548                         freqout = E1000_FREQOUT0;
 549                 }
 550                 spin_lock_irqsave(&igb->tmreg_lock, flags);
 551                 tsauxc = rd32(E1000_TSAUXC);
 552                 tsim = rd32(E1000_TSIM);
 553                 if (rq->perout.index == 1) {
 554                         tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
 555                         tsim &= ~TSINTR_TT1;
 556                 } else {
 557                         tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
 558                         tsim &= ~TSINTR_TT0;
 559                 }
 560                 if (on) {
 561                         int i = rq->perout.index;
 562                         igb_pin_perout(igb, i, pin, use_freq);
 563                         igb->perout[i].start.tv_sec = rq->perout.start.sec;
 564                         igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
 565                         igb->perout[i].period.tv_sec = ts.tv_sec;
 566                         igb->perout[i].period.tv_nsec = ts.tv_nsec;
 567                         wr32(trgttimh, rq->perout.start.sec);
 568                         wr32(trgttiml, rq->perout.start.nsec);
 569                         if (use_freq)
 570                                 wr32(freqout, ns);
 571                         tsauxc |= tsauxc_mask;
 572                         tsim |= tsim_mask;
 573                 }
 574                 wr32(E1000_TSAUXC, tsauxc);
 575                 wr32(E1000_TSIM, tsim);
 576                 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 577                 return 0;
 578
 579         case PTP_CLK_REQ_PPS:
 580                 spin_lock_irqsave(&igb->tmreg_lock, flags);
 581                 tsim = rd32(E1000_TSIM);
 582                 if (on)
 583                         tsim |= TSINTR_SYS_WRAP;
 584                 else
 585                         tsim &= ~TSINTR_SYS_WRAP;
 586                 igb->pps_sys_wrap_on = !!on;
 587                 wr32(E1000_TSIM, tsim);
 588                 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 589                 return 0;
 590         }
 591
 592         return -EOPNOTSUPP;
 593 }
 594
 595 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
 596                                   struct ptp_clock_request *rq, int on)
 597 {
 598         return -EOPNOTSUPP;
 599 }
 600
 601 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
 602                               enum ptp_pin_function func, unsigned int chan)
 603 {
 604         switch (func) {
 605         case PTP_PF_NONE:
 606         case PTP_PF_EXTTS:
 607         case PTP_PF_PEROUT:
 608                 break;
 609         case PTP_PF_PHYSYNC:
 610                 return -1;
 611         }
 612         return 0;
 613 }
 614
 615 /**
 616  * igb_ptp_tx_work
 617  * @work: pointer to work struct
 618  *
 619  * This work function polls the TSYNCTXCTL valid bit to determine when a
 620  * timestamp has been taken for the current stored skb.
 621  **/
 622 static void igb_ptp_tx_work(struct work_struct *work)
 623 {
 624         struct igb_adapter *adapter = container_of(work, struct igb_adapter,
 625                                                    ptp_tx_work);
 626         struct e1000_hw *hw = &adapter->hw;
 627         u32 tsynctxctl;
 628
 629         if (!adapter->ptp_tx_skb)
 630                 return;
 631
 632         if (time_is_before_jiffies(adapter->ptp_tx_start +
 633                                    IGB_PTP_TX_TIMEOUT)) {
 634                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 635                 adapter->ptp_tx_skb = NULL;
 636                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 637                 adapter->tx_hwtstamp_timeouts++;
 638                 /* Clear the tx valid bit in TSYNCTXCTL register to enable
 639                  * interrupt
 640                  */
 641                 rd32(E1000_TXSTMPH);
 642                 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
 643                 return;
 644         }
 645
 646         tsynctxctl = rd32(E1000_TSYNCTXCTL);
 647         if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
 648                 igb_ptp_tx_hwtstamp(adapter);
 649         else
 650                 /* reschedule to check later */
 651                 schedule_work(&adapter->ptp_tx_work);
 652 }
 653
 654 static void igb_ptp_overflow_check(struct work_struct *work)
 655 {
 656         struct igb_adapter *igb =
 657                 container_of(work, struct igb_adapter, ptp_overflow_work.work);
 658         struct timespec64 ts;
 659
 660         igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
 661
 662         pr_debug("igb overflow check at %lld.%09lu\n",
 663                  (long long) ts.tv_sec, ts.tv_nsec);
 664
 665         schedule_delayed_work(&igb->ptp_overflow_work,
 666                               IGB_SYSTIM_OVERFLOW_PERIOD);
 667 }
 668
 669 /**
 670  * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
 671  * @adapter: private network adapter structure
 672  *
 673  * This watchdog task is scheduled to detect error case where hardware has
 674  * dropped an Rx packet that was timestamped when the ring is full. The
 675  * particular error is rare but leaves the device in a state unable to timestamp
 676  * any future packets.
 677  **/
 678 void igb_ptp_rx_hang(struct igb_adapter *adapter)
 679 {
 680         struct e1000_hw *hw = &adapter->hw;
 681         u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
 682         unsigned long rx_event;
 683
 684         /* Other hardware uses per-packet timestamps */
 685         if (hw->mac.type != e1000_82576)
 686                 return;
 687
 688         /* If we don't have a valid timestamp in the registers, just update the
 689          * timeout counter and exit
 690          */
 691         if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
 692                 adapter->last_rx_ptp_check = jiffies;
 693                 return;
 694         }
 695
 696         /* Determine the most recent watchdog or rx_timestamp event */
 697         rx_event = adapter->last_rx_ptp_check;
 698         if (time_after(adapter->last_rx_timestamp, rx_event))
 699                 rx_event = adapter->last_rx_timestamp;
 700
 701         /* Only need to read the high RXSTMP register to clear the lock */
 702         if (time_is_before_jiffies(rx_event + 5 * HZ)) {
 703                 rd32(E1000_RXSTMPH);
 704                 adapter->last_rx_ptp_check = jiffies;
 705                 adapter->rx_hwtstamp_cleared++;
 706                 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
 707         }
 708 }
 709
 710 /**
 711  * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
 712  * @adapter: private network adapter structure
 713  */
 714 void igb_ptp_tx_hang(struct igb_adapter *adapter)
 715 {
 716         struct e1000_hw *hw = &adapter->hw;
 717         bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
 718                                               IGB_PTP_TX_TIMEOUT);
 719
 720         if (!adapter->ptp_tx_skb)
 721                 return;
 722
 723         if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
 724                 return;
 725
 726         /* If we haven't received a timestamp within the timeout, it is
 727          * reasonable to assume that it will never occur, so we can unlock the
 728          * timestamp bit when this occurs.
 729          */
 730         if (timeout) {
 731                 cancel_work_sync(&adapter->ptp_tx_work);
 732                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 733                 adapter->ptp_tx_skb = NULL;
 734                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 735                 adapter->tx_hwtstamp_timeouts++;
 736                 /* Clear the tx valid bit in TSYNCTXCTL register to enable
 737                  * interrupt
 738                  */
 739                 rd32(E1000_TXSTMPH);
 740                 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
 741         }
 742 }
 743
 744 /**
 745  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 746  * @adapter: Board private structure.
 747  *
 748  * If we were asked to do hardware stamping and such a time stamp is
 749  * available, then it must have been for this skb here because we only
 750  * allow only one such packet into the queue.
 751  **/
 752 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
 753 {
 754         struct sk_buff *skb = adapter->ptp_tx_skb;
 755         struct e1000_hw *hw = &adapter->hw;
 756         struct skb_shared_hwtstamps shhwtstamps;
 757         u64 regval;
 758         int adjust = 0;
 759
 760         regval = rd32(E1000_TXSTMPL);
 761         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
 762
 763         igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
 764         /* adjust timestamp for the TX latency based on link speed */
 765         if (adapter->hw.mac.type == e1000_i210) {
 766                 switch (adapter->link_speed) {
 767                 case SPEED_10:
 768                         adjust = IGB_I210_TX_LATENCY_10;
 769                         break;
 770                 case SPEED_100:
 771                         adjust = IGB_I210_TX_LATENCY_100;
 772                         break;
 773                 case SPEED_1000:
 774                         adjust = IGB_I210_TX_LATENCY_1000;
 775                         break;
 776                 }
 777         }
 778
 779         shhwtstamps.hwtstamp =
 780                 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
 781
 782         /* Clear the lock early before calling skb_tstamp_tx so that
 783          * applications are not woken up before the lock bit is clear. We use
 784          * a copy of the skb pointer to ensure other threads can't change it
 785          * while we're notifying the stack.
 786          */
 787         adapter->ptp_tx_skb = NULL;
 788         clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 789
 790         /* Notify the stack and free the skb after we've unlocked */
 791         skb_tstamp_tx(skb, &shhwtstamps);
 792         dev_kfree_skb_any(skb);
 793 }
 794
 795 /**
 796  * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
 797  * @q_vector: Pointer to interrupt specific structure
 798  * @va: Pointer to address containing Rx buffer
 799  * @skb: Buffer containing timestamp and packet
 800  *
 801  * This function is meant to retrieve a timestamp from the first buffer of an
 802  * incoming frame.  The value is stored in little endian format starting on
 803  * byte 8.
 804  **/
 805 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
 806                          struct sk_buff *skb)
 807 {
 808         __le64 *regval = (__le64 *)va;
 809         struct igb_adapter *adapter = q_vector->adapter;
 810         int adjust = 0;
 811
 812         /* The timestamp is recorded in little endian format.
 813          * DWORD: 0        1        2        3
 814          * Field: Reserved Reserved SYSTIML  SYSTIMH
 815          */
 816         igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
 817                                    le64_to_cpu(regval[1]));
 818
 819         /* adjust timestamp for the RX latency based on link speed */
 820         if (adapter->hw.mac.type == e1000_i210) {
 821                 switch (adapter->link_speed) {
 822                 case SPEED_10:
 823                         adjust = IGB_I210_RX_LATENCY_10;
 824                         break;
 825                 case SPEED_100:
 826                         adjust = IGB_I210_RX_LATENCY_100;
 827                         break;
 828                 case SPEED_1000:
 829                         adjust = IGB_I210_RX_LATENCY_1000;
 830                         break;
 831                 }
 832         }
 833         skb_hwtstamps(skb)->hwtstamp =
 834                 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
 835 }
 836
 837 /**
 838  * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
 839  * @q_vector: Pointer to interrupt specific structure
 840  * @skb: Buffer containing timestamp and packet
 841  *
 842  * This function is meant to retrieve a timestamp from the internal registers
 843  * of the adapter and store it in the skb.
 844  **/
 845 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
 846                          struct sk_buff *skb)
 847 {
 848         struct igb_adapter *adapter = q_vector->adapter;
 849         struct e1000_hw *hw = &adapter->hw;
 850         u64 regval;
 851         int adjust = 0;
 852
 853         /* If this bit is set, then the RX registers contain the time stamp. No
 854          * other packet will be time stamped until we read these registers, so
 855          * read the registers to make them available again. Because only one
 856          * packet can be time stamped at a time, we know that the register
 857          * values must belong to this one here and therefore we don't need to
 858          * compare any of the additional attributes stored for it.
 859          *
 860          * If nothing went wrong, then it should have a shared tx_flags that we
 861          * can turn into a skb_shared_hwtstamps.
 862          */
 863         if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
 864                 return;
 865
 866         regval = rd32(E1000_RXSTMPL);
 867         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
 868
 869         igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 870
 871         /* adjust timestamp for the RX latency based on link speed */
 872         if (adapter->hw.mac.type == e1000_i210) {
 873                 switch (adapter->link_speed) {
 874                 case SPEED_10:
 875                         adjust = IGB_I210_RX_LATENCY_10;
 876                         break;
 877                 case SPEED_100:
 878                         adjust = IGB_I210_RX_LATENCY_100;
 879                         break;
 880                 case SPEED_1000:
 881                         adjust = IGB_I210_RX_LATENCY_1000;
 882                         break;
 883                 }
 884         }
 885         skb_hwtstamps(skb)->hwtstamp =
 886                 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
 887
 888         /* Update the last_rx_timestamp timer in order to enable watchdog check
 889          * for error case of latched timestamp on a dropped packet.
 890          */
 891         adapter->last_rx_timestamp = jiffies;
 892 }
 893
 894 /**
 895  * igb_ptp_get_ts_config - get hardware time stamping config
 896  * @netdev:
 897  * @ifreq:
 898  *
 899  * Get the hwtstamp_config settings to return to the user. Rather than attempt
 900  * to deconstruct the settings from the registers, just return a shadow copy
 901  * of the last known settings.
 902  **/
 903 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
 904 {
 905         struct igb_adapter *adapter = netdev_priv(netdev);
 906         struct hwtstamp_config *config = &adapter->tstamp_config;
 907
 908         return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
 909                 -EFAULT : 0;
 910 }
 911
 912 /**
 913  * igb_ptp_set_timestamp_mode - setup hardware for timestamping
 914  * @adapter: networking device structure
 915  * @config: hwtstamp configuration
 916  *
 917  * Outgoing time stamping can be enabled and disabled. Play nice and
 918  * disable it when requested, although it shouldn't case any overhead
 919  * when no packet needs it. At most one packet in the queue may be
 920  * marked for time stamping, otherwise it would be impossible to tell
 921  * for sure to which packet the hardware time stamp belongs.
 922  *
 923  * Incoming time stamping has to be configured via the hardware
 924  * filters. Not all combinations are supported, in particular event
 925  * type has to be specified. Matching the kind of event packet is
 926  * not supported, with the exception of "all V2 events regardless of
 927  * level 2 or 4".
 928  */
 929 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
 930                                       struct hwtstamp_config *config)
 931 {
 932         struct e1000_hw *hw = &adapter->hw;
 933         u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
 934         u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 935         u32 tsync_rx_cfg = 0;
 936         bool is_l4 = false;
 937         bool is_l2 = false;
 938         u32 regval;
 939
 940         /* reserved for future extensions */
 941         if (config->flags)
 942                 return -EINVAL;
 943
 944         switch (config->tx_type) {
 945         case HWTSTAMP_TX_OFF:
 946                 tsync_tx_ctl = 0;
 947         case HWTSTAMP_TX_ON:
 948                 break;
 949         default:
 950                 return -ERANGE;
 951         }
 952
 953         switch (config->rx_filter) {
 954         case HWTSTAMP_FILTER_NONE:
 955                 tsync_rx_ctl = 0;
 956                 break;
 957         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 958                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 959                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
 960                 is_l4 = true;
 961                 break;
 962         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 963                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 964                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
 965                 is_l4 = true;
 966                 break;
 967         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 968         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 969         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 970         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 971         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 972         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 973         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 974         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 975         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 976                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
 977                 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 978                 is_l2 = true;
 979                 is_l4 = true;
 980                 break;
 981         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 982         case HWTSTAMP_FILTER_NTP_ALL:
 983         case HWTSTAMP_FILTER_ALL:
 984                 /* 82576 cannot timestamp all packets, which it needs to do to
 985                  * support both V1 Sync and Delay_Req messages
 986                  */
 987                 if (hw->mac.type != e1000_82576) {
 988                         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 989                         config->rx_filter = HWTSTAMP_FILTER_ALL;
 990                         break;
 991                 }
 992                 /* fall through */
 993         default:
 994                 config->rx_filter = HWTSTAMP_FILTER_NONE;
 995                 return -ERANGE;
 996         }
 997
 998         if (hw->mac.type == e1000_82575) {
 999                 if (tsync_rx_ctl | tsync_tx_ctl)
1000                         return -EINVAL;
1001                 return 0;
1002         }
1003
1004         /* Per-packet timestamping only works if all packets are
1005          * timestamped, so enable timestamping in all packets as
1006          * long as one Rx filter was configured.
1007          */
1008         if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1009                 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1010                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1011                 config->rx_filter = HWTSTAMP_FILTER_ALL;
1012                 is_l2 = true;
1013                 is_l4 = true;
1014
1015                 if ((hw->mac.type == e1000_i210) ||
1016                     (hw->mac.type == e1000_i211)) {
1017                         regval = rd32(E1000_RXPBS);
1018                         regval |= E1000_RXPBS_CFG_TS_EN;
1019                         wr32(E1000_RXPBS, regval);
1020                 }
1021         }
1022
1023         /* enable/disable TX */
1024         regval = rd32(E1000_TSYNCTXCTL);
1025         regval &= ~E1000_TSYNCTXCTL_ENABLED;
1026         regval |= tsync_tx_ctl;
1027         wr32(E1000_TSYNCTXCTL, regval);
1028
1029         /* enable/disable RX */
1030         regval = rd32(E1000_TSYNCRXCTL);
1031         regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1032         regval |= tsync_rx_ctl;
1033         wr32(E1000_TSYNCRXCTL, regval);
1034
1035         /* define which PTP packets are time stamped */
1036         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1037
1038         /* define ethertype filter for timestamped packets */
1039         if (is_l2)
1040                 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1041                      (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1042                       E1000_ETQF_1588 | /* enable timestamping */
1043                       ETH_P_1588));     /* 1588 eth protocol type */
1044         else
1045                 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1046
1047         /* L4 Queue Filter[3]: filter by destination port and protocol */
1048         if (is_l4) {
1049                 u32 ftqf = (IPPROTO_UDP /* UDP */
1050                         | E1000_FTQF_VF_BP /* VF not compared */
1051                         | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1052                         | E1000_FTQF_MASK); /* mask all inputs */
1053                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1054
1055                 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
1056                 wr32(E1000_IMIREXT(3),
1057                      (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1058                 if (hw->mac.type == e1000_82576) {
1059                         /* enable source port check */
1060                         wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1061                         ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1062                 }
1063                 wr32(E1000_FTQF(3), ftqf);
1064         } else {
1065                 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1066         }
1067         wrfl();
1068
1069         /* clear TX/RX time stamp registers, just to be sure */
1070         regval = rd32(E1000_TXSTMPL);
1071         regval = rd32(E1000_TXSTMPH);
1072         regval = rd32(E1000_RXSTMPL);
1073         regval = rd32(E1000_RXSTMPH);
1074
1075         return 0;
1076 }
1077
1078 /**
1079  * igb_ptp_set_ts_config - set hardware time stamping config
1080  * @netdev:
1081  * @ifreq:
1082  *
1083  **/
1084 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1085 {
1086         struct igb_adapter *adapter = netdev_priv(netdev);
1087         struct hwtstamp_config config;
1088         int err;
1089
1090         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1091                 return -EFAULT;
1092
1093         err = igb_ptp_set_timestamp_mode(adapter, &config);
1094         if (err)
1095                 return err;
1096
1097         /* save these settings for future reference */
1098         memcpy(&adapter->tstamp_config, &config,
1099                sizeof(adapter->tstamp_config));
1100
1101         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1102                 -EFAULT : 0;
1103 }
1104
1105 /**
1106  * igb_ptp_init - Initialize PTP functionality
1107  * @adapter: Board private structure
1108  *
1109  * This function is called at device probe to initialize the PTP
1110  * functionality.
1111  */
1112 void igb_ptp_init(struct igb_adapter *adapter)
1113 {
1114         struct e1000_hw *hw = &adapter->hw;
1115         struct net_device *netdev = adapter->netdev;
1116         int i;
1117
1118         switch (hw->mac.type) {
1119         case e1000_82576:
1120                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1121                 adapter->ptp_caps.owner = THIS_MODULE;
1122                 adapter->ptp_caps.max_adj = 999999881;
1123                 adapter->ptp_caps.n_ext_ts = 0;
1124                 adapter->ptp_caps.pps = 0;
1125                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1126                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1127                 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1128                 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1129                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1130                 adapter->cc.read = igb_ptp_read_82576;
1131                 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1132                 adapter->cc.mult = 1;
1133                 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1134                 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1135                 break;
1136         case e1000_82580:
1137         case e1000_i354:
1138         case e1000_i350:
1139                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1140                 adapter->ptp_caps.owner = THIS_MODULE;
1141                 adapter->ptp_caps.max_adj = 62499999;
1142                 adapter->ptp_caps.n_ext_ts = 0;
1143                 adapter->ptp_caps.pps = 0;
1144                 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1145                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1146                 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1147                 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1148                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1149                 adapter->cc.read = igb_ptp_read_82580;
1150                 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1151                 adapter->cc.mult = 1;
1152                 adapter->cc.shift = 0;
1153                 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1154                 break;
1155         case e1000_i210:
1156         case e1000_i211:
1157                 for (i = 0; i < IGB_N_SDP; i++) {
1158                         struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1159
1160                         snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1161                         ppd->index = i;
1162                         ppd->func = PTP_PF_NONE;
1163                 }
1164                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1165                 adapter->ptp_caps.owner = THIS_MODULE;
1166                 adapter->ptp_caps.max_adj = 62499999;
1167                 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1168                 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1169                 adapter->ptp_caps.n_pins = IGB_N_SDP;
1170                 adapter->ptp_caps.pps = 1;
1171                 adapter->ptp_caps.pin_config = adapter->sdp_config;
1172                 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1173                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1174                 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1175                 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1176                 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1177                 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1178                 break;
1179         default:
1180                 adapter->ptp_clock = NULL;
1181                 return;
1182         }
1183
1184         spin_lock_init(&adapter->tmreg_lock);
1185         INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1186
1187         if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1188                 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1189                                   igb_ptp_overflow_check);
1190
1191         adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1192         adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1193
1194         igb_ptp_reset(adapter);
1195
1196         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1197                                                 &adapter->pdev->dev);
1198         if (IS_ERR(adapter->ptp_clock)) {
1199                 adapter->ptp_clock = NULL;
1200                 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1201         } else if (adapter->ptp_clock) {
1202                 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1203                          adapter->netdev->name);
1204                 adapter->ptp_flags |= IGB_PTP_ENABLED;
1205         }
1206 }
1207
1208 /**
1209  * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1210  * @adapter: Board private structure
1211  *
1212  * This function stops the overflow check work and PTP Tx timestamp work, and
1213  * will prepare the device for OS suspend.
1214  */
1215 void igb_ptp_suspend(struct igb_adapter *adapter)
1216 {
1217         if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1218                 return;
1219
1220         if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1221                 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1222
1223         cancel_work_sync(&adapter->ptp_tx_work);
1224         if (adapter->ptp_tx_skb) {
1225                 dev_kfree_skb_any(adapter->ptp_tx_skb);
1226                 adapter->ptp_tx_skb = NULL;
1227                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1228         }
1229 }
1230
1231 /**
1232  * igb_ptp_stop - Disable PTP device and stop the overflow check.
1233  * @adapter: Board private structure.
1234  *
1235  * This function stops the PTP support and cancels the delayed work.
1236  **/
1237 void igb_ptp_stop(struct igb_adapter *adapter)
1238 {
1239         igb_ptp_suspend(adapter);
1240
1241         if (adapter->ptp_clock) {
1242                 ptp_clock_unregister(adapter->ptp_clock);
1243                 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1244                          adapter->netdev->name);
1245                 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1246         }
1247 }
1248
1249 /**
1250  * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1251  * @adapter: Board private structure.
1252  *
1253  * This function handles the reset work required to re-enable the PTP device.
1254  **/
1255 void igb_ptp_reset(struct igb_adapter *adapter)
1256 {
1257         struct e1000_hw *hw = &adapter->hw;
1258         unsigned long flags;
1259
1260         /* reset the tstamp_config */
1261         igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1262
1263         spin_lock_irqsave(&adapter->tmreg_lock, flags);
1264
1265         switch (adapter->hw.mac.type) {
1266         case e1000_82576:
1267                 /* Dial the nominal frequency. */
1268                 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1269                 break;
1270         case e1000_82580:
1271         case e1000_i354:
1272         case e1000_i350:
1273         case e1000_i210:
1274         case e1000_i211:
1275                 wr32(E1000_TSAUXC, 0x0);
1276                 wr32(E1000_TSSDP, 0x0);
1277                 wr32(E1000_TSIM,
1278                      TSYNC_INTERRUPTS |
1279                      (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1280                 wr32(E1000_IMS, E1000_IMS_TS);
1281                 break;
1282         default:
1283                 /* No work to do. */
1284                 goto out;
1285         }
1286
1287         /* Re-initialize the timer. */
1288         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1289                 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1290
1291                 igb_ptp_write_i210(adapter, &ts);
1292         } else {
1293                 timecounter_init(&adapter->tc, &adapter->cc,
1294                                  ktime_to_ns(ktime_get_real()));
1295         }
1296 out:
1297         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1298
1299         wrfl();
1300
1301         if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1302                 schedule_delayed_work(&adapter->ptp_overflow_work,
1303                                       IGB_SYSTIM_OVERFLOW_PERIOD);
1304 }