drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2016 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  31
  32 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  33 {
  34         struct ixgbe_mac_info *mac = &hw->mac;
  35         struct ixgbe_phy_info *phy = &hw->phy;
  36
  37         /* Start with X540 invariants, since so simular */
  38         ixgbe_get_invariants_X540(hw);
  39
  40         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  41                 phy->ops.set_phy_power = NULL;
  42
  43         return 0;
  44 }
  45
  46 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  47  *  @hw: pointer to hardware structure
  48  **/
  49 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  50 {
  51         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  52
  53         if (hw->bus.lan_id) {
  54                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  55                 esdp |= IXGBE_ESDP_SDP1_DIR;
  56         }
  57         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  58         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  59         IXGBE_WRITE_FLUSH(hw);
  60 }
  61
  62 /**
  63  * ixgbe_read_cs4227 - Read CS4227 register
  64  * @hw: pointer to hardware structure
  65  * @reg: register number to write
  66  * @value: pointer to receive value read
  67  *
  68  * Returns status code
  69  */
  70 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  71 {
  72         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  73                                                       value);
  74 }
  75
  76 /**
  77  * ixgbe_write_cs4227 - Write CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: value to write to register
  81  *
  82  * Returns status code
  83  */
  84 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  85 {
  86         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  87                                                        value);
  88 }
  89
  90 /**
  91  * ixgbe_read_pe - Read register from port expander
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to read
  94  * @value: pointer to receive read value
  95  *
  96  * Returns status code
  97  */
  98 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
  99 {
 100         s32 status;
 101
 102         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 103         if (status)
 104                 hw_err(hw, "port expander access failed with %d\n", status);
 105         return status;
 106 }
 107
 108 /**
 109  * ixgbe_write_pe - Write register to port expander
 110  * @hw: pointer to hardware structure
 111  * @reg: register number to write
 112  * @value: value to write
 113  *
 114  * Returns status code
 115  */
 116 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 117 {
 118         s32 status;
 119
 120         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 121                                                        value);
 122         if (status)
 123                 hw_err(hw, "port expander access failed with %d\n", status);
 124         return status;
 125 }
 126
 127 /**
 128  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 129  * @hw: pointer to hardware structure
 130  *
 131  * This function assumes that the caller has acquired the proper semaphore.
 132  * Returns error code
 133  */
 134 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 135 {
 136         s32 status;
 137         u32 retry;
 138         u16 value;
 139         u8 reg;
 140
 141         /* Trigger hard reset. */
 142         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 143         if (status)
 144                 return status;
 145         reg |= IXGBE_PE_BIT1;
 146         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 147         if (status)
 148                 return status;
 149
 150         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 151         if (status)
 152                 return status;
 153         reg &= ~IXGBE_PE_BIT1;
 154         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 155         if (status)
 156                 return status;
 157
 158         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 159         if (status)
 160                 return status;
 161         reg &= ~IXGBE_PE_BIT1;
 162         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 163         if (status)
 164                 return status;
 165
 166         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 167
 168         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 169         if (status)
 170                 return status;
 171         reg |= IXGBE_PE_BIT1;
 172         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 173         if (status)
 174                 return status;
 175
 176         /* Wait for the reset to complete. */
 177         msleep(IXGBE_CS4227_RESET_DELAY);
 178         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 179                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 180                                            &value);
 181                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 182                         break;
 183                 msleep(IXGBE_CS4227_CHECK_DELAY);
 184         }
 185         if (retry == IXGBE_CS4227_RETRIES) {
 186                 hw_err(hw, "CS4227 reset did not complete\n");
 187                 return IXGBE_ERR_PHY;
 188         }
 189
 190         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 191         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 192                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 193                 return IXGBE_ERR_PHY;
 194         }
 195
 196         return 0;
 197 }
 198
 199 /**
 200  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 201  * @hw: pointer to hardware structure
 202  */
 203 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 204 {
 205         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 206         s32 status;
 207         u16 value;
 208         u8 retry;
 209
 210         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 211                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 212                 if (status) {
 213                         hw_err(hw, "semaphore failed with %d\n", status);
 214                         msleep(IXGBE_CS4227_CHECK_DELAY);
 215                         continue;
 216                 }
 217
 218                 /* Get status of reset flow. */
 219                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 220                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 221                         goto out;
 222
 223                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 224                         break;
 225
 226                 /* Reset is pending. Wait and check again. */
 227                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 228                 msleep(IXGBE_CS4227_CHECK_DELAY);
 229         }
 230         /* If still pending, assume other instance failed. */
 231         if (retry == IXGBE_CS4227_RETRIES) {
 232                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 233                 if (status) {
 234                         hw_err(hw, "semaphore failed with %d\n", status);
 235                         return;
 236                 }
 237         }
 238
 239         /* Reset the CS4227. */
 240         status = ixgbe_reset_cs4227(hw);
 241         if (status) {
 242                 hw_err(hw, "CS4227 reset failed: %d", status);
 243                 goto out;
 244         }
 245
 246         /* Reset takes so long, temporarily release semaphore in case the
 247          * other driver instance is waiting for the reset indication.
 248          */
 249         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 250                            IXGBE_CS4227_RESET_PENDING);
 251         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 252         usleep_range(10000, 12000);
 253         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 254         if (status) {
 255                 hw_err(hw, "semaphore failed with %d", status);
 256                 return;
 257         }
 258
 259         /* Record completion for next time. */
 260         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 261                                     IXGBE_CS4227_RESET_COMPLETE);
 262
 263 out:
 264         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 265         msleep(hw->eeprom.semaphore_delay);
 266 }
 267
 268 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 269  *  @hw: pointer to hardware structure
 270  *
 271  *  Returns error code
 272  */
 273 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 274 {
 275         switch (hw->device_id) {
 276         case IXGBE_DEV_ID_X550EM_A_SFP:
 277                 if (hw->bus.lan_id)
 278                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 279                 else
 280                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 281                 return ixgbe_identify_module_generic(hw);
 282         case IXGBE_DEV_ID_X550EM_X_SFP:
 283                 /* set up for CS4227 usage */
 284                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 285                 ixgbe_setup_mux_ctl(hw);
 286                 ixgbe_check_cs4227(hw);
 287                 /* Fallthrough */
 288         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 289                 return ixgbe_identify_module_generic(hw);
 290         case IXGBE_DEV_ID_X550EM_X_KX4:
 291                 hw->phy.type = ixgbe_phy_x550em_kx4;
 292                 break;
 293         case IXGBE_DEV_ID_X550EM_X_KR:
 294         case IXGBE_DEV_ID_X550EM_A_KR:
 295         case IXGBE_DEV_ID_X550EM_A_KR_L:
 296                 hw->phy.type = ixgbe_phy_x550em_kr;
 297                 break;
 298         case IXGBE_DEV_ID_X550EM_A_10G_T:
 299                 if (hw->bus.lan_id)
 300                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 301                 else
 302                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 303                 /* Fallthrough */
 304         case IXGBE_DEV_ID_X550EM_X_1G_T:
 305         case IXGBE_DEV_ID_X550EM_X_10G_T:
 306                 return ixgbe_identify_phy_generic(hw);
 307         default:
 308                 break;
 309         }
 310         return 0;
 311 }
 312
 313 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 314                                      u32 device_type, u16 *phy_data)
 315 {
 316         return IXGBE_NOT_IMPLEMENTED;
 317 }
 318
 319 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 320                                       u32 device_type, u16 phy_data)
 321 {
 322         return IXGBE_NOT_IMPLEMENTED;
 323 }
 324
 325 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 326  *  @hw: pointer to hardware structure
 327  *
 328  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 329  *  ixgbe_hw struct in order to set up EEPROM access.
 330  **/
 331 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 332 {
 333         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 334         u32 eec;
 335         u16 eeprom_size;
 336
 337         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 338                 eeprom->semaphore_delay = 10;
 339                 eeprom->type = ixgbe_flash;
 340
 341                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 342                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 343                                     IXGBE_EEC_SIZE_SHIFT);
 344                 eeprom->word_size = BIT(eeprom_size +
 345                                         IXGBE_EEPROM_WORD_SIZE_SHIFT);
 346
 347                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 348                        eeprom->type, eeprom->word_size);
 349         }
 350
 351         return 0;
 352 }
 353
 354 /**
 355  * ixgbe_iosf_wait - Wait for IOSF command completion
 356  * @hw: pointer to hardware structure
 357  * @ctrl: pointer to location to receive final IOSF control value
 358  *
 359  * Return: failing status on timeout
 360  *
 361  * Note: ctrl can be NULL if the IOSF control register value is not needed
 362  */
 363 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 364 {
 365         u32 i, command;
 366
 367         /* Check every 10 usec to see if the address cycle completed.
 368          * The SB IOSF BUSY bit will clear when the operation is
 369          * complete.
 370          */
 371         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 372                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 373                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 374                         break;
 375                 udelay(10);
 376         }
 377         if (ctrl)
 378                 *ctrl = command;
 379         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 380                 hw_dbg(hw, "IOSF wait timed out\n");
 381                 return IXGBE_ERR_PHY;
 382         }
 383
 384         return 0;
 385 }
 386
 387 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 388  *  IOSF device
 389  *  @hw: pointer to hardware structure
 390  *  @reg_addr: 32 bit PHY register to write
 391  *  @device_type: 3 bit device type
 392  *  @phy_data: Pointer to read data from the register
 393  **/
 394 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 395                                        u32 device_type, u32 *data)
 396 {
 397         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 398         u32 command, error;
 399         s32 ret;
 400
 401         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 402         if (ret)
 403                 return ret;
 404
 405         ret = ixgbe_iosf_wait(hw, NULL);
 406         if (ret)
 407                 goto out;
 408
 409         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 410                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 411
 412         /* Write IOSF control register */
 413         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 414
 415         ret = ixgbe_iosf_wait(hw, &command);
 416
 417         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 418                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 419                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 420                 hw_dbg(hw, "Failed to read, error %x\n", error);
 421                 return IXGBE_ERR_PHY;
 422         }
 423
 424         if (!ret)
 425                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 426
 427 out:
 428         hw->mac.ops.release_swfw_sync(hw, gssr);
 429         return ret;
 430 }
 431
 432 /**
 433  * ixgbe_get_phy_token - Get the token for shared PHY access
 434  * @hw: Pointer to hardware structure
 435  */
 436 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 437 {
 438         struct ixgbe_hic_phy_token_req token_cmd;
 439         s32 status;
 440
 441         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 442         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 443         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 444         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 445         token_cmd.port_number = hw->bus.lan_id;
 446         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 447         token_cmd.pad = 0;
 448         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 449                                               IXGBE_HI_COMMAND_TIMEOUT,
 450                                               true);
 451         if (status)
 452                 return status;
 453         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 454                 return 0;
 455         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 456                 return IXGBE_ERR_FW_RESP_INVALID;
 457
 458         return IXGBE_ERR_TOKEN_RETRY;
 459 }
 460
 461 /**
 462  * ixgbe_put_phy_token - Put the token for shared PHY access
 463  * @hw: Pointer to hardware structure
 464  */
 465 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 466 {
 467         struct ixgbe_hic_phy_token_req token_cmd;
 468         s32 status;
 469
 470         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 471         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 472         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 473         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 474         token_cmd.port_number = hw->bus.lan_id;
 475         token_cmd.command_type = FW_PHY_TOKEN_REL;
 476         token_cmd.pad = 0;
 477         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 478                                               IXGBE_HI_COMMAND_TIMEOUT,
 479                                               true);
 480         if (status)
 481                 return status;
 482         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 483                 return 0;
 484         return IXGBE_ERR_FW_RESP_INVALID;
 485 }
 486
 487 /**
 488  *  ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
 489  *  @hw: pointer to hardware structure
 490  *  @reg_addr: 32 bit PHY register to write
 491  *  @device_type: 3 bit device type
 492  *  @data: Data to write to the register
 493  **/
 494 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 495                                          __always_unused u32 device_type,
 496                                          u32 data)
 497 {
 498         struct ixgbe_hic_internal_phy_req write_cmd;
 499
 500         memset(&write_cmd, 0, sizeof(write_cmd));
 501         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 502         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 503         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 504         write_cmd.port_number = hw->bus.lan_id;
 505         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 506         write_cmd.address = cpu_to_be16(reg_addr);
 507         write_cmd.write_data = cpu_to_be32(data);
 508
 509         return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
 510                                             IXGBE_HI_COMMAND_TIMEOUT, false);
 511 }
 512
 513 /**
 514  *  ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
 515  *  @hw: pointer to hardware structure
 516  *  @reg_addr: 32 bit PHY register to write
 517  *  @device_type: 3 bit device type
 518  *  @data: Pointer to read data from the register
 519  **/
 520 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 521                                         __always_unused u32 device_type,
 522                                         u32 *data)
 523 {
 524         union {
 525                 struct ixgbe_hic_internal_phy_req cmd;
 526                 struct ixgbe_hic_internal_phy_resp rsp;
 527         } hic;
 528         s32 status;
 529
 530         memset(&hic, 0, sizeof(hic));
 531         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 532         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 533         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 534         hic.cmd.port_number = hw->bus.lan_id;
 535         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
 536         hic.cmd.address = cpu_to_be16(reg_addr);
 537
 538         status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 539                                               IXGBE_HI_COMMAND_TIMEOUT, true);
 540
 541         /* Extract the register value from the response. */
 542         *data = be32_to_cpu(hic.rsp.read_data);
 543
 544         return status;
 545 }
 546
 547 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 548  *  command assuming that the semaphore is already obtained.
 549  *  @hw: pointer to hardware structure
 550  *  @offset: offset of  word in the EEPROM to read
 551  *  @data: word read from the EEPROM
 552  *
 553  *  Reads a 16 bit word from the EEPROM using the hostif.
 554  **/
 555 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 556                                           u16 *data)
 557 {
 558         s32 status;
 559         struct ixgbe_hic_read_shadow_ram buffer;
 560
 561         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 562         buffer.hdr.req.buf_lenh = 0;
 563         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 564         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 565
 566         /* convert offset from words to bytes */
 567         buffer.address = cpu_to_be32(offset * 2);
 568         /* one word */
 569         buffer.length = cpu_to_be16(sizeof(u16));
 570
 571         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 572                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 573         if (status)
 574                 return status;
 575
 576         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 577                                           FW_NVM_DATA_OFFSET);
 578
 579         return 0;
 580 }
 581
 582 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 583  *  @hw: pointer to hardware structure
 584  *  @offset: offset of  word in the EEPROM to read
 585  *  @words: number of words
 586  *  @data: word(s) read from the EEPROM
 587  *
 588  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 589  **/
 590 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 591                                             u16 offset, u16 words, u16 *data)
 592 {
 593         struct ixgbe_hic_read_shadow_ram buffer;
 594         u32 current_word = 0;
 595         u16 words_to_read;
 596         s32 status;
 597         u32 i;
 598
 599         /* Take semaphore for the entire operation. */
 600         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 601         if (status) {
 602                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 603                 return status;
 604         }
 605
 606         while (words) {
 607                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 608                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 609                 else
 610                         words_to_read = words;
 611
 612                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 613                 buffer.hdr.req.buf_lenh = 0;
 614                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 615                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 616
 617                 /* convert offset from words to bytes */
 618                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 619                 buffer.length = cpu_to_be16(words_to_read * 2);
 620                 buffer.pad2 = 0;
 621                 buffer.pad3 = 0;
 622
 623                 status = ixgbe_host_interface_command(hw, &buffer,
 624                                                       sizeof(buffer),
 625                                                       IXGBE_HI_COMMAND_TIMEOUT,
 626                                                       false);
 627                 if (status) {
 628                         hw_dbg(hw, "Host interface command failed\n");
 629                         goto out;
 630                 }
 631
 632                 for (i = 0; i < words_to_read; i++) {
 633                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 634                                   2 * i;
 635                         u32 value = IXGBE_READ_REG(hw, reg);
 636
 637                         data[current_word] = (u16)(value & 0xffff);
 638                         current_word++;
 639                         i++;
 640                         if (i < words_to_read) {
 641                                 value >>= 16;
 642                                 data[current_word] = (u16)(value & 0xffff);
 643                                 current_word++;
 644                         }
 645                 }
 646                 words -= words_to_read;
 647         }
 648
 649 out:
 650         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 651         return status;
 652 }
 653
 654 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 655  *  @hw: pointer to hardware structure
 656  *  @ptr: pointer offset in eeprom
 657  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 658  *  @csum: address of checksum to update
 659  *
 660  *  Returns error status for any failure
 661  **/
 662 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 663                                    u16 size, u16 *csum, u16 *buffer,
 664                                    u32 buffer_size)
 665 {
 666         u16 buf[256];
 667         s32 status;
 668         u16 length, bufsz, i, start;
 669         u16 *local_buffer;
 670
 671         bufsz = sizeof(buf) / sizeof(buf[0]);
 672
 673         /* Read a chunk at the pointer location */
 674         if (!buffer) {
 675                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 676                 if (status) {
 677                         hw_dbg(hw, "Failed to read EEPROM image\n");
 678                         return status;
 679                 }
 680                 local_buffer = buf;
 681         } else {
 682                 if (buffer_size < ptr)
 683                         return  IXGBE_ERR_PARAM;
 684                 local_buffer = &buffer[ptr];
 685         }
 686
 687         if (size) {
 688                 start = 0;
 689                 length = size;
 690         } else {
 691                 start = 1;
 692                 length = local_buffer[0];
 693
 694                 /* Skip pointer section if length is invalid. */
 695                 if (length == 0xFFFF || length == 0 ||
 696                     (ptr + length) >= hw->eeprom.word_size)
 697                         return 0;
 698         }
 699
 700         if (buffer && ((u32)start + (u32)length > buffer_size))
 701                 return IXGBE_ERR_PARAM;
 702
 703         for (i = start; length; i++, length--) {
 704                 if (i == bufsz && !buffer) {
 705                         ptr += bufsz;
 706                         i = 0;
 707                         if (length < bufsz)
 708                                 bufsz = length;
 709
 710                         /* Read a chunk at the pointer location */
 711                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 712                                                                   bufsz, buf);
 713                         if (status) {
 714                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 715                                 return status;
 716                         }
 717                 }
 718                 *csum += local_buffer[i];
 719         }
 720         return 0;
 721 }
 722
 723 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 724  *  @hw: pointer to hardware structure
 725  *  @buffer: pointer to buffer containing calculated checksum
 726  *  @buffer_size: size of buffer
 727  *
 728  *  Returns a negative error code on error, or the 16-bit checksum
 729  **/
 730 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 731                                     u32 buffer_size)
 732 {
 733         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 734         u16 *local_buffer;
 735         s32 status;
 736         u16 checksum = 0;
 737         u16 pointer, i, size;
 738
 739         hw->eeprom.ops.init_params(hw);
 740
 741         if (!buffer) {
 742                 /* Read pointer area */
 743                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 744                                                 IXGBE_EEPROM_LAST_WORD + 1,
 745                                                 eeprom_ptrs);
 746                 if (status) {
 747                         hw_dbg(hw, "Failed to read EEPROM image\n");
 748                         return status;
 749                 }
 750                 local_buffer = eeprom_ptrs;
 751         } else {
 752                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 753                         return IXGBE_ERR_PARAM;
 754                 local_buffer = buffer;
 755         }
 756
 757         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 758          * checksum word itself
 759          */
 760         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 761                 if (i != IXGBE_EEPROM_CHECKSUM)
 762                         checksum += local_buffer[i];
 763
 764         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 765          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 766          */
 767         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 768                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 769                         continue;
 770
 771                 pointer = local_buffer[i];
 772
 773                 /* Skip pointer section if the pointer is invalid. */
 774                 if (pointer == 0xFFFF || pointer == 0 ||
 775                     pointer >= hw->eeprom.word_size)
 776                         continue;
 777
 778                 switch (i) {
 779                 case IXGBE_PCIE_GENERAL_PTR:
 780                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 781                         break;
 782                 case IXGBE_PCIE_CONFIG0_PTR:
 783                 case IXGBE_PCIE_CONFIG1_PTR:
 784                         size = IXGBE_PCIE_CONFIG_SIZE;
 785                         break;
 786                 default:
 787                         size = 0;
 788                         break;
 789                 }
 790
 791                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 792                                                  buffer, buffer_size);
 793                 if (status)
 794                         return status;
 795         }
 796
 797         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 798
 799         return (s32)checksum;
 800 }
 801
 802 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 803  *  @hw: pointer to hardware structure
 804  *
 805  *  Returns a negative error code on error, or the 16-bit checksum
 806  **/
 807 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 808 {
 809         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 810 }
 811
 812 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 813  *  @hw: pointer to hardware structure
 814  *  @offset: offset of  word in the EEPROM to read
 815  *  @data: word read from the EEPROM
 816  *
 817  *   Reads a 16 bit word from the EEPROM using the hostif.
 818  **/
 819 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 820 {
 821         s32 status = 0;
 822
 823         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 824                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 825                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 826         } else {
 827                 status = IXGBE_ERR_SWFW_SYNC;
 828         }
 829
 830         return status;
 831 }
 832
 833 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 834  *  @hw: pointer to hardware structure
 835  *  @checksum_val: calculated checksum
 836  *
 837  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 838  *  caller does not need checksum_val, the value can be NULL.
 839  **/
 840 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 841                                                u16 *checksum_val)
 842 {
 843         s32 status;
 844         u16 checksum;
 845         u16 read_checksum = 0;
 846
 847         /* Read the first word from the EEPROM. If this times out or fails, do
 848          * not continue or we could be in for a very long wait while every
 849          * EEPROM read fails
 850          */
 851         status = hw->eeprom.ops.read(hw, 0, &checksum);
 852         if (status) {
 853                 hw_dbg(hw, "EEPROM read failed\n");
 854                 return status;
 855         }
 856
 857         status = hw->eeprom.ops.calc_checksum(hw);
 858         if (status < 0)
 859                 return status;
 860
 861         checksum = (u16)(status & 0xffff);
 862
 863         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 864                                            &read_checksum);
 865         if (status)
 866                 return status;
 867
 868         /* Verify read checksum from EEPROM is the same as
 869          * calculated checksum
 870          */
 871         if (read_checksum != checksum) {
 872                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 873                 hw_dbg(hw, "Invalid EEPROM checksum");
 874         }
 875
 876         /* If the user cares, return the calculated checksum */
 877         if (checksum_val)
 878                 *checksum_val = checksum;
 879
 880         return status;
 881 }
 882
 883 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 884  *  @hw: pointer to hardware structure
 885  *  @offset: offset of  word in the EEPROM to write
 886  *  @data: word write to the EEPROM
 887  *
 888  *  Write a 16 bit word to the EEPROM using the hostif.
 889  **/
 890 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 891                                            u16 data)
 892 {
 893         s32 status;
 894         struct ixgbe_hic_write_shadow_ram buffer;
 895
 896         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 897         buffer.hdr.req.buf_lenh = 0;
 898         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 899         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 900
 901         /* one word */
 902         buffer.length = cpu_to_be16(sizeof(u16));
 903         buffer.data = data;
 904         buffer.address = cpu_to_be32(offset * 2);
 905
 906         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 907                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 908         return status;
 909 }
 910
 911 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 912  *  @hw: pointer to hardware structure
 913  *  @offset: offset of  word in the EEPROM to write
 914  *  @data: word write to the EEPROM
 915  *
 916  *  Write a 16 bit word to the EEPROM using the hostif.
 917  **/
 918 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 919 {
 920         s32 status = 0;
 921
 922         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 923                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 924                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 925         } else {
 926                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 927                 status = IXGBE_ERR_SWFW_SYNC;
 928         }
 929
 930         return status;
 931 }
 932
 933 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 934  *  @hw: pointer to hardware structure
 935  *
 936  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 937  **/
 938 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 939 {
 940         s32 status = 0;
 941         union ixgbe_hic_hdr2 buffer;
 942
 943         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 944         buffer.req.buf_lenh = 0;
 945         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 946         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 947
 948         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 949                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 950         return status;
 951 }
 952
 953 /**
 954  * ixgbe_get_bus_info_X550em - Set PCI bus info
 955  * @hw: pointer to hardware structure
 956  *
 957  * Sets bus link width and speed to unknown because X550em is
 958  * not a PCI device.
 959  **/
 960 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 961 {
 962         hw->bus.type  = ixgbe_bus_type_internal;
 963         hw->bus.width = ixgbe_bus_width_unknown;
 964         hw->bus.speed = ixgbe_bus_speed_unknown;
 965
 966         hw->mac.ops.set_lan_id(hw);
 967
 968         return 0;
 969 }
 970
 971 /** ixgbe_disable_rx_x550 - Disable RX unit
 972  *
 973  *  Enables the Rx DMA unit for x550
 974  **/
 975 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 976 {
 977         u32 rxctrl, pfdtxgswc;
 978         s32 status;
 979         struct ixgbe_hic_disable_rxen fw_cmd;
 980
 981         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 982         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 983                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 984                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 985                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 986                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 987                         hw->mac.set_lben = true;
 988                 } else {
 989                         hw->mac.set_lben = false;
 990                 }
 991
 992                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 993                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 994                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 995                 fw_cmd.port_number = hw->bus.lan_id;
 996
 997                 status = ixgbe_host_interface_command(hw, &fw_cmd,
 998                                         sizeof(struct ixgbe_hic_disable_rxen),
 999                                         IXGBE_HI_COMMAND_TIMEOUT, true);
1000
1001                 /* If we fail - disable RX using register write */
1002                 if (status) {
1003                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1004                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1005                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1006                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1007                         }
1008                 }
1009         }
1010 }
1011
1012 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1013  *  @hw: pointer to hardware structure
1014  *
1015  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
1016  *  checksum and updates the EEPROM and instructs the hardware to update
1017  *  the flash.
1018  **/
1019 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1020 {
1021         s32 status;
1022         u16 checksum = 0;
1023
1024         /* Read the first word from the EEPROM. If this times out or fails, do
1025          * not continue or we could be in for a very long wait while every
1026          * EEPROM read fails
1027          */
1028         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1029         if (status) {
1030                 hw_dbg(hw, "EEPROM read failed\n");
1031                 return status;
1032         }
1033
1034         status = ixgbe_calc_eeprom_checksum_X550(hw);
1035         if (status < 0)
1036                 return status;
1037
1038         checksum = (u16)(status & 0xffff);
1039
1040         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1041                                             checksum);
1042         if (status)
1043                 return status;
1044
1045         status = ixgbe_update_flash_X550(hw);
1046
1047         return status;
1048 }
1049
1050 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1051  *  @hw: pointer to hardware structure
1052  *  @offset: offset of  word in the EEPROM to write
1053  *  @words: number of words
1054  *  @data: word(s) write to the EEPROM
1055  *
1056  *
1057  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1058  **/
1059 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1060                                              u16 offset, u16 words,
1061                                              u16 *data)
1062 {
1063         s32 status = 0;
1064         u32 i = 0;
1065
1066         /* Take semaphore for the entire operation. */
1067         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1068         if (status) {
1069                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1070                 return status;
1071         }
1072
1073         for (i = 0; i < words; i++) {
1074                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1075                                                          data[i]);
1076                 if (status) {
1077                         hw_dbg(hw, "Eeprom buffered write failed\n");
1078                         break;
1079                 }
1080         }
1081
1082         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1083
1084         return status;
1085 }
1086
1087 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1088  *  IOSF device
1089  *
1090  *  @hw: pointer to hardware structure
1091  *  @reg_addr: 32 bit PHY register to write
1092  *  @device_type: 3 bit device type
1093  *  @data: Data to write to the register
1094  **/
1095 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1096                                         u32 device_type, u32 data)
1097 {
1098         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1099         u32 command, error;
1100         s32 ret;
1101
1102         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1103         if (ret)
1104                 return ret;
1105
1106         ret = ixgbe_iosf_wait(hw, NULL);
1107         if (ret)
1108                 goto out;
1109
1110         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1111                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1112
1113         /* Write IOSF control register */
1114         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1115
1116         /* Write IOSF data register */
1117         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1118
1119         ret = ixgbe_iosf_wait(hw, &command);
1120
1121         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1122                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1123                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1124                 hw_dbg(hw, "Failed to write, error %x\n", error);
1125                 return IXGBE_ERR_PHY;
1126         }
1127
1128 out:
1129         hw->mac.ops.release_swfw_sync(hw, gssr);
1130         return ret;
1131 }
1132
1133 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1134  *  @hw: pointer to hardware structure
1135  *  @speed: the link speed to force
1136  *
1137  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1138  *  internal and external PHY at a specific speed, without autonegotiation.
1139  **/
1140 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1141 {
1142         s32 status;
1143         u32 reg_val;
1144
1145         /* Disable AN and force speed to 10G Serial. */
1146         status = ixgbe_read_iosf_sb_reg_x550(hw,
1147                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1148                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1149         if (status)
1150                 return status;
1151
1152         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1153         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1154
1155         /* Select forced link speed for internal PHY. */
1156         switch (*speed) {
1157         case IXGBE_LINK_SPEED_10GB_FULL:
1158                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1159                 break;
1160         case IXGBE_LINK_SPEED_1GB_FULL:
1161                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1162                 break;
1163         default:
1164                 /* Other link speeds are not supported by internal KR PHY. */
1165                 return IXGBE_ERR_LINK_SETUP;
1166         }
1167
1168         status = ixgbe_write_iosf_sb_reg_x550(hw,
1169                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1170                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1171         if (status)
1172                 return status;
1173
1174         /* Disable training protocol FSM. */
1175         status = ixgbe_read_iosf_sb_reg_x550(hw,
1176                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1177                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1178         if (status)
1179                 return status;
1180
1181         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1182         status = ixgbe_write_iosf_sb_reg_x550(hw,
1183                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1184                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1185         if (status)
1186                 return status;
1187
1188         /* Disable Flex from training TXFFE. */
1189         status = ixgbe_read_iosf_sb_reg_x550(hw,
1190                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1191                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1192         if (status)
1193                 return status;
1194
1195         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1196         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1197         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1198         status = ixgbe_write_iosf_sb_reg_x550(hw,
1199                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1200                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1201         if (status)
1202                 return status;
1203
1204         status = ixgbe_read_iosf_sb_reg_x550(hw,
1205                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1206                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1207         if (status)
1208                 return status;
1209
1210         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1211         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1212         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1213         status = ixgbe_write_iosf_sb_reg_x550(hw,
1214                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1215                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1216         if (status)
1217                 return status;
1218
1219         /* Enable override for coefficients. */
1220         status = ixgbe_read_iosf_sb_reg_x550(hw,
1221                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1222                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1223         if (status)
1224                 return status;
1225
1226         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1227         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1228         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1229         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1230         status = ixgbe_write_iosf_sb_reg_x550(hw,
1231                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1232                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1233         if (status)
1234                 return status;
1235
1236         /* Toggle port SW reset by AN reset. */
1237         status = ixgbe_read_iosf_sb_reg_x550(hw,
1238                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1239                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1240         if (status)
1241                 return status;
1242
1243         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1244         status = ixgbe_write_iosf_sb_reg_x550(hw,
1245                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1246                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1247
1248         return status;
1249 }
1250
1251 /**
1252  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1253  *  @hw: pointer to hardware structure
1254  *  @linear: true if SFP module is linear
1255  */
1256 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1257 {
1258         switch (hw->phy.sfp_type) {
1259         case ixgbe_sfp_type_not_present:
1260                 return IXGBE_ERR_SFP_NOT_PRESENT;
1261         case ixgbe_sfp_type_da_cu_core0:
1262         case ixgbe_sfp_type_da_cu_core1:
1263                 *linear = true;
1264                 break;
1265         case ixgbe_sfp_type_srlr_core0:
1266         case ixgbe_sfp_type_srlr_core1:
1267         case ixgbe_sfp_type_da_act_lmt_core0:
1268         case ixgbe_sfp_type_da_act_lmt_core1:
1269         case ixgbe_sfp_type_1g_sx_core0:
1270         case ixgbe_sfp_type_1g_sx_core1:
1271         case ixgbe_sfp_type_1g_lx_core0:
1272         case ixgbe_sfp_type_1g_lx_core1:
1273                 *linear = false;
1274                 break;
1275         case ixgbe_sfp_type_unknown:
1276         case ixgbe_sfp_type_1g_cu_core0:
1277         case ixgbe_sfp_type_1g_cu_core1:
1278         default:
1279                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1280         }
1281
1282         return 0;
1283 }
1284
1285 /**
1286  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1287  *  @hw: pointer to hardware structure
1288  *
1289  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1290  */
1291 static s32
1292 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1293                                 ixgbe_link_speed speed,
1294                                 __always_unused bool autoneg_wait_to_complete)
1295 {
1296         s32 status;
1297         u16 slice, value;
1298         bool setup_linear = false;
1299
1300         /* Check if SFP module is supported and linear */
1301         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1302
1303         /* If no SFP module present, then return success. Return success since
1304          * there is no reason to configure CS4227 and SFP not present error is
1305          * not accepted in the setup MAC link flow.
1306          */
1307         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1308                 return 0;
1309
1310         if (status)
1311                 return status;
1312
1313         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1314                 /* Configure CS4227 LINE side to 10G SR. */
1315                 slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1316                 value = IXGBE_CS4227_SPEED_10G;
1317                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1318                                                           slice, value);
1319                 if (status)
1320                         goto i2c_err;
1321
1322                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1323                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1324                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1325                                                           slice, value);
1326                 if (status)
1327                         goto i2c_err;
1328
1329                 /* Configure CS4227 for HOST connection rate then type. */
1330                 slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1331                 value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1332                         IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1333                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1334                                                           slice, value);
1335                 if (status)
1336                         goto i2c_err;
1337
1338                 slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1339                 if (setup_linear)
1340                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1341                 else
1342                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1343                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1344                                                           slice, value);
1345                 if (status)
1346                         goto i2c_err;
1347
1348                 /* Setup XFI internal link. */
1349                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1350                 if (status) {
1351                         hw_dbg(hw, "setup_ixfi failed with %d\n", status);
1352                         return status;
1353                 }
1354         } else {
1355                 /* Configure internal PHY for KR/KX. */
1356                 status = ixgbe_setup_kr_speed_x550em(hw, speed);
1357                 if (status) {
1358                         hw_dbg(hw, "setup_kr_speed failed with %d\n", status);
1359                         return status;
1360                 }
1361
1362                 /* Configure CS4227 LINE side to proper mode. */
1363                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1364                 if (setup_linear)
1365                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1366                 else
1367                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1368                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1369                                                           slice, value);
1370                 if (status)
1371                         goto i2c_err;
1372         }
1373
1374         return 0;
1375
1376 i2c_err:
1377         hw_dbg(hw, "combined i2c access failed with %d\n", status);
1378         return status;
1379 }
1380
1381 /**
1382  * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1383  * @hw: pointer to hardware structure
1384  *
1385  * Configure the the integrated PHY for native SFP support.
1386  */
1387 static s32
1388 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1389                            __always_unused bool autoneg_wait_to_complete)
1390 {
1391         bool setup_linear = false;
1392         u32 reg_phy_int;
1393         s32 rc;
1394
1395         /* Check if SFP module is supported and linear */
1396         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1397
1398         /* If no SFP module present, then return success. Return success since
1399          * SFP not present error is not excepted in the setup MAC link flow.
1400          */
1401         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1402                 return 0;
1403
1404         if (!rc)
1405                 return rc;
1406
1407         /* Configure internal PHY for native SFI */
1408         rc = hw->mac.ops.read_iosf_sb_reg(hw,
1409                                           IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1410                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
1411                                           &reg_phy_int);
1412         if (rc)
1413                 return rc;
1414
1415         if (setup_linear) {
1416                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
1417                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
1418         } else {
1419                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
1420                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
1421         }
1422
1423         rc = hw->mac.ops.write_iosf_sb_reg(hw,
1424                                            IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1425                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
1426                                            reg_phy_int);
1427         if (rc)
1428                 return rc;
1429
1430         /* Setup XFI/SFI internal link */
1431         return ixgbe_setup_ixfi_x550em(hw, &speed);
1432 }
1433
1434 /**
1435  * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1436  * @hw: pointer to hardware structure
1437  *
1438  * Configure the the integrated PHY for SFP support.
1439  */
1440 static s32
1441 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1442                                __always_unused bool autoneg_wait_to_complete)
1443 {
1444         u32 reg_slice, slice_offset;
1445         bool setup_linear = false;
1446         u16 reg_phy_ext;
1447         s32 rc;
1448
1449         /* Check if SFP module is supported and linear */
1450         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1451
1452         /* If no SFP module present, then return success. Return success since
1453          * SFP not present error is not excepted in the setup MAC link flow.
1454          */
1455         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1456                 return 0;
1457
1458         if (!rc)
1459                 return rc;
1460
1461         /* Configure internal PHY for KR/KX. */
1462         ixgbe_setup_kr_speed_x550em(hw, speed);
1463
1464         if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1465                 return IXGBE_ERR_PHY_ADDR_INVALID;
1466
1467         /* Get external PHY device id */
1468         rc = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
1469                                   IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1470         if (rc)
1471                 return rc;
1472
1473         /* When configuring quad port CS4223, the MAC instance is part
1474          * of the slice offset.
1475          */
1476         if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
1477                 slice_offset = (hw->bus.lan_id +
1478                                 (hw->bus.instance_id << 1)) << 12;
1479         else
1480                 slice_offset = hw->bus.lan_id << 12;
1481
1482         /* Configure CS4227/CS4223 LINE side to proper mode. */
1483         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1484         if (setup_linear)
1485                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1486         else
1487                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1488         return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE,
1489                                      reg_phy_ext);
1490 }
1491
1492 /**
1493  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1494  * @hw: pointer to hardware structure
1495  * @speed: new link speed
1496  * @autoneg_wait_to_complete: true when waiting for completion is needed
1497  *
1498  * Setup internal/external PHY link speed based on link speed, then set
1499  * external PHY auto advertised link speed.
1500  *
1501  * Returns error status for any failure
1502  **/
1503 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1504                                          ixgbe_link_speed speed,
1505                                          bool autoneg_wait)
1506 {
1507         s32 status;
1508         ixgbe_link_speed force_speed;
1509
1510         /* Setup internal/external PHY link speed to iXFI (10G), unless
1511          * only 1G is auto advertised then setup KX link.
1512          */
1513         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1514                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1515         else
1516                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1517
1518         /* If internal link mode is XFI, then setup XFI internal link. */
1519         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1520                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1521
1522                 if (status)
1523                         return status;
1524         }
1525
1526         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1527 }
1528
1529 /** ixgbe_check_link_t_X550em - Determine link and speed status
1530   * @hw: pointer to hardware structure
1531   * @speed: pointer to link speed
1532   * @link_up: true when link is up
1533   * @link_up_wait_to_complete: bool used to wait for link up or not
1534   *
1535   * Check that both the MAC and X557 external PHY have link.
1536   **/
1537 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1538                                      ixgbe_link_speed *speed,
1539                                      bool *link_up,
1540                                      bool link_up_wait_to_complete)
1541 {
1542         u32 status;
1543         u16 autoneg_status;
1544
1545         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1546                 return IXGBE_ERR_CONFIG;
1547
1548         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1549                                               link_up_wait_to_complete);
1550
1551         /* If check link fails or MAC link is not up, then return */
1552         if (status || !(*link_up))
1553                 return status;
1554
1555          /* MAC link is up, so check external PHY link.
1556           * Read this twice back to back to indicate current status.
1557           */
1558         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1559                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1560                                       &autoneg_status);
1561         if (status)
1562                 return status;
1563
1564         /* If external PHY link is not up, then indicate link not up */
1565         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1566                 *link_up = false;
1567
1568         return 0;
1569 }
1570
1571 /**
1572  * ixgbe_setup_sgmii - Set up link for sgmii
1573  * @hw: pointer to hardware structure
1574  */
1575 static s32
1576 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1577                   __always_unused bool autoneg_wait_to_complete)
1578 {
1579         struct ixgbe_mac_info *mac = &hw->mac;
1580         u32 lval, sval;
1581         s32 rc;
1582
1583         rc = mac->ops.read_iosf_sb_reg(hw,
1584                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1585                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1586         if (rc)
1587                 return rc;
1588
1589         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1590         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1591         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1592         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1593         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1594         rc = mac->ops.write_iosf_sb_reg(hw,
1595                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1596                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1597         if (rc)
1598                 return rc;
1599
1600         rc = mac->ops.read_iosf_sb_reg(hw,
1601                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1602                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1603         if (rc)
1604                 return rc;
1605
1606         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1607         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1608         rc = mac->ops.write_iosf_sb_reg(hw,
1609                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1610                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1611         if (rc)
1612                 return rc;
1613
1614         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1615         rc = mac->ops.write_iosf_sb_reg(hw,
1616                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1617                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1618
1619         return rc;
1620 }
1621
1622 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1623  *  @hw: pointer to hardware structure
1624  **/
1625 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1626 {
1627         struct ixgbe_mac_info *mac = &hw->mac;
1628
1629         mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1630
1631         switch (mac->ops.get_media_type(hw)) {
1632         case ixgbe_media_type_fiber:
1633                 /* CS4227 does not support autoneg, so disable the laser control
1634                  * functions for SFP+ fiber
1635                  */
1636                 mac->ops.disable_tx_laser = NULL;
1637                 mac->ops.enable_tx_laser = NULL;
1638                 mac->ops.flap_tx_laser = NULL;
1639                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1640                 switch (hw->device_id) {
1641                 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1642                         mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
1643                         break;
1644                 case IXGBE_DEV_ID_X550EM_A_SFP:
1645                         mac->ops.setup_mac_link =
1646                                                 ixgbe_setup_mac_link_sfp_x550a;
1647                         break;
1648                 default:
1649                         mac->ops.setup_mac_link =
1650                                                 ixgbe_setup_mac_link_sfp_x550em;
1651                         break;
1652                 }
1653                 mac->ops.set_rate_select_speed =
1654                                         ixgbe_set_soft_rate_select_speed;
1655                 break;
1656         case ixgbe_media_type_copper:
1657                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1658                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
1659                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1660                 return;
1661         case ixgbe_media_type_backplane:
1662                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1663                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1664                         mac->ops.setup_link = ixgbe_setup_sgmii;
1665                 break;
1666         default:
1667                 break;
1668         }
1669 }
1670
1671 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1672  * @hw: pointer to hardware structure
1673  */
1674 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1675 {
1676         s32 status;
1677         bool linear;
1678
1679         /* Check if SFP module is supported */
1680         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1681         if (status)
1682                 return status;
1683
1684         ixgbe_init_mac_link_ops_X550em(hw);
1685         hw->phy.ops.reset = NULL;
1686
1687         return 0;
1688 }
1689
1690 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1691  * @hw: pointer to hardware structure
1692  * @speed: pointer to link speed
1693  * @autoneg: true when autoneg or autotry is enabled
1694  **/
1695 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1696                                               ixgbe_link_speed *speed,
1697                                               bool *autoneg)
1698 {
1699         /* SFP */
1700         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1701                 /* CS4227 SFP must not enable auto-negotiation */
1702                 *autoneg = false;
1703
1704                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1705                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1706                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1707                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1708                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1709                         return 0;
1710                 }
1711
1712                 /* Link capabilities are based on SFP */
1713                 if (hw->phy.multispeed_fiber)
1714                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1715                                  IXGBE_LINK_SPEED_1GB_FULL;
1716                 else
1717                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1718         } else {
1719                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1720                          IXGBE_LINK_SPEED_1GB_FULL;
1721                 *autoneg = true;
1722         }
1723         return 0;
1724 }
1725
1726 /**
1727  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1728  * @hw: pointer to hardware structure
1729  * @lsc: pointer to boolean flag which indicates whether external Base T
1730  *       PHY interrupt is lsc
1731  *
1732  * Determime if external Base T PHY interrupt cause is high temperature
1733  * failure alarm or link status change.
1734  *
1735  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1736  * failure alarm, else return PHY access status.
1737  **/
1738 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1739 {
1740         u32 status;
1741         u16 reg;
1742
1743         *lsc = false;
1744
1745         /* Vendor alarm triggered */
1746         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1747                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1748                                       &reg);
1749
1750         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1751                 return status;
1752
1753         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1754         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1755                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1756                                       &reg);
1757
1758         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1759                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1760                 return status;
1761
1762         /* Global alarm triggered */
1763         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1764                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1765                                       &reg);
1766
1767         if (status)
1768                 return status;
1769
1770         /* If high temperature failure, then return over temp error and exit */
1771         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1772                 /* power down the PHY in case the PHY FW didn't already */
1773                 ixgbe_set_copper_phy_power(hw, false);
1774                 return IXGBE_ERR_OVERTEMP;
1775         }
1776         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1777                 /*  device fault alarm triggered */
1778                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1779                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1780                                           &reg);
1781                 if (status)
1782                         return status;
1783
1784                 /* if device fault was due to high temp alarm handle and exit */
1785                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1786                         /* power down the PHY in case the PHY FW didn't */
1787                         ixgbe_set_copper_phy_power(hw, false);
1788                         return IXGBE_ERR_OVERTEMP;
1789                 }
1790         }
1791
1792         /* Vendor alarm 2 triggered */
1793         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1794                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1795
1796         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1797                 return status;
1798
1799         /* link connect/disconnect event occurred */
1800         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1801                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1802
1803         if (status)
1804                 return status;
1805
1806         /* Indicate LSC */
1807         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1808                 *lsc = true;
1809
1810         return 0;
1811 }
1812
1813 /**
1814  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1815  * @hw: pointer to hardware structure
1816  *
1817  * Enable link status change and temperature failure alarm for the external
1818  * Base T PHY
1819  *
1820  * Returns PHY access status
1821  **/
1822 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1823 {
1824         u32 status;
1825         u16 reg;
1826         bool lsc;
1827
1828         /* Clear interrupt flags */
1829         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1830
1831         /* Enable link status change alarm */
1832         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1833                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1834         if (status)
1835                 return status;
1836
1837         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1838
1839         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1840                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1841         if (status)
1842                 return status;
1843
1844         /* Enable high temperature failure and global fault alarms */
1845         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1846                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1847                                       &reg);
1848         if (status)
1849                 return status;
1850
1851         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1852                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1853
1854         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1855                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1856                                        reg);
1857         if (status)
1858                 return status;
1859
1860         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1861         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1862                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1863                                       &reg);
1864         if (status)
1865                 return status;
1866
1867         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1868                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1869
1870         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1871                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1872                                        reg);
1873         if (status)
1874                 return status;
1875
1876         /* Enable chip-wide vendor alarm */
1877         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1878                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1879                                       &reg);
1880         if (status)
1881                 return status;
1882
1883         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1884
1885         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1886                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1887                                        reg);
1888
1889         return status;
1890 }
1891
1892 /**
1893  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1894  * @hw: pointer to hardware structure
1895  *
1896  * Handle external Base T PHY interrupt. If high temperature
1897  * failure alarm then return error, else if link status change
1898  * then setup internal/external PHY link
1899  *
1900  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1901  * failure alarm, else return PHY access status.
1902  **/
1903 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1904 {
1905         struct ixgbe_phy_info *phy = &hw->phy;
1906         bool lsc;
1907         u32 status;
1908
1909         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1910         if (status)
1911                 return status;
1912
1913         if (lsc && phy->ops.setup_internal_link)
1914                 return phy->ops.setup_internal_link(hw);
1915
1916         return 0;
1917 }
1918
1919 /**
1920  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1921  * @hw: pointer to hardware structure
1922  * @speed: link speed
1923  *
1924  * Configures the integrated KR PHY.
1925  **/
1926 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1927                                        ixgbe_link_speed speed)
1928 {
1929         s32 status;
1930         u32 reg_val;
1931
1932         status = hw->mac.ops.read_iosf_sb_reg(hw,
1933                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1934                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1935         if (status)
1936                 return status;
1937
1938         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1939         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1940                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1941
1942         /* Advertise 10G support. */
1943         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1944                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1945
1946         /* Advertise 1G support. */
1947         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1948                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1949
1950         /* Restart auto-negotiation. */
1951         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1952         status = hw->mac.ops.write_iosf_sb_reg(hw,
1953                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1954                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1955
1956         return status;
1957 }
1958
1959 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1960  *  @hw: pointer to hardware structure
1961  *
1962  *   Configures the integrated KX4 PHY.
1963  **/
1964 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1965 {
1966         s32 status;
1967         u32 reg_val;
1968
1969         status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1970                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1971                                               hw->bus.lan_id, &reg_val);
1972         if (status)
1973                 return status;
1974
1975         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1976                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1977
1978         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1979
1980         /* Advertise 10G support. */
1981         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1982                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1983
1984         /* Advertise 1G support. */
1985         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1986                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1987
1988         /* Restart auto-negotiation. */
1989         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1990         status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1991                                                IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1992                                                hw->bus.lan_id, reg_val);
1993
1994         return status;
1995 }
1996
1997 /**
1998  * ixgbe_setup_kr_x550em - Configure the KR PHY
1999  * @hw: pointer to hardware structure
2000  **/
2001 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2002 {
2003         /* leave link alone for 2.5G */
2004         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2005                 return 0;
2006
2007         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2008 }
2009
2010 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2011  *  @hw: address of hardware structure
2012  *  @link_up: address of boolean to indicate link status
2013  *
2014  *  Returns error code if unable to get link status.
2015  **/
2016 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2017 {
2018         u32 ret;
2019         u16 autoneg_status;
2020
2021         *link_up = false;
2022
2023         /* read this twice back to back to indicate current status */
2024         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2025                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2026                                    &autoneg_status);
2027         if (ret)
2028                 return ret;
2029
2030         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2031                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2032                                    &autoneg_status);
2033         if (ret)
2034                 return ret;
2035
2036         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2037
2038         return 0;
2039 }
2040
2041 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2042  *  @hw: point to hardware structure
2043  *
2044  *  Configures the link between the integrated KR PHY and the external X557 PHY
2045  *  The driver will call this function when it gets a link status change
2046  *  interrupt from the X557 PHY. This function configures the link speed
2047  *  between the PHYs to match the link speed of the BASE-T link.
2048  *
2049  * A return of a non-zero value indicates an error, and the base driver should
2050  * not report link up.
2051  **/
2052 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2053 {
2054         ixgbe_link_speed force_speed;
2055         bool link_up;
2056         u32 status;
2057         u16 speed;
2058
2059         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2060                 return IXGBE_ERR_CONFIG;
2061
2062         if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
2063                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2064                         IXGBE_LINK_SPEED_1GB_FULL;
2065                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2066         }
2067
2068         /* If link is not up, then there is no setup necessary so return  */
2069         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2070         if (status)
2071                 return status;
2072
2073         if (!link_up)
2074                 return 0;
2075
2076         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2077                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2078                                       &speed);
2079         if (status)
2080                 return status;
2081
2082         /* If link is not still up, then no setup is necessary so return */
2083         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2084         if (status)
2085                 return status;
2086
2087         if (!link_up)
2088                 return 0;
2089
2090         /* clear everything but the speed and duplex bits */
2091         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2092
2093         switch (speed) {
2094         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2095                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2096                 break;
2097         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2098                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2099                 break;
2100         default:
2101                 /* Internal PHY does not support anything else */
2102                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2103         }
2104
2105         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2106 }
2107
2108 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2109  *  @hw: pointer to hardware structure
2110  **/
2111 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2112 {
2113         s32 status;
2114
2115         status = ixgbe_reset_phy_generic(hw);
2116
2117         if (status)
2118                 return status;
2119
2120         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2121         return ixgbe_enable_lasi_ext_t_x550em(hw);
2122 }
2123
2124 /**
2125  *  ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2126  *  @hw: pointer to hardware structure
2127  *  @led_idx: led number to turn on
2128  **/
2129 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2130 {
2131         u16 phy_data;
2132
2133         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2134                 return IXGBE_ERR_PARAM;
2135
2136         /* To turn on the LED, set mode to ON. */
2137         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2138                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
2139         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2140         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2141                               IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
2142
2143         return 0;
2144 }
2145
2146 /**
2147  *  ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2148  *  @hw: pointer to hardware structure
2149  *  @led_idx: led number to turn off
2150  **/
2151 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2152 {
2153         u16 phy_data;
2154
2155         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2156                 return IXGBE_ERR_PARAM;
2157
2158         /* To turn on the LED, set mode to ON. */
2159         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2160                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
2161         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2162         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2163                               IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
2164
2165         return 0;
2166 }
2167
2168 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2169  *  @hw: pointer to hardware structure
2170  *  @lcd_speed: pointer to lowest common link speed
2171  *
2172  *  Determine lowest common link speed with link partner.
2173  **/
2174 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2175                                   ixgbe_link_speed *lcd_speed)
2176 {
2177         u16 an_lp_status;
2178         s32 status;
2179         u16 word = hw->eeprom.ctrl_word_3;
2180
2181         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2182
2183         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2184                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2185                                       &an_lp_status);
2186         if (status)
2187                 return status;
2188
2189         /* If link partner advertised 1G, return 1G */
2190         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2191                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2192                 return status;
2193         }
2194
2195         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2196         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2197             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2198                 return status;
2199
2200         /* Link partner not capable of lower speeds, return 10G */
2201         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2202         return status;
2203 }
2204
2205 /**
2206  * ixgbe_setup_fc_x550em - Set up flow control
2207  * @hw: pointer to hardware structure
2208  */
2209 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2210 {
2211         bool pause, asm_dir;
2212         u32 reg_val;
2213         s32 rc;
2214
2215         /* Validate the requested mode */
2216         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2217                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2218                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2219         }
2220
2221         /* 10gig parts do not have a word in the EEPROM to determine the
2222          * default flow control setting, so we explicitly set it to full.
2223          */
2224         if (hw->fc.requested_mode == ixgbe_fc_default)
2225                 hw->fc.requested_mode = ixgbe_fc_full;
2226
2227         /* Determine PAUSE and ASM_DIR bits. */
2228         switch (hw->fc.requested_mode) {
2229         case ixgbe_fc_none:
2230                 pause = false;
2231                 asm_dir = false;
2232                 break;
2233         case ixgbe_fc_tx_pause:
2234                 pause = false;
2235                 asm_dir = true;
2236                 break;
2237         case ixgbe_fc_rx_pause:
2238                 /* Rx Flow control is enabled and Tx Flow control is
2239                  * disabled by software override. Since there really
2240                  * isn't a way to advertise that we are capable of RX
2241                  * Pause ONLY, we will advertise that we support both
2242                  * symmetric and asymmetric Rx PAUSE, as such we fall
2243                  * through to the fc_full statement.  Later, we will
2244                  * disable the adapter's ability to send PAUSE frames.
2245                  */
2246                 /* Fallthrough */
2247         case ixgbe_fc_full:
2248                 pause = true;
2249                 asm_dir = true;
2250                 break;
2251         default:
2252                 hw_err(hw, "Flow control param set incorrectly\n");
2253                 return IXGBE_ERR_CONFIG;
2254         }
2255
2256         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR &&
2257             hw->device_id != IXGBE_DEV_ID_X550EM_A_KR &&
2258             hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L)
2259                 return 0;
2260
2261         rc = hw->mac.ops.read_iosf_sb_reg(hw,
2262                                           IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2263                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
2264                                           &reg_val);
2265         if (rc)
2266                 return rc;
2267
2268         reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2269                      IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2270         if (pause)
2271                 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2272         if (asm_dir)
2273                 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2274         rc = hw->mac.ops.write_iosf_sb_reg(hw,
2275                                            IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2276                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
2277                                            reg_val);
2278
2279         /* This device does not fully support AN. */
2280         hw->fc.disable_fc_autoneg = true;
2281
2282         return rc;
2283 }
2284
2285 /** ixgbe_enter_lplu_x550em - Transition to low power states
2286  *  @hw: pointer to hardware structure
2287  *
2288  *  Configures Low Power Link Up on transition to low power states
2289  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
2290  *  the X557 PHY immediately prior to entering LPLU.
2291  **/
2292 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2293 {
2294         u16 an_10g_cntl_reg, autoneg_reg, speed;
2295         s32 status;
2296         ixgbe_link_speed lcd_speed;
2297         u32 save_autoneg;
2298         bool link_up;
2299
2300         /* If blocked by MNG FW, then don't restart AN */
2301         if (ixgbe_check_reset_blocked(hw))
2302                 return 0;
2303
2304         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2305         if (status)
2306                 return status;
2307
2308         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
2309                                      &hw->eeprom.ctrl_word_3);
2310         if (status)
2311                 return status;
2312
2313         /* If link is down, LPLU disabled in NVM, WoL disabled, or
2314          * manageability disabled, then force link down by entering
2315          * low power mode.
2316          */
2317         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2318             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2319                 return ixgbe_set_copper_phy_power(hw, false);
2320
2321         /* Determine LCD */
2322         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2323         if (status)
2324                 return status;
2325
2326         /* If no valid LCD link speed, then force link down and exit. */
2327         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2328                 return ixgbe_set_copper_phy_power(hw, false);
2329
2330         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2331                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2332                                       &speed);
2333         if (status)
2334                 return status;
2335
2336         /* If no link now, speed is invalid so take link down */
2337         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2338         if (status)
2339                 return ixgbe_set_copper_phy_power(hw, false);
2340
2341         /* clear everything but the speed bits */
2342         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2343
2344         /* If current speed is already LCD, then exit. */
2345         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2346              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2347             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2348              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2349                 return status;
2350
2351         /* Clear AN completed indication */
2352         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2353                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2354                                       &autoneg_reg);
2355         if (status)
2356                 return status;
2357
2358         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2359                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2360                                       &an_10g_cntl_reg);
2361         if (status)
2362                 return status;
2363
2364         status = hw->phy.ops.read_reg(hw,
2365                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2366                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2367                                       &autoneg_reg);
2368         if (status)
2369                 return status;
2370
2371         save_autoneg = hw->phy.autoneg_advertised;
2372
2373         /* Setup link at least common link speed */
2374         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2375
2376         /* restore autoneg from before setting lplu speed */
2377         hw->phy.autoneg_advertised = save_autoneg;
2378
2379         return status;
2380 }
2381
2382 /**
2383  * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2384  * @hw: pointer to hardware structure
2385  *
2386  * Read NW_MNG_IF_SEL register and save field values.
2387  */
2388 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2389 {
2390         /* Save NW management interface connected on board. This is used
2391          * to determine internal PHY mode.
2392          */
2393         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2394
2395         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2396          * PHY address. This register field was has only been used for X552.
2397          */
2398         if (hw->mac.type == ixgbe_mac_x550em_a &&
2399             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2400                 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
2401                                       IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2402                                      IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2403         }
2404 }
2405
2406 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2407  *  @hw: pointer to hardware structure
2408  *
2409  *  Initialize any function pointers that were not able to be
2410  *  set during init_shared_code because the PHY/SFP type was
2411  *  not known.  Perform the SFP init if necessary.
2412  **/
2413 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2414 {
2415         struct ixgbe_phy_info *phy = &hw->phy;
2416         s32 ret_val;
2417
2418         hw->mac.ops.set_lan_id(hw);
2419
2420         ixgbe_read_mng_if_sel_x550em(hw);
2421
2422         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2423                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2424                 ixgbe_setup_mux_ctl(hw);
2425         }
2426
2427         /* Identify the PHY or SFP module */
2428         ret_val = phy->ops.identify(hw);
2429
2430         /* Setup function pointers based on detected hardware */
2431         ixgbe_init_mac_link_ops_X550em(hw);
2432         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2433                 phy->ops.reset = NULL;
2434
2435         /* Set functions pointers based on phy type */
2436         switch (hw->phy.type) {
2437         case ixgbe_phy_x550em_kx4:
2438                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2439                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2440                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2441                 break;
2442         case ixgbe_phy_x550em_kr:
2443                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2444                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2445                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2446                 break;
2447         case ixgbe_phy_x550em_ext_t:
2448                 /* Save NW management interface connected on board. This is used
2449                  * to determine internal PHY mode
2450                  */
2451                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2452
2453                 /* If internal link mode is XFI, then setup iXFI internal link,
2454                  * else setup KR now.
2455                  */
2456                 phy->ops.setup_internal_link =
2457                                               ixgbe_setup_internal_phy_t_x550em;
2458
2459                 /* setup SW LPLU only for first revision */
2460                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
2461                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
2462                       IXGBE_FUSES0_REV_MASK))
2463                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2464
2465                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2466                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2467                 break;
2468         default:
2469                 break;
2470         }
2471
2472         return ret_val;
2473 }
2474
2475 /** ixgbe_get_media_type_X550em - Get media type
2476  *  @hw: pointer to hardware structure
2477  *
2478  *  Returns the media type (fiber, copper, backplane)
2479  *
2480  */
2481 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2482 {
2483         enum ixgbe_media_type media_type;
2484
2485         /* Detect if there is a copper PHY attached. */
2486         switch (hw->device_id) {
2487         case IXGBE_DEV_ID_X550EM_A_SGMII:
2488         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2489                 hw->phy.type = ixgbe_phy_sgmii;
2490                 /* Fallthrough */
2491         case IXGBE_DEV_ID_X550EM_X_KR:
2492         case IXGBE_DEV_ID_X550EM_X_KX4:
2493         case IXGBE_DEV_ID_X550EM_A_KR:
2494         case IXGBE_DEV_ID_X550EM_A_KR_L:
2495                 media_type = ixgbe_media_type_backplane;
2496                 break;
2497         case IXGBE_DEV_ID_X550EM_X_SFP:
2498         case IXGBE_DEV_ID_X550EM_A_SFP:
2499         case IXGBE_DEV_ID_X550EM_A_SFP_N:
2500                 media_type = ixgbe_media_type_fiber;
2501                 break;
2502         case IXGBE_DEV_ID_X550EM_X_1G_T:
2503         case IXGBE_DEV_ID_X550EM_X_10G_T:
2504         case IXGBE_DEV_ID_X550EM_A_10G_T:
2505                 media_type = ixgbe_media_type_copper;
2506                 break;
2507         default:
2508                 media_type = ixgbe_media_type_unknown;
2509                 break;
2510         }
2511         return media_type;
2512 }
2513
2514 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2515  ** @hw: pointer to hardware structure
2516  **/
2517 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2518 {
2519         s32 status;
2520         u16 reg;
2521
2522         status = hw->phy.ops.read_reg(hw,
2523                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2524                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2525                                       &reg);
2526         if (status)
2527                 return status;
2528
2529         /* If PHY FW reset completed bit is set then this is the first
2530          * SW instance after a power on so the PHY FW must be un-stalled.
2531          */
2532         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2533                 status = hw->phy.ops.read_reg(hw,
2534                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2535                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2536                                         &reg);
2537                 if (status)
2538                         return status;
2539
2540                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2541
2542                 status = hw->phy.ops.write_reg(hw,
2543                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2544                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2545                                         reg);
2546                 if (status)
2547                         return status;
2548         }
2549
2550         return status;
2551 }
2552
2553 /**
2554  * ixgbe_set_mdio_speed - Set MDIO clock speed
2555  * @hw: pointer to hardware structure
2556  */
2557 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2558 {
2559         u32 hlreg0;
2560
2561         switch (hw->device_id) {
2562         case IXGBE_DEV_ID_X550EM_X_10G_T:
2563         case IXGBE_DEV_ID_X550EM_A_SGMII:
2564         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2565         case IXGBE_DEV_ID_X550EM_A_10G_T:
2566         case IXGBE_DEV_ID_X550EM_A_SFP:
2567                 /* Config MDIO clock speed before the first MDIO PHY access */
2568                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2569                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2570                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2571                 break;
2572         default:
2573                 break;
2574         }
2575 }
2576
2577 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2578  **  @hw: pointer to hardware structure
2579  **
2580  **  Resets the hardware by resetting the transmit and receive units, masks
2581  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2582  **  reset.
2583  **/
2584 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2585 {
2586         ixgbe_link_speed link_speed;
2587         s32 status;
2588         u32 ctrl = 0;
2589         u32 i;
2590         bool link_up = false;
2591
2592         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2593         status = hw->mac.ops.stop_adapter(hw);
2594         if (status)
2595                 return status;
2596
2597         /* flush pending Tx transactions */
2598         ixgbe_clear_tx_pending(hw);
2599
2600         /* set MDIO speed before talking to the PHY in case it's the 1st time */
2601         ixgbe_set_mdio_speed(hw);
2602
2603         /* PHY ops must be identified and initialized prior to reset */
2604
2605         /* Identify PHY and related function pointers */
2606         status = hw->phy.ops.init(hw);
2607
2608         /* start the external PHY */
2609         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2610                 status = ixgbe_init_ext_t_x550em(hw);
2611                 if (status)
2612                         return status;
2613         }
2614
2615         /* Setup SFP module if there is one present. */
2616         if (hw->phy.sfp_setup_needed) {
2617                 status = hw->mac.ops.setup_sfp(hw);
2618                 hw->phy.sfp_setup_needed = false;
2619         }
2620
2621         /* Reset PHY */
2622         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2623                 hw->phy.ops.reset(hw);
2624
2625 mac_reset_top:
2626         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2627          * If link reset is used when link is up, it might reset the PHY when
2628          * mng is using it.  If link is down or the flag to force full link
2629          * reset is set, then perform link reset.
2630          */
2631         ctrl = IXGBE_CTRL_LNK_RST;
2632
2633         if (!hw->force_full_reset) {
2634                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2635                 if (link_up)
2636                         ctrl = IXGBE_CTRL_RST;
2637         }
2638
2639         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2640         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2641         IXGBE_WRITE_FLUSH(hw);
2642         usleep_range(1000, 1200);
2643
2644         /* Poll for reset bit to self-clear meaning reset is complete */
2645         for (i = 0; i < 10; i++) {
2646                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2647                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2648                         break;
2649                 udelay(1);
2650         }
2651
2652         if (ctrl & IXGBE_CTRL_RST_MASK) {
2653                 status = IXGBE_ERR_RESET_FAILED;
2654                 hw_dbg(hw, "Reset polling failed to complete.\n");
2655         }
2656
2657         msleep(50);
2658
2659         /* Double resets are required for recovery from certain error
2660          * clear the multicast table.  Also reset num_rar_entries to 128,
2661          * since we modify this value when programming the SAN MAC address.
2662          */
2663         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2664                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2665                 goto mac_reset_top;
2666         }
2667
2668         /* Store the permanent mac address */
2669         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2670
2671         /* Store MAC address from RAR0, clear receive address registers, and
2672          * clear the multicast table.  Also reset num_rar_entries to 128,
2673          * since we modify this value when programming the SAN MAC address.
2674          */
2675         hw->mac.num_rar_entries = 128;
2676         hw->mac.ops.init_rx_addrs(hw);
2677
2678         ixgbe_set_mdio_speed(hw);
2679
2680         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2681                 ixgbe_setup_mux_ctl(hw);
2682
2683         return status;
2684 }
2685
2686 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2687  *      anti-spoofing
2688  *  @hw:  pointer to hardware structure
2689  *  @enable: enable or disable switch for Ethertype anti-spoofing
2690  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2691  **/
2692 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2693                                                    bool enable, int vf)
2694 {
2695         int vf_target_reg = vf >> 3;
2696         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2697         u32 pfvfspoof;
2698
2699         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2700         if (enable)
2701                 pfvfspoof |= BIT(vf_target_shift);
2702         else
2703                 pfvfspoof &= ~BIT(vf_target_shift);
2704
2705         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2706 }
2707
2708 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2709  *  @hw: pointer to hardware structure
2710  *  @enable: enable or disable source address pruning
2711  *  @pool: Rx pool to set source address pruning for
2712  **/
2713 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2714                                                   bool enable,
2715                                                   unsigned int pool)
2716 {
2717         u64 pfflp;
2718
2719         /* max rx pool is 63 */
2720         if (pool > 63)
2721                 return;
2722
2723         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2724         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2725
2726         if (enable)
2727                 pfflp |= (1ULL << pool);
2728         else
2729                 pfflp &= ~(1ULL << pool);
2730
2731         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2732         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2733 }
2734
2735 /**
2736  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2737  * @hw: pointer to hardware structure
2738  * @state: set mux if 1, clear if 0
2739  */
2740 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2741 {
2742         u32 esdp;
2743
2744         if (!hw->bus.lan_id)
2745                 return;
2746         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2747         if (state)
2748                 esdp |= IXGBE_ESDP_SDP1;
2749         else
2750                 esdp &= ~IXGBE_ESDP_SDP1;
2751         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2752         IXGBE_WRITE_FLUSH(hw);
2753 }
2754
2755 /**
2756  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2757  * @hw: pointer to hardware structure
2758  * @mask: Mask to specify which semaphore to acquire
2759  *
2760  * Acquires the SWFW semaphore and sets the I2C MUX
2761  */
2762 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2763 {
2764         s32 status;
2765
2766         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2767         if (status)
2768                 return status;
2769
2770         if (mask & IXGBE_GSSR_I2C_MASK)
2771                 ixgbe_set_mux(hw, 1);
2772
2773         return 0;
2774 }
2775
2776 /**
2777  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2778  * @hw: pointer to hardware structure
2779  * @mask: Mask to specify which semaphore to release
2780  *
2781  * Releases the SWFW semaphore and sets the I2C MUX
2782  */
2783 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2784 {
2785         if (mask & IXGBE_GSSR_I2C_MASK)
2786                 ixgbe_set_mux(hw, 0);
2787
2788         ixgbe_release_swfw_sync_X540(hw, mask);
2789 }
2790
2791 /**
2792  * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
2793  * @hw: pointer to hardware structure
2794  * @mask: Mask to specify which semaphore to acquire
2795  *
2796  * Acquires the SWFW semaphore and get the shared PHY token as needed
2797  */
2798 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2799 {
2800         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2801         int retries = FW_PHY_TOKEN_RETRIES;
2802         s32 status;
2803
2804         while (--retries) {
2805                 status = 0;
2806                 if (hmask)
2807                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
2808                 if (status)
2809                         return status;
2810                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
2811                         return 0;
2812
2813                 status = ixgbe_get_phy_token(hw);
2814                 if (!status)
2815                         return 0;
2816                 if (hmask)
2817                         ixgbe_release_swfw_sync_X540(hw, hmask);
2818                 if (status != IXGBE_ERR_TOKEN_RETRY)
2819                         return status;
2820                 msleep(FW_PHY_TOKEN_DELAY);
2821         }
2822
2823         return status;
2824 }
2825
2826 /**
2827  * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
2828  * @hw: pointer to hardware structure
2829  * @mask: Mask to specify which semaphore to release
2830  *
2831  * Release the SWFW semaphore and puts the shared PHY token as needed
2832  */
2833 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2834 {
2835         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2836
2837         if (mask & IXGBE_GSSR_TOKEN_SM)
2838                 ixgbe_put_phy_token(hw);
2839
2840         if (hmask)
2841                 ixgbe_release_swfw_sync_X540(hw, hmask);
2842 }
2843
2844 /**
2845  * ixgbe_read_phy_reg_x550a - Reads specified PHY register
2846  * @hw: pointer to hardware structure
2847  * @reg_addr: 32 bit address of PHY register to read
2848  * @phy_data: Pointer to read data from PHY register
2849  *
2850  * Reads a value from a specified PHY register using the SWFW lock and PHY
2851  * Token. The PHY Token is needed since the MDIO is shared between to MAC
2852  * instances.
2853  */
2854 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2855                                     u32 device_type, u16 *phy_data)
2856 {
2857         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2858         s32 status;
2859
2860         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2861                 return IXGBE_ERR_SWFW_SYNC;
2862
2863         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
2864
2865         hw->mac.ops.release_swfw_sync(hw, mask);
2866
2867         return status;
2868 }
2869
2870 /**
2871  * ixgbe_write_phy_reg_x550a - Writes specified PHY register
2872  * @hw: pointer to hardware structure
2873  * @reg_addr: 32 bit PHY register to write
2874  * @device_type: 5 bit device type
2875  * @phy_data: Data to write to the PHY register
2876  *
2877  * Writes a value to specified PHY register using the SWFW lock and PHY Token.
2878  * The PHY Token is needed since the MDIO is shared between to MAC instances.
2879  */
2880 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2881                                      u32 device_type, u16 phy_data)
2882 {
2883         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2884         s32 status;
2885
2886         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2887                 return IXGBE_ERR_SWFW_SYNC;
2888
2889         status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
2890         hw->mac.ops.release_swfw_sync(hw, mask);
2891
2892         return status;
2893 }
2894
2895 #define X550_COMMON_MAC \
2896         .init_hw                        = &ixgbe_init_hw_generic, \
2897         .start_hw                       = &ixgbe_start_hw_X540, \
2898         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2899         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2900         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2901         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2902         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2903         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2904         .read_analog_reg8               = NULL, \
2905         .write_analog_reg8              = NULL, \
2906         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2907         .check_link                     = &ixgbe_check_mac_link_generic, \
2908         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2909         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2910         .set_rar                        = &ixgbe_set_rar_generic, \
2911         .clear_rar                      = &ixgbe_clear_rar_generic, \
2912         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2913         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2914         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2915         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2916         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2917         .enable_mc                      = &ixgbe_enable_mc_generic, \
2918         .disable_mc                     = &ixgbe_disable_mc_generic, \
2919         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2920         .set_vfta                       = &ixgbe_set_vfta_generic, \
2921         .fc_enable                      = &ixgbe_fc_enable_generic, \
2922         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2923         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2924         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2925         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2926         .set_source_address_pruning     = \
2927                                 &ixgbe_set_source_address_pruning_X550, \
2928         .set_ethertype_anti_spoofing    = \
2929                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2930         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2931         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2932         .get_thermal_sensor_data        = NULL, \
2933         .init_thermal_sensor_thresh     = NULL, \
2934         .enable_rx                      = &ixgbe_enable_rx_generic, \
2935         .disable_rx                     = &ixgbe_disable_rx_x550, \
2936
2937 static const struct ixgbe_mac_operations mac_ops_X550 = {
2938         X550_COMMON_MAC
2939         .led_on                 = ixgbe_led_on_generic,
2940         .led_off                = ixgbe_led_off_generic,
2941         .reset_hw               = &ixgbe_reset_hw_X540,
2942         .get_media_type         = &ixgbe_get_media_type_X540,
2943         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2944         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2945         .setup_link             = &ixgbe_setup_mac_link_X540,
2946         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2947         .get_bus_info           = &ixgbe_get_bus_info_generic,
2948         .setup_sfp              = NULL,
2949         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2950         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2951         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2952         .prot_autoc_read        = prot_autoc_read_generic,
2953         .prot_autoc_write       = prot_autoc_write_generic,
2954         .setup_fc               = ixgbe_setup_fc_generic,
2955 };
2956
2957 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
2958         X550_COMMON_MAC
2959         .led_on                 = ixgbe_led_on_t_x550em,
2960         .led_off                = ixgbe_led_off_t_x550em,
2961         .reset_hw               = &ixgbe_reset_hw_X550em,
2962         .get_media_type         = &ixgbe_get_media_type_X550em,
2963         .get_san_mac_addr       = NULL,
2964         .get_wwn_prefix         = NULL,
2965         .setup_link             = &ixgbe_setup_mac_link_X540,
2966         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2967         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2968         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2969         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2970         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2971         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2972         .setup_fc               = NULL, /* defined later */
2973         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
2974         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
2975 };
2976
2977 static struct ixgbe_mac_operations mac_ops_x550em_a = {
2978         X550_COMMON_MAC
2979         .led_on                 = ixgbe_led_on_t_x550em,
2980         .led_off                = ixgbe_led_off_t_x550em,
2981         .reset_hw               = ixgbe_reset_hw_X550em,
2982         .get_media_type         = ixgbe_get_media_type_X550em,
2983         .get_san_mac_addr       = NULL,
2984         .get_wwn_prefix         = NULL,
2985         .setup_link             = NULL, /* defined later */
2986         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
2987         .get_bus_info           = ixgbe_get_bus_info_X550em,
2988         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2989         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
2990         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
2991         .setup_fc               = ixgbe_setup_fc_x550em,
2992         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
2993         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
2994 };
2995
2996 #define X550_COMMON_EEP \
2997         .read                   = &ixgbe_read_ee_hostif_X550, \
2998         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2999         .write                  = &ixgbe_write_ee_hostif_X550, \
3000         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
3001         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
3002         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
3003         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
3004
3005 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3006         X550_COMMON_EEP
3007         .init_params            = &ixgbe_init_eeprom_params_X550,
3008 };
3009
3010 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3011         X550_COMMON_EEP
3012         .init_params            = &ixgbe_init_eeprom_params_X540,
3013 };
3014
3015 #define X550_COMMON_PHY \
3016         .identify_sfp           = &ixgbe_identify_module_generic, \
3017         .reset                  = NULL, \
3018         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
3019         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
3020         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
3021         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
3022         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
3023         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
3024         .setup_link             = &ixgbe_setup_phy_link_generic, \
3025         .set_phy_power          = NULL, \
3026         .check_overtemp         = &ixgbe_tn_check_overtemp, \
3027         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
3028
3029 static const struct ixgbe_phy_operations phy_ops_X550 = {
3030         X550_COMMON_PHY
3031         .init                   = NULL,
3032         .identify               = &ixgbe_identify_phy_generic,
3033         .read_reg               = &ixgbe_read_phy_reg_generic,
3034         .write_reg              = &ixgbe_write_phy_reg_generic,
3035 };
3036
3037 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3038         X550_COMMON_PHY
3039         .init                   = &ixgbe_init_phy_ops_X550em,
3040         .identify               = &ixgbe_identify_phy_x550em,
3041         .read_reg               = &ixgbe_read_phy_reg_generic,
3042         .write_reg              = &ixgbe_write_phy_reg_generic,
3043         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
3044         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
3045         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
3046         .write_i2c_combined_unlocked =
3047                                      &ixgbe_write_i2c_combined_generic_unlocked,
3048 };
3049
3050 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
3051         X550_COMMON_PHY
3052         .init                   = &ixgbe_init_phy_ops_X550em,
3053         .identify               = &ixgbe_identify_phy_x550em,
3054         .read_reg               = &ixgbe_read_phy_reg_x550a,
3055         .write_reg              = &ixgbe_write_phy_reg_x550a,
3056         .read_reg_mdi           = &ixgbe_read_phy_reg_mdi,
3057         .write_reg_mdi          = &ixgbe_write_phy_reg_mdi,
3058 };
3059
3060 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
3061         IXGBE_MVALS_INIT(X550)
3062 };
3063
3064 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
3065         IXGBE_MVALS_INIT(X550EM_x)
3066 };
3067
3068 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
3069         IXGBE_MVALS_INIT(X550EM_a)
3070 };
3071
3072 const struct ixgbe_info ixgbe_X550_info = {
3073         .mac                    = ixgbe_mac_X550,
3074         .get_invariants         = &ixgbe_get_invariants_X540,
3075         .mac_ops                = &mac_ops_X550,
3076         .eeprom_ops             = &eeprom_ops_X550,
3077         .phy_ops                = &phy_ops_X550,
3078         .mbx_ops                = &mbx_ops_generic,
3079         .mvals                  = ixgbe_mvals_X550,
3080 };
3081
3082 const struct ixgbe_info ixgbe_X550EM_x_info = {
3083         .mac                    = ixgbe_mac_X550EM_x,
3084         .get_invariants         = &ixgbe_get_invariants_X550_x,
3085         .mac_ops                = &mac_ops_X550EM_x,
3086         .eeprom_ops             = &eeprom_ops_X550EM_x,
3087         .phy_ops                = &phy_ops_X550EM_x,
3088         .mbx_ops                = &mbx_ops_generic,
3089         .mvals                  = ixgbe_mvals_X550EM_x,
3090 };
3091
3092 const struct ixgbe_info ixgbe_x550em_a_info = {
3093         .mac                    = ixgbe_mac_x550em_a,
3094         .get_invariants         = &ixgbe_get_invariants_X550_x,
3095         .mac_ops                = &mac_ops_x550em_a,
3096         .eeprom_ops             = &eeprom_ops_X550EM_x,
3097         .phy_ops                = &phy_ops_x550em_a,
3098         .mbx_ops                = &mbx_ops_generic,
3099         .mvals                  = ixgbe_mvals_x550em_a,
3100 };