drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2015 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  30 {
  31         struct ixgbe_mac_info *mac = &hw->mac;
  32         struct ixgbe_phy_info *phy = &hw->phy;
  33
  34         /* Start with X540 invariants, since so simular */
  35         ixgbe_get_invariants_X540(hw);
  36
  37         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  38                 phy->ops.set_phy_power = NULL;
  39
  40         return 0;
  41 }
  42
  43 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  44  *  @hw: pointer to hardware structure
  45  **/
  46 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  47 {
  48         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  49
  50         if (hw->bus.lan_id) {
  51                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  52                 esdp |= IXGBE_ESDP_SDP1_DIR;
  53         }
  54         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  55         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  56         IXGBE_WRITE_FLUSH(hw);
  57 }
  58
  59 /**
  60  * ixgbe_read_cs4227 - Read CS4227 register
  61  * @hw: pointer to hardware structure
  62  * @reg: register number to write
  63  * @value: pointer to receive value read
  64  *
  65  * Returns status code
  66  */
  67 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  68 {
  69         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  70                                                       value);
  71 }
  72
  73 /**
  74  * ixgbe_write_cs4227 - Write CS4227 register
  75  * @hw: pointer to hardware structure
  76  * @reg: register number to write
  77  * @value: value to write to register
  78  *
  79  * Returns status code
  80  */
  81 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  82 {
  83         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  84                                                        value);
  85 }
  86
  87 /**
  88  * ixgbe_check_cs4227_reg - Perform diag on a CS4227 register
  89  * @hw: pointer to hardware structure
  90  * @reg: the register to check
  91  *
  92  * Performs a diagnostic on a register in the CS4227 chip. Returns an error
  93  * if it is not operating correctly.
  94  * This function assumes that the caller has acquired the proper semaphore.
  95  */
  96 static s32 ixgbe_check_cs4227_reg(struct ixgbe_hw *hw, u16 reg)
  97 {
  98         s32 status;
  99         u32 retry;
 100         u16 reg_val;
 101
 102         reg_val = (IXGBE_CS4227_EDC_MODE_DIAG << 1) | 1;
 103         status = ixgbe_write_cs4227(hw, reg, reg_val);
 104         if (status)
 105                 return status;
 106         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 107                 msleep(IXGBE_CS4227_CHECK_DELAY);
 108                 reg_val = 0xFFFF;
 109                 ixgbe_read_cs4227(hw, reg, &reg_val);
 110                 if (!reg_val)
 111                         break;
 112         }
 113         if (reg_val) {
 114                 hw_err(hw, "CS4227 reg 0x%04X failed diagnostic\n", reg);
 115                 return status;
 116         }
 117
 118         return 0;
 119 }
 120
 121 /**
 122  * ixgbe_get_cs4227_status - Return CS4227 status
 123  * @hw: pointer to hardware structure
 124  *
 125  * Performs a diagnostic on the CS4227 chip. Returns an error if it is
 126  * not operating correctly.
 127  * This function assumes that the caller has acquired the proper semaphore.
 128  */
 129 static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
 130 {
 131         s32 status;
 132         u16 value = 0;
 133
 134         /* Exit if the diagnostic has already been performed. */
 135         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 136         if (status)
 137                 return status;
 138         if (value == IXGBE_CS4227_RESET_COMPLETE)
 139                 return 0;
 140
 141         /* Check port 0. */
 142         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB);
 143         if (status)
 144                 return status;
 145
 146         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB);
 147         if (status)
 148                 return status;
 149
 150         /* Check port 1. */
 151         status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB +
 152                                         (1 << 12));
 153         if (status)
 154                 return status;
 155
 156         return ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB +
 157                                       (1 << 12));
 158 }
 159
 160 /**
 161  * ixgbe_read_pe - Read register from port expander
 162  * @hw: pointer to hardware structure
 163  * @reg: register number to read
 164  * @value: pointer to receive read value
 165  *
 166  * Returns status code
 167  */
 168 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 169 {
 170         s32 status;
 171
 172         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 173         if (status)
 174                 hw_err(hw, "port expander access failed with %d\n", status);
 175         return status;
 176 }
 177
 178 /**
 179  * ixgbe_write_pe - Write register to port expander
 180  * @hw: pointer to hardware structure
 181  * @reg: register number to write
 182  * @value: value to write
 183  *
 184  * Returns status code
 185  */
 186 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 187 {
 188         s32 status;
 189
 190         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 191                                                        value);
 192         if (status)
 193                 hw_err(hw, "port expander access failed with %d\n", status);
 194         return status;
 195 }
 196
 197 /**
 198  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 199  * @hw: pointer to hardware structure
 200  *
 201  * This function assumes that the caller has acquired the proper semaphore.
 202  * Returns error code
 203  */
 204 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 205 {
 206         s32 status;
 207         u32 retry;
 208         u16 value;
 209         u8 reg;
 210
 211         /* Trigger hard reset. */
 212         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 213         if (status)
 214                 return status;
 215         reg |= IXGBE_PE_BIT1;
 216         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 217         if (status)
 218                 return status;
 219
 220         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 221         if (status)
 222                 return status;
 223         reg &= ~IXGBE_PE_BIT1;
 224         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 225         if (status)
 226                 return status;
 227
 228         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 229         if (status)
 230                 return status;
 231         reg &= ~IXGBE_PE_BIT1;
 232         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 233         if (status)
 234                 return status;
 235
 236         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 237
 238         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 239         if (status)
 240                 return status;
 241         reg |= IXGBE_PE_BIT1;
 242         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 243         if (status)
 244                 return status;
 245
 246         /* Wait for the reset to complete. */
 247         msleep(IXGBE_CS4227_RESET_DELAY);
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 250                                            &value);
 251                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 252                         break;
 253                 msleep(IXGBE_CS4227_CHECK_DELAY);
 254         }
 255         if (retry == IXGBE_CS4227_RETRIES) {
 256                 hw_err(hw, "CS4227 reset did not complete\n");
 257                 return IXGBE_ERR_PHY;
 258         }
 259
 260         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 261         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 262                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 263                 return IXGBE_ERR_PHY;
 264         }
 265
 266         return 0;
 267 }
 268
 269 /**
 270  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 271  * @hw: pointer to hardware structure
 272  */
 273 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 274 {
 275         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 276         s32 status;
 277         u16 value;
 278         u8 retry;
 279
 280         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 281                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 282                 if (status) {
 283                         hw_err(hw, "semaphore failed with %d\n", status);
 284                         msleep(IXGBE_CS4227_CHECK_DELAY);
 285                         continue;
 286                 }
 287
 288                 /* Get status of reset flow. */
 289                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 290                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 291                         goto out;
 292
 293                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 294                         break;
 295
 296                 /* Reset is pending. Wait and check again. */
 297                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 298                 msleep(IXGBE_CS4227_CHECK_DELAY);
 299         }
 300         /* If still pending, assume other instance failed. */
 301         if (retry == IXGBE_CS4227_RETRIES) {
 302                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 303                 if (status) {
 304                         hw_err(hw, "semaphore failed with %d\n", status);
 305                         return;
 306                 }
 307         }
 308
 309         /* Reset the CS4227. */
 310         status = ixgbe_reset_cs4227(hw);
 311         if (status) {
 312                 hw_err(hw, "CS4227 reset failed: %d", status);
 313                 goto out;
 314         }
 315
 316         /* Reset takes so long, temporarily release semaphore in case the
 317          * other driver instance is waiting for the reset indication.
 318          */
 319         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 320                            IXGBE_CS4227_RESET_PENDING);
 321         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 322         usleep_range(10000, 12000);
 323         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 324         if (status) {
 325                 hw_err(hw, "semaphore failed with %d", status);
 326                 return;
 327         }
 328
 329         /* Is the CS4227 working correctly? */
 330         status = ixgbe_get_cs4227_status(hw);
 331         if (status) {
 332                 hw_err(hw, "CS4227 status failed: %d", status);
 333                 goto out;
 334         }
 335
 336         /* Record completion for next time. */
 337         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 338                                     IXGBE_CS4227_RESET_COMPLETE);
 339
 340 out:
 341         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 342         msleep(hw->eeprom.semaphore_delay);
 343 }
 344
 345 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 346  *  @hw: pointer to hardware structure
 347  *
 348  *  Returns error code
 349  */
 350 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 351 {
 352         switch (hw->device_id) {
 353         case IXGBE_DEV_ID_X550EM_X_SFP:
 354                 /* set up for CS4227 usage */
 355                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 356                 ixgbe_setup_mux_ctl(hw);
 357                 ixgbe_check_cs4227(hw);
 358                 return ixgbe_identify_module_generic(hw);
 359         case IXGBE_DEV_ID_X550EM_X_KX4:
 360                 hw->phy.type = ixgbe_phy_x550em_kx4;
 361                 break;
 362         case IXGBE_DEV_ID_X550EM_X_KR:
 363                 hw->phy.type = ixgbe_phy_x550em_kr;
 364                 break;
 365         case IXGBE_DEV_ID_X550EM_X_1G_T:
 366         case IXGBE_DEV_ID_X550EM_X_10G_T:
 367                 return ixgbe_identify_phy_generic(hw);
 368         default:
 369                 break;
 370         }
 371         return 0;
 372 }
 373
 374 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 375                                      u32 device_type, u16 *phy_data)
 376 {
 377         return IXGBE_NOT_IMPLEMENTED;
 378 }
 379
 380 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 381                                       u32 device_type, u16 phy_data)
 382 {
 383         return IXGBE_NOT_IMPLEMENTED;
 384 }
 385
 386 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 387  *  @hw: pointer to hardware structure
 388  *
 389  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 390  *  ixgbe_hw struct in order to set up EEPROM access.
 391  **/
 392 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 393 {
 394         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 395         u32 eec;
 396         u16 eeprom_size;
 397
 398         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 399                 eeprom->semaphore_delay = 10;
 400                 eeprom->type = ixgbe_flash;
 401
 402                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 403                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 404                                     IXGBE_EEC_SIZE_SHIFT);
 405                 eeprom->word_size = 1 << (eeprom_size +
 406                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 407
 408                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 409                        eeprom->type, eeprom->word_size);
 410         }
 411
 412         return 0;
 413 }
 414
 415 /**
 416  * ixgbe_iosf_wait - Wait for IOSF command completion
 417  * @hw: pointer to hardware structure
 418  * @ctrl: pointer to location to receive final IOSF control value
 419  *
 420  * Return: failing status on timeout
 421  *
 422  * Note: ctrl can be NULL if the IOSF control register value is not needed
 423  */
 424 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 425 {
 426         u32 i, command;
 427
 428         /* Check every 10 usec to see if the address cycle completed.
 429          * The SB IOSF BUSY bit will clear when the operation is
 430          * complete.
 431          */
 432         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 433                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 434                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 435                         break;
 436                 usleep_range(10, 20);
 437         }
 438         if (ctrl)
 439                 *ctrl = command;
 440         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 441                 hw_dbg(hw, "IOSF wait timed out\n");
 442                 return IXGBE_ERR_PHY;
 443         }
 444
 445         return 0;
 446 }
 447
 448 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 449  *  IOSF device
 450  *  @hw: pointer to hardware structure
 451  *  @reg_addr: 32 bit PHY register to write
 452  *  @device_type: 3 bit device type
 453  *  @phy_data: Pointer to read data from the register
 454  **/
 455 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 456                                        u32 device_type, u32 *data)
 457 {
 458         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 459         u32 command, error;
 460         s32 ret;
 461
 462         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 463         if (ret)
 464                 return ret;
 465
 466         ret = ixgbe_iosf_wait(hw, NULL);
 467         if (ret)
 468                 goto out;
 469
 470         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 471                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 472
 473         /* Write IOSF control register */
 474         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 475
 476         ret = ixgbe_iosf_wait(hw, &command);
 477
 478         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 479                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 480                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 481                 hw_dbg(hw, "Failed to read, error %x\n", error);
 482                 return IXGBE_ERR_PHY;
 483         }
 484
 485         if (!ret)
 486                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 487
 488 out:
 489         hw->mac.ops.release_swfw_sync(hw, gssr);
 490         return ret;
 491 }
 492
 493 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 494  *  command assuming that the semaphore is already obtained.
 495  *  @hw: pointer to hardware structure
 496  *  @offset: offset of  word in the EEPROM to read
 497  *  @data: word read from the EEPROM
 498  *
 499  *  Reads a 16 bit word from the EEPROM using the hostif.
 500  **/
 501 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 502                                           u16 *data)
 503 {
 504         s32 status;
 505         struct ixgbe_hic_read_shadow_ram buffer;
 506
 507         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 508         buffer.hdr.req.buf_lenh = 0;
 509         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 510         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 511
 512         /* convert offset from words to bytes */
 513         buffer.address = cpu_to_be32(offset * 2);
 514         /* one word */
 515         buffer.length = cpu_to_be16(sizeof(u16));
 516
 517         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 518                                               sizeof(buffer),
 519                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 520         if (status)
 521                 return status;
 522
 523         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 524                                           FW_NVM_DATA_OFFSET);
 525
 526         return 0;
 527 }
 528
 529 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 530  *  @hw: pointer to hardware structure
 531  *  @offset: offset of  word in the EEPROM to read
 532  *  @words: number of words
 533  *  @data: word(s) read from the EEPROM
 534  *
 535  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 536  **/
 537 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 538                                             u16 offset, u16 words, u16 *data)
 539 {
 540         struct ixgbe_hic_read_shadow_ram buffer;
 541         u32 current_word = 0;
 542         u16 words_to_read;
 543         s32 status;
 544         u32 i;
 545
 546         /* Take semaphore for the entire operation. */
 547         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 548         if (status) {
 549                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 550                 return status;
 551         }
 552
 553         while (words) {
 554                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 555                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 556                 else
 557                         words_to_read = words;
 558
 559                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 560                 buffer.hdr.req.buf_lenh = 0;
 561                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 562                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 563
 564                 /* convert offset from words to bytes */
 565                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 566                 buffer.length = cpu_to_be16(words_to_read * 2);
 567                 buffer.pad2 = 0;
 568                 buffer.pad3 = 0;
 569
 570                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 571                                                       sizeof(buffer),
 572                                                       IXGBE_HI_COMMAND_TIMEOUT,
 573                                                       false);
 574                 if (status) {
 575                         hw_dbg(hw, "Host interface command failed\n");
 576                         goto out;
 577                 }
 578
 579                 for (i = 0; i < words_to_read; i++) {
 580                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 581                                   2 * i;
 582                         u32 value = IXGBE_READ_REG(hw, reg);
 583
 584                         data[current_word] = (u16)(value & 0xffff);
 585                         current_word++;
 586                         i++;
 587                         if (i < words_to_read) {
 588                                 value >>= 16;
 589                                 data[current_word] = (u16)(value & 0xffff);
 590                                 current_word++;
 591                         }
 592                 }
 593                 words -= words_to_read;
 594         }
 595
 596 out:
 597         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 598         return status;
 599 }
 600
 601 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 602  *  @hw: pointer to hardware structure
 603  *  @ptr: pointer offset in eeprom
 604  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 605  *  @csum: address of checksum to update
 606  *
 607  *  Returns error status for any failure
 608  **/
 609 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 610                                    u16 size, u16 *csum, u16 *buffer,
 611                                    u32 buffer_size)
 612 {
 613         u16 buf[256];
 614         s32 status;
 615         u16 length, bufsz, i, start;
 616         u16 *local_buffer;
 617
 618         bufsz = sizeof(buf) / sizeof(buf[0]);
 619
 620         /* Read a chunk at the pointer location */
 621         if (!buffer) {
 622                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 623                 if (status) {
 624                         hw_dbg(hw, "Failed to read EEPROM image\n");
 625                         return status;
 626                 }
 627                 local_buffer = buf;
 628         } else {
 629                 if (buffer_size < ptr)
 630                         return  IXGBE_ERR_PARAM;
 631                 local_buffer = &buffer[ptr];
 632         }
 633
 634         if (size) {
 635                 start = 0;
 636                 length = size;
 637         } else {
 638                 start = 1;
 639                 length = local_buffer[0];
 640
 641                 /* Skip pointer section if length is invalid. */
 642                 if (length == 0xFFFF || length == 0 ||
 643                     (ptr + length) >= hw->eeprom.word_size)
 644                         return 0;
 645         }
 646
 647         if (buffer && ((u32)start + (u32)length > buffer_size))
 648                 return IXGBE_ERR_PARAM;
 649
 650         for (i = start; length; i++, length--) {
 651                 if (i == bufsz && !buffer) {
 652                         ptr += bufsz;
 653                         i = 0;
 654                         if (length < bufsz)
 655                                 bufsz = length;
 656
 657                         /* Read a chunk at the pointer location */
 658                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 659                                                                   bufsz, buf);
 660                         if (status) {
 661                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 662                                 return status;
 663                         }
 664                 }
 665                 *csum += local_buffer[i];
 666         }
 667         return 0;
 668 }
 669
 670 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 671  *  @hw: pointer to hardware structure
 672  *  @buffer: pointer to buffer containing calculated checksum
 673  *  @buffer_size: size of buffer
 674  *
 675  *  Returns a negative error code on error, or the 16-bit checksum
 676  **/
 677 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 678                                     u32 buffer_size)
 679 {
 680         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 681         u16 *local_buffer;
 682         s32 status;
 683         u16 checksum = 0;
 684         u16 pointer, i, size;
 685
 686         hw->eeprom.ops.init_params(hw);
 687
 688         if (!buffer) {
 689                 /* Read pointer area */
 690                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 691                                                 IXGBE_EEPROM_LAST_WORD + 1,
 692                                                 eeprom_ptrs);
 693                 if (status) {
 694                         hw_dbg(hw, "Failed to read EEPROM image\n");
 695                         return status;
 696                 }
 697                 local_buffer = eeprom_ptrs;
 698         } else {
 699                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 700                         return IXGBE_ERR_PARAM;
 701                 local_buffer = buffer;
 702         }
 703
 704         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 705          * checksum word itself
 706          */
 707         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 708                 if (i != IXGBE_EEPROM_CHECKSUM)
 709                         checksum += local_buffer[i];
 710
 711         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 712          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 713          */
 714         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 715                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 716                         continue;
 717
 718                 pointer = local_buffer[i];
 719
 720                 /* Skip pointer section if the pointer is invalid. */
 721                 if (pointer == 0xFFFF || pointer == 0 ||
 722                     pointer >= hw->eeprom.word_size)
 723                         continue;
 724
 725                 switch (i) {
 726                 case IXGBE_PCIE_GENERAL_PTR:
 727                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 728                         break;
 729                 case IXGBE_PCIE_CONFIG0_PTR:
 730                 case IXGBE_PCIE_CONFIG1_PTR:
 731                         size = IXGBE_PCIE_CONFIG_SIZE;
 732                         break;
 733                 default:
 734                         size = 0;
 735                         break;
 736                 }
 737
 738                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 739                                                  buffer, buffer_size);
 740                 if (status)
 741                         return status;
 742         }
 743
 744         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 745
 746         return (s32)checksum;
 747 }
 748
 749 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 750  *  @hw: pointer to hardware structure
 751  *
 752  *  Returns a negative error code on error, or the 16-bit checksum
 753  **/
 754 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 755 {
 756         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 757 }
 758
 759 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 760  *  @hw: pointer to hardware structure
 761  *  @offset: offset of  word in the EEPROM to read
 762  *  @data: word read from the EEPROM
 763  *
 764  *   Reads a 16 bit word from the EEPROM using the hostif.
 765  **/
 766 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 767 {
 768         s32 status = 0;
 769
 770         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 771                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 772                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 773         } else {
 774                 status = IXGBE_ERR_SWFW_SYNC;
 775         }
 776
 777         return status;
 778 }
 779
 780 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 781  *  @hw: pointer to hardware structure
 782  *  @checksum_val: calculated checksum
 783  *
 784  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 785  *  caller does not need checksum_val, the value can be NULL.
 786  **/
 787 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 788                                                u16 *checksum_val)
 789 {
 790         s32 status;
 791         u16 checksum;
 792         u16 read_checksum = 0;
 793
 794         /* Read the first word from the EEPROM. If this times out or fails, do
 795          * not continue or we could be in for a very long wait while every
 796          * EEPROM read fails
 797          */
 798         status = hw->eeprom.ops.read(hw, 0, &checksum);
 799         if (status) {
 800                 hw_dbg(hw, "EEPROM read failed\n");
 801                 return status;
 802         }
 803
 804         status = hw->eeprom.ops.calc_checksum(hw);
 805         if (status < 0)
 806                 return status;
 807
 808         checksum = (u16)(status & 0xffff);
 809
 810         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 811                                            &read_checksum);
 812         if (status)
 813                 return status;
 814
 815         /* Verify read checksum from EEPROM is the same as
 816          * calculated checksum
 817          */
 818         if (read_checksum != checksum) {
 819                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 820                 hw_dbg(hw, "Invalid EEPROM checksum");
 821         }
 822
 823         /* If the user cares, return the calculated checksum */
 824         if (checksum_val)
 825                 *checksum_val = checksum;
 826
 827         return status;
 828 }
 829
 830 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 831  *  @hw: pointer to hardware structure
 832  *  @offset: offset of  word in the EEPROM to write
 833  *  @data: word write to the EEPROM
 834  *
 835  *  Write a 16 bit word to the EEPROM using the hostif.
 836  **/
 837 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 838                                            u16 data)
 839 {
 840         s32 status;
 841         struct ixgbe_hic_write_shadow_ram buffer;
 842
 843         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 844         buffer.hdr.req.buf_lenh = 0;
 845         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 846         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 847
 848         /* one word */
 849         buffer.length = cpu_to_be16(sizeof(u16));
 850         buffer.data = data;
 851         buffer.address = cpu_to_be32(offset * 2);
 852
 853         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 854                                               sizeof(buffer),
 855                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 856         return status;
 857 }
 858
 859 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 860  *  @hw: pointer to hardware structure
 861  *  @offset: offset of  word in the EEPROM to write
 862  *  @data: word write to the EEPROM
 863  *
 864  *  Write a 16 bit word to the EEPROM using the hostif.
 865  **/
 866 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 867 {
 868         s32 status = 0;
 869
 870         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 871                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 872                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 873         } else {
 874                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 875                 status = IXGBE_ERR_SWFW_SYNC;
 876         }
 877
 878         return status;
 879 }
 880
 881 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 882  *  @hw: pointer to hardware structure
 883  *
 884  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 885  **/
 886 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 887 {
 888         s32 status = 0;
 889         union ixgbe_hic_hdr2 buffer;
 890
 891         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 892         buffer.req.buf_lenh = 0;
 893         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 894         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 895
 896         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 897                                               sizeof(buffer),
 898                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 899         return status;
 900 }
 901
 902 /**
 903  * ixgbe_get_bus_info_X550em - Set PCI bus info
 904  * @hw: pointer to hardware structure
 905  *
 906  * Sets bus link width and speed to unknown because X550em is
 907  * not a PCI device.
 908  **/
 909 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 910 {
 911         hw->bus.type  = ixgbe_bus_type_internal;
 912         hw->bus.width = ixgbe_bus_width_unknown;
 913         hw->bus.speed = ixgbe_bus_speed_unknown;
 914
 915         hw->mac.ops.set_lan_id(hw);
 916
 917         return 0;
 918 }
 919
 920 /** ixgbe_disable_rx_x550 - Disable RX unit
 921  *
 922  *  Enables the Rx DMA unit for x550
 923  **/
 924 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 925 {
 926         u32 rxctrl, pfdtxgswc;
 927         s32 status;
 928         struct ixgbe_hic_disable_rxen fw_cmd;
 929
 930         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 931         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 932                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 933                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 934                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 935                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 936                         hw->mac.set_lben = true;
 937                 } else {
 938                         hw->mac.set_lben = false;
 939                 }
 940
 941                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 942                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 943                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 944                 fw_cmd.port_number = (u8)hw->bus.lan_id;
 945
 946                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 947                                         sizeof(struct ixgbe_hic_disable_rxen),
 948                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 949
 950                 /* If we fail - disable RX using register write */
 951                 if (status) {
 952                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 953                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 954                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 955                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 956                         }
 957                 }
 958         }
 959 }
 960
 961 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
 962  *  @hw: pointer to hardware structure
 963  *
 964  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
 965  *  checksum and updates the EEPROM and instructs the hardware to update
 966  *  the flash.
 967  **/
 968 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
 969 {
 970         s32 status;
 971         u16 checksum = 0;
 972
 973         /* Read the first word from the EEPROM. If this times out or fails, do
 974          * not continue or we could be in for a very long wait while every
 975          * EEPROM read fails
 976          */
 977         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
 978         if (status) {
 979                 hw_dbg(hw, "EEPROM read failed\n");
 980                 return status;
 981         }
 982
 983         status = ixgbe_calc_eeprom_checksum_X550(hw);
 984         if (status < 0)
 985                 return status;
 986
 987         checksum = (u16)(status & 0xffff);
 988
 989         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 990                                             checksum);
 991         if (status)
 992                 return status;
 993
 994         status = ixgbe_update_flash_X550(hw);
 995
 996         return status;
 997 }
 998
 999 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1000  *  @hw: pointer to hardware structure
1001  *  @offset: offset of  word in the EEPROM to write
1002  *  @words: number of words
1003  *  @data: word(s) write to the EEPROM
1004  *
1005  *
1006  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1007  **/
1008 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1009                                              u16 offset, u16 words,
1010                                              u16 *data)
1011 {
1012         s32 status = 0;
1013         u32 i = 0;
1014
1015         /* Take semaphore for the entire operation. */
1016         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1017         if (status) {
1018                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1019                 return status;
1020         }
1021
1022         for (i = 0; i < words; i++) {
1023                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1024                                                          data[i]);
1025                 if (status) {
1026                         hw_dbg(hw, "Eeprom buffered write failed\n");
1027                         break;
1028                 }
1029         }
1030
1031         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1032
1033         return status;
1034 }
1035
1036 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1037  *  IOSF device
1038  *
1039  *  @hw: pointer to hardware structure
1040  *  @reg_addr: 32 bit PHY register to write
1041  *  @device_type: 3 bit device type
1042  *  @data: Data to write to the register
1043  **/
1044 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1045                                         u32 device_type, u32 data)
1046 {
1047         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1048         u32 command, error;
1049         s32 ret;
1050
1051         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1052         if (ret)
1053                 return ret;
1054
1055         ret = ixgbe_iosf_wait(hw, NULL);
1056         if (ret)
1057                 goto out;
1058
1059         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1060                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1061
1062         /* Write IOSF control register */
1063         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1064
1065         /* Write IOSF data register */
1066         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1067
1068         ret = ixgbe_iosf_wait(hw, &command);
1069
1070         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1071                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1072                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1073                 hw_dbg(hw, "Failed to write, error %x\n", error);
1074                 return IXGBE_ERR_PHY;
1075         }
1076
1077 out:
1078         hw->mac.ops.release_swfw_sync(hw, gssr);
1079         return ret;
1080 }
1081
1082 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1083  *  @hw: pointer to hardware structure
1084  *  @speed: the link speed to force
1085  *
1086  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1087  *  internal and external PHY at a specific speed, without autonegotiation.
1088  **/
1089 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1090 {
1091         s32 status;
1092         u32 reg_val;
1093
1094         /* Disable AN and force speed to 10G Serial. */
1095         status = ixgbe_read_iosf_sb_reg_x550(hw,
1096                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1097                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1098         if (status)
1099                 return status;
1100
1101         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1102         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1103
1104         /* Select forced link speed for internal PHY. */
1105         switch (*speed) {
1106         case IXGBE_LINK_SPEED_10GB_FULL:
1107                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1108                 break;
1109         case IXGBE_LINK_SPEED_1GB_FULL:
1110                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1111                 break;
1112         default:
1113                 /* Other link speeds are not supported by internal KR PHY. */
1114                 return IXGBE_ERR_LINK_SETUP;
1115         }
1116
1117         status = ixgbe_write_iosf_sb_reg_x550(hw,
1118                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1119                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1120         if (status)
1121                 return status;
1122
1123         /* Disable training protocol FSM. */
1124         status = ixgbe_read_iosf_sb_reg_x550(hw,
1125                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1126                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1127         if (status)
1128                 return status;
1129
1130         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1131         status = ixgbe_write_iosf_sb_reg_x550(hw,
1132                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1133                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1134         if (status)
1135                 return status;
1136
1137         /* Disable Flex from training TXFFE. */
1138         status = ixgbe_read_iosf_sb_reg_x550(hw,
1139                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1140                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1141         if (status)
1142                 return status;
1143
1144         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1145         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1146         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1147         status = ixgbe_write_iosf_sb_reg_x550(hw,
1148                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1149                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1150         if (status)
1151                 return status;
1152
1153         status = ixgbe_read_iosf_sb_reg_x550(hw,
1154                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1155                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1156         if (status)
1157                 return status;
1158
1159         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1160         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1161         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1162         status = ixgbe_write_iosf_sb_reg_x550(hw,
1163                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1164                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1165         if (status)
1166                 return status;
1167
1168         /* Enable override for coefficients. */
1169         status = ixgbe_read_iosf_sb_reg_x550(hw,
1170                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1171                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1172         if (status)
1173                 return status;
1174
1175         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1176         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1177         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1178         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1179         status = ixgbe_write_iosf_sb_reg_x550(hw,
1180                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1181                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1182         if (status)
1183                 return status;
1184
1185         /* Toggle port SW reset by AN reset. */
1186         status = ixgbe_read_iosf_sb_reg_x550(hw,
1187                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1188                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1189         if (status)
1190                 return status;
1191
1192         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1193         status = ixgbe_write_iosf_sb_reg_x550(hw,
1194                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1195                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1196
1197         return status;
1198 }
1199
1200 /**
1201  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1202  *  @hw: pointer to hardware structure
1203  *  @linear: true if SFP module is linear
1204  */
1205 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1206 {
1207         switch (hw->phy.sfp_type) {
1208         case ixgbe_sfp_type_not_present:
1209                 return IXGBE_ERR_SFP_NOT_PRESENT;
1210         case ixgbe_sfp_type_da_cu_core0:
1211         case ixgbe_sfp_type_da_cu_core1:
1212                 *linear = true;
1213                 break;
1214         case ixgbe_sfp_type_srlr_core0:
1215         case ixgbe_sfp_type_srlr_core1:
1216         case ixgbe_sfp_type_da_act_lmt_core0:
1217         case ixgbe_sfp_type_da_act_lmt_core1:
1218         case ixgbe_sfp_type_1g_sx_core0:
1219         case ixgbe_sfp_type_1g_sx_core1:
1220         case ixgbe_sfp_type_1g_lx_core0:
1221         case ixgbe_sfp_type_1g_lx_core1:
1222                 *linear = false;
1223                 break;
1224         case ixgbe_sfp_type_unknown:
1225         case ixgbe_sfp_type_1g_cu_core0:
1226         case ixgbe_sfp_type_1g_cu_core1:
1227         default:
1228                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1229         }
1230
1231         return 0;
1232 }
1233
1234 /**
1235  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1236  *  @hw: pointer to hardware structure
1237  *
1238  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1239  */
1240 static s32
1241 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1242                                 ixgbe_link_speed speed,
1243                                 __always_unused bool autoneg_wait_to_complete)
1244 {
1245         s32 status;
1246         u16 slice, value;
1247         bool setup_linear = false;
1248
1249         /* Check if SFP module is supported and linear */
1250         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1251
1252         /* If no SFP module present, then return success. Return success since
1253          * there is no reason to configure CS4227 and SFP not present error is
1254          * not accepted in the setup MAC link flow.
1255          */
1256         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1257                 return 0;
1258
1259         if (status)
1260                 return status;
1261
1262         /* Configure CS4227 LINE side to 10G SR. */
1263         slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1264         value = IXGBE_CS4227_SPEED_10G;
1265         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1266                                                   value);
1267
1268         /* Configure CS4227 for HOST connection rate then type. */
1269         slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1270         value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1271                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1272         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1273                                                   value);
1274
1275         slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1276         if (setup_linear)
1277                 value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1278         else
1279                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1280         status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1281                                                   value);
1282
1283         /* If internal link mode is XFI, then setup XFI internal link. */
1284         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1285                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1286
1287         return status;
1288 }
1289
1290 /**
1291  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1292  * @hw: pointer to hardware structure
1293  * @speed: new link speed
1294  * @autoneg_wait_to_complete: true when waiting for completion is needed
1295  *
1296  * Setup internal/external PHY link speed based on link speed, then set
1297  * external PHY auto advertised link speed.
1298  *
1299  * Returns error status for any failure
1300  **/
1301 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1302                                          ixgbe_link_speed speed,
1303                                          bool autoneg_wait)
1304 {
1305         s32 status;
1306         ixgbe_link_speed force_speed;
1307
1308         /* Setup internal/external PHY link speed to iXFI (10G), unless
1309          * only 1G is auto advertised then setup KX link.
1310          */
1311         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1312                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1313         else
1314                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1315
1316         /* If internal link mode is XFI, then setup XFI internal link. */
1317         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1318                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1319
1320                 if (status)
1321                         return status;
1322         }
1323
1324         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1325 }
1326
1327 /** ixgbe_check_link_t_X550em - Determine link and speed status
1328   * @hw: pointer to hardware structure
1329   * @speed: pointer to link speed
1330   * @link_up: true when link is up
1331   * @link_up_wait_to_complete: bool used to wait for link up or not
1332   *
1333   * Check that both the MAC and X557 external PHY have link.
1334   **/
1335 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1336                                      ixgbe_link_speed *speed,
1337                                      bool *link_up,
1338                                      bool link_up_wait_to_complete)
1339 {
1340         u32 status;
1341         u16 autoneg_status;
1342
1343         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1344                 return IXGBE_ERR_CONFIG;
1345
1346         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1347                                               link_up_wait_to_complete);
1348
1349         /* If check link fails or MAC link is not up, then return */
1350         if (status || !(*link_up))
1351                 return status;
1352
1353          /* MAC link is up, so check external PHY link.
1354           * Read this twice back to back to indicate current status.
1355           */
1356         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1357                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1358                                       &autoneg_status);
1359         if (status)
1360                 return status;
1361
1362         /* If external PHY link is not up, then indicate link not up */
1363         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1364                 *link_up = false;
1365
1366         return 0;
1367 }
1368
1369 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1370  *  @hw: pointer to hardware structure
1371  **/
1372 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1373 {
1374         struct ixgbe_mac_info *mac = &hw->mac;
1375
1376         switch (mac->ops.get_media_type(hw)) {
1377         case ixgbe_media_type_fiber:
1378                 /* CS4227 does not support autoneg, so disable the laser control
1379                  * functions for SFP+ fiber
1380                  */
1381                 mac->ops.disable_tx_laser = NULL;
1382                 mac->ops.enable_tx_laser = NULL;
1383                 mac->ops.flap_tx_laser = NULL;
1384                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1385                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1386                 mac->ops.set_rate_select_speed =
1387                                         ixgbe_set_soft_rate_select_speed;
1388                 break;
1389         case ixgbe_media_type_copper:
1390                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1391                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1392                 break;
1393         default:
1394                 break;
1395         }
1396 }
1397
1398 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1399  * @hw: pointer to hardware structure
1400  */
1401 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1402 {
1403         s32 status;
1404         bool linear;
1405
1406         /* Check if SFP module is supported */
1407         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1408         if (status)
1409                 return status;
1410
1411         ixgbe_init_mac_link_ops_X550em(hw);
1412         hw->phy.ops.reset = NULL;
1413
1414         return 0;
1415 }
1416
1417 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1418  * @hw: pointer to hardware structure
1419  * @speed: pointer to link speed
1420  * @autoneg: true when autoneg or autotry is enabled
1421  **/
1422 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1423                                               ixgbe_link_speed *speed,
1424                                               bool *autoneg)
1425 {
1426         /* SFP */
1427         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1428                 /* CS4227 SFP must not enable auto-negotiation */
1429                 *autoneg = false;
1430
1431                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1432                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1433                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1434                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1435                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1436                         return 0;
1437                 }
1438
1439                 /* Link capabilities are based on SFP */
1440                 if (hw->phy.multispeed_fiber)
1441                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1442                                  IXGBE_LINK_SPEED_1GB_FULL;
1443                 else
1444                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1445         } else {
1446                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1447                          IXGBE_LINK_SPEED_1GB_FULL;
1448                 *autoneg = true;
1449         }
1450         return 0;
1451 }
1452
1453 /**
1454  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1455  * @hw: pointer to hardware structure
1456  * @lsc: pointer to boolean flag which indicates whether external Base T
1457  *       PHY interrupt is lsc
1458  *
1459  * Determime if external Base T PHY interrupt cause is high temperature
1460  * failure alarm or link status change.
1461  *
1462  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1463  * failure alarm, else return PHY access status.
1464  **/
1465 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1466 {
1467         u32 status;
1468         u16 reg;
1469
1470         *lsc = false;
1471
1472         /* Vendor alarm triggered */
1473         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1474                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1475                                       &reg);
1476
1477         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1478                 return status;
1479
1480         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1481         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1482                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1483                                       &reg);
1484
1485         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1486                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1487                 return status;
1488
1489         /* High temperature failure alarm triggered */
1490         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1491                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1492                                       &reg);
1493
1494         if (status)
1495                 return status;
1496
1497         /* If high temperature failure, then return over temp error and exit */
1498         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1499                 /* power down the PHY in case the PHY FW didn't already */
1500                 ixgbe_set_copper_phy_power(hw, false);
1501                 return IXGBE_ERR_OVERTEMP;
1502         }
1503
1504         /* Vendor alarm 2 triggered */
1505         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1506                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1507
1508         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1509                 return status;
1510
1511         /* link connect/disconnect event occurred */
1512         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1513                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1514
1515         if (status)
1516                 return status;
1517
1518         /* Indicate LSC */
1519         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1520                 *lsc = true;
1521
1522         return 0;
1523 }
1524
1525 /**
1526  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1527  * @hw: pointer to hardware structure
1528  *
1529  * Enable link status change and temperature failure alarm for the external
1530  * Base T PHY
1531  *
1532  * Returns PHY access status
1533  **/
1534 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1535 {
1536         u32 status;
1537         u16 reg;
1538         bool lsc;
1539
1540         /* Clear interrupt flags */
1541         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1542
1543         /* Enable link status change alarm */
1544         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1545                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1546         if (status)
1547                 return status;
1548
1549         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1550
1551         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1552                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1553         if (status)
1554                 return status;
1555
1556         /* Enables high temperature failure alarm */
1557         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1558                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1559                                       &reg);
1560         if (status)
1561                 return status;
1562
1563         reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1564
1565         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1566                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1567                                        reg);
1568         if (status)
1569                 return status;
1570
1571         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1572         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1573                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1574                                       &reg);
1575         if (status)
1576                 return status;
1577
1578         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1579                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1580
1581         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1582                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1583                                        reg);
1584         if (status)
1585                 return status;
1586
1587         /* Enable chip-wide vendor alarm */
1588         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1589                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1590                                       &reg);
1591         if (status)
1592                 return status;
1593
1594         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1595
1596         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1597                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1598                                        reg);
1599
1600         return status;
1601 }
1602
1603 /**
1604  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1605  * @hw: pointer to hardware structure
1606  *
1607  * Handle external Base T PHY interrupt. If high temperature
1608  * failure alarm then return error, else if link status change
1609  * then setup internal/external PHY link
1610  *
1611  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1612  * failure alarm, else return PHY access status.
1613  **/
1614 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1615 {
1616         struct ixgbe_phy_info *phy = &hw->phy;
1617         bool lsc;
1618         u32 status;
1619
1620         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1621         if (status)
1622                 return status;
1623
1624         if (lsc && phy->ops.setup_internal_link)
1625                 return phy->ops.setup_internal_link(hw);
1626
1627         return 0;
1628 }
1629
1630 /**
1631  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1632  * @hw: pointer to hardware structure
1633  * @speed: link speed
1634  *
1635  * Configures the integrated KR PHY.
1636  **/
1637 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1638                                        ixgbe_link_speed speed)
1639 {
1640         s32 status;
1641         u32 reg_val;
1642
1643         status = ixgbe_read_iosf_sb_reg_x550(hw,
1644                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1645                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1646         if (status)
1647                 return status;
1648
1649         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1650         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1651                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1652
1653         /* Advertise 10G support. */
1654         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1655                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1656
1657         /* Advertise 1G support. */
1658         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1659                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1660
1661         /* Restart auto-negotiation. */
1662         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1663         status = ixgbe_write_iosf_sb_reg_x550(hw,
1664                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1665                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1666
1667         return status;
1668 }
1669
1670 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1671  *  @hw: pointer to hardware structure
1672  *
1673  *   Configures the integrated KX4 PHY.
1674  **/
1675 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1676 {
1677         s32 status;
1678         u32 reg_val;
1679
1680         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1681                                              IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1682                                              hw->bus.lan_id, &reg_val);
1683         if (status)
1684                 return status;
1685
1686         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1687                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1688
1689         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1690
1691         /* Advertise 10G support. */
1692         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1693                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1694
1695         /* Advertise 1G support. */
1696         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1697                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1698
1699         /* Restart auto-negotiation. */
1700         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1701         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1702                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1703                                               hw->bus.lan_id, reg_val);
1704
1705         return status;
1706 }
1707
1708 /**  ixgbe_setup_kr_x550em - Configure the KR PHY.
1709  *   @hw: pointer to hardware structure
1710  *
1711  *   Configures the integrated KR PHY.
1712  **/
1713 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1714 {
1715         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1716 }
1717
1718 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1719  *  @hw: address of hardware structure
1720  *  @link_up: address of boolean to indicate link status
1721  *
1722  *  Returns error code if unable to get link status.
1723  **/
1724 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1725 {
1726         u32 ret;
1727         u16 autoneg_status;
1728
1729         *link_up = false;
1730
1731         /* read this twice back to back to indicate current status */
1732         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1733                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1734                                    &autoneg_status);
1735         if (ret)
1736                 return ret;
1737
1738         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1739                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1740                                    &autoneg_status);
1741         if (ret)
1742                 return ret;
1743
1744         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1745
1746         return 0;
1747 }
1748
1749 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1750  *  @hw: point to hardware structure
1751  *
1752  *  Configures the link between the integrated KR PHY and the external X557 PHY
1753  *  The driver will call this function when it gets a link status change
1754  *  interrupt from the X557 PHY. This function configures the link speed
1755  *  between the PHYs to match the link speed of the BASE-T link.
1756  *
1757  * A return of a non-zero value indicates an error, and the base driver should
1758  * not report link up.
1759  **/
1760 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1761 {
1762         ixgbe_link_speed force_speed;
1763         bool link_up;
1764         u32 status;
1765         u16 speed;
1766
1767         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1768                 return IXGBE_ERR_CONFIG;
1769
1770         /* If link is not up, then there is no setup necessary so return  */
1771         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1772         if (status)
1773                 return status;
1774
1775         if (!link_up)
1776                 return 0;
1777
1778         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1779                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1780                                       &speed);
1781         if (status)
1782                 return status;
1783
1784         /* If link is not still up, then no setup is necessary so return */
1785         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1786         if (status)
1787                 return status;
1788
1789         if (!link_up)
1790                 return 0;
1791
1792         /* clear everything but the speed and duplex bits */
1793         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1794
1795         switch (speed) {
1796         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1797                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1798                 break;
1799         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1800                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1801                 break;
1802         default:
1803                 /* Internal PHY does not support anything else */
1804                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1805         }
1806
1807         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1808 }
1809
1810 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
1811  *  @hw: pointer to hardware structure
1812  **/
1813 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
1814 {
1815         s32 status;
1816
1817         status = ixgbe_reset_phy_generic(hw);
1818
1819         if (status)
1820                 return status;
1821
1822         /* Configure Link Status Alarm and Temperature Threshold interrupts */
1823         return ixgbe_enable_lasi_ext_t_x550em(hw);
1824 }
1825
1826 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
1827  *  @hw: pointer to hardware structure
1828  *  @lcd_speed: pointer to lowest common link speed
1829  *
1830  *  Determine lowest common link speed with link partner.
1831  **/
1832 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
1833                                   ixgbe_link_speed *lcd_speed)
1834 {
1835         u16 an_lp_status;
1836         s32 status;
1837         u16 word = hw->eeprom.ctrl_word_3;
1838
1839         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
1840
1841         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
1842                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1843                                       &an_lp_status);
1844         if (status)
1845                 return status;
1846
1847         /* If link partner advertised 1G, return 1G */
1848         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
1849                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
1850                 return status;
1851         }
1852
1853         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
1854         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
1855             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
1856                 return status;
1857
1858         /* Link partner not capable of lower speeds, return 10G */
1859         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
1860         return status;
1861 }
1862
1863 /** ixgbe_enter_lplu_x550em - Transition to low power states
1864  *  @hw: pointer to hardware structure
1865  *
1866  *  Configures Low Power Link Up on transition to low power states
1867  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
1868  *  the X557 PHY immediately prior to entering LPLU.
1869  **/
1870 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
1871 {
1872         u16 an_10g_cntl_reg, autoneg_reg, speed;
1873         s32 status;
1874         ixgbe_link_speed lcd_speed;
1875         u32 save_autoneg;
1876         bool link_up;
1877
1878         /* If blocked by MNG FW, then don't restart AN */
1879         if (ixgbe_check_reset_blocked(hw))
1880                 return 0;
1881
1882         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1883         if (status)
1884                 return status;
1885
1886         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
1887                                      &hw->eeprom.ctrl_word_3);
1888         if (status)
1889                 return status;
1890
1891         /* If link is down, LPLU disabled in NVM, WoL disabled, or
1892          * manageability disabled, then force link down by entering
1893          * low power mode.
1894          */
1895         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
1896             !(hw->wol_enabled || ixgbe_mng_present(hw)))
1897                 return ixgbe_set_copper_phy_power(hw, false);
1898
1899         /* Determine LCD */
1900         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
1901         if (status)
1902                 return status;
1903
1904         /* If no valid LCD link speed, then force link down and exit. */
1905         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
1906                 return ixgbe_set_copper_phy_power(hw, false);
1907
1908         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1909                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1910                                       &speed);
1911         if (status)
1912                 return status;
1913
1914         /* If no link now, speed is invalid so take link down */
1915         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1916         if (status)
1917                 return ixgbe_set_copper_phy_power(hw, false);
1918
1919         /* clear everything but the speed bits */
1920         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
1921
1922         /* If current speed is already LCD, then exit. */
1923         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
1924              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
1925             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
1926              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
1927                 return status;
1928
1929         /* Clear AN completed indication */
1930         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
1931                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1932                                       &autoneg_reg);
1933         if (status)
1934                 return status;
1935
1936         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1937                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1938                                       &an_10g_cntl_reg);
1939         if (status)
1940                 return status;
1941
1942         status = hw->phy.ops.read_reg(hw,
1943                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1944                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1945                                       &autoneg_reg);
1946         if (status)
1947                 return status;
1948
1949         save_autoneg = hw->phy.autoneg_advertised;
1950
1951         /* Setup link at least common link speed */
1952         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
1953
1954         /* restore autoneg from before setting lplu speed */
1955         hw->phy.autoneg_advertised = save_autoneg;
1956
1957         return status;
1958 }
1959
1960 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1961  *  @hw: pointer to hardware structure
1962  *
1963  *  Initialize any function pointers that were not able to be
1964  *  set during init_shared_code because the PHY/SFP type was
1965  *  not known.  Perform the SFP init if necessary.
1966  **/
1967 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1968 {
1969         struct ixgbe_phy_info *phy = &hw->phy;
1970         ixgbe_link_speed speed;
1971         s32 ret_val;
1972
1973         hw->mac.ops.set_lan_id(hw);
1974
1975         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1976                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1977                 ixgbe_setup_mux_ctl(hw);
1978
1979                 /* Save NW management interface connected on board. This is used
1980                  * to determine internal PHY mode.
1981                  */
1982                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1983
1984                 /* If internal PHY mode is KR, then initialize KR link */
1985                 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1986                         speed = IXGBE_LINK_SPEED_10GB_FULL |
1987                                 IXGBE_LINK_SPEED_1GB_FULL;
1988                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1989                 }
1990         }
1991
1992         /* Identify the PHY or SFP module */
1993         ret_val = phy->ops.identify(hw);
1994
1995         /* Setup function pointers based on detected hardware */
1996         ixgbe_init_mac_link_ops_X550em(hw);
1997         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1998                 phy->ops.reset = NULL;
1999
2000         /* Set functions pointers based on phy type */
2001         switch (hw->phy.type) {
2002         case ixgbe_phy_x550em_kx4:
2003                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2004                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2005                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2006                 break;
2007         case ixgbe_phy_x550em_kr:
2008                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2009                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2010                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2011                 break;
2012         case ixgbe_phy_x550em_ext_t:
2013                 /* Save NW management interface connected on board. This is used
2014                  * to determine internal PHY mode
2015                  */
2016                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2017
2018                 /* If internal link mode is XFI, then setup iXFI internal link,
2019                  * else setup KR now.
2020                  */
2021                 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2022                         phy->ops.setup_internal_link =
2023                                         ixgbe_setup_internal_phy_t_x550em;
2024                 } else {
2025                         speed = IXGBE_LINK_SPEED_10GB_FULL |
2026                                 IXGBE_LINK_SPEED_1GB_FULL;
2027                         ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
2028                 }
2029
2030                 /* setup SW LPLU only for first revision */
2031                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
2032                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
2033                       IXGBE_FUSES0_REV_MASK))
2034                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2035
2036                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2037                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2038                 break;
2039         default:
2040                 break;
2041         }
2042
2043         return ret_val;
2044 }
2045
2046 /** ixgbe_get_media_type_X550em - Get media type
2047  *  @hw: pointer to hardware structure
2048  *
2049  *  Returns the media type (fiber, copper, backplane)
2050  *
2051  */
2052 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2053 {
2054         enum ixgbe_media_type media_type;
2055
2056         /* Detect if there is a copper PHY attached. */
2057         switch (hw->device_id) {
2058         case IXGBE_DEV_ID_X550EM_X_KR:
2059         case IXGBE_DEV_ID_X550EM_X_KX4:
2060                 media_type = ixgbe_media_type_backplane;
2061                 break;
2062         case IXGBE_DEV_ID_X550EM_X_SFP:
2063                 media_type = ixgbe_media_type_fiber;
2064                 break;
2065         case IXGBE_DEV_ID_X550EM_X_1G_T:
2066         case IXGBE_DEV_ID_X550EM_X_10G_T:
2067                  media_type = ixgbe_media_type_copper;
2068                 break;
2069         default:
2070                 media_type = ixgbe_media_type_unknown;
2071                 break;
2072         }
2073         return media_type;
2074 }
2075
2076 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2077  ** @hw: pointer to hardware structure
2078  **/
2079 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2080 {
2081         s32 status;
2082         u16 reg;
2083
2084         status = hw->phy.ops.read_reg(hw,
2085                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2086                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2087                                       &reg);
2088         if (status)
2089                 return status;
2090
2091         /* If PHY FW reset completed bit is set then this is the first
2092          * SW instance after a power on so the PHY FW must be un-stalled.
2093          */
2094         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2095                 status = hw->phy.ops.read_reg(hw,
2096                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2097                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2098                                         &reg);
2099                 if (status)
2100                         return status;
2101
2102                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2103
2104                 status = hw->phy.ops.write_reg(hw,
2105                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2106                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2107                                         reg);
2108                 if (status)
2109                         return status;
2110         }
2111
2112         return status;
2113 }
2114
2115 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2116  **  @hw: pointer to hardware structure
2117  **
2118  **  Resets the hardware by resetting the transmit and receive units, masks
2119  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2120  **  reset.
2121  **/
2122 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2123 {
2124         ixgbe_link_speed link_speed;
2125         s32 status;
2126         u32 ctrl = 0;
2127         u32 i;
2128         u32 hlreg0;
2129         bool link_up = false;
2130
2131         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2132         status = hw->mac.ops.stop_adapter(hw);
2133         if (status)
2134                 return status;
2135
2136         /* flush pending Tx transactions */
2137         ixgbe_clear_tx_pending(hw);
2138
2139         /* PHY ops must be identified and initialized prior to reset */
2140
2141         /* Identify PHY and related function pointers */
2142         status = hw->phy.ops.init(hw);
2143
2144         /* start the external PHY */
2145         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2146                 status = ixgbe_init_ext_t_x550em(hw);
2147                 if (status)
2148                         return status;
2149         }
2150
2151         /* Setup SFP module if there is one present. */
2152         if (hw->phy.sfp_setup_needed) {
2153                 status = hw->mac.ops.setup_sfp(hw);
2154                 hw->phy.sfp_setup_needed = false;
2155         }
2156
2157         /* Reset PHY */
2158         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2159                 hw->phy.ops.reset(hw);
2160
2161 mac_reset_top:
2162         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2163          * If link reset is used when link is up, it might reset the PHY when
2164          * mng is using it.  If link is down or the flag to force full link
2165          * reset is set, then perform link reset.
2166          */
2167         ctrl = IXGBE_CTRL_LNK_RST;
2168
2169         if (!hw->force_full_reset) {
2170                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2171                 if (link_up)
2172                         ctrl = IXGBE_CTRL_RST;
2173         }
2174
2175         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2176         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2177         IXGBE_WRITE_FLUSH(hw);
2178
2179         /* Poll for reset bit to self-clear meaning reset is complete */
2180         for (i = 0; i < 10; i++) {
2181                 udelay(1);
2182                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2183                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2184                         break;
2185         }
2186
2187         if (ctrl & IXGBE_CTRL_RST_MASK) {
2188                 status = IXGBE_ERR_RESET_FAILED;
2189                 hw_dbg(hw, "Reset polling failed to complete.\n");
2190         }
2191
2192         msleep(50);
2193
2194         /* Double resets are required for recovery from certain error
2195          * clear the multicast table.  Also reset num_rar_entries to 128,
2196          * since we modify this value when programming the SAN MAC address.
2197          */
2198         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2199                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2200                 goto mac_reset_top;
2201         }
2202
2203         /* Store the permanent mac address */
2204         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2205
2206         /* Store MAC address from RAR0, clear receive address registers, and
2207          * clear the multicast table.  Also reset num_rar_entries to 128,
2208          * since we modify this value when programming the SAN MAC address.
2209          */
2210         hw->mac.num_rar_entries = 128;
2211         hw->mac.ops.init_rx_addrs(hw);
2212
2213         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
2214                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2215                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2216                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2217         }
2218
2219         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2220                 ixgbe_setup_mux_ctl(hw);
2221
2222         return status;
2223 }
2224
2225 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2226  *      anti-spoofing
2227  *  @hw:  pointer to hardware structure
2228  *  @enable: enable or disable switch for Ethertype anti-spoofing
2229  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2230  **/
2231 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2232                                                    bool enable, int vf)
2233 {
2234         int vf_target_reg = vf >> 3;
2235         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2236         u32 pfvfspoof;
2237
2238         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2239         if (enable)
2240                 pfvfspoof |= (1 << vf_target_shift);
2241         else
2242                 pfvfspoof &= ~(1 << vf_target_shift);
2243
2244         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2245 }
2246
2247 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2248  *  @hw: pointer to hardware structure
2249  *  @enable: enable or disable source address pruning
2250  *  @pool: Rx pool to set source address pruning for
2251  **/
2252 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2253                                                   bool enable,
2254                                                   unsigned int pool)
2255 {
2256         u64 pfflp;
2257
2258         /* max rx pool is 63 */
2259         if (pool > 63)
2260                 return;
2261
2262         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2263         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2264
2265         if (enable)
2266                 pfflp |= (1ULL << pool);
2267         else
2268                 pfflp &= ~(1ULL << pool);
2269
2270         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2271         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2272 }
2273
2274 /**
2275  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2276  * @hw: pointer to hardware structure
2277  * @state: set mux if 1, clear if 0
2278  */
2279 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2280 {
2281         u32 esdp;
2282
2283         if (!hw->bus.lan_id)
2284                 return;
2285         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2286         if (state)
2287                 esdp |= IXGBE_ESDP_SDP1;
2288         else
2289                 esdp &= ~IXGBE_ESDP_SDP1;
2290         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2291         IXGBE_WRITE_FLUSH(hw);
2292 }
2293
2294 /**
2295  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2296  * @hw: pointer to hardware structure
2297  * @mask: Mask to specify which semaphore to acquire
2298  *
2299  * Acquires the SWFW semaphore and sets the I2C MUX
2300  */
2301 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2302 {
2303         s32 status;
2304
2305         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2306         if (status)
2307                 return status;
2308
2309         if (mask & IXGBE_GSSR_I2C_MASK)
2310                 ixgbe_set_mux(hw, 1);
2311
2312         return 0;
2313 }
2314
2315 /**
2316  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2317  * @hw: pointer to hardware structure
2318  * @mask: Mask to specify which semaphore to release
2319  *
2320  * Releases the SWFW semaphore and sets the I2C MUX
2321  */
2322 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2323 {
2324         if (mask & IXGBE_GSSR_I2C_MASK)
2325                 ixgbe_set_mux(hw, 0);
2326
2327         ixgbe_release_swfw_sync_X540(hw, mask);
2328 }
2329
2330 #define X550_COMMON_MAC \
2331         .init_hw                        = &ixgbe_init_hw_generic, \
2332         .start_hw                       = &ixgbe_start_hw_X540, \
2333         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2334         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2335         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2336         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2337         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2338         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2339         .read_analog_reg8               = NULL, \
2340         .write_analog_reg8              = NULL, \
2341         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2342         .check_link                     = &ixgbe_check_mac_link_generic, \
2343         .led_on                         = &ixgbe_led_on_generic, \
2344         .led_off                        = &ixgbe_led_off_generic, \
2345         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2346         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2347         .set_rar                        = &ixgbe_set_rar_generic, \
2348         .clear_rar                      = &ixgbe_clear_rar_generic, \
2349         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2350         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2351         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2352         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2353         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2354         .enable_mc                      = &ixgbe_enable_mc_generic, \
2355         .disable_mc                     = &ixgbe_disable_mc_generic, \
2356         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2357         .set_vfta                       = &ixgbe_set_vfta_generic, \
2358         .fc_enable                      = &ixgbe_fc_enable_generic, \
2359         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2360         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2361         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2362         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2363         .set_source_address_pruning     = \
2364                                 &ixgbe_set_source_address_pruning_X550, \
2365         .set_ethertype_anti_spoofing    = \
2366                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2367         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2368         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2369         .get_thermal_sensor_data        = NULL, \
2370         .init_thermal_sensor_thresh     = NULL, \
2371         .prot_autoc_read                = &prot_autoc_read_generic, \
2372         .prot_autoc_write               = &prot_autoc_write_generic, \
2373         .enable_rx                      = &ixgbe_enable_rx_generic, \
2374         .disable_rx                     = &ixgbe_disable_rx_x550, \
2375
2376 static struct ixgbe_mac_operations mac_ops_X550 = {
2377         X550_COMMON_MAC
2378         .reset_hw               = &ixgbe_reset_hw_X540,
2379         .get_media_type         = &ixgbe_get_media_type_X540,
2380         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2381         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2382         .setup_link             = &ixgbe_setup_mac_link_X540,
2383         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2384         .get_bus_info           = &ixgbe_get_bus_info_generic,
2385         .setup_sfp              = NULL,
2386         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2387         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2388 };
2389
2390 static struct ixgbe_mac_operations mac_ops_X550EM_x = {
2391         X550_COMMON_MAC
2392         .reset_hw               = &ixgbe_reset_hw_X550em,
2393         .get_media_type         = &ixgbe_get_media_type_X550em,
2394         .get_san_mac_addr       = NULL,
2395         .get_wwn_prefix         = NULL,
2396         .setup_link             = NULL, /* defined later */
2397         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2398         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2399         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2400         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2401         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2402 };
2403
2404 #define X550_COMMON_EEP \
2405         .read                   = &ixgbe_read_ee_hostif_X550, \
2406         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2407         .write                  = &ixgbe_write_ee_hostif_X550, \
2408         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2409         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2410         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2411         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
2412
2413 static struct ixgbe_eeprom_operations eeprom_ops_X550 = {
2414         X550_COMMON_EEP
2415         .init_params            = &ixgbe_init_eeprom_params_X550,
2416 };
2417
2418 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
2419         X550_COMMON_EEP
2420         .init_params            = &ixgbe_init_eeprom_params_X540,
2421 };
2422
2423 #define X550_COMMON_PHY \
2424         .identify_sfp           = &ixgbe_identify_module_generic, \
2425         .reset                  = NULL, \
2426         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
2427         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
2428         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
2429         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
2430         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
2431         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
2432         .read_reg               = &ixgbe_read_phy_reg_generic, \
2433         .write_reg              = &ixgbe_write_phy_reg_generic, \
2434         .setup_link             = &ixgbe_setup_phy_link_generic, \
2435         .set_phy_power          = NULL, \
2436         .check_overtemp         = &ixgbe_tn_check_overtemp, \
2437         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
2438
2439 static struct ixgbe_phy_operations phy_ops_X550 = {
2440         X550_COMMON_PHY
2441         .init                   = NULL,
2442         .identify               = &ixgbe_identify_phy_generic,
2443 };
2444
2445 static struct ixgbe_phy_operations phy_ops_X550EM_x = {
2446         X550_COMMON_PHY
2447         .init                   = &ixgbe_init_phy_ops_X550em,
2448         .identify               = &ixgbe_identify_phy_x550em,
2449         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
2450         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
2451         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
2452         .write_i2c_combined_unlocked =
2453                                      &ixgbe_write_i2c_combined_generic_unlocked,
2454 };
2455
2456 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
2457         IXGBE_MVALS_INIT(X550)
2458 };
2459
2460 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
2461         IXGBE_MVALS_INIT(X550EM_x)
2462 };
2463
2464 struct ixgbe_info ixgbe_X550_info = {
2465         .mac                    = ixgbe_mac_X550,
2466         .get_invariants         = &ixgbe_get_invariants_X540,
2467         .mac_ops                = &mac_ops_X550,
2468         .eeprom_ops             = &eeprom_ops_X550,
2469         .phy_ops                = &phy_ops_X550,
2470         .mbx_ops                = &mbx_ops_generic,
2471         .mvals                  = ixgbe_mvals_X550,
2472 };
2473
2474 struct ixgbe_info ixgbe_X550EM_x_info = {
2475         .mac                    = ixgbe_mac_X550EM_x,
2476         .get_invariants         = &ixgbe_get_invariants_X550_x,
2477         .mac_ops                = &mac_ops_X550EM_x,
2478         .eeprom_ops             = &eeprom_ops_X550EM_x,
2479         .phy_ops                = &phy_ops_X550EM_x,
2480         .mbx_ops                = &mbx_ops_generic,
2481         .mvals                  = ixgbe_mvals_X550EM_x,
2482 };