drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/bpf.h>
  36 #include <linux/bpf_trace.h>
  37 #include <linux/mlx4/cq.h>
  38 #include <linux/slab.h>
  39 #include <linux/mlx4/qp.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/rculist.h>
  42 #include <linux/if_ether.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/irq.h>
  46
  47 #if IS_ENABLED(CONFIG_IPV6)
  48 #include <net/ip6_checksum.h>
  49 #endif
  50
  51 #include "mlx4_en.h"
  52
  53 static int mlx4_alloc_page(struct mlx4_en_priv *priv,
  54                            struct mlx4_en_rx_alloc *frag,
  55                            gfp_t gfp)
  56 {
  57         struct page *page;
  58         dma_addr_t dma;
  59
  60         page = alloc_page(gfp);
  61         if (unlikely(!page))
  62                 return -ENOMEM;
  63         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE, priv->dma_dir);
  64         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
  65                 __free_page(page);
  66                 return -ENOMEM;
  67         }
  68         frag->page = page;
  69         frag->dma = dma;
  70         frag->page_offset = priv->rx_headroom;
  71         return 0;
  72 }
  73
  74 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  75                                struct mlx4_en_rx_ring *ring,
  76                                struct mlx4_en_rx_desc *rx_desc,
  77                                struct mlx4_en_rx_alloc *frags,
  78                                gfp_t gfp)
  79 {
  80         int i;
  81
  82         for (i = 0; i < priv->num_frags; i++, frags++) {
  83                 if (!frags->page) {
  84                         if (mlx4_alloc_page(priv, frags, gfp))
  85                                 return -ENOMEM;
  86                         ring->rx_alloc_pages++;
  87                 }
  88                 rx_desc->data[i].addr = cpu_to_be64(frags->dma +
  89                                                     frags->page_offset);
  90         }
  91         return 0;
  92 }
  93
  94 static void mlx4_en_free_frag(const struct mlx4_en_priv *priv,
  95                               struct mlx4_en_rx_alloc *frag)
  96 {
  97         if (frag->page) {
  98                 dma_unmap_page(priv->ddev, frag->dma,
  99                                PAGE_SIZE, priv->dma_dir);
 100                 __free_page(frag->page);
 101         }
 102         /* We need to clear all fields, otherwise a change of priv->log_rx_info
 103          * could lead to see garbage later in frag->page.
 104          */
 105         memset(frag, 0, sizeof(*frag));
 106 }
 107
 108 static void mlx4_en_init_rx_desc(const struct mlx4_en_priv *priv,
 109                                  struct mlx4_en_rx_ring *ring, int index)
 110 {
 111         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 112         int possible_frags;
 113         int i;
 114
 115         /* Set size and memtype fields */
 116         for (i = 0; i < priv->num_frags; i++) {
 117                 rx_desc->data[i].byte_count =
 118                         cpu_to_be32(priv->frag_info[i].frag_size);
 119                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 120         }
 121
 122         /* If the number of used fragments does not fill up the ring stride,
 123          * remaining (unused) fragments must be padded with null address/size
 124          * and a special memory key */
 125         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 126         for (i = priv->num_frags; i < possible_frags; i++) {
 127                 rx_desc->data[i].byte_count = 0;
 128                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 129                 rx_desc->data[i].addr = 0;
 130         }
 131 }
 132
 133 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 134                                    struct mlx4_en_rx_ring *ring, int index,
 135                                    gfp_t gfp)
 136 {
 137         struct mlx4_en_rx_desc *rx_desc = ring->buf +
 138                 (index << ring->log_stride);
 139         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 140                                         (index << priv->log_rx_info);
 141         if (likely(ring->page_cache.index > 0)) {
 142                 /* XDP uses a single page per frame */
 143                 if (!frags->page) {
 144                         ring->page_cache.index--;
 145                         frags->page = ring->page_cache.buf[ring->page_cache.index].page;
 146                         frags->dma  = ring->page_cache.buf[ring->page_cache.index].dma;
 147                 }
 148                 frags->page_offset = XDP_PACKET_HEADROOM;
 149                 rx_desc->data[0].addr = cpu_to_be64(frags->dma +
 150                                                     XDP_PACKET_HEADROOM);
 151                 return 0;
 152         }
 153
 154         return mlx4_en_alloc_frags(priv, ring, rx_desc, frags, gfp);
 155 }
 156
 157 static bool mlx4_en_is_ring_empty(const struct mlx4_en_rx_ring *ring)
 158 {
 159         return ring->prod == ring->cons;
 160 }
 161
 162 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 163 {
 164         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 165 }
 166
 167 /* slow path */
 168 static void mlx4_en_free_rx_desc(const struct mlx4_en_priv *priv,
 169                                  struct mlx4_en_rx_ring *ring,
 170                                  int index)
 171 {
 172         struct mlx4_en_rx_alloc *frags;
 173         int nr;
 174
 175         frags = ring->rx_info + (index << priv->log_rx_info);
 176         for (nr = 0; nr < priv->num_frags; nr++) {
 177                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 178                 mlx4_en_free_frag(priv, frags + nr);
 179         }
 180 }
 181
 182 /* Function not in fast-path */
 183 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 184 {
 185         struct mlx4_en_rx_ring *ring;
 186         int ring_ind;
 187         int buf_ind;
 188         int new_size;
 189
 190         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 191                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 192                         ring = priv->rx_ring[ring_ind];
 193
 194                         if (mlx4_en_prepare_rx_desc(priv, ring,
 195                                                     ring->actual_size,
 196                                                     GFP_KERNEL)) {
 197                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 198                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 199                                         return -ENOMEM;
 200                                 } else {
 201                                         new_size = rounddown_pow_of_two(ring->actual_size);
 202                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 203                                                 ring->actual_size, new_size);
 204                                         goto reduce_rings;
 205                                 }
 206                         }
 207                         ring->actual_size++;
 208                         ring->prod++;
 209                 }
 210         }
 211         return 0;
 212
 213 reduce_rings:
 214         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 215                 ring = priv->rx_ring[ring_ind];
 216                 while (ring->actual_size > new_size) {
 217                         ring->actual_size--;
 218                         ring->prod--;
 219                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 220                 }
 221         }
 222
 223         return 0;
 224 }
 225
 226 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 227                                 struct mlx4_en_rx_ring *ring)
 228 {
 229         int index;
 230
 231         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 232                ring->cons, ring->prod);
 233
 234         /* Unmap and free Rx buffers */
 235         for (index = 0; index < ring->size; index++) {
 236                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 237                 mlx4_en_free_rx_desc(priv, ring, index);
 238         }
 239         ring->cons = 0;
 240         ring->prod = 0;
 241 }
 242
 243 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 244 {
 245         int i;
 246         int num_of_eqs;
 247         int num_rx_rings;
 248         struct mlx4_dev *dev = mdev->dev;
 249
 250         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 251                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 252                                    min_t(int,
 253                                          mlx4_get_eqs_per_port(mdev->dev, i),
 254                                          DEF_RX_RINGS));
 255
 256                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 257                         min_t(int, num_of_eqs, num_online_cpus());
 258                 mdev->profile.prof[i].rx_ring_num =
 259                         rounddown_pow_of_two(num_rx_rings);
 260         }
 261 }
 262
 263 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 264                            struct mlx4_en_rx_ring **pring,
 265                            u32 size, u16 stride, int node, int queue_index)
 266 {
 267         struct mlx4_en_dev *mdev = priv->mdev;
 268         struct mlx4_en_rx_ring *ring;
 269         int err = -ENOMEM;
 270         int tmp;
 271
 272         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 273         if (!ring) {
 274                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 275                 if (!ring) {
 276                         en_err(priv, "Failed to allocate RX ring structure\n");
 277                         return -ENOMEM;
 278                 }
 279         }
 280
 281         ring->prod = 0;
 282         ring->cons = 0;
 283         ring->size = size;
 284         ring->size_mask = size - 1;
 285         ring->stride = stride;
 286         ring->log_stride = ffs(ring->stride) - 1;
 287         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 288
 289         if (xdp_rxq_info_reg(&ring->xdp_rxq, priv->dev, queue_index) < 0)
 290                 goto err_ring;
 291
 292         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 293                                         sizeof(struct mlx4_en_rx_alloc));
 294         ring->rx_info = kvzalloc_node(tmp, GFP_KERNEL, node);
 295         if (!ring->rx_info) {
 296                 err = -ENOMEM;
 297                 goto err_xdp_info;
 298         }
 299
 300         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 301                  ring->rx_info, tmp);
 302
 303         /* Allocate HW buffers on provided NUMA node */
 304         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 305         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 306         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 307         if (err)
 308                 goto err_info;
 309
 310         ring->buf = ring->wqres.buf.direct.buf;
 311
 312         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 313
 314         *pring = ring;
 315         return 0;
 316
 317 err_info:
 318         kvfree(ring->rx_info);
 319         ring->rx_info = NULL;
 320 err_xdp_info:
 321         xdp_rxq_info_unreg(&ring->xdp_rxq);
 322 err_ring:
 323         kfree(ring);
 324         *pring = NULL;
 325
 326         return err;
 327 }
 328
 329 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 330 {
 331         struct mlx4_en_rx_ring *ring;
 332         int i;
 333         int ring_ind;
 334         int err;
 335         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 336                                         DS_SIZE * priv->num_frags);
 337
 338         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 339                 ring = priv->rx_ring[ring_ind];
 340
 341                 ring->prod = 0;
 342                 ring->cons = 0;
 343                 ring->actual_size = 0;
 344                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 345
 346                 ring->stride = stride;
 347                 if (ring->stride <= TXBB_SIZE) {
 348                         /* Stamp first unused send wqe */
 349                         __be32 *ptr = (__be32 *)ring->buf;
 350                         __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
 351                         *ptr = stamp;
 352                         /* Move pointer to start of rx section */
 353                         ring->buf += TXBB_SIZE;
 354                 }
 355
 356                 ring->log_stride = ffs(ring->stride) - 1;
 357                 ring->buf_size = ring->size * ring->stride;
 358
 359                 memset(ring->buf, 0, ring->buf_size);
 360                 mlx4_en_update_rx_prod_db(ring);
 361
 362                 /* Initialize all descriptors */
 363                 for (i = 0; i < ring->size; i++)
 364                         mlx4_en_init_rx_desc(priv, ring, i);
 365         }
 366         err = mlx4_en_fill_rx_buffers(priv);
 367         if (err)
 368                 goto err_buffers;
 369
 370         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 371                 ring = priv->rx_ring[ring_ind];
 372
 373                 ring->size_mask = ring->actual_size - 1;
 374                 mlx4_en_update_rx_prod_db(ring);
 375         }
 376
 377         return 0;
 378
 379 err_buffers:
 380         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 381                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 382
 383         ring_ind = priv->rx_ring_num - 1;
 384         while (ring_ind >= 0) {
 385                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 386                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 387                 ring_ind--;
 388         }
 389         return err;
 390 }
 391
 392 /* We recover from out of memory by scheduling our napi poll
 393  * function (mlx4_en_process_cq), which tries to allocate
 394  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 395  */
 396 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 397 {
 398         int ring;
 399
 400         if (!priv->port_up)
 401                 return;
 402
 403         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 404                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
 405                         local_bh_disable();
 406                         napi_reschedule(&priv->rx_cq[ring]->napi);
 407                         local_bh_enable();
 408                 }
 409         }
 410 }
 411
 412 /* When the rx ring is running in page-per-packet mode, a released frame can go
 413  * directly into a small cache, to avoid unmapping or touching the page
 414  * allocator. In bpf prog performance scenarios, buffers are either forwarded
 415  * or dropped, never converted to skbs, so every page can come directly from
 416  * this cache when it is sized to be a multiple of the napi budget.
 417  */
 418 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 419                         struct mlx4_en_rx_alloc *frame)
 420 {
 421         struct mlx4_en_page_cache *cache = &ring->page_cache;
 422
 423         if (cache->index >= MLX4_EN_CACHE_SIZE)
 424                 return false;
 425
 426         cache->buf[cache->index].page = frame->page;
 427         cache->buf[cache->index].dma = frame->dma;
 428         cache->index++;
 429         return true;
 430 }
 431
 432 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 433                              struct mlx4_en_rx_ring **pring,
 434                              u32 size, u16 stride)
 435 {
 436         struct mlx4_en_dev *mdev = priv->mdev;
 437         struct mlx4_en_rx_ring *ring = *pring;
 438         struct bpf_prog *old_prog;
 439
 440         old_prog = rcu_dereference_protected(
 441                                         ring->xdp_prog,
 442                                         lockdep_is_held(&mdev->state_lock));
 443         if (old_prog)
 444                 bpf_prog_put(old_prog);
 445         xdp_rxq_info_unreg(&ring->xdp_rxq);
 446         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 447         kvfree(ring->rx_info);
 448         ring->rx_info = NULL;
 449         kfree(ring);
 450         *pring = NULL;
 451 }
 452
 453 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 454                                 struct mlx4_en_rx_ring *ring)
 455 {
 456         int i;
 457
 458         for (i = 0; i < ring->page_cache.index; i++) {
 459                 dma_unmap_page(priv->ddev, ring->page_cache.buf[i].dma,
 460                                PAGE_SIZE, priv->dma_dir);
 461                 put_page(ring->page_cache.buf[i].page);
 462         }
 463         ring->page_cache.index = 0;
 464         mlx4_en_free_rx_buf(priv, ring);
 465         if (ring->stride <= TXBB_SIZE)
 466                 ring->buf -= TXBB_SIZE;
 467 }
 468
 469
 470 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 471                                     struct mlx4_en_rx_alloc *frags,
 472                                     struct sk_buff *skb,
 473                                     int length)
 474 {
 475         const struct mlx4_en_frag_info *frag_info = priv->frag_info;
 476         unsigned int truesize = 0;
 477         bool release = true;
 478         int nr, frag_size;
 479         struct page *page;
 480         dma_addr_t dma;
 481
 482         /* Collect used fragments while replacing them in the HW descriptors */
 483         for (nr = 0;; frags++) {
 484                 frag_size = min_t(int, length, frag_info->frag_size);
 485
 486                 page = frags->page;
 487                 if (unlikely(!page))
 488                         goto fail;
 489
 490                 dma = frags->dma;
 491                 dma_sync_single_range_for_cpu(priv->ddev, dma, frags->page_offset,
 492                                               frag_size, priv->dma_dir);
 493
 494                 __skb_fill_page_desc(skb, nr, page, frags->page_offset,
 495                                      frag_size);
 496
 497                 truesize += frag_info->frag_stride;
 498                 if (frag_info->frag_stride == PAGE_SIZE / 2) {
 499                         frags->page_offset ^= PAGE_SIZE / 2;
 500                         release = page_count(page) != 1 ||
 501                                   page_is_pfmemalloc(page) ||
 502                                   page_to_nid(page) != numa_mem_id();
 503                 } else if (!priv->rx_headroom) {
 504                         /* rx_headroom for non XDP setup is always 0.
 505                          * When XDP is set, the above condition will
 506                          * guarantee page is always released.
 507                          */
 508                         u32 sz_align = ALIGN(frag_size, SMP_CACHE_BYTES);
 509
 510                         frags->page_offset += sz_align;
 511                         release = frags->page_offset + frag_info->frag_size > PAGE_SIZE;
 512                 }
 513                 if (release) {
 514                         dma_unmap_page(priv->ddev, dma, PAGE_SIZE, priv->dma_dir);
 515                         frags->page = NULL;
 516                 } else {
 517                         page_ref_inc(page);
 518                 }
 519
 520                 nr++;
 521                 length -= frag_size;
 522                 if (!length)
 523                         break;
 524                 frag_info++;
 525         }
 526         skb->truesize += truesize;
 527         return nr;
 528
 529 fail:
 530         while (nr > 0) {
 531                 nr--;
 532                 __skb_frag_unref(skb_shinfo(skb)->frags + nr);
 533         }
 534         return 0;
 535 }
 536
 537 static void validate_loopback(struct mlx4_en_priv *priv, void *va)
 538 {
 539         const unsigned char *data = va + ETH_HLEN;
 540         int i;
 541
 542         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++) {
 543                 if (data[i] != (unsigned char)i)
 544                         return;
 545         }
 546         /* Loopback found */
 547         priv->loopback_ok = 1;
 548 }
 549
 550 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 551                                       struct mlx4_en_rx_ring *ring)
 552 {
 553         u32 missing = ring->actual_size - (ring->prod - ring->cons);
 554
 555         /* Try to batch allocations, but not too much. */
 556         if (missing < 8)
 557                 return;
 558         do {
 559                 if (mlx4_en_prepare_rx_desc(priv, ring,
 560                                             ring->prod & ring->size_mask,
 561                                             GFP_ATOMIC | __GFP_MEMALLOC))
 562                         break;
 563                 ring->prod++;
 564         } while (likely(--missing));
 565
 566         mlx4_en_update_rx_prod_db(ring);
 567 }
 568
 569 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 570  * over it and add it to the hardware's checksum calculation
 571  */
 572 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 573                                          struct vlan_hdr *vlanh)
 574 {
 575         return csum_add(hw_checksum, *(__wsum *)vlanh);
 576 }
 577
 578 /* Although the stack expects checksum which doesn't include the pseudo
 579  * header, the HW adds it. To address that, we are subtracting the pseudo
 580  * header checksum from the checksum value provided by the HW.
 581  */
 582 static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 583                                struct iphdr *iph)
 584 {
 585         __u16 length_for_csum = 0;
 586         __wsum csum_pseudo_header = 0;
 587         __u8 ipproto = iph->protocol;
 588
 589         if (unlikely(ipproto == IPPROTO_SCTP))
 590                 return -1;
 591
 592         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 593         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 594                                                 length_for_csum, ipproto, 0);
 595         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 596         return 0;
 597 }
 598
 599 #if IS_ENABLED(CONFIG_IPV6)
 600 /* In IPv6 packets, hw_checksum lacks 6 bytes from IPv6 header:
 601  * 4 first bytes : priority, version, flow_lbl
 602  * and 2 additional bytes : nexthdr, hop_limit.
 603  */
 604 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 605                                struct ipv6hdr *ipv6h)
 606 {
 607         __u8 nexthdr = ipv6h->nexthdr;
 608         __wsum temp;
 609
 610         if (unlikely(nexthdr == IPPROTO_FRAGMENT ||
 611                      nexthdr == IPPROTO_HOPOPTS ||
 612                      nexthdr == IPPROTO_SCTP))
 613                 return -1;
 614
 615         /* priority, version, flow_lbl */
 616         temp = csum_add(hw_checksum, *(__wsum *)ipv6h);
 617         /* nexthdr and hop_limit */
 618         skb->csum = csum_add(temp, (__force __wsum)*(__be16 *)&ipv6h->nexthdr);
 619         return 0;
 620 }
 621 #endif
 622
 623 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 624
 625 /* We reach this function only after checking that any of
 626  * the (IPv4 | IPv6) bits are set in cqe->status.
 627  */
 628 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 629                       netdev_features_t dev_features)
 630 {
 631         __wsum hw_checksum = 0;
 632         void *hdr;
 633
 634         /* CQE csum doesn't cover padding octets in short ethernet
 635          * frames. And the pad field is appended prior to calculating
 636          * and appending the FCS field.
 637          *
 638          * Detecting these padded frames requires to verify and parse
 639          * IP headers, so we simply force all those small frames to skip
 640          * checksum complete.
 641          */
 642         if (short_frame(skb->len))
 643                 return -EINVAL;
 644
 645         hdr = (u8 *)va + sizeof(struct ethhdr);
 646         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 647
 648         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 649             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 650                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 651                 hdr += sizeof(struct vlan_hdr);
 652         }
 653
 654 #if IS_ENABLED(CONFIG_IPV6)
 655         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 656                 return get_fixed_ipv6_csum(hw_checksum, skb, hdr);
 657 #endif
 658         return get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 659 }
 660
 661 #if IS_ENABLED(CONFIG_IPV6)
 662 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4 | MLX4_CQE_STATUS_IPV6)
 663 #else
 664 #define MLX4_CQE_STATUS_IP_ANY (MLX4_CQE_STATUS_IPV4)
 665 #endif
 666
 667 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 668 {
 669         struct mlx4_en_priv *priv = netdev_priv(dev);
 670         int factor = priv->cqe_factor;
 671         struct mlx4_en_rx_ring *ring;
 672         struct bpf_prog *xdp_prog;
 673         int cq_ring = cq->ring;
 674         bool doorbell_pending;
 675         struct mlx4_cqe *cqe;
 676         struct xdp_buff xdp;
 677         int polled = 0;
 678         int index;
 679
 680         if (unlikely(!priv->port_up || budget <= 0))
 681                 return 0;
 682
 683         ring = priv->rx_ring[cq_ring];
 684
 685         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
 686         rcu_read_lock();
 687         xdp_prog = rcu_dereference(ring->xdp_prog);
 688         xdp.rxq = &ring->xdp_rxq;
 689         doorbell_pending = 0;
 690
 691         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 692          * descriptor offset can be deduced from the CQE index instead of
 693          * reading 'cqe->index' */
 694         index = cq->mcq.cons_index & ring->size_mask;
 695         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 696
 697         /* Process all completed CQEs */
 698         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 699                     cq->mcq.cons_index & cq->size)) {
 700                 struct mlx4_en_rx_alloc *frags;
 701                 enum pkt_hash_types hash_type;
 702                 struct sk_buff *skb;
 703                 unsigned int length;
 704                 int ip_summed;
 705                 void *va;
 706                 int nr;
 707
 708                 frags = ring->rx_info + (index << priv->log_rx_info);
 709                 va = page_address(frags[0].page) + frags[0].page_offset;
 710                 prefetchw(va);
 711                 /*
 712                  * make sure we read the CQE after we read the ownership bit
 713                  */
 714                 dma_rmb();
 715
 716                 /* Drop packet on bad receive or bad checksum */
 717                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 718                                                 MLX4_CQE_OPCODE_ERROR)) {
 719                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 720                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 721                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 722                         goto next;
 723                 }
 724                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 725                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 726                         goto next;
 727                 }
 728
 729                 /* Check if we need to drop the packet if SRIOV is not enabled
 730                  * and not performing the selftest or flb disabled
 731                  */
 732                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 733                         const struct ethhdr *ethh = va;
 734                         dma_addr_t dma;
 735                         /* Get pointer to first fragment since we haven't
 736                          * skb yet and cast it to ethhdr struct
 737                          */
 738                         dma = frags[0].dma + frags[0].page_offset;
 739                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 740                                                 DMA_FROM_DEVICE);
 741
 742                         if (is_multicast_ether_addr(ethh->h_dest)) {
 743                                 struct mlx4_mac_entry *entry;
 744                                 struct hlist_head *bucket;
 745                                 unsigned int mac_hash;
 746
 747                                 /* Drop the packet, since HW loopback-ed it */
 748                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 749                                 bucket = &priv->mac_hash[mac_hash];
 750                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 751                                         if (ether_addr_equal_64bits(entry->mac,
 752                                                                     ethh->h_source))
 753                                                 goto next;
 754                                 }
 755                         }
 756                 }
 757
 758                 if (unlikely(priv->validate_loopback)) {
 759                         validate_loopback(priv, va);
 760                         goto next;
 761                 }
 762
 763                 /*
 764                  * Packet is OK - process it.
 765                  */
 766                 length = be32_to_cpu(cqe->byte_cnt);
 767                 length -= ring->fcs_del;
 768
 769                 /* A bpf program gets first chance to drop the packet. It may
 770                  * read bytes but not past the end of the frag.
 771                  */
 772                 if (xdp_prog) {
 773                         dma_addr_t dma;
 774                         void *orig_data;
 775                         u32 act;
 776
 777                         dma = frags[0].dma + frags[0].page_offset;
 778                         dma_sync_single_for_cpu(priv->ddev, dma,
 779                                                 priv->frag_info[0].frag_size,
 780                                                 DMA_FROM_DEVICE);
 781
 782                         xdp.data_hard_start = va - frags[0].page_offset;
 783                         xdp.data = va;
 784                         xdp_set_data_meta_invalid(&xdp);
 785                         xdp.data_end = xdp.data + length;
 786                         orig_data = xdp.data;
 787
 788                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
 789
 790                         length = xdp.data_end - xdp.data;
 791                         if (xdp.data != orig_data) {
 792                                 frags[0].page_offset = xdp.data -
 793                                         xdp.data_hard_start;
 794                                 va = xdp.data;
 795                         }
 796
 797                         switch (act) {
 798                         case XDP_PASS:
 799                                 break;
 800                         case XDP_TX:
 801                                 if (likely(!mlx4_en_xmit_frame(ring, frags, priv,
 802                                                         length, cq_ring,
 803                                                         &doorbell_pending))) {
 804                                         frags[0].page = NULL;
 805                                         goto next;
 806                                 }
 807                                 trace_xdp_exception(dev, xdp_prog, act);
 808                                 goto xdp_drop_no_cnt; /* Drop on xmit failure */
 809                         default:
 810                                 bpf_warn_invalid_xdp_action(act);
 811                                 /* fall through */
 812                         case XDP_ABORTED:
 813                                 trace_xdp_exception(dev, xdp_prog, act);
 814                                 /* fall through */
 815                         case XDP_DROP:
 816                                 ring->xdp_drop++;
 817 xdp_drop_no_cnt:
 818                                 goto next;
 819                         }
 820                 }
 821
 822                 ring->bytes += length;
 823                 ring->packets++;
 824
 825                 skb = napi_get_frags(&cq->napi);
 826                 if (unlikely(!skb))
 827                         goto next;
 828
 829                 if (unlikely(ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL)) {
 830                         u64 timestamp = mlx4_en_get_cqe_ts(cqe);
 831
 832                         mlx4_en_fill_hwtstamps(priv->mdev, skb_hwtstamps(skb),
 833                                                timestamp);
 834                 }
 835                 skb_record_rx_queue(skb, cq_ring);
 836
 837                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 838                         /* TODO: For IP non TCP/UDP packets when csum complete is
 839                          * not an option (not supported or any other reason) we can
 840                          * actually check cqe IPOK status bit and report
 841                          * CHECKSUM_UNNECESSARY rather than CHECKSUM_NONE
 842                          */
 843                         if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 844                                                        MLX4_CQE_STATUS_UDP)) &&
 845                             (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 846                             cqe->checksum == cpu_to_be16(0xffff)) {
 847                                 bool l2_tunnel;
 848
 849                                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 850                                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 851                                 ip_summed = CHECKSUM_UNNECESSARY;
 852                                 hash_type = PKT_HASH_TYPE_L4;
 853                                 if (l2_tunnel)
 854                                         skb->csum_level = 1;
 855                                 ring->csum_ok++;
 856                         } else {
 857                                 if (!(priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 858                                       (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IP_ANY))))
 859                                         goto csum_none;
 860                                 if (check_csum(cqe, skb, va, dev->features))
 861                                         goto csum_none;
 862                                 ip_summed = CHECKSUM_COMPLETE;
 863                                 hash_type = PKT_HASH_TYPE_L3;
 864                                 ring->csum_complete++;
 865                         }
 866                 } else {
 867 csum_none:
 868                         ip_summed = CHECKSUM_NONE;
 869                         hash_type = PKT_HASH_TYPE_L3;
 870                         ring->csum_none++;
 871                 }
 872                 skb->ip_summed = ip_summed;
 873                 if (dev->features & NETIF_F_RXHASH)
 874                         skb_set_hash(skb,
 875                                      be32_to_cpu(cqe->immed_rss_invalid),
 876                                      hash_type);
 877
 878                 if ((cqe->vlan_my_qpn &
 879                      cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
 880                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 881                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 882                                                be16_to_cpu(cqe->sl_vid));
 883                 else if ((cqe->vlan_my_qpn &
 884                           cpu_to_be32(MLX4_CQE_SVLAN_PRESENT_MASK)) &&
 885                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
 886                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
 887                                                be16_to_cpu(cqe->sl_vid));
 888
 889                 nr = mlx4_en_complete_rx_desc(priv, frags, skb, length);
 890                 if (likely(nr)) {
 891                         skb_shinfo(skb)->nr_frags = nr;
 892                         skb->len = length;
 893                         skb->data_len = length;
 894                         napi_gro_frags(&cq->napi);
 895                 } else {
 896                         skb->vlan_tci = 0;
 897                         skb_clear_hash(skb);
 898                 }
 899 next:
 900                 ++cq->mcq.cons_index;
 901                 index = (cq->mcq.cons_index) & ring->size_mask;
 902                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 903                 if (unlikely(++polled == budget))
 904                         break;
 905         }
 906
 907         rcu_read_unlock();
 908
 909         if (likely(polled)) {
 910                 if (doorbell_pending) {
 911                         priv->tx_cq[TX_XDP][cq_ring]->xdp_busy = true;
 912                         mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq_ring]);
 913                 }
 914
 915                 mlx4_cq_set_ci(&cq->mcq);
 916                 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
 917                 ring->cons = cq->mcq.cons_index;
 918         }
 919         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
 920
 921         mlx4_en_refill_rx_buffers(priv, ring);
 922
 923         return polled;
 924 }
 925
 926
 927 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
 928 {
 929         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 930         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 931
 932         if (likely(priv->port_up))
 933                 napi_schedule_irqoff(&cq->napi);
 934         else
 935                 mlx4_en_arm_cq(priv, cq);
 936 }
 937
 938 /* Rx CQ polling - called by NAPI */
 939 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
 940 {
 941         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 942         struct net_device *dev = cq->dev;
 943         struct mlx4_en_priv *priv = netdev_priv(dev);
 944         struct mlx4_en_cq *xdp_tx_cq = NULL;
 945         bool clean_complete = true;
 946         int done;
 947
 948         if (!budget)
 949                 return 0;
 950
 951         if (priv->tx_ring_num[TX_XDP]) {
 952                 xdp_tx_cq = priv->tx_cq[TX_XDP][cq->ring];
 953                 if (xdp_tx_cq->xdp_busy) {
 954                         clean_complete = mlx4_en_process_tx_cq(dev, xdp_tx_cq,
 955                                                                budget);
 956                         xdp_tx_cq->xdp_busy = !clean_complete;
 957                 }
 958         }
 959
 960         done = mlx4_en_process_rx_cq(dev, cq, budget);
 961
 962         /* If we used up all the quota - we're probably not done yet... */
 963         if (done == budget || !clean_complete) {
 964                 const struct cpumask *aff;
 965                 struct irq_data *idata;
 966                 int cpu_curr;
 967
 968                 /* in case we got here because of !clean_complete */
 969                 done = budget;
 970
 971                 INC_PERF_COUNTER(priv->pstats.napi_quota);
 972
 973                 cpu_curr = smp_processor_id();
 974                 idata = irq_desc_get_irq_data(cq->irq_desc);
 975                 aff = irq_data_get_affinity_mask(idata);
 976
 977                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
 978                         return budget;
 979
 980                 /* Current cpu is not according to smp_irq_affinity -
 981                  * probably affinity changed. Need to stop this NAPI
 982                  * poll, and restart it on the right CPU.
 983                  * Try to avoid returning a too small value (like 0),
 984                  * to not fool net_rx_action() and its netdev_budget
 985                  */
 986                 if (done)
 987                         done--;
 988         }
 989         /* Done for now */
 990         if (likely(napi_complete_done(napi, done)))
 991                 mlx4_en_arm_cq(priv, cq);
 992         return done;
 993 }
 994
 995 void mlx4_en_calc_rx_buf(struct net_device *dev)
 996 {
 997         struct mlx4_en_priv *priv = netdev_priv(dev);
 998         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
 999         int i = 0;
1000
1001         /* bpf requires buffers to be set up as 1 packet per page.
1002          * This only works when num_frags == 1.
1003          */
1004         if (priv->tx_ring_num[TX_XDP]) {
1005                 priv->frag_info[0].frag_size = eff_mtu;
1006                 /* This will gain efficient xdp frame recycling at the
1007                  * expense of more costly truesize accounting
1008                  */
1009                 priv->frag_info[0].frag_stride = PAGE_SIZE;
1010                 priv->dma_dir = PCI_DMA_BIDIRECTIONAL;
1011                 priv->rx_headroom = XDP_PACKET_HEADROOM;
1012                 i = 1;
1013         } else {
1014                 int frag_size_max = 2048, buf_size = 0;
1015
1016                 /* should not happen, right ? */
1017                 if (eff_mtu > PAGE_SIZE + (MLX4_EN_MAX_RX_FRAGS - 1) * 2048)
1018                         frag_size_max = PAGE_SIZE;
1019
1020                 while (buf_size < eff_mtu) {
1021                         int frag_stride, frag_size = eff_mtu - buf_size;
1022                         int pad, nb;
1023
1024                         if (i < MLX4_EN_MAX_RX_FRAGS - 1)
1025                                 frag_size = min(frag_size, frag_size_max);
1026
1027                         priv->frag_info[i].frag_size = frag_size;
1028                         frag_stride = ALIGN(frag_size, SMP_CACHE_BYTES);
1029                         /* We can only pack 2 1536-bytes frames in on 4K page
1030                          * Therefore, each frame would consume more bytes (truesize)
1031                          */
1032                         nb = PAGE_SIZE / frag_stride;
1033                         pad = (PAGE_SIZE - nb * frag_stride) / nb;
1034                         pad &= ~(SMP_CACHE_BYTES - 1);
1035                         priv->frag_info[i].frag_stride = frag_stride + pad;
1036
1037                         buf_size += frag_size;
1038                         i++;
1039                 }
1040                 priv->dma_dir = PCI_DMA_FROMDEVICE;
1041                 priv->rx_headroom = 0;
1042         }
1043
1044         priv->num_frags = i;
1045         priv->rx_skb_size = eff_mtu;
1046         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1047
1048         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1049                eff_mtu, priv->num_frags);
1050         for (i = 0; i < priv->num_frags; i++) {
1051                 en_dbg(DRV,
1052                        priv,
1053                        "  frag:%d - size:%d stride:%d\n",
1054                        i,
1055                        priv->frag_info[i].frag_size,
1056                        priv->frag_info[i].frag_stride);
1057         }
1058 }
1059
1060 /* RSS related functions */
1061
1062 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1063                                  struct mlx4_en_rx_ring *ring,
1064                                  enum mlx4_qp_state *state,
1065                                  struct mlx4_qp *qp)
1066 {
1067         struct mlx4_en_dev *mdev = priv->mdev;
1068         struct mlx4_qp_context *context;
1069         int err = 0;
1070
1071         context = kmalloc(sizeof(*context), GFP_KERNEL);
1072         if (!context)
1073                 return -ENOMEM;
1074
1075         err = mlx4_qp_alloc(mdev->dev, qpn, qp);
1076         if (err) {
1077                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1078                 goto out;
1079         }
1080         qp->event = mlx4_en_sqp_event;
1081
1082         memset(context, 0, sizeof(*context));
1083         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1084                                 qpn, ring->cqn, -1, context);
1085         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1086
1087         /* Cancel FCS removal if FW allows */
1088         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1089                 context->param3 |= cpu_to_be32(1 << 29);
1090                 if (priv->dev->features & NETIF_F_RXFCS)
1091                         ring->fcs_del = 0;
1092                 else
1093                         ring->fcs_del = ETH_FCS_LEN;
1094         } else
1095                 ring->fcs_del = 0;
1096
1097         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1098         if (err) {
1099                 mlx4_qp_remove(mdev->dev, qp);
1100                 mlx4_qp_free(mdev->dev, qp);
1101         }
1102         mlx4_en_update_rx_prod_db(ring);
1103 out:
1104         kfree(context);
1105         return err;
1106 }
1107
1108 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1109 {
1110         int err;
1111         u32 qpn;
1112
1113         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1114                                     MLX4_RESERVE_A0_QP,
1115                                     MLX4_RES_USAGE_DRIVER);
1116         if (err) {
1117                 en_err(priv, "Failed reserving drop qpn\n");
1118                 return err;
1119         }
1120         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
1121         if (err) {
1122                 en_err(priv, "Failed allocating drop qp\n");
1123                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1124                 return err;
1125         }
1126
1127         return 0;
1128 }
1129
1130 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1131 {
1132         u32 qpn;
1133
1134         qpn = priv->drop_qp.qpn;
1135         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1136         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1137         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1138 }
1139
1140 /* Allocate rx qp's and configure them according to rss map */
1141 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1142 {
1143         struct mlx4_en_dev *mdev = priv->mdev;
1144         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1145         struct mlx4_qp_context context;
1146         struct mlx4_rss_context *rss_context;
1147         int rss_rings;
1148         void *ptr;
1149         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1150                         MLX4_RSS_TCP_IPV6);
1151         int i, qpn;
1152         int err = 0;
1153         int good_qps = 0;
1154         u8 flags;
1155
1156         en_dbg(DRV, priv, "Configuring rss steering\n");
1157
1158         flags = priv->rx_ring_num == 1 ? MLX4_RESERVE_A0_QP : 0;
1159         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1160                                     priv->rx_ring_num,
1161                                     &rss_map->base_qpn, flags,
1162                                     MLX4_RES_USAGE_DRIVER);
1163         if (err) {
1164                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1165                 return err;
1166         }
1167
1168         for (i = 0; i < priv->rx_ring_num; i++) {
1169                 qpn = rss_map->base_qpn + i;
1170                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1171                                             &rss_map->state[i],
1172                                             &rss_map->qps[i]);
1173                 if (err)
1174                         goto rss_err;
1175
1176                 ++good_qps;
1177         }
1178
1179         if (priv->rx_ring_num == 1) {
1180                 rss_map->indir_qp = &rss_map->qps[0];
1181                 priv->base_qpn = rss_map->indir_qp->qpn;
1182                 en_info(priv, "Optimized Non-RSS steering\n");
1183                 return 0;
1184         }
1185
1186         rss_map->indir_qp = kzalloc(sizeof(*rss_map->indir_qp), GFP_KERNEL);
1187         if (!rss_map->indir_qp) {
1188                 err = -ENOMEM;
1189                 goto rss_err;
1190         }
1191
1192         /* Configure RSS indirection qp */
1193         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, rss_map->indir_qp);
1194         if (err) {
1195                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1196                 goto qp_alloc_err;
1197         }
1198
1199         rss_map->indir_qp->event = mlx4_en_sqp_event;
1200         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1201                                 priv->rx_ring[0]->cqn, -1, &context);
1202
1203         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1204                 rss_rings = priv->rx_ring_num;
1205         else
1206                 rss_rings = priv->prof->rss_rings;
1207
1208         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1209                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1210         rss_context = ptr;
1211         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1212                                             (rss_map->base_qpn));
1213         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1214         if (priv->mdev->profile.udp_rss) {
1215                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1216                 rss_context->base_qpn_udp = rss_context->default_qpn;
1217         }
1218
1219         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1220                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1221                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1222         }
1223
1224         rss_context->flags = rss_mask;
1225         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1226         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1227                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1228         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1229                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1230                 memcpy(rss_context->rss_key, priv->rss_key,
1231                        MLX4_EN_RSS_KEY_SIZE);
1232         } else {
1233                 en_err(priv, "Unknown RSS hash function requested\n");
1234                 err = -EINVAL;
1235                 goto indir_err;
1236         }
1237
1238         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1239                                rss_map->indir_qp, &rss_map->indir_state);
1240         if (err)
1241                 goto indir_err;
1242
1243         return 0;
1244
1245 indir_err:
1246         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1247                        MLX4_QP_STATE_RST, NULL, 0, 0, rss_map->indir_qp);
1248         mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1249         mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1250 qp_alloc_err:
1251         kfree(rss_map->indir_qp);
1252         rss_map->indir_qp = NULL;
1253 rss_err:
1254         for (i = 0; i < good_qps; i++) {
1255                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1256                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1257                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1258                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1259         }
1260         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1261         return err;
1262 }
1263
1264 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1265 {
1266         struct mlx4_en_dev *mdev = priv->mdev;
1267         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1268         int i;
1269
1270         if (priv->rx_ring_num > 1) {
1271                 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1272                                MLX4_QP_STATE_RST, NULL, 0, 0,
1273                                rss_map->indir_qp);
1274                 mlx4_qp_remove(mdev->dev, rss_map->indir_qp);
1275                 mlx4_qp_free(mdev->dev, rss_map->indir_qp);
1276                 kfree(rss_map->indir_qp);
1277                 rss_map->indir_qp = NULL;
1278         }
1279
1280         for (i = 0; i < priv->rx_ring_num; i++) {
1281                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1282                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1283                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1284                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1285         }
1286         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1287 }