2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/vmalloc.h>
42 #include <linux/tcp.h>
44 #include <linux/ipv6.h>
45 #include <linux/moduleparam.h>
49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
50 struct mlx4_en_tx_ring **pring, u32 size,
51 u16 stride, int node, int queue_index)
53 struct mlx4_en_dev *mdev = priv->mdev;
54 struct mlx4_en_tx_ring *ring;
58 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
60 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
62 en_err(priv, "Failed allocating TX ring\n");
68 ring->size_mask = size - 1;
69 ring->sp_stride = stride;
70 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
72 tmp = size * sizeof(struct mlx4_en_tx_info);
73 ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node);
79 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
82 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
83 if (!ring->bounce_buf) {
84 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
85 if (!ring->bounce_buf) {
90 ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE);
92 /* Allocate HW buffers on provided NUMA node */
93 set_dev_node(&mdev->dev->persist->pdev->dev, node);
94 err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
95 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
97 en_err(priv, "Failed allocating hwq resources\n");
101 ring->buf = ring->sp_wqres.buf.direct.buf;
103 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
104 ring, ring->buf, ring->size, ring->buf_size,
105 (unsigned long long) ring->sp_wqres.buf.direct.map);
107 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
108 MLX4_RESERVE_ETH_BF_QP,
109 MLX4_RES_USAGE_DRIVER);
111 en_err(priv, "failed reserving qp for TX ring\n");
115 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp);
117 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
120 ring->sp_qp.event = mlx4_en_sqp_event;
122 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
124 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
125 ring->bf.uar = &mdev->priv_uar;
126 ring->bf.uar->map = mdev->uar_map;
127 ring->bf_enabled = false;
128 ring->bf_alloced = false;
129 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
131 ring->bf_alloced = true;
132 ring->bf_enabled = !!(priv->pflags &
133 MLX4_EN_PRIV_FLAGS_BLUEFLAME);
136 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
137 ring->queue_index = queue_index;
139 if (queue_index < priv->num_tx_rings_p_up)
140 cpumask_set_cpu(cpumask_local_spread(queue_index,
141 priv->mdev->dev->numa_node),
142 &ring->sp_affinity_mask);
148 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
150 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
152 kfree(ring->bounce_buf);
153 ring->bounce_buf = NULL;
155 kvfree(ring->tx_info);
156 ring->tx_info = NULL;
163 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
164 struct mlx4_en_tx_ring **pring)
166 struct mlx4_en_dev *mdev = priv->mdev;
167 struct mlx4_en_tx_ring *ring = *pring;
168 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
170 if (ring->bf_alloced)
171 mlx4_bf_free(mdev->dev, &ring->bf);
172 mlx4_qp_remove(mdev->dev, &ring->sp_qp);
173 mlx4_qp_free(mdev->dev, &ring->sp_qp);
174 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
175 mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
176 kfree(ring->bounce_buf);
177 ring->bounce_buf = NULL;
178 kvfree(ring->tx_info);
179 ring->tx_info = NULL;
184 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
185 struct mlx4_en_tx_ring *ring,
186 int cq, int user_prio)
188 struct mlx4_en_dev *mdev = priv->mdev;
193 ring->cons = 0xffffffff;
194 ring->last_nr_txbb = 1;
195 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
196 memset(ring->buf, 0, ring->buf_size);
197 ring->free_tx_desc = mlx4_en_free_tx_desc;
199 ring->sp_qp_state = MLX4_QP_STATE_RST;
200 ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8);
201 ring->mr_key = cpu_to_be32(mdev->mr.key);
203 mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn,
204 ring->sp_cqn, user_prio, &ring->sp_context);
205 if (ring->bf_alloced)
206 ring->sp_context.usr_page =
207 cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev,
208 ring->bf.uar->index));
210 err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context,
211 &ring->sp_qp, &ring->sp_qp_state);
212 if (!cpumask_empty(&ring->sp_affinity_mask))
213 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask,
219 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
220 struct mlx4_en_tx_ring *ring)
222 struct mlx4_en_dev *mdev = priv->mdev;
224 mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state,
225 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp);
228 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
230 return ring->prod - ring->cons > ring->full_size;
233 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
234 struct mlx4_en_tx_ring *ring, int index,
237 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
238 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
239 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
240 void *end = ring->buf + ring->buf_size;
241 __be32 *ptr = (__be32 *)tx_desc;
244 /* Optimize the common case when there are no wraparounds */
245 if (likely((void *)tx_desc +
246 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
247 /* Stamp the freed descriptor */
248 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
254 /* Stamp the freed descriptor */
255 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
259 if ((void *)ptr >= end) {
261 stamp ^= cpu_to_be32(0x80000000);
268 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
269 struct mlx4_en_tx_ring *ring,
270 int index, u64 timestamp,
273 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
274 struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
275 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
276 void *end = ring->buf + ring->buf_size;
277 struct sk_buff *skb = tx_info->skb;
278 int nr_maps = tx_info->nr_maps;
281 /* We do not touch skb here, so prefetch skb->users location
282 * to speedup consume_skb()
284 prefetchw(&skb->users);
286 if (unlikely(timestamp)) {
287 struct skb_shared_hwtstamps hwts;
289 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
290 skb_tstamp_tx(skb, &hwts);
295 dma_unmap_single(priv->ddev,
297 tx_info->map0_byte_count,
300 dma_unmap_page(priv->ddev,
302 tx_info->map0_byte_count,
304 /* Optimize the common case when there are no wraparounds */
305 if (likely((void *)tx_desc +
306 (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
307 for (i = 1; i < nr_maps; i++) {
309 dma_unmap_page(priv->ddev,
310 (dma_addr_t)be64_to_cpu(data->addr),
311 be32_to_cpu(data->byte_count),
315 if ((void *)data >= end)
316 data = ring->buf + ((void *)data - end);
318 for (i = 1; i < nr_maps; i++) {
320 /* Check for wraparound before unmapping */
321 if ((void *) data >= end)
323 dma_unmap_page(priv->ddev,
324 (dma_addr_t)be64_to_cpu(data->addr),
325 be32_to_cpu(data->byte_count),
330 napi_consume_skb(skb, napi_mode);
332 return tx_info->nr_txbb;
335 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
336 struct mlx4_en_tx_ring *ring,
337 int index, u64 timestamp,
340 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
341 struct mlx4_en_rx_alloc frame = {
342 .page = tx_info->page,
343 .dma = tx_info->map0_dma,
346 if (!napi_mode || !mlx4_en_rx_recycle(ring->recycle_ring, &frame)) {
347 dma_unmap_page(priv->ddev, tx_info->map0_dma,
348 PAGE_SIZE, priv->dma_dir);
349 put_page(tx_info->page);
352 return tx_info->nr_txbb;
355 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
357 struct mlx4_en_priv *priv = netdev_priv(dev);
360 /* Skip last polled descriptor */
361 ring->cons += ring->last_nr_txbb;
362 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
363 ring->cons, ring->prod);
365 if ((u32) (ring->prod - ring->cons) > ring->size) {
366 if (netif_msg_tx_err(priv))
367 en_warn(priv, "Tx consumer passed producer!\n");
371 while (ring->cons != ring->prod) {
372 ring->last_nr_txbb = ring->free_tx_desc(priv, ring,
373 ring->cons & ring->size_mask,
374 0, 0 /* Non-NAPI caller */);
375 ring->cons += ring->last_nr_txbb;
380 netdev_tx_reset_queue(ring->tx_queue);
383 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
388 static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe,
389 u16 cqe_index, struct mlx4_en_tx_ring *ring)
391 struct mlx4_en_dev *mdev = priv->mdev;
392 struct mlx4_en_tx_info *tx_info;
393 struct mlx4_en_tx_desc *tx_desc;
397 en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n",
398 ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome);
399 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe),
402 wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask;
403 tx_info = &ring->tx_info[wqe_index];
404 desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE;
405 en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn,
406 wqe_index, desc_size);
407 tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE);
408 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false);
410 if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state))
413 en_err(priv, "Scheduling port restart\n");
414 queue_work(mdev->workqueue, &priv->restart_task);
417 bool mlx4_en_process_tx_cq(struct net_device *dev,
418 struct mlx4_en_cq *cq, int napi_budget)
420 struct mlx4_en_priv *priv = netdev_priv(dev);
421 struct mlx4_cq *mcq = &cq->mcq;
422 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring];
423 struct mlx4_cqe *cqe;
424 u16 index, ring_index, stamp_index;
425 u32 txbbs_skipped = 0;
427 u32 cons_index = mcq->cons_index;
429 u32 size_mask = ring->size_mask;
430 struct mlx4_cqe *buf = cq->buf;
433 int factor = priv->cqe_factor;
435 int budget = priv->tx_work_limit;
439 if (unlikely(!priv->port_up))
442 netdev_txq_bql_complete_prefetchw(ring->tx_queue);
444 index = cons_index & size_mask;
445 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
446 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
447 ring_cons = ACCESS_ONCE(ring->cons);
448 ring_index = ring_cons & size_mask;
449 stamp_index = ring_index;
451 /* Process all completed CQEs */
452 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
453 cons_index & size) && (done < budget)) {
457 * make sure we read the CQE after we read the
462 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
463 MLX4_CQE_OPCODE_ERROR))
464 if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state))
465 mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index,
468 /* Skip over last polled CQE */
469 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
474 txbbs_skipped += last_nr_txbb;
475 ring_index = (ring_index + last_nr_txbb) & size_mask;
477 if (unlikely(ring->tx_info[ring_index].ts_requested))
478 timestamp = mlx4_en_get_cqe_ts(cqe);
480 /* free next descriptor */
481 last_nr_txbb = ring->free_tx_desc(
482 priv, ring, ring_index,
483 timestamp, napi_budget);
485 mlx4_en_stamp_wqe(priv, ring, stamp_index,
486 !!((ring_cons + txbbs_stamp) &
488 stamp_index = ring_index;
489 txbbs_stamp = txbbs_skipped;
491 bytes += ring->tx_info[ring_index].nr_bytes;
492 } while ((++done < budget) && (ring_index != new_index));
495 index = cons_index & size_mask;
496 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
500 * To prevent CQ overflow we first update CQ consumer and only then
503 mcq->cons_index = cons_index;
507 /* we want to dirty this cache line once */
508 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
509 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
511 if (cq->type == TX_XDP)
512 return done < budget;
514 netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
516 /* Wakeup Tx queue if this stopped, and ring is not full.
518 if (netif_tx_queue_stopped(ring->tx_queue) &&
519 !mlx4_en_is_tx_ring_full(ring)) {
520 netif_tx_wake_queue(ring->tx_queue);
524 return done < budget;
527 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
529 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
530 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
532 if (likely(priv->port_up))
533 napi_schedule_irqoff(&cq->napi);
535 mlx4_en_arm_cq(priv, cq);
538 /* TX CQ polling - called by NAPI */
539 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
541 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
542 struct net_device *dev = cq->dev;
543 struct mlx4_en_priv *priv = netdev_priv(dev);
546 clean_complete = mlx4_en_process_tx_cq(dev, cq, budget);
551 mlx4_en_arm_cq(priv, cq);
556 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
557 struct mlx4_en_tx_ring *ring,
559 unsigned int desc_size)
561 u32 copy = (ring->size - index) << LOG_TXBB_SIZE;
564 for (i = desc_size - copy - 4; i >= 0; i -= 4) {
565 if ((i & (TXBB_SIZE - 1)) == 0)
568 *((u32 *) (ring->buf + i)) =
569 *((u32 *) (ring->bounce_buf + copy + i));
572 for (i = copy - 4; i >= 4 ; i -= 4) {
573 if ((i & (TXBB_SIZE - 1)) == 0)
576 *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) =
577 *((u32 *) (ring->bounce_buf + i));
580 /* Return real descriptor location */
581 return ring->buf + (index << LOG_TXBB_SIZE);
584 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
586 * It seems strange we do not simply use skb_copy_bits().
587 * This would allow to inline all skbs iff skb->len <= inline_thold
589 * Note that caller already checked skb was not a gso packet
591 static bool is_inline(int inline_thold, const struct sk_buff *skb,
592 const struct skb_shared_info *shinfo,
597 if (skb->len > inline_thold || !inline_thold)
600 if (shinfo->nr_frags == 1) {
601 ptr = skb_frag_address_safe(&shinfo->frags[0]);
607 if (shinfo->nr_frags)
612 static int inline_size(const struct sk_buff *skb)
614 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
615 <= MLX4_INLINE_ALIGN)
616 return ALIGN(skb->len + CTRL_SIZE +
617 sizeof(struct mlx4_wqe_inline_seg), 16);
619 return ALIGN(skb->len + CTRL_SIZE + 2 *
620 sizeof(struct mlx4_wqe_inline_seg), 16);
623 static int get_real_size(const struct sk_buff *skb,
624 const struct skb_shared_info *shinfo,
625 struct net_device *dev,
626 int *lso_header_size,
630 struct mlx4_en_priv *priv = netdev_priv(dev);
633 if (shinfo->gso_size) {
635 if (skb->encapsulation)
636 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
638 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
639 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
640 ALIGN(*lso_header_size + 4, DS_SIZE);
641 if (unlikely(*lso_header_size != skb_headlen(skb))) {
642 /* We add a segment for the skb linear buffer only if
643 * it contains data */
644 if (*lso_header_size < skb_headlen(skb))
645 real_size += DS_SIZE;
647 if (netif_msg_tx_err(priv))
648 en_warn(priv, "Non-linear headers\n");
653 *lso_header_size = 0;
654 *inline_ok = is_inline(priv->prof->inline_thold, skb,
658 real_size = inline_size(skb);
660 real_size = CTRL_SIZE +
661 (shinfo->nr_frags + 1) * DS_SIZE;
667 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
668 const struct sk_buff *skb,
669 const struct skb_shared_info *shinfo,
672 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
673 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl);
674 unsigned int hlen = skb_headlen(skb);
676 if (skb->len <= spc) {
677 if (likely(skb->len >= MIN_PKT_LEN)) {
678 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
680 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
681 memset(((void *)(inl + 1)) + skb->len, 0,
682 MIN_PKT_LEN - skb->len);
684 skb_copy_from_linear_data(skb, inl + 1, hlen);
685 if (shinfo->nr_frags)
686 memcpy(((void *)(inl + 1)) + hlen, fragptr,
687 skb_frag_size(&shinfo->frags[0]));
690 inl->byte_count = cpu_to_be32(1 << 31 | spc);
692 skb_copy_from_linear_data(skb, inl + 1, hlen);
694 memcpy(((void *)(inl + 1)) + hlen,
695 fragptr, spc - hlen);
696 fragptr += spc - hlen;
698 inl = (void *) (inl + 1) + spc;
699 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
701 skb_copy_from_linear_data(skb, inl + 1, spc);
702 inl = (void *) (inl + 1) + spc;
703 skb_copy_from_linear_data_offset(skb, spc, inl + 1,
705 if (shinfo->nr_frags)
706 memcpy(((void *)(inl + 1)) + hlen - spc,
708 skb_frag_size(&shinfo->frags[0]));
712 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
716 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
717 void *accel_priv, select_queue_fallback_t fallback)
719 struct mlx4_en_priv *priv = netdev_priv(dev);
720 u16 rings_p_up = priv->num_tx_rings_p_up;
722 if (netdev_get_num_tc(dev))
723 return skb_tx_hash(dev, skb);
725 return fallback(dev, skb) % rings_p_up;
728 static void mlx4_bf_copy(void __iomem *dst, const void *src,
729 unsigned int bytecnt)
731 __iowrite64_copy(dst, src, bytecnt / 8);
734 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring)
737 /* Since there is no iowrite*_native() that writes the
738 * value as is, without byteswapping - using the one
739 * the doesn't do byteswapping in the relevant arch
742 #if defined(__LITTLE_ENDIAN)
748 ring->bf.uar->map + MLX4_SEND_DOORBELL);
751 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring,
752 struct mlx4_en_tx_desc *tx_desc,
753 union mlx4_wqe_qpn_vlan qpn_vlan,
754 int desc_size, int bf_index,
755 __be32 op_own, bool bf_ok,
758 tx_desc->ctrl.qpn_vlan = qpn_vlan;
761 op_own |= htonl((bf_index & 0xffff) << 8);
762 /* Ensure new descriptor hits memory
763 * before setting ownership of this descriptor to HW
766 tx_desc->ctrl.owner_opcode = op_own;
770 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
775 ring->bf.offset ^= ring->bf.buf_size;
777 /* Ensure new descriptor hits memory
778 * before setting ownership of this descriptor to HW
781 tx_desc->ctrl.owner_opcode = op_own;
783 mlx4_en_xmit_doorbell(ring);
789 static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv,
790 struct skb_shared_info *shinfo,
791 struct mlx4_wqe_data_seg *data,
795 struct mlx4_en_tx_info *tx_info)
797 struct device *ddev = priv->ddev;
802 /* Map fragments if any */
803 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
804 const struct skb_frag_struct *frag;
806 frag = &shinfo->frags[i_frag];
807 byte_count = skb_frag_size(frag);
808 dma = skb_frag_dma_map(ddev, frag,
811 if (dma_mapping_error(ddev, dma))
814 data->addr = cpu_to_be64(dma);
817 data->byte_count = cpu_to_be32(byte_count);
821 /* Map linear part if needed */
822 if (tx_info->linear) {
823 byte_count = skb_headlen(skb) - lso_header_size;
825 dma = dma_map_single(ddev, skb->data +
826 lso_header_size, byte_count,
828 if (dma_mapping_error(ddev, dma))
831 data->addr = cpu_to_be64(dma);
834 data->byte_count = cpu_to_be32(byte_count);
836 /* tx completion can avoid cache line miss for common cases */
837 tx_info->map0_dma = dma;
838 tx_info->map0_byte_count = byte_count;
843 en_err(priv, "DMA mapping error\n");
845 while (++i_frag < shinfo->nr_frags) {
847 dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr),
848 be32_to_cpu(data->byte_count),
855 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
857 struct skb_shared_info *shinfo = skb_shinfo(skb);
858 struct mlx4_en_priv *priv = netdev_priv(dev);
859 union mlx4_wqe_qpn_vlan qpn_vlan = {};
860 struct mlx4_en_tx_ring *ring;
861 struct mlx4_en_tx_desc *tx_desc;
862 struct mlx4_wqe_data_seg *data;
863 struct mlx4_en_tx_info *tx_info;
864 u32 __maybe_unused ring_cons;
872 void *fragptr = NULL;
880 tx_ind = skb_get_queue_mapping(skb);
881 ring = priv->tx_ring[TX][tx_ind];
883 if (unlikely(!priv->port_up))
886 /* fetch ring->cons far ahead before needing it to avoid stall */
887 ring_cons = ACCESS_ONCE(ring->cons);
889 real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
890 &inline_ok, &fragptr);
891 if (unlikely(!real_size))
894 /* Align descriptor to TXBB size */
895 desc_size = ALIGN(real_size, TXBB_SIZE);
896 nr_txbb = desc_size >> LOG_TXBB_SIZE;
897 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
898 if (netif_msg_tx_err(priv))
899 en_warn(priv, "Oversized header or SG list\n");
903 bf_ok = ring->bf_enabled;
904 if (skb_vlan_tag_present(skb)) {
907 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb));
908 vlan_proto = be16_to_cpu(skb->vlan_proto);
909 if (vlan_proto == ETH_P_8021AD)
910 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
911 else if (vlan_proto == ETH_P_8021Q)
912 qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
914 qpn_vlan.ins_vlan = 0;
918 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
920 /* Track current inflight packets for performance analysis */
921 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
922 (u32)(ring->prod - ring_cons - 1));
924 /* Packet is good - grab an index and transmit it */
925 index = ring->prod & ring->size_mask;
926 bf_index = ring->prod;
928 /* See if we have enough space for whole descriptor TXBB for setting
929 * SW ownership on next descriptor; if not, use a bounce buffer. */
930 if (likely(index + nr_txbb <= ring->size))
931 tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
933 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
938 /* Save skb in tx_info ring */
939 tx_info = &ring->tx_info[index];
941 tx_info->nr_txbb = nr_txbb;
943 if (!lso_header_size) {
944 data = &tx_desc->data;
945 data_offset = offsetof(struct mlx4_en_tx_desc, data);
947 int lso_align = ALIGN(lso_header_size + 4, DS_SIZE);
949 data = (void *)&tx_desc->lso + lso_align;
950 data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align;
953 /* valid only for none inline segments */
954 tx_info->data_offset = data_offset;
956 tx_info->inl = inline_ok;
958 tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok;
960 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
961 data += tx_info->nr_maps - 1;
964 if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb,
965 lso_header_size, ring->mr_key,
970 * For timestamping add flag to skb_shinfo and
971 * set flag for further reference
973 tx_info->ts_requested = 0;
974 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
975 shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
976 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
977 tx_info->ts_requested = 1;
980 /* Prepare ctrl segement apart opcode+ownership, which depends on
981 * whether LSO is used */
982 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
983 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
984 if (!skb->encapsulation)
985 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
986 MLX4_WQE_CTRL_TCP_UDP_CSUM);
988 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
992 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
995 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
996 * so that VFs and PF can communicate with each other
998 ethh = (struct ethhdr *)skb->data;
999 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
1000 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
1003 /* Handle LSO (TSO) packets */
1004 if (lso_header_size) {
1007 /* Mark opcode as LSO */
1008 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
1009 ((ring->prod & ring->size) ?
1010 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1012 /* Fill in the LSO prefix */
1013 tx_desc->lso.mss_hdr_size = cpu_to_be32(
1014 shinfo->gso_size << 16 | lso_header_size);
1017 * note that we already verified that it is linear */
1018 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
1020 ring->tso_packets++;
1022 i = shinfo->gso_segs;
1023 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
1026 /* Normal (Non LSO) packet */
1027 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1028 ((ring->prod & ring->size) ?
1029 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1030 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
1033 ring->bytes += tx_info->nr_bytes;
1034 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
1035 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
1038 build_inline_wqe(tx_desc, skb, shinfo, fragptr);
1040 if (skb->encapsulation) {
1048 ip.hdr = skb_inner_network_header(skb);
1049 proto = (ip.v4->version == 4) ? ip.v4->protocol :
1052 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP)
1053 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
1055 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
1058 ring->prod += nr_txbb;
1060 /* If we used a bounce buffer then copy descriptor back into place */
1061 if (unlikely(bounce))
1062 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
1064 skb_tx_timestamp(skb);
1066 /* Check available TXBBs And 2K spare for prefetch */
1067 stop_queue = mlx4_en_is_tx_ring_full(ring);
1068 if (unlikely(stop_queue)) {
1069 netif_tx_stop_queue(ring->tx_queue);
1070 ring->queue_stopped++;
1072 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
1074 real_size = (real_size / 16) & 0x3f;
1076 bf_ok &= desc_size <= MAX_BF && send_doorbell;
1079 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size);
1081 qpn_vlan.fence_size = real_size;
1083 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index,
1084 op_own, bf_ok, send_doorbell);
1086 if (unlikely(stop_queue)) {
1087 /* If queue was emptied after the if (stop_queue) , and before
1088 * the netif_tx_stop_queue() - need to wake the queue,
1089 * or else it will remain stopped forever.
1090 * Need a memory barrier to make sure ring->cons was not
1091 * updated before queue was stopped.
1095 ring_cons = ACCESS_ONCE(ring->cons);
1096 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1097 netif_tx_wake_queue(ring->tx_queue);
1101 return NETDEV_TX_OK;
1106 dev_kfree_skb_any(skb);
1107 return NETDEV_TX_OK;
1110 #define MLX4_EN_XDP_TX_NRTXBB 1
1111 #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \
1114 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
1115 struct mlx4_en_rx_alloc *frame,
1116 struct net_device *dev, unsigned int length,
1117 int tx_ind, bool *doorbell_pending)
1119 struct mlx4_en_priv *priv = netdev_priv(dev);
1120 union mlx4_wqe_qpn_vlan qpn_vlan = {};
1121 struct mlx4_en_tx_desc *tx_desc;
1122 struct mlx4_en_tx_info *tx_info;
1123 struct mlx4_wqe_data_seg *data;
1124 struct mlx4_en_tx_ring *ring;
1129 if (unlikely(!priv->port_up))
1132 ring = priv->tx_ring[TX_XDP][tx_ind];
1134 if (unlikely(mlx4_en_is_tx_ring_full(ring)))
1137 index = ring->prod & ring->size_mask;
1138 tx_info = &ring->tx_info[index];
1140 /* Track current inflight packets for performance analysis */
1141 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
1142 (u32)(ring->prod - READ_ONCE(ring->cons) - 1));
1144 tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
1145 data = &tx_desc->data;
1149 tx_info->page = frame->page;
1151 tx_info->map0_dma = dma;
1152 tx_info->map0_byte_count = PAGE_SIZE;
1153 tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB;
1154 tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN);
1155 tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data);
1156 tx_info->ts_requested = 0;
1157 tx_info->nr_maps = 1;
1158 tx_info->linear = 1;
1161 dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset,
1162 length, PCI_DMA_TODEVICE);
1164 data->addr = cpu_to_be64(dma + frame->page_offset);
1165 data->lkey = ring->mr_key;
1167 data->byte_count = cpu_to_be32(length);
1169 /* tx completion can avoid cache line miss for common cases */
1170 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
1172 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1173 ((ring->prod & ring->size) ?
1174 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1177 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length);
1179 ring->prod += MLX4_EN_XDP_TX_NRTXBB;
1181 qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ;
1183 mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, TXBB_SIZE, 0,
1184 op_own, false, false);
1185 *doorbell_pending = true;
1187 return NETDEV_TX_OK;
1190 rx_ring->xdp_tx_full++;
1191 *doorbell_pending = true;
1193 return NETDEV_TX_BUSY;