drivers/net/ethernet/mellanox/mlx4/eq.c

   1 /*
   2  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/interrupt.h>
  35 #include <linux/slab.h>
  36 #include <linux/export.h>
  37 #include <linux/mm.h>
  38 #include <linux/dma-mapping.h>
  39
  40 #include <linux/mlx4/cmd.h>
  41 #include <linux/cpu_rmap.h>
  42
  43 #include "mlx4.h"
  44 #include "fw.h"
  45
  46 enum {
  47         MLX4_IRQNAME_SIZE       = 32
  48 };
  49
  50 enum {
  51         MLX4_NUM_ASYNC_EQE      = 0x100,
  52         MLX4_NUM_SPARE_EQE      = 0x80,
  53         MLX4_EQ_ENTRY_SIZE      = 0x20
  54 };
  55
  56 #define MLX4_EQ_STATUS_OK          ( 0 << 28)
  57 #define MLX4_EQ_STATUS_WRITE_FAIL  (10 << 28)
  58 #define MLX4_EQ_OWNER_SW           ( 0 << 24)
  59 #define MLX4_EQ_OWNER_HW           ( 1 << 24)
  60 #define MLX4_EQ_FLAG_EC            ( 1 << 18)
  61 #define MLX4_EQ_FLAG_OI            ( 1 << 17)
  62 #define MLX4_EQ_STATE_ARMED        ( 9 <<  8)
  63 #define MLX4_EQ_STATE_FIRED        (10 <<  8)
  64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 <<  8)
  65
  66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG)           | \
  67                                (1ull << MLX4_EVENT_TYPE_COMM_EST)           | \
  68                                (1ull << MLX4_EVENT_TYPE_SQ_DRAINED)         | \
  69                                (1ull << MLX4_EVENT_TYPE_CQ_ERROR)           | \
  70                                (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  71                                (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR)    | \
  72                                (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED)    | \
  73                                (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  74                                (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  75                                (1ull << MLX4_EVENT_TYPE_PORT_CHANGE)        | \
  76                                (1ull << MLX4_EVENT_TYPE_ECC_DETECT)         | \
  77                                (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  78                                (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE)    | \
  79                                (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT)          | \
  80                                (1ull << MLX4_EVENT_TYPE_CMD)                | \
  81                                (1ull << MLX4_EVENT_TYPE_OP_REQUIRED)        | \
  82                                (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL)       | \
  83                                (1ull << MLX4_EVENT_TYPE_FLR_EVENT)          | \
  84                                (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
  85
  86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
  87 {
  88         u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
  89         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
  90                 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
  91         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
  92                 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT);
  93
  94         return async_ev_mask;
  95 }
  96
  97 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
  98 {
  99         __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
 100                                                req_not << 31),
 101                      eq->doorbell);
 102         /* We still want ordering, just not swabbing, so add a barrier */
 103         mb();
 104 }
 105
 106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
 107                                 u8 eqe_size)
 108 {
 109         /* (entry & (eq->nent - 1)) gives us a cyclic array */
 110         unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
 111         /* CX3 is capable of extending the EQE from 32 to 64 bytes with
 112          * strides of 64B,128B and 256B.
 113          * When 64B EQE is used, the first (in the lower addresses)
 114          * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
 115          * contain the legacy EQE information.
 116          * In all other cases, the first 32B contains the legacy EQE info.
 117          */
 118         return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
 119 }
 120
 121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
 122 {
 123         struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
 124         return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
 125 }
 126
 127 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
 128 {
 129         struct mlx4_eqe *eqe =
 130                 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
 131         return (!!(eqe->owner & 0x80) ^
 132                 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
 133                 eqe : NULL;
 134 }
 135
 136 void mlx4_gen_slave_eqe(struct work_struct *work)
 137 {
 138         struct mlx4_mfunc_master_ctx *master =
 139                 container_of(work, struct mlx4_mfunc_master_ctx,
 140                              slave_event_work);
 141         struct mlx4_mfunc *mfunc =
 142                 container_of(master, struct mlx4_mfunc, master);
 143         struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
 144         struct mlx4_dev *dev = &priv->dev;
 145         struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
 146         struct mlx4_eqe *eqe;
 147         u8 slave;
 148         int i, phys_port, slave_port;
 149
 150         for (eqe = next_slave_event_eqe(slave_eq); eqe;
 151               eqe = next_slave_event_eqe(slave_eq)) {
 152                 slave = eqe->slave_id;
 153
 154                 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE &&
 155                     eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN &&
 156                     mlx4_is_bonded(dev)) {
 157                         struct mlx4_port_cap port_cap;
 158
 159                         if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state)
 160                                 goto consume;
 161
 162                         if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state)
 163                                 goto consume;
 164                 }
 165                 /* All active slaves need to receive the event */
 166                 if (slave == ALL_SLAVES) {
 167                         for (i = 0; i <= dev->persist->num_vfs; i++) {
 168                                 phys_port = 0;
 169                                 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT &&
 170                                     eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) {
 171                                         phys_port  = eqe->event.port_mgmt_change.port;
 172                                         slave_port = mlx4_phys_to_slave_port(dev, i, phys_port);
 173                                         if (slave_port < 0) /* VF doesn't have this port */
 174                                                 continue;
 175                                         eqe->event.port_mgmt_change.port = slave_port;
 176                                 }
 177                                 if (mlx4_GEN_EQE(dev, i, eqe))
 178                                         mlx4_warn(dev, "Failed to generate event for slave %d\n",
 179                                                   i);
 180                                 if (phys_port)
 181                                         eqe->event.port_mgmt_change.port = phys_port;
 182                         }
 183                 } else {
 184                         if (mlx4_GEN_EQE(dev, slave, eqe))
 185                                 mlx4_warn(dev, "Failed to generate event for slave %d\n",
 186                                           slave);
 187                 }
 188 consume:
 189                 ++slave_eq->cons;
 190         }
 191 }
 192
 193
 194 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
 195 {
 196         struct mlx4_priv *priv = mlx4_priv(dev);
 197         struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
 198         struct mlx4_eqe *s_eqe;
 199         unsigned long flags;
 200
 201         spin_lock_irqsave(&slave_eq->event_lock, flags);
 202         s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
 203         if ((!!(s_eqe->owner & 0x80)) ^
 204             (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
 205                 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n",
 206                           slave);
 207                 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
 208                 return;
 209         }
 210
 211         memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1);
 212         s_eqe->slave_id = slave;
 213         /* ensure all information is written before setting the ownersip bit */
 214         dma_wmb();
 215         s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
 216         ++slave_eq->prod;
 217
 218         queue_work(priv->mfunc.master.comm_wq,
 219                    &priv->mfunc.master.slave_event_work);
 220         spin_unlock_irqrestore(&slave_eq->event_lock, flags);
 221 }
 222
 223 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
 224                              struct mlx4_eqe *eqe)
 225 {
 226         struct mlx4_priv *priv = mlx4_priv(dev);
 227
 228         if (slave < 0 || slave > dev->persist->num_vfs ||
 229             slave == dev->caps.function ||
 230             !priv->mfunc.master.slave_state[slave].active)
 231                 return;
 232
 233         slave_event(dev, slave, eqe);
 234 }
 235
 236 #if defined(CONFIG_SMP)
 237 static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec)
 238 {
 239         int hint_err;
 240         struct mlx4_dev *dev = &priv->dev;
 241         struct mlx4_eq *eq = &priv->eq_table.eq[vec];
 242
 243         if (!cpumask_available(eq->affinity_mask) ||
 244             cpumask_empty(eq->affinity_mask))
 245                 return;
 246
 247         hint_err = irq_set_affinity_hint(eq->irq, eq->affinity_mask);
 248         if (hint_err)
 249                 mlx4_warn(dev, "irq_set_affinity_hint failed, err %d\n", hint_err);
 250 }
 251 #endif
 252
 253 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
 254 {
 255         struct mlx4_eqe eqe;
 256
 257         struct mlx4_priv *priv = mlx4_priv(dev);
 258         struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
 259
 260         if (!s_slave->active)
 261                 return 0;
 262
 263         memset(&eqe, 0, sizeof(eqe));
 264
 265         eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
 266         eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
 267         eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
 268
 269         return mlx4_GEN_EQE(dev, slave, &eqe);
 270 }
 271 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
 272
 273 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
 274 {
 275         struct mlx4_eqe eqe;
 276
 277         /*don't send if we don't have the that slave */
 278         if (dev->persist->num_vfs < slave)
 279                 return 0;
 280         memset(&eqe, 0, sizeof(eqe));
 281
 282         eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
 283         eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
 284         eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
 285
 286         return mlx4_GEN_EQE(dev, slave, &eqe);
 287 }
 288 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
 289
 290 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
 291                                    u8 port_subtype_change)
 292 {
 293         struct mlx4_eqe eqe;
 294         u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port);
 295
 296         /*don't send if we don't have the that slave */
 297         if (dev->persist->num_vfs < slave)
 298                 return 0;
 299         memset(&eqe, 0, sizeof(eqe));
 300
 301         eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
 302         eqe.subtype = port_subtype_change;
 303         eqe.event.port_change.port = cpu_to_be32(slave_port << 28);
 304
 305         mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
 306                  port_subtype_change, slave, port);
 307         return mlx4_GEN_EQE(dev, slave, &eqe);
 308 }
 309 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
 310
 311 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
 312 {
 313         struct mlx4_priv *priv = mlx4_priv(dev);
 314         struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
 315         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
 316
 317         if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
 318             port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
 319                 pr_err("%s: Error: asking for slave:%d, port:%d\n",
 320                        __func__, slave, port);
 321                 return SLAVE_PORT_DOWN;
 322         }
 323         return s_state[slave].port_state[port];
 324 }
 325 EXPORT_SYMBOL(mlx4_get_slave_port_state);
 326
 327 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
 328                                      enum slave_port_state state)
 329 {
 330         struct mlx4_priv *priv = mlx4_priv(dev);
 331         struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
 332         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
 333
 334         if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
 335             port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
 336                 pr_err("%s: Error: asking for slave:%d, port:%d\n",
 337                        __func__, slave, port);
 338                 return -1;
 339         }
 340         s_state[slave].port_state[port] = state;
 341
 342         return 0;
 343 }
 344
 345 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
 346 {
 347         int i;
 348         enum slave_port_gen_event gen_event;
 349         struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
 350                                                                           port);
 351
 352         for (i = 0; i < dev->persist->num_vfs + 1; i++)
 353                 if (test_bit(i, slaves_pport.slaves))
 354                         set_and_calc_slave_port_state(dev, i, port,
 355                                                       event, &gen_event);
 356 }
 357 /**************************************************************************
 358         The function get as input the new event to that port,
 359         and according to the prev state change the slave's port state.
 360         The events are:
 361                 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
 362                 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
 363                 MLX4_PORT_STATE_IB_EVENT_GID_VALID
 364                 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
 365 ***************************************************************************/
 366 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
 367                                   u8 port, int event,
 368                                   enum slave_port_gen_event *gen_event)
 369 {
 370         struct mlx4_priv *priv = mlx4_priv(dev);
 371         struct mlx4_slave_state *ctx = NULL;
 372         unsigned long flags;
 373         int ret = -1;
 374         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
 375         enum slave_port_state cur_state =
 376                 mlx4_get_slave_port_state(dev, slave, port);
 377
 378         *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
 379
 380         if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
 381             port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
 382                 pr_err("%s: Error: asking for slave:%d, port:%d\n",
 383                        __func__, slave, port);
 384                 return ret;
 385         }
 386
 387         ctx = &priv->mfunc.master.slave_state[slave];
 388         spin_lock_irqsave(&ctx->lock, flags);
 389
 390         switch (cur_state) {
 391         case SLAVE_PORT_DOWN:
 392                 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
 393                         mlx4_set_slave_port_state(dev, slave, port,
 394                                                   SLAVE_PENDING_UP);
 395                 break;
 396         case SLAVE_PENDING_UP:
 397                 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
 398                         mlx4_set_slave_port_state(dev, slave, port,
 399                                                   SLAVE_PORT_DOWN);
 400                 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
 401                         mlx4_set_slave_port_state(dev, slave, port,
 402                                                   SLAVE_PORT_UP);
 403                         *gen_event = SLAVE_PORT_GEN_EVENT_UP;
 404                 }
 405                 break;
 406         case SLAVE_PORT_UP:
 407                 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
 408                         mlx4_set_slave_port_state(dev, slave, port,
 409                                                   SLAVE_PORT_DOWN);
 410                         *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
 411                 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
 412                                 event) {
 413                         mlx4_set_slave_port_state(dev, slave, port,
 414                                                   SLAVE_PENDING_UP);
 415                         *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
 416                 }
 417                 break;
 418         default:
 419                 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n",
 420                        __func__, slave, port);
 421                 goto out;
 422         }
 423         ret = mlx4_get_slave_port_state(dev, slave, port);
 424
 425 out:
 426         spin_unlock_irqrestore(&ctx->lock, flags);
 427         return ret;
 428 }
 429
 430 EXPORT_SYMBOL(set_and_calc_slave_port_state);
 431
 432 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
 433 {
 434         struct mlx4_eqe eqe;
 435
 436         memset(&eqe, 0, sizeof(eqe));
 437
 438         eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
 439         eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
 440         eqe.event.port_mgmt_change.port = port;
 441         eqe.event.port_mgmt_change.params.port_info.changed_attr =
 442                 cpu_to_be32((u32) attr);
 443
 444         slave_event(dev, ALL_SLAVES, &eqe);
 445         return 0;
 446 }
 447 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
 448
 449 void mlx4_master_handle_slave_flr(struct work_struct *work)
 450 {
 451         struct mlx4_mfunc_master_ctx *master =
 452                 container_of(work, struct mlx4_mfunc_master_ctx,
 453                              slave_flr_event_work);
 454         struct mlx4_mfunc *mfunc =
 455                 container_of(master, struct mlx4_mfunc, master);
 456         struct mlx4_priv *priv =
 457                 container_of(mfunc, struct mlx4_priv, mfunc);
 458         struct mlx4_dev *dev = &priv->dev;
 459         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
 460         int i;
 461         int err;
 462         unsigned long flags;
 463
 464         mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
 465
 466         for (i = 0 ; i < dev->num_slaves; i++) {
 467
 468                 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
 469                         mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n",
 470                                  i);
 471                         /* In case of 'Reset flow' FLR can be generated for
 472                          * a slave before mlx4_load_one is done.
 473                          * make sure interface is up before trying to delete
 474                          * slave resources which weren't allocated yet.
 475                          */
 476                         if (dev->persist->interface_state &
 477                             MLX4_INTERFACE_STATE_UP)
 478                                 mlx4_delete_all_resources_for_slave(dev, i);
 479                         /*return the slave to running mode*/
 480                         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
 481                         slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
 482                         slave_state[i].is_slave_going_down = 0;
 483                         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
 484                         /*notify the FW:*/
 485                         err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
 486                                        MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 487                         if (err)
 488                                 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n",
 489                                           i);
 490                 }
 491         }
 492 }
 493
 494 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
 495 {
 496         struct mlx4_priv *priv = mlx4_priv(dev);
 497         struct mlx4_eqe *eqe;
 498         int cqn;
 499         int eqes_found = 0;
 500         int set_ci = 0;
 501         int port;
 502         int slave = 0;
 503         int ret;
 504         u32 flr_slave;
 505         u8 update_slave_state;
 506         int i;
 507         enum slave_port_gen_event gen_event;
 508         unsigned long flags;
 509         struct mlx4_vport_state *s_info;
 510         int eqe_size = dev->caps.eqe_size;
 511
 512         while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
 513                 /*
 514                  * Make sure we read EQ entry contents after we've
 515                  * checked the ownership bit.
 516                  */
 517                 dma_rmb();
 518
 519                 switch (eqe->type) {
 520                 case MLX4_EVENT_TYPE_COMP:
 521                         cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
 522                         mlx4_cq_completion(dev, cqn);
 523                         break;
 524
 525                 case MLX4_EVENT_TYPE_PATH_MIG:
 526                 case MLX4_EVENT_TYPE_COMM_EST:
 527                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 528                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 529                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 530                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 531                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 532                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 533                         mlx4_dbg(dev, "event %d arrived\n", eqe->type);
 534                         if (mlx4_is_master(dev)) {
 535                                 /* forward only to slave owning the QP */
 536                                 ret = mlx4_get_slave_from_resource_id(dev,
 537                                                 RES_QP,
 538                                                 be32_to_cpu(eqe->event.qp.qpn)
 539                                                 & 0xffffff, &slave);
 540                                 if (ret && ret != -ENOENT) {
 541                                         mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
 542                                                  eqe->type, eqe->subtype,
 543                                                  eq->eqn, eq->cons_index, ret);
 544                                         break;
 545                                 }
 546
 547                                 if (!ret && slave != dev->caps.function) {
 548                                         mlx4_slave_event(dev, slave, eqe);
 549                                         break;
 550                                 }
 551
 552                         }
 553                         mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
 554                                       0xffffff, eqe->type);
 555                         break;
 556
 557                 case MLX4_EVENT_TYPE_SRQ_LIMIT:
 558                         mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n",
 559                                  __func__, be32_to_cpu(eqe->event.srq.srqn),
 560                                  eq->eqn);
 561                 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
 562                         if (mlx4_is_master(dev)) {
 563                                 /* forward only to slave owning the SRQ */
 564                                 ret = mlx4_get_slave_from_resource_id(dev,
 565                                                 RES_SRQ,
 566                                                 be32_to_cpu(eqe->event.srq.srqn)
 567                                                 & 0xffffff,
 568                                                 &slave);
 569                                 if (ret && ret != -ENOENT) {
 570                                         mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
 571                                                   eqe->type, eqe->subtype,
 572                                                   eq->eqn, eq->cons_index, ret);
 573                                         break;
 574                                 }
 575                                 if (eqe->type ==
 576                                     MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
 577                                         mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
 578                                                   __func__, slave,
 579                                                   be32_to_cpu(eqe->event.srq.srqn),
 580                                                   eqe->type, eqe->subtype);
 581
 582                                 if (!ret && slave != dev->caps.function) {
 583                                         if (eqe->type ==
 584                                             MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
 585                                                 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
 586                                                           __func__, eqe->type,
 587                                                           eqe->subtype, slave);
 588                                         mlx4_slave_event(dev, slave, eqe);
 589                                         break;
 590                                 }
 591                         }
 592                         mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
 593                                        0xffffff, eqe->type);
 594                         break;
 595
 596                 case MLX4_EVENT_TYPE_CMD:
 597                         mlx4_cmd_event(dev,
 598                                        be16_to_cpu(eqe->event.cmd.token),
 599                                        eqe->event.cmd.status,
 600                                        be64_to_cpu(eqe->event.cmd.out_param));
 601                         break;
 602
 603                 case MLX4_EVENT_TYPE_PORT_CHANGE: {
 604                         struct mlx4_slaves_pport slaves_port;
 605                         port = be32_to_cpu(eqe->event.port_change.port) >> 28;
 606                         slaves_port = mlx4_phys_to_slaves_pport(dev, port);
 607                         if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
 608                                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
 609                                                     port);
 610                                 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
 611                                 if (!mlx4_is_master(dev))
 612                                         break;
 613                                 for (i = 0; i < dev->persist->num_vfs + 1;
 614                                      i++) {
 615                                         int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port);
 616
 617                                         if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev))
 618                                                 continue;
 619                                         if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
 620                                                 if (i == mlx4_master_func_num(dev))
 621                                                         continue;
 622                                                 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
 623                                                          __func__, i, port);
 624                                                 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
 625                                                 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
 626                                                         eqe->event.port_change.port =
 627                                                                 cpu_to_be32(
 628                                                                 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
 629                                                                 | (reported_port << 28));
 630                                                         mlx4_slave_event(dev, i, eqe);
 631                                                 }
 632                                         } else {  /* IB port */
 633                                                 set_and_calc_slave_port_state(dev, i, port,
 634                                                                               MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
 635                                                                               &gen_event);
 636                                                 /*we can be in pending state, then do not send port_down event*/
 637                                                 if (SLAVE_PORT_GEN_EVENT_DOWN ==  gen_event) {
 638                                                         if (i == mlx4_master_func_num(dev))
 639                                                                 continue;
 640                                                         eqe->event.port_change.port =
 641                                                                 cpu_to_be32(
 642                                                                 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
 643                                                                 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
 644                                                         mlx4_slave_event(dev, i, eqe);
 645                                                 }
 646                                         }
 647                                 }
 648                         } else {
 649                                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
 650
 651                                 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
 652
 653                                 if (!mlx4_is_master(dev))
 654                                         break;
 655                                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
 656                                         for (i = 0;
 657                                              i < dev->persist->num_vfs + 1;
 658                                              i++) {
 659                                                 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port);
 660
 661                                                 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev))
 662                                                         continue;
 663                                                 if (i == mlx4_master_func_num(dev))
 664                                                         continue;
 665                                                 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
 666                                                 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
 667                                                         eqe->event.port_change.port =
 668                                                                 cpu_to_be32(
 669                                                                 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
 670                                                                 | (reported_port << 28));
 671                                                         mlx4_slave_event(dev, i, eqe);
 672                                                 }
 673                                         }
 674                                 else /* IB port */
 675                                         /* port-up event will be sent to a slave when the
 676                                          * slave's alias-guid is set. This is done in alias_GUID.c
 677                                          */
 678                                         set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
 679                         }
 680                         break;
 681                 }
 682
 683                 case MLX4_EVENT_TYPE_CQ_ERROR:
 684                         mlx4_warn(dev, "CQ %s on CQN %06x\n",
 685                                   eqe->event.cq_err.syndrome == 1 ?
 686                                   "overrun" : "access violation",
 687                                   be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
 688                         if (mlx4_is_master(dev)) {
 689                                 ret = mlx4_get_slave_from_resource_id(dev,
 690                                         RES_CQ,
 691                                         be32_to_cpu(eqe->event.cq_err.cqn)
 692                                         & 0xffffff, &slave);
 693                                 if (ret && ret != -ENOENT) {
 694                                         mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
 695                                                  eqe->type, eqe->subtype,
 696                                                  eq->eqn, eq->cons_index, ret);
 697                                         break;
 698                                 }
 699
 700                                 if (!ret && slave != dev->caps.function) {
 701                                         mlx4_slave_event(dev, slave, eqe);
 702                                         break;
 703                                 }
 704                         }
 705                         mlx4_cq_event(dev,
 706                                       be32_to_cpu(eqe->event.cq_err.cqn)
 707                                       & 0xffffff,
 708                                       eqe->type);
 709                         break;
 710
 711                 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
 712                         mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
 713                         break;
 714
 715                 case MLX4_EVENT_TYPE_OP_REQUIRED:
 716                         atomic_inc(&priv->opreq_count);
 717                         /* FW commands can't be executed from interrupt context
 718                          * working in deferred task
 719                          */
 720                         queue_work(mlx4_wq, &priv->opreq_task);
 721                         break;
 722
 723                 case MLX4_EVENT_TYPE_COMM_CHANNEL:
 724                         if (!mlx4_is_master(dev)) {
 725                                 mlx4_warn(dev, "Received comm channel event for non master device\n");
 726                                 break;
 727                         }
 728                         memcpy(&priv->mfunc.master.comm_arm_bit_vector,
 729                                eqe->event.comm_channel_arm.bit_vec,
 730                                sizeof(eqe->event.comm_channel_arm.bit_vec));
 731                         queue_work(priv->mfunc.master.comm_wq,
 732                                    &priv->mfunc.master.comm_work);
 733                         break;
 734
 735                 case MLX4_EVENT_TYPE_FLR_EVENT:
 736                         flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
 737                         if (!mlx4_is_master(dev)) {
 738                                 mlx4_warn(dev, "Non-master function received FLR event\n");
 739                                 break;
 740                         }
 741
 742                         mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
 743
 744                         if (flr_slave >= dev->num_slaves) {
 745                                 mlx4_warn(dev,
 746                                           "Got FLR for unknown function: %d\n",
 747                                           flr_slave);
 748                                 update_slave_state = 0;
 749                         } else
 750                                 update_slave_state = 1;
 751
 752                         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
 753                         if (update_slave_state) {
 754                                 priv->mfunc.master.slave_state[flr_slave].active = false;
 755                                 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
 756                                 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
 757                         }
 758                         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
 759                         mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN,
 760                                             flr_slave);
 761                         queue_work(priv->mfunc.master.comm_wq,
 762                                    &priv->mfunc.master.slave_flr_event_work);
 763                         break;
 764
 765                 case MLX4_EVENT_TYPE_FATAL_WARNING:
 766                         if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
 767                                 if (mlx4_is_master(dev))
 768                                         for (i = 0; i < dev->num_slaves; i++) {
 769                                                 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n",
 770                                                          __func__, i);
 771                                                 if (i == dev->caps.function)
 772                                                         continue;
 773                                                 mlx4_slave_event(dev, i, eqe);
 774                                         }
 775                                 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n",
 776                                          be16_to_cpu(eqe->event.warming.warning_threshold),
 777                                          be16_to_cpu(eqe->event.warming.current_temperature));
 778                         } else
 779                                 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
 780                                           eqe->type, eqe->subtype, eq->eqn,
 781                                           eq->cons_index, eqe->owner, eq->nent,
 782                                           eqe->slave_id,
 783                                           !!(eqe->owner & 0x80) ^
 784                                           !!(eq->cons_index & eq->nent) ? "HW" : "SW");
 785
 786                         break;
 787
 788                 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
 789                         mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
 790                                             (unsigned long) eqe);
 791                         break;
 792
 793                 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT:
 794                         switch (eqe->subtype) {
 795                         case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE:
 796                                 mlx4_warn(dev, "Bad cable detected on port %u\n",
 797                                           eqe->event.bad_cable.port);
 798                                 break;
 799                         case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE:
 800                                 mlx4_warn(dev, "Unsupported cable detected\n");
 801                                 break;
 802                         default:
 803                                 mlx4_dbg(dev,
 804                                          "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n",
 805                                          eqe->type, eqe->subtype, eq->eqn,
 806                                          eq->cons_index, eqe->owner, eq->nent,
 807                                          !!(eqe->owner & 0x80) ^
 808                                          !!(eq->cons_index & eq->nent) ? "HW" : "SW");
 809                                 break;
 810                         }
 811                         break;
 812
 813                 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
 814                 case MLX4_EVENT_TYPE_ECC_DETECT:
 815                 default:
 816                         mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
 817                                   eqe->type, eqe->subtype, eq->eqn,
 818                                   eq->cons_index, eqe->owner, eq->nent,
 819                                   eqe->slave_id,
 820                                   !!(eqe->owner & 0x80) ^
 821                                   !!(eq->cons_index & eq->nent) ? "HW" : "SW");
 822                         break;
 823                 };
 824
 825                 ++eq->cons_index;
 826                 eqes_found = 1;
 827                 ++set_ci;
 828
 829                 /*
 830                  * The HCA will think the queue has overflowed if we
 831                  * don't tell it we've been processing events.  We
 832                  * create our EQs with MLX4_NUM_SPARE_EQE extra
 833                  * entries, so we must update our consumer index at
 834                  * least that often.
 835                  */
 836                 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
 837                         eq_set_ci(eq, 0);
 838                         set_ci = 0;
 839                 }
 840         }
 841
 842         eq_set_ci(eq, 1);
 843
 844         return eqes_found;
 845 }
 846
 847 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
 848 {
 849         struct mlx4_dev *dev = dev_ptr;
 850         struct mlx4_priv *priv = mlx4_priv(dev);
 851         int work = 0;
 852         int i;
 853
 854         writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
 855
 856         for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
 857                 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
 858
 859         return IRQ_RETVAL(work);
 860 }
 861
 862 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
 863 {
 864         struct mlx4_eq  *eq  = eq_ptr;
 865         struct mlx4_dev *dev = eq->dev;
 866
 867         mlx4_eq_int(dev, eq);
 868
 869         /* MSI-X vectors always belong to us */
 870         return IRQ_HANDLED;
 871 }
 872
 873 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
 874                         struct mlx4_vhcr *vhcr,
 875                         struct mlx4_cmd_mailbox *inbox,
 876                         struct mlx4_cmd_mailbox *outbox,
 877                         struct mlx4_cmd_info *cmd)
 878 {
 879         struct mlx4_priv *priv = mlx4_priv(dev);
 880         struct mlx4_slave_event_eq_info *event_eq =
 881                 priv->mfunc.master.slave_state[slave].event_eq;
 882         u32 in_modifier = vhcr->in_modifier;
 883         u32 eqn = in_modifier & 0x3FF;
 884         u64 in_param =  vhcr->in_param;
 885         int err = 0;
 886         int i;
 887
 888         if (slave == dev->caps.function)
 889                 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
 890                                0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
 891                                MLX4_CMD_NATIVE);
 892         if (!err)
 893                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
 894                         if (in_param & (1LL << i))
 895                                 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
 896
 897         return err;
 898 }
 899
 900 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
 901                         int eq_num)
 902 {
 903         return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
 904                         0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
 905                         MLX4_CMD_WRAPPED);
 906 }
 907
 908 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 909                          int eq_num)
 910 {
 911         return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
 912                         MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
 913                         MLX4_CMD_WRAPPED);
 914 }
 915
 916 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev,  int eq_num)
 917 {
 918         return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
 919                         MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 920 }
 921
 922 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
 923 {
 924         /*
 925          * Each UAR holds 4 EQ doorbells.  To figure out how many UARs
 926          * we need to map, take the difference of highest index and
 927          * the lowest index we'll use and add 1.
 928          */
 929         return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
 930                 dev->caps.reserved_eqs / 4 + 1;
 931 }
 932
 933 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
 934 {
 935         struct mlx4_priv *priv = mlx4_priv(dev);
 936         int index;
 937
 938         index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
 939
 940         if (!priv->eq_table.uar_map[index]) {
 941                 priv->eq_table.uar_map[index] =
 942                         ioremap(
 943                                 pci_resource_start(dev->persist->pdev, 2) +
 944                                 ((eq->eqn / 4) << (dev->uar_page_shift)),
 945                                 (1 << (dev->uar_page_shift)));
 946                 if (!priv->eq_table.uar_map[index]) {
 947                         mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
 948                                  eq->eqn);
 949                         return NULL;
 950                 }
 951         }
 952
 953         return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
 954 }
 955
 956 static void mlx4_unmap_uar(struct mlx4_dev *dev)
 957 {
 958         struct mlx4_priv *priv = mlx4_priv(dev);
 959         int i;
 960
 961         for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
 962                 if (priv->eq_table.uar_map[i]) {
 963                         iounmap(priv->eq_table.uar_map[i]);
 964                         priv->eq_table.uar_map[i] = NULL;
 965                 }
 966 }
 967
 968 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
 969                           u8 intr, struct mlx4_eq *eq)
 970 {
 971         struct mlx4_priv *priv = mlx4_priv(dev);
 972         struct mlx4_cmd_mailbox *mailbox;
 973         struct mlx4_eq_context *eq_context;
 974         int npages;
 975         u64 *dma_list = NULL;
 976         dma_addr_t t;
 977         u64 mtt_addr;
 978         int err = -ENOMEM;
 979         int i;
 980
 981         eq->dev   = dev;
 982         eq->nent  = roundup_pow_of_two(max(nent, 2));
 983         /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
 984          * strides of 64B,128B and 256B.
 985          */
 986         npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
 987
 988         eq->page_list = kmalloc_array(npages, sizeof(*eq->page_list),
 989                                       GFP_KERNEL);
 990         if (!eq->page_list)
 991                 goto err_out;
 992
 993         for (i = 0; i < npages; ++i)
 994                 eq->page_list[i].buf = NULL;
 995
 996         dma_list = kmalloc_array(npages, sizeof(*dma_list), GFP_KERNEL);
 997         if (!dma_list)
 998                 goto err_out_free;
 999
1000         mailbox = mlx4_alloc_cmd_mailbox(dev);
1001         if (IS_ERR(mailbox))
1002                 goto err_out_free;
1003         eq_context = mailbox->buf;
1004
1005         for (i = 0; i < npages; ++i) {
1006                 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist->
1007                                                           pdev->dev,
1008                                                           PAGE_SIZE, &t,
1009                                                           GFP_KERNEL);
1010                 if (!eq->page_list[i].buf)
1011                         goto err_out_free_pages;
1012
1013                 dma_list[i] = t;
1014                 eq->page_list[i].map = t;
1015
1016                 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
1017         }
1018
1019         eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
1020         if (eq->eqn == -1)
1021                 goto err_out_free_pages;
1022
1023         eq->doorbell = mlx4_get_eq_uar(dev, eq);
1024         if (!eq->doorbell) {
1025                 err = -ENOMEM;
1026                 goto err_out_free_eq;
1027         }
1028
1029         err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
1030         if (err)
1031                 goto err_out_free_eq;
1032
1033         err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
1034         if (err)
1035                 goto err_out_free_mtt;
1036
1037         eq_context->flags         = cpu_to_be32(MLX4_EQ_STATUS_OK   |
1038                                                 MLX4_EQ_STATE_ARMED);
1039         eq_context->log_eq_size   = ilog2(eq->nent);
1040         eq_context->intr          = intr;
1041         eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
1042
1043         mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
1044         eq_context->mtt_base_addr_h = mtt_addr >> 32;
1045         eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
1046
1047         err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
1048         if (err) {
1049                 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
1050                 goto err_out_free_mtt;
1051         }
1052
1053         kfree(dma_list);
1054         mlx4_free_cmd_mailbox(dev, mailbox);
1055
1056         eq->cons_index = 0;
1057
1058         INIT_LIST_HEAD(&eq->tasklet_ctx.list);
1059         INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
1060         spin_lock_init(&eq->tasklet_ctx.lock);
1061         tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb,
1062                      (unsigned long)&eq->tasklet_ctx);
1063
1064         return err;
1065
1066 err_out_free_mtt:
1067         mlx4_mtt_cleanup(dev, &eq->mtt);
1068
1069 err_out_free_eq:
1070         mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1071
1072 err_out_free_pages:
1073         for (i = 0; i < npages; ++i)
1074                 if (eq->page_list[i].buf)
1075                         dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1076                                           eq->page_list[i].buf,
1077                                           eq->page_list[i].map);
1078
1079         mlx4_free_cmd_mailbox(dev, mailbox);
1080
1081 err_out_free:
1082         kfree(eq->page_list);
1083         kfree(dma_list);
1084
1085 err_out:
1086         return err;
1087 }
1088
1089 static void mlx4_free_eq(struct mlx4_dev *dev,
1090                          struct mlx4_eq *eq)
1091 {
1092         struct mlx4_priv *priv = mlx4_priv(dev);
1093         int err;
1094         int i;
1095         /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
1096          * strides of 64B,128B and 256B
1097          */
1098         int npages = PAGE_ALIGN(dev->caps.eqe_size  * eq->nent) / PAGE_SIZE;
1099
1100         err = mlx4_HW2SW_EQ(dev, eq->eqn);
1101         if (err)
1102                 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1103
1104         synchronize_irq(eq->irq);
1105         tasklet_disable(&eq->tasklet_ctx.task);
1106
1107         mlx4_mtt_cleanup(dev, &eq->mtt);
1108         for (i = 0; i < npages; ++i)
1109                 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1110                                   eq->page_list[i].buf,
1111                                   eq->page_list[i].map);
1112
1113         kfree(eq->page_list);
1114         mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1115 }
1116
1117 static void mlx4_free_irqs(struct mlx4_dev *dev)
1118 {
1119         struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1120         int     i;
1121
1122         if (eq_table->have_irq)
1123                 free_irq(dev->persist->pdev->irq, dev);
1124
1125         for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1126                 if (eq_table->eq[i].have_irq) {
1127                         free_cpumask_var(eq_table->eq[i].affinity_mask);
1128 #if defined(CONFIG_SMP)
1129                         irq_set_affinity_hint(eq_table->eq[i].irq, NULL);
1130 #endif
1131                         free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1132                         eq_table->eq[i].have_irq = 0;
1133                 }
1134
1135         kfree(eq_table->irq_names);
1136 }
1137
1138 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1139 {
1140         struct mlx4_priv *priv = mlx4_priv(dev);
1141
1142         priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev,
1143                                  priv->fw.clr_int_bar) +
1144                                  priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1145         if (!priv->clr_base) {
1146                 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n");
1147                 return -ENOMEM;
1148         }
1149
1150         return 0;
1151 }
1152
1153 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1154 {
1155         struct mlx4_priv *priv = mlx4_priv(dev);
1156
1157         iounmap(priv->clr_base);
1158 }
1159
1160 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1161 {
1162         struct mlx4_priv *priv = mlx4_priv(dev);
1163
1164         priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1165                                     sizeof(*priv->eq_table.eq), GFP_KERNEL);
1166         if (!priv->eq_table.eq)
1167                 return -ENOMEM;
1168
1169         return 0;
1170 }
1171
1172 void mlx4_free_eq_table(struct mlx4_dev *dev)
1173 {
1174         kfree(mlx4_priv(dev)->eq_table.eq);
1175 }
1176
1177 int mlx4_init_eq_table(struct mlx4_dev *dev)
1178 {
1179         struct mlx4_priv *priv = mlx4_priv(dev);
1180         int err;
1181         int i;
1182
1183         priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1184                                          sizeof(*priv->eq_table.uar_map),
1185                                          GFP_KERNEL);
1186         if (!priv->eq_table.uar_map) {
1187                 err = -ENOMEM;
1188                 goto err_out_free;
1189         }
1190
1191         err = mlx4_bitmap_init(&priv->eq_table.bitmap,
1192                                roundup_pow_of_two(dev->caps.num_eqs),
1193                                dev->caps.num_eqs - 1,
1194                                dev->caps.reserved_eqs,
1195                                roundup_pow_of_two(dev->caps.num_eqs) -
1196                                dev->caps.num_eqs);
1197         if (err)
1198                 goto err_out_free;
1199
1200         for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1201                 priv->eq_table.uar_map[i] = NULL;
1202
1203         if (!mlx4_is_slave(dev)) {
1204                 err = mlx4_map_clr_int(dev);
1205                 if (err)
1206                         goto err_out_bitmap;
1207
1208                 priv->eq_table.clr_mask =
1209                         swab32(1 << (priv->eq_table.inta_pin & 31));
1210                 priv->eq_table.clr_int  = priv->clr_base +
1211                         (priv->eq_table.inta_pin < 32 ? 4 : 0);
1212         }
1213
1214         priv->eq_table.irq_names =
1215                 kmalloc_array(MLX4_IRQNAME_SIZE,
1216                               (dev->caps.num_comp_vectors + 1),
1217                               GFP_KERNEL);
1218         if (!priv->eq_table.irq_names) {
1219                 err = -ENOMEM;
1220                 goto err_out_clr_int;
1221         }
1222
1223         for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1224                 if (i == MLX4_EQ_ASYNC) {
1225                         err = mlx4_create_eq(dev,
1226                                              MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1227                                              0, &priv->eq_table.eq[MLX4_EQ_ASYNC]);
1228                 } else {
1229                         struct mlx4_eq  *eq = &priv->eq_table.eq[i];
1230 #ifdef CONFIG_RFS_ACCEL
1231                         int port = find_first_bit(eq->actv_ports.ports,
1232                                                   dev->caps.num_ports) + 1;
1233
1234                         if (port <= dev->caps.num_ports) {
1235                                 struct mlx4_port_info *info =
1236                                         &mlx4_priv(dev)->port[port];
1237
1238                                 if (!info->rmap) {
1239                                         info->rmap = alloc_irq_cpu_rmap(
1240                                                 mlx4_get_eqs_per_port(dev, port));
1241                                         if (!info->rmap) {
1242                                                 mlx4_warn(dev, "Failed to allocate cpu rmap\n");
1243                                                 err = -ENOMEM;
1244                                                 goto err_out_unmap;
1245                                         }
1246                                 }
1247
1248                                 err = irq_cpu_rmap_add(
1249                                         info->rmap, eq->irq);
1250                                 if (err)
1251                                         mlx4_warn(dev, "Failed adding irq rmap\n");
1252                         }
1253 #endif
1254                         err = mlx4_create_eq(dev, dev->quotas.cq +
1255                                              MLX4_NUM_SPARE_EQE,
1256                                              (dev->flags & MLX4_FLAG_MSI_X) ?
1257                                              i + 1 - !!(i > MLX4_EQ_ASYNC) : 0,
1258                                              eq);
1259                 }
1260                 if (err)
1261                         goto err_out_unmap;
1262         }
1263
1264         if (dev->flags & MLX4_FLAG_MSI_X) {
1265                 const char *eq_name;
1266
1267                 snprintf(priv->eq_table.irq_names +
1268                          MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE,
1269                          MLX4_IRQNAME_SIZE,
1270                          "mlx4-async@pci:%s",
1271                          pci_name(dev->persist->pdev));
1272                 eq_name = priv->eq_table.irq_names +
1273                         MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE;
1274
1275                 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq,
1276                                   mlx4_msi_x_interrupt, 0, eq_name,
1277                                   priv->eq_table.eq + MLX4_EQ_ASYNC);
1278                 if (err)
1279                         goto err_out_unmap;
1280
1281                 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1;
1282         } else {
1283                 snprintf(priv->eq_table.irq_names,
1284                          MLX4_IRQNAME_SIZE,
1285                          DRV_NAME "@pci:%s",
1286                          pci_name(dev->persist->pdev));
1287                 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt,
1288                                   IRQF_SHARED, priv->eq_table.irq_names, dev);
1289                 if (err)
1290                         goto err_out_unmap;
1291
1292                 priv->eq_table.have_irq = 1;
1293         }
1294
1295         err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1296                           priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1297         if (err)
1298                 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1299                            priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err);
1300
1301         /* arm ASYNC eq */
1302         eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1);
1303
1304         return 0;
1305
1306 err_out_unmap:
1307         while (i > 0)
1308                 mlx4_free_eq(dev, &priv->eq_table.eq[--i]);
1309 #ifdef CONFIG_RFS_ACCEL
1310         for (i = 1; i <= dev->caps.num_ports; i++) {
1311                 if (mlx4_priv(dev)->port[i].rmap) {
1312                         free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1313                         mlx4_priv(dev)->port[i].rmap = NULL;
1314                 }
1315         }
1316 #endif
1317         mlx4_free_irqs(dev);
1318
1319 err_out_clr_int:
1320         if (!mlx4_is_slave(dev))
1321                 mlx4_unmap_clr_int(dev);
1322
1323 err_out_bitmap:
1324         mlx4_unmap_uar(dev);
1325         mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1326
1327 err_out_free:
1328         kfree(priv->eq_table.uar_map);
1329
1330         return err;
1331 }
1332
1333 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1334 {
1335         struct mlx4_priv *priv = mlx4_priv(dev);
1336         int i;
1337
1338         mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1339                     priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1340
1341 #ifdef CONFIG_RFS_ACCEL
1342         for (i = 1; i <= dev->caps.num_ports; i++) {
1343                 if (mlx4_priv(dev)->port[i].rmap) {
1344                         free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1345                         mlx4_priv(dev)->port[i].rmap = NULL;
1346                 }
1347         }
1348 #endif
1349         mlx4_free_irqs(dev);
1350
1351         for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1352                 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1353
1354         if (!mlx4_is_slave(dev))
1355                 mlx4_unmap_clr_int(dev);
1356
1357         mlx4_unmap_uar(dev);
1358         mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1359
1360         kfree(priv->eq_table.uar_map);
1361 }
1362
1363 /* A test that verifies that we can accept interrupts
1364  * on the vector allocated for asynchronous events
1365  */
1366 int mlx4_test_async(struct mlx4_dev *dev)
1367 {
1368         return mlx4_NOP(dev);
1369 }
1370 EXPORT_SYMBOL(mlx4_test_async);
1371
1372 /* A test that verifies that we can accept interrupts
1373  * on the given irq vector of the tested port.
1374  * Interrupts are checked using the NOP command.
1375  */
1376 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector)
1377 {
1378         struct mlx4_priv *priv = mlx4_priv(dev);
1379         int err;
1380
1381         /* Temporary use polling for command completions */
1382         mlx4_cmd_use_polling(dev);
1383
1384         /* Map the new eq to handle all asynchronous events */
1385         err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1386                           priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn);
1387         if (err) {
1388                 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1389                 goto out;
1390         }
1391
1392         /* Go back to using events */
1393         mlx4_cmd_use_events(dev);
1394         err = mlx4_NOP(dev);
1395
1396         /* Return to default */
1397         mlx4_cmd_use_polling(dev);
1398 out:
1399         mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1400                     priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1401         mlx4_cmd_use_events(dev);
1402
1403         return err;
1404 }
1405 EXPORT_SYMBOL(mlx4_test_interrupt);
1406
1407 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector)
1408 {
1409         struct mlx4_priv *priv = mlx4_priv(dev);
1410
1411         vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1412         if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) ||
1413             (vector == MLX4_EQ_ASYNC))
1414                 return false;
1415
1416         return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports);
1417 }
1418 EXPORT_SYMBOL(mlx4_is_eq_vector_valid);
1419
1420 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port)
1421 {
1422         struct mlx4_priv *priv = mlx4_priv(dev);
1423         unsigned int i;
1424         unsigned int sum = 0;
1425
1426         for (i = 0; i < dev->caps.num_comp_vectors + 1; i++)
1427                 sum += !!test_bit(port - 1,
1428                                   priv->eq_table.eq[i].actv_ports.ports);
1429
1430         return sum;
1431 }
1432 EXPORT_SYMBOL(mlx4_get_eqs_per_port);
1433
1434 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector)
1435 {
1436         struct mlx4_priv *priv = mlx4_priv(dev);
1437
1438         vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1439         if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1))
1440                 return -EINVAL;
1441
1442         return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports,
1443                                 dev->caps.num_ports) > 1);
1444 }
1445 EXPORT_SYMBOL(mlx4_is_eq_shared);
1446
1447 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port)
1448 {
1449         return mlx4_priv(dev)->port[port].rmap;
1450 }
1451 EXPORT_SYMBOL(mlx4_get_cpu_rmap);
1452
1453 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector)
1454 {
1455         struct mlx4_priv *priv = mlx4_priv(dev);
1456         int err = 0, i = 0;
1457         u32 min_ref_count_val = (u32)-1;
1458         int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector);
1459         int *prequested_vector = NULL;
1460
1461
1462         mutex_lock(&priv->msix_ctl.pool_lock);
1463         if (requested_vector < (dev->caps.num_comp_vectors + 1) &&
1464             (requested_vector >= 0) &&
1465             (requested_vector != MLX4_EQ_ASYNC)) {
1466                 if (test_bit(port - 1,
1467                              priv->eq_table.eq[requested_vector].actv_ports.ports)) {
1468                         prequested_vector = &requested_vector;
1469                 } else {
1470                         struct mlx4_eq *eq;
1471
1472                         for (i = 1; i < port;
1473                              requested_vector += mlx4_get_eqs_per_port(dev, i++))
1474                                 ;
1475
1476                         eq = &priv->eq_table.eq[requested_vector];
1477                         if (requested_vector < dev->caps.num_comp_vectors + 1 &&
1478                             test_bit(port - 1, eq->actv_ports.ports)) {
1479                                 prequested_vector = &requested_vector;
1480                         }
1481                 }
1482         }
1483
1484         if  (!prequested_vector) {
1485                 requested_vector = -1;
1486                 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1;
1487                      i++) {
1488                         struct mlx4_eq *eq = &priv->eq_table.eq[i];
1489
1490                         if (min_ref_count_val > eq->ref_count &&
1491                             test_bit(port - 1, eq->actv_ports.ports)) {
1492                                 min_ref_count_val = eq->ref_count;
1493                                 requested_vector = i;
1494                         }
1495                 }
1496
1497                 if (requested_vector < 0) {
1498                         err = -ENOSPC;
1499                         goto err_unlock;
1500                 }
1501
1502                 prequested_vector = &requested_vector;
1503         }
1504
1505         if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) &&
1506             dev->flags & MLX4_FLAG_MSI_X) {
1507                 set_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1508                 snprintf(priv->eq_table.irq_names +
1509                          *prequested_vector * MLX4_IRQNAME_SIZE,
1510                          MLX4_IRQNAME_SIZE, "mlx4-%d@%s",
1511                          *prequested_vector, dev_name(&dev->persist->pdev->dev));
1512
1513                 err = request_irq(priv->eq_table.eq[*prequested_vector].irq,
1514                                   mlx4_msi_x_interrupt, 0,
1515                                   &priv->eq_table.irq_names[*prequested_vector << 5],
1516                                   priv->eq_table.eq + *prequested_vector);
1517
1518                 if (err) {
1519                         clear_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1520                         *prequested_vector = -1;
1521                 } else {
1522 #if defined(CONFIG_SMP)
1523                         mlx4_set_eq_affinity_hint(priv, *prequested_vector);
1524 #endif
1525                         eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1);
1526                         priv->eq_table.eq[*prequested_vector].have_irq = 1;
1527                 }
1528         }
1529
1530         if (!err && *prequested_vector >= 0)
1531                 priv->eq_table.eq[*prequested_vector].ref_count++;
1532
1533 err_unlock:
1534         mutex_unlock(&priv->msix_ctl.pool_lock);
1535
1536         if (!err && *prequested_vector >= 0)
1537                 *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector);
1538         else
1539                 *vector = 0;
1540
1541         return err;
1542 }
1543 EXPORT_SYMBOL(mlx4_assign_eq);
1544
1545 int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec)
1546 {
1547         struct mlx4_priv *priv = mlx4_priv(dev);
1548
1549         return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq;
1550 }
1551 EXPORT_SYMBOL(mlx4_eq_get_irq);
1552
1553 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1554 {
1555         struct mlx4_priv *priv = mlx4_priv(dev);
1556         int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec);
1557
1558         mutex_lock(&priv->msix_ctl.pool_lock);
1559         priv->eq_table.eq[eq_vec].ref_count--;
1560
1561         /* once we allocated EQ, we don't release it because it might be binded
1562          * to cpu_rmap.
1563          */
1564         mutex_unlock(&priv->msix_ctl.pool_lock);
1565 }
1566 EXPORT_SYMBOL(mlx4_release_eq);
1567