drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/kmod.h>
  45 #include <linux/etherdevice.h>
  46 #include <net/devlink.h>
  47
  48 #include <linux/mlx4/device.h>
  49 #include <linux/mlx4/doorbell.h>
  50
  51 #include "mlx4.h"
  52 #include "fw.h"
  53 #include "icm.h"
  54
  55 MODULE_AUTHOR("Roland Dreier");
  56 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  57 MODULE_LICENSE("Dual BSD/GPL");
  58 MODULE_VERSION(DRV_VERSION);
  59
  60 struct workqueue_struct *mlx4_wq;
  61
  62 #ifdef CONFIG_MLX4_DEBUG
  63
  64 int mlx4_debug_level = 0;
  65 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  66 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  67
  68 #endif /* CONFIG_MLX4_DEBUG */
  69
  70 #ifdef CONFIG_PCI_MSI
  71
  72 static int msi_x = 1;
  73 module_param(msi_x, int, 0444);
  74 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  75
  76 #else /* CONFIG_PCI_MSI */
  77
  78 #define msi_x (0)
  79
  80 #endif /* CONFIG_PCI_MSI */
  81
  82 static uint8_t num_vfs[3] = {0, 0, 0};
  83 static int num_vfs_argc;
  84 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
  85 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
  86                           "num_vfs=port1,port2,port1+2");
  87
  88 static uint8_t probe_vf[3] = {0, 0, 0};
  89 static int probe_vfs_argc;
  90 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
  91 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
  92                            "probe_vf=port1,port2,port1+2");
  93
  94 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  95 module_param_named(log_num_mgm_entry_size,
  96                         mlx4_log_num_mgm_entry_size, int, 0444);
  97 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  98                                          " of qp per mcg, for example:"
  99                                          " 10 gives 248.range: 7 <="
 100                                          " log_num_mgm_entry_size <= 12."
 101                                          " To activate device managed"
 102                                          " flow steering when available, set to -1");
 103
 104 static bool enable_64b_cqe_eqe = true;
 105 module_param(enable_64b_cqe_eqe, bool, 0444);
 106 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 107                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 108
 109 static bool enable_4k_uar;
 110 module_param(enable_4k_uar, bool, 0444);
 111 MODULE_PARM_DESC(enable_4k_uar,
 112                  "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
 113
 114 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
 115                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
 116                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
 117
 118 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
 119
 120 static char mlx4_version[] =
 121         DRV_NAME ": Mellanox ConnectX core driver v"
 122         DRV_VERSION " (" DRV_RELDATE ")\n";
 123
 124 static struct mlx4_profile default_profile = {
 125         .num_qp         = 1 << 18,
 126         .num_srq        = 1 << 16,
 127         .rdmarc_per_qp  = 1 << 4,
 128         .num_cq         = 1 << 16,
 129         .num_mcg        = 1 << 13,
 130         .num_mpt        = 1 << 19,
 131         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 132 };
 133
 134 static struct mlx4_profile low_mem_profile = {
 135         .num_qp         = 1 << 17,
 136         .num_srq        = 1 << 6,
 137         .rdmarc_per_qp  = 1 << 4,
 138         .num_cq         = 1 << 8,
 139         .num_mcg        = 1 << 8,
 140         .num_mpt        = 1 << 9,
 141         .num_mtt        = 1 << 7,
 142 };
 143
 144 static int log_num_mac = 7;
 145 module_param_named(log_num_mac, log_num_mac, int, 0444);
 146 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 147
 148 static int log_num_vlan;
 149 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 150 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 151 /* Log2 max number of VLANs per ETH port (0-7) */
 152 #define MLX4_LOG_NUM_VLANS 7
 153 #define MLX4_MIN_LOG_NUM_VLANS 0
 154 #define MLX4_MIN_LOG_NUM_MAC 1
 155
 156 static bool use_prio;
 157 module_param_named(use_prio, use_prio, bool, 0444);
 158 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
 159
 160 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 161 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 162 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 163
 164 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 165 static int arr_argc = 2;
 166 module_param_array(port_type_array, int, &arr_argc, 0444);
 167 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 168                                 "1 for IB, 2 for Ethernet");
 169
 170 struct mlx4_port_config {
 171         struct list_head list;
 172         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 173         struct pci_dev *pdev;
 174 };
 175
 176 static atomic_t pf_loading = ATOMIC_INIT(0);
 177
 178 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
 179                                               struct mlx4_dev_cap *dev_cap)
 180 {
 181         /* The reserved_uars is calculated by system page size unit.
 182          * Therefore, adjustment is added when the uar page size is less
 183          * than the system page size
 184          */
 185         dev->caps.reserved_uars =
 186                 max_t(int,
 187                       mlx4_get_num_reserved_uar(dev),
 188                       dev_cap->reserved_uars /
 189                         (1 << (PAGE_SHIFT - dev->uar_page_shift)));
 190 }
 191
 192 int mlx4_check_port_params(struct mlx4_dev *dev,
 193                            enum mlx4_port_type *port_type)
 194 {
 195         int i;
 196
 197         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 198                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
 199                         if (port_type[i] != port_type[i + 1]) {
 200                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
 201                                 return -EOPNOTSUPP;
 202                         }
 203                 }
 204         }
 205
 206         for (i = 0; i < dev->caps.num_ports; i++) {
 207                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 208                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
 209                                  i + 1);
 210                         return -EOPNOTSUPP;
 211                 }
 212         }
 213         return 0;
 214 }
 215
 216 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 217 {
 218         int i;
 219
 220         for (i = 1; i <= dev->caps.num_ports; ++i)
 221                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 222 }
 223
 224 enum {
 225         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
 226 };
 227
 228 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 229 {
 230         int err = 0;
 231         struct mlx4_func func;
 232
 233         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
 234                 err = mlx4_QUERY_FUNC(dev, &func, 0);
 235                 if (err) {
 236                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 237                         return err;
 238                 }
 239                 dev_cap->max_eqs = func.max_eq;
 240                 dev_cap->reserved_eqs = func.rsvd_eqs;
 241                 dev_cap->reserved_uars = func.rsvd_uars;
 242                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
 243         }
 244         return err;
 245 }
 246
 247 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
 248 {
 249         struct mlx4_caps *dev_cap = &dev->caps;
 250
 251         /* FW not supporting or cancelled by user */
 252         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
 253             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
 254                 return;
 255
 256         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
 257          * When FW has NCSI it may decide not to report 64B CQE/EQEs
 258          */
 259         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
 260             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
 261                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 262                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 263                 return;
 264         }
 265
 266         if (cache_line_size() == 128 || cache_line_size() == 256) {
 267                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
 268                 /* Changing the real data inside CQE size to 32B */
 269                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 270                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 271
 272                 if (mlx4_is_master(dev))
 273                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
 274         } else {
 275                 if (cache_line_size() != 32  && cache_line_size() != 64)
 276                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
 277                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 278                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 279         }
 280 }
 281
 282 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
 283                           struct mlx4_port_cap *port_cap)
 284 {
 285         dev->caps.vl_cap[port]      = port_cap->max_vl;
 286         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
 287         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
 288         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
 289         /* set gid and pkey table operating lengths by default
 290          * to non-sriov values
 291          */
 292         dev->caps.gid_table_len[port]  = port_cap->max_gids;
 293         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
 294         dev->caps.port_width_cap[port] = port_cap->max_port_width;
 295         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
 296         dev->caps.max_tc_eth           = port_cap->max_tc_eth;
 297         dev->caps.def_mac[port]        = port_cap->def_mac;
 298         dev->caps.supported_type[port] = port_cap->supported_port_types;
 299         dev->caps.suggested_type[port] = port_cap->suggested_type;
 300         dev->caps.default_sense[port] = port_cap->default_sense;
 301         dev->caps.trans_type[port]          = port_cap->trans_type;
 302         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
 303         dev->caps.wavelength[port]     = port_cap->wavelength;
 304         dev->caps.trans_code[port]     = port_cap->trans_code;
 305
 306         return 0;
 307 }
 308
 309 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
 310                          struct mlx4_port_cap *port_cap)
 311 {
 312         int err = 0;
 313
 314         err = mlx4_QUERY_PORT(dev, port, port_cap);
 315
 316         if (err)
 317                 mlx4_err(dev, "QUERY_PORT command failed.\n");
 318
 319         return err;
 320 }
 321
 322 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
 323 {
 324         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
 325                 return;
 326
 327         if (mlx4_is_mfunc(dev)) {
 328                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
 329                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 330                 return;
 331         }
 332
 333         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
 334                 mlx4_dbg(dev,
 335                          "Keep FCS is not supported - Disabling Ignore FCS");
 336                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 337                 return;
 338         }
 339 }
 340
 341 #define MLX4_A0_STEERING_TABLE_SIZE     256
 342 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 343 {
 344         int err;
 345         int i;
 346
 347         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 348         if (err) {
 349                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 350                 return err;
 351         }
 352         mlx4_dev_cap_dump(dev, dev_cap);
 353
 354         if (dev_cap->min_page_sz > PAGE_SIZE) {
 355                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 356                          dev_cap->min_page_sz, PAGE_SIZE);
 357                 return -ENODEV;
 358         }
 359         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 360                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 361                          dev_cap->num_ports, MLX4_MAX_PORTS);
 362                 return -ENODEV;
 363         }
 364
 365         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
 366                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 367                          dev_cap->uar_size,
 368                          (unsigned long long)
 369                          pci_resource_len(dev->persist->pdev, 2));
 370                 return -ENODEV;
 371         }
 372
 373         dev->caps.num_ports          = dev_cap->num_ports;
 374         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
 375         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
 376                                       dev->caps.num_sys_eqs :
 377                                       MLX4_MAX_EQ_NUM;
 378         for (i = 1; i <= dev->caps.num_ports; ++i) {
 379                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
 380                 if (err) {
 381                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
 382                         return err;
 383                 }
 384         }
 385
 386         dev->caps.uar_page_size      = PAGE_SIZE;
 387         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 388         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 389         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 390         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 391         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 392         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 393         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 394         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 395         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 396         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 397         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 398         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 399         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 400         /*
 401          * Subtract 1 from the limit because we need to allocate a
 402          * spare CQE so the HCA HW can tell the difference between an
 403          * empty CQ and a full CQ.
 404          */
 405         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 406         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 407         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 408         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 409         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 410
 411         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 412         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 413                                         dev_cap->reserved_xrcds : 0;
 414         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 415                                         dev_cap->max_xrcds : 0;
 416         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 417
 418         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 419         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 420         dev->caps.flags              = dev_cap->flags;
 421         dev->caps.flags2             = dev_cap->flags2;
 422         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 423         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 424         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 425         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 426         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 427
 428         /* Save uar page shift */
 429         if (!mlx4_is_slave(dev)) {
 430                 /* Virtual PCI function needs to determine UAR page size from
 431                  * firmware. Only master PCI function can set the uar page size
 432                  */
 433                 if (enable_4k_uar || !dev->persist->num_vfs)
 434                         dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
 435                 else
 436                         dev->uar_page_shift = PAGE_SHIFT;
 437
 438                 mlx4_set_num_reserved_uars(dev, dev_cap);
 439         }
 440
 441         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
 442                 struct mlx4_init_hca_param hca_param;
 443
 444                 memset(&hca_param, 0, sizeof(hca_param));
 445                 err = mlx4_QUERY_HCA(dev, &hca_param);
 446                 /* Turn off PHV_EN flag in case phv_check_en is set.
 447                  * phv_check_en is a HW check that parse the packet and verify
 448                  * phv bit was reported correctly in the wqe. To allow QinQ
 449                  * PHV_EN flag should be set and phv_check_en must be cleared
 450                  * otherwise QinQ packets will be drop by the HW.
 451                  */
 452                 if (err || hca_param.phv_check_en)
 453                         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
 454         }
 455
 456         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 457         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 458                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 459         /* Don't do sense port on multifunction devices (for now at least) */
 460         if (mlx4_is_mfunc(dev))
 461                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 462
 463         if (mlx4_low_memory_profile()) {
 464                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
 465                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
 466         } else {
 467                 dev->caps.log_num_macs  = log_num_mac;
 468                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 469         }
 470
 471         for (i = 1; i <= dev->caps.num_ports; ++i) {
 472                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 473                 if (dev->caps.supported_type[i]) {
 474                         /* if only ETH is supported - assign ETH */
 475                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 476                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 477                         /* if only IB is supported, assign IB */
 478                         else if (dev->caps.supported_type[i] ==
 479                                  MLX4_PORT_TYPE_IB)
 480                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 481                         else {
 482                                 /* if IB and ETH are supported, we set the port
 483                                  * type according to user selection of port type;
 484                                  * if user selected none, take the FW hint */
 485                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 486                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 487                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 488                                 else
 489                                         dev->caps.port_type[i] = port_type_array[i - 1];
 490                         }
 491                 }
 492                 /*
 493                  * Link sensing is allowed on the port if 3 conditions are true:
 494                  * 1. Both protocols are supported on the port.
 495                  * 2. Different types are supported on the port
 496                  * 3. FW declared that it supports link sensing
 497                  */
 498                 mlx4_priv(dev)->sense.sense_allowed[i] =
 499                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 500                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 501                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 502
 503                 /*
 504                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 505                  * and perform sense_port FW command to try and set the correct
 506                  * port type from beginning
 507                  */
 508                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 509                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 510                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 511                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 512                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 513                                 dev->caps.port_type[i] = sensed_port;
 514                 } else {
 515                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 516                 }
 517
 518                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
 519                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
 520                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
 521                                   i, 1 << dev->caps.log_num_macs);
 522                 }
 523                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
 524                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
 525                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
 526                                   i, 1 << dev->caps.log_num_vlans);
 527                 }
 528         }
 529
 530         if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
 531             (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
 532             (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
 533                 mlx4_warn(dev,
 534                           "Granular QoS per VF not supported with IB/Eth configuration\n");
 535                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
 536         }
 537
 538         dev->caps.max_counters = dev_cap->max_counters;
 539
 540         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 541         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 542                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 543                 (1 << dev->caps.log_num_macs) *
 544                 (1 << dev->caps.log_num_vlans) *
 545                 dev->caps.num_ports;
 546         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 547
 548         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
 549             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
 550                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
 551         else
 552                 dev->caps.dmfs_high_rate_qpn_base =
 553                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 554
 555         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
 556             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
 557                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
 558                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
 559                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
 560         } else {
 561                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
 562                 dev->caps.dmfs_high_rate_qpn_base =
 563                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 564                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
 565         }
 566
 567         dev->caps.rl_caps = dev_cap->rl_caps;
 568
 569         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
 570                 dev->caps.dmfs_high_rate_qpn_range;
 571
 572         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 573                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 574                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 575                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 576
 577         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 578
 579         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 580                 if (dev_cap->flags &
 581                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 582                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 583                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 584                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 585                 }
 586
 587                 if (dev_cap->flags2 &
 588                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
 589                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
 590                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
 591                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 592                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 593                 }
 594         }
 595
 596         if ((dev->caps.flags &
 597             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 598             mlx4_is_master(dev))
 599                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 600
 601         if (!mlx4_is_slave(dev)) {
 602                 mlx4_enable_cqe_eqe_stride(dev);
 603                 dev->caps.alloc_res_qp_mask =
 604                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
 605                         MLX4_RESERVE_A0_QP;
 606
 607                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
 608                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
 609                         mlx4_warn(dev, "Old device ETS support detected\n");
 610                         mlx4_warn(dev, "Consider upgrading device FW.\n");
 611                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
 612                 }
 613
 614         } else {
 615                 dev->caps.alloc_res_qp_mask = 0;
 616         }
 617
 618         mlx4_enable_ignore_fcs(dev);
 619
 620         return 0;
 621 }
 622
 623 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 624                                        enum pci_bus_speed *speed,
 625                                        enum pcie_link_width *width)
 626 {
 627         u32 lnkcap1, lnkcap2;
 628         int err1, err2;
 629
 630 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 631
 632         *speed = PCI_SPEED_UNKNOWN;
 633         *width = PCIE_LNK_WIDTH_UNKNOWN;
 634
 635         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
 636                                           &lnkcap1);
 637         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
 638                                           &lnkcap2);
 639         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 640                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 641                         *speed = PCIE_SPEED_8_0GT;
 642                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 643                         *speed = PCIE_SPEED_5_0GT;
 644                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 645                         *speed = PCIE_SPEED_2_5GT;
 646         }
 647         if (!err1) {
 648                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 649                 if (!lnkcap2) { /* pre-r3.0 */
 650                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 651                                 *speed = PCIE_SPEED_5_0GT;
 652                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 653                                 *speed = PCIE_SPEED_2_5GT;
 654                 }
 655         }
 656
 657         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 658                 return err1 ? err1 :
 659                         err2 ? err2 : -EINVAL;
 660         }
 661         return 0;
 662 }
 663
 664 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 665 {
 666         enum pcie_link_width width, width_cap;
 667         enum pci_bus_speed speed, speed_cap;
 668         int err;
 669
 670 #define PCIE_SPEED_STR(speed) \
 671         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 672          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 673          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 674          "Unknown")
 675
 676         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 677         if (err) {
 678                 mlx4_warn(dev,
 679                           "Unable to determine PCIe device BW capabilities\n");
 680                 return;
 681         }
 682
 683         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
 684         if (err || speed == PCI_SPEED_UNKNOWN ||
 685             width == PCIE_LNK_WIDTH_UNKNOWN) {
 686                 mlx4_warn(dev,
 687                           "Unable to determine PCI device chain minimum BW\n");
 688                 return;
 689         }
 690
 691         if (width != width_cap || speed != speed_cap)
 692                 mlx4_warn(dev,
 693                           "PCIe BW is different than device's capability\n");
 694
 695         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 696                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 697         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 698                   width, width_cap);
 699         return;
 700 }
 701
 702 /*The function checks if there are live vf, return the num of them*/
 703 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 704 {
 705         struct mlx4_priv *priv = mlx4_priv(dev);
 706         struct mlx4_slave_state *s_state;
 707         int i;
 708         int ret = 0;
 709
 710         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 711                 s_state = &priv->mfunc.master.slave_state[i];
 712                 if (s_state->active && s_state->last_cmd !=
 713                     MLX4_COMM_CMD_RESET) {
 714                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 715                                   __func__, i);
 716                         ret++;
 717                 }
 718         }
 719         return ret;
 720 }
 721
 722 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 723 {
 724         u32 qk = MLX4_RESERVED_QKEY_BASE;
 725
 726         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 727             qpn < dev->phys_caps.base_proxy_sqpn)
 728                 return -EINVAL;
 729
 730         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 731                 /* tunnel qp */
 732                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 733         else
 734                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 735         *qkey = qk;
 736         return 0;
 737 }
 738 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 739
 740 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 741 {
 742         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 743
 744         if (!mlx4_is_master(dev))
 745                 return;
 746
 747         priv->virt2phys_pkey[slave][port - 1][i] = val;
 748 }
 749 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 750
 751 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 752 {
 753         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 754
 755         if (!mlx4_is_master(dev))
 756                 return;
 757
 758         priv->slave_node_guids[slave] = guid;
 759 }
 760 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 761
 762 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 763 {
 764         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 765
 766         if (!mlx4_is_master(dev))
 767                 return 0;
 768
 769         return priv->slave_node_guids[slave];
 770 }
 771 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 772
 773 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 774 {
 775         struct mlx4_priv *priv = mlx4_priv(dev);
 776         struct mlx4_slave_state *s_slave;
 777
 778         if (!mlx4_is_master(dev))
 779                 return 0;
 780
 781         s_slave = &priv->mfunc.master.slave_state[slave];
 782         return !!s_slave->active;
 783 }
 784 EXPORT_SYMBOL(mlx4_is_slave_active);
 785
 786 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
 787                                        struct _rule_hw *eth_header)
 788 {
 789         if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
 790             is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
 791                 struct mlx4_net_trans_rule_hw_eth *eth =
 792                         (struct mlx4_net_trans_rule_hw_eth *)eth_header;
 793                 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
 794                 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
 795                         next_rule->rsvd == 0;
 796
 797                 if (last_rule)
 798                         ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
 799         }
 800 }
 801 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
 802
 803 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 804                                        struct mlx4_dev_cap *dev_cap,
 805                                        struct mlx4_init_hca_param *hca_param)
 806 {
 807         dev->caps.steering_mode = hca_param->steering_mode;
 808         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 809                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 810                 dev->caps.fs_log_max_ucast_qp_range_size =
 811                         dev_cap->fs_log_max_ucast_qp_range_size;
 812         } else
 813                 dev->caps.num_qp_per_mgm =
 814                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 815
 816         mlx4_dbg(dev, "Steering mode is: %s\n",
 817                  mlx4_steering_mode_str(dev->caps.steering_mode));
 818 }
 819
 820 static int mlx4_slave_cap(struct mlx4_dev *dev)
 821 {
 822         int                        err;
 823         u32                        page_size;
 824         struct mlx4_dev_cap        dev_cap;
 825         struct mlx4_func_cap       func_cap;
 826         struct mlx4_init_hca_param hca_param;
 827         u8                         i;
 828
 829         memset(&hca_param, 0, sizeof(hca_param));
 830         err = mlx4_QUERY_HCA(dev, &hca_param);
 831         if (err) {
 832                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
 833                 return err;
 834         }
 835
 836         /* fail if the hca has an unknown global capability
 837          * at this time global_caps should be always zeroed
 838          */
 839         if (hca_param.global_caps) {
 840                 mlx4_err(dev, "Unknown hca global capabilities\n");
 841                 return -ENOSYS;
 842         }
 843
 844         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 845
 846         memset(&dev_cap, 0, sizeof(dev_cap));
 847         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 848         err = mlx4_dev_cap(dev, &dev_cap);
 849         if (err) {
 850                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 851                 return err;
 852         }
 853
 854         err = mlx4_QUERY_FW(dev);
 855         if (err)
 856                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
 857
 858         page_size = ~dev->caps.page_size_cap + 1;
 859         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 860         if (page_size > PAGE_SIZE) {
 861                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 862                          page_size, PAGE_SIZE);
 863                 return -ENODEV;
 864         }
 865
 866         /* Set uar_page_shift for VF */
 867         dev->uar_page_shift = hca_param.uar_page_sz + 12;
 868
 869         /* Make sure the master uar page size is valid */
 870         if (dev->uar_page_shift > PAGE_SHIFT) {
 871                 mlx4_err(dev,
 872                          "Invalid configuration: uar page size is larger than system page size\n");
 873                 return  -ENODEV;
 874         }
 875
 876         /* Set reserved_uars based on the uar_page_shift */
 877         mlx4_set_num_reserved_uars(dev, &dev_cap);
 878
 879         /* Although uar page size in FW differs from system page size,
 880          * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
 881          * still works with assumption that uar page size == system page size
 882          */
 883         dev->caps.uar_page_size = PAGE_SIZE;
 884
 885         memset(&func_cap, 0, sizeof(func_cap));
 886         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 887         if (err) {
 888                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
 889                          err);
 890                 return err;
 891         }
 892
 893         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 894             PF_CONTEXT_BEHAVIOUR_MASK) {
 895                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
 896                          func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
 897                 return -ENOSYS;
 898         }
 899
 900         dev->caps.num_ports             = func_cap.num_ports;
 901         dev->quotas.qp                  = func_cap.qp_quota;
 902         dev->quotas.srq                 = func_cap.srq_quota;
 903         dev->quotas.cq                  = func_cap.cq_quota;
 904         dev->quotas.mpt                 = func_cap.mpt_quota;
 905         dev->quotas.mtt                 = func_cap.mtt_quota;
 906         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 907         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 908         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 909         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 910         dev->caps.num_eqs               = func_cap.max_eq;
 911         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 912         dev->caps.reserved_lkey         = func_cap.reserved_lkey;
 913         dev->caps.num_pds               = MLX4_NUM_PDS;
 914         dev->caps.num_mgms              = 0;
 915         dev->caps.num_amgms             = 0;
 916
 917         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 918                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 919                          dev->caps.num_ports, MLX4_MAX_PORTS);
 920                 return -ENODEV;
 921         }
 922
 923         mlx4_replace_zero_macs(dev);
 924
 925         dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
 926         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 927         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 928         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 929         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 930
 931         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 932             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
 933             !dev->caps.qp0_qkey) {
 934                 err = -ENOMEM;
 935                 goto err_mem;
 936         }
 937
 938         for (i = 1; i <= dev->caps.num_ports; ++i) {
 939                 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
 940                 if (err) {
 941                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
 942                                  i, err);
 943                         goto err_mem;
 944                 }
 945                 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
 946                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 947                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 948                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 949                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 950                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 951                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 952                 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 953                                                       &dev->caps.gid_table_len[i],
 954                                                       &dev->caps.pkey_table_len[i]);
 955                 if (err)
 956                         goto err_mem;
 957         }
 958
 959         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 960                                        dev->caps.reserved_uars) >
 961                                        pci_resource_len(dev->persist->pdev,
 962                                                         2)) {
 963                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 964                          dev->caps.uar_page_size * dev->caps.num_uars,
 965                          (unsigned long long)
 966                          pci_resource_len(dev->persist->pdev, 2));
 967                 err = -ENOMEM;
 968                 goto err_mem;
 969         }
 970
 971         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 972                 dev->caps.eqe_size   = 64;
 973                 dev->caps.eqe_factor = 1;
 974         } else {
 975                 dev->caps.eqe_size   = 32;
 976                 dev->caps.eqe_factor = 0;
 977         }
 978
 979         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 980                 dev->caps.cqe_size   = 64;
 981                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 982         } else {
 983                 dev->caps.cqe_size   = 32;
 984         }
 985
 986         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
 987                 dev->caps.eqe_size = hca_param.eqe_size;
 988                 dev->caps.eqe_factor = 0;
 989         }
 990
 991         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
 992                 dev->caps.cqe_size = hca_param.cqe_size;
 993                 /* User still need to know when CQE > 32B */
 994                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 995         }
 996
 997         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 998         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
 999
1000         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
1001         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
1002                  hca_param.rss_ip_frags ? "on" : "off");
1003
1004         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
1005             dev->caps.bf_reg_size)
1006                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1007
1008         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
1009                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1010
1011         return 0;
1012
1013 err_mem:
1014         kfree(dev->caps.qp0_qkey);
1015         kfree(dev->caps.qp0_tunnel);
1016         kfree(dev->caps.qp0_proxy);
1017         kfree(dev->caps.qp1_tunnel);
1018         kfree(dev->caps.qp1_proxy);
1019         dev->caps.qp0_qkey = NULL;
1020         dev->caps.qp0_tunnel = NULL;
1021         dev->caps.qp0_proxy = NULL;
1022         dev->caps.qp1_tunnel = NULL;
1023         dev->caps.qp1_proxy = NULL;
1024
1025         return err;
1026 }
1027
1028 static void mlx4_request_modules(struct mlx4_dev *dev)
1029 {
1030         int port;
1031         int has_ib_port = false;
1032         int has_eth_port = false;
1033 #define EN_DRV_NAME     "mlx4_en"
1034 #define IB_DRV_NAME     "mlx4_ib"
1035
1036         for (port = 1; port <= dev->caps.num_ports; port++) {
1037                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1038                         has_ib_port = true;
1039                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1040                         has_eth_port = true;
1041         }
1042
1043         if (has_eth_port)
1044                 request_module_nowait(EN_DRV_NAME);
1045         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1046                 request_module_nowait(IB_DRV_NAME);
1047 }
1048
1049 /*
1050  * Change the port configuration of the device.
1051  * Every user of this function must hold the port mutex.
1052  */
1053 int mlx4_change_port_types(struct mlx4_dev *dev,
1054                            enum mlx4_port_type *port_types)
1055 {
1056         int err = 0;
1057         int change = 0;
1058         int port;
1059
1060         for (port = 0; port <  dev->caps.num_ports; port++) {
1061                 /* Change the port type only if the new type is different
1062                  * from the current, and not set to Auto */
1063                 if (port_types[port] != dev->caps.port_type[port + 1])
1064                         change = 1;
1065         }
1066         if (change) {
1067                 mlx4_unregister_device(dev);
1068                 for (port = 1; port <= dev->caps.num_ports; port++) {
1069                         mlx4_CLOSE_PORT(dev, port);
1070                         dev->caps.port_type[port] = port_types[port - 1];
1071                         err = mlx4_SET_PORT(dev, port, -1);
1072                         if (err) {
1073                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1074                                          port);
1075                                 goto out;
1076                         }
1077                 }
1078                 mlx4_set_port_mask(dev);
1079                 err = mlx4_register_device(dev);
1080                 if (err) {
1081                         mlx4_err(dev, "Failed to register device\n");
1082                         goto out;
1083                 }
1084                 mlx4_request_modules(dev);
1085         }
1086
1087 out:
1088         return err;
1089 }
1090
1091 static ssize_t show_port_type(struct device *dev,
1092                               struct device_attribute *attr,
1093                               char *buf)
1094 {
1095         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1096                                                    port_attr);
1097         struct mlx4_dev *mdev = info->dev;
1098         char type[8];
1099
1100         sprintf(type, "%s",
1101                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1102                 "ib" : "eth");
1103         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1104                 sprintf(buf, "auto (%s)\n", type);
1105         else
1106                 sprintf(buf, "%s\n", type);
1107
1108         return strlen(buf);
1109 }
1110
1111 static int __set_port_type(struct mlx4_port_info *info,
1112                            enum mlx4_port_type port_type)
1113 {
1114         struct mlx4_dev *mdev = info->dev;
1115         struct mlx4_priv *priv = mlx4_priv(mdev);
1116         enum mlx4_port_type types[MLX4_MAX_PORTS];
1117         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1118         int i;
1119         int err = 0;
1120
1121         if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1122                 mlx4_err(mdev,
1123                          "Requested port type for port %d is not supported on this HCA\n",
1124                          info->port);
1125                 return -EOPNOTSUPP;
1126         }
1127
1128         mlx4_stop_sense(mdev);
1129         mutex_lock(&priv->port_mutex);
1130         info->tmp_type = port_type;
1131
1132         /* Possible type is always the one that was delivered */
1133         mdev->caps.possible_type[info->port] = info->tmp_type;
1134
1135         for (i = 0; i < mdev->caps.num_ports; i++) {
1136                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1137                                         mdev->caps.possible_type[i+1];
1138                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1139                         types[i] = mdev->caps.port_type[i+1];
1140         }
1141
1142         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1143             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1144                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1145                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1146                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1147                                 err = -EOPNOTSUPP;
1148                         }
1149                 }
1150         }
1151         if (err) {
1152                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1153                 goto out;
1154         }
1155
1156         mlx4_do_sense_ports(mdev, new_types, types);
1157
1158         err = mlx4_check_port_params(mdev, new_types);
1159         if (err)
1160                 goto out;
1161
1162         /* We are about to apply the changes after the configuration
1163          * was verified, no need to remember the temporary types
1164          * any more */
1165         for (i = 0; i < mdev->caps.num_ports; i++)
1166                 priv->port[i + 1].tmp_type = 0;
1167
1168         err = mlx4_change_port_types(mdev, new_types);
1169
1170 out:
1171         mlx4_start_sense(mdev);
1172         mutex_unlock(&priv->port_mutex);
1173
1174         return err;
1175 }
1176
1177 static ssize_t set_port_type(struct device *dev,
1178                              struct device_attribute *attr,
1179                              const char *buf, size_t count)
1180 {
1181         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1182                                                    port_attr);
1183         struct mlx4_dev *mdev = info->dev;
1184         enum mlx4_port_type port_type;
1185         static DEFINE_MUTEX(set_port_type_mutex);
1186         int err;
1187
1188         mutex_lock(&set_port_type_mutex);
1189
1190         if (!strcmp(buf, "ib\n")) {
1191                 port_type = MLX4_PORT_TYPE_IB;
1192         } else if (!strcmp(buf, "eth\n")) {
1193                 port_type = MLX4_PORT_TYPE_ETH;
1194         } else if (!strcmp(buf, "auto\n")) {
1195                 port_type = MLX4_PORT_TYPE_AUTO;
1196         } else {
1197                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1198                 err = -EINVAL;
1199                 goto err_out;
1200         }
1201
1202         err = __set_port_type(info, port_type);
1203
1204 err_out:
1205         mutex_unlock(&set_port_type_mutex);
1206
1207         return err ? err : count;
1208 }
1209
1210 enum ibta_mtu {
1211         IB_MTU_256  = 1,
1212         IB_MTU_512  = 2,
1213         IB_MTU_1024 = 3,
1214         IB_MTU_2048 = 4,
1215         IB_MTU_4096 = 5
1216 };
1217
1218 static inline int int_to_ibta_mtu(int mtu)
1219 {
1220         switch (mtu) {
1221         case 256:  return IB_MTU_256;
1222         case 512:  return IB_MTU_512;
1223         case 1024: return IB_MTU_1024;
1224         case 2048: return IB_MTU_2048;
1225         case 4096: return IB_MTU_4096;
1226         default: return -1;
1227         }
1228 }
1229
1230 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1231 {
1232         switch (mtu) {
1233         case IB_MTU_256:  return  256;
1234         case IB_MTU_512:  return  512;
1235         case IB_MTU_1024: return 1024;
1236         case IB_MTU_2048: return 2048;
1237         case IB_MTU_4096: return 4096;
1238         default: return -1;
1239         }
1240 }
1241
1242 static ssize_t show_port_ib_mtu(struct device *dev,
1243                              struct device_attribute *attr,
1244                              char *buf)
1245 {
1246         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1247                                                    port_mtu_attr);
1248         struct mlx4_dev *mdev = info->dev;
1249
1250         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1251                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1252
1253         sprintf(buf, "%d\n",
1254                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1255         return strlen(buf);
1256 }
1257
1258 static ssize_t set_port_ib_mtu(struct device *dev,
1259                              struct device_attribute *attr,
1260                              const char *buf, size_t count)
1261 {
1262         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1263                                                    port_mtu_attr);
1264         struct mlx4_dev *mdev = info->dev;
1265         struct mlx4_priv *priv = mlx4_priv(mdev);
1266         int err, port, mtu, ibta_mtu = -1;
1267
1268         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1269                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1270                 return -EINVAL;
1271         }
1272
1273         err = kstrtoint(buf, 0, &mtu);
1274         if (!err)
1275                 ibta_mtu = int_to_ibta_mtu(mtu);
1276
1277         if (err || ibta_mtu < 0) {
1278                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1279                 return -EINVAL;
1280         }
1281
1282         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1283
1284         mlx4_stop_sense(mdev);
1285         mutex_lock(&priv->port_mutex);
1286         mlx4_unregister_device(mdev);
1287         for (port = 1; port <= mdev->caps.num_ports; port++) {
1288                 mlx4_CLOSE_PORT(mdev, port);
1289                 err = mlx4_SET_PORT(mdev, port, -1);
1290                 if (err) {
1291                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1292                                  port);
1293                         goto err_set_port;
1294                 }
1295         }
1296         err = mlx4_register_device(mdev);
1297 err_set_port:
1298         mutex_unlock(&priv->port_mutex);
1299         mlx4_start_sense(mdev);
1300         return err ? err : count;
1301 }
1302
1303 /* bond for multi-function device */
1304 #define MAX_MF_BOND_ALLOWED_SLAVES 63
1305 static int mlx4_mf_bond(struct mlx4_dev *dev)
1306 {
1307         int err = 0;
1308         int nvfs;
1309         struct mlx4_slaves_pport slaves_port1;
1310         struct mlx4_slaves_pport slaves_port2;
1311         DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1312
1313         slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1314         slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1315         bitmap_and(slaves_port_1_2,
1316                    slaves_port1.slaves, slaves_port2.slaves,
1317                    dev->persist->num_vfs + 1);
1318
1319         /* only single port vfs are allowed */
1320         if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1321                 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1322                 return -EINVAL;
1323         }
1324
1325         /* number of virtual functions is number of total functions minus one
1326          * physical function for each port.
1327          */
1328         nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1329                 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1330
1331         /* limit on maximum allowed VFs */
1332         if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1333                 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1334                           nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
1335                 return -EINVAL;
1336         }
1337
1338         if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1339                 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1340                 return -EINVAL;
1341         }
1342
1343         err = mlx4_bond_mac_table(dev);
1344         if (err)
1345                 return err;
1346         err = mlx4_bond_vlan_table(dev);
1347         if (err)
1348                 goto err1;
1349         err = mlx4_bond_fs_rules(dev);
1350         if (err)
1351                 goto err2;
1352
1353         return 0;
1354 err2:
1355         (void)mlx4_unbond_vlan_table(dev);
1356 err1:
1357         (void)mlx4_unbond_mac_table(dev);
1358         return err;
1359 }
1360
1361 static int mlx4_mf_unbond(struct mlx4_dev *dev)
1362 {
1363         int ret, ret1;
1364
1365         ret = mlx4_unbond_fs_rules(dev);
1366         if (ret)
1367                 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1368         ret1 = mlx4_unbond_mac_table(dev);
1369         if (ret1) {
1370                 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1371                 ret = ret1;
1372         }
1373         ret1 = mlx4_unbond_vlan_table(dev);
1374         if (ret1) {
1375                 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1376                 ret = ret1;
1377         }
1378         return ret;
1379 }
1380
1381 int mlx4_bond(struct mlx4_dev *dev)
1382 {
1383         int ret = 0;
1384         struct mlx4_priv *priv = mlx4_priv(dev);
1385
1386         mutex_lock(&priv->bond_mutex);
1387
1388         if (!mlx4_is_bonded(dev)) {
1389                 ret = mlx4_do_bond(dev, true);
1390                 if (ret)
1391                         mlx4_err(dev, "Failed to bond device: %d\n", ret);
1392                 if (!ret && mlx4_is_master(dev)) {
1393                         ret = mlx4_mf_bond(dev);
1394                         if (ret) {
1395                                 mlx4_err(dev, "bond for multifunction failed\n");
1396                                 mlx4_do_bond(dev, false);
1397                         }
1398                 }
1399         }
1400
1401         mutex_unlock(&priv->bond_mutex);
1402         if (!ret)
1403                 mlx4_dbg(dev, "Device is bonded\n");
1404
1405         return ret;
1406 }
1407 EXPORT_SYMBOL_GPL(mlx4_bond);
1408
1409 int mlx4_unbond(struct mlx4_dev *dev)
1410 {
1411         int ret = 0;
1412         struct mlx4_priv *priv = mlx4_priv(dev);
1413
1414         mutex_lock(&priv->bond_mutex);
1415
1416         if (mlx4_is_bonded(dev)) {
1417                 int ret2 = 0;
1418
1419                 ret = mlx4_do_bond(dev, false);
1420                 if (ret)
1421                         mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1422                 if (mlx4_is_master(dev))
1423                         ret2 = mlx4_mf_unbond(dev);
1424                 if (ret2) {
1425                         mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1426                         ret = ret2;
1427                 }
1428         }
1429
1430         mutex_unlock(&priv->bond_mutex);
1431         if (!ret)
1432                 mlx4_dbg(dev, "Device is unbonded\n");
1433
1434         return ret;
1435 }
1436 EXPORT_SYMBOL_GPL(mlx4_unbond);
1437
1438
1439 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1440 {
1441         u8 port1 = v2p->port1;
1442         u8 port2 = v2p->port2;
1443         struct mlx4_priv *priv = mlx4_priv(dev);
1444         int err;
1445
1446         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1447                 return -ENOTSUPP;
1448
1449         mutex_lock(&priv->bond_mutex);
1450
1451         /* zero means keep current mapping for this port */
1452         if (port1 == 0)
1453                 port1 = priv->v2p.port1;
1454         if (port2 == 0)
1455                 port2 = priv->v2p.port2;
1456
1457         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1458             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1459             (port1 == 2 && port2 == 1)) {
1460                 /* besides boundary checks cross mapping makes
1461                  * no sense and therefore not allowed */
1462                 err = -EINVAL;
1463         } else if ((port1 == priv->v2p.port1) &&
1464                  (port2 == priv->v2p.port2)) {
1465                 err = 0;
1466         } else {
1467                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1468                 if (!err) {
1469                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1470                                  port1, port2);
1471                         priv->v2p.port1 = port1;
1472                         priv->v2p.port2 = port2;
1473                 } else {
1474                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1475                 }
1476         }
1477
1478         mutex_unlock(&priv->bond_mutex);
1479         return err;
1480 }
1481 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1482
1483 static int mlx4_load_fw(struct mlx4_dev *dev)
1484 {
1485         struct mlx4_priv *priv = mlx4_priv(dev);
1486         int err;
1487
1488         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1489                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1490         if (!priv->fw.fw_icm) {
1491                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1492                 return -ENOMEM;
1493         }
1494
1495         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1496         if (err) {
1497                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1498                 goto err_free;
1499         }
1500
1501         err = mlx4_RUN_FW(dev);
1502         if (err) {
1503                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1504                 goto err_unmap_fa;
1505         }
1506
1507         return 0;
1508
1509 err_unmap_fa:
1510         mlx4_UNMAP_FA(dev);
1511
1512 err_free:
1513         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1514         return err;
1515 }
1516
1517 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1518                                 int cmpt_entry_sz)
1519 {
1520         struct mlx4_priv *priv = mlx4_priv(dev);
1521         int err;
1522         int num_eqs;
1523
1524         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1525                                   cmpt_base +
1526                                   ((u64) (MLX4_CMPT_TYPE_QP *
1527                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1528                                   cmpt_entry_sz, dev->caps.num_qps,
1529                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1530                                   0, 0);
1531         if (err)
1532                 goto err;
1533
1534         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1535                                   cmpt_base +
1536                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1537                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1538                                   cmpt_entry_sz, dev->caps.num_srqs,
1539                                   dev->caps.reserved_srqs, 0, 0);
1540         if (err)
1541                 goto err_qp;
1542
1543         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1544                                   cmpt_base +
1545                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1546                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1547                                   cmpt_entry_sz, dev->caps.num_cqs,
1548                                   dev->caps.reserved_cqs, 0, 0);
1549         if (err)
1550                 goto err_srq;
1551
1552         num_eqs = dev->phys_caps.num_phys_eqs;
1553         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1554                                   cmpt_base +
1555                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1556                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1557                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1558         if (err)
1559                 goto err_cq;
1560
1561         return 0;
1562
1563 err_cq:
1564         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1565
1566 err_srq:
1567         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1568
1569 err_qp:
1570         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1571
1572 err:
1573         return err;
1574 }
1575
1576 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1577                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1578 {
1579         struct mlx4_priv *priv = mlx4_priv(dev);
1580         u64 aux_pages;
1581         int num_eqs;
1582         int err;
1583
1584         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1585         if (err) {
1586                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1587                 return err;
1588         }
1589
1590         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1591                  (unsigned long long) icm_size >> 10,
1592                  (unsigned long long) aux_pages << 2);
1593
1594         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1595                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1596         if (!priv->fw.aux_icm) {
1597                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1598                 return -ENOMEM;
1599         }
1600
1601         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1602         if (err) {
1603                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1604                 goto err_free_aux;
1605         }
1606
1607         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1608         if (err) {
1609                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1610                 goto err_unmap_aux;
1611         }
1612
1613
1614         num_eqs = dev->phys_caps.num_phys_eqs;
1615         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1616                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1617                                   num_eqs, num_eqs, 0, 0);
1618         if (err) {
1619                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1620                 goto err_unmap_cmpt;
1621         }
1622
1623         /*
1624          * Reserved MTT entries must be aligned up to a cacheline
1625          * boundary, since the FW will write to them, while the driver
1626          * writes to all other MTT entries. (The variable
1627          * dev->caps.mtt_entry_sz below is really the MTT segment
1628          * size, not the raw entry size)
1629          */
1630         dev->caps.reserved_mtts =
1631                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1632                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1633
1634         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1635                                   init_hca->mtt_base,
1636                                   dev->caps.mtt_entry_sz,
1637                                   dev->caps.num_mtts,
1638                                   dev->caps.reserved_mtts, 1, 0);
1639         if (err) {
1640                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1641                 goto err_unmap_eq;
1642         }
1643
1644         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1645                                   init_hca->dmpt_base,
1646                                   dev_cap->dmpt_entry_sz,
1647                                   dev->caps.num_mpts,
1648                                   dev->caps.reserved_mrws, 1, 1);
1649         if (err) {
1650                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1651                 goto err_unmap_mtt;
1652         }
1653
1654         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1655                                   init_hca->qpc_base,
1656                                   dev_cap->qpc_entry_sz,
1657                                   dev->caps.num_qps,
1658                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1659                                   0, 0);
1660         if (err) {
1661                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1662                 goto err_unmap_dmpt;
1663         }
1664
1665         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1666                                   init_hca->auxc_base,
1667                                   dev_cap->aux_entry_sz,
1668                                   dev->caps.num_qps,
1669                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1670                                   0, 0);
1671         if (err) {
1672                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1673                 goto err_unmap_qp;
1674         }
1675
1676         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1677                                   init_hca->altc_base,
1678                                   dev_cap->altc_entry_sz,
1679                                   dev->caps.num_qps,
1680                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1681                                   0, 0);
1682         if (err) {
1683                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1684                 goto err_unmap_auxc;
1685         }
1686
1687         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1688                                   init_hca->rdmarc_base,
1689                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1690                                   dev->caps.num_qps,
1691                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1692                                   0, 0);
1693         if (err) {
1694                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1695                 goto err_unmap_altc;
1696         }
1697
1698         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1699                                   init_hca->cqc_base,
1700                                   dev_cap->cqc_entry_sz,
1701                                   dev->caps.num_cqs,
1702                                   dev->caps.reserved_cqs, 0, 0);
1703         if (err) {
1704                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1705                 goto err_unmap_rdmarc;
1706         }
1707
1708         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1709                                   init_hca->srqc_base,
1710                                   dev_cap->srq_entry_sz,
1711                                   dev->caps.num_srqs,
1712                                   dev->caps.reserved_srqs, 0, 0);
1713         if (err) {
1714                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1715                 goto err_unmap_cq;
1716         }
1717
1718         /*
1719          * For flow steering device managed mode it is required to use
1720          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1721          * required, but for simplicity just map the whole multicast
1722          * group table now.  The table isn't very big and it's a lot
1723          * easier than trying to track ref counts.
1724          */
1725         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1726                                   init_hca->mc_base,
1727                                   mlx4_get_mgm_entry_size(dev),
1728                                   dev->caps.num_mgms + dev->caps.num_amgms,
1729                                   dev->caps.num_mgms + dev->caps.num_amgms,
1730                                   0, 0);
1731         if (err) {
1732                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1733                 goto err_unmap_srq;
1734         }
1735
1736         return 0;
1737
1738 err_unmap_srq:
1739         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1740
1741 err_unmap_cq:
1742         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1743
1744 err_unmap_rdmarc:
1745         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1746
1747 err_unmap_altc:
1748         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1749
1750 err_unmap_auxc:
1751         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1752
1753 err_unmap_qp:
1754         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1755
1756 err_unmap_dmpt:
1757         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1758
1759 err_unmap_mtt:
1760         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1761
1762 err_unmap_eq:
1763         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1764
1765 err_unmap_cmpt:
1766         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1767         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1768         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1769         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1770
1771 err_unmap_aux:
1772         mlx4_UNMAP_ICM_AUX(dev);
1773
1774 err_free_aux:
1775         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1776
1777         return err;
1778 }
1779
1780 static void mlx4_free_icms(struct mlx4_dev *dev)
1781 {
1782         struct mlx4_priv *priv = mlx4_priv(dev);
1783
1784         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1785         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1786         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1787         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1788         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1789         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1790         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1791         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1792         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1793         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1794         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1795         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1796         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1797         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1798
1799         mlx4_UNMAP_ICM_AUX(dev);
1800         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1801 }
1802
1803 static void mlx4_slave_exit(struct mlx4_dev *dev)
1804 {
1805         struct mlx4_priv *priv = mlx4_priv(dev);
1806
1807         mutex_lock(&priv->cmd.slave_cmd_mutex);
1808         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1809                           MLX4_COMM_TIME))
1810                 mlx4_warn(dev, "Failed to close slave function\n");
1811         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1812 }
1813
1814 static int map_bf_area(struct mlx4_dev *dev)
1815 {
1816         struct mlx4_priv *priv = mlx4_priv(dev);
1817         resource_size_t bf_start;
1818         resource_size_t bf_len;
1819         int err = 0;
1820
1821         if (!dev->caps.bf_reg_size)
1822                 return -ENXIO;
1823
1824         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1825                         (dev->caps.num_uars << PAGE_SHIFT);
1826         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1827                         (dev->caps.num_uars << PAGE_SHIFT);
1828         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1829         if (!priv->bf_mapping)
1830                 err = -ENOMEM;
1831
1832         return err;
1833 }
1834
1835 static void unmap_bf_area(struct mlx4_dev *dev)
1836 {
1837         if (mlx4_priv(dev)->bf_mapping)
1838                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1839 }
1840
1841 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1842 {
1843         u32 clockhi, clocklo, clockhi1;
1844         cycle_t cycles;
1845         int i;
1846         struct mlx4_priv *priv = mlx4_priv(dev);
1847
1848         for (i = 0; i < 10; i++) {
1849                 clockhi = swab32(readl(priv->clock_mapping));
1850                 clocklo = swab32(readl(priv->clock_mapping + 4));
1851                 clockhi1 = swab32(readl(priv->clock_mapping));
1852                 if (clockhi == clockhi1)
1853                         break;
1854         }
1855
1856         cycles = (u64) clockhi << 32 | (u64) clocklo;
1857
1858         return cycles;
1859 }
1860 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1861
1862
1863 static int map_internal_clock(struct mlx4_dev *dev)
1864 {
1865         struct mlx4_priv *priv = mlx4_priv(dev);
1866
1867         priv->clock_mapping =
1868                 ioremap(pci_resource_start(dev->persist->pdev,
1869                                            priv->fw.clock_bar) +
1870                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1871
1872         if (!priv->clock_mapping)
1873                 return -ENOMEM;
1874
1875         return 0;
1876 }
1877
1878 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1879                                    struct mlx4_clock_params *params)
1880 {
1881         struct mlx4_priv *priv = mlx4_priv(dev);
1882
1883         if (mlx4_is_slave(dev))
1884                 return -ENOTSUPP;
1885
1886         if (!params)
1887                 return -EINVAL;
1888
1889         params->bar = priv->fw.clock_bar;
1890         params->offset = priv->fw.clock_offset;
1891         params->size = MLX4_CLOCK_SIZE;
1892
1893         return 0;
1894 }
1895 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1896
1897 static void unmap_internal_clock(struct mlx4_dev *dev)
1898 {
1899         struct mlx4_priv *priv = mlx4_priv(dev);
1900
1901         if (priv->clock_mapping)
1902                 iounmap(priv->clock_mapping);
1903 }
1904
1905 static void mlx4_close_hca(struct mlx4_dev *dev)
1906 {
1907         unmap_internal_clock(dev);
1908         unmap_bf_area(dev);
1909         if (mlx4_is_slave(dev))
1910                 mlx4_slave_exit(dev);
1911         else {
1912                 mlx4_CLOSE_HCA(dev, 0);
1913                 mlx4_free_icms(dev);
1914         }
1915 }
1916
1917 static void mlx4_close_fw(struct mlx4_dev *dev)
1918 {
1919         if (!mlx4_is_slave(dev)) {
1920                 mlx4_UNMAP_FA(dev);
1921                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1922         }
1923 }
1924
1925 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1926 {
1927 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1928
1929         u32 comm_flags;
1930         u32 offline_bit;
1931         unsigned long end;
1932         struct mlx4_priv *priv = mlx4_priv(dev);
1933
1934         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1935         while (time_before(jiffies, end)) {
1936                 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1937                                           MLX4_COMM_CHAN_FLAGS));
1938                 offline_bit = (comm_flags &
1939                                (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1940                 if (!offline_bit)
1941                         return 0;
1942
1943                 /* If device removal has been requested,
1944                  * do not continue retrying.
1945                  */
1946                 if (dev->persist->interface_state &
1947                     MLX4_INTERFACE_STATE_NOWAIT)
1948                         break;
1949
1950                 /* There are cases as part of AER/Reset flow that PF needs
1951                  * around 100 msec to load. We therefore sleep for 100 msec
1952                  * to allow other tasks to make use of that CPU during this
1953                  * time interval.
1954                  */
1955                 msleep(100);
1956         }
1957         mlx4_err(dev, "Communication channel is offline.\n");
1958         return -EIO;
1959 }
1960
1961 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1962 {
1963 #define COMM_CHAN_RST_OFFSET 0x1e
1964
1965         struct mlx4_priv *priv = mlx4_priv(dev);
1966         u32 comm_rst;
1967         u32 comm_caps;
1968
1969         comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1970                                  MLX4_COMM_CHAN_CAPS));
1971         comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1972
1973         if (comm_rst)
1974                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1975 }
1976
1977 static int mlx4_init_slave(struct mlx4_dev *dev)
1978 {
1979         struct mlx4_priv *priv = mlx4_priv(dev);
1980         u64 dma = (u64) priv->mfunc.vhcr_dma;
1981         int ret_from_reset = 0;
1982         u32 slave_read;
1983         u32 cmd_channel_ver;
1984
1985         if (atomic_read(&pf_loading)) {
1986                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1987                 return -EPROBE_DEFER;
1988         }
1989
1990         mutex_lock(&priv->cmd.slave_cmd_mutex);
1991         priv->cmd.max_cmds = 1;
1992         if (mlx4_comm_check_offline(dev)) {
1993                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1994                 goto err_offline;
1995         }
1996
1997         mlx4_reset_vf_support(dev);
1998         mlx4_warn(dev, "Sending reset\n");
1999         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
2000                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
2001         /* if we are in the middle of flr the slave will try
2002          * NUM_OF_RESET_RETRIES times before leaving.*/
2003         if (ret_from_reset) {
2004                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
2005                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
2006                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2007                         return -EPROBE_DEFER;
2008                 } else
2009                         goto err;
2010         }
2011
2012         /* check the driver version - the slave I/F revision
2013          * must match the master's */
2014         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
2015         cmd_channel_ver = mlx4_comm_get_version();
2016
2017         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
2018                 MLX4_COMM_GET_IF_REV(slave_read)) {
2019                 mlx4_err(dev, "slave driver version is not supported by the master\n");
2020                 goto err;
2021         }
2022
2023         mlx4_warn(dev, "Sending vhcr0\n");
2024         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
2025                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2026                 goto err;
2027         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
2028                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2029                 goto err;
2030         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
2031                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2032                 goto err;
2033         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
2034                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2035                 goto err;
2036
2037         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2038         return 0;
2039
2040 err:
2041         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
2042 err_offline:
2043         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2044         return -EIO;
2045 }
2046
2047 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2048 {
2049         int i;
2050
2051         for (i = 1; i <= dev->caps.num_ports; i++) {
2052                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2053                         dev->caps.gid_table_len[i] =
2054                                 mlx4_get_slave_num_gids(dev, 0, i);
2055                 else
2056                         dev->caps.gid_table_len[i] = 1;
2057                 dev->caps.pkey_table_len[i] =
2058                         dev->phys_caps.pkey_phys_table_len[i] - 1;
2059         }
2060 }
2061
2062 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2063 {
2064         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2065
2066         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2067               i++) {
2068                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2069                         break;
2070         }
2071
2072         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2073 }
2074
2075 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2076 {
2077         switch (dmfs_high_steer_mode) {
2078         case MLX4_STEERING_DMFS_A0_DEFAULT:
2079                 return "default performance";
2080
2081         case MLX4_STEERING_DMFS_A0_DYNAMIC:
2082                 return "dynamic hybrid mode";
2083
2084         case MLX4_STEERING_DMFS_A0_STATIC:
2085                 return "performance optimized for limited rule configuration (static)";
2086
2087         case MLX4_STEERING_DMFS_A0_DISABLE:
2088                 return "disabled performance optimized steering";
2089
2090         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2091                 return "performance optimized steering not supported";
2092
2093         default:
2094                 return "Unrecognized mode";
2095         }
2096 }
2097
2098 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
2099
2100 static void choose_steering_mode(struct mlx4_dev *dev,
2101                                  struct mlx4_dev_cap *dev_cap)
2102 {
2103         if (mlx4_log_num_mgm_entry_size <= 0) {
2104                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2105                         if (dev->caps.dmfs_high_steer_mode ==
2106                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2107                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
2108                         else
2109                                 dev->caps.dmfs_high_steer_mode =
2110                                         MLX4_STEERING_DMFS_A0_STATIC;
2111                 }
2112         }
2113
2114         if (mlx4_log_num_mgm_entry_size <= 0 &&
2115             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
2116             (!mlx4_is_mfunc(dev) ||
2117              (dev_cap->fs_max_num_qp_per_entry >=
2118              (dev->persist->num_vfs + 1))) &&
2119             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2120                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2121                 dev->oper_log_mgm_entry_size =
2122                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
2123                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2124                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2125                 dev->caps.fs_log_max_ucast_qp_range_size =
2126                         dev_cap->fs_log_max_ucast_qp_range_size;
2127         } else {
2128                 if (dev->caps.dmfs_high_steer_mode !=
2129                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2130                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2131                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2132                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2133                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2134                 else {
2135                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2136
2137                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2138                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2139                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
2140                 }
2141                 dev->oper_log_mgm_entry_size =
2142                         mlx4_log_num_mgm_entry_size > 0 ?
2143                         mlx4_log_num_mgm_entry_size :
2144                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2145                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2146         }
2147         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
2148                  mlx4_steering_mode_str(dev->caps.steering_mode),
2149                  dev->oper_log_mgm_entry_size,
2150                  mlx4_log_num_mgm_entry_size);
2151 }
2152
2153 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2154                                        struct mlx4_dev_cap *dev_cap)
2155 {
2156         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2157             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
2158                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2159         else
2160                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2161
2162         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
2163                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2164 }
2165
2166 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2167 {
2168         int i;
2169         struct mlx4_port_cap port_cap;
2170
2171         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2172                 return -EINVAL;
2173
2174         for (i = 1; i <= dev->caps.num_ports; i++) {
2175                 if (mlx4_dev_port(dev, i, &port_cap)) {
2176                         mlx4_err(dev,
2177                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2178                 } else if ((dev->caps.dmfs_high_steer_mode !=
2179                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
2180                            (port_cap.dmfs_optimized_state ==
2181                             !!(dev->caps.dmfs_high_steer_mode ==
2182                             MLX4_STEERING_DMFS_A0_DISABLE))) {
2183                         mlx4_err(dev,
2184                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2185                                  dmfs_high_rate_steering_mode_str(
2186                                         dev->caps.dmfs_high_steer_mode),
2187                                  (port_cap.dmfs_optimized_state ?
2188                                         "enabled" : "disabled"));
2189                 }
2190         }
2191
2192         return 0;
2193 }
2194
2195 static int mlx4_init_fw(struct mlx4_dev *dev)
2196 {
2197         struct mlx4_mod_stat_cfg   mlx4_cfg;
2198         int err = 0;
2199
2200         if (!mlx4_is_slave(dev)) {
2201                 err = mlx4_QUERY_FW(dev);
2202                 if (err) {
2203                         if (err == -EACCES)
2204                                 mlx4_info(dev, "non-primary physical function, skipping\n");
2205                         else
2206                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2207                         return err;
2208                 }
2209
2210                 err = mlx4_load_fw(dev);
2211                 if (err) {
2212                         mlx4_err(dev, "Failed to start FW, aborting\n");
2213                         return err;
2214                 }
2215
2216                 mlx4_cfg.log_pg_sz_m = 1;
2217                 mlx4_cfg.log_pg_sz = 0;
2218                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2219                 if (err)
2220                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2221         }
2222
2223         return err;
2224 }
2225
2226 static int mlx4_init_hca(struct mlx4_dev *dev)
2227 {
2228         struct mlx4_priv          *priv = mlx4_priv(dev);
2229         struct mlx4_adapter        adapter;
2230         struct mlx4_dev_cap        dev_cap;
2231         struct mlx4_profile        profile;
2232         struct mlx4_init_hca_param init_hca;
2233         u64 icm_size;
2234         struct mlx4_config_dev_params params;
2235         int err;
2236
2237         if (!mlx4_is_slave(dev)) {
2238                 err = mlx4_dev_cap(dev, &dev_cap);
2239                 if (err) {
2240                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2241                         return err;
2242                 }
2243
2244                 choose_steering_mode(dev, &dev_cap);
2245                 choose_tunnel_offload_mode(dev, &dev_cap);
2246
2247                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2248                     mlx4_is_master(dev))
2249                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2250
2251                 err = mlx4_get_phys_port_id(dev);
2252                 if (err)
2253                         mlx4_err(dev, "Fail to get physical port id\n");
2254
2255                 if (mlx4_is_master(dev))
2256                         mlx4_parav_master_pf_caps(dev);
2257
2258                 if (mlx4_low_memory_profile()) {
2259                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2260                         profile = low_mem_profile;
2261                 } else {
2262                         profile = default_profile;
2263                 }
2264                 if (dev->caps.steering_mode ==
2265                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2266                         profile.num_mcg = MLX4_FS_NUM_MCG;
2267
2268                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2269                                              &init_hca);
2270                 if ((long long) icm_size < 0) {
2271                         err = icm_size;
2272                         return err;
2273                 }
2274
2275                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2276
2277                 if (enable_4k_uar || !dev->persist->num_vfs) {
2278                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2279                                                     PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2280                         init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2281                 } else {
2282                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2283                         init_hca.uar_page_sz = PAGE_SHIFT - 12;
2284                 }
2285
2286                 init_hca.mw_enabled = 0;
2287                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2288                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2289                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2290
2291                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2292                 if (err)
2293                         return err;
2294
2295                 err = mlx4_INIT_HCA(dev, &init_hca);
2296                 if (err) {
2297                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2298                         goto err_free_icm;
2299                 }
2300
2301                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2302                         err = mlx4_query_func(dev, &dev_cap);
2303                         if (err < 0) {
2304                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2305                                 goto err_close;
2306                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2307                                 dev->caps.num_eqs = dev_cap.max_eqs;
2308                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2309                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2310                         }
2311                 }
2312
2313                 /*
2314                  * If TS is supported by FW
2315                  * read HCA frequency by QUERY_HCA command
2316                  */
2317                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2318                         memset(&init_hca, 0, sizeof(init_hca));
2319                         err = mlx4_QUERY_HCA(dev, &init_hca);
2320                         if (err) {
2321                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2322                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2323                         } else {
2324                                 dev->caps.hca_core_clock =
2325                                         init_hca.hca_core_clock;
2326                         }
2327
2328                         /* In case we got HCA frequency 0 - disable timestamping
2329                          * to avoid dividing by zero
2330                          */
2331                         if (!dev->caps.hca_core_clock) {
2332                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2333                                 mlx4_err(dev,
2334                                          "HCA frequency is 0 - timestamping is not supported\n");
2335                         } else if (map_internal_clock(dev)) {
2336                                 /*
2337                                  * Map internal clock,
2338                                  * in case of failure disable timestamping
2339                                  */
2340                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2341                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2342                         }
2343                 }
2344
2345                 if (dev->caps.dmfs_high_steer_mode !=
2346                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2347                         if (mlx4_validate_optimized_steering(dev))
2348                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2349
2350                         if (dev->caps.dmfs_high_steer_mode ==
2351                             MLX4_STEERING_DMFS_A0_DISABLE) {
2352                                 dev->caps.dmfs_high_rate_qpn_base =
2353                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2354                                 dev->caps.dmfs_high_rate_qpn_range =
2355                                         MLX4_A0_STEERING_TABLE_SIZE;
2356                         }
2357
2358                         mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2359                                  dmfs_high_rate_steering_mode_str(
2360                                         dev->caps.dmfs_high_steer_mode));
2361                 }
2362         } else {
2363                 err = mlx4_init_slave(dev);
2364                 if (err) {
2365                         if (err != -EPROBE_DEFER)
2366                                 mlx4_err(dev, "Failed to initialize slave\n");
2367                         return err;
2368                 }
2369
2370                 err = mlx4_slave_cap(dev);
2371                 if (err) {
2372                         mlx4_err(dev, "Failed to obtain slave caps\n");
2373                         goto err_close;
2374                 }
2375         }
2376
2377         if (map_bf_area(dev))
2378                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2379
2380         /*Only the master set the ports, all the rest got it from it.*/
2381         if (!mlx4_is_slave(dev))
2382                 mlx4_set_port_mask(dev);
2383
2384         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2385         if (err) {
2386                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2387                 goto unmap_bf;
2388         }
2389
2390         /* Query CONFIG_DEV parameters */
2391         err = mlx4_config_dev_retrieval(dev, &params);
2392         if (err && err != -ENOTSUPP) {
2393                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2394         } else if (!err) {
2395                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2396                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2397         }
2398         priv->eq_table.inta_pin = adapter.inta_pin;
2399         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2400
2401         return 0;
2402
2403 unmap_bf:
2404         unmap_internal_clock(dev);
2405         unmap_bf_area(dev);
2406
2407         if (mlx4_is_slave(dev)) {
2408                 kfree(dev->caps.qp0_qkey);
2409                 kfree(dev->caps.qp0_tunnel);
2410                 kfree(dev->caps.qp0_proxy);
2411                 kfree(dev->caps.qp1_tunnel);
2412                 kfree(dev->caps.qp1_proxy);
2413         }
2414
2415 err_close:
2416         if (mlx4_is_slave(dev))
2417                 mlx4_slave_exit(dev);
2418         else
2419                 mlx4_CLOSE_HCA(dev, 0);
2420
2421 err_free_icm:
2422         if (!mlx4_is_slave(dev))
2423                 mlx4_free_icms(dev);
2424
2425         return err;
2426 }
2427
2428 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2429 {
2430         struct mlx4_priv *priv = mlx4_priv(dev);
2431         int nent_pow2;
2432
2433         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2434                 return -ENOENT;
2435
2436         if (!dev->caps.max_counters)
2437                 return -ENOSPC;
2438
2439         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2440         /* reserve last counter index for sink counter */
2441         return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2442                                 nent_pow2 - 1, 0,
2443                                 nent_pow2 - dev->caps.max_counters + 1);
2444 }
2445
2446 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2447 {
2448         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2449                 return;
2450
2451         if (!dev->caps.max_counters)
2452                 return;
2453
2454         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2455 }
2456
2457 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2458 {
2459         struct mlx4_priv *priv = mlx4_priv(dev);
2460         int port;
2461
2462         for (port = 0; port < dev->caps.num_ports; port++)
2463                 if (priv->def_counter[port] != -1)
2464                         mlx4_counter_free(dev,  priv->def_counter[port]);
2465 }
2466
2467 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2468 {
2469         struct mlx4_priv *priv = mlx4_priv(dev);
2470         int port, err = 0;
2471         u32 idx;
2472
2473         for (port = 0; port < dev->caps.num_ports; port++)
2474                 priv->def_counter[port] = -1;
2475
2476         for (port = 0; port < dev->caps.num_ports; port++) {
2477                 err = mlx4_counter_alloc(dev, &idx);
2478
2479                 if (!err || err == -ENOSPC) {
2480                         priv->def_counter[port] = idx;
2481                         err = 0;
2482                 } else if (err == -ENOENT) {
2483                         err = 0;
2484                         continue;
2485                 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2486                         priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2487                         mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2488                                   MLX4_SINK_COUNTER_INDEX(dev));
2489                         err = 0;
2490                 } else {
2491                         mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2492                                  __func__, port + 1, err);
2493                         mlx4_cleanup_default_counters(dev);
2494                         return err;
2495                 }
2496
2497                 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2498                          __func__, priv->def_counter[port], port + 1);
2499         }
2500
2501         return err;
2502 }
2503
2504 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2505 {
2506         struct mlx4_priv *priv = mlx4_priv(dev);
2507
2508         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2509                 return -ENOENT;
2510
2511         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2512         if (*idx == -1) {
2513                 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2514                 return -ENOSPC;
2515         }
2516
2517         return 0;
2518 }
2519
2520 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2521 {
2522         u64 out_param;
2523         int err;
2524
2525         if (mlx4_is_mfunc(dev)) {
2526                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2527                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2528                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2529                 if (!err)
2530                         *idx = get_param_l(&out_param);
2531                 if (WARN_ON(err == -ENOSPC))
2532                         err = -EINVAL;
2533                 return err;
2534         }
2535         return __mlx4_counter_alloc(dev, idx);
2536 }
2537 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2538
2539 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2540                                 u8 counter_index)
2541 {
2542         struct mlx4_cmd_mailbox *if_stat_mailbox;
2543         int err;
2544         u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2545
2546         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2547         if (IS_ERR(if_stat_mailbox))
2548                 return PTR_ERR(if_stat_mailbox);
2549
2550         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2551                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2552                            MLX4_CMD_NATIVE);
2553
2554         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2555         return err;
2556 }
2557
2558 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2559 {
2560         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2561                 return;
2562
2563         if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2564                 return;
2565
2566         __mlx4_clear_if_stat(dev, idx);
2567
2568         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2569         return;
2570 }
2571
2572 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2573 {
2574         u64 in_param = 0;
2575
2576         if (mlx4_is_mfunc(dev)) {
2577                 set_param_l(&in_param, idx);
2578                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2579                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2580                          MLX4_CMD_WRAPPED);
2581                 return;
2582         }
2583         __mlx4_counter_free(dev, idx);
2584 }
2585 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2586
2587 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2588 {
2589         struct mlx4_priv *priv = mlx4_priv(dev);
2590
2591         return priv->def_counter[port - 1];
2592 }
2593 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2594
2595 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2596 {
2597         struct mlx4_priv *priv = mlx4_priv(dev);
2598
2599         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2600 }
2601 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2602
2603 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2604 {
2605         struct mlx4_priv *priv = mlx4_priv(dev);
2606
2607         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2608 }
2609 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2610
2611 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2612 {
2613         struct mlx4_priv *priv = mlx4_priv(dev);
2614         __be64 guid;
2615
2616         /* hw GUID */
2617         if (entry == 0)
2618                 return;
2619
2620         get_random_bytes((char *)&guid, sizeof(guid));
2621         guid &= ~(cpu_to_be64(1ULL << 56));
2622         guid |= cpu_to_be64(1ULL << 57);
2623         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2624 }
2625
2626 static int mlx4_setup_hca(struct mlx4_dev *dev)
2627 {
2628         struct mlx4_priv *priv = mlx4_priv(dev);
2629         int err;
2630         int port;
2631         __be32 ib_port_default_caps;
2632
2633         err = mlx4_init_uar_table(dev);
2634         if (err) {
2635                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2636                 return err;
2637         }
2638
2639         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2640         if (err) {
2641                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2642                 goto err_uar_table_free;
2643         }
2644
2645         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2646         if (!priv->kar) {
2647                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2648                 err = -ENOMEM;
2649                 goto err_uar_free;
2650         }
2651
2652         err = mlx4_init_pd_table(dev);
2653         if (err) {
2654                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2655                 goto err_kar_unmap;
2656         }
2657
2658         err = mlx4_init_xrcd_table(dev);
2659         if (err) {
2660                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2661                 goto err_pd_table_free;
2662         }
2663
2664         err = mlx4_init_mr_table(dev);
2665         if (err) {
2666                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2667                 goto err_xrcd_table_free;
2668         }
2669
2670         if (!mlx4_is_slave(dev)) {
2671                 err = mlx4_init_mcg_table(dev);
2672                 if (err) {
2673                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2674                         goto err_mr_table_free;
2675                 }
2676                 err = mlx4_config_mad_demux(dev);
2677                 if (err) {
2678                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2679                         goto err_mcg_table_free;
2680                 }
2681         }
2682
2683         err = mlx4_init_eq_table(dev);
2684         if (err) {
2685                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2686                 goto err_mcg_table_free;
2687         }
2688
2689         err = mlx4_cmd_use_events(dev);
2690         if (err) {
2691                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2692                 goto err_eq_table_free;
2693         }
2694
2695         err = mlx4_NOP(dev);
2696         if (err) {
2697                 if (dev->flags & MLX4_FLAG_MSI_X) {
2698                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2699                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2700                         mlx4_warn(dev, "Trying again without MSI-X\n");
2701                 } else {
2702                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2703                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2704                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2705                 }
2706
2707                 goto err_cmd_poll;
2708         }
2709
2710         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2711
2712         err = mlx4_init_cq_table(dev);
2713         if (err) {
2714                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2715                 goto err_cmd_poll;
2716         }
2717
2718         err = mlx4_init_srq_table(dev);
2719         if (err) {
2720                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2721                 goto err_cq_table_free;
2722         }
2723
2724         err = mlx4_init_qp_table(dev);
2725         if (err) {
2726                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2727                 goto err_srq_table_free;
2728         }
2729
2730         if (!mlx4_is_slave(dev)) {
2731                 err = mlx4_init_counters_table(dev);
2732                 if (err && err != -ENOENT) {
2733                         mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2734                         goto err_qp_table_free;
2735                 }
2736         }
2737
2738         err = mlx4_allocate_default_counters(dev);
2739         if (err) {
2740                 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2741                 goto err_counters_table_free;
2742         }
2743
2744         if (!mlx4_is_slave(dev)) {
2745                 for (port = 1; port <= dev->caps.num_ports; port++) {
2746                         ib_port_default_caps = 0;
2747                         err = mlx4_get_port_ib_caps(dev, port,
2748                                                     &ib_port_default_caps);
2749                         if (err)
2750                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2751                                           port, err);
2752                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2753
2754                         /* initialize per-slave default ib port capabilities */
2755                         if (mlx4_is_master(dev)) {
2756                                 int i;
2757                                 for (i = 0; i < dev->num_slaves; i++) {
2758                                         if (i == mlx4_master_func_num(dev))
2759                                                 continue;
2760                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2761                                                 ib_port_default_caps;
2762                                 }
2763                         }
2764
2765                         if (mlx4_is_mfunc(dev))
2766                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2767                         else
2768                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2769
2770                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2771                                             dev->caps.pkey_table_len[port] : -1);
2772                         if (err) {
2773                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2774                                          port);
2775                                 goto err_default_countes_free;
2776                         }
2777                 }
2778         }
2779
2780         return 0;
2781
2782 err_default_countes_free:
2783         mlx4_cleanup_default_counters(dev);
2784
2785 err_counters_table_free:
2786         if (!mlx4_is_slave(dev))
2787                 mlx4_cleanup_counters_table(dev);
2788
2789 err_qp_table_free:
2790         mlx4_cleanup_qp_table(dev);
2791
2792 err_srq_table_free:
2793         mlx4_cleanup_srq_table(dev);
2794
2795 err_cq_table_free:
2796         mlx4_cleanup_cq_table(dev);
2797
2798 err_cmd_poll:
2799         mlx4_cmd_use_polling(dev);
2800
2801 err_eq_table_free:
2802         mlx4_cleanup_eq_table(dev);
2803
2804 err_mcg_table_free:
2805         if (!mlx4_is_slave(dev))
2806                 mlx4_cleanup_mcg_table(dev);
2807
2808 err_mr_table_free:
2809         mlx4_cleanup_mr_table(dev);
2810
2811 err_xrcd_table_free:
2812         mlx4_cleanup_xrcd_table(dev);
2813
2814 err_pd_table_free:
2815         mlx4_cleanup_pd_table(dev);
2816
2817 err_kar_unmap:
2818         iounmap(priv->kar);
2819
2820 err_uar_free:
2821         mlx4_uar_free(dev, &priv->driver_uar);
2822
2823 err_uar_table_free:
2824         mlx4_cleanup_uar_table(dev);
2825         return err;
2826 }
2827
2828 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2829 {
2830         int requested_cpu = 0;
2831         struct mlx4_priv *priv = mlx4_priv(dev);
2832         struct mlx4_eq *eq;
2833         int off = 0;
2834         int i;
2835
2836         if (eqn > dev->caps.num_comp_vectors)
2837                 return -EINVAL;
2838
2839         for (i = 1; i < port; i++)
2840                 off += mlx4_get_eqs_per_port(dev, i);
2841
2842         requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2843
2844         /* Meaning EQs are shared, and this call comes from the second port */
2845         if (requested_cpu < 0)
2846                 return 0;
2847
2848         eq = &priv->eq_table.eq[eqn];
2849
2850         if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2851                 return -ENOMEM;
2852
2853         cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2854
2855         return 0;
2856 }
2857
2858 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2859 {
2860         struct mlx4_priv *priv = mlx4_priv(dev);
2861         struct msix_entry *entries;
2862         int i;
2863         int port = 0;
2864
2865         if (msi_x) {
2866                 int nreq = dev->caps.num_ports * num_online_cpus() + 1;
2867
2868                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2869                              nreq);
2870                 if (nreq > MAX_MSIX)
2871                         nreq = MAX_MSIX;
2872
2873                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2874                 if (!entries)
2875                         goto no_msi;
2876
2877                 for (i = 0; i < nreq; ++i)
2878                         entries[i].entry = i;
2879
2880                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2881                                              nreq);
2882
2883                 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2884                         kfree(entries);
2885                         goto no_msi;
2886                 }
2887                 /* 1 is reserved for events (asyncrounous EQ) */
2888                 dev->caps.num_comp_vectors = nreq - 1;
2889
2890                 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2891                 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2892                             dev->caps.num_ports);
2893
2894                 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2895                         if (i == MLX4_EQ_ASYNC)
2896                                 continue;
2897
2898                         priv->eq_table.eq[i].irq =
2899                                 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2900
2901                         if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2902                                 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2903                                             dev->caps.num_ports);
2904                                 /* We don't set affinity hint when there
2905                                  * aren't enough EQs
2906                                  */
2907                         } else {
2908                                 set_bit(port,
2909                                         priv->eq_table.eq[i].actv_ports.ports);
2910                                 if (mlx4_init_affinity_hint(dev, port + 1, i))
2911                                         mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2912                                                   i);
2913                         }
2914                         /* We divide the Eqs evenly between the two ports.
2915                          * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2916                          * refers to the number of Eqs per port
2917                          * (i.e eqs_per_port). Theoretically, we would like to
2918                          * write something like (i + 1) % eqs_per_port == 0.
2919                          * However, since there's an asynchronous Eq, we have
2920                          * to skip over it by comparing this condition to
2921                          * !!((i + 1) > MLX4_EQ_ASYNC).
2922                          */
2923                         if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2924                             ((i + 1) %
2925                              (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2926                             !!((i + 1) > MLX4_EQ_ASYNC))
2927                                 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2928                                  * everything is shared anyway.
2929                                  */
2930                                 port++;
2931                 }
2932
2933                 dev->flags |= MLX4_FLAG_MSI_X;
2934
2935                 kfree(entries);
2936                 return;
2937         }
2938
2939 no_msi:
2940         dev->caps.num_comp_vectors = 1;
2941
2942         BUG_ON(MLX4_EQ_ASYNC >= 2);
2943         for (i = 0; i < 2; ++i) {
2944                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2945                 if (i != MLX4_EQ_ASYNC) {
2946                         bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2947                                     dev->caps.num_ports);
2948                 }
2949         }
2950 }
2951
2952 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2953 {
2954         struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2955         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2956         int err;
2957
2958         err = devlink_port_register(devlink, &info->devlink_port, port);
2959         if (err)
2960                 return err;
2961
2962         info->dev = dev;
2963         info->port = port;
2964         if (!mlx4_is_slave(dev)) {
2965                 mlx4_init_mac_table(dev, &info->mac_table);
2966                 mlx4_init_vlan_table(dev, &info->vlan_table);
2967                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2968                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2969         }
2970
2971         sprintf(info->dev_name, "mlx4_port%d", port);
2972         info->port_attr.attr.name = info->dev_name;
2973         if (mlx4_is_mfunc(dev))
2974                 info->port_attr.attr.mode = S_IRUGO;
2975         else {
2976                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2977                 info->port_attr.store     = set_port_type;
2978         }
2979         info->port_attr.show      = show_port_type;
2980         sysfs_attr_init(&info->port_attr.attr);
2981
2982         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2983         if (err) {
2984                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2985                 devlink_port_unregister(&info->devlink_port);
2986                 info->port = -1;
2987                 return err;
2988         }
2989
2990         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2991         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2992         if (mlx4_is_mfunc(dev))
2993                 info->port_mtu_attr.attr.mode = S_IRUGO;
2994         else {
2995                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2996                 info->port_mtu_attr.store     = set_port_ib_mtu;
2997         }
2998         info->port_mtu_attr.show      = show_port_ib_mtu;
2999         sysfs_attr_init(&info->port_mtu_attr.attr);
3000
3001         err = device_create_file(&dev->persist->pdev->dev,
3002                                  &info->port_mtu_attr);
3003         if (err) {
3004                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
3005                 device_remove_file(&info->dev->persist->pdev->dev,
3006                                    &info->port_attr);
3007                 devlink_port_unregister(&info->devlink_port);
3008                 info->port = -1;
3009                 return err;
3010         }
3011
3012         return 0;
3013 }
3014
3015 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3016 {
3017         if (info->port < 0)
3018                 return;
3019
3020         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
3021         device_remove_file(&info->dev->persist->pdev->dev,
3022                            &info->port_mtu_attr);
3023         devlink_port_unregister(&info->devlink_port);
3024
3025 #ifdef CONFIG_RFS_ACCEL
3026         free_irq_cpu_rmap(info->rmap);
3027         info->rmap = NULL;
3028 #endif
3029 }
3030
3031 static int mlx4_init_steering(struct mlx4_dev *dev)
3032 {
3033         struct mlx4_priv *priv = mlx4_priv(dev);
3034         int num_entries = dev->caps.num_ports;
3035         int i, j;
3036
3037         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3038         if (!priv->steer)
3039                 return -ENOMEM;
3040
3041         for (i = 0; i < num_entries; i++)
3042                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3043                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3044                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3045                 }
3046         return 0;
3047 }
3048
3049 static void mlx4_clear_steering(struct mlx4_dev *dev)
3050 {
3051         struct mlx4_priv *priv = mlx4_priv(dev);
3052         struct mlx4_steer_index *entry, *tmp_entry;
3053         struct mlx4_promisc_qp *pqp, *tmp_pqp;
3054         int num_entries = dev->caps.num_ports;
3055         int i, j;
3056
3057         for (i = 0; i < num_entries; i++) {
3058                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3059                         list_for_each_entry_safe(pqp, tmp_pqp,
3060                                                  &priv->steer[i].promisc_qps[j],
3061                                                  list) {
3062                                 list_del(&pqp->list);
3063                                 kfree(pqp);
3064                         }
3065                         list_for_each_entry_safe(entry, tmp_entry,
3066                                                  &priv->steer[i].steer_entries[j],
3067                                                  list) {
3068                                 list_del(&entry->list);
3069                                 list_for_each_entry_safe(pqp, tmp_pqp,
3070                                                          &entry->duplicates,
3071                                                          list) {
3072                                         list_del(&pqp->list);
3073                                         kfree(pqp);
3074                                 }
3075                                 kfree(entry);
3076                         }
3077                 }
3078         }
3079         kfree(priv->steer);
3080 }
3081
3082 static int extended_func_num(struct pci_dev *pdev)
3083 {
3084         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3085 }
3086
3087 #define MLX4_OWNER_BASE 0x8069c
3088 #define MLX4_OWNER_SIZE 4
3089
3090 static int mlx4_get_ownership(struct mlx4_dev *dev)
3091 {
3092         void __iomem *owner;
3093         u32 ret;
3094
3095         if (pci_channel_offline(dev->persist->pdev))
3096                 return -EIO;
3097
3098         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3099                         MLX4_OWNER_BASE,
3100                         MLX4_OWNER_SIZE);
3101         if (!owner) {
3102                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3103                 return -ENOMEM;
3104         }
3105
3106         ret = readl(owner);
3107         iounmap(owner);
3108         return (int) !!ret;
3109 }
3110
3111 static void mlx4_free_ownership(struct mlx4_dev *dev)
3112 {
3113         void __iomem *owner;
3114
3115         if (pci_channel_offline(dev->persist->pdev))
3116                 return;
3117
3118         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3119                         MLX4_OWNER_BASE,
3120                         MLX4_OWNER_SIZE);
3121         if (!owner) {
3122                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3123                 return;
3124         }
3125         writel(0, owner);
3126         msleep(1000);
3127         iounmap(owner);
3128 }
3129
3130 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3131                                   !!((flags) & MLX4_FLAG_MASTER))
3132
3133 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
3134                              u8 total_vfs, int existing_vfs, int reset_flow)
3135 {
3136         u64 dev_flags = dev->flags;
3137         int err = 0;
3138         int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3139                                         MLX4_MAX_NUM_VF);
3140
3141         if (reset_flow) {
3142                 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3143                                        GFP_KERNEL);
3144                 if (!dev->dev_vfs)
3145                         goto free_mem;
3146                 return dev_flags;
3147         }
3148
3149         atomic_inc(&pf_loading);
3150         if (dev->flags &  MLX4_FLAG_SRIOV) {
3151                 if (existing_vfs != total_vfs) {
3152                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3153                                  existing_vfs, total_vfs);
3154                         total_vfs = existing_vfs;
3155                 }
3156         }
3157
3158         dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
3159         if (NULL == dev->dev_vfs) {
3160                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3161                 goto disable_sriov;
3162         }
3163
3164         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
3165                 if (total_vfs > fw_enabled_sriov_vfs) {
3166                         mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3167                                  total_vfs, fw_enabled_sriov_vfs);
3168                         err = -ENOMEM;
3169                         goto disable_sriov;
3170                 }
3171                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3172                 err = pci_enable_sriov(pdev, total_vfs);
3173         }
3174         if (err) {
3175                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3176                          err);
3177                 goto disable_sriov;
3178         } else {
3179                 mlx4_warn(dev, "Running in master mode\n");
3180                 dev_flags |= MLX4_FLAG_SRIOV |
3181                         MLX4_FLAG_MASTER;
3182                 dev_flags &= ~MLX4_FLAG_SLAVE;
3183                 dev->persist->num_vfs = total_vfs;
3184         }
3185         return dev_flags;
3186
3187 disable_sriov:
3188         atomic_dec(&pf_loading);
3189 free_mem:
3190         dev->persist->num_vfs = 0;
3191         kfree(dev->dev_vfs);
3192         dev->dev_vfs = NULL;
3193         return dev_flags & ~MLX4_FLAG_MASTER;
3194 }
3195
3196 enum {
3197         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3198 };
3199
3200 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3201                               int *nvfs)
3202 {
3203         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3204         /* Checking for 64 VFs as a limitation of CX2 */
3205         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3206             requested_vfs >= 64) {
3207                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3208                          requested_vfs);
3209                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3210         }
3211         return 0;
3212 }
3213
3214 static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3215 {
3216         struct pci_dev *pdev = dev->persist->pdev;
3217         int err = 0;
3218
3219         mutex_lock(&dev->persist->pci_status_mutex);
3220         if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3221                 err = pci_enable_device(pdev);
3222                 if (!err)
3223                         dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3224         }
3225         mutex_unlock(&dev->persist->pci_status_mutex);
3226
3227         return err;
3228 }
3229
3230 static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3231 {
3232         struct pci_dev *pdev = dev->persist->pdev;
3233
3234         mutex_lock(&dev->persist->pci_status_mutex);
3235         if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3236                 pci_disable_device(pdev);
3237                 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3238         }
3239         mutex_unlock(&dev->persist->pci_status_mutex);
3240 }
3241
3242 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
3243                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
3244                          int reset_flow)
3245 {
3246         struct mlx4_dev *dev;
3247         unsigned sum = 0;
3248         int err;
3249         int port;
3250         int i;
3251         struct mlx4_dev_cap *dev_cap = NULL;
3252         int existing_vfs = 0;
3253
3254         dev = &priv->dev;
3255
3256         INIT_LIST_HEAD(&priv->ctx_list);
3257         spin_lock_init(&priv->ctx_lock);
3258
3259         mutex_init(&priv->port_mutex);
3260         mutex_init(&priv->bond_mutex);
3261
3262         INIT_LIST_HEAD(&priv->pgdir_list);
3263         mutex_init(&priv->pgdir_mutex);
3264         spin_lock_init(&priv->cmd.context_lock);
3265
3266         INIT_LIST_HEAD(&priv->bf_list);
3267         mutex_init(&priv->bf_mutex);
3268
3269         dev->rev_id = pdev->revision;
3270         dev->numa_node = dev_to_node(&pdev->dev);
3271
3272         /* Detect if this device is a virtual function */
3273         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3274                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3275                 dev->flags |= MLX4_FLAG_SLAVE;
3276         } else {
3277                 /* We reset the device and enable SRIOV only for physical
3278                  * devices.  Try to claim ownership on the device;
3279                  * if already taken, skip -- do not allow multiple PFs */
3280                 err = mlx4_get_ownership(dev);
3281                 if (err) {
3282                         if (err < 0)
3283                                 return err;
3284                         else {
3285                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3286                                 return -EINVAL;
3287                         }
3288                 }
3289
3290                 atomic_set(&priv->opreq_count, 0);
3291                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3292
3293                 /*
3294                  * Now reset the HCA before we touch the PCI capabilities or
3295                  * attempt a firmware command, since a boot ROM may have left
3296                  * the HCA in an undefined state.
3297                  */
3298                 err = mlx4_reset(dev);
3299                 if (err) {
3300                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
3301                         goto err_sriov;
3302                 }
3303
3304                 if (total_vfs) {
3305                         dev->flags = MLX4_FLAG_MASTER;
3306                         existing_vfs = pci_num_vf(pdev);
3307                         if (existing_vfs)
3308                                 dev->flags |= MLX4_FLAG_SRIOV;
3309                         dev->persist->num_vfs = total_vfs;
3310                 }
3311         }
3312
3313         /* on load remove any previous indication of internal error,
3314          * device is up.
3315          */
3316         dev->persist->state = MLX4_DEVICE_STATE_UP;
3317
3318 slave_start:
3319         err = mlx4_cmd_init(dev);
3320         if (err) {
3321                 mlx4_err(dev, "Failed to init command interface, aborting\n");
3322                 goto err_sriov;
3323         }
3324
3325         /* In slave functions, the communication channel must be initialized
3326          * before posting commands. Also, init num_slaves before calling
3327          * mlx4_init_hca */
3328         if (mlx4_is_mfunc(dev)) {
3329                 if (mlx4_is_master(dev)) {
3330                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3331
3332                 } else {
3333                         dev->num_slaves = 0;
3334                         err = mlx4_multi_func_init(dev);
3335                         if (err) {
3336                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3337                                 goto err_cmd;
3338                         }
3339                 }
3340         }
3341
3342         err = mlx4_init_fw(dev);
3343         if (err) {
3344                 mlx4_err(dev, "Failed to init fw, aborting.\n");
3345                 goto err_mfunc;
3346         }
3347
3348         if (mlx4_is_master(dev)) {
3349                 /* when we hit the goto slave_start below, dev_cap already initialized */
3350                 if (!dev_cap) {
3351                         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3352
3353                         if (!dev_cap) {
3354                                 err = -ENOMEM;
3355                                 goto err_fw;
3356                         }
3357
3358                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3359                         if (err) {
3360                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3361                                 goto err_fw;
3362                         }
3363
3364                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3365                                 goto err_fw;
3366
3367                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3368                                 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3369                                                                   total_vfs,
3370                                                                   existing_vfs,
3371                                                                   reset_flow);
3372
3373                                 mlx4_close_fw(dev);
3374                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3375                                 dev->flags = dev_flags;
3376                                 if (!SRIOV_VALID_STATE(dev->flags)) {
3377                                         mlx4_err(dev, "Invalid SRIOV state\n");
3378                                         goto err_sriov;
3379                                 }
3380                                 err = mlx4_reset(dev);
3381                                 if (err) {
3382                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3383                                         goto err_sriov;
3384                                 }
3385                                 goto slave_start;
3386                         }
3387                 } else {
3388                         /* Legacy mode FW requires SRIOV to be enabled before
3389                          * doing QUERY_DEV_CAP, since max_eq's value is different if
3390                          * SRIOV is enabled.
3391                          */
3392                         memset(dev_cap, 0, sizeof(*dev_cap));
3393                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3394                         if (err) {
3395                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3396                                 goto err_fw;
3397                         }
3398
3399                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3400                                 goto err_fw;
3401                 }
3402         }
3403
3404         err = mlx4_init_hca(dev);
3405         if (err) {
3406                 if (err == -EACCES) {
3407                         /* Not primary Physical function
3408                          * Running in slave mode */
3409                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3410                         /* We're not a PF */
3411                         if (dev->flags & MLX4_FLAG_SRIOV) {
3412                                 if (!existing_vfs)
3413                                         pci_disable_sriov(pdev);
3414                                 if (mlx4_is_master(dev) && !reset_flow)
3415                                         atomic_dec(&pf_loading);
3416                                 dev->flags &= ~MLX4_FLAG_SRIOV;
3417                         }
3418                         if (!mlx4_is_slave(dev))
3419                                 mlx4_free_ownership(dev);
3420                         dev->flags |= MLX4_FLAG_SLAVE;
3421                         dev->flags &= ~MLX4_FLAG_MASTER;
3422                         goto slave_start;
3423                 } else
3424                         goto err_fw;
3425         }
3426
3427         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3428                 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3429                                                   existing_vfs, reset_flow);
3430
3431                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3432                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3433                         dev->flags = dev_flags;
3434                         err = mlx4_cmd_init(dev);
3435                         if (err) {
3436                                 /* Only VHCR is cleaned up, so could still
3437                                  * send FW commands
3438                                  */
3439                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3440                                 goto err_close;
3441                         }
3442                 } else {
3443                         dev->flags = dev_flags;
3444                 }
3445
3446                 if (!SRIOV_VALID_STATE(dev->flags)) {
3447                         mlx4_err(dev, "Invalid SRIOV state\n");
3448                         err = -EINVAL;
3449                         goto err_close;
3450                 }
3451         }
3452
3453         /* check if the device is functioning at its maximum possible speed.
3454          * No return code for this call, just warn the user in case of PCI
3455          * express device capabilities are under-satisfied by the bus.
3456          */
3457         if (!mlx4_is_slave(dev))
3458                 mlx4_check_pcie_caps(dev);
3459
3460         /* In master functions, the communication channel must be initialized
3461          * after obtaining its address from fw */
3462         if (mlx4_is_master(dev)) {
3463                 if (dev->caps.num_ports < 2 &&
3464                     num_vfs_argc > 1) {
3465                         err = -EINVAL;
3466                         mlx4_err(dev,
3467                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3468                                  dev->caps.num_ports);
3469                         goto err_close;
3470                 }
3471                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3472
3473                 for (i = 0;
3474                      i < sizeof(dev->persist->nvfs)/
3475                      sizeof(dev->persist->nvfs[0]); i++) {
3476                         unsigned j;
3477
3478                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3479                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3480                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3481                                         dev->caps.num_ports;
3482                         }
3483                 }
3484
3485                 /* In master functions, the communication channel
3486                  * must be initialized after obtaining its address from fw
3487                  */
3488                 err = mlx4_multi_func_init(dev);
3489                 if (err) {
3490                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3491                         goto err_close;
3492                 }
3493         }
3494
3495         err = mlx4_alloc_eq_table(dev);
3496         if (err)
3497                 goto err_master_mfunc;
3498
3499         bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3500         mutex_init(&priv->msix_ctl.pool_lock);
3501
3502         mlx4_enable_msi_x(dev);
3503         if ((mlx4_is_mfunc(dev)) &&
3504             !(dev->flags & MLX4_FLAG_MSI_X)) {
3505                 err = -ENOSYS;
3506                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3507                 goto err_free_eq;
3508         }
3509
3510         if (!mlx4_is_slave(dev)) {
3511                 err = mlx4_init_steering(dev);
3512                 if (err)
3513                         goto err_disable_msix;
3514         }
3515
3516         err = mlx4_setup_hca(dev);
3517         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3518             !mlx4_is_mfunc(dev)) {
3519                 dev->flags &= ~MLX4_FLAG_MSI_X;
3520                 dev->caps.num_comp_vectors = 1;
3521                 pci_disable_msix(pdev);
3522                 err = mlx4_setup_hca(dev);
3523         }
3524
3525         if (err)
3526                 goto err_steer;
3527
3528         mlx4_init_quotas(dev);
3529         /* When PF resources are ready arm its comm channel to enable
3530          * getting commands
3531          */
3532         if (mlx4_is_master(dev)) {
3533                 err = mlx4_ARM_COMM_CHANNEL(dev);
3534                 if (err) {
3535                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3536                                  err);
3537                         goto err_steer;
3538                 }
3539         }
3540
3541         for (port = 1; port <= dev->caps.num_ports; port++) {
3542                 err = mlx4_init_port_info(dev, port);
3543                 if (err)
3544                         goto err_port;
3545         }
3546
3547         priv->v2p.port1 = 1;
3548         priv->v2p.port2 = 2;
3549
3550         err = mlx4_register_device(dev);
3551         if (err)
3552                 goto err_port;
3553
3554         mlx4_request_modules(dev);
3555
3556         mlx4_sense_init(dev);
3557         mlx4_start_sense(dev);
3558
3559         priv->removed = 0;
3560
3561         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3562                 atomic_dec(&pf_loading);
3563
3564         kfree(dev_cap);
3565         return 0;
3566
3567 err_port:
3568         for (--port; port >= 1; --port)
3569                 mlx4_cleanup_port_info(&priv->port[port]);
3570
3571         mlx4_cleanup_default_counters(dev);
3572         if (!mlx4_is_slave(dev))
3573                 mlx4_cleanup_counters_table(dev);
3574         mlx4_cleanup_qp_table(dev);
3575         mlx4_cleanup_srq_table(dev);
3576         mlx4_cleanup_cq_table(dev);
3577         mlx4_cmd_use_polling(dev);
3578         mlx4_cleanup_eq_table(dev);
3579         mlx4_cleanup_mcg_table(dev);
3580         mlx4_cleanup_mr_table(dev);
3581         mlx4_cleanup_xrcd_table(dev);
3582         mlx4_cleanup_pd_table(dev);
3583         mlx4_cleanup_uar_table(dev);
3584
3585 err_steer:
3586         if (!mlx4_is_slave(dev))
3587                 mlx4_clear_steering(dev);
3588
3589 err_disable_msix:
3590         if (dev->flags & MLX4_FLAG_MSI_X)
3591                 pci_disable_msix(pdev);
3592
3593 err_free_eq:
3594         mlx4_free_eq_table(dev);
3595
3596 err_master_mfunc:
3597         if (mlx4_is_master(dev)) {
3598                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3599                 mlx4_multi_func_cleanup(dev);
3600         }
3601
3602         if (mlx4_is_slave(dev)) {
3603                 kfree(dev->caps.qp0_qkey);
3604                 kfree(dev->caps.qp0_tunnel);
3605                 kfree(dev->caps.qp0_proxy);
3606                 kfree(dev->caps.qp1_tunnel);
3607                 kfree(dev->caps.qp1_proxy);
3608         }
3609
3610 err_close:
3611         mlx4_close_hca(dev);
3612
3613 err_fw:
3614         mlx4_close_fw(dev);
3615
3616 err_mfunc:
3617         if (mlx4_is_slave(dev))
3618                 mlx4_multi_func_cleanup(dev);
3619
3620 err_cmd:
3621         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3622
3623 err_sriov:
3624         if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3625                 pci_disable_sriov(pdev);
3626                 dev->flags &= ~MLX4_FLAG_SRIOV;
3627         }
3628
3629         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3630                 atomic_dec(&pf_loading);
3631
3632         kfree(priv->dev.dev_vfs);
3633
3634         if (!mlx4_is_slave(dev))
3635                 mlx4_free_ownership(dev);
3636
3637         kfree(dev_cap);
3638         return err;
3639 }
3640
3641 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3642                            struct mlx4_priv *priv)
3643 {
3644         int err;
3645         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3646         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3647         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3648                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3649         unsigned total_vfs = 0;
3650         unsigned int i;
3651
3652         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3653
3654         err = mlx4_pci_enable_device(&priv->dev);
3655         if (err) {
3656                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3657                 return err;
3658         }
3659
3660         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3661          * per port, we must limit the number of VFs to 63 (since their are
3662          * 128 MACs)
3663          */
3664         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3665              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3666                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3667                 if (nvfs[i] < 0) {
3668                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3669                         err = -EINVAL;
3670                         goto err_disable_pdev;
3671                 }
3672         }
3673         for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3674              i++) {
3675                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3676                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3677                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3678                         err = -EINVAL;
3679                         goto err_disable_pdev;
3680                 }
3681         }
3682         if (total_vfs > MLX4_MAX_NUM_VF) {
3683                 dev_err(&pdev->dev,
3684                         "Requested more VF's (%d) than allowed by hw (%d)\n",
3685                         total_vfs, MLX4_MAX_NUM_VF);
3686                 err = -EINVAL;
3687                 goto err_disable_pdev;
3688         }
3689
3690         for (i = 0; i < MLX4_MAX_PORTS; i++) {
3691                 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
3692                         dev_err(&pdev->dev,
3693                                 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
3694                                 nvfs[i] + nvfs[2], i + 1,
3695                                 MLX4_MAX_NUM_VF_P_PORT);
3696                         err = -EINVAL;
3697                         goto err_disable_pdev;
3698                 }
3699         }
3700
3701         /* Check for BARs. */
3702         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3703             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3704                 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3705                         pci_dev_data, pci_resource_flags(pdev, 0));
3706                 err = -ENODEV;
3707                 goto err_disable_pdev;
3708         }
3709         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3710                 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3711                 err = -ENODEV;
3712                 goto err_disable_pdev;
3713         }
3714
3715         err = pci_request_regions(pdev, DRV_NAME);
3716         if (err) {
3717                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3718                 goto err_disable_pdev;
3719         }
3720
3721         pci_set_master(pdev);
3722
3723         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3724         if (err) {
3725                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3726                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3727                 if (err) {
3728                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3729                         goto err_release_regions;
3730                 }
3731         }
3732         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3733         if (err) {
3734                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3735                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3736                 if (err) {
3737                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3738                         goto err_release_regions;
3739                 }
3740         }
3741
3742         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3743         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3744         /* Detect if this device is a virtual function */
3745         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3746                 /* When acting as pf, we normally skip vfs unless explicitly
3747                  * requested to probe them.
3748                  */
3749                 if (total_vfs) {
3750                         unsigned vfs_offset = 0;
3751
3752                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3753                              vfs_offset + nvfs[i] < extended_func_num(pdev);
3754                              vfs_offset += nvfs[i], i++)
3755                                 ;
3756                         if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3757                                 err = -ENODEV;
3758                                 goto err_release_regions;
3759                         }
3760                         if ((extended_func_num(pdev) - vfs_offset)
3761                             > prb_vf[i]) {
3762                                 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3763                                          extended_func_num(pdev));
3764                                 err = -ENODEV;
3765                                 goto err_release_regions;
3766                         }
3767                 }
3768         }
3769
3770         err = mlx4_catas_init(&priv->dev);
3771         if (err)
3772                 goto err_release_regions;
3773
3774         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3775         if (err)
3776                 goto err_catas;
3777
3778         return 0;
3779
3780 err_catas:
3781         mlx4_catas_end(&priv->dev);
3782
3783 err_release_regions:
3784         pci_release_regions(pdev);
3785
3786 err_disable_pdev:
3787         mlx4_pci_disable_device(&priv->dev);
3788         pci_set_drvdata(pdev, NULL);
3789         return err;
3790 }
3791
3792 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3793                                       enum devlink_port_type port_type)
3794 {
3795         struct mlx4_port_info *info = container_of(devlink_port,
3796                                                    struct mlx4_port_info,
3797                                                    devlink_port);
3798         enum mlx4_port_type mlx4_port_type;
3799
3800         switch (port_type) {
3801         case DEVLINK_PORT_TYPE_AUTO:
3802                 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3803                 break;
3804         case DEVLINK_PORT_TYPE_ETH:
3805                 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3806                 break;
3807         case DEVLINK_PORT_TYPE_IB:
3808                 mlx4_port_type = MLX4_PORT_TYPE_IB;
3809                 break;
3810         default:
3811                 return -EOPNOTSUPP;
3812         }
3813
3814         return __set_port_type(info, mlx4_port_type);
3815 }
3816
3817 static const struct devlink_ops mlx4_devlink_ops = {
3818         .port_type_set  = mlx4_devlink_port_type_set,
3819 };
3820
3821 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3822 {
3823         struct devlink *devlink;
3824         struct mlx4_priv *priv;
3825         struct mlx4_dev *dev;
3826         int ret;
3827
3828         printk_once(KERN_INFO "%s", mlx4_version);
3829
3830         devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
3831         if (!devlink)
3832                 return -ENOMEM;
3833         priv = devlink_priv(devlink);
3834
3835         dev       = &priv->dev;
3836         dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3837         if (!dev->persist) {
3838                 ret = -ENOMEM;
3839                 goto err_devlink_free;
3840         }
3841         dev->persist->pdev = pdev;
3842         dev->persist->dev = dev;
3843         pci_set_drvdata(pdev, dev->persist);
3844         priv->pci_dev_data = id->driver_data;
3845         mutex_init(&dev->persist->device_state_mutex);
3846         mutex_init(&dev->persist->interface_state_mutex);
3847         mutex_init(&dev->persist->pci_status_mutex);
3848
3849         ret = devlink_register(devlink, &pdev->dev);
3850         if (ret)
3851                 goto err_persist_free;
3852
3853         ret =  __mlx4_init_one(pdev, id->driver_data, priv);
3854         if (ret)
3855                 goto err_devlink_unregister;
3856
3857         pci_save_state(pdev);
3858         return 0;
3859
3860 err_devlink_unregister:
3861         devlink_unregister(devlink);
3862 err_persist_free:
3863         kfree(dev->persist);
3864 err_devlink_free:
3865         devlink_free(devlink);
3866         return ret;
3867 }
3868
3869 static void mlx4_clean_dev(struct mlx4_dev *dev)
3870 {
3871         struct mlx4_dev_persistent *persist = dev->persist;
3872         struct mlx4_priv *priv = mlx4_priv(dev);
3873         unsigned long   flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3874
3875         memset(priv, 0, sizeof(*priv));
3876         priv->dev.persist = persist;
3877         priv->dev.flags = flags;
3878 }
3879
3880 static void mlx4_unload_one(struct pci_dev *pdev)
3881 {
3882         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3883         struct mlx4_dev  *dev  = persist->dev;
3884         struct mlx4_priv *priv = mlx4_priv(dev);
3885         int               pci_dev_data;
3886         int p, i;
3887
3888         if (priv->removed)
3889                 return;
3890
3891         /* saving current ports type for further use */
3892         for (i = 0; i < dev->caps.num_ports; i++) {
3893                 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3894                 dev->persist->curr_port_poss_type[i] = dev->caps.
3895                                                        possible_type[i + 1];
3896         }
3897
3898         pci_dev_data = priv->pci_dev_data;
3899
3900         mlx4_stop_sense(dev);
3901         mlx4_unregister_device(dev);
3902
3903         for (p = 1; p <= dev->caps.num_ports; p++) {
3904                 mlx4_cleanup_port_info(&priv->port[p]);
3905                 mlx4_CLOSE_PORT(dev, p);
3906         }
3907
3908         if (mlx4_is_master(dev))
3909                 mlx4_free_resource_tracker(dev,
3910                                            RES_TR_FREE_SLAVES_ONLY);
3911
3912         mlx4_cleanup_default_counters(dev);
3913         if (!mlx4_is_slave(dev))
3914                 mlx4_cleanup_counters_table(dev);
3915         mlx4_cleanup_qp_table(dev);
3916         mlx4_cleanup_srq_table(dev);
3917         mlx4_cleanup_cq_table(dev);
3918         mlx4_cmd_use_polling(dev);
3919         mlx4_cleanup_eq_table(dev);
3920         mlx4_cleanup_mcg_table(dev);
3921         mlx4_cleanup_mr_table(dev);
3922         mlx4_cleanup_xrcd_table(dev);
3923         mlx4_cleanup_pd_table(dev);
3924
3925         if (mlx4_is_master(dev))
3926                 mlx4_free_resource_tracker(dev,
3927                                            RES_TR_FREE_STRUCTS_ONLY);
3928
3929         iounmap(priv->kar);
3930         mlx4_uar_free(dev, &priv->driver_uar);
3931         mlx4_cleanup_uar_table(dev);
3932         if (!mlx4_is_slave(dev))
3933                 mlx4_clear_steering(dev);
3934         mlx4_free_eq_table(dev);
3935         if (mlx4_is_master(dev))
3936                 mlx4_multi_func_cleanup(dev);
3937         mlx4_close_hca(dev);
3938         mlx4_close_fw(dev);
3939         if (mlx4_is_slave(dev))
3940                 mlx4_multi_func_cleanup(dev);
3941         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3942
3943         if (dev->flags & MLX4_FLAG_MSI_X)
3944                 pci_disable_msix(pdev);
3945
3946         if (!mlx4_is_slave(dev))
3947                 mlx4_free_ownership(dev);
3948
3949         kfree(dev->caps.qp0_qkey);
3950         kfree(dev->caps.qp0_tunnel);
3951         kfree(dev->caps.qp0_proxy);
3952         kfree(dev->caps.qp1_tunnel);
3953         kfree(dev->caps.qp1_proxy);
3954         kfree(dev->dev_vfs);
3955
3956         mlx4_clean_dev(dev);
3957         priv->pci_dev_data = pci_dev_data;
3958         priv->removed = 1;
3959 }
3960
3961 static void mlx4_remove_one(struct pci_dev *pdev)
3962 {
3963         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3964         struct mlx4_dev  *dev  = persist->dev;
3965         struct mlx4_priv *priv = mlx4_priv(dev);
3966         struct devlink *devlink = priv_to_devlink(priv);
3967         int active_vfs = 0;
3968
3969         if (mlx4_is_slave(dev))
3970                 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
3971
3972         mutex_lock(&persist->interface_state_mutex);
3973         persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3974         mutex_unlock(&persist->interface_state_mutex);
3975
3976         /* Disabling SR-IOV is not allowed while there are active vf's */
3977         if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3978                 active_vfs = mlx4_how_many_lives_vf(dev);
3979                 if (active_vfs) {
3980                         pr_warn("Removing PF when there are active VF's !!\n");
3981                         pr_warn("Will not disable SR-IOV.\n");
3982                 }
3983         }
3984
3985         /* device marked to be under deletion running now without the lock
3986          * letting other tasks to be terminated
3987          */
3988         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3989                 mlx4_unload_one(pdev);
3990         else
3991                 mlx4_info(dev, "%s: interface is down\n", __func__);
3992         mlx4_catas_end(dev);
3993         if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3994                 mlx4_warn(dev, "Disabling SR-IOV\n");
3995                 pci_disable_sriov(pdev);
3996         }
3997
3998         pci_release_regions(pdev);
3999         mlx4_pci_disable_device(dev);
4000         devlink_unregister(devlink);
4001         kfree(dev->persist);
4002         devlink_free(devlink);
4003         pci_set_drvdata(pdev, NULL);
4004 }
4005
4006 static int restore_current_port_types(struct mlx4_dev *dev,
4007                                       enum mlx4_port_type *types,
4008                                       enum mlx4_port_type *poss_types)
4009 {
4010         struct mlx4_priv *priv = mlx4_priv(dev);
4011         int err, i;
4012
4013         mlx4_stop_sense(dev);
4014
4015         mutex_lock(&priv->port_mutex);
4016         for (i = 0; i < dev->caps.num_ports; i++)
4017                 dev->caps.possible_type[i + 1] = poss_types[i];
4018         err = mlx4_change_port_types(dev, types);
4019         mlx4_start_sense(dev);
4020         mutex_unlock(&priv->port_mutex);
4021
4022         return err;
4023 }
4024
4025 int mlx4_restart_one(struct pci_dev *pdev)
4026 {
4027         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4028         struct mlx4_dev  *dev  = persist->dev;
4029         struct mlx4_priv *priv = mlx4_priv(dev);
4030         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4031         int pci_dev_data, err, total_vfs;
4032
4033         pci_dev_data = priv->pci_dev_data;
4034         total_vfs = dev->persist->num_vfs;
4035         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4036
4037         mlx4_unload_one(pdev);
4038         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
4039         if (err) {
4040                 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
4041                          __func__, pci_name(pdev), err);
4042                 return err;
4043         }
4044
4045         err = restore_current_port_types(dev, dev->persist->curr_port_type,
4046                                          dev->persist->curr_port_poss_type);
4047         if (err)
4048                 mlx4_err(dev, "could not restore original port types (%d)\n",
4049                          err);
4050
4051         return err;
4052 }
4053
4054 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
4055 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
4056 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
4057
4058 static const struct pci_device_id mlx4_pci_table[] = {
4059         /* MT25408 "Hermon" */
4060         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR),      /* SDR */
4061         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR),      /* DDR */
4062         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR),      /* QDR */
4063         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
4064         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
4065         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN),       /* EN 10GigE */
4066         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2),  /* EN 10GigE Gen2 */
4067         /* MT25458 ConnectX EN 10GBASE-T */
4068         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4069         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2),      /* Gen2 */
4070         /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
4071         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4072         /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
4073         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4074         /* MT26478 ConnectX2 40GigE PCIe Gen2 */
4075         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4076         /* MT25400 Family [ConnectX-2] */
4077         MLX_VF(0x1002),                                 /* Virtual Function */
4078         /* MT27500 Family [ConnectX-3] */
4079         MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4080         MLX_VF(0x1004),                                 /* Virtual Function */
4081         MLX_GN(0x1005),                                 /* MT27510 Family */
4082         MLX_GN(0x1006),                                 /* MT27511 Family */
4083         MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO),   /* MT27520 Family */
4084         MLX_GN(0x1008),                                 /* MT27521 Family */
4085         MLX_GN(0x1009),                                 /* MT27530 Family */
4086         MLX_GN(0x100a),                                 /* MT27531 Family */
4087         MLX_GN(0x100b),                                 /* MT27540 Family */
4088         MLX_GN(0x100c),                                 /* MT27541 Family */
4089         MLX_GN(0x100d),                                 /* MT27550 Family */
4090         MLX_GN(0x100e),                                 /* MT27551 Family */
4091         MLX_GN(0x100f),                                 /* MT27560 Family */
4092         MLX_GN(0x1010),                                 /* MT27561 Family */
4093
4094         /*
4095          * See the mellanox_check_broken_intx_masking() quirk when
4096          * adding devices
4097          */
4098
4099         { 0, }
4100 };
4101
4102 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4103
4104 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4105                                               pci_channel_state_t state)
4106 {
4107         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4108
4109         mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4110         mlx4_enter_error_state(persist);
4111
4112         mutex_lock(&persist->interface_state_mutex);
4113         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4114                 mlx4_unload_one(pdev);
4115
4116         mutex_unlock(&persist->interface_state_mutex);
4117         if (state == pci_channel_io_perm_failure)
4118                 return PCI_ERS_RESULT_DISCONNECT;
4119
4120         mlx4_pci_disable_device(persist->dev);
4121         return PCI_ERS_RESULT_NEED_RESET;
4122 }
4123
4124 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4125 {
4126         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4127         struct mlx4_dev  *dev  = persist->dev;
4128         int err;
4129
4130         mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4131         err = mlx4_pci_enable_device(dev);
4132         if (err) {
4133                 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
4134                 return PCI_ERS_RESULT_DISCONNECT;
4135         }
4136
4137         pci_set_master(pdev);
4138         pci_restore_state(pdev);
4139         pci_save_state(pdev);
4140         return PCI_ERS_RESULT_RECOVERED;
4141 }
4142
4143 static void mlx4_pci_resume(struct pci_dev *pdev)
4144 {
4145         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4146         struct mlx4_dev  *dev  = persist->dev;
4147         struct mlx4_priv *priv = mlx4_priv(dev);
4148         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4149         int total_vfs;
4150         int err;
4151
4152         mlx4_err(dev, "%s was called\n", __func__);
4153         total_vfs = dev->persist->num_vfs;
4154         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4155
4156         mutex_lock(&persist->interface_state_mutex);
4157         if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4158                 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
4159                                     priv, 1);
4160                 if (err) {
4161                         mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4162                                  __func__,  err);
4163                         goto end;
4164                 }
4165
4166                 err = restore_current_port_types(dev, dev->persist->
4167                                                  curr_port_type, dev->persist->
4168                                                  curr_port_poss_type);
4169                 if (err)
4170                         mlx4_err(dev, "could not restore original port types (%d)\n", err);
4171         }
4172 end:
4173         mutex_unlock(&persist->interface_state_mutex);
4174
4175 }
4176
4177 static void mlx4_shutdown(struct pci_dev *pdev)
4178 {
4179         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4180         struct mlx4_dev *dev = persist->dev;
4181
4182         mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4183         mutex_lock(&persist->interface_state_mutex);
4184         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4185                 mlx4_unload_one(pdev);
4186         mutex_unlock(&persist->interface_state_mutex);
4187         mlx4_pci_disable_device(dev);
4188 }
4189
4190 static const struct pci_error_handlers mlx4_err_handler = {
4191         .error_detected = mlx4_pci_err_detected,
4192         .slot_reset     = mlx4_pci_slot_reset,
4193         .resume         = mlx4_pci_resume,
4194 };
4195
4196 static struct pci_driver mlx4_driver = {
4197         .name           = DRV_NAME,
4198         .id_table       = mlx4_pci_table,
4199         .probe          = mlx4_init_one,
4200         .shutdown       = mlx4_shutdown,
4201         .remove         = mlx4_remove_one,
4202         .err_handler    = &mlx4_err_handler,
4203 };
4204
4205 static int __init mlx4_verify_params(void)
4206 {
4207         if ((log_num_mac < 0) || (log_num_mac > 7)) {
4208                 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
4209                 return -1;
4210         }
4211
4212         if (log_num_vlan != 0)
4213                 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4214                         MLX4_LOG_NUM_VLANS);
4215
4216         if (use_prio != 0)
4217                 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
4218
4219         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
4220                 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4221                         log_mtts_per_seg);
4222                 return -1;
4223         }
4224
4225         /* Check if module param for ports type has legal combination */
4226         if (port_type_array[0] == false && port_type_array[1] == true) {
4227                 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
4228                 port_type_array[0] = true;
4229         }
4230
4231         if (mlx4_log_num_mgm_entry_size < -7 ||
4232             (mlx4_log_num_mgm_entry_size > 0 &&
4233              (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4234               mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4235                 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
4236                         mlx4_log_num_mgm_entry_size,
4237                         MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4238                         MLX4_MAX_MGM_LOG_ENTRY_SIZE);
4239                 return -1;
4240         }
4241
4242         return 0;
4243 }
4244
4245 static int __init mlx4_init(void)
4246 {
4247         int ret;
4248
4249         if (mlx4_verify_params())
4250                 return -EINVAL;
4251
4252
4253         mlx4_wq = create_singlethread_workqueue("mlx4");
4254         if (!mlx4_wq)
4255                 return -ENOMEM;
4256
4257         ret = pci_register_driver(&mlx4_driver);
4258         if (ret < 0)
4259                 destroy_workqueue(mlx4_wq);
4260         return ret < 0 ? ret : 0;
4261 }
4262
4263 static void __exit mlx4_cleanup(void)
4264 {
4265         pci_unregister_driver(&mlx4_driver);
4266         destroy_workqueue(mlx4_wq);
4267 }
4268
4269 module_init(mlx4_init);
4270 module_exit(mlx4_cleanup);