drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/kmod.h>
  45
  46 #include <linux/mlx4/device.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "mlx4.h"
  50 #include "fw.h"
  51 #include "icm.h"
  52
  53 MODULE_AUTHOR("Roland Dreier");
  54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  55 MODULE_LICENSE("Dual BSD/GPL");
  56 MODULE_VERSION(DRV_VERSION);
  57
  58 struct workqueue_struct *mlx4_wq;
  59
  60 #ifdef CONFIG_MLX4_DEBUG
  61
  62 int mlx4_debug_level = 0;
  63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  65
  66 #endif /* CONFIG_MLX4_DEBUG */
  67
  68 #ifdef CONFIG_PCI_MSI
  69
  70 static int msi_x = 1;
  71 module_param(msi_x, int, 0444);
  72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  73
  74 #else /* CONFIG_PCI_MSI */
  75
  76 #define msi_x (0)
  77
  78 #endif /* CONFIG_PCI_MSI */
  79
  80 static uint8_t num_vfs[3] = {0, 0, 0};
  81 static int num_vfs_argc;
  82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
  83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
  84                           "num_vfs=port1,port2,port1+2");
  85
  86 static uint8_t probe_vf[3] = {0, 0, 0};
  87 static int probe_vfs_argc;
  88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
  89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
  90                            "probe_vf=port1,port2,port1+2");
  91
  92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  93 module_param_named(log_num_mgm_entry_size,
  94                         mlx4_log_num_mgm_entry_size, int, 0444);
  95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  96                                          " of qp per mcg, for example:"
  97                                          " 10 gives 248.range: 7 <="
  98                                          " log_num_mgm_entry_size <= 12."
  99                                          " To activate device managed"
 100                                          " flow steering when available, set to -1");
 101
 102 static bool enable_64b_cqe_eqe = true;
 103 module_param(enable_64b_cqe_eqe, bool, 0444);
 104 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 105                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 106
 107 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
 108                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
 109                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
 110
 111 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
 112
 113 static char mlx4_version[] =
 114         DRV_NAME ": Mellanox ConnectX core driver v"
 115         DRV_VERSION " (" DRV_RELDATE ")\n";
 116
 117 static struct mlx4_profile default_profile = {
 118         .num_qp         = 1 << 18,
 119         .num_srq        = 1 << 16,
 120         .rdmarc_per_qp  = 1 << 4,
 121         .num_cq         = 1 << 16,
 122         .num_mcg        = 1 << 13,
 123         .num_mpt        = 1 << 19,
 124         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 125 };
 126
 127 static struct mlx4_profile low_mem_profile = {
 128         .num_qp         = 1 << 17,
 129         .num_srq        = 1 << 6,
 130         .rdmarc_per_qp  = 1 << 4,
 131         .num_cq         = 1 << 8,
 132         .num_mcg        = 1 << 8,
 133         .num_mpt        = 1 << 9,
 134         .num_mtt        = 1 << 7,
 135 };
 136
 137 static int log_num_mac = 7;
 138 module_param_named(log_num_mac, log_num_mac, int, 0444);
 139 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 140
 141 static int log_num_vlan;
 142 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 143 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 144 /* Log2 max number of VLANs per ETH port (0-7) */
 145 #define MLX4_LOG_NUM_VLANS 7
 146 #define MLX4_MIN_LOG_NUM_VLANS 0
 147 #define MLX4_MIN_LOG_NUM_MAC 1
 148
 149 static bool use_prio;
 150 module_param_named(use_prio, use_prio, bool, 0444);
 151 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
 152
 153 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 154 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 155 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 156
 157 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 158 static int arr_argc = 2;
 159 module_param_array(port_type_array, int, &arr_argc, 0444);
 160 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 161                                 "1 for IB, 2 for Ethernet");
 162
 163 struct mlx4_port_config {
 164         struct list_head list;
 165         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 166         struct pci_dev *pdev;
 167 };
 168
 169 static atomic_t pf_loading = ATOMIC_INIT(0);
 170
 171 int mlx4_check_port_params(struct mlx4_dev *dev,
 172                            enum mlx4_port_type *port_type)
 173 {
 174         int i;
 175
 176         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 177                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
 178                         if (port_type[i] != port_type[i + 1]) {
 179                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
 180                                 return -EINVAL;
 181                         }
 182                 }
 183         }
 184
 185         for (i = 0; i < dev->caps.num_ports; i++) {
 186                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 187                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
 188                                  i + 1);
 189                         return -EINVAL;
 190                 }
 191         }
 192         return 0;
 193 }
 194
 195 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 196 {
 197         int i;
 198
 199         for (i = 1; i <= dev->caps.num_ports; ++i)
 200                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 201 }
 202
 203 enum {
 204         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
 205 };
 206
 207 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 208 {
 209         int err = 0;
 210         struct mlx4_func func;
 211
 212         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
 213                 err = mlx4_QUERY_FUNC(dev, &func, 0);
 214                 if (err) {
 215                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 216                         return err;
 217                 }
 218                 dev_cap->max_eqs = func.max_eq;
 219                 dev_cap->reserved_eqs = func.rsvd_eqs;
 220                 dev_cap->reserved_uars = func.rsvd_uars;
 221                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
 222         }
 223         return err;
 224 }
 225
 226 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
 227 {
 228         struct mlx4_caps *dev_cap = &dev->caps;
 229
 230         /* FW not supporting or cancelled by user */
 231         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
 232             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
 233                 return;
 234
 235         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
 236          * When FW has NCSI it may decide not to report 64B CQE/EQEs
 237          */
 238         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
 239             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
 240                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 241                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 242                 return;
 243         }
 244
 245         if (cache_line_size() == 128 || cache_line_size() == 256) {
 246                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
 247                 /* Changing the real data inside CQE size to 32B */
 248                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 249                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 250
 251                 if (mlx4_is_master(dev))
 252                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
 253         } else {
 254                 if (cache_line_size() != 32  && cache_line_size() != 64)
 255                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
 256                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 257                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 258         }
 259 }
 260
 261 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
 262                           struct mlx4_port_cap *port_cap)
 263 {
 264         dev->caps.vl_cap[port]      = port_cap->max_vl;
 265         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
 266         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
 267         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
 268         /* set gid and pkey table operating lengths by default
 269          * to non-sriov values
 270          */
 271         dev->caps.gid_table_len[port]  = port_cap->max_gids;
 272         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
 273         dev->caps.port_width_cap[port] = port_cap->max_port_width;
 274         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
 275         dev->caps.def_mac[port]        = port_cap->def_mac;
 276         dev->caps.supported_type[port] = port_cap->supported_port_types;
 277         dev->caps.suggested_type[port] = port_cap->suggested_type;
 278         dev->caps.default_sense[port] = port_cap->default_sense;
 279         dev->caps.trans_type[port]          = port_cap->trans_type;
 280         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
 281         dev->caps.wavelength[port]     = port_cap->wavelength;
 282         dev->caps.trans_code[port]     = port_cap->trans_code;
 283
 284         return 0;
 285 }
 286
 287 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
 288                          struct mlx4_port_cap *port_cap)
 289 {
 290         int err = 0;
 291
 292         err = mlx4_QUERY_PORT(dev, port, port_cap);
 293
 294         if (err)
 295                 mlx4_err(dev, "QUERY_PORT command failed.\n");
 296
 297         return err;
 298 }
 299
 300 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
 301 {
 302         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
 303                 return;
 304
 305         if (mlx4_is_mfunc(dev)) {
 306                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
 307                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 308                 return;
 309         }
 310
 311         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
 312                 mlx4_dbg(dev,
 313                          "Keep FCS is not supported - Disabling Ignore FCS");
 314                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 315                 return;
 316         }
 317 }
 318
 319 #define MLX4_A0_STEERING_TABLE_SIZE     256
 320 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 321 {
 322         int err;
 323         int i;
 324
 325         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 326         if (err) {
 327                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 328                 return err;
 329         }
 330         mlx4_dev_cap_dump(dev, dev_cap);
 331
 332         if (dev_cap->min_page_sz > PAGE_SIZE) {
 333                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 334                          dev_cap->min_page_sz, PAGE_SIZE);
 335                 return -ENODEV;
 336         }
 337         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 338                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 339                          dev_cap->num_ports, MLX4_MAX_PORTS);
 340                 return -ENODEV;
 341         }
 342
 343         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
 344                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 345                          dev_cap->uar_size,
 346                          (unsigned long long)
 347                          pci_resource_len(dev->persist->pdev, 2));
 348                 return -ENODEV;
 349         }
 350
 351         dev->caps.num_ports          = dev_cap->num_ports;
 352         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
 353         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
 354                                       dev->caps.num_sys_eqs :
 355                                       MLX4_MAX_EQ_NUM;
 356         for (i = 1; i <= dev->caps.num_ports; ++i) {
 357                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
 358                 if (err) {
 359                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
 360                         return err;
 361                 }
 362         }
 363
 364         dev->caps.uar_page_size      = PAGE_SIZE;
 365         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 366         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 367         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 368         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 369         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 370         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 371         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 372         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 373         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 374         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 375         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 376         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 377         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 378         /*
 379          * Subtract 1 from the limit because we need to allocate a
 380          * spare CQE so the HCA HW can tell the difference between an
 381          * empty CQ and a full CQ.
 382          */
 383         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 384         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 385         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 386         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 387         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 388
 389         /* The first 128 UARs are used for EQ doorbells */
 390         dev->caps.reserved_uars      = max_t(int, 128, dev_cap->reserved_uars);
 391         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 392         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 393                                         dev_cap->reserved_xrcds : 0;
 394         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 395                                         dev_cap->max_xrcds : 0;
 396         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 397
 398         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 399         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 400         dev->caps.flags              = dev_cap->flags;
 401         dev->caps.flags2             = dev_cap->flags2;
 402         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 403         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 404         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 405         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 406         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 407
 408         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
 409                 struct mlx4_init_hca_param hca_param;
 410
 411                 memset(&hca_param, 0, sizeof(hca_param));
 412                 err = mlx4_QUERY_HCA(dev, &hca_param);
 413                 /* Turn off PHV_EN flag in case phv_check_en is set.
 414                  * phv_check_en is a HW check that parse the packet and verify
 415                  * phv bit was reported correctly in the wqe. To allow QinQ
 416                  * PHV_EN flag should be set and phv_check_en must be cleared
 417                  * otherwise QinQ packets will be drop by the HW.
 418                  */
 419                 if (err || hca_param.phv_check_en)
 420                         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
 421         }
 422
 423         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 424         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 425                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 426         /* Don't do sense port on multifunction devices (for now at least) */
 427         if (mlx4_is_mfunc(dev))
 428                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 429
 430         if (mlx4_low_memory_profile()) {
 431                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
 432                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
 433         } else {
 434                 dev->caps.log_num_macs  = log_num_mac;
 435                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 436         }
 437
 438         for (i = 1; i <= dev->caps.num_ports; ++i) {
 439                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 440                 if (dev->caps.supported_type[i]) {
 441                         /* if only ETH is supported - assign ETH */
 442                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 443                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 444                         /* if only IB is supported, assign IB */
 445                         else if (dev->caps.supported_type[i] ==
 446                                  MLX4_PORT_TYPE_IB)
 447                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 448                         else {
 449                                 /* if IB and ETH are supported, we set the port
 450                                  * type according to user selection of port type;
 451                                  * if user selected none, take the FW hint */
 452                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 453                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 454                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 455                                 else
 456                                         dev->caps.port_type[i] = port_type_array[i - 1];
 457                         }
 458                 }
 459                 /*
 460                  * Link sensing is allowed on the port if 3 conditions are true:
 461                  * 1. Both protocols are supported on the port.
 462                  * 2. Different types are supported on the port
 463                  * 3. FW declared that it supports link sensing
 464                  */
 465                 mlx4_priv(dev)->sense.sense_allowed[i] =
 466                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 467                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 468                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 469
 470                 /*
 471                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 472                  * and perform sense_port FW command to try and set the correct
 473                  * port type from beginning
 474                  */
 475                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 476                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 477                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 478                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 479                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 480                                 dev->caps.port_type[i] = sensed_port;
 481                 } else {
 482                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 483                 }
 484
 485                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
 486                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
 487                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
 488                                   i, 1 << dev->caps.log_num_macs);
 489                 }
 490                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
 491                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
 492                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
 493                                   i, 1 << dev->caps.log_num_vlans);
 494                 }
 495         }
 496
 497         if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
 498             (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
 499             (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
 500                 mlx4_warn(dev,
 501                           "Granular QoS per VF not supported with IB/Eth configuration\n");
 502                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
 503         }
 504
 505         dev->caps.max_counters = dev_cap->max_counters;
 506
 507         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 508         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 509                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 510                 (1 << dev->caps.log_num_macs) *
 511                 (1 << dev->caps.log_num_vlans) *
 512                 dev->caps.num_ports;
 513         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 514
 515         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
 516             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
 517                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
 518         else
 519                 dev->caps.dmfs_high_rate_qpn_base =
 520                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 521
 522         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
 523             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
 524                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
 525                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
 526                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
 527         } else {
 528                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
 529                 dev->caps.dmfs_high_rate_qpn_base =
 530                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 531                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
 532         }
 533
 534         dev->caps.rl_caps = dev_cap->rl_caps;
 535
 536         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
 537                 dev->caps.dmfs_high_rate_qpn_range;
 538
 539         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 540                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 541                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 542                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 543
 544         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 545
 546         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 547                 if (dev_cap->flags &
 548                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 549                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 550                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 551                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 552                 }
 553
 554                 if (dev_cap->flags2 &
 555                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
 556                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
 557                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
 558                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 559                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 560                 }
 561         }
 562
 563         if ((dev->caps.flags &
 564             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 565             mlx4_is_master(dev))
 566                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 567
 568         if (!mlx4_is_slave(dev)) {
 569                 mlx4_enable_cqe_eqe_stride(dev);
 570                 dev->caps.alloc_res_qp_mask =
 571                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
 572                         MLX4_RESERVE_A0_QP;
 573
 574                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
 575                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
 576                         mlx4_warn(dev, "Old device ETS support detected\n");
 577                         mlx4_warn(dev, "Consider upgrading device FW.\n");
 578                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
 579                 }
 580
 581         } else {
 582                 dev->caps.alloc_res_qp_mask = 0;
 583         }
 584
 585         mlx4_enable_ignore_fcs(dev);
 586
 587         return 0;
 588 }
 589
 590 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 591                                        enum pci_bus_speed *speed,
 592                                        enum pcie_link_width *width)
 593 {
 594         u32 lnkcap1, lnkcap2;
 595         int err1, err2;
 596
 597 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 598
 599         *speed = PCI_SPEED_UNKNOWN;
 600         *width = PCIE_LNK_WIDTH_UNKNOWN;
 601
 602         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
 603                                           &lnkcap1);
 604         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
 605                                           &lnkcap2);
 606         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 607                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 608                         *speed = PCIE_SPEED_8_0GT;
 609                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 610                         *speed = PCIE_SPEED_5_0GT;
 611                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 612                         *speed = PCIE_SPEED_2_5GT;
 613         }
 614         if (!err1) {
 615                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 616                 if (!lnkcap2) { /* pre-r3.0 */
 617                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 618                                 *speed = PCIE_SPEED_5_0GT;
 619                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 620                                 *speed = PCIE_SPEED_2_5GT;
 621                 }
 622         }
 623
 624         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 625                 return err1 ? err1 :
 626                         err2 ? err2 : -EINVAL;
 627         }
 628         return 0;
 629 }
 630
 631 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 632 {
 633         enum pcie_link_width width, width_cap;
 634         enum pci_bus_speed speed, speed_cap;
 635         int err;
 636
 637 #define PCIE_SPEED_STR(speed) \
 638         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 639          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 640          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 641          "Unknown")
 642
 643         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 644         if (err) {
 645                 mlx4_warn(dev,
 646                           "Unable to determine PCIe device BW capabilities\n");
 647                 return;
 648         }
 649
 650         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
 651         if (err || speed == PCI_SPEED_UNKNOWN ||
 652             width == PCIE_LNK_WIDTH_UNKNOWN) {
 653                 mlx4_warn(dev,
 654                           "Unable to determine PCI device chain minimum BW\n");
 655                 return;
 656         }
 657
 658         if (width != width_cap || speed != speed_cap)
 659                 mlx4_warn(dev,
 660                           "PCIe BW is different than device's capability\n");
 661
 662         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 663                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 664         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 665                   width, width_cap);
 666         return;
 667 }
 668
 669 /*The function checks if there are live vf, return the num of them*/
 670 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 671 {
 672         struct mlx4_priv *priv = mlx4_priv(dev);
 673         struct mlx4_slave_state *s_state;
 674         int i;
 675         int ret = 0;
 676
 677         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 678                 s_state = &priv->mfunc.master.slave_state[i];
 679                 if (s_state->active && s_state->last_cmd !=
 680                     MLX4_COMM_CMD_RESET) {
 681                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 682                                   __func__, i);
 683                         ret++;
 684                 }
 685         }
 686         return ret;
 687 }
 688
 689 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 690 {
 691         u32 qk = MLX4_RESERVED_QKEY_BASE;
 692
 693         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 694             qpn < dev->phys_caps.base_proxy_sqpn)
 695                 return -EINVAL;
 696
 697         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 698                 /* tunnel qp */
 699                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 700         else
 701                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 702         *qkey = qk;
 703         return 0;
 704 }
 705 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 706
 707 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 708 {
 709         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 710
 711         if (!mlx4_is_master(dev))
 712                 return;
 713
 714         priv->virt2phys_pkey[slave][port - 1][i] = val;
 715 }
 716 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 717
 718 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 719 {
 720         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 721
 722         if (!mlx4_is_master(dev))
 723                 return;
 724
 725         priv->slave_node_guids[slave] = guid;
 726 }
 727 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 728
 729 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 730 {
 731         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 732
 733         if (!mlx4_is_master(dev))
 734                 return 0;
 735
 736         return priv->slave_node_guids[slave];
 737 }
 738 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 739
 740 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 741 {
 742         struct mlx4_priv *priv = mlx4_priv(dev);
 743         struct mlx4_slave_state *s_slave;
 744
 745         if (!mlx4_is_master(dev))
 746                 return 0;
 747
 748         s_slave = &priv->mfunc.master.slave_state[slave];
 749         return !!s_slave->active;
 750 }
 751 EXPORT_SYMBOL(mlx4_is_slave_active);
 752
 753 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 754                                        struct mlx4_dev_cap *dev_cap,
 755                                        struct mlx4_init_hca_param *hca_param)
 756 {
 757         dev->caps.steering_mode = hca_param->steering_mode;
 758         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 759                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 760                 dev->caps.fs_log_max_ucast_qp_range_size =
 761                         dev_cap->fs_log_max_ucast_qp_range_size;
 762         } else
 763                 dev->caps.num_qp_per_mgm =
 764                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 765
 766         mlx4_dbg(dev, "Steering mode is: %s\n",
 767                  mlx4_steering_mode_str(dev->caps.steering_mode));
 768 }
 769
 770 static int mlx4_slave_cap(struct mlx4_dev *dev)
 771 {
 772         int                        err;
 773         u32                        page_size;
 774         struct mlx4_dev_cap        dev_cap;
 775         struct mlx4_func_cap       func_cap;
 776         struct mlx4_init_hca_param hca_param;
 777         u8                         i;
 778
 779         memset(&hca_param, 0, sizeof(hca_param));
 780         err = mlx4_QUERY_HCA(dev, &hca_param);
 781         if (err) {
 782                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
 783                 return err;
 784         }
 785
 786         /* fail if the hca has an unknown global capability
 787          * at this time global_caps should be always zeroed
 788          */
 789         if (hca_param.global_caps) {
 790                 mlx4_err(dev, "Unknown hca global capabilities\n");
 791                 return -ENOSYS;
 792         }
 793
 794         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 795
 796         memset(&dev_cap, 0, sizeof(dev_cap));
 797         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 798         err = mlx4_dev_cap(dev, &dev_cap);
 799         if (err) {
 800                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 801                 return err;
 802         }
 803
 804         err = mlx4_QUERY_FW(dev);
 805         if (err)
 806                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
 807
 808         page_size = ~dev->caps.page_size_cap + 1;
 809         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 810         if (page_size > PAGE_SIZE) {
 811                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 812                          page_size, PAGE_SIZE);
 813                 return -ENODEV;
 814         }
 815
 816         /* slave gets uar page size from QUERY_HCA fw command */
 817         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
 818
 819         /* TODO: relax this assumption */
 820         if (dev->caps.uar_page_size != PAGE_SIZE) {
 821                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
 822                          dev->caps.uar_page_size, PAGE_SIZE);
 823                 return -ENODEV;
 824         }
 825
 826         memset(&func_cap, 0, sizeof(func_cap));
 827         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 828         if (err) {
 829                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
 830                          err);
 831                 return err;
 832         }
 833
 834         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 835             PF_CONTEXT_BEHAVIOUR_MASK) {
 836                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
 837                          func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
 838                 return -ENOSYS;
 839         }
 840
 841         dev->caps.num_ports             = func_cap.num_ports;
 842         dev->quotas.qp                  = func_cap.qp_quota;
 843         dev->quotas.srq                 = func_cap.srq_quota;
 844         dev->quotas.cq                  = func_cap.cq_quota;
 845         dev->quotas.mpt                 = func_cap.mpt_quota;
 846         dev->quotas.mtt                 = func_cap.mtt_quota;
 847         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 848         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 849         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 850         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 851         dev->caps.num_eqs               = func_cap.max_eq;
 852         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 853         dev->caps.reserved_lkey         = func_cap.reserved_lkey;
 854         dev->caps.num_pds               = MLX4_NUM_PDS;
 855         dev->caps.num_mgms              = 0;
 856         dev->caps.num_amgms             = 0;
 857
 858         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 859                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 860                          dev->caps.num_ports, MLX4_MAX_PORTS);
 861                 return -ENODEV;
 862         }
 863
 864         mlx4_replace_zero_macs(dev);
 865
 866         dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
 867         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 868         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 869         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 870         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 871
 872         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 873             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
 874             !dev->caps.qp0_qkey) {
 875                 err = -ENOMEM;
 876                 goto err_mem;
 877         }
 878
 879         for (i = 1; i <= dev->caps.num_ports; ++i) {
 880                 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
 881                 if (err) {
 882                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
 883                                  i, err);
 884                         goto err_mem;
 885                 }
 886                 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
 887                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 888                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 889                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 890                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 891                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 892                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 893                 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 894                                                       &dev->caps.gid_table_len[i],
 895                                                       &dev->caps.pkey_table_len[i]);
 896                 if (err)
 897                         goto err_mem;
 898         }
 899
 900         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 901                                        dev->caps.reserved_uars) >
 902                                        pci_resource_len(dev->persist->pdev,
 903                                                         2)) {
 904                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 905                          dev->caps.uar_page_size * dev->caps.num_uars,
 906                          (unsigned long long)
 907                          pci_resource_len(dev->persist->pdev, 2));
 908                 err = -ENOMEM;
 909                 goto err_mem;
 910         }
 911
 912         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 913                 dev->caps.eqe_size   = 64;
 914                 dev->caps.eqe_factor = 1;
 915         } else {
 916                 dev->caps.eqe_size   = 32;
 917                 dev->caps.eqe_factor = 0;
 918         }
 919
 920         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 921                 dev->caps.cqe_size   = 64;
 922                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 923         } else {
 924                 dev->caps.cqe_size   = 32;
 925         }
 926
 927         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
 928                 dev->caps.eqe_size = hca_param.eqe_size;
 929                 dev->caps.eqe_factor = 0;
 930         }
 931
 932         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
 933                 dev->caps.cqe_size = hca_param.cqe_size;
 934                 /* User still need to know when CQE > 32B */
 935                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 936         }
 937
 938         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 939         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
 940
 941         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 942         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
 943                  hca_param.rss_ip_frags ? "on" : "off");
 944
 945         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
 946             dev->caps.bf_reg_size)
 947                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
 948
 949         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
 950                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
 951
 952         return 0;
 953
 954 err_mem:
 955         kfree(dev->caps.qp0_qkey);
 956         kfree(dev->caps.qp0_tunnel);
 957         kfree(dev->caps.qp0_proxy);
 958         kfree(dev->caps.qp1_tunnel);
 959         kfree(dev->caps.qp1_proxy);
 960         dev->caps.qp0_qkey = NULL;
 961         dev->caps.qp0_tunnel = NULL;
 962         dev->caps.qp0_proxy = NULL;
 963         dev->caps.qp1_tunnel = NULL;
 964         dev->caps.qp1_proxy = NULL;
 965
 966         return err;
 967 }
 968
 969 static void mlx4_request_modules(struct mlx4_dev *dev)
 970 {
 971         int port;
 972         int has_ib_port = false;
 973         int has_eth_port = false;
 974 #define EN_DRV_NAME     "mlx4_en"
 975 #define IB_DRV_NAME     "mlx4_ib"
 976
 977         for (port = 1; port <= dev->caps.num_ports; port++) {
 978                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
 979                         has_ib_port = true;
 980                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
 981                         has_eth_port = true;
 982         }
 983
 984         if (has_eth_port)
 985                 request_module_nowait(EN_DRV_NAME);
 986         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
 987                 request_module_nowait(IB_DRV_NAME);
 988 }
 989
 990 /*
 991  * Change the port configuration of the device.
 992  * Every user of this function must hold the port mutex.
 993  */
 994 int mlx4_change_port_types(struct mlx4_dev *dev,
 995                            enum mlx4_port_type *port_types)
 996 {
 997         int err = 0;
 998         int change = 0;
 999         int port;
1000
1001         for (port = 0; port <  dev->caps.num_ports; port++) {
1002                 /* Change the port type only if the new type is different
1003                  * from the current, and not set to Auto */
1004                 if (port_types[port] != dev->caps.port_type[port + 1])
1005                         change = 1;
1006         }
1007         if (change) {
1008                 mlx4_unregister_device(dev);
1009                 for (port = 1; port <= dev->caps.num_ports; port++) {
1010                         mlx4_CLOSE_PORT(dev, port);
1011                         dev->caps.port_type[port] = port_types[port - 1];
1012                         err = mlx4_SET_PORT(dev, port, -1);
1013                         if (err) {
1014                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1015                                          port);
1016                                 goto out;
1017                         }
1018                 }
1019                 mlx4_set_port_mask(dev);
1020                 err = mlx4_register_device(dev);
1021                 if (err) {
1022                         mlx4_err(dev, "Failed to register device\n");
1023                         goto out;
1024                 }
1025                 mlx4_request_modules(dev);
1026         }
1027
1028 out:
1029         return err;
1030 }
1031
1032 static ssize_t show_port_type(struct device *dev,
1033                               struct device_attribute *attr,
1034                               char *buf)
1035 {
1036         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1037                                                    port_attr);
1038         struct mlx4_dev *mdev = info->dev;
1039         char type[8];
1040
1041         sprintf(type, "%s",
1042                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1043                 "ib" : "eth");
1044         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1045                 sprintf(buf, "auto (%s)\n", type);
1046         else
1047                 sprintf(buf, "%s\n", type);
1048
1049         return strlen(buf);
1050 }
1051
1052 static ssize_t set_port_type(struct device *dev,
1053                              struct device_attribute *attr,
1054                              const char *buf, size_t count)
1055 {
1056         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1057                                                    port_attr);
1058         struct mlx4_dev *mdev = info->dev;
1059         struct mlx4_priv *priv = mlx4_priv(mdev);
1060         enum mlx4_port_type types[MLX4_MAX_PORTS];
1061         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1062         static DEFINE_MUTEX(set_port_type_mutex);
1063         int i;
1064         int err = 0;
1065
1066         mutex_lock(&set_port_type_mutex);
1067
1068         if (!strcmp(buf, "ib\n"))
1069                 info->tmp_type = MLX4_PORT_TYPE_IB;
1070         else if (!strcmp(buf, "eth\n"))
1071                 info->tmp_type = MLX4_PORT_TYPE_ETH;
1072         else if (!strcmp(buf, "auto\n"))
1073                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1074         else {
1075                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1076                 err = -EINVAL;
1077                 goto err_out;
1078         }
1079
1080         mlx4_stop_sense(mdev);
1081         mutex_lock(&priv->port_mutex);
1082         /* Possible type is always the one that was delivered */
1083         mdev->caps.possible_type[info->port] = info->tmp_type;
1084
1085         for (i = 0; i < mdev->caps.num_ports; i++) {
1086                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1087                                         mdev->caps.possible_type[i+1];
1088                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1089                         types[i] = mdev->caps.port_type[i+1];
1090         }
1091
1092         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1093             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1094                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1095                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1096                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1097                                 err = -EINVAL;
1098                         }
1099                 }
1100         }
1101         if (err) {
1102                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1103                 goto out;
1104         }
1105
1106         mlx4_do_sense_ports(mdev, new_types, types);
1107
1108         err = mlx4_check_port_params(mdev, new_types);
1109         if (err)
1110                 goto out;
1111
1112         /* We are about to apply the changes after the configuration
1113          * was verified, no need to remember the temporary types
1114          * any more */
1115         for (i = 0; i < mdev->caps.num_ports; i++)
1116                 priv->port[i + 1].tmp_type = 0;
1117
1118         err = mlx4_change_port_types(mdev, new_types);
1119
1120 out:
1121         mlx4_start_sense(mdev);
1122         mutex_unlock(&priv->port_mutex);
1123 err_out:
1124         mutex_unlock(&set_port_type_mutex);
1125
1126         return err ? err : count;
1127 }
1128
1129 enum ibta_mtu {
1130         IB_MTU_256  = 1,
1131         IB_MTU_512  = 2,
1132         IB_MTU_1024 = 3,
1133         IB_MTU_2048 = 4,
1134         IB_MTU_4096 = 5
1135 };
1136
1137 static inline int int_to_ibta_mtu(int mtu)
1138 {
1139         switch (mtu) {
1140         case 256:  return IB_MTU_256;
1141         case 512:  return IB_MTU_512;
1142         case 1024: return IB_MTU_1024;
1143         case 2048: return IB_MTU_2048;
1144         case 4096: return IB_MTU_4096;
1145         default: return -1;
1146         }
1147 }
1148
1149 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1150 {
1151         switch (mtu) {
1152         case IB_MTU_256:  return  256;
1153         case IB_MTU_512:  return  512;
1154         case IB_MTU_1024: return 1024;
1155         case IB_MTU_2048: return 2048;
1156         case IB_MTU_4096: return 4096;
1157         default: return -1;
1158         }
1159 }
1160
1161 static ssize_t show_port_ib_mtu(struct device *dev,
1162                              struct device_attribute *attr,
1163                              char *buf)
1164 {
1165         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1166                                                    port_mtu_attr);
1167         struct mlx4_dev *mdev = info->dev;
1168
1169         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1170                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1171
1172         sprintf(buf, "%d\n",
1173                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1174         return strlen(buf);
1175 }
1176
1177 static ssize_t set_port_ib_mtu(struct device *dev,
1178                              struct device_attribute *attr,
1179                              const char *buf, size_t count)
1180 {
1181         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1182                                                    port_mtu_attr);
1183         struct mlx4_dev *mdev = info->dev;
1184         struct mlx4_priv *priv = mlx4_priv(mdev);
1185         int err, port, mtu, ibta_mtu = -1;
1186
1187         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1188                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1189                 return -EINVAL;
1190         }
1191
1192         err = kstrtoint(buf, 0, &mtu);
1193         if (!err)
1194                 ibta_mtu = int_to_ibta_mtu(mtu);
1195
1196         if (err || ibta_mtu < 0) {
1197                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1198                 return -EINVAL;
1199         }
1200
1201         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1202
1203         mlx4_stop_sense(mdev);
1204         mutex_lock(&priv->port_mutex);
1205         mlx4_unregister_device(mdev);
1206         for (port = 1; port <= mdev->caps.num_ports; port++) {
1207                 mlx4_CLOSE_PORT(mdev, port);
1208                 err = mlx4_SET_PORT(mdev, port, -1);
1209                 if (err) {
1210                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1211                                  port);
1212                         goto err_set_port;
1213                 }
1214         }
1215         err = mlx4_register_device(mdev);
1216 err_set_port:
1217         mutex_unlock(&priv->port_mutex);
1218         mlx4_start_sense(mdev);
1219         return err ? err : count;
1220 }
1221
1222 int mlx4_bond(struct mlx4_dev *dev)
1223 {
1224         int ret = 0;
1225         struct mlx4_priv *priv = mlx4_priv(dev);
1226
1227         mutex_lock(&priv->bond_mutex);
1228
1229         if (!mlx4_is_bonded(dev))
1230                 ret = mlx4_do_bond(dev, true);
1231         else
1232                 ret = 0;
1233
1234         mutex_unlock(&priv->bond_mutex);
1235         if (ret)
1236                 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1237         else
1238                 mlx4_dbg(dev, "Device is bonded\n");
1239         return ret;
1240 }
1241 EXPORT_SYMBOL_GPL(mlx4_bond);
1242
1243 int mlx4_unbond(struct mlx4_dev *dev)
1244 {
1245         int ret = 0;
1246         struct mlx4_priv *priv = mlx4_priv(dev);
1247
1248         mutex_lock(&priv->bond_mutex);
1249
1250         if (mlx4_is_bonded(dev))
1251                 ret = mlx4_do_bond(dev, false);
1252
1253         mutex_unlock(&priv->bond_mutex);
1254         if (ret)
1255                 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1256         else
1257                 mlx4_dbg(dev, "Device is unbonded\n");
1258         return ret;
1259 }
1260 EXPORT_SYMBOL_GPL(mlx4_unbond);
1261
1262
1263 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1264 {
1265         u8 port1 = v2p->port1;
1266         u8 port2 = v2p->port2;
1267         struct mlx4_priv *priv = mlx4_priv(dev);
1268         int err;
1269
1270         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1271                 return -ENOTSUPP;
1272
1273         mutex_lock(&priv->bond_mutex);
1274
1275         /* zero means keep current mapping for this port */
1276         if (port1 == 0)
1277                 port1 = priv->v2p.port1;
1278         if (port2 == 0)
1279                 port2 = priv->v2p.port2;
1280
1281         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1282             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1283             (port1 == 2 && port2 == 1)) {
1284                 /* besides boundary checks cross mapping makes
1285                  * no sense and therefore not allowed */
1286                 err = -EINVAL;
1287         } else if ((port1 == priv->v2p.port1) &&
1288                  (port2 == priv->v2p.port2)) {
1289                 err = 0;
1290         } else {
1291                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1292                 if (!err) {
1293                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1294                                  port1, port2);
1295                         priv->v2p.port1 = port1;
1296                         priv->v2p.port2 = port2;
1297                 } else {
1298                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1299                 }
1300         }
1301
1302         mutex_unlock(&priv->bond_mutex);
1303         return err;
1304 }
1305 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1306
1307 static int mlx4_load_fw(struct mlx4_dev *dev)
1308 {
1309         struct mlx4_priv *priv = mlx4_priv(dev);
1310         int err;
1311
1312         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1313                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1314         if (!priv->fw.fw_icm) {
1315                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1316                 return -ENOMEM;
1317         }
1318
1319         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1320         if (err) {
1321                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1322                 goto err_free;
1323         }
1324
1325         err = mlx4_RUN_FW(dev);
1326         if (err) {
1327                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1328                 goto err_unmap_fa;
1329         }
1330
1331         return 0;
1332
1333 err_unmap_fa:
1334         mlx4_UNMAP_FA(dev);
1335
1336 err_free:
1337         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1338         return err;
1339 }
1340
1341 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1342                                 int cmpt_entry_sz)
1343 {
1344         struct mlx4_priv *priv = mlx4_priv(dev);
1345         int err;
1346         int num_eqs;
1347
1348         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1349                                   cmpt_base +
1350                                   ((u64) (MLX4_CMPT_TYPE_QP *
1351                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1352                                   cmpt_entry_sz, dev->caps.num_qps,
1353                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1354                                   0, 0);
1355         if (err)
1356                 goto err;
1357
1358         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1359                                   cmpt_base +
1360                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1361                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1362                                   cmpt_entry_sz, dev->caps.num_srqs,
1363                                   dev->caps.reserved_srqs, 0, 0);
1364         if (err)
1365                 goto err_qp;
1366
1367         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1368                                   cmpt_base +
1369                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1370                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1371                                   cmpt_entry_sz, dev->caps.num_cqs,
1372                                   dev->caps.reserved_cqs, 0, 0);
1373         if (err)
1374                 goto err_srq;
1375
1376         num_eqs = dev->phys_caps.num_phys_eqs;
1377         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1378                                   cmpt_base +
1379                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1380                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1381                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1382         if (err)
1383                 goto err_cq;
1384
1385         return 0;
1386
1387 err_cq:
1388         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1389
1390 err_srq:
1391         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1392
1393 err_qp:
1394         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1395
1396 err:
1397         return err;
1398 }
1399
1400 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1401                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1402 {
1403         struct mlx4_priv *priv = mlx4_priv(dev);
1404         u64 aux_pages;
1405         int num_eqs;
1406         int err;
1407
1408         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1409         if (err) {
1410                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1411                 return err;
1412         }
1413
1414         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1415                  (unsigned long long) icm_size >> 10,
1416                  (unsigned long long) aux_pages << 2);
1417
1418         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1419                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1420         if (!priv->fw.aux_icm) {
1421                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1422                 return -ENOMEM;
1423         }
1424
1425         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1426         if (err) {
1427                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1428                 goto err_free_aux;
1429         }
1430
1431         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1432         if (err) {
1433                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1434                 goto err_unmap_aux;
1435         }
1436
1437
1438         num_eqs = dev->phys_caps.num_phys_eqs;
1439         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1440                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1441                                   num_eqs, num_eqs, 0, 0);
1442         if (err) {
1443                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1444                 goto err_unmap_cmpt;
1445         }
1446
1447         /*
1448          * Reserved MTT entries must be aligned up to a cacheline
1449          * boundary, since the FW will write to them, while the driver
1450          * writes to all other MTT entries. (The variable
1451          * dev->caps.mtt_entry_sz below is really the MTT segment
1452          * size, not the raw entry size)
1453          */
1454         dev->caps.reserved_mtts =
1455                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1456                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1457
1458         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1459                                   init_hca->mtt_base,
1460                                   dev->caps.mtt_entry_sz,
1461                                   dev->caps.num_mtts,
1462                                   dev->caps.reserved_mtts, 1, 0);
1463         if (err) {
1464                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1465                 goto err_unmap_eq;
1466         }
1467
1468         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1469                                   init_hca->dmpt_base,
1470                                   dev_cap->dmpt_entry_sz,
1471                                   dev->caps.num_mpts,
1472                                   dev->caps.reserved_mrws, 1, 1);
1473         if (err) {
1474                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1475                 goto err_unmap_mtt;
1476         }
1477
1478         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1479                                   init_hca->qpc_base,
1480                                   dev_cap->qpc_entry_sz,
1481                                   dev->caps.num_qps,
1482                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1483                                   0, 0);
1484         if (err) {
1485                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1486                 goto err_unmap_dmpt;
1487         }
1488
1489         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1490                                   init_hca->auxc_base,
1491                                   dev_cap->aux_entry_sz,
1492                                   dev->caps.num_qps,
1493                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1494                                   0, 0);
1495         if (err) {
1496                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1497                 goto err_unmap_qp;
1498         }
1499
1500         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1501                                   init_hca->altc_base,
1502                                   dev_cap->altc_entry_sz,
1503                                   dev->caps.num_qps,
1504                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1505                                   0, 0);
1506         if (err) {
1507                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1508                 goto err_unmap_auxc;
1509         }
1510
1511         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1512                                   init_hca->rdmarc_base,
1513                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1514                                   dev->caps.num_qps,
1515                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1516                                   0, 0);
1517         if (err) {
1518                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1519                 goto err_unmap_altc;
1520         }
1521
1522         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1523                                   init_hca->cqc_base,
1524                                   dev_cap->cqc_entry_sz,
1525                                   dev->caps.num_cqs,
1526                                   dev->caps.reserved_cqs, 0, 0);
1527         if (err) {
1528                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1529                 goto err_unmap_rdmarc;
1530         }
1531
1532         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1533                                   init_hca->srqc_base,
1534                                   dev_cap->srq_entry_sz,
1535                                   dev->caps.num_srqs,
1536                                   dev->caps.reserved_srqs, 0, 0);
1537         if (err) {
1538                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1539                 goto err_unmap_cq;
1540         }
1541
1542         /*
1543          * For flow steering device managed mode it is required to use
1544          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1545          * required, but for simplicity just map the whole multicast
1546          * group table now.  The table isn't very big and it's a lot
1547          * easier than trying to track ref counts.
1548          */
1549         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1550                                   init_hca->mc_base,
1551                                   mlx4_get_mgm_entry_size(dev),
1552                                   dev->caps.num_mgms + dev->caps.num_amgms,
1553                                   dev->caps.num_mgms + dev->caps.num_amgms,
1554                                   0, 0);
1555         if (err) {
1556                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1557                 goto err_unmap_srq;
1558         }
1559
1560         return 0;
1561
1562 err_unmap_srq:
1563         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1564
1565 err_unmap_cq:
1566         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1567
1568 err_unmap_rdmarc:
1569         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1570
1571 err_unmap_altc:
1572         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1573
1574 err_unmap_auxc:
1575         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1576
1577 err_unmap_qp:
1578         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1579
1580 err_unmap_dmpt:
1581         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1582
1583 err_unmap_mtt:
1584         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1585
1586 err_unmap_eq:
1587         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1588
1589 err_unmap_cmpt:
1590         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1591         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1592         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1593         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1594
1595 err_unmap_aux:
1596         mlx4_UNMAP_ICM_AUX(dev);
1597
1598 err_free_aux:
1599         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1600
1601         return err;
1602 }
1603
1604 static void mlx4_free_icms(struct mlx4_dev *dev)
1605 {
1606         struct mlx4_priv *priv = mlx4_priv(dev);
1607
1608         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1609         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1610         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1611         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1612         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1613         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1614         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1615         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1616         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1617         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1618         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1619         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1620         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1621         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1622
1623         mlx4_UNMAP_ICM_AUX(dev);
1624         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1625 }
1626
1627 static void mlx4_slave_exit(struct mlx4_dev *dev)
1628 {
1629         struct mlx4_priv *priv = mlx4_priv(dev);
1630
1631         mutex_lock(&priv->cmd.slave_cmd_mutex);
1632         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1633                           MLX4_COMM_TIME))
1634                 mlx4_warn(dev, "Failed to close slave function\n");
1635         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1636 }
1637
1638 static int map_bf_area(struct mlx4_dev *dev)
1639 {
1640         struct mlx4_priv *priv = mlx4_priv(dev);
1641         resource_size_t bf_start;
1642         resource_size_t bf_len;
1643         int err = 0;
1644
1645         if (!dev->caps.bf_reg_size)
1646                 return -ENXIO;
1647
1648         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1649                         (dev->caps.num_uars << PAGE_SHIFT);
1650         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1651                         (dev->caps.num_uars << PAGE_SHIFT);
1652         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1653         if (!priv->bf_mapping)
1654                 err = -ENOMEM;
1655
1656         return err;
1657 }
1658
1659 static void unmap_bf_area(struct mlx4_dev *dev)
1660 {
1661         if (mlx4_priv(dev)->bf_mapping)
1662                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1663 }
1664
1665 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1666 {
1667         u32 clockhi, clocklo, clockhi1;
1668         cycle_t cycles;
1669         int i;
1670         struct mlx4_priv *priv = mlx4_priv(dev);
1671
1672         for (i = 0; i < 10; i++) {
1673                 clockhi = swab32(readl(priv->clock_mapping));
1674                 clocklo = swab32(readl(priv->clock_mapping + 4));
1675                 clockhi1 = swab32(readl(priv->clock_mapping));
1676                 if (clockhi == clockhi1)
1677                         break;
1678         }
1679
1680         cycles = (u64) clockhi << 32 | (u64) clocklo;
1681
1682         return cycles;
1683 }
1684 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1685
1686
1687 static int map_internal_clock(struct mlx4_dev *dev)
1688 {
1689         struct mlx4_priv *priv = mlx4_priv(dev);
1690
1691         priv->clock_mapping =
1692                 ioremap(pci_resource_start(dev->persist->pdev,
1693                                            priv->fw.clock_bar) +
1694                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1695
1696         if (!priv->clock_mapping)
1697                 return -ENOMEM;
1698
1699         return 0;
1700 }
1701
1702 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1703                                    struct mlx4_clock_params *params)
1704 {
1705         struct mlx4_priv *priv = mlx4_priv(dev);
1706
1707         if (mlx4_is_slave(dev))
1708                 return -ENOTSUPP;
1709
1710         if (!params)
1711                 return -EINVAL;
1712
1713         params->bar = priv->fw.clock_bar;
1714         params->offset = priv->fw.clock_offset;
1715         params->size = MLX4_CLOCK_SIZE;
1716
1717         return 0;
1718 }
1719 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1720
1721 static void unmap_internal_clock(struct mlx4_dev *dev)
1722 {
1723         struct mlx4_priv *priv = mlx4_priv(dev);
1724
1725         if (priv->clock_mapping)
1726                 iounmap(priv->clock_mapping);
1727 }
1728
1729 static void mlx4_close_hca(struct mlx4_dev *dev)
1730 {
1731         unmap_internal_clock(dev);
1732         unmap_bf_area(dev);
1733         if (mlx4_is_slave(dev))
1734                 mlx4_slave_exit(dev);
1735         else {
1736                 mlx4_CLOSE_HCA(dev, 0);
1737                 mlx4_free_icms(dev);
1738         }
1739 }
1740
1741 static void mlx4_close_fw(struct mlx4_dev *dev)
1742 {
1743         if (!mlx4_is_slave(dev)) {
1744                 mlx4_UNMAP_FA(dev);
1745                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1746         }
1747 }
1748
1749 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1750 {
1751 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1752
1753         u32 comm_flags;
1754         u32 offline_bit;
1755         unsigned long end;
1756         struct mlx4_priv *priv = mlx4_priv(dev);
1757
1758         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1759         while (time_before(jiffies, end)) {
1760                 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1761                                           MLX4_COMM_CHAN_FLAGS));
1762                 offline_bit = (comm_flags &
1763                                (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1764                 if (!offline_bit)
1765                         return 0;
1766
1767                 /* If device removal has been requested,
1768                  * do not continue retrying.
1769                  */
1770                 if (dev->persist->interface_state &
1771                     MLX4_INTERFACE_STATE_NOWAIT)
1772                         break;
1773
1774                 /* There are cases as part of AER/Reset flow that PF needs
1775                  * around 100 msec to load. We therefore sleep for 100 msec
1776                  * to allow other tasks to make use of that CPU during this
1777                  * time interval.
1778                  */
1779                 msleep(100);
1780         }
1781         mlx4_err(dev, "Communication channel is offline.\n");
1782         return -EIO;
1783 }
1784
1785 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1786 {
1787 #define COMM_CHAN_RST_OFFSET 0x1e
1788
1789         struct mlx4_priv *priv = mlx4_priv(dev);
1790         u32 comm_rst;
1791         u32 comm_caps;
1792
1793         comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1794                                  MLX4_COMM_CHAN_CAPS));
1795         comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1796
1797         if (comm_rst)
1798                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1799 }
1800
1801 static int mlx4_init_slave(struct mlx4_dev *dev)
1802 {
1803         struct mlx4_priv *priv = mlx4_priv(dev);
1804         u64 dma = (u64) priv->mfunc.vhcr_dma;
1805         int ret_from_reset = 0;
1806         u32 slave_read;
1807         u32 cmd_channel_ver;
1808
1809         if (atomic_read(&pf_loading)) {
1810                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1811                 return -EPROBE_DEFER;
1812         }
1813
1814         mutex_lock(&priv->cmd.slave_cmd_mutex);
1815         priv->cmd.max_cmds = 1;
1816         if (mlx4_comm_check_offline(dev)) {
1817                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1818                 goto err_offline;
1819         }
1820
1821         mlx4_reset_vf_support(dev);
1822         mlx4_warn(dev, "Sending reset\n");
1823         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1824                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1825         /* if we are in the middle of flr the slave will try
1826          * NUM_OF_RESET_RETRIES times before leaving.*/
1827         if (ret_from_reset) {
1828                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1829                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1830                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1831                         return -EPROBE_DEFER;
1832                 } else
1833                         goto err;
1834         }
1835
1836         /* check the driver version - the slave I/F revision
1837          * must match the master's */
1838         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1839         cmd_channel_ver = mlx4_comm_get_version();
1840
1841         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1842                 MLX4_COMM_GET_IF_REV(slave_read)) {
1843                 mlx4_err(dev, "slave driver version is not supported by the master\n");
1844                 goto err;
1845         }
1846
1847         mlx4_warn(dev, "Sending vhcr0\n");
1848         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1849                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1850                 goto err;
1851         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1852                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1853                 goto err;
1854         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1855                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1856                 goto err;
1857         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1858                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1859                 goto err;
1860
1861         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1862         return 0;
1863
1864 err:
1865         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
1866 err_offline:
1867         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1868         return -EIO;
1869 }
1870
1871 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1872 {
1873         int i;
1874
1875         for (i = 1; i <= dev->caps.num_ports; i++) {
1876                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1877                         dev->caps.gid_table_len[i] =
1878                                 mlx4_get_slave_num_gids(dev, 0, i);
1879                 else
1880                         dev->caps.gid_table_len[i] = 1;
1881                 dev->caps.pkey_table_len[i] =
1882                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1883         }
1884 }
1885
1886 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1887 {
1888         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1889
1890         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1891               i++) {
1892                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1893                         break;
1894         }
1895
1896         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1897 }
1898
1899 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1900 {
1901         switch (dmfs_high_steer_mode) {
1902         case MLX4_STEERING_DMFS_A0_DEFAULT:
1903                 return "default performance";
1904
1905         case MLX4_STEERING_DMFS_A0_DYNAMIC:
1906                 return "dynamic hybrid mode";
1907
1908         case MLX4_STEERING_DMFS_A0_STATIC:
1909                 return "performance optimized for limited rule configuration (static)";
1910
1911         case MLX4_STEERING_DMFS_A0_DISABLE:
1912                 return "disabled performance optimized steering";
1913
1914         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1915                 return "performance optimized steering not supported";
1916
1917         default:
1918                 return "Unrecognized mode";
1919         }
1920 }
1921
1922 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
1923
1924 static void choose_steering_mode(struct mlx4_dev *dev,
1925                                  struct mlx4_dev_cap *dev_cap)
1926 {
1927         if (mlx4_log_num_mgm_entry_size <= 0) {
1928                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1929                         if (dev->caps.dmfs_high_steer_mode ==
1930                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1931                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
1932                         else
1933                                 dev->caps.dmfs_high_steer_mode =
1934                                         MLX4_STEERING_DMFS_A0_STATIC;
1935                 }
1936         }
1937
1938         if (mlx4_log_num_mgm_entry_size <= 0 &&
1939             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1940             (!mlx4_is_mfunc(dev) ||
1941              (dev_cap->fs_max_num_qp_per_entry >=
1942              (dev->persist->num_vfs + 1))) &&
1943             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1944                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1945                 dev->oper_log_mgm_entry_size =
1946                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1947                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1948                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1949                 dev->caps.fs_log_max_ucast_qp_range_size =
1950                         dev_cap->fs_log_max_ucast_qp_range_size;
1951         } else {
1952                 if (dev->caps.dmfs_high_steer_mode !=
1953                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1954                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
1955                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1956                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1957                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1958                 else {
1959                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1960
1961                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1962                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1963                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1964                 }
1965                 dev->oper_log_mgm_entry_size =
1966                         mlx4_log_num_mgm_entry_size > 0 ?
1967                         mlx4_log_num_mgm_entry_size :
1968                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1969                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1970         }
1971         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1972                  mlx4_steering_mode_str(dev->caps.steering_mode),
1973                  dev->oper_log_mgm_entry_size,
1974                  mlx4_log_num_mgm_entry_size);
1975 }
1976
1977 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1978                                        struct mlx4_dev_cap *dev_cap)
1979 {
1980         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1981             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1982                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1983         else
1984                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1985
1986         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
1987                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1988 }
1989
1990 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1991 {
1992         int i;
1993         struct mlx4_port_cap port_cap;
1994
1995         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1996                 return -EINVAL;
1997
1998         for (i = 1; i <= dev->caps.num_ports; i++) {
1999                 if (mlx4_dev_port(dev, i, &port_cap)) {
2000                         mlx4_err(dev,
2001                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2002                 } else if ((dev->caps.dmfs_high_steer_mode !=
2003                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
2004                            (port_cap.dmfs_optimized_state ==
2005                             !!(dev->caps.dmfs_high_steer_mode ==
2006                             MLX4_STEERING_DMFS_A0_DISABLE))) {
2007                         mlx4_err(dev,
2008                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2009                                  dmfs_high_rate_steering_mode_str(
2010                                         dev->caps.dmfs_high_steer_mode),
2011                                  (port_cap.dmfs_optimized_state ?
2012                                         "enabled" : "disabled"));
2013                 }
2014         }
2015
2016         return 0;
2017 }
2018
2019 static int mlx4_init_fw(struct mlx4_dev *dev)
2020 {
2021         struct mlx4_mod_stat_cfg   mlx4_cfg;
2022         int err = 0;
2023
2024         if (!mlx4_is_slave(dev)) {
2025                 err = mlx4_QUERY_FW(dev);
2026                 if (err) {
2027                         if (err == -EACCES)
2028                                 mlx4_info(dev, "non-primary physical function, skipping\n");
2029                         else
2030                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2031                         return err;
2032                 }
2033
2034                 err = mlx4_load_fw(dev);
2035                 if (err) {
2036                         mlx4_err(dev, "Failed to start FW, aborting\n");
2037                         return err;
2038                 }
2039
2040                 mlx4_cfg.log_pg_sz_m = 1;
2041                 mlx4_cfg.log_pg_sz = 0;
2042                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2043                 if (err)
2044                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2045         }
2046
2047         return err;
2048 }
2049
2050 static int mlx4_init_hca(struct mlx4_dev *dev)
2051 {
2052         struct mlx4_priv          *priv = mlx4_priv(dev);
2053         struct mlx4_adapter        adapter;
2054         struct mlx4_dev_cap        dev_cap;
2055         struct mlx4_profile        profile;
2056         struct mlx4_init_hca_param init_hca;
2057         u64 icm_size;
2058         struct mlx4_config_dev_params params;
2059         int err;
2060
2061         if (!mlx4_is_slave(dev)) {
2062                 err = mlx4_dev_cap(dev, &dev_cap);
2063                 if (err) {
2064                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2065                         return err;
2066                 }
2067
2068                 choose_steering_mode(dev, &dev_cap);
2069                 choose_tunnel_offload_mode(dev, &dev_cap);
2070
2071                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2072                     mlx4_is_master(dev))
2073                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2074
2075                 err = mlx4_get_phys_port_id(dev);
2076                 if (err)
2077                         mlx4_err(dev, "Fail to get physical port id\n");
2078
2079                 if (mlx4_is_master(dev))
2080                         mlx4_parav_master_pf_caps(dev);
2081
2082                 if (mlx4_low_memory_profile()) {
2083                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2084                         profile = low_mem_profile;
2085                 } else {
2086                         profile = default_profile;
2087                 }
2088                 if (dev->caps.steering_mode ==
2089                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2090                         profile.num_mcg = MLX4_FS_NUM_MCG;
2091
2092                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2093                                              &init_hca);
2094                 if ((long long) icm_size < 0) {
2095                         err = icm_size;
2096                         return err;
2097                 }
2098
2099                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2100
2101                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2102                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2103                 init_hca.mw_enabled = 0;
2104                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2105                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2106                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2107
2108                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2109                 if (err)
2110                         return err;
2111
2112                 err = mlx4_INIT_HCA(dev, &init_hca);
2113                 if (err) {
2114                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2115                         goto err_free_icm;
2116                 }
2117
2118                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2119                         err = mlx4_query_func(dev, &dev_cap);
2120                         if (err < 0) {
2121                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2122                                 goto err_close;
2123                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2124                                 dev->caps.num_eqs = dev_cap.max_eqs;
2125                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2126                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2127                         }
2128                 }
2129
2130                 /*
2131                  * If TS is supported by FW
2132                  * read HCA frequency by QUERY_HCA command
2133                  */
2134                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2135                         memset(&init_hca, 0, sizeof(init_hca));
2136                         err = mlx4_QUERY_HCA(dev, &init_hca);
2137                         if (err) {
2138                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2139                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2140                         } else {
2141                                 dev->caps.hca_core_clock =
2142                                         init_hca.hca_core_clock;
2143                         }
2144
2145                         /* In case we got HCA frequency 0 - disable timestamping
2146                          * to avoid dividing by zero
2147                          */
2148                         if (!dev->caps.hca_core_clock) {
2149                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2150                                 mlx4_err(dev,
2151                                          "HCA frequency is 0 - timestamping is not supported\n");
2152                         } else if (map_internal_clock(dev)) {
2153                                 /*
2154                                  * Map internal clock,
2155                                  * in case of failure disable timestamping
2156                                  */
2157                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2158                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2159                         }
2160                 }
2161
2162                 if (dev->caps.dmfs_high_steer_mode !=
2163                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2164                         if (mlx4_validate_optimized_steering(dev))
2165                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2166
2167                         if (dev->caps.dmfs_high_steer_mode ==
2168                             MLX4_STEERING_DMFS_A0_DISABLE) {
2169                                 dev->caps.dmfs_high_rate_qpn_base =
2170                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2171                                 dev->caps.dmfs_high_rate_qpn_range =
2172                                         MLX4_A0_STEERING_TABLE_SIZE;
2173                         }
2174
2175                         mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2176                                  dmfs_high_rate_steering_mode_str(
2177                                         dev->caps.dmfs_high_steer_mode));
2178                 }
2179         } else {
2180                 err = mlx4_init_slave(dev);
2181                 if (err) {
2182                         if (err != -EPROBE_DEFER)
2183                                 mlx4_err(dev, "Failed to initialize slave\n");
2184                         return err;
2185                 }
2186
2187                 err = mlx4_slave_cap(dev);
2188                 if (err) {
2189                         mlx4_err(dev, "Failed to obtain slave caps\n");
2190                         goto err_close;
2191                 }
2192         }
2193
2194         if (map_bf_area(dev))
2195                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2196
2197         /*Only the master set the ports, all the rest got it from it.*/
2198         if (!mlx4_is_slave(dev))
2199                 mlx4_set_port_mask(dev);
2200
2201         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2202         if (err) {
2203                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2204                 goto unmap_bf;
2205         }
2206
2207         /* Query CONFIG_DEV parameters */
2208         err = mlx4_config_dev_retrieval(dev, &params);
2209         if (err && err != -ENOTSUPP) {
2210                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2211         } else if (!err) {
2212                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2213                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2214         }
2215         priv->eq_table.inta_pin = adapter.inta_pin;
2216         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2217
2218         return 0;
2219
2220 unmap_bf:
2221         unmap_internal_clock(dev);
2222         unmap_bf_area(dev);
2223
2224         if (mlx4_is_slave(dev)) {
2225                 kfree(dev->caps.qp0_qkey);
2226                 kfree(dev->caps.qp0_tunnel);
2227                 kfree(dev->caps.qp0_proxy);
2228                 kfree(dev->caps.qp1_tunnel);
2229                 kfree(dev->caps.qp1_proxy);
2230         }
2231
2232 err_close:
2233         if (mlx4_is_slave(dev))
2234                 mlx4_slave_exit(dev);
2235         else
2236                 mlx4_CLOSE_HCA(dev, 0);
2237
2238 err_free_icm:
2239         if (!mlx4_is_slave(dev))
2240                 mlx4_free_icms(dev);
2241
2242         return err;
2243 }
2244
2245 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2246 {
2247         struct mlx4_priv *priv = mlx4_priv(dev);
2248         int nent_pow2;
2249
2250         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2251                 return -ENOENT;
2252
2253         if (!dev->caps.max_counters)
2254                 return -ENOSPC;
2255
2256         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2257         /* reserve last counter index for sink counter */
2258         return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2259                                 nent_pow2 - 1, 0,
2260                                 nent_pow2 - dev->caps.max_counters + 1);
2261 }
2262
2263 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2264 {
2265         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2266                 return;
2267
2268         if (!dev->caps.max_counters)
2269                 return;
2270
2271         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2272 }
2273
2274 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2275 {
2276         struct mlx4_priv *priv = mlx4_priv(dev);
2277         int port;
2278
2279         for (port = 0; port < dev->caps.num_ports; port++)
2280                 if (priv->def_counter[port] != -1)
2281                         mlx4_counter_free(dev,  priv->def_counter[port]);
2282 }
2283
2284 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2285 {
2286         struct mlx4_priv *priv = mlx4_priv(dev);
2287         int port, err = 0;
2288         u32 idx;
2289
2290         for (port = 0; port < dev->caps.num_ports; port++)
2291                 priv->def_counter[port] = -1;
2292
2293         for (port = 0; port < dev->caps.num_ports; port++) {
2294                 err = mlx4_counter_alloc(dev, &idx);
2295
2296                 if (!err || err == -ENOSPC) {
2297                         priv->def_counter[port] = idx;
2298                         err = 0;
2299                 } else if (err == -ENOENT) {
2300                         err = 0;
2301                         continue;
2302                 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2303                         priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2304                         mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2305                                   MLX4_SINK_COUNTER_INDEX(dev));
2306                         err = 0;
2307                 } else {
2308                         mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2309                                  __func__, port + 1, err);
2310                         mlx4_cleanup_default_counters(dev);
2311                         return err;
2312                 }
2313
2314                 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2315                          __func__, priv->def_counter[port], port + 1);
2316         }
2317
2318         return err;
2319 }
2320
2321 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2322 {
2323         struct mlx4_priv *priv = mlx4_priv(dev);
2324
2325         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2326                 return -ENOENT;
2327
2328         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2329         if (*idx == -1) {
2330                 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2331                 return -ENOSPC;
2332         }
2333
2334         return 0;
2335 }
2336
2337 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2338 {
2339         u64 out_param;
2340         int err;
2341
2342         if (mlx4_is_mfunc(dev)) {
2343                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2344                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2345                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2346                 if (!err)
2347                         *idx = get_param_l(&out_param);
2348                 if (WARN_ON(err == -ENOSPC))
2349                         err = -EINVAL;
2350                 return err;
2351         }
2352         return __mlx4_counter_alloc(dev, idx);
2353 }
2354 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2355
2356 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2357                                 u8 counter_index)
2358 {
2359         struct mlx4_cmd_mailbox *if_stat_mailbox;
2360         int err;
2361         u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2362
2363         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2364         if (IS_ERR(if_stat_mailbox))
2365                 return PTR_ERR(if_stat_mailbox);
2366
2367         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2368                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2369                            MLX4_CMD_NATIVE);
2370
2371         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2372         return err;
2373 }
2374
2375 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2376 {
2377         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2378                 return;
2379
2380         if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2381                 return;
2382
2383         __mlx4_clear_if_stat(dev, idx);
2384
2385         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2386         return;
2387 }
2388
2389 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2390 {
2391         u64 in_param = 0;
2392
2393         if (mlx4_is_mfunc(dev)) {
2394                 set_param_l(&in_param, idx);
2395                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2396                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2397                          MLX4_CMD_WRAPPED);
2398                 return;
2399         }
2400         __mlx4_counter_free(dev, idx);
2401 }
2402 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2403
2404 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2405 {
2406         struct mlx4_priv *priv = mlx4_priv(dev);
2407
2408         return priv->def_counter[port - 1];
2409 }
2410 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2411
2412 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2413 {
2414         struct mlx4_priv *priv = mlx4_priv(dev);
2415
2416         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2417 }
2418 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2419
2420 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2421 {
2422         struct mlx4_priv *priv = mlx4_priv(dev);
2423
2424         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2425 }
2426 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2427
2428 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2429 {
2430         struct mlx4_priv *priv = mlx4_priv(dev);
2431         __be64 guid;
2432
2433         /* hw GUID */
2434         if (entry == 0)
2435                 return;
2436
2437         get_random_bytes((char *)&guid, sizeof(guid));
2438         guid &= ~(cpu_to_be64(1ULL << 56));
2439         guid |= cpu_to_be64(1ULL << 57);
2440         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2441 }
2442
2443 static int mlx4_setup_hca(struct mlx4_dev *dev)
2444 {
2445         struct mlx4_priv *priv = mlx4_priv(dev);
2446         int err;
2447         int port;
2448         __be32 ib_port_default_caps;
2449
2450         err = mlx4_init_uar_table(dev);
2451         if (err) {
2452                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2453                  return err;
2454         }
2455
2456         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2457         if (err) {
2458                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2459                 goto err_uar_table_free;
2460         }
2461
2462         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2463         if (!priv->kar) {
2464                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2465                 err = -ENOMEM;
2466                 goto err_uar_free;
2467         }
2468
2469         err = mlx4_init_pd_table(dev);
2470         if (err) {
2471                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2472                 goto err_kar_unmap;
2473         }
2474
2475         err = mlx4_init_xrcd_table(dev);
2476         if (err) {
2477                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2478                 goto err_pd_table_free;
2479         }
2480
2481         err = mlx4_init_mr_table(dev);
2482         if (err) {
2483                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2484                 goto err_xrcd_table_free;
2485         }
2486
2487         if (!mlx4_is_slave(dev)) {
2488                 err = mlx4_init_mcg_table(dev);
2489                 if (err) {
2490                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2491                         goto err_mr_table_free;
2492                 }
2493                 err = mlx4_config_mad_demux(dev);
2494                 if (err) {
2495                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2496                         goto err_mcg_table_free;
2497                 }
2498         }
2499
2500         err = mlx4_init_eq_table(dev);
2501         if (err) {
2502                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2503                 goto err_mcg_table_free;
2504         }
2505
2506         err = mlx4_cmd_use_events(dev);
2507         if (err) {
2508                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2509                 goto err_eq_table_free;
2510         }
2511
2512         err = mlx4_NOP(dev);
2513         if (err) {
2514                 if (dev->flags & MLX4_FLAG_MSI_X) {
2515                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2516                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2517                         mlx4_warn(dev, "Trying again without MSI-X\n");
2518                 } else {
2519                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2520                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2521                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2522                 }
2523
2524                 goto err_cmd_poll;
2525         }
2526
2527         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2528
2529         err = mlx4_init_cq_table(dev);
2530         if (err) {
2531                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2532                 goto err_cmd_poll;
2533         }
2534
2535         err = mlx4_init_srq_table(dev);
2536         if (err) {
2537                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2538                 goto err_cq_table_free;
2539         }
2540
2541         err = mlx4_init_qp_table(dev);
2542         if (err) {
2543                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2544                 goto err_srq_table_free;
2545         }
2546
2547         if (!mlx4_is_slave(dev)) {
2548                 err = mlx4_init_counters_table(dev);
2549                 if (err && err != -ENOENT) {
2550                         mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2551                         goto err_qp_table_free;
2552                 }
2553         }
2554
2555         err = mlx4_allocate_default_counters(dev);
2556         if (err) {
2557                 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2558                 goto err_counters_table_free;
2559         }
2560
2561         if (!mlx4_is_slave(dev)) {
2562                 for (port = 1; port <= dev->caps.num_ports; port++) {
2563                         ib_port_default_caps = 0;
2564                         err = mlx4_get_port_ib_caps(dev, port,
2565                                                     &ib_port_default_caps);
2566                         if (err)
2567                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2568                                           port, err);
2569                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2570
2571                         /* initialize per-slave default ib port capabilities */
2572                         if (mlx4_is_master(dev)) {
2573                                 int i;
2574                                 for (i = 0; i < dev->num_slaves; i++) {
2575                                         if (i == mlx4_master_func_num(dev))
2576                                                 continue;
2577                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2578                                                 ib_port_default_caps;
2579                                 }
2580                         }
2581
2582                         if (mlx4_is_mfunc(dev))
2583                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2584                         else
2585                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2586
2587                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2588                                             dev->caps.pkey_table_len[port] : -1);
2589                         if (err) {
2590                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2591                                          port);
2592                                 goto err_default_countes_free;
2593                         }
2594                 }
2595         }
2596
2597         return 0;
2598
2599 err_default_countes_free:
2600         mlx4_cleanup_default_counters(dev);
2601
2602 err_counters_table_free:
2603         if (!mlx4_is_slave(dev))
2604                 mlx4_cleanup_counters_table(dev);
2605
2606 err_qp_table_free:
2607         mlx4_cleanup_qp_table(dev);
2608
2609 err_srq_table_free:
2610         mlx4_cleanup_srq_table(dev);
2611
2612 err_cq_table_free:
2613         mlx4_cleanup_cq_table(dev);
2614
2615 err_cmd_poll:
2616         mlx4_cmd_use_polling(dev);
2617
2618 err_eq_table_free:
2619         mlx4_cleanup_eq_table(dev);
2620
2621 err_mcg_table_free:
2622         if (!mlx4_is_slave(dev))
2623                 mlx4_cleanup_mcg_table(dev);
2624
2625 err_mr_table_free:
2626         mlx4_cleanup_mr_table(dev);
2627
2628 err_xrcd_table_free:
2629         mlx4_cleanup_xrcd_table(dev);
2630
2631 err_pd_table_free:
2632         mlx4_cleanup_pd_table(dev);
2633
2634 err_kar_unmap:
2635         iounmap(priv->kar);
2636
2637 err_uar_free:
2638         mlx4_uar_free(dev, &priv->driver_uar);
2639
2640 err_uar_table_free:
2641         mlx4_cleanup_uar_table(dev);
2642         return err;
2643 }
2644
2645 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2646 {
2647         int requested_cpu = 0;
2648         struct mlx4_priv *priv = mlx4_priv(dev);
2649         struct mlx4_eq *eq;
2650         int off = 0;
2651         int i;
2652
2653         if (eqn > dev->caps.num_comp_vectors)
2654                 return -EINVAL;
2655
2656         for (i = 1; i < port; i++)
2657                 off += mlx4_get_eqs_per_port(dev, i);
2658
2659         requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2660
2661         /* Meaning EQs are shared, and this call comes from the second port */
2662         if (requested_cpu < 0)
2663                 return 0;
2664
2665         eq = &priv->eq_table.eq[eqn];
2666
2667         if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2668                 return -ENOMEM;
2669
2670         cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2671
2672         return 0;
2673 }
2674
2675 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2676 {
2677         struct mlx4_priv *priv = mlx4_priv(dev);
2678         struct msix_entry *entries;
2679         int i;
2680         int port = 0;
2681
2682         if (msi_x) {
2683                 int nreq = dev->caps.num_ports * num_online_cpus() + 1;
2684
2685                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2686                              nreq);
2687                 if (nreq > MAX_MSIX)
2688                         nreq = MAX_MSIX;
2689
2690                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2691                 if (!entries)
2692                         goto no_msi;
2693
2694                 for (i = 0; i < nreq; ++i)
2695                         entries[i].entry = i;
2696
2697                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2698                                              nreq);
2699
2700                 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2701                         kfree(entries);
2702                         goto no_msi;
2703                 }
2704                 /* 1 is reserved for events (asyncrounous EQ) */
2705                 dev->caps.num_comp_vectors = nreq - 1;
2706
2707                 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2708                 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2709                             dev->caps.num_ports);
2710
2711                 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2712                         if (i == MLX4_EQ_ASYNC)
2713                                 continue;
2714
2715                         priv->eq_table.eq[i].irq =
2716                                 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2717
2718                         if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2719                                 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2720                                             dev->caps.num_ports);
2721                                 /* We don't set affinity hint when there
2722                                  * aren't enough EQs
2723                                  */
2724                         } else {
2725                                 set_bit(port,
2726                                         priv->eq_table.eq[i].actv_ports.ports);
2727                                 if (mlx4_init_affinity_hint(dev, port + 1, i))
2728                                         mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2729                                                   i);
2730                         }
2731                         /* We divide the Eqs evenly between the two ports.
2732                          * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2733                          * refers to the number of Eqs per port
2734                          * (i.e eqs_per_port). Theoretically, we would like to
2735                          * write something like (i + 1) % eqs_per_port == 0.
2736                          * However, since there's an asynchronous Eq, we have
2737                          * to skip over it by comparing this condition to
2738                          * !!((i + 1) > MLX4_EQ_ASYNC).
2739                          */
2740                         if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2741                             ((i + 1) %
2742                              (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2743                             !!((i + 1) > MLX4_EQ_ASYNC))
2744                                 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2745                                  * everything is shared anyway.
2746                                  */
2747                                 port++;
2748                 }
2749
2750                 dev->flags |= MLX4_FLAG_MSI_X;
2751
2752                 kfree(entries);
2753                 return;
2754         }
2755
2756 no_msi:
2757         dev->caps.num_comp_vectors = 1;
2758
2759         BUG_ON(MLX4_EQ_ASYNC >= 2);
2760         for (i = 0; i < 2; ++i) {
2761                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2762                 if (i != MLX4_EQ_ASYNC) {
2763                         bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2764                                     dev->caps.num_ports);
2765                 }
2766         }
2767 }
2768
2769 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2770 {
2771         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2772         int err = 0;
2773
2774         info->dev = dev;
2775         info->port = port;
2776         if (!mlx4_is_slave(dev)) {
2777                 mlx4_init_mac_table(dev, &info->mac_table);
2778                 mlx4_init_vlan_table(dev, &info->vlan_table);
2779                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2780                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2781         }
2782
2783         sprintf(info->dev_name, "mlx4_port%d", port);
2784         info->port_attr.attr.name = info->dev_name;
2785         if (mlx4_is_mfunc(dev))
2786                 info->port_attr.attr.mode = S_IRUGO;
2787         else {
2788                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2789                 info->port_attr.store     = set_port_type;
2790         }
2791         info->port_attr.show      = show_port_type;
2792         sysfs_attr_init(&info->port_attr.attr);
2793
2794         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2795         if (err) {
2796                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2797                 info->port = -1;
2798         }
2799
2800         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2801         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2802         if (mlx4_is_mfunc(dev))
2803                 info->port_mtu_attr.attr.mode = S_IRUGO;
2804         else {
2805                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2806                 info->port_mtu_attr.store     = set_port_ib_mtu;
2807         }
2808         info->port_mtu_attr.show      = show_port_ib_mtu;
2809         sysfs_attr_init(&info->port_mtu_attr.attr);
2810
2811         err = device_create_file(&dev->persist->pdev->dev,
2812                                  &info->port_mtu_attr);
2813         if (err) {
2814                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2815                 device_remove_file(&info->dev->persist->pdev->dev,
2816                                    &info->port_attr);
2817                 info->port = -1;
2818         }
2819
2820         return err;
2821 }
2822
2823 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2824 {
2825         if (info->port < 0)
2826                 return;
2827
2828         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2829         device_remove_file(&info->dev->persist->pdev->dev,
2830                            &info->port_mtu_attr);
2831 #ifdef CONFIG_RFS_ACCEL
2832         free_irq_cpu_rmap(info->rmap);
2833         info->rmap = NULL;
2834 #endif
2835 }
2836
2837 static int mlx4_init_steering(struct mlx4_dev *dev)
2838 {
2839         struct mlx4_priv *priv = mlx4_priv(dev);
2840         int num_entries = dev->caps.num_ports;
2841         int i, j;
2842
2843         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2844         if (!priv->steer)
2845                 return -ENOMEM;
2846
2847         for (i = 0; i < num_entries; i++)
2848                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2849                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2850                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2851                 }
2852         return 0;
2853 }
2854
2855 static void mlx4_clear_steering(struct mlx4_dev *dev)
2856 {
2857         struct mlx4_priv *priv = mlx4_priv(dev);
2858         struct mlx4_steer_index *entry, *tmp_entry;
2859         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2860         int num_entries = dev->caps.num_ports;
2861         int i, j;
2862
2863         for (i = 0; i < num_entries; i++) {
2864                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2865                         list_for_each_entry_safe(pqp, tmp_pqp,
2866                                                  &priv->steer[i].promisc_qps[j],
2867                                                  list) {
2868                                 list_del(&pqp->list);
2869                                 kfree(pqp);
2870                         }
2871                         list_for_each_entry_safe(entry, tmp_entry,
2872                                                  &priv->steer[i].steer_entries[j],
2873                                                  list) {
2874                                 list_del(&entry->list);
2875                                 list_for_each_entry_safe(pqp, tmp_pqp,
2876                                                          &entry->duplicates,
2877                                                          list) {
2878                                         list_del(&pqp->list);
2879                                         kfree(pqp);
2880                                 }
2881                                 kfree(entry);
2882                         }
2883                 }
2884         }
2885         kfree(priv->steer);
2886 }
2887
2888 static int extended_func_num(struct pci_dev *pdev)
2889 {
2890         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2891 }
2892
2893 #define MLX4_OWNER_BASE 0x8069c
2894 #define MLX4_OWNER_SIZE 4
2895
2896 static int mlx4_get_ownership(struct mlx4_dev *dev)
2897 {
2898         void __iomem *owner;
2899         u32 ret;
2900
2901         if (pci_channel_offline(dev->persist->pdev))
2902                 return -EIO;
2903
2904         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2905                         MLX4_OWNER_BASE,
2906                         MLX4_OWNER_SIZE);
2907         if (!owner) {
2908                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2909                 return -ENOMEM;
2910         }
2911
2912         ret = readl(owner);
2913         iounmap(owner);
2914         return (int) !!ret;
2915 }
2916
2917 static void mlx4_free_ownership(struct mlx4_dev *dev)
2918 {
2919         void __iomem *owner;
2920
2921         if (pci_channel_offline(dev->persist->pdev))
2922                 return;
2923
2924         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2925                         MLX4_OWNER_BASE,
2926                         MLX4_OWNER_SIZE);
2927         if (!owner) {
2928                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2929                 return;
2930         }
2931         writel(0, owner);
2932         msleep(1000);
2933         iounmap(owner);
2934 }
2935
2936 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2937                                   !!((flags) & MLX4_FLAG_MASTER))
2938
2939 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
2940                              u8 total_vfs, int existing_vfs, int reset_flow)
2941 {
2942         u64 dev_flags = dev->flags;
2943         int err = 0;
2944         int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
2945                                         MLX4_MAX_NUM_VF);
2946
2947         if (reset_flow) {
2948                 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
2949                                        GFP_KERNEL);
2950                 if (!dev->dev_vfs)
2951                         goto free_mem;
2952                 return dev_flags;
2953         }
2954
2955         atomic_inc(&pf_loading);
2956         if (dev->flags &  MLX4_FLAG_SRIOV) {
2957                 if (existing_vfs != total_vfs) {
2958                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2959                                  existing_vfs, total_vfs);
2960                         total_vfs = existing_vfs;
2961                 }
2962         }
2963
2964         dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
2965         if (NULL == dev->dev_vfs) {
2966                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2967                 goto disable_sriov;
2968         }
2969
2970         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
2971                 if (total_vfs > fw_enabled_sriov_vfs) {
2972                         mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
2973                                  total_vfs, fw_enabled_sriov_vfs);
2974                         err = -ENOMEM;
2975                         goto disable_sriov;
2976                 }
2977                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2978                 err = pci_enable_sriov(pdev, total_vfs);
2979         }
2980         if (err) {
2981                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2982                          err);
2983                 goto disable_sriov;
2984         } else {
2985                 mlx4_warn(dev, "Running in master mode\n");
2986                 dev_flags |= MLX4_FLAG_SRIOV |
2987                         MLX4_FLAG_MASTER;
2988                 dev_flags &= ~MLX4_FLAG_SLAVE;
2989                 dev->persist->num_vfs = total_vfs;
2990         }
2991         return dev_flags;
2992
2993 disable_sriov:
2994         atomic_dec(&pf_loading);
2995 free_mem:
2996         dev->persist->num_vfs = 0;
2997         kfree(dev->dev_vfs);
2998         dev->dev_vfs = NULL;
2999         return dev_flags & ~MLX4_FLAG_MASTER;
3000 }
3001
3002 enum {
3003         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3004 };
3005
3006 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3007                               int *nvfs)
3008 {
3009         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3010         /* Checking for 64 VFs as a limitation of CX2 */
3011         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3012             requested_vfs >= 64) {
3013                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3014                          requested_vfs);
3015                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3016         }
3017         return 0;
3018 }
3019
3020 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
3021                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
3022                          int reset_flow)
3023 {
3024         struct mlx4_dev *dev;
3025         unsigned sum = 0;
3026         int err;
3027         int port;
3028         int i;
3029         struct mlx4_dev_cap *dev_cap = NULL;
3030         int existing_vfs = 0;
3031
3032         dev = &priv->dev;
3033
3034         INIT_LIST_HEAD(&priv->ctx_list);
3035         spin_lock_init(&priv->ctx_lock);
3036
3037         mutex_init(&priv->port_mutex);
3038         mutex_init(&priv->bond_mutex);
3039
3040         INIT_LIST_HEAD(&priv->pgdir_list);
3041         mutex_init(&priv->pgdir_mutex);
3042
3043         INIT_LIST_HEAD(&priv->bf_list);
3044         mutex_init(&priv->bf_mutex);
3045
3046         dev->rev_id = pdev->revision;
3047         dev->numa_node = dev_to_node(&pdev->dev);
3048
3049         /* Detect if this device is a virtual function */
3050         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3051                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3052                 dev->flags |= MLX4_FLAG_SLAVE;
3053         } else {
3054                 /* We reset the device and enable SRIOV only for physical
3055                  * devices.  Try to claim ownership on the device;
3056                  * if already taken, skip -- do not allow multiple PFs */
3057                 err = mlx4_get_ownership(dev);
3058                 if (err) {
3059                         if (err < 0)
3060                                 return err;
3061                         else {
3062                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3063                                 return -EINVAL;
3064                         }
3065                 }
3066
3067                 atomic_set(&priv->opreq_count, 0);
3068                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3069
3070                 /*
3071                  * Now reset the HCA before we touch the PCI capabilities or
3072                  * attempt a firmware command, since a boot ROM may have left
3073                  * the HCA in an undefined state.
3074                  */
3075                 err = mlx4_reset(dev);
3076                 if (err) {
3077                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
3078                         goto err_sriov;
3079                 }
3080
3081                 if (total_vfs) {
3082                         dev->flags = MLX4_FLAG_MASTER;
3083                         existing_vfs = pci_num_vf(pdev);
3084                         if (existing_vfs)
3085                                 dev->flags |= MLX4_FLAG_SRIOV;
3086                         dev->persist->num_vfs = total_vfs;
3087                 }
3088         }
3089
3090         /* on load remove any previous indication of internal error,
3091          * device is up.
3092          */
3093         dev->persist->state = MLX4_DEVICE_STATE_UP;
3094
3095 slave_start:
3096         err = mlx4_cmd_init(dev);
3097         if (err) {
3098                 mlx4_err(dev, "Failed to init command interface, aborting\n");
3099                 goto err_sriov;
3100         }
3101
3102         /* In slave functions, the communication channel must be initialized
3103          * before posting commands. Also, init num_slaves before calling
3104          * mlx4_init_hca */
3105         if (mlx4_is_mfunc(dev)) {
3106                 if (mlx4_is_master(dev)) {
3107                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3108
3109                 } else {
3110                         dev->num_slaves = 0;
3111                         err = mlx4_multi_func_init(dev);
3112                         if (err) {
3113                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3114                                 goto err_cmd;
3115                         }
3116                 }
3117         }
3118
3119         err = mlx4_init_fw(dev);
3120         if (err) {
3121                 mlx4_err(dev, "Failed to init fw, aborting.\n");
3122                 goto err_mfunc;
3123         }
3124
3125         if (mlx4_is_master(dev)) {
3126                 /* when we hit the goto slave_start below, dev_cap already initialized */
3127                 if (!dev_cap) {
3128                         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3129
3130                         if (!dev_cap) {
3131                                 err = -ENOMEM;
3132                                 goto err_fw;
3133                         }
3134
3135                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3136                         if (err) {
3137                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3138                                 goto err_fw;
3139                         }
3140
3141                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3142                                 goto err_fw;
3143
3144                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3145                                 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3146                                                                   total_vfs,
3147                                                                   existing_vfs,
3148                                                                   reset_flow);
3149
3150                                 mlx4_close_fw(dev);
3151                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3152                                 dev->flags = dev_flags;
3153                                 if (!SRIOV_VALID_STATE(dev->flags)) {
3154                                         mlx4_err(dev, "Invalid SRIOV state\n");
3155                                         goto err_sriov;
3156                                 }
3157                                 err = mlx4_reset(dev);
3158                                 if (err) {
3159                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3160                                         goto err_sriov;
3161                                 }
3162                                 goto slave_start;
3163                         }
3164                 } else {
3165                         /* Legacy mode FW requires SRIOV to be enabled before
3166                          * doing QUERY_DEV_CAP, since max_eq's value is different if
3167                          * SRIOV is enabled.
3168                          */
3169                         memset(dev_cap, 0, sizeof(*dev_cap));
3170                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3171                         if (err) {
3172                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3173                                 goto err_fw;
3174                         }
3175
3176                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3177                                 goto err_fw;
3178                 }
3179         }
3180
3181         err = mlx4_init_hca(dev);
3182         if (err) {
3183                 if (err == -EACCES) {
3184                         /* Not primary Physical function
3185                          * Running in slave mode */
3186                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3187                         /* We're not a PF */
3188                         if (dev->flags & MLX4_FLAG_SRIOV) {
3189                                 if (!existing_vfs)
3190                                         pci_disable_sriov(pdev);
3191                                 if (mlx4_is_master(dev) && !reset_flow)
3192                                         atomic_dec(&pf_loading);
3193                                 dev->flags &= ~MLX4_FLAG_SRIOV;
3194                         }
3195                         if (!mlx4_is_slave(dev))
3196                                 mlx4_free_ownership(dev);
3197                         dev->flags |= MLX4_FLAG_SLAVE;
3198                         dev->flags &= ~MLX4_FLAG_MASTER;
3199                         goto slave_start;
3200                 } else
3201                         goto err_fw;
3202         }
3203
3204         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3205                 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3206                                                   existing_vfs, reset_flow);
3207
3208                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3209                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3210                         dev->flags = dev_flags;
3211                         err = mlx4_cmd_init(dev);
3212                         if (err) {
3213                                 /* Only VHCR is cleaned up, so could still
3214                                  * send FW commands
3215                                  */
3216                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3217                                 goto err_close;
3218                         }
3219                 } else {
3220                         dev->flags = dev_flags;
3221                 }
3222
3223                 if (!SRIOV_VALID_STATE(dev->flags)) {
3224                         mlx4_err(dev, "Invalid SRIOV state\n");
3225                         err = -EINVAL;
3226                         goto err_close;
3227                 }
3228         }
3229
3230         /* check if the device is functioning at its maximum possible speed.
3231          * No return code for this call, just warn the user in case of PCI
3232          * express device capabilities are under-satisfied by the bus.
3233          */
3234         if (!mlx4_is_slave(dev))
3235                 mlx4_check_pcie_caps(dev);
3236
3237         /* In master functions, the communication channel must be initialized
3238          * after obtaining its address from fw */
3239         if (mlx4_is_master(dev)) {
3240                 if (dev->caps.num_ports < 2 &&
3241                     num_vfs_argc > 1) {
3242                         err = -EINVAL;
3243                         mlx4_err(dev,
3244                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3245                                  dev->caps.num_ports);
3246                         goto err_close;
3247                 }
3248                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3249
3250                 for (i = 0;
3251                      i < sizeof(dev->persist->nvfs)/
3252                      sizeof(dev->persist->nvfs[0]); i++) {
3253                         unsigned j;
3254
3255                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3256                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3257                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3258                                         dev->caps.num_ports;
3259                         }
3260                 }
3261
3262                 /* In master functions, the communication channel
3263                  * must be initialized after obtaining its address from fw
3264                  */
3265                 err = mlx4_multi_func_init(dev);
3266                 if (err) {
3267                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3268                         goto err_close;
3269                 }
3270         }
3271
3272         err = mlx4_alloc_eq_table(dev);
3273         if (err)
3274                 goto err_master_mfunc;
3275
3276         bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3277         mutex_init(&priv->msix_ctl.pool_lock);
3278
3279         mlx4_enable_msi_x(dev);
3280         if ((mlx4_is_mfunc(dev)) &&
3281             !(dev->flags & MLX4_FLAG_MSI_X)) {
3282                 err = -ENOSYS;
3283                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3284                 goto err_free_eq;
3285         }
3286
3287         if (!mlx4_is_slave(dev)) {
3288                 err = mlx4_init_steering(dev);
3289                 if (err)
3290                         goto err_disable_msix;
3291         }
3292
3293         err = mlx4_setup_hca(dev);
3294         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3295             !mlx4_is_mfunc(dev)) {
3296                 dev->flags &= ~MLX4_FLAG_MSI_X;
3297                 dev->caps.num_comp_vectors = 1;
3298                 pci_disable_msix(pdev);
3299                 err = mlx4_setup_hca(dev);
3300         }
3301
3302         if (err)
3303                 goto err_steer;
3304
3305         mlx4_init_quotas(dev);
3306         /* When PF resources are ready arm its comm channel to enable
3307          * getting commands
3308          */
3309         if (mlx4_is_master(dev)) {
3310                 err = mlx4_ARM_COMM_CHANNEL(dev);
3311                 if (err) {
3312                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3313                                  err);
3314                         goto err_steer;
3315                 }
3316         }
3317
3318         for (port = 1; port <= dev->caps.num_ports; port++) {
3319                 err = mlx4_init_port_info(dev, port);
3320                 if (err)
3321                         goto err_port;
3322         }
3323
3324         priv->v2p.port1 = 1;
3325         priv->v2p.port2 = 2;
3326
3327         err = mlx4_register_device(dev);
3328         if (err)
3329                 goto err_port;
3330
3331         mlx4_request_modules(dev);
3332
3333         mlx4_sense_init(dev);
3334         mlx4_start_sense(dev);
3335
3336         priv->removed = 0;
3337
3338         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3339                 atomic_dec(&pf_loading);
3340
3341         kfree(dev_cap);
3342         return 0;
3343
3344 err_port:
3345         for (--port; port >= 1; --port)
3346                 mlx4_cleanup_port_info(&priv->port[port]);
3347
3348         mlx4_cleanup_default_counters(dev);
3349         if (!mlx4_is_slave(dev))
3350                 mlx4_cleanup_counters_table(dev);
3351         mlx4_cleanup_qp_table(dev);
3352         mlx4_cleanup_srq_table(dev);
3353         mlx4_cleanup_cq_table(dev);
3354         mlx4_cmd_use_polling(dev);
3355         mlx4_cleanup_eq_table(dev);
3356         mlx4_cleanup_mcg_table(dev);
3357         mlx4_cleanup_mr_table(dev);
3358         mlx4_cleanup_xrcd_table(dev);
3359         mlx4_cleanup_pd_table(dev);
3360         mlx4_cleanup_uar_table(dev);
3361
3362 err_steer:
3363         if (!mlx4_is_slave(dev))
3364                 mlx4_clear_steering(dev);
3365
3366 err_disable_msix:
3367         if (dev->flags & MLX4_FLAG_MSI_X)
3368                 pci_disable_msix(pdev);
3369
3370 err_free_eq:
3371         mlx4_free_eq_table(dev);
3372
3373 err_master_mfunc:
3374         if (mlx4_is_master(dev)) {
3375                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3376                 mlx4_multi_func_cleanup(dev);
3377         }
3378
3379         if (mlx4_is_slave(dev)) {
3380                 kfree(dev->caps.qp0_qkey);
3381                 kfree(dev->caps.qp0_tunnel);
3382                 kfree(dev->caps.qp0_proxy);
3383                 kfree(dev->caps.qp1_tunnel);
3384                 kfree(dev->caps.qp1_proxy);
3385         }
3386
3387 err_close:
3388         mlx4_close_hca(dev);
3389
3390 err_fw:
3391         mlx4_close_fw(dev);
3392
3393 err_mfunc:
3394         if (mlx4_is_slave(dev))
3395                 mlx4_multi_func_cleanup(dev);
3396
3397 err_cmd:
3398         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3399
3400 err_sriov:
3401         if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3402                 pci_disable_sriov(pdev);
3403                 dev->flags &= ~MLX4_FLAG_SRIOV;
3404         }
3405
3406         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3407                 atomic_dec(&pf_loading);
3408
3409         kfree(priv->dev.dev_vfs);
3410
3411         if (!mlx4_is_slave(dev))
3412                 mlx4_free_ownership(dev);
3413
3414         kfree(dev_cap);
3415         return err;
3416 }
3417
3418 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3419                            struct mlx4_priv *priv)
3420 {
3421         int err;
3422         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3423         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3424         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3425                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3426         unsigned total_vfs = 0;
3427         unsigned int i;
3428
3429         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3430
3431         err = pci_enable_device(pdev);
3432         if (err) {
3433                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3434                 return err;
3435         }
3436
3437         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3438          * per port, we must limit the number of VFs to 63 (since their are
3439          * 128 MACs)
3440          */
3441         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3442              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3443                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3444                 if (nvfs[i] < 0) {
3445                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3446                         err = -EINVAL;
3447                         goto err_disable_pdev;
3448                 }
3449         }
3450         for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3451              i++) {
3452                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3453                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3454                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3455                         err = -EINVAL;
3456                         goto err_disable_pdev;
3457                 }
3458         }
3459         if (total_vfs > MLX4_MAX_NUM_VF) {
3460                 dev_err(&pdev->dev,
3461                         "Requested more VF's (%d) than allowed by hw (%d)\n",
3462                         total_vfs, MLX4_MAX_NUM_VF);
3463                 err = -EINVAL;
3464                 goto err_disable_pdev;
3465         }
3466
3467         for (i = 0; i < MLX4_MAX_PORTS; i++) {
3468                 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
3469                         dev_err(&pdev->dev,
3470                                 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
3471                                 nvfs[i] + nvfs[2], i + 1,
3472                                 MLX4_MAX_NUM_VF_P_PORT);
3473                         err = -EINVAL;
3474                         goto err_disable_pdev;
3475                 }
3476         }
3477
3478         /* Check for BARs. */
3479         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3480             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3481                 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3482                         pci_dev_data, pci_resource_flags(pdev, 0));
3483                 err = -ENODEV;
3484                 goto err_disable_pdev;
3485         }
3486         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3487                 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3488                 err = -ENODEV;
3489                 goto err_disable_pdev;
3490         }
3491
3492         err = pci_request_regions(pdev, DRV_NAME);
3493         if (err) {
3494                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3495                 goto err_disable_pdev;
3496         }
3497
3498         pci_set_master(pdev);
3499
3500         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3501         if (err) {
3502                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3503                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3504                 if (err) {
3505                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3506                         goto err_release_regions;
3507                 }
3508         }
3509         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3510         if (err) {
3511                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3512                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3513                 if (err) {
3514                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3515                         goto err_release_regions;
3516                 }
3517         }
3518
3519         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3520         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3521         /* Detect if this device is a virtual function */
3522         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3523                 /* When acting as pf, we normally skip vfs unless explicitly
3524                  * requested to probe them.
3525                  */
3526                 if (total_vfs) {
3527                         unsigned vfs_offset = 0;
3528
3529                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3530                              vfs_offset + nvfs[i] < extended_func_num(pdev);
3531                              vfs_offset += nvfs[i], i++)
3532                                 ;
3533                         if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3534                                 err = -ENODEV;
3535                                 goto err_release_regions;
3536                         }
3537                         if ((extended_func_num(pdev) - vfs_offset)
3538                             > prb_vf[i]) {
3539                                 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3540                                          extended_func_num(pdev));
3541                                 err = -ENODEV;
3542                                 goto err_release_regions;
3543                         }
3544                 }
3545         }
3546
3547         err = mlx4_catas_init(&priv->dev);
3548         if (err)
3549                 goto err_release_regions;
3550
3551         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3552         if (err)
3553                 goto err_catas;
3554
3555         return 0;
3556
3557 err_catas:
3558         mlx4_catas_end(&priv->dev);
3559
3560 err_release_regions:
3561         pci_release_regions(pdev);
3562
3563 err_disable_pdev:
3564         pci_disable_device(pdev);
3565         pci_set_drvdata(pdev, NULL);
3566         return err;
3567 }
3568
3569 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3570 {
3571         struct mlx4_priv *priv;
3572         struct mlx4_dev *dev;
3573         int ret;
3574
3575         printk_once(KERN_INFO "%s", mlx4_version);
3576
3577         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3578         if (!priv)
3579                 return -ENOMEM;
3580
3581         dev       = &priv->dev;
3582         dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3583         if (!dev->persist) {
3584                 kfree(priv);
3585                 return -ENOMEM;
3586         }
3587         dev->persist->pdev = pdev;
3588         dev->persist->dev = dev;
3589         pci_set_drvdata(pdev, dev->persist);
3590         priv->pci_dev_data = id->driver_data;
3591         mutex_init(&dev->persist->device_state_mutex);
3592         mutex_init(&dev->persist->interface_state_mutex);
3593
3594         ret =  __mlx4_init_one(pdev, id->driver_data, priv);
3595         if (ret) {
3596                 kfree(dev->persist);
3597                 kfree(priv);
3598         } else {
3599                 pci_save_state(pdev);
3600         }
3601
3602         return ret;
3603 }
3604
3605 static void mlx4_clean_dev(struct mlx4_dev *dev)
3606 {
3607         struct mlx4_dev_persistent *persist = dev->persist;
3608         struct mlx4_priv *priv = mlx4_priv(dev);
3609         unsigned long   flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3610
3611         memset(priv, 0, sizeof(*priv));
3612         priv->dev.persist = persist;
3613         priv->dev.flags = flags;
3614 }
3615
3616 static void mlx4_unload_one(struct pci_dev *pdev)
3617 {
3618         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3619         struct mlx4_dev  *dev  = persist->dev;
3620         struct mlx4_priv *priv = mlx4_priv(dev);
3621         int               pci_dev_data;
3622         int p, i;
3623
3624         if (priv->removed)
3625                 return;
3626
3627         /* saving current ports type for further use */
3628         for (i = 0; i < dev->caps.num_ports; i++) {
3629                 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3630                 dev->persist->curr_port_poss_type[i] = dev->caps.
3631                                                        possible_type[i + 1];
3632         }
3633
3634         pci_dev_data = priv->pci_dev_data;
3635
3636         mlx4_stop_sense(dev);
3637         mlx4_unregister_device(dev);
3638
3639         for (p = 1; p <= dev->caps.num_ports; p++) {
3640                 mlx4_cleanup_port_info(&priv->port[p]);
3641                 mlx4_CLOSE_PORT(dev, p);
3642         }
3643
3644         if (mlx4_is_master(dev))
3645                 mlx4_free_resource_tracker(dev,
3646                                            RES_TR_FREE_SLAVES_ONLY);
3647
3648         mlx4_cleanup_default_counters(dev);
3649         if (!mlx4_is_slave(dev))
3650                 mlx4_cleanup_counters_table(dev);
3651         mlx4_cleanup_qp_table(dev);
3652         mlx4_cleanup_srq_table(dev);
3653         mlx4_cleanup_cq_table(dev);
3654         mlx4_cmd_use_polling(dev);
3655         mlx4_cleanup_eq_table(dev);
3656         mlx4_cleanup_mcg_table(dev);
3657         mlx4_cleanup_mr_table(dev);
3658         mlx4_cleanup_xrcd_table(dev);
3659         mlx4_cleanup_pd_table(dev);
3660
3661         if (mlx4_is_master(dev))
3662                 mlx4_free_resource_tracker(dev,
3663                                            RES_TR_FREE_STRUCTS_ONLY);
3664
3665         iounmap(priv->kar);
3666         mlx4_uar_free(dev, &priv->driver_uar);
3667         mlx4_cleanup_uar_table(dev);
3668         if (!mlx4_is_slave(dev))
3669                 mlx4_clear_steering(dev);
3670         mlx4_free_eq_table(dev);
3671         if (mlx4_is_master(dev))
3672                 mlx4_multi_func_cleanup(dev);
3673         mlx4_close_hca(dev);
3674         mlx4_close_fw(dev);
3675         if (mlx4_is_slave(dev))
3676                 mlx4_multi_func_cleanup(dev);
3677         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3678
3679         if (dev->flags & MLX4_FLAG_MSI_X)
3680                 pci_disable_msix(pdev);
3681
3682         if (!mlx4_is_slave(dev))
3683                 mlx4_free_ownership(dev);
3684
3685         kfree(dev->caps.qp0_qkey);
3686         kfree(dev->caps.qp0_tunnel);
3687         kfree(dev->caps.qp0_proxy);
3688         kfree(dev->caps.qp1_tunnel);
3689         kfree(dev->caps.qp1_proxy);
3690         kfree(dev->dev_vfs);
3691
3692         mlx4_clean_dev(dev);
3693         priv->pci_dev_data = pci_dev_data;
3694         priv->removed = 1;
3695 }
3696
3697 static void mlx4_remove_one(struct pci_dev *pdev)
3698 {
3699         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3700         struct mlx4_dev  *dev  = persist->dev;
3701         struct mlx4_priv *priv = mlx4_priv(dev);
3702         int active_vfs = 0;
3703
3704         if (mlx4_is_slave(dev))
3705                 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
3706
3707         mutex_lock(&persist->interface_state_mutex);
3708         persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3709         mutex_unlock(&persist->interface_state_mutex);
3710
3711         /* Disabling SR-IOV is not allowed while there are active vf's */
3712         if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3713                 active_vfs = mlx4_how_many_lives_vf(dev);
3714                 if (active_vfs) {
3715                         pr_warn("Removing PF when there are active VF's !!\n");
3716                         pr_warn("Will not disable SR-IOV.\n");
3717                 }
3718         }
3719
3720         /* device marked to be under deletion running now without the lock
3721          * letting other tasks to be terminated
3722          */
3723         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3724                 mlx4_unload_one(pdev);
3725         else
3726                 mlx4_info(dev, "%s: interface is down\n", __func__);
3727         mlx4_catas_end(dev);
3728         if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3729                 mlx4_warn(dev, "Disabling SR-IOV\n");
3730                 pci_disable_sriov(pdev);
3731         }
3732
3733         pci_release_regions(pdev);
3734         pci_disable_device(pdev);
3735         kfree(dev->persist);
3736         kfree(priv);
3737         pci_set_drvdata(pdev, NULL);
3738 }
3739
3740 static int restore_current_port_types(struct mlx4_dev *dev,
3741                                       enum mlx4_port_type *types,
3742                                       enum mlx4_port_type *poss_types)
3743 {
3744         struct mlx4_priv *priv = mlx4_priv(dev);
3745         int err, i;
3746
3747         mlx4_stop_sense(dev);
3748
3749         mutex_lock(&priv->port_mutex);
3750         for (i = 0; i < dev->caps.num_ports; i++)
3751                 dev->caps.possible_type[i + 1] = poss_types[i];
3752         err = mlx4_change_port_types(dev, types);
3753         mlx4_start_sense(dev);
3754         mutex_unlock(&priv->port_mutex);
3755
3756         return err;
3757 }
3758
3759 int mlx4_restart_one(struct pci_dev *pdev)
3760 {
3761         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3762         struct mlx4_dev  *dev  = persist->dev;
3763         struct mlx4_priv *priv = mlx4_priv(dev);
3764         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3765         int pci_dev_data, err, total_vfs;
3766
3767         pci_dev_data = priv->pci_dev_data;
3768         total_vfs = dev->persist->num_vfs;
3769         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3770
3771         mlx4_unload_one(pdev);
3772         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
3773         if (err) {
3774                 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3775                          __func__, pci_name(pdev), err);
3776                 return err;
3777         }
3778
3779         err = restore_current_port_types(dev, dev->persist->curr_port_type,
3780                                          dev->persist->curr_port_poss_type);
3781         if (err)
3782                 mlx4_err(dev, "could not restore original port types (%d)\n",
3783                          err);
3784
3785         return err;
3786 }
3787
3788 static const struct pci_device_id mlx4_pci_table[] = {
3789         /* MT25408 "Hermon" SDR */
3790         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3791         /* MT25408 "Hermon" DDR */
3792         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3793         /* MT25408 "Hermon" QDR */
3794         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3795         /* MT25408 "Hermon" DDR PCIe gen2 */
3796         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3797         /* MT25408 "Hermon" QDR PCIe gen2 */
3798         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3799         /* MT25408 "Hermon" EN 10GigE */
3800         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3801         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3802         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3803         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3804         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3805         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3806         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3807         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3808         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3809         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3810         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3811         /* MT26478 ConnectX2 40GigE PCIe gen2 */
3812         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3813         /* MT25400 Family [ConnectX-2 Virtual Function] */
3814         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
3815         /* MT27500 Family [ConnectX-3] */
3816         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3817         /* MT27500 Family [ConnectX-3 Virtual Function] */
3818         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
3819         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3820         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3821         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3822         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3823         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3824         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3825         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3826         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3827         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3828         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3829         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3830         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
3831         { 0, }
3832 };
3833
3834 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3835
3836 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3837                                               pci_channel_state_t state)
3838 {
3839         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3840
3841         mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
3842         mlx4_enter_error_state(persist);
3843
3844         mutex_lock(&persist->interface_state_mutex);
3845         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3846                 mlx4_unload_one(pdev);
3847
3848         mutex_unlock(&persist->interface_state_mutex);
3849         if (state == pci_channel_io_perm_failure)
3850                 return PCI_ERS_RESULT_DISCONNECT;
3851
3852         pci_disable_device(pdev);
3853         return PCI_ERS_RESULT_NEED_RESET;
3854 }
3855
3856 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3857 {
3858         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3859         struct mlx4_dev  *dev  = persist->dev;
3860         int err;
3861
3862         mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
3863         err = pci_enable_device(pdev);
3864         if (err) {
3865                 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
3866                 return PCI_ERS_RESULT_DISCONNECT;
3867         }
3868
3869         pci_set_master(pdev);
3870         pci_restore_state(pdev);
3871         pci_save_state(pdev);
3872         return PCI_ERS_RESULT_RECOVERED;
3873 }
3874
3875 static void mlx4_pci_resume(struct pci_dev *pdev)
3876 {
3877         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3878         struct mlx4_dev  *dev  = persist->dev;
3879         struct mlx4_priv *priv = mlx4_priv(dev);
3880         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3881         int total_vfs;
3882         int err;
3883
3884         mlx4_err(dev, "%s was called\n", __func__);
3885         total_vfs = dev->persist->num_vfs;
3886         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3887
3888         mutex_lock(&persist->interface_state_mutex);
3889         if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
3890                 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
3891                                     priv, 1);
3892                 if (err) {
3893                         mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
3894                                  __func__,  err);
3895                         goto end;
3896                 }
3897
3898                 err = restore_current_port_types(dev, dev->persist->
3899                                                  curr_port_type, dev->persist->
3900                                                  curr_port_poss_type);
3901                 if (err)
3902                         mlx4_err(dev, "could not restore original port types (%d)\n", err);
3903         }
3904 end:
3905         mutex_unlock(&persist->interface_state_mutex);
3906
3907 }
3908
3909 static void mlx4_shutdown(struct pci_dev *pdev)
3910 {
3911         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3912
3913         mlx4_info(persist->dev, "mlx4_shutdown was called\n");
3914         mutex_lock(&persist->interface_state_mutex);
3915         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3916                 mlx4_unload_one(pdev);
3917         mutex_unlock(&persist->interface_state_mutex);
3918 }
3919
3920 static const struct pci_error_handlers mlx4_err_handler = {
3921         .error_detected = mlx4_pci_err_detected,
3922         .slot_reset     = mlx4_pci_slot_reset,
3923         .resume         = mlx4_pci_resume,
3924 };
3925
3926 static struct pci_driver mlx4_driver = {
3927         .name           = DRV_NAME,
3928         .id_table       = mlx4_pci_table,
3929         .probe          = mlx4_init_one,
3930         .shutdown       = mlx4_shutdown,
3931         .remove         = mlx4_remove_one,
3932         .err_handler    = &mlx4_err_handler,
3933 };
3934
3935 static int __init mlx4_verify_params(void)
3936 {
3937         if ((log_num_mac < 0) || (log_num_mac > 7)) {
3938                 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
3939                 return -1;
3940         }
3941
3942         if (log_num_vlan != 0)
3943                 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3944                         MLX4_LOG_NUM_VLANS);
3945
3946         if (use_prio != 0)
3947                 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
3948
3949         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
3950                 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3951                         log_mtts_per_seg);
3952                 return -1;
3953         }
3954
3955         /* Check if module param for ports type has legal combination */
3956         if (port_type_array[0] == false && port_type_array[1] == true) {
3957                 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
3958                 port_type_array[0] = true;
3959         }
3960
3961         if (mlx4_log_num_mgm_entry_size < -7 ||
3962             (mlx4_log_num_mgm_entry_size > 0 &&
3963              (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3964               mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3965                 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
3966                         mlx4_log_num_mgm_entry_size,
3967                         MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3968                         MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3969                 return -1;
3970         }
3971
3972         return 0;
3973 }
3974
3975 static int __init mlx4_init(void)
3976 {
3977         int ret;
3978
3979         if (mlx4_verify_params())
3980                 return -EINVAL;
3981
3982
3983         mlx4_wq = create_singlethread_workqueue("mlx4");
3984         if (!mlx4_wq)
3985                 return -ENOMEM;
3986
3987         ret = pci_register_driver(&mlx4_driver);
3988         if (ret < 0)
3989                 destroy_workqueue(mlx4_wq);
3990         return ret < 0 ? ret : 0;
3991 }
3992
3993 static void __exit mlx4_cleanup(void)
3994 {
3995         pci_unregister_driver(&mlx4_driver);
3996         destroy_workqueue(mlx4_wq);
3997 }
3998
3999 module_init(mlx4_init);
4000 module_exit(mlx4_cleanup);