drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  68 };
  69
  70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  71                                            struct mlx5_cmd_msg *in,
  72                                            struct mlx5_cmd_msg *out,
  73                                            void *uout, int uout_size,
  74                                            mlx5_cmd_cbk_t cbk,
  75                                            void *context, int page_queue)
  76 {
  77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  78         struct mlx5_cmd_work_ent *ent;
  79
  80         ent = kzalloc(sizeof(*ent), alloc_flags);
  81         if (!ent)
  82                 return ERR_PTR(-ENOMEM);
  83
  84         ent->in         = in;
  85         ent->out        = out;
  86         ent->uout       = uout;
  87         ent->uout_size  = uout_size;
  88         ent->callback   = cbk;
  89         ent->context    = context;
  90         ent->cmd        = cmd;
  91         ent->page_queue = page_queue;
  92
  93         return ent;
  94 }
  95
  96 static u8 alloc_token(struct mlx5_cmd *cmd)
  97 {
  98         u8 token;
  99
 100         spin_lock(&cmd->token_lock);
 101         cmd->token++;
 102         if (cmd->token == 0)
 103                 cmd->token++;
 104         token = cmd->token;
 105         spin_unlock(&cmd->token_lock);
 106
 107         return token;
 108 }
 109
 110 static int alloc_ent(struct mlx5_cmd *cmd)
 111 {
 112         unsigned long flags;
 113         int ret;
 114
 115         spin_lock_irqsave(&cmd->alloc_lock, flags);
 116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 117         if (ret < cmd->max_reg_cmds)
 118                 clear_bit(ret, &cmd->bitmask);
 119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 120
 121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 122 }
 123
 124 static void free_ent(struct mlx5_cmd *cmd, int idx)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&cmd->alloc_lock, flags);
 129         set_bit(idx, &cmd->bitmask);
 130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 131 }
 132
 133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 134 {
 135         return cmd->cmd_buf + (idx << cmd->log_stride);
 136 }
 137
 138 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
 139 {
 140         int size = msg->len;
 141         int blen = size - min_t(int, sizeof(msg->first.data), size);
 142
 143         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
 144 }
 145
 146 static u8 xor8_buf(void *buf, size_t offset, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151         int end = len + offset;
 152
 153         for (i = offset; i < end; i++)
 154                 sum ^= ptr[i];
 155
 156         return sum;
 157 }
 158
 159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 160 {
 161         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 162         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 163
 164         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 165                 return -EINVAL;
 166
 167         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 168                 return -EINVAL;
 169
 170         return 0;
 171 }
 172
 173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 174 {
 175         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 176         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 177
 178         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 179         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 180 }
 181
 182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 183 {
 184         struct mlx5_cmd_mailbox *next = msg->next;
 185         int n = mlx5_calc_cmd_blocks(msg);
 186         int i = 0;
 187
 188         for (i = 0; i < n && next; i++)  {
 189                 calc_block_sig(next->buf);
 190                 next = next->next;
 191         }
 192 }
 193
 194 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 195 {
 196         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 197         if (csum) {
 198                 calc_chain_sig(ent->in);
 199                 calc_chain_sig(ent->out);
 200         }
 201 }
 202
 203 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 204 {
 205         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 206         u8 own;
 207
 208         do {
 209                 own = READ_ONCE(ent->lay->status_own);
 210                 if (!(own & CMD_OWNER_HW)) {
 211                         ent->ret = 0;
 212                         return;
 213                 }
 214                 cond_resched();
 215         } while (time_before(jiffies, poll_end));
 216
 217         ent->ret = -ETIMEDOUT;
 218 }
 219
 220 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 221 {
 222         kfree(ent);
 223 }
 224
 225 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 226 {
 227         struct mlx5_cmd_mailbox *next = ent->out->next;
 228         int n = mlx5_calc_cmd_blocks(ent->out);
 229         int err;
 230         u8 sig;
 231         int i = 0;
 232
 233         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 234         if (sig != 0xff)
 235                 return -EINVAL;
 236
 237         for (i = 0; i < n && next; i++) {
 238                 err = verify_block_sig(next->buf);
 239                 if (err)
 240                         return err;
 241
 242                 next = next->next;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static void dump_buf(void *buf, int size, int data_only, int offset)
 249 {
 250         __be32 *p = buf;
 251         int i;
 252
 253         for (i = 0; i < size; i += 16) {
 254                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 255                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 256                          be32_to_cpu(p[3]));
 257                 p += 4;
 258                 offset += 16;
 259         }
 260         if (!data_only)
 261                 pr_debug("\n");
 262 }
 263
 264 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 265                                        u32 *synd, u8 *status)
 266 {
 267         *synd = 0;
 268         *status = 0;
 269
 270         switch (op) {
 271         case MLX5_CMD_OP_TEARDOWN_HCA:
 272         case MLX5_CMD_OP_DISABLE_HCA:
 273         case MLX5_CMD_OP_MANAGE_PAGES:
 274         case MLX5_CMD_OP_DESTROY_MKEY:
 275         case MLX5_CMD_OP_DESTROY_EQ:
 276         case MLX5_CMD_OP_DESTROY_CQ:
 277         case MLX5_CMD_OP_DESTROY_QP:
 278         case MLX5_CMD_OP_DESTROY_PSV:
 279         case MLX5_CMD_OP_DESTROY_SRQ:
 280         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 281         case MLX5_CMD_OP_DESTROY_XRQ:
 282         case MLX5_CMD_OP_DESTROY_DCT:
 283         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 284         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 285         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 286         case MLX5_CMD_OP_DEALLOC_PD:
 287         case MLX5_CMD_OP_DEALLOC_UAR:
 288         case MLX5_CMD_OP_DETACH_FROM_MCG:
 289         case MLX5_CMD_OP_DEALLOC_XRCD:
 290         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 291         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 292         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 293         case MLX5_CMD_OP_DESTROY_LAG:
 294         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 295         case MLX5_CMD_OP_DESTROY_TIR:
 296         case MLX5_CMD_OP_DESTROY_SQ:
 297         case MLX5_CMD_OP_DESTROY_RQ:
 298         case MLX5_CMD_OP_DESTROY_RMP:
 299         case MLX5_CMD_OP_DESTROY_TIS:
 300         case MLX5_CMD_OP_DESTROY_RQT:
 301         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 302         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 303         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 304         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 305         case MLX5_CMD_OP_2ERR_QP:
 306         case MLX5_CMD_OP_2RST_QP:
 307         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 308         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 309         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 310         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 311         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 312         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 313         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 314         case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
 315                 return MLX5_CMD_STAT_OK;
 316
 317         case MLX5_CMD_OP_QUERY_HCA_CAP:
 318         case MLX5_CMD_OP_QUERY_ADAPTER:
 319         case MLX5_CMD_OP_INIT_HCA:
 320         case MLX5_CMD_OP_ENABLE_HCA:
 321         case MLX5_CMD_OP_QUERY_PAGES:
 322         case MLX5_CMD_OP_SET_HCA_CAP:
 323         case MLX5_CMD_OP_QUERY_ISSI:
 324         case MLX5_CMD_OP_SET_ISSI:
 325         case MLX5_CMD_OP_CREATE_MKEY:
 326         case MLX5_CMD_OP_QUERY_MKEY:
 327         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 328         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 329         case MLX5_CMD_OP_CREATE_EQ:
 330         case MLX5_CMD_OP_QUERY_EQ:
 331         case MLX5_CMD_OP_GEN_EQE:
 332         case MLX5_CMD_OP_CREATE_CQ:
 333         case MLX5_CMD_OP_QUERY_CQ:
 334         case MLX5_CMD_OP_MODIFY_CQ:
 335         case MLX5_CMD_OP_CREATE_QP:
 336         case MLX5_CMD_OP_RST2INIT_QP:
 337         case MLX5_CMD_OP_INIT2RTR_QP:
 338         case MLX5_CMD_OP_RTR2RTS_QP:
 339         case MLX5_CMD_OP_RTS2RTS_QP:
 340         case MLX5_CMD_OP_SQERR2RTS_QP:
 341         case MLX5_CMD_OP_QUERY_QP:
 342         case MLX5_CMD_OP_SQD_RTS_QP:
 343         case MLX5_CMD_OP_INIT2INIT_QP:
 344         case MLX5_CMD_OP_CREATE_PSV:
 345         case MLX5_CMD_OP_CREATE_SRQ:
 346         case MLX5_CMD_OP_QUERY_SRQ:
 347         case MLX5_CMD_OP_ARM_RQ:
 348         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 349         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 350         case MLX5_CMD_OP_ARM_XRC_SRQ:
 351         case MLX5_CMD_OP_CREATE_XRQ:
 352         case MLX5_CMD_OP_QUERY_XRQ:
 353         case MLX5_CMD_OP_ARM_XRQ:
 354         case MLX5_CMD_OP_CREATE_DCT:
 355         case MLX5_CMD_OP_DRAIN_DCT:
 356         case MLX5_CMD_OP_QUERY_DCT:
 357         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 358         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 359         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 360         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 361         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 362         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 363         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 364         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 365         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 366         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 367         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 368         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 369         case MLX5_CMD_OP_QUERY_VNIC_ENV:
 370         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 371         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 372         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 373         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
 374         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 375         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 376         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 377         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 378         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 379         case MLX5_CMD_OP_ALLOC_PD:
 380         case MLX5_CMD_OP_ALLOC_UAR:
 381         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 382         case MLX5_CMD_OP_ACCESS_REG:
 383         case MLX5_CMD_OP_ATTACH_TO_MCG:
 384         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 385         case MLX5_CMD_OP_MAD_IFC:
 386         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 387         case MLX5_CMD_OP_SET_MAD_DEMUX:
 388         case MLX5_CMD_OP_NOP:
 389         case MLX5_CMD_OP_ALLOC_XRCD:
 390         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 391         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 392         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 393         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 394         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 395         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 396         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 397         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 398         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 399         case MLX5_CMD_OP_CREATE_LAG:
 400         case MLX5_CMD_OP_MODIFY_LAG:
 401         case MLX5_CMD_OP_QUERY_LAG:
 402         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 403         case MLX5_CMD_OP_CREATE_TIR:
 404         case MLX5_CMD_OP_MODIFY_TIR:
 405         case MLX5_CMD_OP_QUERY_TIR:
 406         case MLX5_CMD_OP_CREATE_SQ:
 407         case MLX5_CMD_OP_MODIFY_SQ:
 408         case MLX5_CMD_OP_QUERY_SQ:
 409         case MLX5_CMD_OP_CREATE_RQ:
 410         case MLX5_CMD_OP_MODIFY_RQ:
 411         case MLX5_CMD_OP_QUERY_RQ:
 412         case MLX5_CMD_OP_CREATE_RMP:
 413         case MLX5_CMD_OP_MODIFY_RMP:
 414         case MLX5_CMD_OP_QUERY_RMP:
 415         case MLX5_CMD_OP_CREATE_TIS:
 416         case MLX5_CMD_OP_MODIFY_TIS:
 417         case MLX5_CMD_OP_QUERY_TIS:
 418         case MLX5_CMD_OP_CREATE_RQT:
 419         case MLX5_CMD_OP_MODIFY_RQT:
 420         case MLX5_CMD_OP_QUERY_RQT:
 421
 422         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 423         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 424         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 425         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 426         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 427         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 428         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 429         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 430         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 431         case MLX5_CMD_OP_FPGA_CREATE_QP:
 432         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 433         case MLX5_CMD_OP_FPGA_QUERY_QP:
 434         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 435         case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
 436         case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
 437         case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
 438                 *status = MLX5_DRIVER_STATUS_ABORTED;
 439                 *synd = MLX5_DRIVER_SYND;
 440                 return -EIO;
 441         default:
 442                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 443                 return -EINVAL;
 444         }
 445 }
 446
 447 const char *mlx5_command_str(int command)
 448 {
 449 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 450
 451         switch (command) {
 452         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 453         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 454         MLX5_COMMAND_STR_CASE(INIT_HCA);
 455         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 456         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 457         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 458         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 459         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 460         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 461         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 462         MLX5_COMMAND_STR_CASE(SET_ISSI);
 463         MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
 464         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 465         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 466         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 467         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 468         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 469         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 470         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 471         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 472         MLX5_COMMAND_STR_CASE(GEN_EQE);
 473         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 474         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 475         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 476         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 477         MLX5_COMMAND_STR_CASE(CREATE_QP);
 478         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 479         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 480         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 481         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 482         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 483         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 484         MLX5_COMMAND_STR_CASE(2ERR_QP);
 485         MLX5_COMMAND_STR_CASE(2RST_QP);
 486         MLX5_COMMAND_STR_CASE(QUERY_QP);
 487         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 488         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 489         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 490         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 491         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 492         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 493         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 494         MLX5_COMMAND_STR_CASE(ARM_RQ);
 495         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 496         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 497         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 498         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 499         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 500         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 501         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 502         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 503         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 504         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 505         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 506         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 507         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 508         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 509         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 510         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 511         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 512         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 513         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 514         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 515         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 516         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
 517         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 518         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 519         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 520         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 521         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
 522         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 523         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 524         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 525         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 526         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 527         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 528         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 529         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 530         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 531         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 532         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 533         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 534         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 535         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 536         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 537         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 538         MLX5_COMMAND_STR_CASE(MAD_IFC);
 539         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 540         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 541         MLX5_COMMAND_STR_CASE(NOP);
 542         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 543         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 544         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 545         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 546         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 547         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 548         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 549         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 550         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 551         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 552         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 553         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 554         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 555         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 556         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 557         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 558         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 559         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 560         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 561         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 562         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 563         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 564         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 565         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 566         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 567         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 568         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 569         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 570         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 571         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 572         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 573         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 574         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 575         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 576         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 577         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 578         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 579         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 580         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 581         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 582         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 583         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 584         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 585         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 586         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 587         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 588         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 589         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 590         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 591         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 592         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 593         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 594         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 595         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 596         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 597         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 598         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 599         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 600         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 601         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 602         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
 603         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
 604         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 605         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 606         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 607         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 608         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 609         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 610         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 611         MLX5_COMMAND_STR_CASE(CREATE_XRQ);
 612         MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
 613         MLX5_COMMAND_STR_CASE(QUERY_XRQ);
 614         MLX5_COMMAND_STR_CASE(ARM_XRQ);
 615         MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
 616         MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
 617         MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
 618         MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
 619         MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
 620         default: return "unknown command opcode";
 621         }
 622 }
 623
 624 static const char *cmd_status_str(u8 status)
 625 {
 626         switch (status) {
 627         case MLX5_CMD_STAT_OK:
 628                 return "OK";
 629         case MLX5_CMD_STAT_INT_ERR:
 630                 return "internal error";
 631         case MLX5_CMD_STAT_BAD_OP_ERR:
 632                 return "bad operation";
 633         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 634                 return "bad parameter";
 635         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 636                 return "bad system state";
 637         case MLX5_CMD_STAT_BAD_RES_ERR:
 638                 return "bad resource";
 639         case MLX5_CMD_STAT_RES_BUSY:
 640                 return "resource busy";
 641         case MLX5_CMD_STAT_LIM_ERR:
 642                 return "limits exceeded";
 643         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 644                 return "bad resource state";
 645         case MLX5_CMD_STAT_IX_ERR:
 646                 return "bad index";
 647         case MLX5_CMD_STAT_NO_RES_ERR:
 648                 return "no resources";
 649         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 650                 return "bad input length";
 651         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 652                 return "bad output length";
 653         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 654                 return "bad QP state";
 655         case MLX5_CMD_STAT_BAD_PKT_ERR:
 656                 return "bad packet (discarded)";
 657         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 658                 return "bad size too many outstanding CQEs";
 659         default:
 660                 return "unknown status";
 661         }
 662 }
 663
 664 static int cmd_status_to_err(u8 status)
 665 {
 666         switch (status) {
 667         case MLX5_CMD_STAT_OK:                          return 0;
 668         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 669         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 670         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 671         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 672         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 673         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 674         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 675         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 676         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 677         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 678         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 679         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 680         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 681         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 682         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 683         default:                                        return -EIO;
 684         }
 685 }
 686
 687 struct mlx5_ifc_mbox_out_bits {
 688         u8         status[0x8];
 689         u8         reserved_at_8[0x18];
 690
 691         u8         syndrome[0x20];
 692
 693         u8         reserved_at_40[0x40];
 694 };
 695
 696 struct mlx5_ifc_mbox_in_bits {
 697         u8         opcode[0x10];
 698         u8         uid[0x10];
 699
 700         u8         reserved_at_20[0x10];
 701         u8         op_mod[0x10];
 702
 703         u8         reserved_at_40[0x40];
 704 };
 705
 706 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 707 {
 708         *status = MLX5_GET(mbox_out, out, status);
 709         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 710 }
 711
 712 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 713 {
 714         u32 syndrome;
 715         u8  status;
 716         u16 opcode;
 717         u16 op_mod;
 718         u16 uid;
 719
 720         mlx5_cmd_mbox_status(out, &status, &syndrome);
 721         if (!status)
 722                 return 0;
 723
 724         opcode = MLX5_GET(mbox_in, in, opcode);
 725         op_mod = MLX5_GET(mbox_in, in, op_mod);
 726         uid    = MLX5_GET(mbox_in, in, uid);
 727
 728         if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
 729                 mlx5_core_err_rl(dev,
 730                         "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 731                         mlx5_command_str(opcode), opcode, op_mod,
 732                         cmd_status_str(status), status, syndrome);
 733         else
 734                 mlx5_core_dbg(dev,
 735                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 736                       mlx5_command_str(opcode),
 737                       opcode, op_mod,
 738                       cmd_status_str(status),
 739                       status,
 740                       syndrome);
 741
 742         return cmd_status_to_err(status);
 743 }
 744
 745 static void dump_command(struct mlx5_core_dev *dev,
 746                          struct mlx5_cmd_work_ent *ent, int input)
 747 {
 748         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 749         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 750         struct mlx5_cmd_mailbox *next = msg->next;
 751         int n = mlx5_calc_cmd_blocks(msg);
 752         int data_only;
 753         u32 offset = 0;
 754         int dump_len;
 755         int i;
 756
 757         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 758
 759         if (data_only)
 760                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 761                                    "dump command data %s(0x%x) %s\n",
 762                                    mlx5_command_str(op), op,
 763                                    input ? "INPUT" : "OUTPUT");
 764         else
 765                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 766                               mlx5_command_str(op), op,
 767                               input ? "INPUT" : "OUTPUT");
 768
 769         if (data_only) {
 770                 if (input) {
 771                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 772                         offset += sizeof(ent->lay->in);
 773                 } else {
 774                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 775                         offset += sizeof(ent->lay->out);
 776                 }
 777         } else {
 778                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 779                 offset += sizeof(*ent->lay);
 780         }
 781
 782         for (i = 0; i < n && next; i++)  {
 783                 if (data_only) {
 784                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 785                         dump_buf(next->buf, dump_len, 1, offset);
 786                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 787                 } else {
 788                         mlx5_core_dbg(dev, "command block:\n");
 789                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 790                         offset += sizeof(struct mlx5_cmd_prot_block);
 791                 }
 792                 next = next->next;
 793         }
 794
 795         if (data_only)
 796                 pr_debug("\n");
 797 }
 798
 799 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 800 {
 801         return MLX5_GET(mbox_in, in->first.data, opcode);
 802 }
 803
 804 static void cb_timeout_handler(struct work_struct *work)
 805 {
 806         struct delayed_work *dwork = container_of(work, struct delayed_work,
 807                                                   work);
 808         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 809                                                      struct mlx5_cmd_work_ent,
 810                                                      cb_timeout_work);
 811         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 812                                                  cmd);
 813
 814         ent->ret = -ETIMEDOUT;
 815         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 816                        mlx5_command_str(msg_to_opcode(ent->in)),
 817                        msg_to_opcode(ent->in));
 818         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 819 }
 820
 821 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 822 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 823                               struct mlx5_cmd_msg *msg);
 824
 825 static void cmd_work_handler(struct work_struct *work)
 826 {
 827         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 828         struct mlx5_cmd *cmd = ent->cmd;
 829         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 830         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 831         struct mlx5_cmd_layout *lay;
 832         struct semaphore *sem;
 833         unsigned long flags;
 834         bool poll_cmd = ent->polling;
 835         int alloc_ret;
 836         int cmd_mode;
 837
 838         complete(&ent->handling);
 839         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 840         down(sem);
 841         if (!ent->page_queue) {
 842                 alloc_ret = alloc_ent(cmd);
 843                 if (alloc_ret < 0) {
 844                         mlx5_core_err(dev, "failed to allocate command entry\n");
 845                         if (ent->callback) {
 846                                 ent->callback(-EAGAIN, ent->context);
 847                                 mlx5_free_cmd_msg(dev, ent->out);
 848                                 free_msg(dev, ent->in);
 849                                 free_cmd(ent);
 850                         } else {
 851                                 ent->ret = -EAGAIN;
 852                                 complete(&ent->done);
 853                         }
 854                         up(sem);
 855                         return;
 856                 }
 857                 ent->idx = alloc_ret;
 858         } else {
 859                 ent->idx = cmd->max_reg_cmds;
 860                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 861                 clear_bit(ent->idx, &cmd->bitmask);
 862                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 863         }
 864
 865         cmd->ent_arr[ent->idx] = ent;
 866         lay = get_inst(cmd, ent->idx);
 867         ent->lay = lay;
 868         memset(lay, 0, sizeof(*lay));
 869         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 870         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 871         if (ent->in->next)
 872                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 873         lay->inlen = cpu_to_be32(ent->in->len);
 874         if (ent->out->next)
 875                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 876         lay->outlen = cpu_to_be32(ent->out->len);
 877         lay->type = MLX5_PCI_CMD_XPORT;
 878         lay->token = ent->token;
 879         lay->status_own = CMD_OWNER_HW;
 880         set_signature(ent, !cmd->checksum_disabled);
 881         dump_command(dev, ent, 1);
 882         ent->ts1 = ktime_get_ns();
 883         cmd_mode = cmd->mode;
 884
 885         if (ent->callback)
 886                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 887         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 888
 889         /* Skip sending command to fw if internal error */
 890         if (pci_channel_offline(dev->pdev) ||
 891             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 892                 u8 status = 0;
 893                 u32 drv_synd;
 894
 895                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 896                 MLX5_SET(mbox_out, ent->out, status, status);
 897                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 898
 899                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 900                 /* no doorbell, no need to keep the entry */
 901                 free_ent(cmd, ent->idx);
 902                 if (ent->callback)
 903                         free_cmd(ent);
 904                 return;
 905         }
 906
 907         /* ring doorbell after the descriptor is valid */
 908         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 909         wmb();
 910         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 911         mmiowb();
 912         /* if not in polling don't use ent after this point */
 913         if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
 914                 poll_timeout(ent);
 915                 /* make sure we read the descriptor after ownership is SW */
 916                 rmb();
 917                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 918         }
 919 }
 920
 921 static const char *deliv_status_to_str(u8 status)
 922 {
 923         switch (status) {
 924         case MLX5_CMD_DELIVERY_STAT_OK:
 925                 return "no errors";
 926         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 927                 return "signature error";
 928         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 929                 return "token error";
 930         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 931                 return "bad block number";
 932         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 933                 return "output pointer not aligned to block size";
 934         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 935                 return "input pointer not aligned to block size";
 936         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 937                 return "firmware internal error";
 938         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 939                 return "command input length error";
 940         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 941                 return "command output length error";
 942         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 943                 return "reserved fields not cleared";
 944         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 945                 return "bad command descriptor type";
 946         default:
 947                 return "unknown status code";
 948         }
 949 }
 950
 951 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 952 {
 953         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 954         struct mlx5_cmd *cmd = &dev->cmd;
 955         int err;
 956
 957         if (!wait_for_completion_timeout(&ent->handling, timeout) &&
 958             cancel_work_sync(&ent->work)) {
 959                 ent->ret = -ECANCELED;
 960                 goto out_err;
 961         }
 962         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 963                 wait_for_completion(&ent->done);
 964         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 965                 ent->ret = -ETIMEDOUT;
 966                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 967         }
 968
 969 out_err:
 970         err = ent->ret;
 971
 972         if (err == -ETIMEDOUT) {
 973                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 974                                mlx5_command_str(msg_to_opcode(ent->in)),
 975                                msg_to_opcode(ent->in));
 976         } else if (err == -ECANCELED) {
 977                 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
 978                                mlx5_command_str(msg_to_opcode(ent->in)),
 979                                msg_to_opcode(ent->in));
 980         }
 981         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 982                       err, deliv_status_to_str(ent->status), ent->status);
 983
 984         return err;
 985 }
 986
 987 /*  Notes:
 988  *    1. Callback functions may not sleep
 989  *    2. page queue commands do not support asynchrous completion
 990  */
 991 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 992                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 993                            mlx5_cmd_cbk_t callback,
 994                            void *context, int page_queue, u8 *status,
 995                            u8 token, bool force_polling)
 996 {
 997         struct mlx5_cmd *cmd = &dev->cmd;
 998         struct mlx5_cmd_work_ent *ent;
 999         struct mlx5_cmd_stats *stats;
1000         int err = 0;
1001         s64 ds;
1002         u16 op;
1003
1004         if (callback && page_queue)
1005                 return -EINVAL;
1006
1007         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
1008                         page_queue);
1009         if (IS_ERR(ent))
1010                 return PTR_ERR(ent);
1011
1012         ent->token = token;
1013         ent->polling = force_polling;
1014
1015         init_completion(&ent->handling);
1016         if (!callback)
1017                 init_completion(&ent->done);
1018
1019         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1020         INIT_WORK(&ent->work, cmd_work_handler);
1021         if (page_queue) {
1022                 cmd_work_handler(&ent->work);
1023         } else if (!queue_work(cmd->wq, &ent->work)) {
1024                 mlx5_core_warn(dev, "failed to queue work\n");
1025                 err = -ENOMEM;
1026                 goto out_free;
1027         }
1028
1029         if (callback)
1030                 goto out;
1031
1032         err = wait_func(dev, ent);
1033         if (err == -ETIMEDOUT)
1034                 goto out;
1035         if (err == -ECANCELED)
1036                 goto out_free;
1037
1038         ds = ent->ts2 - ent->ts1;
1039         op = MLX5_GET(mbox_in, in->first.data, opcode);
1040         if (op < ARRAY_SIZE(cmd->stats)) {
1041                 stats = &cmd->stats[op];
1042                 spin_lock_irq(&stats->lock);
1043                 stats->sum += ds;
1044                 ++stats->n;
1045                 spin_unlock_irq(&stats->lock);
1046         }
1047         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1048                            "fw exec time for %s is %lld nsec\n",
1049                            mlx5_command_str(op), ds);
1050         *status = ent->status;
1051
1052 out_free:
1053         free_cmd(ent);
1054 out:
1055         return err;
1056 }
1057
1058 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1059                          size_t count, loff_t *pos)
1060 {
1061         struct mlx5_core_dev *dev = filp->private_data;
1062         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1063         char lbuf[3];
1064         int err;
1065
1066         if (!dbg->in_msg || !dbg->out_msg)
1067                 return -ENOMEM;
1068
1069         if (count < sizeof(lbuf) - 1)
1070                 return -EINVAL;
1071
1072         if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1073                 return -EFAULT;
1074
1075         lbuf[sizeof(lbuf) - 1] = 0;
1076
1077         if (strcmp(lbuf, "go"))
1078                 return -EINVAL;
1079
1080         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1081
1082         return err ? err : count;
1083 }
1084
1085 static const struct file_operations fops = {
1086         .owner  = THIS_MODULE,
1087         .open   = simple_open,
1088         .write  = dbg_write,
1089 };
1090
1091 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1092                             u8 token)
1093 {
1094         struct mlx5_cmd_prot_block *block;
1095         struct mlx5_cmd_mailbox *next;
1096         int copy;
1097
1098         if (!to || !from)
1099                 return -ENOMEM;
1100
1101         copy = min_t(int, size, sizeof(to->first.data));
1102         memcpy(to->first.data, from, copy);
1103         size -= copy;
1104         from += copy;
1105
1106         next = to->next;
1107         while (size) {
1108                 if (!next) {
1109                         /* this is a BUG */
1110                         return -ENOMEM;
1111                 }
1112
1113                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1114                 block = next->buf;
1115                 memcpy(block->data, from, copy);
1116                 from += copy;
1117                 size -= copy;
1118                 block->token = token;
1119                 next = next->next;
1120         }
1121
1122         return 0;
1123 }
1124
1125 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1126 {
1127         struct mlx5_cmd_prot_block *block;
1128         struct mlx5_cmd_mailbox *next;
1129         int copy;
1130
1131         if (!to || !from)
1132                 return -ENOMEM;
1133
1134         copy = min_t(int, size, sizeof(from->first.data));
1135         memcpy(to, from->first.data, copy);
1136         size -= copy;
1137         to += copy;
1138
1139         next = from->next;
1140         while (size) {
1141                 if (!next) {
1142                         /* this is a BUG */
1143                         return -ENOMEM;
1144                 }
1145
1146                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1147                 block = next->buf;
1148
1149                 memcpy(to, block->data, copy);
1150                 to += copy;
1151                 size -= copy;
1152                 next = next->next;
1153         }
1154
1155         return 0;
1156 }
1157
1158 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1159                                               gfp_t flags)
1160 {
1161         struct mlx5_cmd_mailbox *mailbox;
1162
1163         mailbox = kmalloc(sizeof(*mailbox), flags);
1164         if (!mailbox)
1165                 return ERR_PTR(-ENOMEM);
1166
1167         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1168                                        &mailbox->dma);
1169         if (!mailbox->buf) {
1170                 mlx5_core_dbg(dev, "failed allocation\n");
1171                 kfree(mailbox);
1172                 return ERR_PTR(-ENOMEM);
1173         }
1174         mailbox->next = NULL;
1175
1176         return mailbox;
1177 }
1178
1179 static void free_cmd_box(struct mlx5_core_dev *dev,
1180                          struct mlx5_cmd_mailbox *mailbox)
1181 {
1182         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1183         kfree(mailbox);
1184 }
1185
1186 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1187                                                gfp_t flags, int size,
1188                                                u8 token)
1189 {
1190         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1191         struct mlx5_cmd_prot_block *block;
1192         struct mlx5_cmd_msg *msg;
1193         int err;
1194         int n;
1195         int i;
1196
1197         msg = kzalloc(sizeof(*msg), flags);
1198         if (!msg)
1199                 return ERR_PTR(-ENOMEM);
1200
1201         msg->len = size;
1202         n = mlx5_calc_cmd_blocks(msg);
1203
1204         for (i = 0; i < n; i++) {
1205                 tmp = alloc_cmd_box(dev, flags);
1206                 if (IS_ERR(tmp)) {
1207                         mlx5_core_warn(dev, "failed allocating block\n");
1208                         err = PTR_ERR(tmp);
1209                         goto err_alloc;
1210                 }
1211
1212                 block = tmp->buf;
1213                 tmp->next = head;
1214                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1215                 block->block_num = cpu_to_be32(n - i - 1);
1216                 block->token = token;
1217                 head = tmp;
1218         }
1219         msg->next = head;
1220         return msg;
1221
1222 err_alloc:
1223         while (head) {
1224                 tmp = head->next;
1225                 free_cmd_box(dev, head);
1226                 head = tmp;
1227         }
1228         kfree(msg);
1229
1230         return ERR_PTR(err);
1231 }
1232
1233 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1234                               struct mlx5_cmd_msg *msg)
1235 {
1236         struct mlx5_cmd_mailbox *head = msg->next;
1237         struct mlx5_cmd_mailbox *next;
1238
1239         while (head) {
1240                 next = head->next;
1241                 free_cmd_box(dev, head);
1242                 head = next;
1243         }
1244         kfree(msg);
1245 }
1246
1247 static ssize_t data_write(struct file *filp, const char __user *buf,
1248                           size_t count, loff_t *pos)
1249 {
1250         struct mlx5_core_dev *dev = filp->private_data;
1251         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1252         void *ptr;
1253
1254         if (*pos != 0)
1255                 return -EINVAL;
1256
1257         kfree(dbg->in_msg);
1258         dbg->in_msg = NULL;
1259         dbg->inlen = 0;
1260         ptr = memdup_user(buf, count);
1261         if (IS_ERR(ptr))
1262                 return PTR_ERR(ptr);
1263         dbg->in_msg = ptr;
1264         dbg->inlen = count;
1265
1266         *pos = count;
1267
1268         return count;
1269 }
1270
1271 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1272                          loff_t *pos)
1273 {
1274         struct mlx5_core_dev *dev = filp->private_data;
1275         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1276
1277         if (!dbg->out_msg)
1278                 return -ENOMEM;
1279
1280         return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1281                                        dbg->outlen);
1282 }
1283
1284 static const struct file_operations dfops = {
1285         .owner  = THIS_MODULE,
1286         .open   = simple_open,
1287         .write  = data_write,
1288         .read   = data_read,
1289 };
1290
1291 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1292                            loff_t *pos)
1293 {
1294         struct mlx5_core_dev *dev = filp->private_data;
1295         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1296         char outlen[8];
1297         int err;
1298
1299         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1300         if (err < 0)
1301                 return err;
1302
1303         return simple_read_from_buffer(buf, count, pos, outlen, err);
1304 }
1305
1306 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1307                             size_t count, loff_t *pos)
1308 {
1309         struct mlx5_core_dev *dev = filp->private_data;
1310         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1311         char outlen_str[8] = {0};
1312         int outlen;
1313         void *ptr;
1314         int err;
1315
1316         if (*pos != 0 || count > 6)
1317                 return -EINVAL;
1318
1319         kfree(dbg->out_msg);
1320         dbg->out_msg = NULL;
1321         dbg->outlen = 0;
1322
1323         if (copy_from_user(outlen_str, buf, count))
1324                 return -EFAULT;
1325
1326         err = sscanf(outlen_str, "%d", &outlen);
1327         if (err < 0)
1328                 return err;
1329
1330         ptr = kzalloc(outlen, GFP_KERNEL);
1331         if (!ptr)
1332                 return -ENOMEM;
1333
1334         dbg->out_msg = ptr;
1335         dbg->outlen = outlen;
1336
1337         *pos = count;
1338
1339         return count;
1340 }
1341
1342 static const struct file_operations olfops = {
1343         .owner  = THIS_MODULE,
1344         .open   = simple_open,
1345         .write  = outlen_write,
1346         .read   = outlen_read,
1347 };
1348
1349 static void set_wqname(struct mlx5_core_dev *dev)
1350 {
1351         struct mlx5_cmd *cmd = &dev->cmd;
1352
1353         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1354                  dev_name(&dev->pdev->dev));
1355 }
1356
1357 static void clean_debug_files(struct mlx5_core_dev *dev)
1358 {
1359         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1360
1361         if (!mlx5_debugfs_root)
1362                 return;
1363
1364         mlx5_cmdif_debugfs_cleanup(dev);
1365         debugfs_remove_recursive(dbg->dbg_root);
1366 }
1367
1368 static int create_debugfs_files(struct mlx5_core_dev *dev)
1369 {
1370         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1371         int err = -ENOMEM;
1372
1373         if (!mlx5_debugfs_root)
1374                 return 0;
1375
1376         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1377         if (!dbg->dbg_root)
1378                 return err;
1379
1380         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1381                                           dev, &dfops);
1382         if (!dbg->dbg_in)
1383                 goto err_dbg;
1384
1385         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1386                                            dev, &dfops);
1387         if (!dbg->dbg_out)
1388                 goto err_dbg;
1389
1390         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1391                                               dev, &olfops);
1392         if (!dbg->dbg_outlen)
1393                 goto err_dbg;
1394
1395         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1396                                             &dbg->status);
1397         if (!dbg->dbg_status)
1398                 goto err_dbg;
1399
1400         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1401         if (!dbg->dbg_run)
1402                 goto err_dbg;
1403
1404         mlx5_cmdif_debugfs_init(dev);
1405
1406         return 0;
1407
1408 err_dbg:
1409         clean_debug_files(dev);
1410         return err;
1411 }
1412
1413 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1414 {
1415         struct mlx5_cmd *cmd = &dev->cmd;
1416         int i;
1417
1418         for (i = 0; i < cmd->max_reg_cmds; i++)
1419                 down(&cmd->sem);
1420         down(&cmd->pages_sem);
1421
1422         cmd->mode = mode;
1423
1424         up(&cmd->pages_sem);
1425         for (i = 0; i < cmd->max_reg_cmds; i++)
1426                 up(&cmd->sem);
1427 }
1428
1429 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1430 {
1431         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1432 }
1433
1434 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1435 {
1436         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1437 }
1438
1439 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1440 {
1441         unsigned long flags;
1442
1443         if (msg->parent) {
1444                 spin_lock_irqsave(&msg->parent->lock, flags);
1445                 list_add_tail(&msg->list, &msg->parent->head);
1446                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1447         } else {
1448                 mlx5_free_cmd_msg(dev, msg);
1449         }
1450 }
1451
1452 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1453 {
1454         struct mlx5_cmd *cmd = &dev->cmd;
1455         struct mlx5_cmd_work_ent *ent;
1456         mlx5_cmd_cbk_t callback;
1457         void *context;
1458         int err;
1459         int i;
1460         s64 ds;
1461         struct mlx5_cmd_stats *stats;
1462         unsigned long flags;
1463         unsigned long vector;
1464
1465         /* there can be at most 32 command queues */
1466         vector = vec & 0xffffffff;
1467         for (i = 0; i < (1 << cmd->log_sz); i++) {
1468                 if (test_bit(i, &vector)) {
1469                         struct semaphore *sem;
1470
1471                         ent = cmd->ent_arr[i];
1472
1473                         /* if we already completed the command, ignore it */
1474                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1475                                                 &ent->state)) {
1476                                 /* only real completion can free the cmd slot */
1477                                 if (!forced) {
1478                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1479                                                       ent->idx);
1480                                         free_ent(cmd, ent->idx);
1481                                         free_cmd(ent);
1482                                 }
1483                                 continue;
1484                         }
1485
1486                         if (ent->callback)
1487                                 cancel_delayed_work(&ent->cb_timeout_work);
1488                         if (ent->page_queue)
1489                                 sem = &cmd->pages_sem;
1490                         else
1491                                 sem = &cmd->sem;
1492                         ent->ts2 = ktime_get_ns();
1493                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1494                         dump_command(dev, ent, 0);
1495                         if (!ent->ret) {
1496                                 if (!cmd->checksum_disabled)
1497                                         ent->ret = verify_signature(ent);
1498                                 else
1499                                         ent->ret = 0;
1500                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1501                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1502                                 else
1503                                         ent->status = ent->lay->status_own >> 1;
1504
1505                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1506                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1507                         }
1508
1509                         /* only real completion will free the entry slot */
1510                         if (!forced)
1511                                 free_ent(cmd, ent->idx);
1512
1513                         if (ent->callback) {
1514                                 ds = ent->ts2 - ent->ts1;
1515                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1516                                         stats = &cmd->stats[ent->op];
1517                                         spin_lock_irqsave(&stats->lock, flags);
1518                                         stats->sum += ds;
1519                                         ++stats->n;
1520                                         spin_unlock_irqrestore(&stats->lock, flags);
1521                                 }
1522
1523                                 callback = ent->callback;
1524                                 context = ent->context;
1525                                 err = ent->ret;
1526                                 if (!err) {
1527                                         err = mlx5_copy_from_msg(ent->uout,
1528                                                                  ent->out,
1529                                                                  ent->uout_size);
1530
1531                                         err = err ? err : mlx5_cmd_check(dev,
1532                                                                         ent->in->first.data,
1533                                                                         ent->uout);
1534                                 }
1535
1536                                 mlx5_free_cmd_msg(dev, ent->out);
1537                                 free_msg(dev, ent->in);
1538
1539                                 err = err ? err : ent->status;
1540                                 if (!forced)
1541                                         free_cmd(ent);
1542                                 callback(err, context);
1543                         } else {
1544                                 complete(&ent->done);
1545                         }
1546                         up(sem);
1547                 }
1548         }
1549 }
1550 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1551
1552 static int status_to_err(u8 status)
1553 {
1554         return status ? -1 : 0; /* TBD more meaningful codes */
1555 }
1556
1557 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1558                                       gfp_t gfp)
1559 {
1560         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1561         struct cmd_msg_cache *ch = NULL;
1562         struct mlx5_cmd *cmd = &dev->cmd;
1563         int i;
1564
1565         if (in_size <= 16)
1566                 goto cache_miss;
1567
1568         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1569                 ch = &cmd->cache[i];
1570                 if (in_size > ch->max_inbox_size)
1571                         continue;
1572                 spin_lock_irq(&ch->lock);
1573                 if (list_empty(&ch->head)) {
1574                         spin_unlock_irq(&ch->lock);
1575                         continue;
1576                 }
1577                 msg = list_entry(ch->head.next, typeof(*msg), list);
1578                 /* For cached lists, we must explicitly state what is
1579                  * the real size
1580                  */
1581                 msg->len = in_size;
1582                 list_del(&msg->list);
1583                 spin_unlock_irq(&ch->lock);
1584                 break;
1585         }
1586
1587         if (!IS_ERR(msg))
1588                 return msg;
1589
1590 cache_miss:
1591         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1592         return msg;
1593 }
1594
1595 static int is_manage_pages(void *in)
1596 {
1597         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1598 }
1599
1600 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1601                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1602                     bool force_polling)
1603 {
1604         struct mlx5_cmd_msg *inb;
1605         struct mlx5_cmd_msg *outb;
1606         int pages_queue;
1607         gfp_t gfp;
1608         int err;
1609         u8 status = 0;
1610         u32 drv_synd;
1611         u8 token;
1612
1613         if (pci_channel_offline(dev->pdev) ||
1614             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1615                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1616
1617                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1618                 MLX5_SET(mbox_out, out, status, status);
1619                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1620                 return err;
1621         }
1622
1623         pages_queue = is_manage_pages(in);
1624         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1625
1626         inb = alloc_msg(dev, in_size, gfp);
1627         if (IS_ERR(inb)) {
1628                 err = PTR_ERR(inb);
1629                 return err;
1630         }
1631
1632         token = alloc_token(&dev->cmd);
1633
1634         err = mlx5_copy_to_msg(inb, in, in_size, token);
1635         if (err) {
1636                 mlx5_core_warn(dev, "err %d\n", err);
1637                 goto out_in;
1638         }
1639
1640         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1641         if (IS_ERR(outb)) {
1642                 err = PTR_ERR(outb);
1643                 goto out_in;
1644         }
1645
1646         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1647                               pages_queue, &status, token, force_polling);
1648         if (err)
1649                 goto out_out;
1650
1651         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1652         if (status) {
1653                 err = status_to_err(status);
1654                 goto out_out;
1655         }
1656
1657         if (!callback)
1658                 err = mlx5_copy_from_msg(out, outb, out_size);
1659
1660 out_out:
1661         if (!callback)
1662                 mlx5_free_cmd_msg(dev, outb);
1663
1664 out_in:
1665         if (!callback)
1666                 free_msg(dev, inb);
1667         return err;
1668 }
1669
1670 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1671                   int out_size)
1672 {
1673         int err;
1674
1675         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1676         return err ? : mlx5_cmd_check(dev, in, out);
1677 }
1678 EXPORT_SYMBOL(mlx5_cmd_exec);
1679
1680 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1681                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1682                      void *context)
1683 {
1684         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1685                         false);
1686 }
1687 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1688
1689 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1690                           void *out, int out_size)
1691 {
1692         int err;
1693
1694         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1695
1696         return err ? : mlx5_cmd_check(dev, in, out);
1697 }
1698 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1699
1700 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1701 {
1702         struct cmd_msg_cache *ch;
1703         struct mlx5_cmd_msg *msg;
1704         struct mlx5_cmd_msg *n;
1705         int i;
1706
1707         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1708                 ch = &dev->cmd.cache[i];
1709                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1710                         list_del(&msg->list);
1711                         mlx5_free_cmd_msg(dev, msg);
1712                 }
1713         }
1714 }
1715
1716 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1717         512, 32, 16, 8, 2
1718 };
1719
1720 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1721         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1722         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1723         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1724         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1725         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1726 };
1727
1728 static void create_msg_cache(struct mlx5_core_dev *dev)
1729 {
1730         struct mlx5_cmd *cmd = &dev->cmd;
1731         struct cmd_msg_cache *ch;
1732         struct mlx5_cmd_msg *msg;
1733         int i;
1734         int k;
1735
1736         /* Initialize and fill the caches with initial entries */
1737         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1738                 ch = &cmd->cache[k];
1739                 spin_lock_init(&ch->lock);
1740                 INIT_LIST_HEAD(&ch->head);
1741                 ch->num_ent = cmd_cache_num_ent[k];
1742                 ch->max_inbox_size = cmd_cache_ent_size[k];
1743                 for (i = 0; i < ch->num_ent; i++) {
1744                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1745                                                  ch->max_inbox_size, 0);
1746                         if (IS_ERR(msg))
1747                                 break;
1748                         msg->parent = ch;
1749                         list_add_tail(&msg->list, &ch->head);
1750                 }
1751         }
1752 }
1753
1754 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1755 {
1756         struct device *ddev = &dev->pdev->dev;
1757
1758         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1759                                                  &cmd->alloc_dma, GFP_KERNEL);
1760         if (!cmd->cmd_alloc_buf)
1761                 return -ENOMEM;
1762
1763         /* make sure it is aligned to 4K */
1764         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1765                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1766                 cmd->dma = cmd->alloc_dma;
1767                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1768                 return 0;
1769         }
1770
1771         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1772                           cmd->alloc_dma);
1773         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1774                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1775                                                  &cmd->alloc_dma, GFP_KERNEL);
1776         if (!cmd->cmd_alloc_buf)
1777                 return -ENOMEM;
1778
1779         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1780         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1781         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1782         return 0;
1783 }
1784
1785 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1786 {
1787         struct device *ddev = &dev->pdev->dev;
1788
1789         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1790                           cmd->alloc_dma);
1791 }
1792
1793 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1794 {
1795         int size = sizeof(struct mlx5_cmd_prot_block);
1796         int align = roundup_pow_of_two(size);
1797         struct mlx5_cmd *cmd = &dev->cmd;
1798         u32 cmd_h, cmd_l;
1799         u16 cmd_if_rev;
1800         int err;
1801         int i;
1802
1803         memset(cmd, 0, sizeof(*cmd));
1804         cmd_if_rev = cmdif_rev(dev);
1805         if (cmd_if_rev != CMD_IF_REV) {
1806                 dev_err(&dev->pdev->dev,
1807                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1808                         CMD_IF_REV, cmd_if_rev);
1809                 return -EINVAL;
1810         }
1811
1812         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1813                                     0);
1814         if (!cmd->pool)
1815                 return -ENOMEM;
1816
1817         err = alloc_cmd_page(dev, cmd);
1818         if (err)
1819                 goto err_free_pool;
1820
1821         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1822         cmd->log_sz = cmd_l >> 4 & 0xf;
1823         cmd->log_stride = cmd_l & 0xf;
1824         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1825                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1826                         1 << cmd->log_sz);
1827                 err = -EINVAL;
1828                 goto err_free_page;
1829         }
1830
1831         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1832                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1833                 err = -EINVAL;
1834                 goto err_free_page;
1835         }
1836
1837         cmd->checksum_disabled = 1;
1838         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1839         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1840
1841         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1842         if (cmd->cmdif_rev > CMD_IF_REV) {
1843                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1844                         CMD_IF_REV, cmd->cmdif_rev);
1845                 err = -EOPNOTSUPP;
1846                 goto err_free_page;
1847         }
1848
1849         spin_lock_init(&cmd->alloc_lock);
1850         spin_lock_init(&cmd->token_lock);
1851         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1852                 spin_lock_init(&cmd->stats[i].lock);
1853
1854         sema_init(&cmd->sem, cmd->max_reg_cmds);
1855         sema_init(&cmd->pages_sem, 1);
1856
1857         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1858         cmd_l = (u32)(cmd->dma);
1859         if (cmd_l & 0xfff) {
1860                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1861                 err = -ENOMEM;
1862                 goto err_free_page;
1863         }
1864
1865         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1866         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1867
1868         /* Make sure firmware sees the complete address before we proceed */
1869         wmb();
1870
1871         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1872
1873         cmd->mode = CMD_MODE_POLLING;
1874
1875         create_msg_cache(dev);
1876
1877         set_wqname(dev);
1878         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1879         if (!cmd->wq) {
1880                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1881                 err = -ENOMEM;
1882                 goto err_cache;
1883         }
1884
1885         err = create_debugfs_files(dev);
1886         if (err) {
1887                 err = -ENOMEM;
1888                 goto err_wq;
1889         }
1890
1891         return 0;
1892
1893 err_wq:
1894         destroy_workqueue(cmd->wq);
1895
1896 err_cache:
1897         destroy_msg_cache(dev);
1898
1899 err_free_page:
1900         free_cmd_page(dev, cmd);
1901
1902 err_free_pool:
1903         dma_pool_destroy(cmd->pool);
1904
1905         return err;
1906 }
1907 EXPORT_SYMBOL(mlx5_cmd_init);
1908
1909 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1910 {
1911         struct mlx5_cmd *cmd = &dev->cmd;
1912
1913         clean_debug_files(dev);
1914         destroy_workqueue(cmd->wq);
1915         destroy_msg_cache(dev);
1916         free_cmd_page(dev, cmd);
1917         dma_pool_destroy(cmd->pool);
1918 }
1919 EXPORT_SYMBOL(mlx5_cmd_cleanup);