drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <net/busy_poll.h>
  38 #include <net/ip6_checksum.h>
  39 #include <net/page_pool.h>
  40 #include <net/inet_ecn.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/tls_rxtx.h"
  48 #include "lib/clock.h"
  49 #include "en/xdp.h"
  50
  51 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  52 {
  53         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  54 }
  55
  56 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  57                                        void *data)
  58 {
  59         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
  60
  61         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  62 }
  63
  64 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  65                                          struct mlx5e_cq *cq, u32 cqcc)
  66 {
  67         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  68         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  69         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  70         rq->stats->cqe_compress_blks++;
  71 }
  72
  73 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  74 {
  75         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  76         cq->mini_arr_idx = 0;
  77 }
  78
  79 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  80 {
  81         struct mlx5_cqwq *wq = &cq->wq;
  82
  83         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  84         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  85         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  86         u32 ci_top = min_t(u32, wq_sz, ci + n);
  87
  88         for (; ci < ci_top; ci++, n--) {
  89                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  90
  91                 cqe->op_own = op_own;
  92         }
  93
  94         if (unlikely(ci == wq_sz)) {
  95                 op_own = !op_own;
  96                 for (ci = 0; ci < n; ci++) {
  97                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  98
  99                         cqe->op_own = op_own;
 100                 }
 101         }
 102 }
 103
 104 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 105                                         struct mlx5e_cq *cq, u32 cqcc)
 106 {
 107         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 108         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 109         cq->title.op_own      &= 0xf0;
 110         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 111         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 112
 113         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 114                 cq->decmprs_wqe_counter +=
 115                         mpwrq_get_cqe_consumed_strides(&cq->title);
 116         else
 117                 cq->decmprs_wqe_counter =
 118                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
 119 }
 120
 121 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 122                                                 struct mlx5e_cq *cq, u32 cqcc)
 123 {
 124         mlx5e_decompress_cqe(rq, cq, cqcc);
 125         cq->title.rss_hash_type   = 0;
 126         cq->title.rss_hash_result = 0;
 127 }
 128
 129 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 130                                              struct mlx5e_cq *cq,
 131                                              int update_owner_only,
 132                                              int budget_rem)
 133 {
 134         u32 cqcc = cq->wq.cc + update_owner_only;
 135         u32 cqe_count;
 136         u32 i;
 137
 138         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 139
 140         for (i = update_owner_only; i < cqe_count;
 141              i++, cq->mini_arr_idx++, cqcc++) {
 142                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 143                         mlx5e_read_mini_arr_slot(cq, cqcc);
 144
 145                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 146                 rq->handle_rx_cqe(rq, &cq->title);
 147         }
 148         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 149         cq->wq.cc = cqcc;
 150         cq->decmprs_left -= cqe_count;
 151         rq->stats->cqe_compress_pkts += cqe_count;
 152
 153         return cqe_count;
 154 }
 155
 156 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 157                                               struct mlx5e_cq *cq,
 158                                               int budget_rem)
 159 {
 160         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 161         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 162         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 163         rq->handle_rx_cqe(rq, &cq->title);
 164         cq->mini_arr_idx++;
 165
 166         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 167 }
 168
 169 static inline bool mlx5e_page_is_reserved(struct page *page)
 170 {
 171         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 172 }
 173
 174 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 175                                       struct mlx5e_dma_info *dma_info)
 176 {
 177         struct mlx5e_page_cache *cache = &rq->page_cache;
 178         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 179         struct mlx5e_rq_stats *stats = rq->stats;
 180
 181         if (tail_next == cache->head) {
 182                 stats->cache_full++;
 183                 return false;
 184         }
 185
 186         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 187                 stats->cache_waive++;
 188                 return false;
 189         }
 190
 191         cache->page_cache[cache->tail] = *dma_info;
 192         cache->tail = tail_next;
 193         return true;
 194 }
 195
 196 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 197                                       struct mlx5e_dma_info *dma_info)
 198 {
 199         struct mlx5e_page_cache *cache = &rq->page_cache;
 200         struct mlx5e_rq_stats *stats = rq->stats;
 201
 202         if (unlikely(cache->head == cache->tail)) {
 203                 stats->cache_empty++;
 204                 return false;
 205         }
 206
 207         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 208                 stats->cache_busy++;
 209                 return false;
 210         }
 211
 212         *dma_info = cache->page_cache[cache->head];
 213         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 214         stats->cache_reuse++;
 215
 216         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 217                                    PAGE_SIZE,
 218                                    DMA_FROM_DEVICE);
 219         return true;
 220 }
 221
 222 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 223                                           struct mlx5e_dma_info *dma_info)
 224 {
 225         if (mlx5e_rx_cache_get(rq, dma_info))
 226                 return 0;
 227
 228         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 229         if (unlikely(!dma_info->page))
 230                 return -ENOMEM;
 231
 232         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 233                                       PAGE_SIZE, rq->buff.map_dir);
 234         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 235                 put_page(dma_info->page);
 236                 dma_info->page = NULL;
 237                 return -ENOMEM;
 238         }
 239
 240         return 0;
 241 }
 242
 243 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 244 {
 245         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 246 }
 247
 248 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 249                         bool recycle)
 250 {
 251         if (likely(recycle)) {
 252                 if (mlx5e_rx_cache_put(rq, dma_info))
 253                         return;
 254
 255                 mlx5e_page_dma_unmap(rq, dma_info);
 256                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 257         } else {
 258                 mlx5e_page_dma_unmap(rq, dma_info);
 259                 put_page(dma_info->page);
 260         }
 261 }
 262
 263 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 264                                     struct mlx5e_wqe_frag_info *frag)
 265 {
 266         int err = 0;
 267
 268         if (!frag->offset)
 269                 /* On first frag (offset == 0), replenish page (dma_info actually).
 270                  * Other frags that point to the same dma_info (with a different
 271                  * offset) should just use the new one without replenishing again
 272                  * by themselves.
 273                  */
 274                 err = mlx5e_page_alloc_mapped(rq, frag->di);
 275
 276         return err;
 277 }
 278
 279 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 280                                      struct mlx5e_wqe_frag_info *frag,
 281                                      bool recycle)
 282 {
 283         if (frag->last_in_page)
 284                 mlx5e_page_release(rq, frag->di, recycle);
 285 }
 286
 287 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 288 {
 289         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 290 }
 291
 292 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 293                               u16 ix)
 294 {
 295         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 296         int err;
 297         int i;
 298
 299         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 300                 err = mlx5e_get_rx_frag(rq, frag);
 301                 if (unlikely(err))
 302                         goto free_frags;
 303
 304                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 305                                                 frag->offset + rq->buff.headroom);
 306         }
 307
 308         return 0;
 309
 310 free_frags:
 311         while (--i >= 0)
 312                 mlx5e_put_rx_frag(rq, --frag, true);
 313
 314         return err;
 315 }
 316
 317 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 318                                      struct mlx5e_wqe_frag_info *wi,
 319                                      bool recycle)
 320 {
 321         int i;
 322
 323         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 324                 mlx5e_put_rx_frag(rq, wi, recycle);
 325 }
 326
 327 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 328 {
 329         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 330
 331         mlx5e_free_rx_wqe(rq, wi, false);
 332 }
 333
 334 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 335 {
 336         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 337         int err;
 338         int i;
 339
 340         for (i = 0; i < wqe_bulk; i++) {
 341                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 342
 343                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 344                 if (unlikely(err))
 345                         goto free_wqes;
 346         }
 347
 348         return 0;
 349
 350 free_wqes:
 351         while (--i >= 0)
 352                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 353
 354         return err;
 355 }
 356
 357 static inline void
 358 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 359                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 360                    unsigned int truesize)
 361 {
 362         dma_sync_single_for_cpu(rq->pdev,
 363                                 di->addr + frag_offset,
 364                                 len, DMA_FROM_DEVICE);
 365         page_ref_inc(di->page);
 366         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 367                         di->page, frag_offset, len, truesize);
 368 }
 369
 370 static inline void
 371 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 372                       struct mlx5e_dma_info *dma_info,
 373                       int offset_from, int offset_to, u32 headlen)
 374 {
 375         const void *from = page_address(dma_info->page) + offset_from;
 376         /* Aligning len to sizeof(long) optimizes memcpy performance */
 377         unsigned int len = ALIGN(headlen, sizeof(long));
 378
 379         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 380                                 DMA_FROM_DEVICE);
 381         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
 382 }
 383
 384 static inline void
 385 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 386                             struct sk_buff *skb,
 387                             struct mlx5e_dma_info *dma_info,
 388                             u32 offset, u32 headlen)
 389 {
 390         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 391
 392         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
 393
 394         if (unlikely(offset + headlen > PAGE_SIZE)) {
 395                 dma_info++;
 396                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
 397                                       headlen - headlen_pg);
 398         }
 399 }
 400
 401 static void
 402 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 403 {
 404         const bool no_xdp_xmit =
 405                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 406         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 407         int i;
 408
 409         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 410                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 411                         mlx5e_page_release(rq, &dma_info[i], recycle);
 412 }
 413
 414 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 415 {
 416         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 417         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 418
 419         rq->mpwqe.umr_in_progress = false;
 420
 421         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 422
 423         /* ensure wqes are visible to device before updating doorbell record */
 424         dma_wmb();
 425
 426         mlx5_wq_ll_update_db_record(wq);
 427 }
 428
 429 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
 430 {
 431         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
 432 }
 433
 434 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 435                                               struct mlx5_wq_cyc *wq,
 436                                               u16 pi, u16 nnops)
 437 {
 438         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 439
 440         edge_wi = wi + nnops;
 441
 442         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 443         for (; wi < edge_wi; wi++) {
 444                 wi->opcode = MLX5_OPCODE_NOP;
 445                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 446         }
 447 }
 448
 449 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 450 {
 451         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 452         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 453         struct mlx5e_icosq *sq = &rq->channel->icosq;
 454         struct mlx5_wq_cyc *wq = &sq->wq;
 455         struct mlx5e_umr_wqe *umr_wqe;
 456         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 457         u16 pi, contig_wqebbs_room;
 458         int err;
 459         int i;
 460
 461         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 462         contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
 463         if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
 464                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
 465                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 466         }
 467
 468         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 469         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
 470                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
 471                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
 472
 473         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 474                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 475                 if (unlikely(err))
 476                         goto err_unmap;
 477                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 478         }
 479
 480         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 481         wi->consumed_strides = 0;
 482
 483         rq->mpwqe.umr_in_progress = true;
 484
 485         umr_wqe->ctrl.opmod_idx_opcode =
 486                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 487                             MLX5_OPCODE_UMR);
 488         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 489
 490         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 491         sq->pc += MLX5E_UMR_WQEBBS;
 492         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
 493
 494         return 0;
 495
 496 err_unmap:
 497         while (--i >= 0) {
 498                 dma_info--;
 499                 mlx5e_page_release(rq, dma_info, true);
 500         }
 501         rq->stats->buff_alloc_err++;
 502
 503         return err;
 504 }
 505
 506 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 507 {
 508         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 509         /* Don't recycle, this function is called on rq/netdev close */
 510         mlx5e_free_rx_mpwqe(rq, wi, false);
 511 }
 512
 513 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 514 {
 515         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 516         u8 wqe_bulk;
 517         int err;
 518
 519         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 520                 return false;
 521
 522         wqe_bulk = rq->wqe.info.wqe_bulk;
 523
 524         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 525                 return false;
 526
 527         do {
 528                 u16 head = mlx5_wq_cyc_get_head(wq);
 529
 530                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 531                 if (unlikely(err)) {
 532                         rq->stats->buff_alloc_err++;
 533                         break;
 534                 }
 535
 536                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 537         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 538
 539         /* ensure wqes are visible to device before updating doorbell record */
 540         dma_wmb();
 541
 542         mlx5_wq_cyc_update_db_record(wq);
 543
 544         return !!err;
 545 }
 546
 547 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 548                                              struct mlx5e_icosq *sq,
 549                                              struct mlx5e_rq *rq,
 550                                              struct mlx5_cqe64 *cqe)
 551 {
 552         struct mlx5_wq_cyc *wq = &sq->wq;
 553         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
 554         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 555
 556         mlx5_cqwq_pop(&cq->wq);
 557
 558         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 559                 netdev_WARN_ONCE(cq->channel->netdev,
 560                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 561                 return;
 562         }
 563
 564         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 565                 mlx5e_post_rx_mpwqe(rq);
 566                 return;
 567         }
 568
 569         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 570                 netdev_WARN_ONCE(cq->channel->netdev,
 571                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 572 }
 573
 574 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 575 {
 576         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 577         struct mlx5_cqe64 *cqe;
 578
 579         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 580                 return;
 581
 582         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 583         if (likely(!cqe))
 584                 return;
 585
 586         /* by design, there's only a single cqe */
 587         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 588
 589         mlx5_cqwq_update_db_record(&cq->wq);
 590 }
 591
 592 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 593 {
 594         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 595
 596         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 597                 return false;
 598
 599         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 600
 601         if (mlx5_wq_ll_is_full(wq))
 602                 return false;
 603
 604         if (!rq->mpwqe.umr_in_progress)
 605                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 606         else
 607                 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
 608
 609         return false;
 610 }
 611
 612 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 613 {
 614         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 615         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 616                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 617
 618         tcp->check                      = 0;
 619         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 620
 621         if (tcp_ack) {
 622                 tcp->ack                = 1;
 623                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 624                 tcp->window             = cqe->lro_tcp_win;
 625         }
 626 }
 627
 628 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 629                                  u32 cqe_bcnt)
 630 {
 631         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 632         struct tcphdr   *tcp;
 633         int network_depth = 0;
 634         __wsum check;
 635         __be16 proto;
 636         u16 tot_len;
 637         void *ip_p;
 638
 639         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 640
 641         tot_len = cqe_bcnt - network_depth;
 642         ip_p = skb->data + network_depth;
 643
 644         if (proto == htons(ETH_P_IP)) {
 645                 struct iphdr *ipv4 = ip_p;
 646
 647                 tcp = ip_p + sizeof(struct iphdr);
 648                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 649
 650                 ipv4->ttl               = cqe->lro_min_ttl;
 651                 ipv4->tot_len           = cpu_to_be16(tot_len);
 652                 ipv4->check             = 0;
 653                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 654                                                        ipv4->ihl);
 655
 656                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 657                 check = csum_partial(tcp, tcp->doff * 4,
 658                                      csum_unfold((__force __sum16)cqe->check_sum));
 659                 /* Almost done, don't forget the pseudo header */
 660                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 661                                                tot_len - sizeof(struct iphdr),
 662                                                IPPROTO_TCP, check);
 663         } else {
 664                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 665                 struct ipv6hdr *ipv6 = ip_p;
 666
 667                 tcp = ip_p + sizeof(struct ipv6hdr);
 668                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 669
 670                 ipv6->hop_limit         = cqe->lro_min_ttl;
 671                 ipv6->payload_len       = cpu_to_be16(payload_len);
 672
 673                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 674                 check = csum_partial(tcp, tcp->doff * 4,
 675                                      csum_unfold((__force __sum16)cqe->check_sum));
 676                 /* Almost done, don't forget the pseudo header */
 677                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 678                                              IPPROTO_TCP, check);
 679         }
 680 }
 681
 682 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 683                                       struct sk_buff *skb)
 684 {
 685         u8 cht = cqe->rss_hash_type;
 686         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 687                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 688                                             PKT_HASH_TYPE_NONE;
 689         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 690 }
 691
 692 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 693                                         __be16 *proto)
 694 {
 695         *proto = ((struct ethhdr *)skb->data)->h_proto;
 696         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 697
 698         if (*proto == htons(ETH_P_IP))
 699                 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
 700
 701         if (*proto == htons(ETH_P_IPV6))
 702                 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
 703
 704         return false;
 705 }
 706
 707 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 708 {
 709         int network_depth = 0;
 710         __be16 proto;
 711         void *ip;
 712         int rc;
 713
 714         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 715                 return;
 716
 717         ip = skb->data + network_depth;
 718         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 719                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 720
 721         rq->stats->ecn_mark += !!rc;
 722 }
 723
 724 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 725 {
 726         void *ip_p = skb->data + network_depth;
 727
 728         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 729                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 730 }
 731
 732 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 733
 734 #define MAX_PADDING 8
 735
 736 static void
 737 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
 738                        struct mlx5e_rq_stats *stats)
 739 {
 740         stats->csum_complete_tail_slow++;
 741         skb->csum = csum_block_add(skb->csum,
 742                                    skb_checksum(skb, offset, len, 0),
 743                                    offset);
 744 }
 745
 746 static void
 747 tail_padding_csum(struct sk_buff *skb, int offset,
 748                   struct mlx5e_rq_stats *stats)
 749 {
 750         u8 tail_padding[MAX_PADDING];
 751         int len = skb->len - offset;
 752         void *tail;
 753
 754         if (unlikely(len > MAX_PADDING)) {
 755                 tail_padding_csum_slow(skb, offset, len, stats);
 756                 return;
 757         }
 758
 759         tail = skb_header_pointer(skb, offset, len, tail_padding);
 760         if (unlikely(!tail)) {
 761                 tail_padding_csum_slow(skb, offset, len, stats);
 762                 return;
 763         }
 764
 765         stats->csum_complete_tail++;
 766         skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
 767 }
 768
 769 static void
 770 mlx5e_skb_padding_csum(struct sk_buff *skb, int network_depth, __be16 proto,
 771                        struct mlx5e_rq_stats *stats)
 772 {
 773         struct ipv6hdr *ip6;
 774         struct iphdr   *ip4;
 775         int pkt_len;
 776
 777         switch (proto) {
 778         case htons(ETH_P_IP):
 779                 ip4 = (struct iphdr *)(skb->data + network_depth);
 780                 pkt_len = network_depth + ntohs(ip4->tot_len);
 781                 break;
 782         case htons(ETH_P_IPV6):
 783                 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
 784                 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
 785                 break;
 786         default:
 787                 return;
 788         }
 789
 790         if (likely(pkt_len >= skb->len))
 791                 return;
 792
 793         tail_padding_csum(skb, pkt_len, stats);
 794 }
 795
 796 static inline void mlx5e_handle_csum(struct net_device *netdev,
 797                                      struct mlx5_cqe64 *cqe,
 798                                      struct mlx5e_rq *rq,
 799                                      struct sk_buff *skb,
 800                                      bool   lro)
 801 {
 802         struct mlx5e_rq_stats *stats = rq->stats;
 803         int network_depth = 0;
 804         __be16 proto;
 805
 806         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 807                 goto csum_none;
 808
 809         if (lro) {
 810                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 811                 stats->csum_unnecessary++;
 812                 return;
 813         }
 814
 815         /* True when explicitly set via priv flag, or XDP prog is loaded */
 816         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 817                 goto csum_unnecessary;
 818
 819         /* CQE csum doesn't cover padding octets in short ethernet
 820          * frames. And the pad field is appended prior to calculating
 821          * and appending the FCS field.
 822          *
 823          * Detecting these padded frames requires to verify and parse
 824          * IP headers, so we simply force all those small frames to be
 825          * CHECKSUM_UNNECESSARY even if they are not padded.
 826          */
 827         if (short_frame(skb->len))
 828                 goto csum_unnecessary;
 829
 830         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 831                 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
 832                         goto csum_unnecessary;
 833
 834                 skb->ip_summed = CHECKSUM_COMPLETE;
 835                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 836                 if (network_depth > ETH_HLEN)
 837                         /* CQE csum is calculated from the IP header and does
 838                          * not cover VLAN headers (if present). This will add
 839                          * the checksum manually.
 840                          */
 841                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 842                                                  network_depth - ETH_HLEN,
 843                                                  skb->csum);
 844
 845                 mlx5e_skb_padding_csum(skb, network_depth, proto, stats);
 846                 stats->csum_complete++;
 847                 return;
 848         }
 849
 850 csum_unnecessary:
 851         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 852                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 853                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 854                 if (cqe_is_tunneled(cqe)) {
 855                         skb->csum_level = 1;
 856                         skb->encapsulation = 1;
 857                         stats->csum_unnecessary_inner++;
 858                         return;
 859                 }
 860                 stats->csum_unnecessary++;
 861                 return;
 862         }
 863 csum_none:
 864         skb->ip_summed = CHECKSUM_NONE;
 865         stats->csum_none++;
 866 }
 867
 868 #define MLX5E_CE_BIT_MASK 0x80
 869
 870 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 871                                       u32 cqe_bcnt,
 872                                       struct mlx5e_rq *rq,
 873                                       struct sk_buff *skb)
 874 {
 875         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 876         struct mlx5e_rq_stats *stats = rq->stats;
 877         struct net_device *netdev = rq->netdev;
 878
 879         skb->mac_len = ETH_HLEN;
 880
 881 #ifdef CONFIG_MLX5_EN_TLS
 882         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
 883 #endif
 884
 885         if (lro_num_seg > 1) {
 886                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 887                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 888                 /* Subtract one since we already counted this as one
 889                  * "regular" packet in mlx5e_complete_rx_cqe()
 890                  */
 891                 stats->packets += lro_num_seg - 1;
 892                 stats->lro_packets++;
 893                 stats->lro_bytes += cqe_bcnt;
 894         }
 895
 896         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 897                 skb_hwtstamps(skb)->hwtstamp =
 898                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 899
 900         skb_record_rx_queue(skb, rq->ix);
 901
 902         if (likely(netdev->features & NETIF_F_RXHASH))
 903                 mlx5e_skb_set_hash(cqe, skb);
 904
 905         if (cqe_has_vlan(cqe)) {
 906                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 907                                        be16_to_cpu(cqe->vlan_info));
 908                 stats->removed_vlan_packets++;
 909         }
 910
 911         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 912
 913         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 914         /* checking CE bit in cqe - MSB in ml_path field */
 915         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
 916                 mlx5e_enable_ecn(rq, skb);
 917
 918         skb->protocol = eth_type_trans(skb, netdev);
 919 }
 920
 921 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 922                                          struct mlx5_cqe64 *cqe,
 923                                          u32 cqe_bcnt,
 924                                          struct sk_buff *skb)
 925 {
 926         struct mlx5e_rq_stats *stats = rq->stats;
 927
 928         stats->packets++;
 929         stats->bytes += cqe_bcnt;
 930         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 931 }
 932
 933 static inline
 934 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 935                                        u32 frag_size, u16 headroom,
 936                                        u32 cqe_bcnt)
 937 {
 938         struct sk_buff *skb = build_skb(va, frag_size);
 939
 940         if (unlikely(!skb)) {
 941                 rq->stats->buff_alloc_err++;
 942                 return NULL;
 943         }
 944
 945         skb_reserve(skb, headroom);
 946         skb_put(skb, cqe_bcnt);
 947
 948         return skb;
 949 }
 950
 951 struct sk_buff *
 952 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 953                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 954 {
 955         struct mlx5e_dma_info *di = wi->di;
 956         u16 rx_headroom = rq->buff.headroom;
 957         struct sk_buff *skb;
 958         void *va, *data;
 959         bool consumed;
 960         u32 frag_size;
 961
 962         va             = page_address(di->page) + wi->offset;
 963         data           = va + rx_headroom;
 964         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 965
 966         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
 967                                       frag_size, DMA_FROM_DEVICE);
 968         prefetchw(va); /* xdp_frame data area */
 969         prefetch(data);
 970
 971         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 972                 rq->stats->wqe_err++;
 973                 return NULL;
 974         }
 975
 976         rcu_read_lock();
 977         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 978         rcu_read_unlock();
 979         if (consumed)
 980                 return NULL; /* page/packet was consumed by XDP */
 981
 982         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
 983         if (unlikely(!skb))
 984                 return NULL;
 985
 986         /* queue up for recycling/reuse */
 987         page_ref_inc(di->page);
 988
 989         return skb;
 990 }
 991
 992 struct sk_buff *
 993 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 994                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 995 {
 996         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 997         struct mlx5e_wqe_frag_info *head_wi = wi;
 998         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
 999         u16 frag_headlen = headlen;
1000         u16 byte_cnt     = cqe_bcnt - headlen;
1001         struct sk_buff *skb;
1002
1003         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1004                 rq->stats->wqe_err++;
1005                 return NULL;
1006         }
1007
1008         /* XDP is not supported in this configuration, as incoming packets
1009          * might spread among multiple pages.
1010          */
1011         skb = napi_alloc_skb(rq->cq.napi,
1012                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1013         if (unlikely(!skb)) {
1014                 rq->stats->buff_alloc_err++;
1015                 return NULL;
1016         }
1017
1018         prefetchw(skb->data);
1019
1020         while (byte_cnt) {
1021                 u16 frag_consumed_bytes =
1022                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1023
1024                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1025                                    frag_consumed_bytes, frag_info->frag_stride);
1026                 byte_cnt -= frag_consumed_bytes;
1027                 frag_headlen = 0;
1028                 frag_info++;
1029                 wi++;
1030         }
1031
1032         /* copy header */
1033         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
1034                               0, headlen);
1035         /* skb linear part was allocated with headlen and aligned to long */
1036         skb->tail += headlen;
1037         skb->len  += headlen;
1038
1039         return skb;
1040 }
1041
1042 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1043 {
1044         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1045         struct mlx5e_wqe_frag_info *wi;
1046         struct sk_buff *skb;
1047         u32 cqe_bcnt;
1048         u16 ci;
1049
1050         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1051         wi       = get_frag(rq, ci);
1052         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1053
1054         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1055         if (!skb) {
1056                 /* probably for XDP */
1057                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1058                         /* do not return page to cache,
1059                          * it will be returned on XDP_TX completion.
1060                          */
1061                         goto wq_cyc_pop;
1062                 }
1063                 goto free_wqe;
1064         }
1065
1066         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1067         napi_gro_receive(rq->cq.napi, skb);
1068
1069 free_wqe:
1070         mlx5e_free_rx_wqe(rq, wi, true);
1071 wq_cyc_pop:
1072         mlx5_wq_cyc_pop(wq);
1073 }
1074
1075 #ifdef CONFIG_MLX5_ESWITCH
1076 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1077 {
1078         struct net_device *netdev = rq->netdev;
1079         struct mlx5e_priv *priv = netdev_priv(netdev);
1080         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1081         struct mlx5_eswitch_rep *rep = rpriv->rep;
1082         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1083         struct mlx5e_wqe_frag_info *wi;
1084         struct sk_buff *skb;
1085         u32 cqe_bcnt;
1086         u16 ci;
1087
1088         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1089         wi       = get_frag(rq, ci);
1090         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1091
1092         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1093         if (!skb) {
1094                 /* probably for XDP */
1095                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1096                         /* do not return page to cache,
1097                          * it will be returned on XDP_TX completion.
1098                          */
1099                         goto wq_cyc_pop;
1100                 }
1101                 goto free_wqe;
1102         }
1103
1104         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1105
1106         if (rep->vlan && skb_vlan_tag_present(skb))
1107                 skb_vlan_pop(skb);
1108
1109         napi_gro_receive(rq->cq.napi, skb);
1110
1111 free_wqe:
1112         mlx5e_free_rx_wqe(rq, wi, true);
1113 wq_cyc_pop:
1114         mlx5_wq_cyc_pop(wq);
1115 }
1116 #endif
1117
1118 struct sk_buff *
1119 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1120                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1121 {
1122         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1123         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1124         u32 frag_offset    = head_offset + headlen;
1125         u32 byte_cnt       = cqe_bcnt - headlen;
1126         struct mlx5e_dma_info *head_di = di;
1127         struct sk_buff *skb;
1128
1129         skb = napi_alloc_skb(rq->cq.napi,
1130                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1131         if (unlikely(!skb)) {
1132                 rq->stats->buff_alloc_err++;
1133                 return NULL;
1134         }
1135
1136         prefetchw(skb->data);
1137
1138         if (unlikely(frag_offset >= PAGE_SIZE)) {
1139                 di++;
1140                 frag_offset -= PAGE_SIZE;
1141         }
1142
1143         while (byte_cnt) {
1144                 u32 pg_consumed_bytes =
1145                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1146                 unsigned int truesize =
1147                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1148
1149                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1150                                    pg_consumed_bytes, truesize);
1151                 byte_cnt -= pg_consumed_bytes;
1152                 frag_offset = 0;
1153                 di++;
1154         }
1155         /* copy header */
1156         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1157                                     head_offset, headlen);
1158         /* skb linear part was allocated with headlen and aligned to long */
1159         skb->tail += headlen;
1160         skb->len  += headlen;
1161
1162         return skb;
1163 }
1164
1165 struct sk_buff *
1166 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1167                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1168 {
1169         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1170         u16 rx_headroom = rq->buff.headroom;
1171         u32 cqe_bcnt32 = cqe_bcnt;
1172         struct sk_buff *skb;
1173         void *va, *data;
1174         u32 frag_size;
1175         bool consumed;
1176
1177         /* Check packet size. Note LRO doesn't use linear SKB */
1178         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1179                 rq->stats->oversize_pkts_sw_drop++;
1180                 return NULL;
1181         }
1182
1183         va             = page_address(di->page) + head_offset;
1184         data           = va + rx_headroom;
1185         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1186
1187         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1188                                       frag_size, DMA_FROM_DEVICE);
1189         prefetchw(va); /* xdp_frame data area */
1190         prefetch(data);
1191
1192         rcu_read_lock();
1193         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1194         rcu_read_unlock();
1195         if (consumed) {
1196                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1197                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1198                 return NULL; /* page/packet was consumed by XDP */
1199         }
1200
1201         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1202         if (unlikely(!skb))
1203                 return NULL;
1204
1205         /* queue up for recycling/reuse */
1206         page_ref_inc(di->page);
1207
1208         return skb;
1209 }
1210
1211 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1212 {
1213         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1214         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1215         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1216         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1217         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1218         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1219         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1220         struct mlx5e_rx_wqe_ll *wqe;
1221         struct mlx5_wq_ll *wq;
1222         struct sk_buff *skb;
1223         u16 cqe_bcnt;
1224
1225         wi->consumed_strides += cstrides;
1226
1227         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1228                 rq->stats->wqe_err++;
1229                 goto mpwrq_cqe_out;
1230         }
1231
1232         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1233                 struct mlx5e_rq_stats *stats = rq->stats;
1234
1235                 stats->mpwqe_filler_cqes++;
1236                 stats->mpwqe_filler_strides += cstrides;
1237                 goto mpwrq_cqe_out;
1238         }
1239
1240         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1241
1242         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1243                                            page_idx);
1244         if (!skb)
1245                 goto mpwrq_cqe_out;
1246
1247         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1248         napi_gro_receive(rq->cq.napi, skb);
1249
1250 mpwrq_cqe_out:
1251         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1252                 return;
1253
1254         wq  = &rq->mpwqe.wq;
1255         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1256         mlx5e_free_rx_mpwqe(rq, wi, true);
1257         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1258 }
1259
1260 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1261 {
1262         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1263         struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
1264         struct mlx5_cqe64 *cqe;
1265         int work_done = 0;
1266
1267         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1268                 return 0;
1269
1270         if (cq->decmprs_left) {
1271                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1272                 if (cq->decmprs_left || work_done >= budget)
1273                         goto out;
1274         }
1275
1276         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1277         if (!cqe) {
1278                 if (unlikely(work_done))
1279                         goto out;
1280                 return 0;
1281         }
1282
1283         do {
1284                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1285                         work_done +=
1286                                 mlx5e_decompress_cqes_start(rq, cq,
1287                                                             budget - work_done);
1288                         continue;
1289                 }
1290
1291                 mlx5_cqwq_pop(&cq->wq);
1292
1293                 rq->handle_rx_cqe(rq, cqe);
1294         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1295
1296 out:
1297         if (xdpsq->doorbell) {
1298                 mlx5e_xmit_xdp_doorbell(xdpsq);
1299                 xdpsq->doorbell = false;
1300         }
1301
1302         if (xdpsq->redirect_flush) {
1303                 xdp_do_flush_map();
1304                 xdpsq->redirect_flush = false;
1305         }
1306
1307         mlx5_cqwq_update_db_record(&cq->wq);
1308
1309         /* ensure cq space is freed before enabling more cqes */
1310         wmb();
1311
1312         return work_done;
1313 }
1314
1315 #ifdef CONFIG_MLX5_CORE_IPOIB
1316
1317 #define MLX5_IB_GRH_SGID_OFFSET 8
1318 #define MLX5_IB_GRH_DGID_OFFSET 24
1319 #define MLX5_GID_SIZE           16
1320
1321 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1322                                          struct mlx5_cqe64 *cqe,
1323                                          u32 cqe_bcnt,
1324                                          struct sk_buff *skb)
1325 {
1326         struct mlx5e_rq_stats *stats = rq->stats;
1327         struct hwtstamp_config *tstamp;
1328         struct net_device *netdev;
1329         struct mlx5e_priv *priv;
1330         char *pseudo_header;
1331         u32 flags_rqpn;
1332         u32 qpn;
1333         u8 *dgid;
1334         u8 g;
1335
1336         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1337         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1338
1339         /* No mapping present, cannot process SKB. This might happen if a child
1340          * interface is going down while having unprocessed CQEs on parent RQ
1341          */
1342         if (unlikely(!netdev)) {
1343                 /* TODO: add drop counters support */
1344                 skb->dev = NULL;
1345                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1346                 return;
1347         }
1348
1349         priv = mlx5i_epriv(netdev);
1350         tstamp = &priv->tstamp;
1351
1352         flags_rqpn = be32_to_cpu(cqe->flags_rqpn);
1353         g = (flags_rqpn >> 28) & 3;
1354         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1355         if ((!g) || dgid[0] != 0xff)
1356                 skb->pkt_type = PACKET_HOST;
1357         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1358                 skb->pkt_type = PACKET_BROADCAST;
1359         else
1360                 skb->pkt_type = PACKET_MULTICAST;
1361
1362         /* Drop packets that this interface sent, ie multicast packets
1363          * that the HCA has replicated.
1364          */
1365         if (g && (qpn == (flags_rqpn & 0xffffff)) &&
1366             (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET,
1367                     MLX5_GID_SIZE) == 0)) {
1368                 skb->dev = NULL;
1369                 return;
1370         }
1371
1372         skb_pull(skb, MLX5_IB_GRH_BYTES);
1373
1374         skb->protocol = *((__be16 *)(skb->data));
1375
1376         if (netdev->features & NETIF_F_RXCSUM) {
1377                 skb->ip_summed = CHECKSUM_COMPLETE;
1378                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1379                 stats->csum_complete++;
1380         } else {
1381                 skb->ip_summed = CHECKSUM_NONE;
1382                 stats->csum_none++;
1383         }
1384
1385         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1386                 skb_hwtstamps(skb)->hwtstamp =
1387                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1388
1389         skb_record_rx_queue(skb, rq->ix);
1390
1391         if (likely(netdev->features & NETIF_F_RXHASH))
1392                 mlx5e_skb_set_hash(cqe, skb);
1393
1394         /* 20 bytes of ipoib header and 4 for encap existing */
1395         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1396         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1397         skb_reset_mac_header(skb);
1398         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1399
1400         skb->dev = netdev;
1401
1402         stats->packets++;
1403         stats->bytes += cqe_bcnt;
1404 }
1405
1406 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1407 {
1408         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1409         struct mlx5e_wqe_frag_info *wi;
1410         struct sk_buff *skb;
1411         u32 cqe_bcnt;
1412         u16 ci;
1413
1414         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1415         wi       = get_frag(rq, ci);
1416         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1417
1418         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1419         if (!skb)
1420                 goto wq_free_wqe;
1421
1422         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1423         if (unlikely(!skb->dev)) {
1424                 dev_kfree_skb_any(skb);
1425                 goto wq_free_wqe;
1426         }
1427         napi_gro_receive(rq->cq.napi, skb);
1428
1429 wq_free_wqe:
1430         mlx5e_free_rx_wqe(rq, wi, true);
1431         mlx5_wq_cyc_pop(wq);
1432 }
1433
1434 #endif /* CONFIG_MLX5_CORE_IPOIB */
1435
1436 #ifdef CONFIG_MLX5_EN_IPSEC
1437
1438 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1439 {
1440         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1441         struct mlx5e_wqe_frag_info *wi;
1442         struct sk_buff *skb;
1443         u32 cqe_bcnt;
1444         u16 ci;
1445
1446         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1447         wi       = get_frag(rq, ci);
1448         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1449
1450         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1451         if (unlikely(!skb)) {
1452                 /* a DROP, save the page-reuse checks */
1453                 mlx5e_free_rx_wqe(rq, wi, true);
1454                 goto wq_cyc_pop;
1455         }
1456         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1457         if (unlikely(!skb)) {
1458                 mlx5e_free_rx_wqe(rq, wi, true);
1459                 goto wq_cyc_pop;
1460         }
1461
1462         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1463         napi_gro_receive(rq->cq.napi, skb);
1464
1465         mlx5e_free_rx_wqe(rq, wi, true);
1466 wq_cyc_pop:
1467         mlx5_wq_cyc_pop(wq);
1468 }
1469
1470 #endif /* CONFIG_MLX5_EN_IPSEC */