2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/flow_dissector.h>
34 #include <net/sch_generic.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_skbedit.h>
38 #include <linux/mlx5/fs.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/rhashtable.h>
41 #include <net/switchdev.h>
42 #include <net/tc_act/tc_mirred.h>
43 #include <net/tc_act/tc_vlan.h>
44 #include <net/tc_act/tc_tunnel_key.h>
45 #include <net/tc_act/tc_pedit.h>
46 #include <net/tc_act/tc_csum.h>
47 #include <net/vxlan.h>
53 #include "lib/vxlan.h"
57 struct mlx5_nic_flow_attr {
63 struct mlx5_flow_table *hairpin_ft;
66 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
69 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
70 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
71 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
72 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
73 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
74 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
75 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
78 #define MLX5E_TC_MAX_SPLITS 1
80 struct mlx5e_tc_flow {
81 struct rhash_head node;
82 struct mlx5e_priv *priv;
85 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
86 struct list_head encap; /* flows sharing the same encap ID */
87 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
88 struct list_head hairpin; /* flows sharing the same hairpin */
90 struct mlx5_esw_flow_attr esw_attr[0];
91 struct mlx5_nic_flow_attr nic_attr[0];
95 struct mlx5e_tc_flow_parse_attr {
96 struct ip_tunnel_info tun_info;
97 struct mlx5_flow_spec spec;
98 int num_mod_hdr_actions;
99 int max_mod_hdr_actions;
100 void *mod_hdr_actions;
105 MLX5_HEADER_TYPE_VXLAN = 0x0,
106 MLX5_HEADER_TYPE_NVGRE = 0x1,
109 #define MLX5E_TC_TABLE_NUM_GROUPS 4
110 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
112 struct mlx5e_hairpin {
113 struct mlx5_hairpin *pair;
115 struct mlx5_core_dev *func_mdev;
116 struct mlx5e_priv *func_priv;
121 struct mlx5e_rqt indir_rqt;
122 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
123 struct mlx5e_ttc_table ttc;
126 struct mlx5e_hairpin_entry {
127 /* a node of a hash table which keeps all the hairpin entries */
128 struct hlist_node hairpin_hlist;
130 /* flows sharing the same hairpin */
131 struct list_head flows;
135 struct mlx5e_hairpin *hp;
143 struct mlx5e_mod_hdr_entry {
144 /* a node of a hash table which keeps all the mod_hdr entries */
145 struct hlist_node mod_hdr_hlist;
147 /* flows sharing the same mod_hdr entry */
148 struct list_head flows;
150 struct mod_hdr_key key;
155 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
157 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
159 return jhash(key->actions,
160 key->num_actions * MLX5_MH_ACT_SZ, 0);
163 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
164 struct mod_hdr_key *b)
166 if (a->num_actions != b->num_actions)
169 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
172 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
173 struct mlx5e_tc_flow *flow,
174 struct mlx5e_tc_flow_parse_attr *parse_attr)
176 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
177 int num_actions, actions_size, namespace, err;
178 struct mlx5e_mod_hdr_entry *mh;
179 struct mod_hdr_key key;
183 num_actions = parse_attr->num_mod_hdr_actions;
184 actions_size = MLX5_MH_ACT_SZ * num_actions;
186 key.actions = parse_attr->mod_hdr_actions;
187 key.num_actions = num_actions;
189 hash_key = hash_mod_hdr_info(&key);
191 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
192 namespace = MLX5_FLOW_NAMESPACE_FDB;
193 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
194 mod_hdr_hlist, hash_key) {
195 if (!cmp_mod_hdr_info(&mh->key, &key)) {
201 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
202 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
203 mod_hdr_hlist, hash_key) {
204 if (!cmp_mod_hdr_info(&mh->key, &key)) {
214 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
218 mh->key.actions = (void *)mh + sizeof(*mh);
219 memcpy(mh->key.actions, key.actions, actions_size);
220 mh->key.num_actions = num_actions;
221 INIT_LIST_HEAD(&mh->flows);
223 err = mlx5_modify_header_alloc(priv->mdev, namespace,
230 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
231 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
233 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
236 list_add(&flow->mod_hdr, &mh->flows);
237 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
238 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
240 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
249 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
250 struct mlx5e_tc_flow *flow)
252 struct list_head *next = flow->mod_hdr.next;
254 list_del(&flow->mod_hdr);
256 if (list_empty(next)) {
257 struct mlx5e_mod_hdr_entry *mh;
259 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
261 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
262 hash_del(&mh->mod_hdr_hlist);
268 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
270 struct net_device *netdev;
271 struct mlx5e_priv *priv;
273 netdev = __dev_get_by_index(net, ifindex);
274 priv = netdev_priv(netdev);
278 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
280 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
284 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
288 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
290 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
291 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
292 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
294 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
301 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
306 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
308 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
309 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
312 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
314 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
315 struct mlx5e_priv *priv = hp->func_priv;
316 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
318 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
321 for (i = 0; i < sz; i++) {
323 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
324 ix = mlx5e_bits_invert(i, ilog2(sz));
325 ix = indirection_rqt[ix];
326 rqn = hp->pair->rqn[ix];
327 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
331 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
333 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
334 struct mlx5e_priv *priv = hp->func_priv;
335 struct mlx5_core_dev *mdev = priv->mdev;
339 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
340 in = kvzalloc(inlen, GFP_KERNEL);
344 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
346 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
347 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
349 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
351 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
353 hp->indir_rqt.enabled = true;
359 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
361 struct mlx5e_priv *priv = hp->func_priv;
362 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
366 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
367 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
368 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
370 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
371 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
372 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
373 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
375 err = mlx5_core_create_tir(hp->func_mdev, in,
376 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
378 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
379 goto err_destroy_tirs;
385 for (i = 0; i < tt; i++)
386 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
390 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
394 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
395 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
398 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
399 struct ttc_params *ttc_params)
401 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
404 memset(ttc_params, 0, sizeof(*ttc_params));
406 ttc_params->any_tt_tirn = hp->tirn;
408 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
409 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
411 ft_attr->max_fte = MLX5E_NUM_TT;
412 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
413 ft_attr->prio = MLX5E_TC_PRIO;
416 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
418 struct mlx5e_priv *priv = hp->func_priv;
419 struct ttc_params ttc_params;
422 err = mlx5e_hairpin_create_indirect_rqt(hp);
426 err = mlx5e_hairpin_create_indirect_tirs(hp);
428 goto err_create_indirect_tirs;
430 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
431 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
433 goto err_create_ttc_table;
435 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
436 hp->num_channels, hp->ttc.ft.t->id);
440 err_create_ttc_table:
441 mlx5e_hairpin_destroy_indirect_tirs(hp);
442 err_create_indirect_tirs:
443 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
448 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
450 struct mlx5e_priv *priv = hp->func_priv;
452 mlx5e_destroy_ttc_table(priv, &hp->ttc);
453 mlx5e_hairpin_destroy_indirect_tirs(hp);
454 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
457 static struct mlx5e_hairpin *
458 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
461 struct mlx5_core_dev *func_mdev, *peer_mdev;
462 struct mlx5e_hairpin *hp;
463 struct mlx5_hairpin *pair;
466 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
468 return ERR_PTR(-ENOMEM);
470 func_mdev = priv->mdev;
471 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
473 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
476 goto create_pair_err;
479 hp->func_mdev = func_mdev;
480 hp->func_priv = priv;
481 hp->num_channels = params->num_channels;
483 err = mlx5e_hairpin_create_transport(hp);
485 goto create_transport_err;
487 if (hp->num_channels > 1) {
488 err = mlx5e_hairpin_rss_init(hp);
496 mlx5e_hairpin_destroy_transport(hp);
497 create_transport_err:
498 mlx5_core_hairpin_destroy(hp->pair);
504 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
506 if (hp->num_channels > 1)
507 mlx5e_hairpin_rss_cleanup(hp);
508 mlx5e_hairpin_destroy_transport(hp);
509 mlx5_core_hairpin_destroy(hp->pair);
513 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
515 return (peer_vhca_id << 16 | prio);
518 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
519 u16 peer_vhca_id, u8 prio)
521 struct mlx5e_hairpin_entry *hpe;
522 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
524 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
525 hairpin_hlist, hash_key) {
526 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
533 #define UNKNOWN_MATCH_PRIO 8
535 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
536 struct mlx5_flow_spec *spec, u8 *match_prio)
538 void *headers_c, *headers_v;
539 u8 prio_val, prio_mask = 0;
542 #ifdef CONFIG_MLX5_CORE_EN_DCB
543 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
544 netdev_warn(priv->netdev,
545 "only PCP trust state supported for hairpin\n");
549 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
550 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
552 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
554 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
555 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
558 if (!vlan_present || !prio_mask) {
559 prio_val = UNKNOWN_MATCH_PRIO;
560 } else if (prio_mask != 0x7) {
561 netdev_warn(priv->netdev,
562 "masked priority match not supported for hairpin\n");
566 *match_prio = prio_val;
570 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
571 struct mlx5e_tc_flow *flow,
572 struct mlx5e_tc_flow_parse_attr *parse_attr)
574 int peer_ifindex = parse_attr->mirred_ifindex;
575 struct mlx5_hairpin_params params;
576 struct mlx5_core_dev *peer_mdev;
577 struct mlx5e_hairpin_entry *hpe;
578 struct mlx5e_hairpin *hp;
585 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
586 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
587 netdev_warn(priv->netdev, "hairpin is not supported\n");
591 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
592 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
595 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
599 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
603 INIT_LIST_HEAD(&hpe->flows);
604 hpe->peer_vhca_id = peer_id;
605 hpe->prio = match_prio;
607 params.log_data_size = 15;
608 params.log_data_size = min_t(u8, params.log_data_size,
609 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
610 params.log_data_size = max_t(u8, params.log_data_size,
611 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
613 params.log_num_packets = params.log_data_size -
614 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
615 params.log_num_packets = min_t(u8, params.log_num_packets,
616 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
618 params.q_counter = priv->q_counter;
619 /* set hairpin pair per each 50Gbs share of the link */
620 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
621 link_speed = max_t(u32, link_speed, 50000);
622 link_speed64 = link_speed;
623 do_div(link_speed64, 50000);
624 params.num_channels = link_speed64;
626 hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex);
629 goto create_hairpin_err;
632 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
633 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
634 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
637 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
638 hash_hairpin_info(peer_id, match_prio));
641 if (hpe->hp->num_channels > 1) {
642 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
643 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
645 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
647 list_add(&flow->hairpin, &hpe->flows);
656 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
657 struct mlx5e_tc_flow *flow)
659 struct list_head *next = flow->hairpin.next;
661 list_del(&flow->hairpin);
663 /* no more hairpin flows for us, release the hairpin pair */
664 if (list_empty(next)) {
665 struct mlx5e_hairpin_entry *hpe;
667 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
669 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
670 hpe->hp->pair->peer_mdev->priv.name);
672 mlx5e_hairpin_destroy(hpe->hp);
673 hash_del(&hpe->hairpin_hlist);
678 static struct mlx5_flow_handle *
679 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
680 struct mlx5e_tc_flow_parse_attr *parse_attr,
681 struct mlx5e_tc_flow *flow)
683 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
684 struct mlx5_core_dev *dev = priv->mdev;
685 struct mlx5_flow_destination dest[2] = {};
686 struct mlx5_flow_act flow_act = {
687 .action = attr->action,
688 .has_flow_tag = true,
689 .flow_tag = attr->flow_tag,
692 struct mlx5_fc *counter = NULL;
693 struct mlx5_flow_handle *rule;
694 bool table_created = false;
695 int err, dest_ix = 0;
697 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
698 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
701 goto err_add_hairpin_flow;
703 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
704 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
705 dest[dest_ix].ft = attr->hairpin_ft;
707 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
708 dest[dest_ix].tir_num = attr->hairpin_tirn;
711 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
712 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
713 dest[dest_ix].ft = priv->fs.vlan.ft.t;
717 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
718 counter = mlx5_fc_create(dev, true);
719 if (IS_ERR(counter)) {
720 rule = ERR_CAST(counter);
723 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
724 dest[dest_ix].counter = counter;
728 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
729 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
730 flow_act.modify_id = attr->mod_hdr_id;
731 kfree(parse_attr->mod_hdr_actions);
734 goto err_create_mod_hdr_id;
738 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
739 int tc_grp_size, tc_tbl_size;
740 u32 max_flow_counter;
742 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
743 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
745 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
747 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
748 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
751 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
754 MLX5E_TC_TABLE_NUM_GROUPS,
755 MLX5E_TC_FT_LEVEL, 0);
756 if (IS_ERR(priv->fs.tc.t)) {
757 netdev_err(priv->netdev,
758 "Failed to create tc offload table\n");
759 rule = ERR_CAST(priv->fs.tc.t);
763 table_created = true;
766 if (attr->match_level != MLX5_MATCH_NONE)
767 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
769 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
770 &flow_act, dest, dest_ix);
779 mlx5_destroy_flow_table(priv->fs.tc.t);
780 priv->fs.tc.t = NULL;
783 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
784 mlx5e_detach_mod_hdr(priv, flow);
785 err_create_mod_hdr_id:
786 mlx5_fc_destroy(dev, counter);
788 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
789 mlx5e_hairpin_flow_del(priv, flow);
790 err_add_hairpin_flow:
794 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
795 struct mlx5e_tc_flow *flow)
797 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
798 struct mlx5_fc *counter = NULL;
800 counter = mlx5_flow_rule_counter(flow->rule[0]);
801 mlx5_del_flow_rules(flow->rule[0]);
802 mlx5_fc_destroy(priv->mdev, counter);
804 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
805 mlx5_destroy_flow_table(priv->fs.tc.t);
806 priv->fs.tc.t = NULL;
809 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
810 mlx5e_detach_mod_hdr(priv, flow);
812 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
813 mlx5e_hairpin_flow_del(priv, flow);
816 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
817 struct mlx5e_tc_flow *flow);
819 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
820 struct ip_tunnel_info *tun_info,
821 struct net_device *mirred_dev,
822 struct net_device **encap_dev,
823 struct mlx5e_tc_flow *flow);
825 static struct mlx5_flow_handle *
826 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
827 struct mlx5e_tc_flow_parse_attr *parse_attr,
828 struct mlx5e_tc_flow *flow)
830 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
831 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
832 struct net_device *out_dev, *encap_dev = NULL;
833 struct mlx5_flow_handle *rule = NULL;
834 struct mlx5e_rep_priv *rpriv;
835 struct mlx5e_priv *out_priv;
838 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
839 out_dev = __dev_get_by_index(dev_net(priv->netdev),
840 attr->parse_attr->mirred_ifindex);
841 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
842 out_dev, &encap_dev, flow);
846 goto err_attach_encap;
848 out_priv = netdev_priv(encap_dev);
849 rpriv = out_priv->ppriv;
850 attr->out_rep[attr->out_count] = rpriv->rep;
851 attr->out_mdev[attr->out_count++] = out_priv->mdev;
854 err = mlx5_eswitch_add_vlan_action(esw, attr);
860 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
861 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
862 kfree(parse_attr->mod_hdr_actions);
869 /* we get here if (1) there's no error (rule being null) or when
870 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
872 if (rule != ERR_PTR(-EAGAIN)) {
873 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
877 if (attr->mirror_count) {
878 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &parse_attr->spec, attr);
879 if (IS_ERR(flow->rule[1]))
886 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
887 rule = flow->rule[1];
889 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
890 mlx5e_detach_mod_hdr(priv, flow);
892 mlx5_eswitch_del_vlan_action(esw, attr);
894 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
895 mlx5e_detach_encap(priv, flow);
900 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
901 struct mlx5e_tc_flow *flow)
903 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
904 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
906 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
907 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
908 if (attr->mirror_count)
909 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
910 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
913 mlx5_eswitch_del_vlan_action(esw, attr);
915 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
916 mlx5e_detach_encap(priv, flow);
917 kvfree(attr->parse_attr);
920 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
921 mlx5e_detach_mod_hdr(priv, flow);
924 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
925 struct mlx5e_encap_entry *e)
927 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
928 struct mlx5_esw_flow_attr *esw_attr;
929 struct mlx5e_tc_flow *flow;
932 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
933 e->encap_size, e->encap_header,
936 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
940 e->flags |= MLX5_ENCAP_ENTRY_VALID;
941 mlx5e_rep_queue_neigh_stats_work(priv);
943 list_for_each_entry(flow, &e->flows, encap) {
944 esw_attr = flow->esw_attr;
945 esw_attr->encap_id = e->encap_id;
946 flow->rule[0] = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
947 if (IS_ERR(flow->rule[0])) {
948 err = PTR_ERR(flow->rule[0]);
949 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
954 if (esw_attr->mirror_count) {
955 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
956 if (IS_ERR(flow->rule[1])) {
957 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], esw_attr);
958 err = PTR_ERR(flow->rule[1]);
959 mlx5_core_warn(priv->mdev, "Failed to update cached mirror flow, %d\n",
965 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
969 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
970 struct mlx5e_encap_entry *e)
972 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
973 struct mlx5e_tc_flow *flow;
975 list_for_each_entry(flow, &e->flows, encap) {
976 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
977 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
979 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
980 if (attr->mirror_count)
981 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
982 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
986 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
987 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
988 mlx5_encap_dealloc(priv->mdev, e->encap_id);
992 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
994 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
995 struct mlx5e_tc_flow *flow;
996 struct mlx5e_encap_entry *e;
997 struct mlx5_fc *counter;
998 struct neigh_table *tbl;
999 bool neigh_used = false;
1000 struct neighbour *n;
1003 if (m_neigh->family == AF_INET)
1005 #if IS_ENABLED(CONFIG_IPV6)
1006 else if (m_neigh->family == AF_INET6)
1012 list_for_each_entry(e, &nhe->encap_list, encap_list) {
1013 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1015 list_for_each_entry(flow, &e->flows, encap) {
1016 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1017 counter = mlx5_flow_rule_counter(flow->rule[0]);
1018 lastuse = mlx5_fc_query_lastuse(counter);
1019 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1030 nhe->reported_lastuse = jiffies;
1032 /* find the relevant neigh according to the cached device and
1035 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1039 neigh_event_send(n, NULL);
1044 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1045 struct mlx5e_tc_flow *flow)
1047 struct list_head *next = flow->encap.next;
1049 list_del(&flow->encap);
1050 if (list_empty(next)) {
1051 struct mlx5e_encap_entry *e;
1053 e = list_entry(next, struct mlx5e_encap_entry, flows);
1054 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1056 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1057 mlx5_encap_dealloc(priv->mdev, e->encap_id);
1059 hash_del_rcu(&e->encap_hlist);
1060 kfree(e->encap_header);
1065 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1066 struct mlx5e_tc_flow *flow)
1068 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1069 mlx5e_tc_del_fdb_flow(priv, flow);
1071 mlx5e_tc_del_nic_flow(priv, flow);
1074 static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1075 struct tc_cls_flower_offload *f)
1077 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1079 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1081 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1083 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1086 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1087 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1089 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1090 struct flow_dissector_key_keyid *key =
1091 skb_flow_dissector_target(f->dissector,
1092 FLOW_DISSECTOR_KEY_ENC_KEYID,
1094 struct flow_dissector_key_keyid *mask =
1095 skb_flow_dissector_target(f->dissector,
1096 FLOW_DISSECTOR_KEY_ENC_KEYID,
1098 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1099 be32_to_cpu(mask->keyid));
1100 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1101 be32_to_cpu(key->keyid));
1105 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1106 struct mlx5_flow_spec *spec,
1107 struct tc_cls_flower_offload *f)
1109 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1111 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1114 struct flow_dissector_key_control *enc_control =
1115 skb_flow_dissector_target(f->dissector,
1116 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1119 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1120 struct flow_dissector_key_ports *key =
1121 skb_flow_dissector_target(f->dissector,
1122 FLOW_DISSECTOR_KEY_ENC_PORTS,
1124 struct flow_dissector_key_ports *mask =
1125 skb_flow_dissector_target(f->dissector,
1126 FLOW_DISSECTOR_KEY_ENC_PORTS,
1129 /* Full udp dst port must be given */
1130 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
1131 goto vxlan_match_offload_err;
1133 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->dst)) &&
1134 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1135 parse_vxlan_attr(spec, f);
1137 netdev_warn(priv->netdev,
1138 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
1142 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1143 udp_dport, ntohs(mask->dst));
1144 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1145 udp_dport, ntohs(key->dst));
1147 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1148 udp_sport, ntohs(mask->src));
1149 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1150 udp_sport, ntohs(key->src));
1151 } else { /* udp dst port must be given */
1152 vxlan_match_offload_err:
1153 netdev_warn(priv->netdev,
1154 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1158 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1159 struct flow_dissector_key_ipv4_addrs *key =
1160 skb_flow_dissector_target(f->dissector,
1161 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1163 struct flow_dissector_key_ipv4_addrs *mask =
1164 skb_flow_dissector_target(f->dissector,
1165 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1167 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1168 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1170 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1171 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1174 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1175 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1177 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1178 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1181 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1182 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
1183 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1184 struct flow_dissector_key_ipv6_addrs *key =
1185 skb_flow_dissector_target(f->dissector,
1186 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1188 struct flow_dissector_key_ipv6_addrs *mask =
1189 skb_flow_dissector_target(f->dissector,
1190 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1193 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1194 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1195 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1196 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1197 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1198 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1200 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1201 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1202 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1203 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1204 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1205 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1207 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1208 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
1211 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1212 struct flow_dissector_key_ip *key =
1213 skb_flow_dissector_target(f->dissector,
1214 FLOW_DISSECTOR_KEY_ENC_IP,
1216 struct flow_dissector_key_ip *mask =
1217 skb_flow_dissector_target(f->dissector,
1218 FLOW_DISSECTOR_KEY_ENC_IP,
1221 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1222 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1224 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1225 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1227 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1228 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1231 /* Enforce DMAC when offloading incoming tunneled flows.
1232 * Flow counters require a match on the DMAC.
1234 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1235 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1236 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1237 dmac_47_16), priv->netdev->dev_addr);
1239 /* let software handle IP fragments */
1240 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1241 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1246 static int __parse_cls_flower(struct mlx5e_priv *priv,
1247 struct mlx5_flow_spec *spec,
1248 struct tc_cls_flower_offload *f,
1251 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1253 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1255 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1257 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1262 *match_level = MLX5_MATCH_NONE;
1264 if (f->dissector->used_keys &
1265 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1266 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1267 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1268 BIT(FLOW_DISSECTOR_KEY_VLAN) |
1269 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1270 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1271 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1272 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1273 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1274 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1275 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1276 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1277 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1278 BIT(FLOW_DISSECTOR_KEY_TCP) |
1279 BIT(FLOW_DISSECTOR_KEY_IP) |
1280 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
1281 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1282 f->dissector->used_keys);
1286 if ((dissector_uses_key(f->dissector,
1287 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1288 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1289 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1290 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1291 struct flow_dissector_key_control *key =
1292 skb_flow_dissector_target(f->dissector,
1293 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1295 switch (key->addr_type) {
1296 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
1297 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
1298 if (parse_tunnel_attr(priv, spec, f))
1305 /* In decap flow, header pointers should point to the inner
1306 * headers, outer header were already set by parse_tunnel_attr
1308 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1310 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1314 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1315 struct flow_dissector_key_basic *key =
1316 skb_flow_dissector_target(f->dissector,
1317 FLOW_DISSECTOR_KEY_BASIC,
1319 struct flow_dissector_key_basic *mask =
1320 skb_flow_dissector_target(f->dissector,
1321 FLOW_DISSECTOR_KEY_BASIC,
1323 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1324 ntohs(mask->n_proto));
1325 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1326 ntohs(key->n_proto));
1329 *match_level = MLX5_MATCH_L2;
1332 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1333 struct flow_dissector_key_vlan *key =
1334 skb_flow_dissector_target(f->dissector,
1335 FLOW_DISSECTOR_KEY_VLAN,
1337 struct flow_dissector_key_vlan *mask =
1338 skb_flow_dissector_target(f->dissector,
1339 FLOW_DISSECTOR_KEY_VLAN,
1341 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1342 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1343 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1345 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1348 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1350 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1354 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1355 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
1357 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1358 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
1360 *match_level = MLX5_MATCH_L2;
1362 } else if (*match_level != MLX5_MATCH_NONE) {
1363 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1364 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1365 *match_level = MLX5_MATCH_L2;
1368 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1369 struct flow_dissector_key_vlan *key =
1370 skb_flow_dissector_target(f->dissector,
1371 FLOW_DISSECTOR_KEY_CVLAN,
1373 struct flow_dissector_key_vlan *mask =
1374 skb_flow_dissector_target(f->dissector,
1375 FLOW_DISSECTOR_KEY_CVLAN,
1377 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1378 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1379 MLX5_SET(fte_match_set_misc, misc_c,
1380 outer_second_svlan_tag, 1);
1381 MLX5_SET(fte_match_set_misc, misc_v,
1382 outer_second_svlan_tag, 1);
1384 MLX5_SET(fte_match_set_misc, misc_c,
1385 outer_second_cvlan_tag, 1);
1386 MLX5_SET(fte_match_set_misc, misc_v,
1387 outer_second_cvlan_tag, 1);
1390 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1392 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1394 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1395 mask->vlan_priority);
1396 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1397 key->vlan_priority);
1399 *match_level = MLX5_MATCH_L2;
1403 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1404 struct flow_dissector_key_eth_addrs *key =
1405 skb_flow_dissector_target(f->dissector,
1406 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1408 struct flow_dissector_key_eth_addrs *mask =
1409 skb_flow_dissector_target(f->dissector,
1410 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1413 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1416 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1420 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1423 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1427 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
1428 *match_level = MLX5_MATCH_L2;
1431 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1432 struct flow_dissector_key_control *key =
1433 skb_flow_dissector_target(f->dissector,
1434 FLOW_DISSECTOR_KEY_CONTROL,
1437 struct flow_dissector_key_control *mask =
1438 skb_flow_dissector_target(f->dissector,
1439 FLOW_DISSECTOR_KEY_CONTROL,
1441 addr_type = key->addr_type;
1443 /* the HW doesn't support frag first/later */
1444 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1447 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1448 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1449 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1450 key->flags & FLOW_DIS_IS_FRAGMENT);
1452 /* the HW doesn't need L3 inline to match on frag=no */
1453 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
1454 *match_level = MLX5_MATCH_L2;
1455 /* *** L2 attributes parsing up to here *** */
1457 *match_level = MLX5_MATCH_L3;
1461 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1462 struct flow_dissector_key_basic *key =
1463 skb_flow_dissector_target(f->dissector,
1464 FLOW_DISSECTOR_KEY_BASIC,
1466 struct flow_dissector_key_basic *mask =
1467 skb_flow_dissector_target(f->dissector,
1468 FLOW_DISSECTOR_KEY_BASIC,
1470 ip_proto = key->ip_proto;
1472 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1474 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1478 *match_level = MLX5_MATCH_L3;
1481 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1482 struct flow_dissector_key_ipv4_addrs *key =
1483 skb_flow_dissector_target(f->dissector,
1484 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1486 struct flow_dissector_key_ipv4_addrs *mask =
1487 skb_flow_dissector_target(f->dissector,
1488 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1491 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1492 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1493 &mask->src, sizeof(mask->src));
1494 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1495 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1496 &key->src, sizeof(key->src));
1497 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1498 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1499 &mask->dst, sizeof(mask->dst));
1500 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1501 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1502 &key->dst, sizeof(key->dst));
1504 if (mask->src || mask->dst)
1505 *match_level = MLX5_MATCH_L3;
1508 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1509 struct flow_dissector_key_ipv6_addrs *key =
1510 skb_flow_dissector_target(f->dissector,
1511 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1513 struct flow_dissector_key_ipv6_addrs *mask =
1514 skb_flow_dissector_target(f->dissector,
1515 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1518 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1519 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1520 &mask->src, sizeof(mask->src));
1521 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1522 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1523 &key->src, sizeof(key->src));
1525 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1526 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1527 &mask->dst, sizeof(mask->dst));
1528 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1529 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1530 &key->dst, sizeof(key->dst));
1532 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1533 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
1534 *match_level = MLX5_MATCH_L3;
1537 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1538 struct flow_dissector_key_ip *key =
1539 skb_flow_dissector_target(f->dissector,
1540 FLOW_DISSECTOR_KEY_IP,
1542 struct flow_dissector_key_ip *mask =
1543 skb_flow_dissector_target(f->dissector,
1544 FLOW_DISSECTOR_KEY_IP,
1547 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1548 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1550 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1551 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1553 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1554 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1557 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1558 ft_field_support.outer_ipv4_ttl))
1561 if (mask->tos || mask->ttl)
1562 *match_level = MLX5_MATCH_L3;
1565 /* *** L3 attributes parsing up to here *** */
1567 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1568 struct flow_dissector_key_ports *key =
1569 skb_flow_dissector_target(f->dissector,
1570 FLOW_DISSECTOR_KEY_PORTS,
1572 struct flow_dissector_key_ports *mask =
1573 skb_flow_dissector_target(f->dissector,
1574 FLOW_DISSECTOR_KEY_PORTS,
1578 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1579 tcp_sport, ntohs(mask->src));
1580 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1581 tcp_sport, ntohs(key->src));
1583 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1584 tcp_dport, ntohs(mask->dst));
1585 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1586 tcp_dport, ntohs(key->dst));
1590 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1591 udp_sport, ntohs(mask->src));
1592 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1593 udp_sport, ntohs(key->src));
1595 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1596 udp_dport, ntohs(mask->dst));
1597 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1598 udp_dport, ntohs(key->dst));
1601 netdev_err(priv->netdev,
1602 "Only UDP and TCP transport are supported\n");
1606 if (mask->src || mask->dst)
1607 *match_level = MLX5_MATCH_L4;
1610 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1611 struct flow_dissector_key_tcp *key =
1612 skb_flow_dissector_target(f->dissector,
1613 FLOW_DISSECTOR_KEY_TCP,
1615 struct flow_dissector_key_tcp *mask =
1616 skb_flow_dissector_target(f->dissector,
1617 FLOW_DISSECTOR_KEY_TCP,
1620 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1621 ntohs(mask->flags));
1622 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1626 *match_level = MLX5_MATCH_L4;
1632 static int parse_cls_flower(struct mlx5e_priv *priv,
1633 struct mlx5e_tc_flow *flow,
1634 struct mlx5_flow_spec *spec,
1635 struct tc_cls_flower_offload *f)
1637 struct mlx5_core_dev *dev = priv->mdev;
1638 struct mlx5_eswitch *esw = dev->priv.eswitch;
1639 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1640 struct mlx5_eswitch_rep *rep;
1644 err = __parse_cls_flower(priv, spec, f, &match_level);
1646 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1648 if (rep->vport != FDB_UPLINK_VPORT &&
1649 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1650 esw->offloads.inline_mode < match_level)) {
1651 netdev_warn(priv->netdev,
1652 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1653 match_level, esw->offloads.inline_mode);
1658 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1659 flow->esw_attr->match_level = match_level;
1661 flow->nic_attr->match_level = match_level;
1666 struct pedit_headers {
1674 static int pedit_header_offsets[] = {
1675 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1676 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1677 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1678 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1679 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1682 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1684 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1685 struct pedit_headers *masks,
1686 struct pedit_headers *vals)
1688 u32 *curr_pmask, *curr_pval;
1690 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1693 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1694 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1696 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1699 *curr_pmask |= mask;
1700 *curr_pval |= (val & mask);
1708 struct mlx5_fields {
1714 #define OFFLOAD(fw_field, size, field, off) \
1715 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1717 static struct mlx5_fields fields[] = {
1718 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1719 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1720 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1721 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1722 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1724 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1725 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1726 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1728 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1729 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1730 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1731 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1732 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1733 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1734 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1735 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
1736 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
1738 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1739 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1740 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1742 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1743 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
1746 /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
1747 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
1748 * says how many HW actions were actually parsed.
1750 static int offload_pedit_fields(struct pedit_headers *masks,
1751 struct pedit_headers *vals,
1752 struct mlx5e_tc_flow_parse_attr *parse_attr)
1754 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
1755 int i, action_size, nactions, max_actions, first, last, next_z;
1756 void *s_masks_p, *a_masks_p, *vals_p;
1757 struct mlx5_fields *f;
1758 u8 cmd, field_bsize;
1765 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1766 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1767 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1768 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1770 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1771 action = parse_attr->mod_hdr_actions +
1772 parse_attr->num_mod_hdr_actions * action_size;
1774 max_actions = parse_attr->max_mod_hdr_actions;
1775 nactions = parse_attr->num_mod_hdr_actions;
1777 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1779 /* avoid seeing bits set from previous iterations */
1783 s_masks_p = (void *)set_masks + f->offset;
1784 a_masks_p = (void *)add_masks + f->offset;
1786 memcpy(&s_mask, s_masks_p, f->size);
1787 memcpy(&a_mask, a_masks_p, f->size);
1789 if (!s_mask && !a_mask) /* nothing to offload here */
1792 if (s_mask && a_mask) {
1793 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1797 if (nactions == max_actions) {
1798 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1803 cmd = MLX5_ACTION_TYPE_SET;
1805 vals_p = (void *)set_vals + f->offset;
1806 /* clear to denote we consumed this field */
1807 memset(s_masks_p, 0, f->size);
1809 cmd = MLX5_ACTION_TYPE_ADD;
1811 vals_p = (void *)add_vals + f->offset;
1812 /* clear to denote we consumed this field */
1813 memset(a_masks_p, 0, f->size);
1816 field_bsize = f->size * BITS_PER_BYTE;
1818 if (field_bsize == 32) {
1819 mask_be32 = *(__be32 *)&mask;
1820 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1821 } else if (field_bsize == 16) {
1822 mask_be16 = *(__be16 *)&mask;
1823 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1826 first = find_first_bit(&mask, field_bsize);
1827 next_z = find_next_zero_bit(&mask, field_bsize, first);
1828 last = find_last_bit(&mask, field_bsize);
1829 if (first < next_z && next_z < last) {
1830 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
1835 MLX5_SET(set_action_in, action, action_type, cmd);
1836 MLX5_SET(set_action_in, action, field, f->field);
1838 if (cmd == MLX5_ACTION_TYPE_SET) {
1839 MLX5_SET(set_action_in, action, offset, first);
1840 /* length is num of bits to be written, zero means length of 32 */
1841 MLX5_SET(set_action_in, action, length, (last - first + 1));
1844 if (field_bsize == 32)
1845 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
1846 else if (field_bsize == 16)
1847 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
1848 else if (field_bsize == 8)
1849 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
1851 action += action_size;
1855 parse_attr->num_mod_hdr_actions = nactions;
1859 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1860 const struct tc_action *a, int namespace,
1861 struct mlx5e_tc_flow_parse_attr *parse_attr)
1863 int nkeys, action_size, max_actions;
1865 nkeys = tcf_pedit_nkeys(a);
1866 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1868 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1869 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1870 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1871 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1873 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1874 max_actions = min(max_actions, nkeys * 16);
1876 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1877 if (!parse_attr->mod_hdr_actions)
1880 parse_attr->max_mod_hdr_actions = max_actions;
1884 static const struct pedit_headers zero_masks = {};
1886 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1887 const struct tc_action *a, int namespace,
1888 struct mlx5e_tc_flow_parse_attr *parse_attr)
1890 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1891 int nkeys, i, err = -EOPNOTSUPP;
1892 u32 mask, val, offset;
1895 nkeys = tcf_pedit_nkeys(a);
1897 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1898 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1900 for (i = 0; i < nkeys; i++) {
1901 htype = tcf_pedit_htype(a, i);
1902 cmd = tcf_pedit_cmd(a, i);
1903 err = -EOPNOTSUPP; /* can't be all optimistic */
1905 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1906 netdev_warn(priv->netdev, "legacy pedit isn't offloaded\n");
1910 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1911 netdev_warn(priv->netdev, "pedit cmd %d isn't offloaded\n", cmd);
1915 mask = tcf_pedit_mask(a, i);
1916 val = tcf_pedit_val(a, i);
1917 offset = tcf_pedit_offset(a, i);
1919 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1924 if (!parse_attr->mod_hdr_actions) {
1925 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1930 err = offload_pedit_fields(masks, vals, parse_attr);
1932 goto out_dealloc_parsed_actions;
1934 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1935 cmd_masks = &masks[cmd];
1936 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1937 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
1938 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1939 16, 1, cmd_masks, sizeof(zero_masks), true);
1941 goto out_dealloc_parsed_actions;
1947 out_dealloc_parsed_actions:
1948 kfree(parse_attr->mod_hdr_actions);
1953 static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1955 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1956 TCA_CSUM_UPDATE_FLAG_UDP;
1958 /* The HW recalcs checksums only if re-writing headers */
1959 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1960 netdev_warn(priv->netdev,
1961 "TC csum action is only offloaded with pedit\n");
1965 if (update_flags & ~prot_flags) {
1966 netdev_warn(priv->netdev,
1967 "can't offload TC csum action for some header/s - flags %#x\n",
1975 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1976 struct tcf_exts *exts)
1978 const struct tc_action *a;
1979 bool modify_ip_header;
1986 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1987 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1989 /* for non-IP we only re-write MACs, so we're okay */
1990 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1993 modify_ip_header = false;
1994 tcf_exts_for_each_action(i, a, exts) {
1997 if (!is_tcf_pedit(a))
2000 nkeys = tcf_pedit_nkeys(a);
2001 for (k = 0; k < nkeys; k++) {
2002 htype = tcf_pedit_htype(a, k);
2003 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2004 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2005 modify_ip_header = true;
2011 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2012 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2013 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2014 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2022 static bool actions_match_supported(struct mlx5e_priv *priv,
2023 struct tcf_exts *exts,
2024 struct mlx5e_tc_flow_parse_attr *parse_attr,
2025 struct mlx5e_tc_flow *flow)
2029 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2030 actions = flow->esw_attr->action;
2032 actions = flow->nic_attr->action;
2034 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2035 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2038 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2039 return modify_header_match_supported(&parse_attr->spec, exts);
2044 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2046 struct mlx5_core_dev *fmdev, *pmdev;
2047 u64 fsystem_guid, psystem_guid;
2050 pmdev = peer_priv->mdev;
2052 mlx5_query_nic_vport_system_image_guid(fmdev, &fsystem_guid);
2053 mlx5_query_nic_vport_system_image_guid(pmdev, &psystem_guid);
2055 return (fsystem_guid == psystem_guid);
2058 static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
2059 struct mlx5e_tc_flow_parse_attr *parse_attr,
2060 struct mlx5e_tc_flow *flow)
2062 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2063 const struct tc_action *a;
2068 if (!tcf_exts_has_actions(exts))
2071 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2073 tcf_exts_for_each_action(i, a, exts) {
2074 if (is_tcf_gact_shot(a)) {
2075 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2076 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2077 flow_table_properties_nic_receive.flow_counter))
2078 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2082 if (is_tcf_pedit(a)) {
2083 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
2088 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2089 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2093 if (is_tcf_csum(a)) {
2094 if (csum_offload_supported(priv, action,
2095 tcf_csum_update_flags(a)))
2101 if (is_tcf_mirred_egress_redirect(a)) {
2102 struct net_device *peer_dev = tcf_mirred_dev(a);
2104 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2105 same_hw_devs(priv, netdev_priv(peer_dev))) {
2106 parse_attr->mirred_ifindex = peer_dev->ifindex;
2107 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
2108 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2109 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2111 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2118 if (is_tcf_skbedit_mark(a)) {
2119 u32 mark = tcf_skbedit_mark(a);
2121 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2122 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
2127 attr->flow_tag = mark;
2128 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2135 attr->action = action;
2136 if (!actions_match_supported(priv, exts, parse_attr, flow))
2142 static inline int cmp_encap_info(struct ip_tunnel_key *a,
2143 struct ip_tunnel_key *b)
2145 return memcmp(a, b, sizeof(*a));
2148 static inline int hash_encap_info(struct ip_tunnel_key *key)
2150 return jhash(key, sizeof(*key), 0);
2153 static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2154 struct net_device *mirred_dev,
2155 struct net_device **out_dev,
2157 struct neighbour **out_n,
2160 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2161 struct mlx5e_rep_priv *uplink_rpriv;
2163 struct neighbour *n = NULL;
2165 #if IS_ENABLED(CONFIG_INET)
2168 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
2169 ret = PTR_ERR_OR_ZERO(rt);
2175 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2176 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2177 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
2178 *out_dev = uplink_rpriv->netdev;
2180 *out_dev = rt->dst.dev;
2183 *out_ttl = ip4_dst_hoplimit(&rt->dst);
2184 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2193 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2194 struct net_device *peer_netdev)
2196 struct mlx5e_priv *peer_priv;
2198 peer_priv = netdev_priv(peer_netdev);
2200 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2201 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2202 same_hw_devs(priv, peer_priv) &&
2203 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2204 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2207 static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2208 struct net_device *mirred_dev,
2209 struct net_device **out_dev,
2211 struct neighbour **out_n,
2214 struct neighbour *n = NULL;
2215 struct dst_entry *dst;
2217 #if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
2218 struct mlx5e_rep_priv *uplink_rpriv;
2219 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2221 dst = ipv6_stub->ipv6_dst_lookup_flow(dev_net(mirred_dev), NULL, fl6,
2224 return PTR_ERR(dst);
2227 *out_ttl = ip6_dst_hoplimit(dst);
2229 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2230 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2231 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
2232 *out_dev = uplink_rpriv->netdev;
2234 *out_dev = dst->dev;
2239 n = dst_neigh_lookup(dst, &fl6->daddr);
2248 static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2249 char buf[], int encap_size,
2250 unsigned char h_dest[ETH_ALEN],
2254 __be16 udp_dst_port,
2257 struct ethhdr *eth = (struct ethhdr *)buf;
2258 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2259 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2260 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2262 memset(buf, 0, encap_size);
2264 ether_addr_copy(eth->h_dest, h_dest);
2265 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2266 eth->h_proto = htons(ETH_P_IP);
2273 ip->protocol = IPPROTO_UDP;
2277 udp->dest = udp_dst_port;
2278 vxh->vx_flags = VXLAN_HF_VNI;
2279 vxh->vx_vni = vxlan_vni_field(vx_vni);
2282 static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2283 char buf[], int encap_size,
2284 unsigned char h_dest[ETH_ALEN],
2286 struct in6_addr *daddr,
2287 struct in6_addr *saddr,
2288 __be16 udp_dst_port,
2291 struct ethhdr *eth = (struct ethhdr *)buf;
2292 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2293 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2294 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2296 memset(buf, 0, encap_size);
2298 ether_addr_copy(eth->h_dest, h_dest);
2299 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2300 eth->h_proto = htons(ETH_P_IPV6);
2302 ip6_flow_hdr(ip6h, tos, 0);
2303 /* the HW fills up ipv6 payload len */
2304 ip6h->nexthdr = IPPROTO_UDP;
2305 ip6h->hop_limit = ttl;
2306 ip6h->daddr = *daddr;
2307 ip6h->saddr = *saddr;
2309 udp->dest = udp_dst_port;
2310 vxh->vx_flags = VXLAN_HF_VNI;
2311 vxh->vx_vni = vxlan_vni_field(vx_vni);
2314 static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2315 struct net_device *mirred_dev,
2316 struct mlx5e_encap_entry *e)
2318 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2319 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
2320 struct ip_tunnel_key *tun_key = &e->tun_info.key;
2321 struct net_device *out_dev;
2322 struct neighbour *n = NULL;
2323 struct flowi4 fl4 = {};
2324 u8 nud_state, tos, ttl;
2328 if (max_encap_size < ipv4_encap_size) {
2329 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2330 ipv4_encap_size, max_encap_size);
2334 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
2338 switch (e->tunnel_type) {
2339 case MLX5_HEADER_TYPE_VXLAN:
2340 fl4.flowi4_proto = IPPROTO_UDP;
2341 fl4.fl4_dport = tun_key->tp_dst;
2351 fl4.flowi4_tos = tun_key->tos;
2352 fl4.daddr = tun_key->u.ipv4.dst;
2353 fl4.saddr = tun_key->u.ipv4.src;
2355 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
2360 /* used by mlx5e_detach_encap to lookup a neigh hash table
2361 * entry in the neigh hash table when a user deletes a rule
2363 e->m_neigh.dev = n->dev;
2364 e->m_neigh.family = n->ops->family;
2365 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2366 e->out_dev = out_dev;
2368 /* It's importent to add the neigh to the hash table before checking
2369 * the neigh validity state. So if we'll get a notification, in case the
2370 * neigh changes it's validity state, we would find the relevant neigh
2373 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2377 read_lock_bh(&n->lock);
2378 nud_state = n->nud_state;
2379 ether_addr_copy(e->h_dest, n->ha);
2380 read_unlock_bh(&n->lock);
2382 switch (e->tunnel_type) {
2383 case MLX5_HEADER_TYPE_VXLAN:
2384 gen_vxlan_header_ipv4(out_dev, encap_header,
2385 ipv4_encap_size, e->h_dest, tos, ttl,
2387 fl4.saddr, tun_key->tp_dst,
2388 tunnel_id_to_key32(tun_key->tun_id));
2392 goto destroy_neigh_entry;
2394 e->encap_size = ipv4_encap_size;
2395 e->encap_header = encap_header;
2397 if (!(nud_state & NUD_VALID)) {
2398 neigh_event_send(n, NULL);
2403 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
2404 ipv4_encap_size, encap_header, &e->encap_id);
2406 goto destroy_neigh_entry;
2408 e->flags |= MLX5_ENCAP_ENTRY_VALID;
2409 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2413 destroy_neigh_entry:
2414 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2416 kfree(encap_header);
2423 static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2424 struct net_device *mirred_dev,
2425 struct mlx5e_encap_entry *e)
2427 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2428 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
2429 struct ip_tunnel_key *tun_key = &e->tun_info.key;
2430 struct net_device *out_dev = NULL;
2431 struct neighbour *n = NULL;
2432 struct flowi6 fl6 = {};
2433 u8 nud_state, tos, ttl;
2437 if (max_encap_size < ipv6_encap_size) {
2438 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2439 ipv6_encap_size, max_encap_size);
2443 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
2447 switch (e->tunnel_type) {
2448 case MLX5_HEADER_TYPE_VXLAN:
2449 fl6.flowi6_proto = IPPROTO_UDP;
2450 fl6.fl6_dport = tun_key->tp_dst;
2460 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2461 fl6.daddr = tun_key->u.ipv6.dst;
2462 fl6.saddr = tun_key->u.ipv6.src;
2464 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
2469 /* used by mlx5e_detach_encap to lookup a neigh hash table
2470 * entry in the neigh hash table when a user deletes a rule
2472 e->m_neigh.dev = n->dev;
2473 e->m_neigh.family = n->ops->family;
2474 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2475 e->out_dev = out_dev;
2477 /* It's importent to add the neigh to the hash table before checking
2478 * the neigh validity state. So if we'll get a notification, in case the
2479 * neigh changes it's validity state, we would find the relevant neigh
2482 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2486 read_lock_bh(&n->lock);
2487 nud_state = n->nud_state;
2488 ether_addr_copy(e->h_dest, n->ha);
2489 read_unlock_bh(&n->lock);
2491 switch (e->tunnel_type) {
2492 case MLX5_HEADER_TYPE_VXLAN:
2493 gen_vxlan_header_ipv6(out_dev, encap_header,
2494 ipv6_encap_size, e->h_dest, tos, ttl,
2496 &fl6.saddr, tun_key->tp_dst,
2497 tunnel_id_to_key32(tun_key->tun_id));
2501 goto destroy_neigh_entry;
2504 e->encap_size = ipv6_encap_size;
2505 e->encap_header = encap_header;
2507 if (!(nud_state & NUD_VALID)) {
2508 neigh_event_send(n, NULL);
2513 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
2514 ipv6_encap_size, encap_header, &e->encap_id);
2516 goto destroy_neigh_entry;
2518 e->flags |= MLX5_ENCAP_ENTRY_VALID;
2519 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2523 destroy_neigh_entry:
2524 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2526 kfree(encap_header);
2533 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2534 struct ip_tunnel_info *tun_info,
2535 struct net_device *mirred_dev,
2536 struct net_device **encap_dev,
2537 struct mlx5e_tc_flow *flow)
2539 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2540 unsigned short family = ip_tunnel_info_af(tun_info);
2541 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2542 struct ip_tunnel_key *key = &tun_info->key;
2543 struct mlx5e_encap_entry *e;
2544 int tunnel_type, err = 0;
2548 /* udp dst port must be set */
2549 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2550 goto vxlan_encap_offload_err;
2552 /* setting udp src port isn't supported */
2553 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2554 vxlan_encap_offload_err:
2555 netdev_warn(priv->netdev,
2556 "must set udp dst port and not set udp src port\n");
2560 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->tp_dst)) &&
2561 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
2562 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2564 netdev_warn(priv->netdev,
2565 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
2569 hash_key = hash_encap_info(key);
2571 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2572 encap_hlist, hash_key) {
2573 if (!cmp_encap_info(&e->tun_info.key, key)) {
2579 /* must verify if encap is valid or not */
2583 e = kzalloc(sizeof(*e), GFP_KERNEL);
2587 e->tun_info = *tun_info;
2588 e->tunnel_type = tunnel_type;
2589 INIT_LIST_HEAD(&e->flows);
2591 if (family == AF_INET)
2592 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
2593 else if (family == AF_INET6)
2594 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
2596 if (err && err != -EAGAIN)
2599 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2602 list_add(&flow->encap, &e->flows);
2603 *encap_dev = e->out_dev;
2604 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2605 attr->encap_id = e->encap_id;
2616 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2617 const struct tc_action *a,
2618 struct mlx5_esw_flow_attr *attr,
2621 u8 vlan_idx = attr->total_vlan;
2623 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2626 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
2628 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2629 MLX5_FS_VLAN_DEPTH))
2632 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2634 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2636 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
2637 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2638 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2639 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2640 if (!attr->vlan_proto[vlan_idx])
2641 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2644 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2645 MLX5_FS_VLAN_DEPTH))
2648 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2650 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2651 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2652 tcf_vlan_push_prio(a)))
2655 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
2657 } else { /* action is TCA_VLAN_ACT_MODIFY */
2661 attr->total_vlan = vlan_idx + 1;
2666 static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
2667 struct mlx5e_tc_flow_parse_attr *parse_attr,
2668 struct mlx5e_tc_flow *flow)
2670 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2671 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2672 struct ip_tunnel_info *info = NULL;
2673 const struct tc_action *a;
2679 if (!tcf_exts_has_actions(exts))
2682 attr->in_rep = rpriv->rep;
2683 attr->in_mdev = priv->mdev;
2685 tcf_exts_for_each_action(i, a, exts) {
2686 if (is_tcf_gact_shot(a)) {
2687 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2688 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2692 if (is_tcf_pedit(a)) {
2693 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2698 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2699 attr->mirror_count = attr->out_count;
2703 if (is_tcf_csum(a)) {
2704 if (csum_offload_supported(priv, action,
2705 tcf_csum_update_flags(a)))
2711 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
2712 struct mlx5e_priv *out_priv;
2713 struct net_device *out_dev;
2715 out_dev = tcf_mirred_dev(a);
2717 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
2718 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2723 if (switchdev_port_same_parent_id(priv->netdev,
2725 is_merged_eswitch_dev(priv, out_dev)) {
2726 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2727 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2728 out_priv = netdev_priv(out_dev);
2729 rpriv = out_priv->ppriv;
2730 attr->out_rep[attr->out_count] = rpriv->rep;
2731 attr->out_mdev[attr->out_count++] = out_priv->mdev;
2733 parse_attr->mirred_ifindex = out_dev->ifindex;
2734 parse_attr->tun_info = *info;
2735 attr->parse_attr = parse_attr;
2736 action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2737 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2738 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2739 /* attr->out_rep is resolved when we handle encap */
2741 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2742 priv->netdev->name, out_dev->name);
2748 if (is_tcf_tunnel_set(a)) {
2749 info = tcf_tunnel_info(a);
2754 attr->mirror_count = attr->out_count;
2758 if (is_tcf_vlan(a)) {
2759 err = parse_tc_vlan_action(priv, a, attr, &action);
2764 attr->mirror_count = attr->out_count;
2768 if (is_tcf_tunnel_release(a)) {
2769 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2776 attr->action = action;
2777 if (!actions_match_supported(priv, exts, parse_attr, flow))
2780 if (attr->out_count > 1 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
2781 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2788 static void get_flags(int flags, u8 *flow_flags)
2790 u8 __flow_flags = 0;
2792 if (flags & MLX5E_TC_INGRESS)
2793 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2794 if (flags & MLX5E_TC_EGRESS)
2795 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2797 *flow_flags = __flow_flags;
2800 static const struct rhashtable_params tc_ht_params = {
2801 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2802 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2803 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2804 .automatic_shrinking = true,
2807 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
2809 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2810 struct mlx5e_rep_priv *uplink_rpriv;
2812 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
2813 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2814 return &uplink_rpriv->tc_ht;
2816 return &priv->fs.tc.ht;
2819 int mlx5e_configure_flower(struct mlx5e_priv *priv,
2820 struct tc_cls_flower_offload *f, int flags)
2822 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2823 struct mlx5e_tc_flow_parse_attr *parse_attr;
2824 struct rhashtable *tc_ht = get_tc_ht(priv);
2825 struct mlx5e_tc_flow *flow;
2826 int attr_size, err = 0;
2829 get_flags(flags, &flow_flags);
2831 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2833 netdev_warn_once(priv->netdev, "flow cookie %lx already exists, ignoring\n", f->cookie);
2837 if (esw && esw->mode == SRIOV_OFFLOADS) {
2838 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2839 attr_size = sizeof(struct mlx5_esw_flow_attr);
2841 flow_flags |= MLX5E_TC_FLOW_NIC;
2842 attr_size = sizeof(struct mlx5_nic_flow_attr);
2845 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
2846 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
2847 if (!parse_attr || !flow) {
2852 flow->cookie = f->cookie;
2853 flow->flags = flow_flags;
2856 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
2860 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
2861 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
2864 flow->rule[0] = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
2866 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
2869 flow->rule[0] = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
2872 if (IS_ERR(flow->rule[0])) {
2873 err = PTR_ERR(flow->rule[0]);
2879 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2881 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
2882 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2885 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
2887 mlx5e_tc_del_flow(priv, flow);
2899 #define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2900 #define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2902 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2904 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2910 int mlx5e_delete_flower(struct mlx5e_priv *priv,
2911 struct tc_cls_flower_offload *f, int flags)
2913 struct rhashtable *tc_ht = get_tc_ht(priv);
2914 struct mlx5e_tc_flow *flow;
2916 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2917 if (!flow || !same_flow_direction(flow, flags))
2920 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
2922 mlx5e_tc_del_flow(priv, flow);
2929 int mlx5e_stats_flower(struct mlx5e_priv *priv,
2930 struct tc_cls_flower_offload *f, int flags)
2932 struct rhashtable *tc_ht = get_tc_ht(priv);
2933 struct mlx5e_tc_flow *flow;
2934 struct mlx5_fc *counter;
2939 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2940 if (!flow || !same_flow_direction(flow, flags))
2943 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2946 counter = mlx5_flow_rule_counter(flow->rule[0]);
2950 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2952 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
2957 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
2958 struct mlx5e_priv *peer_priv)
2960 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
2961 struct mlx5e_hairpin_entry *hpe;
2965 if (!same_hw_devs(priv, peer_priv))
2968 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
2970 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
2971 if (hpe->peer_vhca_id == peer_vhca_id)
2972 hpe->hp->pair->peer_gone = true;
2976 static int mlx5e_tc_netdev_event(struct notifier_block *this,
2977 unsigned long event, void *ptr)
2979 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2980 struct mlx5e_flow_steering *fs;
2981 struct mlx5e_priv *peer_priv;
2982 struct mlx5e_tc_table *tc;
2983 struct mlx5e_priv *priv;
2985 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
2986 event != NETDEV_UNREGISTER ||
2987 ndev->reg_state == NETREG_REGISTERED)
2990 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
2991 fs = container_of(tc, struct mlx5e_flow_steering, tc);
2992 priv = container_of(fs, struct mlx5e_priv, fs);
2993 peer_priv = netdev_priv(ndev);
2994 if (priv == peer_priv ||
2995 !(priv->netdev->features & NETIF_F_HW_TC))
2998 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3003 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
3005 struct mlx5e_tc_table *tc = &priv->fs.tc;
3008 hash_init(tc->mod_hdr_tbl);
3009 hash_init(tc->hairpin_tbl);
3011 err = rhashtable_init(&tc->ht, &tc_ht_params);
3015 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3016 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3017 tc->netdevice_nb.notifier_call = NULL;
3018 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3024 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3026 struct mlx5e_tc_flow *flow = ptr;
3027 struct mlx5e_priv *priv = flow->priv;
3029 mlx5e_tc_del_flow(priv, flow);
3033 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
3035 struct mlx5e_tc_table *tc = &priv->fs.tc;
3037 if (tc->netdevice_nb.notifier_call)
3038 unregister_netdevice_notifier(&tc->netdevice_nb);
3040 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
3042 if (!IS_ERR_OR_NULL(tc->t)) {
3043 mlx5_destroy_flow_table(tc->t);
3048 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3050 return rhashtable_init(tc_ht, &tc_ht_params);
3053 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3055 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3058 int mlx5e_tc_num_filters(struct mlx5e_priv *priv)
3060 struct rhashtable *tc_ht = get_tc_ht(priv);
3062 return atomic_read(&tc_ht->nelems);