drivers/net/ethernet/mellanox/mlxsw/spectrum.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/slab.h>
  12 #include <linux/device.h>
  13 #include <linux/skbuff.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/if_bridge.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/bitops.h>
  19 #include <linux/list.h>
  20 #include <linux/notifier.h>
  21 #include <linux/dcbnl.h>
  22 #include <linux/inetdevice.h>
  23 #include <linux/netlink.h>
  24 #include <net/switchdev.h>
  25 #include <net/pkt_cls.h>
  26 #include <net/tc_act/tc_mirred.h>
  27 #include <net/netevent.h>
  28 #include <net/tc_act/tc_sample.h>
  29 #include <net/addrconf.h>
  30
  31 #include "spectrum.h"
  32 #include "pci.h"
  33 #include "core.h"
  34 #include "reg.h"
  35 #include "port.h"
  36 #include "trap.h"
  37 #include "txheader.h"
  38 #include "spectrum_cnt.h"
  39 #include "spectrum_dpipe.h"
  40 #include "spectrum_acl_flex_actions.h"
  41 #include "spectrum_span.h"
  42 #include "../mlxfw/mlxfw.h"
  43
  44 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
  45
  46 #define MLXSW_SP1_FWREV_MAJOR 13
  47 #define MLXSW_SP1_FWREV_MINOR 1703
  48 #define MLXSW_SP1_FWREV_SUBMINOR 4
  49 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  50
  51 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  52         .major = MLXSW_SP1_FWREV_MAJOR,
  53         .minor = MLXSW_SP1_FWREV_MINOR,
  54         .subminor = MLXSW_SP1_FWREV_SUBMINOR,
  55         .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  56 };
  57
  58 #define MLXSW_SP1_FW_FILENAME \
  59         "/*(DEBLOBBED)*/"
  60
  61 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  62 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  63 static const char mlxsw_sp_driver_version[] = "1.0";
  64
  65 /* tx_hdr_version
  66  * Tx header version.
  67  * Must be set to 1.
  68  */
  69 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  70
  71 /* tx_hdr_ctl
  72  * Packet control type.
  73  * 0 - Ethernet control (e.g. EMADs, LACP)
  74  * 1 - Ethernet data
  75  */
  76 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  77
  78 /* tx_hdr_proto
  79  * Packet protocol type. Must be set to 1 (Ethernet).
  80  */
  81 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  82
  83 /* tx_hdr_rx_is_router
  84  * Packet is sent from the router. Valid for data packets only.
  85  */
  86 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
  87
  88 /* tx_hdr_fid_valid
  89  * Indicates if the 'fid' field is valid and should be used for
  90  * forwarding lookup. Valid for data packets only.
  91  */
  92 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
  93
  94 /* tx_hdr_swid
  95  * Switch partition ID. Must be set to 0.
  96  */
  97 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
  98
  99 /* tx_hdr_control_tclass
 100  * Indicates if the packet should use the control TClass and not one
 101  * of the data TClasses.
 102  */
 103 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
 104
 105 /* tx_hdr_etclass
 106  * Egress TClass to be used on the egress device on the egress port.
 107  */
 108 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
 109
 110 /* tx_hdr_port_mid
 111  * Destination local port for unicast packets.
 112  * Destination multicast ID for multicast packets.
 113  *
 114  * Control packets are directed to a specific egress port, while data
 115  * packets are transmitted through the CPU port (0) into the switch partition,
 116  * where forwarding rules are applied.
 117  */
 118 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 119
 120 /* tx_hdr_fid
 121  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
 122  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
 123  * Valid for data packets only.
 124  */
 125 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
 126
 127 /* tx_hdr_type
 128  * 0 - Data packets
 129  * 6 - Control packets
 130  */
 131 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 132
 133 struct mlxsw_sp_mlxfw_dev {
 134         struct mlxfw_dev mlxfw_dev;
 135         struct mlxsw_sp *mlxsw_sp;
 136 };
 137
 138 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
 139                                     u16 component_index, u32 *p_max_size,
 140                                     u8 *p_align_bits, u16 *p_max_write_size)
 141 {
 142         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 143                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 144         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 145         char mcqi_pl[MLXSW_REG_MCQI_LEN];
 146         int err;
 147
 148         mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
 149         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
 150         if (err)
 151                 return err;
 152         mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
 153                               p_max_write_size);
 154
 155         *p_align_bits = max_t(u8, *p_align_bits, 2);
 156         *p_max_write_size = min_t(u16, *p_max_write_size,
 157                                   MLXSW_REG_MCDA_MAX_DATA_LEN);
 158         return 0;
 159 }
 160
 161 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 162 {
 163         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 164                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 165         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 166         char mcc_pl[MLXSW_REG_MCC_LEN];
 167         u8 control_state;
 168         int err;
 169
 170         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
 171         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 172         if (err)
 173                 return err;
 174
 175         mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
 176         if (control_state != MLXFW_FSM_STATE_IDLE)
 177                 return -EBUSY;
 178
 179         mlxsw_reg_mcc_pack(mcc_pl,
 180                            MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 181                            0, *fwhandle, 0);
 182         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 183 }
 184
 185 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
 186                                          u32 fwhandle, u16 component_index,
 187                                          u32 component_size)
 188 {
 189         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 190                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 191         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 192         char mcc_pl[MLXSW_REG_MCC_LEN];
 193
 194         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 195                            component_index, fwhandle, component_size);
 196         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 197 }
 198
 199 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
 200                                        u32 fwhandle, u8 *data, u16 size,
 201                                        u32 offset)
 202 {
 203         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 204                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 205         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 206         char mcda_pl[MLXSW_REG_MCDA_LEN];
 207
 208         mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
 209         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
 210 }
 211
 212 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
 213                                          u32 fwhandle, u16 component_index)
 214 {
 215         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 216                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 217         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 218         char mcc_pl[MLXSW_REG_MCC_LEN];
 219
 220         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 221                            component_index, fwhandle, 0);
 222         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 223 }
 224
 225 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 226 {
 227         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 228                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 229         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 230         char mcc_pl[MLXSW_REG_MCC_LEN];
 231
 232         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 233                            fwhandle, 0);
 234         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 235 }
 236
 237 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 238                                     enum mlxfw_fsm_state *fsm_state,
 239                                     enum mlxfw_fsm_state_err *fsm_state_err)
 240 {
 241         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 242                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 243         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 244         char mcc_pl[MLXSW_REG_MCC_LEN];
 245         u8 control_state;
 246         u8 error_code;
 247         int err;
 248
 249         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
 250         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 251         if (err)
 252                 return err;
 253
 254         mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
 255         *fsm_state = control_state;
 256         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 257                                MLXFW_FSM_STATE_ERR_MAX);
 258         return 0;
 259 }
 260
 261 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 262 {
 263         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 264                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 265         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 266         char mcc_pl[MLXSW_REG_MCC_LEN];
 267
 268         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
 269                            fwhandle, 0);
 270         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 271 }
 272
 273 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 274 {
 275         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 276                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 277         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 278         char mcc_pl[MLXSW_REG_MCC_LEN];
 279
 280         mlxsw_reg_mcc_pack(mcc_pl,
 281                            MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 282                            fwhandle, 0);
 283         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 284 }
 285
 286 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
 287         .component_query        = mlxsw_sp_component_query,
 288         .fsm_lock               = mlxsw_sp_fsm_lock,
 289         .fsm_component_update   = mlxsw_sp_fsm_component_update,
 290         .fsm_block_download     = mlxsw_sp_fsm_block_download,
 291         .fsm_component_verify   = mlxsw_sp_fsm_component_verify,
 292         .fsm_activate           = mlxsw_sp_fsm_activate,
 293         .fsm_query_state        = mlxsw_sp_fsm_query_state,
 294         .fsm_cancel             = mlxsw_sp_fsm_cancel,
 295         .fsm_release            = mlxsw_sp_fsm_release
 296 };
 297
 298 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
 299                                    const struct firmware *firmware)
 300 {
 301         struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
 302                 .mlxfw_dev = {
 303                         .ops = &mlxsw_sp_mlxfw_dev_ops,
 304                         .psid = mlxsw_sp->bus_info->psid,
 305                         .psid_size = strlen(mlxsw_sp->bus_info->psid),
 306                 },
 307                 .mlxsw_sp = mlxsw_sp
 308         };
 309         int err;
 310
 311         mlxsw_core_fw_flash_start(mlxsw_sp->core);
 312         err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
 313         mlxsw_core_fw_flash_end(mlxsw_sp->core);
 314
 315         return err;
 316 }
 317
 318 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
 319 {
 320         const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
 321         const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
 322         const char *fw_filename = mlxsw_sp->fw_filename;
 323         const struct firmware *firmware;
 324         int err;
 325
 326         /* Don't check if driver does not require it */
 327         if (!req_rev || !fw_filename)
 328                 return 0;
 329
 330         /* Validate driver & FW are compatible */
 331         if (rev->major != req_rev->major) {
 332                 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
 333                      rev->major, req_rev->major);
 334                 return -EINVAL;
 335         }
 336         if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
 337             MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
 338             (rev->minor > req_rev->minor ||
 339              (rev->minor == req_rev->minor &&
 340               rev->subminor >= req_rev->subminor)))
 341                 return 0;
 342
 343         dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
 344                  rev->major, rev->minor, rev->subminor);
 345         dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
 346                  fw_filename);
 347
 348         err = reject_firmware_direct(&firmware, fw_filename,
 349                                       mlxsw_sp->bus_info->dev);
 350         if (err) {
 351                 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
 352                         fw_filename);
 353                 return err;
 354         }
 355
 356         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
 357         release_firmware(firmware);
 358         if (err)
 359                 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
 360
 361         /* On FW flash success, tell the caller FW reset is needed
 362          * if current FW supports it.
 363          */
 364         if (rev->minor >= req_rev->can_reset_minor)
 365                 return err ? err : -EAGAIN;
 366         else
 367                 return 0;
 368 }
 369
 370 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
 371                               unsigned int counter_index, u64 *packets,
 372                               u64 *bytes)
 373 {
 374         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 375         int err;
 376
 377         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
 378                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 379         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 380         if (err)
 381                 return err;
 382         if (packets)
 383                 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
 384         if (bytes)
 385                 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
 386         return 0;
 387 }
 388
 389 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
 390                                        unsigned int counter_index)
 391 {
 392         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 393
 394         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
 395                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 396         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 397 }
 398
 399 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
 400                                 unsigned int *p_counter_index)
 401 {
 402         int err;
 403
 404         err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 405                                      p_counter_index);
 406         if (err)
 407                 return err;
 408         err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
 409         if (err)
 410                 goto err_counter_clear;
 411         return 0;
 412
 413 err_counter_clear:
 414         mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 415                               *p_counter_index);
 416         return err;
 417 }
 418
 419 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
 420                                 unsigned int counter_index)
 421 {
 422          mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 423                                counter_index);
 424 }
 425
 426 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
 427                                      const struct mlxsw_tx_info *tx_info)
 428 {
 429         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 430
 431         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 432
 433         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
 434         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 435         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 436         mlxsw_tx_hdr_swid_set(txhdr, 0);
 437         mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
 438         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 439         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 440 }
 441
 442 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
 443 {
 444         switch (state) {
 445         case BR_STATE_FORWARDING:
 446                 return MLXSW_REG_SPMS_STATE_FORWARDING;
 447         case BR_STATE_LEARNING:
 448                 return MLXSW_REG_SPMS_STATE_LEARNING;
 449         case BR_STATE_LISTENING: /* fall-through */
 450         case BR_STATE_DISABLED: /* fall-through */
 451         case BR_STATE_BLOCKING:
 452                 return MLXSW_REG_SPMS_STATE_DISCARDING;
 453         default:
 454                 BUG();
 455         }
 456 }
 457
 458 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 459                               u8 state)
 460 {
 461         enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
 462         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 463         char *spms_pl;
 464         int err;
 465
 466         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 467         if (!spms_pl)
 468                 return -ENOMEM;
 469         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
 470         mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
 471
 472         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
 473         kfree(spms_pl);
 474         return err;
 475 }
 476
 477 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
 478 {
 479         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 480         int err;
 481
 482         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
 483         if (err)
 484                 return err;
 485         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
 486         return 0;
 487 }
 488
 489 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
 490                                     bool enable, u32 rate)
 491 {
 492         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 493         char mpsc_pl[MLXSW_REG_MPSC_LEN];
 494
 495         mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
 496         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
 497 }
 498
 499 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
 500                                           bool is_up)
 501 {
 502         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 503         char paos_pl[MLXSW_REG_PAOS_LEN];
 504
 505         mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
 506                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 507                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 508         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
 509 }
 510
 511 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
 512                                       unsigned char *addr)
 513 {
 514         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 515         char ppad_pl[MLXSW_REG_PPAD_LEN];
 516
 517         mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
 518         mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
 519         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
 520 }
 521
 522 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
 523 {
 524         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 525         unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
 526
 527         ether_addr_copy(addr, mlxsw_sp->base_mac);
 528         addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
 529         return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
 530 }
 531
 532 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
 533 {
 534         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 535         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 536         int max_mtu;
 537         int err;
 538
 539         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 540         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
 541         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 542         if (err)
 543                 return err;
 544         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 545
 546         if (mtu > max_mtu)
 547                 return -EINVAL;
 548
 549         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
 550         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 551 }
 552
 553 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
 554 {
 555         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 556         char pspa_pl[MLXSW_REG_PSPA_LEN];
 557
 558         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
 559         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
 560 }
 561
 562 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
 563 {
 564         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 565         char svpe_pl[MLXSW_REG_SVPE_LEN];
 566
 567         mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
 568         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
 569 }
 570
 571 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 572                                    bool learn_enable)
 573 {
 574         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 575         char *spvmlr_pl;
 576         int err;
 577
 578         spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
 579         if (!spvmlr_pl)
 580                 return -ENOMEM;
 581         mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
 582                               learn_enable);
 583         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
 584         kfree(spvmlr_pl);
 585         return err;
 586 }
 587
 588 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
 589                                     u16 vid)
 590 {
 591         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 592         char spvid_pl[MLXSW_REG_SPVID_LEN];
 593
 594         mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
 595         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
 596 }
 597
 598 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
 599                                             bool allow)
 600 {
 601         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 602         char spaft_pl[MLXSW_REG_SPAFT_LEN];
 603
 604         mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
 605         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
 606 }
 607
 608 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
 609 {
 610         int err;
 611
 612         if (!vid) {
 613                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
 614                 if (err)
 615                         return err;
 616         } else {
 617                 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
 618                 if (err)
 619                         return err;
 620                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
 621                 if (err)
 622                         goto err_port_allow_untagged_set;
 623         }
 624
 625         mlxsw_sp_port->pvid = vid;
 626         return 0;
 627
 628 err_port_allow_untagged_set:
 629         __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
 630         return err;
 631 }
 632
 633 static int
 634 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
 635 {
 636         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 637         char sspr_pl[MLXSW_REG_SSPR_LEN];
 638
 639         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
 640         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
 641 }
 642
 643 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
 644                                          u8 local_port, u8 *p_module,
 645                                          u8 *p_width, u8 *p_lane)
 646 {
 647         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 648         int err;
 649
 650         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 651         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 652         if (err)
 653                 return err;
 654         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 655         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 656         *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
 657         return 0;
 658 }
 659
 660 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
 661                                     u8 module, u8 width, u8 lane)
 662 {
 663         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 664         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 665         int i;
 666
 667         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 668         mlxsw_reg_pmlp_width_set(pmlp_pl, width);
 669         for (i = 0; i < width; i++) {
 670                 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
 671                 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);  /* Rx & Tx */
 672         }
 673
 674         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 675 }
 676
 677 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
 678 {
 679         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 680         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 681
 682         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 683         mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
 684         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 685 }
 686
 687 static int mlxsw_sp_port_open(struct net_device *dev)
 688 {
 689         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 690         int err;
 691
 692         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
 693         if (err)
 694                 return err;
 695         netif_start_queue(dev);
 696         return 0;
 697 }
 698
 699 static int mlxsw_sp_port_stop(struct net_device *dev)
 700 {
 701         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 702
 703         netif_stop_queue(dev);
 704         return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
 705 }
 706
 707 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
 708                                       struct net_device *dev)
 709 {
 710         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 711         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 712         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
 713         const struct mlxsw_tx_info tx_info = {
 714                 .local_port = mlxsw_sp_port->local_port,
 715                 .is_emad = false,
 716         };
 717         u64 len;
 718         int err;
 719
 720         if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
 721                 return NETDEV_TX_BUSY;
 722
 723         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 724                 struct sk_buff *skb_orig = skb;
 725
 726                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 727                 if (!skb) {
 728                         this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 729                         dev_kfree_skb_any(skb_orig);
 730                         return NETDEV_TX_OK;
 731                 }
 732                 dev_consume_skb_any(skb_orig);
 733         }
 734
 735         if (eth_skb_pad(skb)) {
 736                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 737                 return NETDEV_TX_OK;
 738         }
 739
 740         mlxsw_sp_txhdr_construct(skb, &tx_info);
 741         /* TX header is consumed by HW on the way so we shouldn't count its
 742          * bytes as being sent.
 743          */
 744         len = skb->len - MLXSW_TXHDR_LEN;
 745
 746         /* Due to a race we might fail here because of a full queue. In that
 747          * unlikely case we simply drop the packet.
 748          */
 749         err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
 750
 751         if (!err) {
 752                 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
 753                 u64_stats_update_begin(&pcpu_stats->syncp);
 754                 pcpu_stats->tx_packets++;
 755                 pcpu_stats->tx_bytes += len;
 756                 u64_stats_update_end(&pcpu_stats->syncp);
 757         } else {
 758                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 759                 dev_kfree_skb_any(skb);
 760         }
 761         return NETDEV_TX_OK;
 762 }
 763
 764 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
 765 {
 766 }
 767
 768 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
 769 {
 770         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 771         struct sockaddr *addr = p;
 772         int err;
 773
 774         if (!is_valid_ether_addr(addr->sa_data))
 775                 return -EADDRNOTAVAIL;
 776
 777         err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
 778         if (err)
 779                 return err;
 780         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 781         return 0;
 782 }
 783
 784 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
 785                                          int mtu)
 786 {
 787         return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
 788 }
 789
 790 #define MLXSW_SP_CELL_FACTOR 2  /* 2 * cell_size / (IPG + cell_size + 1) */
 791
 792 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 793                                   u16 delay)
 794 {
 795         delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
 796                                                             BITS_PER_BYTE));
 797         return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
 798                                                                    mtu);
 799 }
 800
 801 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
 802  * Assumes 100m cable and maximum MTU.
 803  */
 804 #define MLXSW_SP_PAUSE_DELAY 58752
 805
 806 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 807                                      u16 delay, bool pfc, bool pause)
 808 {
 809         if (pfc)
 810                 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
 811         else if (pause)
 812                 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
 813         else
 814                 return 0;
 815 }
 816
 817 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
 818                                  bool lossy)
 819 {
 820         if (lossy)
 821                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
 822         else
 823                 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
 824                                                     thres);
 825 }
 826
 827 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
 828                                  u8 *prio_tc, bool pause_en,
 829                                  struct ieee_pfc *my_pfc)
 830 {
 831         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 832         u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
 833         u16 delay = !!my_pfc ? my_pfc->delay : 0;
 834         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 835         int i, j, err;
 836
 837         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
 838         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 839         if (err)
 840                 return err;
 841
 842         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 843                 bool configure = false;
 844                 bool pfc = false;
 845                 u16 thres_cells;
 846                 u16 delay_cells;
 847                 bool lossy;
 848
 849                 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
 850                         if (prio_tc[j] == i) {
 851                                 pfc = pfc_en & BIT(j);
 852                                 configure = true;
 853                                 break;
 854                         }
 855                 }
 856
 857                 if (!configure)
 858                         continue;
 859
 860                 lossy = !(pfc || pause_en);
 861                 thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
 862                 delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
 863                                                         pfc, pause_en);
 864                 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres_cells + delay_cells,
 865                                      thres_cells, lossy);
 866         }
 867
 868         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 869 }
 870
 871 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
 872                                       int mtu, bool pause_en)
 873 {
 874         u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
 875         bool dcb_en = !!mlxsw_sp_port->dcb.ets;
 876         struct ieee_pfc *my_pfc;
 877         u8 *prio_tc;
 878
 879         prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
 880         my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
 881
 882         return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
 883                                             pause_en, my_pfc);
 884 }
 885
 886 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
 887 {
 888         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 889         bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
 890         int err;
 891
 892         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
 893         if (err)
 894                 return err;
 895         err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
 896         if (err)
 897                 goto err_span_port_mtu_update;
 898         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
 899         if (err)
 900                 goto err_port_mtu_set;
 901         dev->mtu = mtu;
 902         return 0;
 903
 904 err_port_mtu_set:
 905         mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
 906 err_span_port_mtu_update:
 907         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
 908         return err;
 909 }
 910
 911 static int
 912 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
 913                              struct rtnl_link_stats64 *stats)
 914 {
 915         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 916         struct mlxsw_sp_port_pcpu_stats *p;
 917         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 918         u32 tx_dropped = 0;
 919         unsigned int start;
 920         int i;
 921
 922         for_each_possible_cpu(i) {
 923                 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
 924                 do {
 925                         start = u64_stats_fetch_begin_irq(&p->syncp);
 926                         rx_packets      = p->rx_packets;
 927                         rx_bytes        = p->rx_bytes;
 928                         tx_packets      = p->tx_packets;
 929                         tx_bytes        = p->tx_bytes;
 930                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 931
 932                 stats->rx_packets       += rx_packets;
 933                 stats->rx_bytes         += rx_bytes;
 934                 stats->tx_packets       += tx_packets;
 935                 stats->tx_bytes         += tx_bytes;
 936                 /* tx_dropped is u32, updated without syncp protection. */
 937                 tx_dropped      += p->tx_dropped;
 938         }
 939         stats->tx_dropped       = tx_dropped;
 940         return 0;
 941 }
 942
 943 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
 944 {
 945         switch (attr_id) {
 946         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 947                 return true;
 948         }
 949
 950         return false;
 951 }
 952
 953 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
 954                                            void *sp)
 955 {
 956         switch (attr_id) {
 957         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 958                 return mlxsw_sp_port_get_sw_stats64(dev, sp);
 959         }
 960
 961         return -EINVAL;
 962 }
 963
 964 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
 965                                        int prio, char *ppcnt_pl)
 966 {
 967         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 968         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 969
 970         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
 971         return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
 972 }
 973
 974 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
 975                                       struct rtnl_link_stats64 *stats)
 976 {
 977         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 978         int err;
 979
 980         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
 981                                           0, ppcnt_pl);
 982         if (err)
 983                 goto out;
 984
 985         stats->tx_packets =
 986                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
 987         stats->rx_packets =
 988                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
 989         stats->tx_bytes =
 990                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
 991         stats->rx_bytes =
 992                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
 993         stats->multicast =
 994                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
 995
 996         stats->rx_crc_errors =
 997                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
 998         stats->rx_frame_errors =
 999                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1000
1001         stats->rx_length_errors = (
1002                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1003                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1004                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1005
1006         stats->rx_errors = (stats->rx_crc_errors +
1007                 stats->rx_frame_errors + stats->rx_length_errors);
1008
1009 out:
1010         return err;
1011 }
1012
1013 static void
1014 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1015                             struct mlxsw_sp_port_xstats *xstats)
1016 {
1017         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1018         int err, i;
1019
1020         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1021                                           ppcnt_pl);
1022         if (!err)
1023                 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1024
1025         for (i = 0; i < TC_MAX_QUEUE; i++) {
1026                 err = mlxsw_sp_port_get_stats_raw(dev,
1027                                                   MLXSW_REG_PPCNT_TC_CONG_TC,
1028                                                   i, ppcnt_pl);
1029                 if (!err)
1030                         xstats->wred_drop[i] =
1031                                 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1032
1033                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034                                                   i, ppcnt_pl);
1035                 if (err)
1036                         continue;
1037
1038                 xstats->backlog[i] =
1039                         mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1040                 xstats->tail_drop[i] =
1041                         mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1042         }
1043
1044         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1045                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1046                                                   i, ppcnt_pl);
1047                 if (err)
1048                         continue;
1049
1050                 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1051                 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1052         }
1053 }
1054
1055 static void update_stats_cache(struct work_struct *work)
1056 {
1057         struct mlxsw_sp_port *mlxsw_sp_port =
1058                 container_of(work, struct mlxsw_sp_port,
1059                              periodic_hw_stats.update_dw.work);
1060
1061         if (!netif_carrier_ok(mlxsw_sp_port->dev))
1062                 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
1063                  * necessary when port goes down.
1064                  */
1065                 goto out;
1066
1067         mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1068                                    &mlxsw_sp_port->periodic_hw_stats.stats);
1069         mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1070                                     &mlxsw_sp_port->periodic_hw_stats.xstats);
1071
1072 out:
1073         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1074                                MLXSW_HW_STATS_UPDATE_TIME);
1075 }
1076
1077 /* Return the stats from a cache that is updated periodically,
1078  * as this function might get called in an atomic context.
1079  */
1080 static void
1081 mlxsw_sp_port_get_stats64(struct net_device *dev,
1082                           struct rtnl_link_stats64 *stats)
1083 {
1084         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1085
1086         memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1087 }
1088
1089 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1090                                     u16 vid_begin, u16 vid_end,
1091                                     bool is_member, bool untagged)
1092 {
1093         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1094         char *spvm_pl;
1095         int err;
1096
1097         spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1098         if (!spvm_pl)
1099                 return -ENOMEM;
1100
1101         mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1102                             vid_end, is_member, untagged);
1103         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1104         kfree(spvm_pl);
1105         return err;
1106 }
1107
1108 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1109                            u16 vid_end, bool is_member, bool untagged)
1110 {
1111         u16 vid, vid_e;
1112         int err;
1113
1114         for (vid = vid_begin; vid <= vid_end;
1115              vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1116                 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1117                             vid_end);
1118
1119                 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1120                                                is_member, untagged);
1121                 if (err)
1122                         return err;
1123         }
1124
1125         return 0;
1126 }
1127
1128 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
1129 {
1130         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1131
1132         list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1133                                  &mlxsw_sp_port->vlans_list, list)
1134                 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1135 }
1136
1137 static struct mlxsw_sp_port_vlan *
1138 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1139 {
1140         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1141         bool untagged = vid == 1;
1142         int err;
1143
1144         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1145         if (err)
1146                 return ERR_PTR(err);
1147
1148         mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1149         if (!mlxsw_sp_port_vlan) {
1150                 err = -ENOMEM;
1151                 goto err_port_vlan_alloc;
1152         }
1153
1154         mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1155         mlxsw_sp_port_vlan->ref_count = 1;
1156         mlxsw_sp_port_vlan->vid = vid;
1157         list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1158
1159         return mlxsw_sp_port_vlan;
1160
1161 err_port_vlan_alloc:
1162         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1163         return ERR_PTR(err);
1164 }
1165
1166 static void
1167 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1168 {
1169         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1170         u16 vid = mlxsw_sp_port_vlan->vid;
1171
1172         list_del(&mlxsw_sp_port_vlan->list);
1173         kfree(mlxsw_sp_port_vlan);
1174         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1175 }
1176
1177 struct mlxsw_sp_port_vlan *
1178 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1179 {
1180         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1181
1182         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1183         if (mlxsw_sp_port_vlan) {
1184                 mlxsw_sp_port_vlan->ref_count++;
1185                 return mlxsw_sp_port_vlan;
1186         }
1187
1188         return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1189 }
1190
1191 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1192 {
1193         struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1194
1195         if (--mlxsw_sp_port_vlan->ref_count != 0)
1196                 return;
1197
1198         if (mlxsw_sp_port_vlan->bridge_port)
1199                 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1200         else if (fid)
1201                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1202
1203         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1204 }
1205
1206 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1207                                  __be16 __always_unused proto, u16 vid)
1208 {
1209         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1210
1211         /* VLAN 0 is added to HW filter when device goes up, but it is
1212          * reserved in our case, so simply return.
1213          */
1214         if (!vid)
1215                 return 0;
1216
1217         return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
1218 }
1219
1220 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1221                                   __be16 __always_unused proto, u16 vid)
1222 {
1223         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1224         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1225
1226         /* VLAN 0 is removed from HW filter when device goes down, but
1227          * it is reserved in our case, so simply return.
1228          */
1229         if (!vid)
1230                 return 0;
1231
1232         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1233         if (!mlxsw_sp_port_vlan)
1234                 return 0;
1235         mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1236
1237         return 0;
1238 }
1239
1240 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1241                                             size_t len)
1242 {
1243         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1244
1245         return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1246                                                   mlxsw_sp_port->local_port,
1247                                                   name, len);
1248 }
1249
1250 static struct mlxsw_sp_port_mall_tc_entry *
1251 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1252                                  unsigned long cookie) {
1253         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1254
1255         list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1256                 if (mall_tc_entry->cookie == cookie)
1257                         return mall_tc_entry;
1258
1259         return NULL;
1260 }
1261
1262 static int
1263 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1264                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1265                                       const struct tc_action *a,
1266                                       bool ingress)
1267 {
1268         enum mlxsw_sp_span_type span_type;
1269         struct net_device *to_dev;
1270
1271         to_dev = tcf_mirred_dev(a);
1272         if (!to_dev) {
1273                 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1274                 return -EINVAL;
1275         }
1276
1277         mirror->ingress = ingress;
1278         span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1279         return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
1280                                         true, &mirror->span_id);
1281 }
1282
1283 static void
1284 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1285                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1286 {
1287         enum mlxsw_sp_span_type span_type;
1288
1289         span_type = mirror->ingress ?
1290                         MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1291         mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1292                                  span_type, true);
1293 }
1294
1295 static int
1296 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1297                                       struct tc_cls_matchall_offload *cls,
1298                                       const struct tc_action *a,
1299                                       bool ingress)
1300 {
1301         int err;
1302
1303         if (!mlxsw_sp_port->sample)
1304                 return -EOPNOTSUPP;
1305         if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1306                 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1307                 return -EEXIST;
1308         }
1309         if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1310                 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1311                 return -EOPNOTSUPP;
1312         }
1313
1314         rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1315                            tcf_sample_psample_group(a));
1316         mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1317         mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1318         mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1319
1320         err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1321         if (err)
1322                 goto err_port_sample_set;
1323         return 0;
1324
1325 err_port_sample_set:
1326         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1327         return err;
1328 }
1329
1330 static void
1331 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1332 {
1333         if (!mlxsw_sp_port->sample)
1334                 return;
1335
1336         mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1337         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1338 }
1339
1340 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1341                                           struct tc_cls_matchall_offload *f,
1342                                           bool ingress)
1343 {
1344         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1345         __be16 protocol = f->common.protocol;
1346         const struct tc_action *a;
1347         LIST_HEAD(actions);
1348         int err;
1349
1350         if (!tcf_exts_has_one_action(f->exts)) {
1351                 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1352                 return -EOPNOTSUPP;
1353         }
1354
1355         mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1356         if (!mall_tc_entry)
1357                 return -ENOMEM;
1358         mall_tc_entry->cookie = f->cookie;
1359
1360         a = tcf_exts_first_action(f->exts);
1361
1362         if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1363                 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1364
1365                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1366                 mirror = &mall_tc_entry->mirror;
1367                 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1368                                                             mirror, a, ingress);
1369         } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1370                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1371                 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1372                                                             a, ingress);
1373         } else {
1374                 err = -EOPNOTSUPP;
1375         }
1376
1377         if (err)
1378                 goto err_add_action;
1379
1380         list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1381         return 0;
1382
1383 err_add_action:
1384         kfree(mall_tc_entry);
1385         return err;
1386 }
1387
1388 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1389                                            struct tc_cls_matchall_offload *f)
1390 {
1391         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1392
1393         mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1394                                                          f->cookie);
1395         if (!mall_tc_entry) {
1396                 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1397                 return;
1398         }
1399         list_del(&mall_tc_entry->list);
1400
1401         switch (mall_tc_entry->type) {
1402         case MLXSW_SP_PORT_MALL_MIRROR:
1403                 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1404                                                       &mall_tc_entry->mirror);
1405                 break;
1406         case MLXSW_SP_PORT_MALL_SAMPLE:
1407                 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1408                 break;
1409         default:
1410                 WARN_ON(1);
1411         }
1412
1413         kfree(mall_tc_entry);
1414 }
1415
1416 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1417                                           struct tc_cls_matchall_offload *f,
1418                                           bool ingress)
1419 {
1420         switch (f->command) {
1421         case TC_CLSMATCHALL_REPLACE:
1422                 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1423                                                       ingress);
1424         case TC_CLSMATCHALL_DESTROY:
1425                 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1426                 return 0;
1427         default:
1428                 return -EOPNOTSUPP;
1429         }
1430 }
1431
1432 static int
1433 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1434                              struct tc_cls_flower_offload *f)
1435 {
1436         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1437
1438         switch (f->command) {
1439         case TC_CLSFLOWER_REPLACE:
1440                 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1441         case TC_CLSFLOWER_DESTROY:
1442                 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1443                 return 0;
1444         case TC_CLSFLOWER_STATS:
1445                 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1446         case TC_CLSFLOWER_TMPLT_CREATE:
1447                 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1448         case TC_CLSFLOWER_TMPLT_DESTROY:
1449                 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1450                 return 0;
1451         default:
1452                 return -EOPNOTSUPP;
1453         }
1454 }
1455
1456 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1457                                                void *type_data,
1458                                                void *cb_priv, bool ingress)
1459 {
1460         struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1461
1462         switch (type) {
1463         case TC_SETUP_CLSMATCHALL:
1464                 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1465                                                    type_data))
1466                         return -EOPNOTSUPP;
1467
1468                 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1469                                                       ingress);
1470         case TC_SETUP_CLSFLOWER:
1471                 return 0;
1472         default:
1473                 return -EOPNOTSUPP;
1474         }
1475 }
1476
1477 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1478                                                   void *type_data,
1479                                                   void *cb_priv)
1480 {
1481         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1482                                                    cb_priv, true);
1483 }
1484
1485 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1486                                                   void *type_data,
1487                                                   void *cb_priv)
1488 {
1489         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1490                                                    cb_priv, false);
1491 }
1492
1493 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1494                                              void *type_data, void *cb_priv)
1495 {
1496         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1497
1498         switch (type) {
1499         case TC_SETUP_CLSMATCHALL:
1500                 return 0;
1501         case TC_SETUP_CLSFLOWER:
1502                 if (mlxsw_sp_acl_block_disabled(acl_block))
1503                         return -EOPNOTSUPP;
1504
1505                 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1506         default:
1507                 return -EOPNOTSUPP;
1508         }
1509 }
1510
1511 static int
1512 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1513                                     struct tcf_block *block, bool ingress,
1514                                     struct netlink_ext_ack *extack)
1515 {
1516         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1517         struct mlxsw_sp_acl_block *acl_block;
1518         struct tcf_block_cb *block_cb;
1519         int err;
1520
1521         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1522                                        mlxsw_sp);
1523         if (!block_cb) {
1524                 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1525                 if (!acl_block)
1526                         return -ENOMEM;
1527                 block_cb = __tcf_block_cb_register(block,
1528                                                    mlxsw_sp_setup_tc_block_cb_flower,
1529                                                    mlxsw_sp, acl_block, extack);
1530                 if (IS_ERR(block_cb)) {
1531                         err = PTR_ERR(block_cb);
1532                         goto err_cb_register;
1533                 }
1534         } else {
1535                 acl_block = tcf_block_cb_priv(block_cb);
1536         }
1537         tcf_block_cb_incref(block_cb);
1538         err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1539                                       mlxsw_sp_port, ingress);
1540         if (err)
1541                 goto err_block_bind;
1542
1543         if (ingress)
1544                 mlxsw_sp_port->ing_acl_block = acl_block;
1545         else
1546                 mlxsw_sp_port->eg_acl_block = acl_block;
1547
1548         return 0;
1549
1550 err_block_bind:
1551         if (!tcf_block_cb_decref(block_cb)) {
1552                 __tcf_block_cb_unregister(block, block_cb);
1553 err_cb_register:
1554                 mlxsw_sp_acl_block_destroy(acl_block);
1555         }
1556         return err;
1557 }
1558
1559 static void
1560 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1561                                       struct tcf_block *block, bool ingress)
1562 {
1563         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1564         struct mlxsw_sp_acl_block *acl_block;
1565         struct tcf_block_cb *block_cb;
1566         int err;
1567
1568         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1569                                        mlxsw_sp);
1570         if (!block_cb)
1571                 return;
1572
1573         if (ingress)
1574                 mlxsw_sp_port->ing_acl_block = NULL;
1575         else
1576                 mlxsw_sp_port->eg_acl_block = NULL;
1577
1578         acl_block = tcf_block_cb_priv(block_cb);
1579         err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1580                                         mlxsw_sp_port, ingress);
1581         if (!err && !tcf_block_cb_decref(block_cb)) {
1582                 __tcf_block_cb_unregister(block, block_cb);
1583                 mlxsw_sp_acl_block_destroy(acl_block);
1584         }
1585 }
1586
1587 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1588                                    struct tc_block_offload *f)
1589 {
1590         tc_setup_cb_t *cb;
1591         bool ingress;
1592         int err;
1593
1594         if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1595                 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1596                 ingress = true;
1597         } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1598                 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1599                 ingress = false;
1600         } else {
1601                 return -EOPNOTSUPP;
1602         }
1603
1604         switch (f->command) {
1605         case TC_BLOCK_BIND:
1606                 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1607                                             mlxsw_sp_port, f->extack);
1608                 if (err)
1609                         return err;
1610                 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1611                                                           f->block, ingress,
1612                                                           f->extack);
1613                 if (err) {
1614                         tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1615                         return err;
1616                 }
1617                 return 0;
1618         case TC_BLOCK_UNBIND:
1619                 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1620                                                       f->block, ingress);
1621                 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1622                 return 0;
1623         default:
1624                 return -EOPNOTSUPP;
1625         }
1626 }
1627
1628 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1629                              void *type_data)
1630 {
1631         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1632
1633         switch (type) {
1634         case TC_SETUP_BLOCK:
1635                 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1636         case TC_SETUP_QDISC_RED:
1637                 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1638         case TC_SETUP_QDISC_PRIO:
1639                 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1640         default:
1641                 return -EOPNOTSUPP;
1642         }
1643 }
1644
1645
1646 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1647 {
1648         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1649
1650         if (!enable) {
1651                 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1652                     mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1653                     !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1654                         netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1655                         return -EINVAL;
1656                 }
1657                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1658                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1659         } else {
1660                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1661                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1662         }
1663         return 0;
1664 }
1665
1666 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1667
1668 static int mlxsw_sp_handle_feature(struct net_device *dev,
1669                                    netdev_features_t wanted_features,
1670                                    netdev_features_t feature,
1671                                    mlxsw_sp_feature_handler feature_handler)
1672 {
1673         netdev_features_t changes = wanted_features ^ dev->features;
1674         bool enable = !!(wanted_features & feature);
1675         int err;
1676
1677         if (!(changes & feature))
1678                 return 0;
1679
1680         err = feature_handler(dev, enable);
1681         if (err) {
1682                 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1683                            enable ? "Enable" : "Disable", &feature, err);
1684                 return err;
1685         }
1686
1687         if (enable)
1688                 dev->features |= feature;
1689         else
1690                 dev->features &= ~feature;
1691
1692         return 0;
1693 }
1694 static int mlxsw_sp_set_features(struct net_device *dev,
1695                                  netdev_features_t features)
1696 {
1697         return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1698                                        mlxsw_sp_feature_hw_tc);
1699 }
1700
1701 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1702         .ndo_open               = mlxsw_sp_port_open,
1703         .ndo_stop               = mlxsw_sp_port_stop,
1704         .ndo_start_xmit         = mlxsw_sp_port_xmit,
1705         .ndo_setup_tc           = mlxsw_sp_setup_tc,
1706         .ndo_set_rx_mode        = mlxsw_sp_set_rx_mode,
1707         .ndo_set_mac_address    = mlxsw_sp_port_set_mac_address,
1708         .ndo_change_mtu         = mlxsw_sp_port_change_mtu,
1709         .ndo_get_stats64        = mlxsw_sp_port_get_stats64,
1710         .ndo_has_offload_stats  = mlxsw_sp_port_has_offload_stats,
1711         .ndo_get_offload_stats  = mlxsw_sp_port_get_offload_stats,
1712         .ndo_vlan_rx_add_vid    = mlxsw_sp_port_add_vid,
1713         .ndo_vlan_rx_kill_vid   = mlxsw_sp_port_kill_vid,
1714         .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1715         .ndo_set_features       = mlxsw_sp_set_features,
1716 };
1717
1718 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1719                                       struct ethtool_drvinfo *drvinfo)
1720 {
1721         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1722         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1723
1724         strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1725                 sizeof(drvinfo->driver));
1726         strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1727                 sizeof(drvinfo->version));
1728         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1729                  "%d.%d.%d",
1730                  mlxsw_sp->bus_info->fw_rev.major,
1731                  mlxsw_sp->bus_info->fw_rev.minor,
1732                  mlxsw_sp->bus_info->fw_rev.subminor);
1733         strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1734                 sizeof(drvinfo->bus_info));
1735 }
1736
1737 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1738                                          struct ethtool_pauseparam *pause)
1739 {
1740         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1741
1742         pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1743         pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1744 }
1745
1746 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1747                                    struct ethtool_pauseparam *pause)
1748 {
1749         char pfcc_pl[MLXSW_REG_PFCC_LEN];
1750
1751         mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1752         mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1753         mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1754
1755         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1756                                pfcc_pl);
1757 }
1758
1759 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1760                                         struct ethtool_pauseparam *pause)
1761 {
1762         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1763         bool pause_en = pause->tx_pause || pause->rx_pause;
1764         int err;
1765
1766         if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1767                 netdev_err(dev, "PFC already enabled on port\n");
1768                 return -EINVAL;
1769         }
1770
1771         if (pause->autoneg) {
1772                 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1773                 return -EINVAL;
1774         }
1775
1776         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1777         if (err) {
1778                 netdev_err(dev, "Failed to configure port's headroom\n");
1779                 return err;
1780         }
1781
1782         err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1783         if (err) {
1784                 netdev_err(dev, "Failed to set PAUSE parameters\n");
1785                 goto err_port_pause_configure;
1786         }
1787
1788         mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1789         mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1790
1791         return 0;
1792
1793 err_port_pause_configure:
1794         pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1795         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1796         return err;
1797 }
1798
1799 struct mlxsw_sp_port_hw_stats {
1800         char str[ETH_GSTRING_LEN];
1801         u64 (*getter)(const char *payload);
1802         bool cells_bytes;
1803 };
1804
1805 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1806         {
1807                 .str = "a_frames_transmitted_ok",
1808                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1809         },
1810         {
1811                 .str = "a_frames_received_ok",
1812                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1813         },
1814         {
1815                 .str = "a_frame_check_sequence_errors",
1816                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1817         },
1818         {
1819                 .str = "a_alignment_errors",
1820                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1821         },
1822         {
1823                 .str = "a_octets_transmitted_ok",
1824                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1825         },
1826         {
1827                 .str = "a_octets_received_ok",
1828                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1829         },
1830         {
1831                 .str = "a_multicast_frames_xmitted_ok",
1832                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1833         },
1834         {
1835                 .str = "a_broadcast_frames_xmitted_ok",
1836                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1837         },
1838         {
1839                 .str = "a_multicast_frames_received_ok",
1840                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1841         },
1842         {
1843                 .str = "a_broadcast_frames_received_ok",
1844                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1845         },
1846         {
1847                 .str = "a_in_range_length_errors",
1848                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1849         },
1850         {
1851                 .str = "a_out_of_range_length_field",
1852                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1853         },
1854         {
1855                 .str = "a_frame_too_long_errors",
1856                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1857         },
1858         {
1859                 .str = "a_symbol_error_during_carrier",
1860                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1861         },
1862         {
1863                 .str = "a_mac_control_frames_transmitted",
1864                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1865         },
1866         {
1867                 .str = "a_mac_control_frames_received",
1868                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1869         },
1870         {
1871                 .str = "a_unsupported_opcodes_received",
1872                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1873         },
1874         {
1875                 .str = "a_pause_mac_ctrl_frames_received",
1876                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1877         },
1878         {
1879                 .str = "a_pause_mac_ctrl_frames_xmitted",
1880                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1881         },
1882 };
1883
1884 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1885
1886 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
1887         {
1888                 .str = "ether_pkts64octets",
1889                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
1890         },
1891         {
1892                 .str = "ether_pkts65to127octets",
1893                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
1894         },
1895         {
1896                 .str = "ether_pkts128to255octets",
1897                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
1898         },
1899         {
1900                 .str = "ether_pkts256to511octets",
1901                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
1902         },
1903         {
1904                 .str = "ether_pkts512to1023octets",
1905                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
1906         },
1907         {
1908                 .str = "ether_pkts1024to1518octets",
1909                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
1910         },
1911         {
1912                 .str = "ether_pkts1519to2047octets",
1913                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
1914         },
1915         {
1916                 .str = "ether_pkts2048to4095octets",
1917                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
1918         },
1919         {
1920                 .str = "ether_pkts4096to8191octets",
1921                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
1922         },
1923         {
1924                 .str = "ether_pkts8192to10239octets",
1925                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
1926         },
1927 };
1928
1929 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
1930         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
1931
1932 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1933         {
1934                 .str = "rx_octets_prio",
1935                 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1936         },
1937         {
1938                 .str = "rx_frames_prio",
1939                 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1940         },
1941         {
1942                 .str = "tx_octets_prio",
1943                 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1944         },
1945         {
1946                 .str = "tx_frames_prio",
1947                 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1948         },
1949         {
1950                 .str = "rx_pause_prio",
1951                 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1952         },
1953         {
1954                 .str = "rx_pause_duration_prio",
1955                 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1956         },
1957         {
1958                 .str = "tx_pause_prio",
1959                 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1960         },
1961         {
1962                 .str = "tx_pause_duration_prio",
1963                 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1964         },
1965 };
1966
1967 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1968
1969 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1970         {
1971                 .str = "tc_transmit_queue_tc",
1972                 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1973                 .cells_bytes = true,
1974         },
1975         {
1976                 .str = "tc_no_buffer_discard_uc_tc",
1977                 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1978         },
1979 };
1980
1981 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1982
1983 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1984                                          MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
1985                                          (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
1986                                           IEEE_8021QAZ_MAX_TCS) + \
1987                                          (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
1988                                           TC_MAX_QUEUE))
1989
1990 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1991 {
1992         int i;
1993
1994         for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1995                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
1996                          mlxsw_sp_port_hw_prio_stats[i].str, prio);
1997                 *p += ETH_GSTRING_LEN;
1998         }
1999 }
2000
2001 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2002 {
2003         int i;
2004
2005         for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2006                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2007                          mlxsw_sp_port_hw_tc_stats[i].str, tc);
2008                 *p += ETH_GSTRING_LEN;
2009         }
2010 }
2011
2012 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2013                                       u32 stringset, u8 *data)
2014 {
2015         u8 *p = data;
2016         int i;
2017
2018         switch (stringset) {
2019         case ETH_SS_STATS:
2020                 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2021                         memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2022                                ETH_GSTRING_LEN);
2023                         p += ETH_GSTRING_LEN;
2024                 }
2025                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2026                         memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2027                                ETH_GSTRING_LEN);
2028                         p += ETH_GSTRING_LEN;
2029                 }
2030
2031                 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2032                         mlxsw_sp_port_get_prio_strings(&p, i);
2033
2034                 for (i = 0; i < TC_MAX_QUEUE; i++)
2035                         mlxsw_sp_port_get_tc_strings(&p, i);
2036
2037                 break;
2038         }
2039 }
2040
2041 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2042                                      enum ethtool_phys_id_state state)
2043 {
2044         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2045         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2046         char mlcr_pl[MLXSW_REG_MLCR_LEN];
2047         bool active;
2048
2049         switch (state) {
2050         case ETHTOOL_ID_ACTIVE:
2051                 active = true;
2052                 break;
2053         case ETHTOOL_ID_INACTIVE:
2054                 active = false;
2055                 break;
2056         default:
2057                 return -EOPNOTSUPP;
2058         }
2059
2060         mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2061         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2062 }
2063
2064 static int
2065 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2066                                int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2067 {
2068         switch (grp) {
2069         case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2070                 *p_hw_stats = mlxsw_sp_port_hw_stats;
2071                 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2072                 break;
2073         case MLXSW_REG_PPCNT_RFC_2819_CNT:
2074                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2075                 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2076                 break;
2077         case MLXSW_REG_PPCNT_PRIO_CNT:
2078                 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2079                 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2080                 break;
2081         case MLXSW_REG_PPCNT_TC_CNT:
2082                 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2083                 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2084                 break;
2085         default:
2086                 WARN_ON(1);
2087                 return -EOPNOTSUPP;
2088         }
2089         return 0;
2090 }
2091
2092 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2093                                       enum mlxsw_reg_ppcnt_grp grp, int prio,
2094                                       u64 *data, int data_index)
2095 {
2096         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2097         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2098         struct mlxsw_sp_port_hw_stats *hw_stats;
2099         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2100         int i, len;
2101         int err;
2102
2103         err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2104         if (err)
2105                 return;
2106         mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2107         for (i = 0; i < len; i++) {
2108                 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2109                 if (!hw_stats[i].cells_bytes)
2110                         continue;
2111                 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2112                                                             data[data_index + i]);
2113         }
2114 }
2115
2116 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2117                                     struct ethtool_stats *stats, u64 *data)
2118 {
2119         int i, data_index = 0;
2120
2121         /* IEEE 802.3 Counters */
2122         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2123                                   data, data_index);
2124         data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2125
2126         /* RFC 2819 Counters */
2127         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2128                                   data, data_index);
2129         data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2130
2131         /* Per-Priority Counters */
2132         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2133                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2134                                           data, data_index);
2135                 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2136         }
2137
2138         /* Per-TC Counters */
2139         for (i = 0; i < TC_MAX_QUEUE; i++) {
2140                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2141                                           data, data_index);
2142                 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2143         }
2144 }
2145
2146 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2147 {
2148         switch (sset) {
2149         case ETH_SS_STATS:
2150                 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
2151         default:
2152                 return -EOPNOTSUPP;
2153         }
2154 }
2155
2156 struct mlxsw_sp_port_link_mode {
2157         enum ethtool_link_mode_bit_indices mask_ethtool;
2158         u32 mask;
2159         u32 speed;
2160 };
2161
2162 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2163         {
2164                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2165                 .mask_ethtool   = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2166                 .speed          = SPEED_100,
2167         },
2168         {
2169                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2170                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2171                 .mask_ethtool   = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2172                 .speed          = SPEED_1000,
2173         },
2174         {
2175                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2176                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2177                 .speed          = SPEED_10000,
2178         },
2179         {
2180                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2181                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2182                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2183                 .speed          = SPEED_10000,
2184         },
2185         {
2186                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2187                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2188                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2189                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2190                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2191                 .speed          = SPEED_10000,
2192         },
2193         {
2194                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2195                 .mask_ethtool   = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2196                 .speed          = SPEED_20000,
2197         },
2198         {
2199                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2200                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2201                 .speed          = SPEED_40000,
2202         },
2203         {
2204                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2205                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2206                 .speed          = SPEED_40000,
2207         },
2208         {
2209                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2210                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2211                 .speed          = SPEED_40000,
2212         },
2213         {
2214                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2215                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2216                 .speed          = SPEED_40000,
2217         },
2218         {
2219                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2220                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2221                 .speed          = SPEED_25000,
2222         },
2223         {
2224                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2225                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2226                 .speed          = SPEED_25000,
2227         },
2228         {
2229                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2230                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2231                 .speed          = SPEED_25000,
2232         },
2233         {
2234                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2235                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2236                 .speed          = SPEED_25000,
2237         },
2238         {
2239                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2240                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2241                 .speed          = SPEED_50000,
2242         },
2243         {
2244                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2245                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2246                 .speed          = SPEED_50000,
2247         },
2248         {
2249                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2250                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2251                 .speed          = SPEED_50000,
2252         },
2253         {
2254                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2255                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2256                 .speed          = SPEED_56000,
2257         },
2258         {
2259                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2260                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2261                 .speed          = SPEED_56000,
2262         },
2263         {
2264                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2265                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2266                 .speed          = SPEED_56000,
2267         },
2268         {
2269                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2270                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2271                 .speed          = SPEED_56000,
2272         },
2273         {
2274                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2275                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2276                 .speed          = SPEED_100000,
2277         },
2278         {
2279                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2280                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2281                 .speed          = SPEED_100000,
2282         },
2283         {
2284                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2285                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2286                 .speed          = SPEED_100000,
2287         },
2288         {
2289                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2290                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2291                 .speed          = SPEED_100000,
2292         },
2293 };
2294
2295 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2296
2297 static void
2298 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2299                                   struct ethtool_link_ksettings *cmd)
2300 {
2301         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2302                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2303                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2304                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2305                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2306                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2307                 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2308
2309         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2310                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2311                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2312                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2313                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2314                 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2315 }
2316
2317 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2318 {
2319         int i;
2320
2321         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2322                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2323                         __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2324                                   mode);
2325         }
2326 }
2327
2328 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2329                                             struct ethtool_link_ksettings *cmd)
2330 {
2331         u32 speed = SPEED_UNKNOWN;
2332         u8 duplex = DUPLEX_UNKNOWN;
2333         int i;
2334
2335         if (!carrier_ok)
2336                 goto out;
2337
2338         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2339                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2340                         speed = mlxsw_sp_port_link_mode[i].speed;
2341                         duplex = DUPLEX_FULL;
2342                         break;
2343                 }
2344         }
2345 out:
2346         cmd->base.speed = speed;
2347         cmd->base.duplex = duplex;
2348 }
2349
2350 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2351 {
2352         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2353                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2354                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2355                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2356                 return PORT_FIBRE;
2357
2358         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2359                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2360                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2361                 return PORT_DA;
2362
2363         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2364                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2365                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2366                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2367                 return PORT_NONE;
2368
2369         return PORT_OTHER;
2370 }
2371
2372 static u32
2373 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2374 {
2375         u32 ptys_proto = 0;
2376         int i;
2377
2378         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2379                 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2380                              cmd->link_modes.advertising))
2381                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2382         }
2383         return ptys_proto;
2384 }
2385
2386 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2387 {
2388         u32 ptys_proto = 0;
2389         int i;
2390
2391         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2392                 if (speed == mlxsw_sp_port_link_mode[i].speed)
2393                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2394         }
2395         return ptys_proto;
2396 }
2397
2398 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2399 {
2400         u32 ptys_proto = 0;
2401         int i;
2402
2403         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2404                 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2405                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2406         }
2407         return ptys_proto;
2408 }
2409
2410 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2411                                              struct ethtool_link_ksettings *cmd)
2412 {
2413         ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2414         ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2415         ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2416
2417         mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2418         mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2419 }
2420
2421 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2422                                              struct ethtool_link_ksettings *cmd)
2423 {
2424         if (!autoneg)
2425                 return;
2426
2427         ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2428         mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2429 }
2430
2431 static void
2432 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2433                                     struct ethtool_link_ksettings *cmd)
2434 {
2435         if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2436                 return;
2437
2438         ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2439         mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2440 }
2441
2442 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2443                                             struct ethtool_link_ksettings *cmd)
2444 {
2445         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2446         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2447         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2448         char ptys_pl[MLXSW_REG_PTYS_LEN];
2449         u8 autoneg_status;
2450         bool autoneg;
2451         int err;
2452
2453         autoneg = mlxsw_sp_port->link.autoneg;
2454         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2455         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2456         if (err)
2457                 return err;
2458         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2459                                   &eth_proto_oper);
2460
2461         mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2462
2463         mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2464
2465         eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2466         autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2467         mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2468
2469         cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2470         cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2471         mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2472                                         cmd);
2473
2474         return 0;
2475 }
2476
2477 static int
2478 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2479                                  const struct ethtool_link_ksettings *cmd)
2480 {
2481         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2482         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2483         char ptys_pl[MLXSW_REG_PTYS_LEN];
2484         u32 eth_proto_cap, eth_proto_new;
2485         bool autoneg;
2486         int err;
2487
2488         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2489         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2490         if (err)
2491                 return err;
2492         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2493
2494         autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2495         if (!autoneg && cmd->base.speed == SPEED_56000) {
2496                 netdev_err(dev, "56G not supported with autoneg off\n");
2497                 return -EINVAL;
2498         }
2499         eth_proto_new = autoneg ?
2500                 mlxsw_sp_to_ptys_advert_link(cmd) :
2501                 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2502
2503         eth_proto_new = eth_proto_new & eth_proto_cap;
2504         if (!eth_proto_new) {
2505                 netdev_err(dev, "No supported speed requested\n");
2506                 return -EINVAL;
2507         }
2508
2509         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2510                                 eth_proto_new, autoneg);
2511         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2512         if (err)
2513                 return err;
2514
2515         mlxsw_sp_port->link.autoneg = autoneg;
2516
2517         if (!netif_running(dev))
2518                 return 0;
2519
2520         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2521         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2522
2523         return 0;
2524 }
2525
2526 static int mlxsw_sp_flash_device(struct net_device *dev,
2527                                  struct ethtool_flash *flash)
2528 {
2529         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2530         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2531         const struct firmware *firmware;
2532         int err;
2533
2534         if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2535                 return -EOPNOTSUPP;
2536
2537         dev_hold(dev);
2538         rtnl_unlock();
2539
2540         err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2541         if (err)
2542                 goto out;
2543         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2544         release_firmware(firmware);
2545 out:
2546         rtnl_lock();
2547         dev_put(dev);
2548         return err;
2549 }
2550
2551 #define MLXSW_SP_I2C_ADDR_LOW 0x50
2552 #define MLXSW_SP_I2C_ADDR_HIGH 0x51
2553 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2554
2555 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2556                                         u16 offset, u16 size, void *data,
2557                                         unsigned int *p_read_size)
2558 {
2559         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2560         char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2561         char mcia_pl[MLXSW_REG_MCIA_LEN];
2562         u16 i2c_addr;
2563         int status;
2564         int err;
2565
2566         size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2567
2568         if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2569             offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2570                 /* Cross pages read, read until offset 256 in low page */
2571                 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2572
2573         i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2574         if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2575                 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2576                 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2577         }
2578
2579         mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2580                             0, 0, offset, size, i2c_addr);
2581
2582         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2583         if (err)
2584                 return err;
2585
2586         status = mlxsw_reg_mcia_status_get(mcia_pl);
2587         if (status)
2588                 return -EIO;
2589
2590         mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2591         memcpy(data, eeprom_tmp, size);
2592         *p_read_size = size;
2593
2594         return 0;
2595 }
2596
2597 enum mlxsw_sp_eeprom_module_info_rev_id {
2598         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC      = 0x00,
2599         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436       = 0x01,
2600         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636       = 0x03,
2601 };
2602
2603 enum mlxsw_sp_eeprom_module_info_id {
2604         MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP              = 0x03,
2605         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP             = 0x0C,
2606         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS        = 0x0D,
2607         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28           = 0x11,
2608 };
2609
2610 enum mlxsw_sp_eeprom_module_info {
2611         MLXSW_SP_EEPROM_MODULE_INFO_ID,
2612         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2613         MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2614 };
2615
2616 static int mlxsw_sp_get_module_info(struct net_device *netdev,
2617                                     struct ethtool_modinfo *modinfo)
2618 {
2619         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2620         u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2621         u8 module_rev_id, module_id;
2622         unsigned int read_size;
2623         int err;
2624
2625         err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2626                                            MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2627                                            module_info, &read_size);
2628         if (err)
2629                 return err;
2630
2631         if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2632                 return -EIO;
2633
2634         module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2635         module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2636
2637         switch (module_id) {
2638         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2639                 modinfo->type       = ETH_MODULE_SFF_8436;
2640                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2641                 break;
2642         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2643         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2644                 if (module_id  == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2645                     module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2646                         modinfo->type       = ETH_MODULE_SFF_8636;
2647                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2648                 } else {
2649                         modinfo->type       = ETH_MODULE_SFF_8436;
2650                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2651                 }
2652                 break;
2653         case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2654                 modinfo->type       = ETH_MODULE_SFF_8472;
2655                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2656                 break;
2657         default:
2658                 return -EINVAL;
2659         }
2660
2661         return 0;
2662 }
2663
2664 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2665                                       struct ethtool_eeprom *ee,
2666                                       u8 *data)
2667 {
2668         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2669         int offset = ee->offset;
2670         unsigned int read_size;
2671         int i = 0;
2672         int err;
2673
2674         if (!ee->len)
2675                 return -EINVAL;
2676
2677         memset(data, 0, ee->len);
2678
2679         while (i < ee->len) {
2680                 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2681                                                    ee->len - i, data + i,
2682                                                    &read_size);
2683                 if (err) {
2684                         netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2685                         return err;
2686                 }
2687
2688                 i += read_size;
2689                 offset += read_size;
2690         }
2691
2692         return 0;
2693 }
2694
2695 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2696         .get_drvinfo            = mlxsw_sp_port_get_drvinfo,
2697         .get_link               = ethtool_op_get_link,
2698         .get_pauseparam         = mlxsw_sp_port_get_pauseparam,
2699         .set_pauseparam         = mlxsw_sp_port_set_pauseparam,
2700         .get_strings            = mlxsw_sp_port_get_strings,
2701         .set_phys_id            = mlxsw_sp_port_set_phys_id,
2702         .get_ethtool_stats      = mlxsw_sp_port_get_stats,
2703         .get_sset_count         = mlxsw_sp_port_get_sset_count,
2704         .get_link_ksettings     = mlxsw_sp_port_get_link_ksettings,
2705         .set_link_ksettings     = mlxsw_sp_port_set_link_ksettings,
2706         .flash_device           = mlxsw_sp_flash_device,
2707         .get_module_info        = mlxsw_sp_get_module_info,
2708         .get_module_eeprom      = mlxsw_sp_get_module_eeprom,
2709 };
2710
2711 static int
2712 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2713 {
2714         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2715         u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2716         char ptys_pl[MLXSW_REG_PTYS_LEN];
2717         u32 eth_proto_admin;
2718
2719         eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2720         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2721                                 eth_proto_admin, mlxsw_sp_port->link.autoneg);
2722         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2723 }
2724
2725 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2726                           enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2727                           bool dwrr, u8 dwrr_weight)
2728 {
2729         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2730         char qeec_pl[MLXSW_REG_QEEC_LEN];
2731
2732         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2733                             next_index);
2734         mlxsw_reg_qeec_de_set(qeec_pl, true);
2735         mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2736         mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2737         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2738 }
2739
2740 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2741                                   enum mlxsw_reg_qeec_hr hr, u8 index,
2742                                   u8 next_index, u32 maxrate)
2743 {
2744         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2745         char qeec_pl[MLXSW_REG_QEEC_LEN];
2746
2747         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2748                             next_index);
2749         mlxsw_reg_qeec_mase_set(qeec_pl, true);
2750         mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2751         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2752 }
2753
2754 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
2755                                     enum mlxsw_reg_qeec_hr hr, u8 index,
2756                                     u8 next_index, u32 minrate)
2757 {
2758         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2759         char qeec_pl[MLXSW_REG_QEEC_LEN];
2760
2761         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2762                             next_index);
2763         mlxsw_reg_qeec_mise_set(qeec_pl, true);
2764         mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
2765
2766         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2767 }
2768
2769 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2770                               u8 switch_prio, u8 tclass)
2771 {
2772         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2773         char qtct_pl[MLXSW_REG_QTCT_LEN];
2774
2775         mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2776                             tclass);
2777         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2778 }
2779
2780 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2781 {
2782         int err, i;
2783
2784         /* Setup the elements hierarcy, so that each TC is linked to
2785          * one subgroup, which are all member in the same group.
2786          */
2787         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2788                                     MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2789                                     0);
2790         if (err)
2791                 return err;
2792         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2793                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2794                                             MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2795                                             0, false, 0);
2796                 if (err)
2797                         return err;
2798         }
2799         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2800                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2801                                             MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2802                                             false, 0);
2803                 if (err)
2804                         return err;
2805
2806                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2807                                             MLXSW_REG_QEEC_HIERARCY_TC,
2808                                             i + 8, i,
2809                                             true, 100);
2810                 if (err)
2811                         return err;
2812         }
2813
2814         /* Make sure the max shaper is disabled in all hierarchies that
2815          * support it.
2816          */
2817         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2818                                             MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2819                                             MLXSW_REG_QEEC_MAS_DIS);
2820         if (err)
2821                 return err;
2822         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2823                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2824                                                     MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2825                                                     i, 0,
2826                                                     MLXSW_REG_QEEC_MAS_DIS);
2827                 if (err)
2828                         return err;
2829         }
2830         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2831                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2832                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2833                                                     i, i,
2834                                                     MLXSW_REG_QEEC_MAS_DIS);
2835                 if (err)
2836                         return err;
2837
2838                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2839                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2840                                                     i + 8, i,
2841                                                     MLXSW_REG_QEEC_MAS_DIS);
2842                 if (err)
2843                         return err;
2844         }
2845
2846         /* Configure the min shaper for multicast TCs. */
2847         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2848                 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
2849                                                MLXSW_REG_QEEC_HIERARCY_TC,
2850                                                i + 8, i,
2851                                                MLXSW_REG_QEEC_MIS_MIN);
2852                 if (err)
2853                         return err;
2854         }
2855
2856         /* Map all priorities to traffic class 0. */
2857         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2858                 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2859                 if (err)
2860                         return err;
2861         }
2862
2863         return 0;
2864 }
2865
2866 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
2867                                         bool enable)
2868 {
2869         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2870         char qtctm_pl[MLXSW_REG_QTCTM_LEN];
2871
2872         mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
2873         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
2874 }
2875
2876 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2877                                 bool split, u8 module, u8 width, u8 lane)
2878 {
2879         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
2880         struct mlxsw_sp_port *mlxsw_sp_port;
2881         struct net_device *dev;
2882         int err;
2883
2884         err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2885         if (err) {
2886                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2887                         local_port);
2888                 return err;
2889         }
2890
2891         dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2892         if (!dev) {
2893                 err = -ENOMEM;
2894                 goto err_alloc_etherdev;
2895         }
2896         SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2897         mlxsw_sp_port = netdev_priv(dev);
2898         mlxsw_sp_port->dev = dev;
2899         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2900         mlxsw_sp_port->local_port = local_port;
2901         mlxsw_sp_port->pvid = 1;
2902         mlxsw_sp_port->split = split;
2903         mlxsw_sp_port->mapping.module = module;
2904         mlxsw_sp_port->mapping.width = width;
2905         mlxsw_sp_port->mapping.lane = lane;
2906         mlxsw_sp_port->link.autoneg = 1;
2907         INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
2908         INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2909
2910         mlxsw_sp_port->pcpu_stats =
2911                 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2912         if (!mlxsw_sp_port->pcpu_stats) {
2913                 err = -ENOMEM;
2914                 goto err_alloc_stats;
2915         }
2916
2917         mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2918                                         GFP_KERNEL);
2919         if (!mlxsw_sp_port->sample) {
2920                 err = -ENOMEM;
2921                 goto err_alloc_sample;
2922         }
2923
2924         INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
2925                           &update_stats_cache);
2926
2927         dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2928         dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2929
2930         err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
2931         if (err) {
2932                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2933                         mlxsw_sp_port->local_port);
2934                 goto err_port_module_map;
2935         }
2936
2937         err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2938         if (err) {
2939                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2940                         mlxsw_sp_port->local_port);
2941                 goto err_port_swid_set;
2942         }
2943
2944         err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2945         if (err) {
2946                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2947                         mlxsw_sp_port->local_port);
2948                 goto err_dev_addr_init;
2949         }
2950
2951         netif_carrier_off(dev);
2952
2953         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2954                          NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2955         dev->hw_features |= NETIF_F_HW_TC;
2956
2957         dev->min_mtu = 0;
2958         dev->max_mtu = ETH_MAX_MTU;
2959
2960         /* Each packet needs to have a Tx header (metadata) on top all other
2961          * headers.
2962          */
2963         dev->needed_headroom = MLXSW_TXHDR_LEN;
2964
2965         err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2966         if (err) {
2967                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2968                         mlxsw_sp_port->local_port);
2969                 goto err_port_system_port_mapping_set;
2970         }
2971
2972         err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2973         if (err) {
2974                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2975                         mlxsw_sp_port->local_port);
2976                 goto err_port_speed_by_width_set;
2977         }
2978
2979         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2980         if (err) {
2981                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2982                         mlxsw_sp_port->local_port);
2983                 goto err_port_mtu_set;
2984         }
2985
2986         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2987         if (err)
2988                 goto err_port_admin_status_set;
2989
2990         err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2991         if (err) {
2992                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2993                         mlxsw_sp_port->local_port);
2994                 goto err_port_buffers_init;
2995         }
2996
2997         err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2998         if (err) {
2999                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3000                         mlxsw_sp_port->local_port);
3001                 goto err_port_ets_init;
3002         }
3003
3004         err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3005         if (err) {
3006                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3007                         mlxsw_sp_port->local_port);
3008                 goto err_port_tc_mc_mode;
3009         }
3010
3011         /* ETS and buffers must be initialized before DCB. */
3012         err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3013         if (err) {
3014                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3015                         mlxsw_sp_port->local_port);
3016                 goto err_port_dcb_init;
3017         }
3018
3019         err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3020         if (err) {
3021                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3022                         mlxsw_sp_port->local_port);
3023                 goto err_port_fids_init;
3024         }
3025
3026         err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3027         if (err) {
3028                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3029                         mlxsw_sp_port->local_port);
3030                 goto err_port_qdiscs_init;
3031         }
3032
3033         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3034         if (IS_ERR(mlxsw_sp_port_vlan)) {
3035                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3036                         mlxsw_sp_port->local_port);
3037                 err = PTR_ERR(mlxsw_sp_port_vlan);
3038                 goto err_port_vlan_get;
3039         }
3040
3041         mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
3042         mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3043         err = register_netdev(dev);
3044         if (err) {
3045                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3046                         mlxsw_sp_port->local_port);
3047                 goto err_register_netdev;
3048         }
3049
3050         mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3051                                 mlxsw_sp_port, dev, module + 1,
3052                                 mlxsw_sp_port->split, lane / width);
3053         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3054         return 0;
3055
3056 err_register_netdev:
3057         mlxsw_sp->ports[local_port] = NULL;
3058         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3059         mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3060 err_port_vlan_get:
3061         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3062 err_port_qdiscs_init:
3063         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3064 err_port_fids_init:
3065         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3066 err_port_dcb_init:
3067         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3068 err_port_tc_mc_mode:
3069 err_port_ets_init:
3070 err_port_buffers_init:
3071 err_port_admin_status_set:
3072 err_port_mtu_set:
3073 err_port_speed_by_width_set:
3074 err_port_system_port_mapping_set:
3075 err_dev_addr_init:
3076         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3077 err_port_swid_set:
3078         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3079 err_port_module_map:
3080         kfree(mlxsw_sp_port->sample);
3081 err_alloc_sample:
3082         free_percpu(mlxsw_sp_port->pcpu_stats);
3083 err_alloc_stats:
3084         free_netdev(dev);
3085 err_alloc_etherdev:
3086         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3087         return err;
3088 }
3089
3090 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3091 {
3092         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3093
3094         cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3095         mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3096         unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3097         mlxsw_sp->ports[local_port] = NULL;
3098         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3099         mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
3100         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3101         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3102         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3103         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3104         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3105         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3106         kfree(mlxsw_sp_port->sample);
3107         free_percpu(mlxsw_sp_port->pcpu_stats);
3108         WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3109         free_netdev(mlxsw_sp_port->dev);
3110         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3111 }
3112
3113 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3114 {
3115         return mlxsw_sp->ports[local_port] != NULL;
3116 }
3117
3118 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3119 {
3120         int i;
3121
3122         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3123                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3124                         mlxsw_sp_port_remove(mlxsw_sp, i);
3125         kfree(mlxsw_sp->port_to_module);
3126         kfree(mlxsw_sp->ports);
3127         mlxsw_sp->ports = NULL;
3128 }
3129
3130 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3131 {
3132         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3133         u8 module, width, lane;
3134         size_t alloc_size;
3135         int i;
3136         int err;
3137
3138         alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3139         mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3140         if (!mlxsw_sp->ports)
3141                 return -ENOMEM;
3142
3143         mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3144                                                  GFP_KERNEL);
3145         if (!mlxsw_sp->port_to_module) {
3146                 err = -ENOMEM;
3147                 goto err_port_to_module_alloc;
3148         }
3149
3150         for (i = 1; i < max_ports; i++) {
3151                 /* Mark as invalid */
3152                 mlxsw_sp->port_to_module[i] = -1;
3153
3154                 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3155                                                     &width, &lane);
3156                 if (err)
3157                         goto err_port_module_info_get;
3158                 if (!width)
3159                         continue;
3160                 mlxsw_sp->port_to_module[i] = module;
3161                 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3162                                            module, width, lane);
3163                 if (err)
3164                         goto err_port_create;
3165         }
3166         return 0;
3167
3168 err_port_create:
3169 err_port_module_info_get:
3170         for (i--; i >= 1; i--)
3171                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3172                         mlxsw_sp_port_remove(mlxsw_sp, i);
3173         kfree(mlxsw_sp->port_to_module);
3174 err_port_to_module_alloc:
3175         kfree(mlxsw_sp->ports);
3176         mlxsw_sp->ports = NULL;
3177         return err;
3178 }
3179
3180 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3181 {
3182         u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3183
3184         return local_port - offset;
3185 }
3186
3187 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3188                                       u8 module, unsigned int count)
3189 {
3190         u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3191         int err, i;
3192
3193         for (i = 0; i < count; i++) {
3194                 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
3195                                            module, width, i * width);
3196                 if (err)
3197                         goto err_port_create;
3198         }
3199
3200         return 0;
3201
3202 err_port_create:
3203         for (i--; i >= 0; i--)
3204                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3205                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3206         return err;
3207 }
3208
3209 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3210                                          u8 base_port, unsigned int count)
3211 {
3212         u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3213         int i;
3214
3215         /* Split by four means we need to re-create two ports, otherwise
3216          * only one.
3217          */
3218         count = count / 2;
3219
3220         for (i = 0; i < count; i++) {
3221                 local_port = base_port + i * 2;
3222                 if (mlxsw_sp->port_to_module[local_port] < 0)
3223                         continue;
3224                 module = mlxsw_sp->port_to_module[local_port];
3225
3226                 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
3227                                      width, 0);
3228         }
3229 }
3230
3231 static struct mlxsw_sp_port *
3232 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3233 {
3234         if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
3235                 return mlxsw_sp->ports[local_port];
3236         return NULL;
3237 }
3238
3239 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3240                                unsigned int count,
3241                                struct netlink_ext_ack *extack)
3242 {
3243         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3244         struct mlxsw_sp_port *mlxsw_sp_port;
3245         u8 module, cur_width, base_port;
3246         int i;
3247         int err;
3248
3249         mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
3250         if (!mlxsw_sp_port) {
3251                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3252                         local_port);
3253                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3254                 return -EINVAL;
3255         }
3256
3257         module = mlxsw_sp_port->mapping.module;
3258         cur_width = mlxsw_sp_port->mapping.width;
3259
3260         if (count != 2 && count != 4) {
3261                 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3262                 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
3263                 return -EINVAL;
3264         }
3265
3266         if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3267                 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3268                 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
3269                 return -EINVAL;
3270         }
3271
3272         /* Make sure we have enough slave (even) ports for the split. */
3273         if (count == 2) {
3274                 base_port = local_port;
3275                 if (mlxsw_sp->ports[base_port + 1]) {
3276                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3277                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3278                         return -EINVAL;
3279                 }
3280         } else {
3281                 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3282                 if (mlxsw_sp->ports[base_port + 1] ||
3283                     mlxsw_sp->ports[base_port + 3]) {
3284                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3285                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3286                         return -EINVAL;
3287                 }
3288         }
3289
3290         for (i = 0; i < count; i++)
3291                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3292                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3293
3294         err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3295         if (err) {
3296                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3297                 goto err_port_split_create;
3298         }
3299
3300         return 0;
3301
3302 err_port_split_create:
3303         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3304         return err;
3305 }
3306
3307 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3308                                  struct netlink_ext_ack *extack)
3309 {
3310         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3311         struct mlxsw_sp_port *mlxsw_sp_port;
3312         u8 cur_width, base_port;
3313         unsigned int count;
3314         int i;
3315
3316         mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
3317         if (!mlxsw_sp_port) {
3318                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3319                         local_port);
3320                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3321                 return -EINVAL;
3322         }
3323
3324         if (!mlxsw_sp_port->split) {
3325                 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3326                 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
3327                 return -EINVAL;
3328         }
3329
3330         cur_width = mlxsw_sp_port->mapping.width;
3331         count = cur_width == 1 ? 4 : 2;
3332
3333         base_port = mlxsw_sp_cluster_base_port_get(local_port);
3334
3335         /* Determine which ports to remove. */
3336         if (count == 2 && local_port >= base_port + 2)
3337                 base_port = base_port + 2;
3338
3339         for (i = 0; i < count; i++)
3340                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3341                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3342
3343         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3344
3345         return 0;
3346 }
3347
3348 static void
3349 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
3350 {
3351         int i;
3352
3353         for (i = 0; i < TC_MAX_QUEUE; i++)
3354                 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
3355 }
3356
3357 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3358                                      char *pude_pl, void *priv)
3359 {
3360         struct mlxsw_sp *mlxsw_sp = priv;
3361         struct mlxsw_sp_port *mlxsw_sp_port;
3362         enum mlxsw_reg_pude_oper_status status;
3363         u8 local_port;
3364
3365         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3366         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3367         if (!mlxsw_sp_port)
3368                 return;
3369
3370         status = mlxsw_reg_pude_oper_status_get(pude_pl);
3371         if (status == MLXSW_PORT_OPER_STATUS_UP) {
3372                 netdev_info(mlxsw_sp_port->dev, "link up\n");
3373                 netif_carrier_on(mlxsw_sp_port->dev);
3374         } else {
3375                 netdev_info(mlxsw_sp_port->dev, "link down\n");
3376                 netif_carrier_off(mlxsw_sp_port->dev);
3377                 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
3378         }
3379 }
3380
3381 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3382                                               u8 local_port, void *priv)
3383 {
3384         struct mlxsw_sp *mlxsw_sp = priv;
3385         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3386         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3387
3388         if (unlikely(!mlxsw_sp_port)) {
3389                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3390                                      local_port);
3391                 return;
3392         }
3393
3394         skb->dev = mlxsw_sp_port->dev;
3395
3396         pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3397         u64_stats_update_begin(&pcpu_stats->syncp);
3398         pcpu_stats->rx_packets++;
3399         pcpu_stats->rx_bytes += skb->len;
3400         u64_stats_update_end(&pcpu_stats->syncp);
3401
3402         skb->protocol = eth_type_trans(skb, skb->dev);
3403         netif_receive_skb(skb);
3404 }
3405
3406 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3407                                            void *priv)
3408 {
3409         skb->offload_fwd_mark = 1;
3410         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3411 }
3412
3413 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3414                                               u8 local_port, void *priv)
3415 {
3416         skb->offload_mr_fwd_mark = 1;
3417         skb->offload_fwd_mark = 1;
3418         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3419 }
3420
3421 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3422                                              void *priv)
3423 {
3424         struct mlxsw_sp *mlxsw_sp = priv;
3425         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3426         struct psample_group *psample_group;
3427         u32 size;
3428
3429         if (unlikely(!mlxsw_sp_port)) {
3430                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3431                                      local_port);
3432                 goto out;
3433         }
3434         if (unlikely(!mlxsw_sp_port->sample)) {
3435                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3436                                      local_port);
3437                 goto out;
3438         }
3439
3440         size = mlxsw_sp_port->sample->truncate ?
3441                   mlxsw_sp_port->sample->trunc_size : skb->len;
3442
3443         rcu_read_lock();
3444         psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3445         if (!psample_group)
3446                 goto out_unlock;
3447         psample_sample_packet(psample_group, skb, size,
3448                               mlxsw_sp_port->dev->ifindex, 0,
3449                               mlxsw_sp_port->sample->rate);
3450 out_unlock:
3451         rcu_read_unlock();
3452 out:
3453         consume_skb(skb);
3454 }
3455
3456 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
3457         MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3458                   _is_ctrl, SP_##_trap_group, DISCARD)
3459
3460 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)     \
3461         MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,    \
3462                 _is_ctrl, SP_##_trap_group, DISCARD)
3463
3464 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
3465         MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3466                 _is_ctrl, SP_##_trap_group, DISCARD)
3467
3468 #define MLXSW_SP_EVENTL(_func, _trap_id)                \
3469         MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
3470
3471 static const struct mlxsw_listener mlxsw_sp_listener[] = {
3472         /* Events */
3473         MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
3474         /* L2 traps */
3475         MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3476         MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3477         MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3478         MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3479         MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3480         MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3481         MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3482         MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3483         MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3484         MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3485         MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
3486         MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
3487         MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3488                           false),
3489         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3490                              false),
3491         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3492                              false),
3493         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3494                              false),
3495         /* L3 traps */
3496         MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3497         MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3498         MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3499         MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3500         MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3501                           false),
3502         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3503         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3504         MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3505         MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3506                           false),
3507         MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3508         MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3509         MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
3510         MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3511         MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3512         MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3513         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3514                           false),
3515         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3516                           false),
3517         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3518                           false),
3519         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3520                           false),
3521         MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3522         MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3523                           false),
3524         MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3525         MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
3526         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
3527         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
3528         MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3529         MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3530         MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3531         /* PKT Sample trap */
3532         MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3533                   false, SP_IP2ME, DISCARD),
3534         /* ACL trap */
3535         MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
3536         /* Multicast Router Traps */
3537         MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3538         MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
3539         MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3540         MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
3541         MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
3542 };
3543
3544 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3545 {
3546         char qpcr_pl[MLXSW_REG_QPCR_LEN];
3547         enum mlxsw_reg_qpcr_ir_units ir_units;
3548         int max_cpu_policers;
3549         bool is_bytes;
3550         u8 burst_size;
3551         u32 rate;
3552         int i, err;
3553
3554         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3555                 return -EIO;
3556
3557         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3558
3559         ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3560         for (i = 0; i < max_cpu_policers; i++) {
3561                 is_bytes = false;
3562                 switch (i) {
3563                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3564                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3565                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3566                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3567                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3568                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3569                         rate = 128;
3570                         burst_size = 7;
3571                         break;
3572                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3573                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3574                         rate = 16 * 1024;
3575                         burst_size = 10;
3576                         break;
3577                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3578                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3579                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3580                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3581                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3582                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3583                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3584                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3585                         rate = 1024;
3586                         burst_size = 7;
3587                         break;
3588                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3589                         rate = 4 * 1024;
3590                         burst_size = 4;
3591                         break;
3592                 default:
3593                         continue;
3594                 }
3595
3596                 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3597                                     burst_size);
3598                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3599                 if (err)
3600                         return err;
3601         }
3602
3603         return 0;
3604 }
3605
3606 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
3607 {
3608         char htgt_pl[MLXSW_REG_HTGT_LEN];
3609         enum mlxsw_reg_htgt_trap_group i;
3610         int max_cpu_policers;
3611         int max_trap_groups;
3612         u8 priority, tc;
3613         u16 policer_id;
3614         int err;
3615
3616         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3617                 return -EIO;
3618
3619         max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
3620         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3621
3622         for (i = 0; i < max_trap_groups; i++) {
3623                 policer_id = i;
3624                 switch (i) {
3625                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3626                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3627                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3628                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3629                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3630                         priority = 5;
3631                         tc = 5;
3632                         break;
3633                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3634                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3635                         priority = 4;
3636                         tc = 4;
3637                         break;
3638                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3639                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3640                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3641                         priority = 3;
3642                         tc = 3;
3643                         break;
3644                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3645                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3646                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3647                         priority = 2;
3648                         tc = 2;
3649                         break;
3650                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3651                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3652                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3653                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3654                         priority = 1;
3655                         tc = 1;
3656                         break;
3657                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
3658                         priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3659                         tc = MLXSW_REG_HTGT_DEFAULT_TC;
3660                         policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
3661                         break;
3662                 default:
3663                         continue;
3664                 }
3665
3666                 if (max_cpu_policers <= policer_id &&
3667                     policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3668                         return -EIO;
3669
3670                 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
3671                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3672                 if (err)
3673                         return err;
3674         }
3675
3676         return 0;
3677 }
3678
3679 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3680 {
3681         int i;
3682         int err;
3683
3684         err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3685         if (err)
3686                 return err;
3687
3688         err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
3689         if (err)
3690                 return err;
3691
3692         for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3693                 err = mlxsw_core_trap_register(mlxsw_sp->core,
3694                                                &mlxsw_sp_listener[i],
3695                                                mlxsw_sp);
3696                 if (err)
3697                         goto err_listener_register;
3698
3699         }
3700         return 0;
3701
3702 err_listener_register:
3703         for (i--; i >= 0; i--) {
3704                 mlxsw_core_trap_unregister(mlxsw_sp->core,
3705                                            &mlxsw_sp_listener[i],
3706                                            mlxsw_sp);
3707         }
3708         return err;
3709 }
3710
3711 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3712 {
3713         int i;
3714
3715         for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3716                 mlxsw_core_trap_unregister(mlxsw_sp->core,
3717                                            &mlxsw_sp_listener[i],
3718                                            mlxsw_sp);
3719         }
3720 }
3721
3722 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3723 {
3724         char slcr_pl[MLXSW_REG_SLCR_LEN];
3725         int err;
3726
3727         mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3728                                      MLXSW_REG_SLCR_LAG_HASH_DMAC |
3729                                      MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3730                                      MLXSW_REG_SLCR_LAG_HASH_VLANID |
3731                                      MLXSW_REG_SLCR_LAG_HASH_SIP |
3732                                      MLXSW_REG_SLCR_LAG_HASH_DIP |
3733                                      MLXSW_REG_SLCR_LAG_HASH_SPORT |
3734                                      MLXSW_REG_SLCR_LAG_HASH_DPORT |
3735                                      MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
3736         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3737         if (err)
3738                 return err;
3739
3740         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3741             !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3742                 return -EIO;
3743
3744         mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3745                                  sizeof(struct mlxsw_sp_upper),
3746                                  GFP_KERNEL);
3747         if (!mlxsw_sp->lags)
3748                 return -ENOMEM;
3749
3750         return 0;
3751 }
3752
3753 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3754 {
3755         kfree(mlxsw_sp->lags);
3756 }
3757
3758 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3759 {
3760         char htgt_pl[MLXSW_REG_HTGT_LEN];
3761
3762         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3763                             MLXSW_REG_HTGT_INVALID_POLICER,
3764                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3765                             MLXSW_REG_HTGT_DEFAULT_TC);
3766         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3767 }
3768
3769 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3770                                     unsigned long event, void *ptr);
3771
3772 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3773                          const struct mlxsw_bus_info *mlxsw_bus_info)
3774 {
3775         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3776         int err;
3777
3778         mlxsw_sp->core = mlxsw_core;
3779         mlxsw_sp->bus_info = mlxsw_bus_info;
3780
3781         err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3782         if (err)
3783                 return err;
3784
3785         err = mlxsw_sp_base_mac_get(mlxsw_sp);
3786         if (err) {
3787                 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3788                 return err;
3789         }
3790
3791         err = mlxsw_sp_kvdl_init(mlxsw_sp);
3792         if (err) {
3793                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3794                 return err;
3795         }
3796
3797         err = mlxsw_sp_fids_init(mlxsw_sp);
3798         if (err) {
3799                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3800                 goto err_fids_init;
3801         }
3802
3803         err = mlxsw_sp_traps_init(mlxsw_sp);
3804         if (err) {
3805                 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3806                 goto err_traps_init;
3807         }
3808
3809         err = mlxsw_sp_buffers_init(mlxsw_sp);
3810         if (err) {
3811                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3812                 goto err_buffers_init;
3813         }
3814
3815         err = mlxsw_sp_lag_init(mlxsw_sp);
3816         if (err) {
3817                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3818                 goto err_lag_init;
3819         }
3820
3821         /* Initialize SPAN before router and switchdev, so that those components
3822          * can call mlxsw_sp_span_respin().
3823          */
3824         err = mlxsw_sp_span_init(mlxsw_sp);
3825         if (err) {
3826                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3827                 goto err_span_init;
3828         }
3829
3830         err = mlxsw_sp_switchdev_init(mlxsw_sp);
3831         if (err) {
3832                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3833                 goto err_switchdev_init;
3834         }
3835
3836         err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3837         if (err) {
3838                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3839                 goto err_counter_pool_init;
3840         }
3841
3842         err = mlxsw_sp_afa_init(mlxsw_sp);
3843         if (err) {
3844                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3845                 goto err_afa_init;
3846         }
3847
3848         err = mlxsw_sp_router_init(mlxsw_sp);
3849         if (err) {
3850                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3851                 goto err_router_init;
3852         }
3853
3854         /* Initialize netdevice notifier after router and SPAN is initialized,
3855          * so that the event handler can use router structures and call SPAN
3856          * respin.
3857          */
3858         mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3859         err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3860         if (err) {
3861                 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3862                 goto err_netdev_notifier;
3863         }
3864
3865         err = mlxsw_sp_acl_init(mlxsw_sp);
3866         if (err) {
3867                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3868                 goto err_acl_init;
3869         }
3870
3871         err = mlxsw_sp_dpipe_init(mlxsw_sp);
3872         if (err) {
3873                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3874                 goto err_dpipe_init;
3875         }
3876
3877         err = mlxsw_sp_ports_create(mlxsw_sp);
3878         if (err) {
3879                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3880                 goto err_ports_create;
3881         }
3882
3883         return 0;
3884
3885 err_ports_create:
3886         mlxsw_sp_dpipe_fini(mlxsw_sp);
3887 err_dpipe_init:
3888         mlxsw_sp_acl_fini(mlxsw_sp);
3889 err_acl_init:
3890         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3891 err_netdev_notifier:
3892         mlxsw_sp_router_fini(mlxsw_sp);
3893 err_router_init:
3894         mlxsw_sp_afa_fini(mlxsw_sp);
3895 err_afa_init:
3896         mlxsw_sp_counter_pool_fini(mlxsw_sp);
3897 err_counter_pool_init:
3898         mlxsw_sp_switchdev_fini(mlxsw_sp);
3899 err_switchdev_init:
3900         mlxsw_sp_span_fini(mlxsw_sp);
3901 err_span_init:
3902         mlxsw_sp_lag_fini(mlxsw_sp);
3903 err_lag_init:
3904         mlxsw_sp_buffers_fini(mlxsw_sp);
3905 err_buffers_init:
3906         mlxsw_sp_traps_fini(mlxsw_sp);
3907 err_traps_init:
3908         mlxsw_sp_fids_fini(mlxsw_sp);
3909 err_fids_init:
3910         mlxsw_sp_kvdl_fini(mlxsw_sp);
3911         return err;
3912 }
3913
3914 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3915                           const struct mlxsw_bus_info *mlxsw_bus_info)
3916 {
3917         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3918
3919         mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3920         mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
3921         mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3922         mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3923         mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3924         mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3925         mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3926
3927         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3928 }
3929
3930 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3931                           const struct mlxsw_bus_info *mlxsw_bus_info)
3932 {
3933         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3934
3935         mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3936         mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3937         mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3938         mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3939         mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3940
3941         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3942 }
3943
3944 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3945 {
3946         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3947
3948         mlxsw_sp_ports_remove(mlxsw_sp);
3949         mlxsw_sp_dpipe_fini(mlxsw_sp);
3950         mlxsw_sp_acl_fini(mlxsw_sp);
3951         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3952         mlxsw_sp_router_fini(mlxsw_sp);
3953         mlxsw_sp_afa_fini(mlxsw_sp);
3954         mlxsw_sp_counter_pool_fini(mlxsw_sp);
3955         mlxsw_sp_switchdev_fini(mlxsw_sp);
3956         mlxsw_sp_span_fini(mlxsw_sp);
3957         mlxsw_sp_lag_fini(mlxsw_sp);
3958         mlxsw_sp_buffers_fini(mlxsw_sp);
3959         mlxsw_sp_traps_fini(mlxsw_sp);
3960         mlxsw_sp_fids_fini(mlxsw_sp);
3961         mlxsw_sp_kvdl_fini(mlxsw_sp);
3962 }
3963
3964 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3965         .used_max_mid                   = 1,
3966         .max_mid                        = MLXSW_SP_MID_MAX,
3967         .used_flood_tables              = 1,
3968         .used_flood_mode                = 1,
3969         .flood_mode                     = 3,
3970         .max_fid_offset_flood_tables    = 3,
3971         .fid_offset_flood_table_size    = VLAN_N_VID - 1,
3972         .max_fid_flood_tables           = 3,
3973         .fid_flood_table_size           = MLXSW_SP_FID_8021D_MAX,
3974         .used_max_ib_mc                 = 1,
3975         .max_ib_mc                      = 0,
3976         .used_max_pkey                  = 1,
3977         .max_pkey                       = 0,
3978         .used_kvd_sizes                 = 1,
3979         .kvd_hash_single_parts          = 59,
3980         .kvd_hash_double_parts          = 41,
3981         .kvd_linear_size                = MLXSW_SP_KVD_LINEAR_SIZE,
3982         .swid_config                    = {
3983                 {
3984                         .used_type      = 1,
3985                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
3986                 }
3987         },
3988 };
3989
3990 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3991         .used_max_mid                   = 1,
3992         .max_mid                        = MLXSW_SP_MID_MAX,
3993         .used_flood_tables              = 1,
3994         .used_flood_mode                = 1,
3995         .flood_mode                     = 3,
3996         .max_fid_offset_flood_tables    = 3,
3997         .fid_offset_flood_table_size    = VLAN_N_VID - 1,
3998         .max_fid_flood_tables           = 3,
3999         .fid_flood_table_size           = MLXSW_SP_FID_8021D_MAX,
4000         .used_max_ib_mc                 = 1,
4001         .max_ib_mc                      = 0,
4002         .used_max_pkey                  = 1,
4003         .max_pkey                       = 0,
4004         .swid_config                    = {
4005                 {
4006                         .used_type      = 1,
4007                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
4008                 }
4009         },
4010 };
4011
4012 static void
4013 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
4014                                       struct devlink_resource_size_params *kvd_size_params,
4015                                       struct devlink_resource_size_params *linear_size_params,
4016                                       struct devlink_resource_size_params *hash_double_size_params,
4017                                       struct devlink_resource_size_params *hash_single_size_params)
4018 {
4019         u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4020                                                  KVD_SINGLE_MIN_SIZE);
4021         u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4022                                                  KVD_DOUBLE_MIN_SIZE);
4023         u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4024         u32 linear_size_min = 0;
4025
4026         devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
4027                                           MLXSW_SP_KVD_GRANULARITY,
4028                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4029         devlink_resource_size_params_init(linear_size_params, linear_size_min,
4030                                           kvd_size - single_size_min -
4031                                           double_size_min,
4032                                           MLXSW_SP_KVD_GRANULARITY,
4033                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4034         devlink_resource_size_params_init(hash_double_size_params,
4035                                           double_size_min,
4036                                           kvd_size - single_size_min -
4037                                           linear_size_min,
4038                                           MLXSW_SP_KVD_GRANULARITY,
4039                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4040         devlink_resource_size_params_init(hash_single_size_params,
4041                                           single_size_min,
4042                                           kvd_size - double_size_min -
4043                                           linear_size_min,
4044                                           MLXSW_SP_KVD_GRANULARITY,
4045                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4046 }
4047
4048 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
4049 {
4050         struct devlink *devlink = priv_to_devlink(mlxsw_core);
4051         struct devlink_resource_size_params hash_single_size_params;
4052         struct devlink_resource_size_params hash_double_size_params;
4053         struct devlink_resource_size_params linear_size_params;
4054         struct devlink_resource_size_params kvd_size_params;
4055         u32 kvd_size, single_size, double_size, linear_size;
4056         const struct mlxsw_config_profile *profile;
4057         int err;
4058
4059         profile = &mlxsw_sp1_config_profile;
4060         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4061                 return -EIO;
4062
4063         mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
4064                                               &linear_size_params,
4065                                               &hash_double_size_params,
4066                                               &hash_single_size_params);
4067
4068         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4069         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4070                                         kvd_size, MLXSW_SP_RESOURCE_KVD,
4071                                         DEVLINK_RESOURCE_ID_PARENT_TOP,
4072                                         &kvd_size_params);
4073         if (err)
4074                 return err;
4075
4076         linear_size = profile->kvd_linear_size;
4077         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4078                                         linear_size,
4079                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
4080                                         MLXSW_SP_RESOURCE_KVD,
4081                                         &linear_size_params);
4082         if (err)
4083                 return err;
4084
4085         err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
4086         if  (err)
4087                 return err;
4088
4089         double_size = kvd_size - linear_size;
4090         double_size *= profile->kvd_hash_double_parts;
4091         double_size /= profile->kvd_hash_double_parts +
4092                        profile->kvd_hash_single_parts;
4093         double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
4094         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4095                                         double_size,
4096                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4097                                         MLXSW_SP_RESOURCE_KVD,
4098                                         &hash_double_size_params);
4099         if (err)
4100                 return err;
4101
4102         single_size = kvd_size - double_size - linear_size;
4103         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4104                                         single_size,
4105                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4106                                         MLXSW_SP_RESOURCE_KVD,
4107                                         &hash_single_size_params);
4108         if (err)
4109                 return err;
4110
4111         return 0;
4112 }
4113
4114 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
4115 {
4116         return mlxsw_sp1_resources_kvd_register(mlxsw_core);
4117 }
4118
4119 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
4120 {
4121         return 0;
4122 }
4123
4124 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4125                                   const struct mlxsw_config_profile *profile,
4126                                   u64 *p_single_size, u64 *p_double_size,
4127                                   u64 *p_linear_size)
4128 {
4129         struct devlink *devlink = priv_to_devlink(mlxsw_core);
4130         u32 double_size;
4131         int err;
4132
4133         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4134             !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
4135                 return -EIO;
4136
4137         /* The hash part is what left of the kvd without the
4138          * linear part. It is split to the single size and
4139          * double size by the parts ratio from the profile.
4140          * Both sizes must be a multiplications of the
4141          * granularity from the profile. In case the user
4142          * provided the sizes they are obtained via devlink.
4143          */
4144         err = devlink_resource_size_get(devlink,
4145                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
4146                                         p_linear_size);
4147         if (err)
4148                 *p_linear_size = profile->kvd_linear_size;
4149
4150         err = devlink_resource_size_get(devlink,
4151                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4152                                         p_double_size);
4153         if (err) {
4154                 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4155                               *p_linear_size;
4156                 double_size *= profile->kvd_hash_double_parts;
4157                 double_size /= profile->kvd_hash_double_parts +
4158                                profile->kvd_hash_single_parts;
4159                 *p_double_size = rounddown(double_size,
4160                                            MLXSW_SP_KVD_GRANULARITY);
4161         }
4162
4163         err = devlink_resource_size_get(devlink,
4164                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4165                                         p_single_size);
4166         if (err)
4167                 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4168                                  *p_double_size - *p_linear_size;
4169
4170         /* Check results are legal. */
4171         if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4172             *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4173             MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4174                 return -EIO;
4175
4176         return 0;
4177 }
4178
4179 static struct mlxsw_driver mlxsw_sp1_driver = {
4180         .kind                           = mlxsw_sp1_driver_name,
4181         .priv_size                      = sizeof(struct mlxsw_sp),
4182         .init                           = mlxsw_sp1_init,
4183         .fini                           = mlxsw_sp_fini,
4184         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
4185         .port_split                     = mlxsw_sp_port_split,
4186         .port_unsplit                   = mlxsw_sp_port_unsplit,
4187         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
4188         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
4189         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
4190         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
4191         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
4192         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
4193         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
4194         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
4195         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
4196         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
4197         .txhdr_construct                = mlxsw_sp_txhdr_construct,
4198         .resources_register             = mlxsw_sp1_resources_register,
4199         .kvd_sizes_get                  = mlxsw_sp_kvd_sizes_get,
4200         .txhdr_len                      = MLXSW_TXHDR_LEN,
4201         .profile                        = &mlxsw_sp1_config_profile,
4202         .res_query_enabled              = true,
4203 };
4204
4205 static struct mlxsw_driver mlxsw_sp2_driver = {
4206         .kind                           = mlxsw_sp2_driver_name,
4207         .priv_size                      = sizeof(struct mlxsw_sp),
4208         .init                           = mlxsw_sp2_init,
4209         .fini                           = mlxsw_sp_fini,
4210         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
4211         .port_split                     = mlxsw_sp_port_split,
4212         .port_unsplit                   = mlxsw_sp_port_unsplit,
4213         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
4214         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
4215         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
4216         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
4217         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
4218         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
4219         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
4220         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
4221         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
4222         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
4223         .txhdr_construct                = mlxsw_sp_txhdr_construct,
4224         .resources_register             = mlxsw_sp2_resources_register,
4225         .txhdr_len                      = MLXSW_TXHDR_LEN,
4226         .profile                        = &mlxsw_sp2_config_profile,
4227         .res_query_enabled              = true,
4228 };
4229
4230 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4231 {
4232         return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4233 }
4234
4235 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
4236 {
4237         struct mlxsw_sp_port **p_mlxsw_sp_port = data;
4238         int ret = 0;
4239
4240         if (mlxsw_sp_port_dev_check(lower_dev)) {
4241                 *p_mlxsw_sp_port = netdev_priv(lower_dev);
4242                 ret = 1;
4243         }
4244
4245         return ret;
4246 }
4247
4248 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4249 {
4250         struct mlxsw_sp_port *mlxsw_sp_port;
4251
4252         if (mlxsw_sp_port_dev_check(dev))
4253                 return netdev_priv(dev);
4254
4255         mlxsw_sp_port = NULL;
4256         netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
4257
4258         return mlxsw_sp_port;
4259 }
4260
4261 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4262 {
4263         struct mlxsw_sp_port *mlxsw_sp_port;
4264
4265         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4266         return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4267 }
4268
4269 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4270 {
4271         struct mlxsw_sp_port *mlxsw_sp_port;
4272
4273         if (mlxsw_sp_port_dev_check(dev))
4274                 return netdev_priv(dev);
4275
4276         mlxsw_sp_port = NULL;
4277         netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4278                                       &mlxsw_sp_port);
4279
4280         return mlxsw_sp_port;
4281 }
4282
4283 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4284 {
4285         struct mlxsw_sp_port *mlxsw_sp_port;
4286
4287         rcu_read_lock();
4288         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4289         if (mlxsw_sp_port)
4290                 dev_hold(mlxsw_sp_port->dev);
4291         rcu_read_unlock();
4292         return mlxsw_sp_port;
4293 }
4294
4295 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4296 {
4297         dev_put(mlxsw_sp_port->dev);
4298 }
4299
4300 static void
4301 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
4302                                  struct net_device *lag_dev)
4303 {
4304         struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
4305         struct net_device *upper_dev;
4306         struct list_head *iter;
4307
4308         if (netif_is_bridge_port(lag_dev))
4309                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
4310
4311         netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4312                 if (!netif_is_bridge_port(upper_dev))
4313                         continue;
4314                 br_dev = netdev_master_upper_dev_get(upper_dev);
4315                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
4316         }
4317 }
4318
4319 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4320 {
4321         char sldr_pl[MLXSW_REG_SLDR_LEN];
4322
4323         mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4324         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4325 }
4326
4327 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4328 {
4329         char sldr_pl[MLXSW_REG_SLDR_LEN];
4330
4331         mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4332         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4333 }
4334
4335 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4336                                      u16 lag_id, u8 port_index)
4337 {
4338         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4339         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4340
4341         mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4342                                       lag_id, port_index);
4343         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4344 }
4345
4346 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4347                                         u16 lag_id)
4348 {
4349         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4350         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4351
4352         mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4353                                          lag_id);
4354         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4355 }
4356
4357 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4358                                         u16 lag_id)
4359 {
4360         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4361         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4362
4363         mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4364                                         lag_id);
4365         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4366 }
4367
4368 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4369                                          u16 lag_id)
4370 {
4371         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4372         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4373
4374         mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4375                                          lag_id);
4376         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4377 }
4378
4379 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4380                                   struct net_device *lag_dev,
4381                                   u16 *p_lag_id)
4382 {
4383         struct mlxsw_sp_upper *lag;
4384         int free_lag_id = -1;
4385         u64 max_lag;
4386         int i;
4387
4388         max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4389         for (i = 0; i < max_lag; i++) {
4390                 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4391                 if (lag->ref_count) {
4392                         if (lag->dev == lag_dev) {
4393                                 *p_lag_id = i;
4394                                 return 0;
4395                         }
4396                 } else if (free_lag_id < 0) {
4397                         free_lag_id = i;
4398                 }
4399         }
4400         if (free_lag_id < 0)
4401                 return -EBUSY;
4402         *p_lag_id = free_lag_id;
4403         return 0;
4404 }
4405
4406 static bool
4407 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4408                           struct net_device *lag_dev,
4409                           struct netdev_lag_upper_info *lag_upper_info,
4410                           struct netlink_ext_ack *extack)
4411 {
4412         u16 lag_id;
4413
4414         if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4415                 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
4416                 return false;
4417         }
4418         if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4419                 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4420                 return false;
4421         }
4422         return true;
4423 }
4424
4425 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4426                                        u16 lag_id, u8 *p_port_index)
4427 {
4428         u64 max_lag_members;
4429         int i;
4430
4431         max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4432                                              MAX_LAG_MEMBERS);
4433         for (i = 0; i < max_lag_members; i++) {
4434                 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4435                         *p_port_index = i;
4436                         return 0;
4437                 }
4438         }
4439         return -EBUSY;
4440 }
4441
4442 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4443                                   struct net_device *lag_dev)
4444 {
4445         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4446         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
4447         struct mlxsw_sp_upper *lag;
4448         u16 lag_id;
4449         u8 port_index;
4450         int err;
4451
4452         err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4453         if (err)
4454                 return err;
4455         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4456         if (!lag->ref_count) {
4457                 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4458                 if (err)
4459                         return err;
4460                 lag->dev = lag_dev;
4461         }
4462
4463         err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4464         if (err)
4465                 return err;
4466         err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4467         if (err)
4468                 goto err_col_port_add;
4469
4470         mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4471                                    mlxsw_sp_port->local_port);
4472         mlxsw_sp_port->lag_id = lag_id;
4473         mlxsw_sp_port->lagged = 1;
4474         lag->ref_count++;
4475
4476         /* Port is no longer usable as a router interface */
4477         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4478         if (mlxsw_sp_port_vlan->fid)
4479                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
4480
4481         return 0;
4482
4483 err_col_port_add:
4484         if (!lag->ref_count)
4485                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4486         return err;
4487 }
4488
4489 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4490                                     struct net_device *lag_dev)
4491 {
4492         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4493         u16 lag_id = mlxsw_sp_port->lag_id;
4494         struct mlxsw_sp_upper *lag;
4495
4496         if (!mlxsw_sp_port->lagged)
4497                 return;
4498         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4499         WARN_ON(lag->ref_count == 0);
4500
4501         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4502
4503         /* Any VLANs configured on the port are no longer valid */
4504         mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4505         /* Make the LAG and its directly linked uppers leave bridges they
4506          * are memeber in
4507          */
4508         mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
4509
4510         if (lag->ref_count == 1)
4511                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4512
4513         mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4514                                      mlxsw_sp_port->local_port);
4515         mlxsw_sp_port->lagged = 0;
4516         lag->ref_count--;
4517
4518         mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4519         /* Make sure untagged frames are allowed to ingress */
4520         mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4521 }
4522
4523 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4524                                       u16 lag_id)
4525 {
4526         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4527         char sldr_pl[MLXSW_REG_SLDR_LEN];
4528
4529         mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4530                                          mlxsw_sp_port->local_port);
4531         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4532 }
4533
4534 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4535                                          u16 lag_id)
4536 {
4537         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4538         char sldr_pl[MLXSW_REG_SLDR_LEN];
4539
4540         mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4541                                             mlxsw_sp_port->local_port);
4542         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4543 }
4544
4545 static int
4546 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
4547 {
4548         int err;
4549
4550         err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
4551                                            mlxsw_sp_port->lag_id);
4552         if (err)
4553                 return err;
4554
4555         err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4556         if (err)
4557                 goto err_dist_port_add;
4558
4559         return 0;
4560
4561 err_dist_port_add:
4562         mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4563         return err;
4564 }
4565
4566 static int
4567 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
4568 {
4569         int err;
4570
4571         err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4572                                             mlxsw_sp_port->lag_id);
4573         if (err)
4574                 return err;
4575
4576         err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
4577                                             mlxsw_sp_port->lag_id);
4578         if (err)
4579                 goto err_col_port_disable;
4580
4581         return 0;
4582
4583 err_col_port_disable:
4584         mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4585         return err;
4586 }
4587
4588 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4589                                      struct netdev_lag_lower_state_info *info)
4590 {
4591         if (info->tx_enabled)
4592                 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
4593         else
4594                 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4595 }
4596
4597 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4598                                  bool enable)
4599 {
4600         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4601         enum mlxsw_reg_spms_state spms_state;
4602         char *spms_pl;
4603         u16 vid;
4604         int err;
4605
4606         spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4607                               MLXSW_REG_SPMS_STATE_DISCARDING;
4608
4609         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4610         if (!spms_pl)
4611                 return -ENOMEM;
4612         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4613
4614         for (vid = 0; vid < VLAN_N_VID; vid++)
4615                 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4616
4617         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4618         kfree(spms_pl);
4619         return err;
4620 }
4621
4622 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4623 {
4624         u16 vid = 1;
4625         int err;
4626
4627         err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4628         if (err)
4629                 return err;
4630         err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4631         if (err)
4632                 goto err_port_stp_set;
4633         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4634                                      true, false);
4635         if (err)
4636                 goto err_port_vlan_set;
4637
4638         for (; vid <= VLAN_N_VID - 1; vid++) {
4639                 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4640                                                      vid, false);
4641                 if (err)
4642                         goto err_vid_learning_set;
4643         }
4644
4645         return 0;
4646
4647 err_vid_learning_set:
4648         for (vid--; vid >= 1; vid--)
4649                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4650 err_port_vlan_set:
4651         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4652 err_port_stp_set:
4653         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4654         return err;
4655 }
4656
4657 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4658 {
4659         u16 vid;
4660
4661         for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4662                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4663                                                vid, true);
4664
4665         mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4666                                false, false);
4667         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4668         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4669 }
4670
4671 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4672                                                struct net_device *dev,
4673                                                unsigned long event, void *ptr)
4674 {
4675         struct netdev_notifier_changeupper_info *info;
4676         struct mlxsw_sp_port *mlxsw_sp_port;
4677         struct netlink_ext_ack *extack;
4678         struct net_device *upper_dev;
4679         struct mlxsw_sp *mlxsw_sp;
4680         int err = 0;
4681
4682         mlxsw_sp_port = netdev_priv(dev);
4683         mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4684         info = ptr;
4685         extack = netdev_notifier_info_to_extack(&info->info);
4686
4687         switch (event) {
4688         case NETDEV_PRECHANGEUPPER:
4689                 upper_dev = info->upper_dev;
4690                 if (!is_vlan_dev(upper_dev) &&
4691                     !netif_is_lag_master(upper_dev) &&
4692                     !netif_is_bridge_master(upper_dev) &&
4693                     !netif_is_ovs_master(upper_dev) &&
4694                     !netif_is_macvlan(upper_dev)) {
4695                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4696                         return -EINVAL;
4697                 }
4698                 if (!info->linking)
4699                         break;
4700                 if (netdev_has_any_upper_dev(upper_dev) &&
4701                     (!netif_is_bridge_master(upper_dev) ||
4702                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4703                                                           upper_dev))) {
4704                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4705                         return -EINVAL;
4706                 }
4707                 if (netif_is_lag_master(upper_dev) &&
4708                     !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4709                                                info->upper_info, extack))
4710                         return -EINVAL;
4711                 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4712                         NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4713                         return -EINVAL;
4714                 }
4715                 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4716                     !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4717                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4718                         return -EINVAL;
4719                 }
4720                 if (netif_is_macvlan(upper_dev) &&
4721                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
4722                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4723                         return -EOPNOTSUPP;
4724                 }
4725                 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4726                         NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4727                         return -EINVAL;
4728                 }
4729                 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4730                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4731                         return -EINVAL;
4732                 }
4733                 if (is_vlan_dev(upper_dev) &&
4734                     vlan_dev_vlan_id(upper_dev) == 1) {
4735                         NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4736                         return -EINVAL;
4737                 }
4738                 break;
4739         case NETDEV_CHANGEUPPER:
4740                 upper_dev = info->upper_dev;
4741                 if (netif_is_bridge_master(upper_dev)) {
4742                         if (info->linking)
4743                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4744                                                                 lower_dev,
4745                                                                 upper_dev,
4746                                                                 extack);
4747                         else
4748                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4749                                                            lower_dev,
4750                                                            upper_dev);
4751                 } else if (netif_is_lag_master(upper_dev)) {
4752                         if (info->linking) {
4753                                 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4754                                                              upper_dev);
4755                         } else {
4756                                 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4757                                 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4758                                                         upper_dev);
4759                         }
4760                 } else if (netif_is_ovs_master(upper_dev)) {
4761                         if (info->linking)
4762                                 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4763                         else
4764                                 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4765                 } else if (netif_is_macvlan(upper_dev)) {
4766                         if (!info->linking)
4767                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4768                 } else if (is_vlan_dev(upper_dev)) {
4769                         struct net_device *br_dev;
4770
4771                         if (!netif_is_bridge_port(upper_dev))
4772                                 break;
4773                         if (info->linking)
4774                                 break;
4775                         br_dev = netdev_master_upper_dev_get(upper_dev);
4776                         mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
4777                                                    br_dev);
4778                 }
4779                 break;
4780         }
4781
4782         return err;
4783 }
4784
4785 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4786                                                unsigned long event, void *ptr)
4787 {
4788         struct netdev_notifier_changelowerstate_info *info;
4789         struct mlxsw_sp_port *mlxsw_sp_port;
4790         int err;
4791
4792         mlxsw_sp_port = netdev_priv(dev);
4793         info = ptr;
4794
4795         switch (event) {
4796         case NETDEV_CHANGELOWERSTATE:
4797                 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4798                         err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4799                                                         info->lower_state_info);
4800                         if (err)
4801                                 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4802                 }
4803                 break;
4804         }
4805
4806         return 0;
4807 }
4808
4809 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4810                                          struct net_device *port_dev,
4811                                          unsigned long event, void *ptr)
4812 {
4813         switch (event) {
4814         case NETDEV_PRECHANGEUPPER:
4815         case NETDEV_CHANGEUPPER:
4816                 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4817                                                            event, ptr);
4818         case NETDEV_CHANGELOWERSTATE:
4819                 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4820                                                            ptr);
4821         }
4822
4823         return 0;
4824 }
4825
4826 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4827                                         unsigned long event, void *ptr)
4828 {
4829         struct net_device *dev;
4830         struct list_head *iter;
4831         int ret;
4832
4833         netdev_for_each_lower_dev(lag_dev, dev, iter) {
4834                 if (mlxsw_sp_port_dev_check(dev)) {
4835                         ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4836                                                             ptr);
4837                         if (ret)
4838                                 return ret;
4839                 }
4840         }
4841
4842         return 0;
4843 }
4844
4845 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4846                                               struct net_device *dev,
4847                                               unsigned long event, void *ptr,
4848                                               u16 vid)
4849 {
4850         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4851         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4852         struct netdev_notifier_changeupper_info *info = ptr;
4853         struct netlink_ext_ack *extack;
4854         struct net_device *upper_dev;
4855         int err = 0;
4856
4857         extack = netdev_notifier_info_to_extack(&info->info);
4858
4859         switch (event) {
4860         case NETDEV_PRECHANGEUPPER:
4861                 upper_dev = info->upper_dev;
4862                 if (!netif_is_bridge_master(upper_dev) &&
4863                     !netif_is_macvlan(upper_dev)) {
4864                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4865                         return -EINVAL;
4866                 }
4867                 if (!info->linking)
4868                         break;
4869                 if (netdev_has_any_upper_dev(upper_dev) &&
4870                     (!netif_is_bridge_master(upper_dev) ||
4871                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4872                                                           upper_dev))) {
4873                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4874                         return -EINVAL;
4875                 }
4876                 if (netif_is_macvlan(upper_dev) &&
4877                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
4878                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4879                         return -EOPNOTSUPP;
4880                 }
4881                 break;
4882         case NETDEV_CHANGEUPPER:
4883                 upper_dev = info->upper_dev;
4884                 if (netif_is_bridge_master(upper_dev)) {
4885                         if (info->linking)
4886                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4887                                                                 vlan_dev,
4888                                                                 upper_dev,
4889                                                                 extack);
4890                         else
4891                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4892                                                            vlan_dev,
4893                                                            upper_dev);
4894                 } else if (netif_is_macvlan(upper_dev)) {
4895                         if (!info->linking)
4896                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4897                 } else {
4898                         err = -EINVAL;
4899                         WARN_ON(1);
4900                 }
4901                 break;
4902         }
4903
4904         return err;
4905 }
4906
4907 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4908                                                   struct net_device *lag_dev,
4909                                                   unsigned long event,
4910                                                   void *ptr, u16 vid)
4911 {
4912         struct net_device *dev;
4913         struct list_head *iter;
4914         int ret;
4915
4916         netdev_for_each_lower_dev(lag_dev, dev, iter) {
4917                 if (mlxsw_sp_port_dev_check(dev)) {
4918                         ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4919                                                                  event, ptr,
4920                                                                  vid);
4921                         if (ret)
4922                                 return ret;
4923                 }
4924         }
4925
4926         return 0;
4927 }
4928
4929 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4930                                          unsigned long event, void *ptr)
4931 {
4932         struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4933         u16 vid = vlan_dev_vlan_id(vlan_dev);
4934
4935         if (mlxsw_sp_port_dev_check(real_dev))
4936                 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4937                                                           event, ptr, vid);
4938         else if (netif_is_lag_master(real_dev))
4939                 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4940                                                               real_dev, event,
4941                                                               ptr, vid);
4942
4943         return 0;
4944 }
4945
4946 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4947                                            unsigned long event, void *ptr)
4948 {
4949         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4950         struct netdev_notifier_changeupper_info *info = ptr;
4951         struct netlink_ext_ack *extack;
4952         struct net_device *upper_dev;
4953
4954         if (!mlxsw_sp)
4955                 return 0;
4956
4957         extack = netdev_notifier_info_to_extack(&info->info);
4958
4959         switch (event) {
4960         case NETDEV_PRECHANGEUPPER:
4961                 upper_dev = info->upper_dev;
4962                 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
4963                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4964                         return -EOPNOTSUPP;
4965                 }
4966                 if (!info->linking)
4967                         break;
4968                 if (netif_is_macvlan(upper_dev) &&
4969                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
4970                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4971                         return -EOPNOTSUPP;
4972                 }
4973                 break;
4974         case NETDEV_CHANGEUPPER:
4975                 upper_dev = info->upper_dev;
4976                 if (info->linking)
4977                         break;
4978                 if (is_vlan_dev(upper_dev))
4979                         mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
4980                 if (netif_is_macvlan(upper_dev))
4981                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4982                 break;
4983         }
4984
4985         return 0;
4986 }
4987
4988 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
4989                                             unsigned long event, void *ptr)
4990 {
4991         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
4992         struct netdev_notifier_changeupper_info *info = ptr;
4993         struct netlink_ext_ack *extack;
4994
4995         if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
4996                 return 0;
4997
4998         extack = netdev_notifier_info_to_extack(&info->info);
4999
5000         /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
5001         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5002
5003         return -EOPNOTSUPP;
5004 }
5005
5006 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
5007 {
5008         struct netdev_notifier_changeupper_info *info = ptr;
5009
5010         if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
5011                 return false;
5012         return netif_is_l3_master(info->upper_dev);
5013 }
5014
5015 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
5016                                     unsigned long event, void *ptr)
5017 {
5018         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
5019         struct mlxsw_sp_span_entry *span_entry;
5020         struct mlxsw_sp *mlxsw_sp;
5021         int err = 0;
5022
5023         mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5024         if (event == NETDEV_UNREGISTER) {
5025                 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5026                 if (span_entry)
5027                         mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5028         }
5029         mlxsw_sp_span_respin(mlxsw_sp);
5030
5031         if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5032                 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5033                                                        event, ptr);
5034         else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5035                 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5036                                                        event, ptr);
5037         else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
5038                 err = mlxsw_sp_netdevice_router_port_event(dev);
5039         else if (mlxsw_sp_is_vrf_event(event, ptr))
5040                 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
5041         else if (mlxsw_sp_port_dev_check(dev))
5042                 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
5043         else if (netif_is_lag_master(dev))
5044                 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5045         else if (is_vlan_dev(dev))
5046                 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
5047         else if (netif_is_bridge_master(dev))
5048                 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
5049         else if (netif_is_macvlan(dev))
5050                 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
5051
5052         return notifier_from_errno(err);
5053 }
5054
5055 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5056         .notifier_call = mlxsw_sp_inetaddr_valid_event,
5057 };
5058
5059 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5060         .notifier_call = mlxsw_sp_inetaddr_event,
5061 };
5062
5063 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5064         .notifier_call = mlxsw_sp_inet6addr_valid_event,
5065 };
5066
5067 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5068         .notifier_call = mlxsw_sp_inet6addr_event,
5069 };
5070
5071 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
5072         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5073         {0, },
5074 };
5075
5076 static struct pci_driver mlxsw_sp1_pci_driver = {
5077         .name = mlxsw_sp1_driver_name,
5078         .id_table = mlxsw_sp1_pci_id_table,
5079 };
5080
5081 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5082         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
5083         {0, },
5084 };
5085
5086 static struct pci_driver mlxsw_sp2_pci_driver = {
5087         .name = mlxsw_sp2_driver_name,
5088         .id_table = mlxsw_sp2_pci_id_table,
5089 };
5090
5091 static int __init mlxsw_sp_module_init(void)
5092 {
5093         int err;
5094
5095         register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5096         register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5097         register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5098         register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5099
5100         err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
5101         if (err)
5102                 goto err_sp1_core_driver_register;
5103
5104         err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
5105         if (err)
5106                 goto err_sp2_core_driver_register;
5107
5108         err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5109         if (err)
5110                 goto err_sp1_pci_driver_register;
5111
5112         err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5113         if (err)
5114                 goto err_sp2_pci_driver_register;
5115
5116         return 0;
5117
5118 err_sp2_pci_driver_register:
5119         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5120 err_sp1_pci_driver_register:
5121         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5122 err_sp2_core_driver_register:
5123         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5124 err_sp1_core_driver_register:
5125         unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5126         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5127         unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5128         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5129         return err;
5130 }
5131
5132 static void __exit mlxsw_sp_module_exit(void)
5133 {
5134         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5135         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5136         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5137         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5138         unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5139         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5140         unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5141         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5142 }
5143
5144 module_init(mlxsw_sp_module_init);
5145 module_exit(mlxsw_sp_module_exit);
5146
5147 MODULE_LICENSE("Dual BSD/GPL");
5148 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5149 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5150 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5151 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5152 /*(DEBLOBBED)*/