1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/slab.h>
11 #include <linux/device.h>
12 #include <linux/skbuff.h>
13 #include <linux/if_vlan.h>
14 #include <net/switchdev.h>
24 static const char mlxsw_sib_driver_name[] = "mlxsw_switchib";
25 static const char mlxsw_sib2_driver_name[] = "mlxsw_switchib2";
27 struct mlxsw_sib_port;
30 struct mlxsw_sib_port **ports;
31 struct mlxsw_core *core;
32 const struct mlxsw_bus_info *bus_info;
35 struct mlxsw_sib_port {
36 struct mlxsw_sib *mlxsw_sib;
47 MLXSW_ITEM32(tx_v1, hdr, version, 0x00, 28, 4);
50 * Packet control type.
51 * 0 - Ethernet control (e.g. EMADs, LACP)
54 MLXSW_ITEM32(tx_v1, hdr, ctl, 0x00, 26, 2);
57 * Packet protocol type. Must be set to 1 (Ethernet).
59 MLXSW_ITEM32(tx_v1, hdr, proto, 0x00, 21, 3);
62 * Switch partition ID. Must be set to 0.
64 MLXSW_ITEM32(tx_v1, hdr, swid, 0x00, 12, 3);
66 /* tx_v1_hdr_control_tclass
67 * Indicates if the packet should use the control TClass and not one
68 * of the data TClasses.
70 MLXSW_ITEM32(tx_v1, hdr, control_tclass, 0x00, 6, 1);
73 * Destination local port for unicast packets.
74 * Destination multicast ID for multicast packets.
76 * Control packets are directed to a specific egress port, while data
77 * packets are transmitted through the CPU port (0) into the switch partition,
78 * where forwarding rules are applied.
80 MLXSW_ITEM32(tx_v1, hdr, port_mid, 0x04, 16, 16);
86 MLXSW_ITEM32(tx_v1, hdr, type, 0x0C, 0, 4);
89 mlxsw_sib_tx_v1_hdr_construct(struct sk_buff *skb,
90 const struct mlxsw_tx_info *tx_info)
92 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
94 memset(txhdr, 0, MLXSW_TXHDR_LEN);
96 mlxsw_tx_v1_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
97 mlxsw_tx_v1_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
98 mlxsw_tx_v1_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
99 mlxsw_tx_v1_hdr_swid_set(txhdr, 0);
100 mlxsw_tx_v1_hdr_control_tclass_set(txhdr, 1);
101 mlxsw_tx_v1_hdr_port_mid_set(txhdr, tx_info->local_port);
102 mlxsw_tx_v1_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
106 mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port *mlxsw_sib_port,
109 struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
110 char paos_pl[MLXSW_REG_PAOS_LEN];
112 mlxsw_reg_paos_pack(paos_pl, mlxsw_sib_port->local_port,
113 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
114 MLXSW_PORT_ADMIN_STATUS_DOWN);
115 return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(paos), paos_pl);
118 static int mlxsw_sib_port_mtu_set(struct mlxsw_sib_port *mlxsw_sib_port,
121 struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
122 char pmtu_pl[MLXSW_REG_PMTU_LEN];
126 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, 0);
127 err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
130 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
135 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, mtu);
136 return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
139 static int mlxsw_sib_port_set(struct mlxsw_sib_port *mlxsw_sib_port, u8 port)
141 struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
142 char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
145 mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sib_port->local_port);
146 mlxsw_reg_plib_ib_port_set(plib_pl, port);
147 err = mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(plib), plib_pl);
151 static int mlxsw_sib_port_swid_set(struct mlxsw_sib_port *mlxsw_sib_port,
154 struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
155 char pspa_pl[MLXSW_REG_PSPA_LEN];
157 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sib_port->local_port);
158 return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pspa), pspa_pl);
161 static int mlxsw_sib_port_module_info_get(struct mlxsw_sib *mlxsw_sib,
162 u8 local_port, u8 *p_module,
165 char pmlp_pl[MLXSW_REG_PMLP_LEN];
168 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
169 err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmlp), pmlp_pl);
172 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
173 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
177 static int mlxsw_sib_port_speed_set(struct mlxsw_sib_port *mlxsw_sib_port,
178 u16 speed, u16 width)
180 struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
181 char ptys_pl[MLXSW_REG_PTYS_LEN];
183 mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sib_port->local_port, speed,
185 return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(ptys), ptys_pl);
188 static bool mlxsw_sib_port_created(struct mlxsw_sib *mlxsw_sib, u8 local_port)
190 return mlxsw_sib->ports[local_port] != NULL;
193 static int __mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
196 struct mlxsw_sib_port *mlxsw_sib_port;
199 mlxsw_sib_port = kzalloc(sizeof(*mlxsw_sib_port), GFP_KERNEL);
202 mlxsw_sib_port->mlxsw_sib = mlxsw_sib;
203 mlxsw_sib_port->local_port = local_port;
204 mlxsw_sib_port->mapping.module = module;
206 err = mlxsw_sib_port_swid_set(mlxsw_sib_port, 0);
208 dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set SWID\n",
209 mlxsw_sib_port->local_port);
210 goto err_port_swid_set;
213 /* Expose the IB port number as it's front panel name */
214 err = mlxsw_sib_port_set(mlxsw_sib_port, module + 1);
216 dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set IB port\n",
217 mlxsw_sib_port->local_port);
218 goto err_port_ib_set;
221 /* Supports all speeds from SDR to FDR (bitmask) and support bus width
222 * of 1x, 2x and 4x (3 bits bitmask)
224 err = mlxsw_sib_port_speed_set(mlxsw_sib_port,
225 MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
228 dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set speed\n",
229 mlxsw_sib_port->local_port);
230 goto err_port_speed_set;
233 /* Change to the maximum MTU the device supports, the SMA will take
234 * care of the active MTU
236 err = mlxsw_sib_port_mtu_set(mlxsw_sib_port, MLXSW_IB_DEFAULT_MTU);
238 dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set MTU\n",
239 mlxsw_sib_port->local_port);
240 goto err_port_mtu_set;
243 err = mlxsw_sib_port_admin_status_set(mlxsw_sib_port, true);
245 dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
246 mlxsw_sib_port->local_port);
247 goto err_port_admin_set;
250 mlxsw_core_port_ib_set(mlxsw_sib->core, mlxsw_sib_port->local_port,
252 mlxsw_sib->ports[local_port] = mlxsw_sib_port;
259 mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
261 kfree(mlxsw_sib_port);
265 static int mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
270 err = mlxsw_core_port_init(mlxsw_sib->core, local_port);
272 dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to init core port\n",
276 err = __mlxsw_sib_port_create(mlxsw_sib, local_port, module, width);
278 goto err_port_create;
283 mlxsw_core_port_fini(mlxsw_sib->core, local_port);
287 static void __mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
289 struct mlxsw_sib_port *mlxsw_sib_port = mlxsw_sib->ports[local_port];
291 mlxsw_core_port_clear(mlxsw_sib->core, local_port, mlxsw_sib);
292 mlxsw_sib->ports[local_port] = NULL;
293 mlxsw_sib_port_admin_status_set(mlxsw_sib_port, false);
294 mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
295 kfree(mlxsw_sib_port);
298 static void mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
300 __mlxsw_sib_port_remove(mlxsw_sib, local_port);
301 mlxsw_core_port_fini(mlxsw_sib->core, local_port);
304 static void mlxsw_sib_ports_remove(struct mlxsw_sib *mlxsw_sib)
308 for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++)
309 if (mlxsw_sib_port_created(mlxsw_sib, i))
310 mlxsw_sib_port_remove(mlxsw_sib, i);
311 kfree(mlxsw_sib->ports);
314 static int mlxsw_sib_ports_create(struct mlxsw_sib *mlxsw_sib)
321 alloc_size = sizeof(struct mlxsw_sib_port *) * MLXSW_PORT_MAX_IB_PORTS;
322 mlxsw_sib->ports = kzalloc(alloc_size, GFP_KERNEL);
323 if (!mlxsw_sib->ports)
326 for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++) {
327 err = mlxsw_sib_port_module_info_get(mlxsw_sib, i, &module,
330 goto err_port_module_info_get;
333 err = mlxsw_sib_port_create(mlxsw_sib, i, module, width);
335 goto err_port_create;
340 err_port_module_info_get:
341 for (i--; i >= 1; i--)
342 if (mlxsw_sib_port_created(mlxsw_sib, i))
343 mlxsw_sib_port_remove(mlxsw_sib, i);
344 kfree(mlxsw_sib->ports);
349 mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port *mlxsw_sib_port,
350 enum mlxsw_reg_pude_oper_status status)
352 if (status == MLXSW_PORT_OPER_STATUS_UP)
353 pr_info("ib link for port %d - up\n",
354 mlxsw_sib_port->mapping.module + 1);
356 pr_info("ib link for port %d - down\n",
357 mlxsw_sib_port->mapping.module + 1);
360 static void mlxsw_sib_pude_event_func(const struct mlxsw_reg_info *reg,
361 char *pude_pl, void *priv)
363 struct mlxsw_sib *mlxsw_sib = priv;
364 struct mlxsw_sib_port *mlxsw_sib_port;
365 enum mlxsw_reg_pude_oper_status status;
368 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
369 mlxsw_sib_port = mlxsw_sib->ports[local_port];
370 if (!mlxsw_sib_port) {
371 dev_warn(mlxsw_sib->bus_info->dev, "Port %d: Link event received for non-existent port\n",
376 status = mlxsw_reg_pude_oper_status_get(pude_pl);
377 mlxsw_sib_pude_ib_event_func(mlxsw_sib_port, status);
380 static const struct mlxsw_listener mlxsw_sib_listener[] = {
381 MLXSW_EVENTL(mlxsw_sib_pude_event_func, PUDE, EMAD),
384 static int mlxsw_sib_taps_init(struct mlxsw_sib *mlxsw_sib)
389 for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
390 err = mlxsw_core_trap_register(mlxsw_sib->core,
391 &mlxsw_sib_listener[i],
394 goto err_rx_listener_register;
399 err_rx_listener_register:
400 for (i--; i >= 0; i--) {
401 mlxsw_core_trap_unregister(mlxsw_sib->core,
402 &mlxsw_sib_listener[i],
409 static void mlxsw_sib_traps_fini(struct mlxsw_sib *mlxsw_sib)
413 for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
414 mlxsw_core_trap_unregister(mlxsw_sib->core,
415 &mlxsw_sib_listener[i], mlxsw_sib);
419 static int mlxsw_sib_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
421 char htgt_pl[MLXSW_REG_HTGT_LEN];
423 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
424 MLXSW_REG_HTGT_INVALID_POLICER,
425 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
426 MLXSW_REG_HTGT_DEFAULT_TC);
427 mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
428 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
429 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD);
430 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
433 static int mlxsw_sib_init(struct mlxsw_core *mlxsw_core,
434 const struct mlxsw_bus_info *mlxsw_bus_info)
436 struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
439 mlxsw_sib->core = mlxsw_core;
440 mlxsw_sib->bus_info = mlxsw_bus_info;
442 err = mlxsw_sib_ports_create(mlxsw_sib);
444 dev_err(mlxsw_sib->bus_info->dev, "Failed to create ports\n");
448 err = mlxsw_sib_taps_init(mlxsw_sib);
450 dev_err(mlxsw_sib->bus_info->dev, "Failed to set traps\n");
451 goto err_traps_init_err;
457 mlxsw_sib_ports_remove(mlxsw_sib);
461 static void mlxsw_sib_fini(struct mlxsw_core *mlxsw_core)
463 struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
465 mlxsw_sib_traps_fini(mlxsw_sib);
466 mlxsw_sib_ports_remove(mlxsw_sib);
469 static const struct mlxsw_config_profile mlxsw_sib_config_profile = {
470 .used_max_system_port = 1,
471 .max_system_port = 48000,
479 .type = MLXSW_PORT_SWID_TYPE_IB,
484 static struct mlxsw_driver mlxsw_sib_driver = {
485 .kind = mlxsw_sib_driver_name,
486 .priv_size = sizeof(struct mlxsw_sib),
487 .init = mlxsw_sib_init,
488 .fini = mlxsw_sib_fini,
489 .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
490 .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
491 .txhdr_len = MLXSW_TXHDR_LEN,
492 .profile = &mlxsw_sib_config_profile,
495 static struct mlxsw_driver mlxsw_sib2_driver = {
496 .kind = mlxsw_sib2_driver_name,
497 .priv_size = sizeof(struct mlxsw_sib),
498 .init = mlxsw_sib_init,
499 .fini = mlxsw_sib_fini,
500 .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
501 .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
502 .txhdr_len = MLXSW_TXHDR_LEN,
503 .profile = &mlxsw_sib_config_profile,
506 static const struct pci_device_id mlxsw_sib_pci_id_table[] = {
507 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB), 0},
511 static struct pci_driver mlxsw_sib_pci_driver = {
512 .name = mlxsw_sib_driver_name,
513 .id_table = mlxsw_sib_pci_id_table,
516 static const struct pci_device_id mlxsw_sib2_pci_id_table[] = {
517 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB2), 0},
521 static struct pci_driver mlxsw_sib2_pci_driver = {
522 .name = mlxsw_sib2_driver_name,
523 .id_table = mlxsw_sib2_pci_id_table,
526 static int __init mlxsw_sib_module_init(void)
530 err = mlxsw_core_driver_register(&mlxsw_sib_driver);
534 err = mlxsw_core_driver_register(&mlxsw_sib2_driver);
536 goto err_sib2_driver_register;
538 err = mlxsw_pci_driver_register(&mlxsw_sib_pci_driver);
540 goto err_sib_pci_driver_register;
542 err = mlxsw_pci_driver_register(&mlxsw_sib2_pci_driver);
544 goto err_sib2_pci_driver_register;
548 err_sib2_pci_driver_register:
549 mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
550 err_sib_pci_driver_register:
551 mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
552 err_sib2_driver_register:
553 mlxsw_core_driver_unregister(&mlxsw_sib_driver);
557 static void __exit mlxsw_sib_module_exit(void)
559 mlxsw_pci_driver_unregister(&mlxsw_sib2_pci_driver);
560 mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
561 mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
562 mlxsw_core_driver_unregister(&mlxsw_sib_driver);
565 module_init(mlxsw_sib_module_init);
566 module_exit(mlxsw_sib_module_exit);
568 MODULE_LICENSE("Dual BSD/GPL");
569 MODULE_AUTHOR("Elad Raz <eladr@@mellanox.com>");
570 MODULE_DESCRIPTION("Mellanox SwitchIB and SwitchIB-2 driver");
571 MODULE_ALIAS("mlxsw_switchib2");
572 MODULE_DEVICE_TABLE(pci, mlxsw_sib_pci_id_table);
573 MODULE_DEVICE_TABLE(pci, mlxsw_sib2_pci_id_table);