drivers/net/ethernet/mscc/ocelot_board.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7 #include <linux/interrupt.h>
   8 #include <linux/module.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/of_mdio.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/skbuff.h>
  13
  14 #include "ocelot.h"
  15
  16 static int ocelot_parse_ifh(u32 *ifh, struct frame_info *info)
  17 {
  18         int i;
  19         u8 llen, wlen;
  20
  21         /* The IFH is in network order, switch to CPU order */
  22         for (i = 0; i < IFH_LEN; i++)
  23                 ifh[i] = ntohl((__force __be32)ifh[i]);
  24
  25         wlen = (ifh[1] >> 7) & 0xff;
  26         llen = (ifh[1] >> 15) & 0x3f;
  27         info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;
  28
  29         info->port = (ifh[2] & GENMASK(14, 11)) >> 11;
  30
  31         info->cpuq = (ifh[3] & GENMASK(27, 20)) >> 20;
  32         info->tag_type = (ifh[3] & BIT(16)) >> 16;
  33         info->vid = ifh[3] & GENMASK(11, 0);
  34
  35         return 0;
  36 }
  37
  38 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
  39                                 u32 *rval)
  40 {
  41         u32 val;
  42         u32 bytes_valid;
  43
  44         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  45         if (val == XTR_NOT_READY) {
  46                 if (ifh)
  47                         return -EIO;
  48
  49                 do {
  50                         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  51                 } while (val == XTR_NOT_READY);
  52         }
  53
  54         switch (val) {
  55         case XTR_ABORT:
  56                 return -EIO;
  57         case XTR_EOF_0:
  58         case XTR_EOF_1:
  59         case XTR_EOF_2:
  60         case XTR_EOF_3:
  61         case XTR_PRUNED:
  62                 bytes_valid = XTR_VALID_BYTES(val);
  63                 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  64                 if (val == XTR_ESCAPE)
  65                         *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  66                 else
  67                         *rval = val;
  68
  69                 return bytes_valid;
  70         case XTR_ESCAPE:
  71                 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  72
  73                 return 4;
  74         default:
  75                 *rval = val;
  76
  77                 return 4;
  78         }
  79 }
  80
  81 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
  82 {
  83         struct ocelot *ocelot = arg;
  84         int i = 0, grp = 0;
  85         int err = 0;
  86
  87         if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)))
  88                 return IRQ_NONE;
  89
  90         do {
  91                 struct sk_buff *skb;
  92                 struct net_device *dev;
  93                 u32 *buf;
  94                 int sz, len, buf_len;
  95                 u32 ifh[4];
  96                 u32 val;
  97                 struct frame_info info;
  98
  99                 for (i = 0; i < IFH_LEN; i++) {
 100                         err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
 101                         if (err != 4)
 102                                 break;
 103                 }
 104
 105                 if (err != 4)
 106                         break;
 107
 108                 /* At this point the IFH was read correctly, so it is safe to
 109                  * presume that there is no error. The err needs to be reset
 110                  * otherwise a frame could come in CPU queue between the while
 111                  * condition and the check for error later on. And in that case
 112                  * the new frame is just removed and not processed.
 113                  */
 114                 err = 0;
 115
 116                 ocelot_parse_ifh(ifh, &info);
 117
 118                 dev = ocelot->ports[info.port]->dev;
 119
 120                 skb = netdev_alloc_skb(dev, info.len);
 121
 122                 if (unlikely(!skb)) {
 123                         netdev_err(dev, "Unable to allocate sk_buff\n");
 124                         err = -ENOMEM;
 125                         break;
 126                 }
 127                 buf_len = info.len - ETH_FCS_LEN;
 128                 buf = (u32 *)skb_put(skb, buf_len);
 129
 130                 len = 0;
 131                 do {
 132                         sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 133                         *buf++ = val;
 134                         len += sz;
 135                 } while (len < buf_len);
 136
 137                 /* Read the FCS and discard it */
 138                 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 139                 /* Update the statistics if part of the FCS was read before */
 140                 len -= ETH_FCS_LEN - sz;
 141
 142                 if (sz < 0) {
 143                         err = sz;
 144                         break;
 145                 }
 146
 147                 /* Everything we see on an interface that is in the HW bridge
 148                  * has already been forwarded.
 149                  */
 150                 if (ocelot->bridge_mask & BIT(info.port))
 151                         skb->offload_fwd_mark = 1;
 152
 153                 skb->protocol = eth_type_trans(skb, dev);
 154                 netif_rx(skb);
 155                 dev->stats.rx_bytes += len;
 156                 dev->stats.rx_packets++;
 157         } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp));
 158
 159         if (err)
 160                 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
 161                         ocelot_read_rix(ocelot, QS_XTR_RD, grp);
 162
 163         return IRQ_HANDLED;
 164 }
 165
 166 static const struct of_device_id mscc_ocelot_match[] = {
 167         { .compatible = "mscc,vsc7514-switch" },
 168         { }
 169 };
 170 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
 171
 172 static int mscc_ocelot_probe(struct platform_device *pdev)
 173 {
 174         int err, irq;
 175         unsigned int i;
 176         struct device_node *np = pdev->dev.of_node;
 177         struct device_node *ports, *portnp;
 178         struct ocelot *ocelot;
 179         u32 val;
 180
 181         struct {
 182                 enum ocelot_target id;
 183                 char *name;
 184         } res[] = {
 185                 { SYS, "sys" },
 186                 { REW, "rew" },
 187                 { QSYS, "qsys" },
 188                 { ANA, "ana" },
 189                 { QS, "qs" },
 190                 { HSIO, "hsio" },
 191         };
 192
 193         if (!np && !pdev->dev.platform_data)
 194                 return -ENODEV;
 195
 196         ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);
 197         if (!ocelot)
 198                 return -ENOMEM;
 199
 200         platform_set_drvdata(pdev, ocelot);
 201         ocelot->dev = &pdev->dev;
 202
 203         for (i = 0; i < ARRAY_SIZE(res); i++) {
 204                 struct regmap *target;
 205
 206                 target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
 207                 if (IS_ERR(target))
 208                         return PTR_ERR(target);
 209
 210                 ocelot->targets[res[i].id] = target;
 211         }
 212
 213         err = ocelot_chip_init(ocelot);
 214         if (err)
 215                 return err;
 216
 217         irq = platform_get_irq_byname(pdev, "xtr");
 218         if (irq < 0)
 219                 return -ENODEV;
 220
 221         err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 222                                         ocelot_xtr_irq_handler, IRQF_ONESHOT,
 223                                         "frame extraction", ocelot);
 224         if (err)
 225                 return err;
 226
 227         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
 228         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 229
 230         do {
 231                 msleep(1);
 232                 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
 233                                   &val);
 234         } while (val);
 235
 236         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 237         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
 238
 239         ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
 240
 241         ports = of_get_child_by_name(np, "ethernet-ports");
 242         if (!ports) {
 243                 dev_err(&pdev->dev, "no ethernet-ports child node found\n");
 244                 return -ENODEV;
 245         }
 246
 247         ocelot->num_phys_ports = of_get_child_count(ports);
 248
 249         ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports,
 250                                      sizeof(struct ocelot_port *), GFP_KERNEL);
 251
 252         INIT_LIST_HEAD(&ocelot->multicast);
 253         ocelot_init(ocelot);
 254
 255         ocelot_rmw(ocelot, HSIO_HW_CFG_DEV1G_4_MODE |
 256                      HSIO_HW_CFG_DEV1G_6_MODE |
 257                      HSIO_HW_CFG_DEV1G_9_MODE,
 258                      HSIO_HW_CFG_DEV1G_4_MODE |
 259                      HSIO_HW_CFG_DEV1G_6_MODE |
 260                      HSIO_HW_CFG_DEV1G_9_MODE,
 261                      HSIO_HW_CFG);
 262
 263         for_each_available_child_of_node(ports, portnp) {
 264                 struct device_node *phy_node;
 265                 struct phy_device *phy;
 266                 struct resource *res;
 267                 void __iomem *regs;
 268                 char res_name[8];
 269                 u32 port;
 270
 271                 if (of_property_read_u32(portnp, "reg", &port))
 272                         continue;
 273
 274                 snprintf(res_name, sizeof(res_name), "port%d", port);
 275
 276                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 277                                                    res_name);
 278                 regs = devm_ioremap_resource(&pdev->dev, res);
 279                 if (IS_ERR(regs))
 280                         continue;
 281
 282                 phy_node = of_parse_phandle(portnp, "phy-handle", 0);
 283                 if (!phy_node)
 284                         continue;
 285
 286                 phy = of_phy_find_device(phy_node);
 287                 if (!phy)
 288                         continue;
 289
 290                 err = ocelot_probe_port(ocelot, port, regs, phy);
 291                 if (err) {
 292                         dev_err(&pdev->dev, "failed to probe ports\n");
 293                         goto err_probe_ports;
 294                 }
 295         }
 296
 297         register_netdevice_notifier(&ocelot_netdevice_nb);
 298
 299         dev_info(&pdev->dev, "Ocelot switch probed\n");
 300
 301         return 0;
 302
 303 err_probe_ports:
 304         return err;
 305 }
 306
 307 static int mscc_ocelot_remove(struct platform_device *pdev)
 308 {
 309         struct ocelot *ocelot = platform_get_drvdata(pdev);
 310
 311         ocelot_deinit(ocelot);
 312         unregister_netdevice_notifier(&ocelot_netdevice_nb);
 313
 314         return 0;
 315 }
 316
 317 static struct platform_driver mscc_ocelot_driver = {
 318         .probe = mscc_ocelot_probe,
 319         .remove = mscc_ocelot_remove,
 320         .driver = {
 321                 .name = "ocelot-switch",
 322                 .of_match_table = mscc_ocelot_match,
 323         },
 324 };
 325
 326 module_platform_driver(mscc_ocelot_driver);
 327
 328 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
 329 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
 330 MODULE_LICENSE("Dual MIT/GPL");