drivers/net/ethernet/neterion/vxge/vxge-config.c

   1 /******************************************************************************
   2  * This software may be used and distributed according to the terms of
   3  * the GNU General Public License (GPL), incorporated herein by reference.
   4  * Drivers based on or derived from this code fall under the GPL and must
   5  * retain the authorship, copyright and license notice.  This file is not
   6  * a complete program and may only be used when the entire operating
   7  * system is licensed under the GPL.
   8  * See the file COPYING in this distribution for more information.
   9  *
  10  * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
  11  *                Virtualized Server Adapter.
  12  * Copyright(c) 2002-2010 Exar Corp.
  13  ******************************************************************************/
  14 #include <linux/vmalloc.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18
  19 #include "vxge-traffic.h"
  20 #include "vxge-config.h"
  21 #include "vxge-main.h"
  22
  23 #define VXGE_HW_VPATH_STATS_PIO_READ(offset) {                          \
  24         status = __vxge_hw_vpath_stats_access(vpath,                    \
  25                                               VXGE_HW_STATS_OP_READ,    \
  26                                               offset,                   \
  27                                               &val64);                  \
  28         if (status != VXGE_HW_OK)                                       \
  29                 return status;                                          \
  30 }
  31
  32 static void
  33 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
  34 {
  35         u64 val64;
  36
  37         val64 = readq(&vp_reg->rxmac_vcfg0);
  38         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
  39         writeq(val64, &vp_reg->rxmac_vcfg0);
  40         val64 = readq(&vp_reg->rxmac_vcfg0);
  41 }
  42
  43 /*
  44  * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
  45  */
  46 int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
  47 {
  48         struct vxge_hw_vpath_reg __iomem *vp_reg;
  49         struct __vxge_hw_virtualpath *vpath;
  50         u64 val64, rxd_count, rxd_spat;
  51         int count = 0, total_count = 0;
  52
  53         vpath = &hldev->virtual_paths[vp_id];
  54         vp_reg = vpath->vp_reg;
  55
  56         vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
  57
  58         /* Check that the ring controller for this vpath has enough free RxDs
  59          * to send frames to the host.  This is done by reading the
  60          * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
  61          * RXD_SPAT value for the vpath.
  62          */
  63         val64 = readq(&vp_reg->prc_cfg6);
  64         rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
  65         /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
  66          * leg room.
  67          */
  68         rxd_spat *= 2;
  69
  70         do {
  71                 mdelay(1);
  72
  73                 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
  74
  75                 /* Check that the ring controller for this vpath does
  76                  * not have any frame in its pipeline.
  77                  */
  78                 val64 = readq(&vp_reg->frm_in_progress_cnt);
  79                 if ((rxd_count <= rxd_spat) || (val64 > 0))
  80                         count = 0;
  81                 else
  82                         count++;
  83                 total_count++;
  84         } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
  85                         (total_count < VXGE_HW_MAX_POLLING_COUNT));
  86
  87         if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
  88                 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
  89                         __func__);
  90
  91         return total_count;
  92 }
  93
  94 /* vxge_hw_device_wait_receive_idle - This function waits until all frames
  95  * stored in the frame buffer for each vpath assigned to the given
  96  * function (hldev) have been sent to the host.
  97  */
  98 void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
  99 {
 100         int i, total_count = 0;
 101
 102         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 103                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 104                         continue;
 105
 106                 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
 107                 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
 108                         break;
 109         }
 110 }
 111
 112 /*
 113  * __vxge_hw_device_register_poll
 114  * Will poll certain register for specified amount of time.
 115  * Will poll until masked bit is not cleared.
 116  */
 117 static enum vxge_hw_status
 118 __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
 119 {
 120         u64 val64;
 121         u32 i = 0;
 122
 123         udelay(10);
 124
 125         do {
 126                 val64 = readq(reg);
 127                 if (!(val64 & mask))
 128                         return VXGE_HW_OK;
 129                 udelay(100);
 130         } while (++i <= 9);
 131
 132         i = 0;
 133         do {
 134                 val64 = readq(reg);
 135                 if (!(val64 & mask))
 136                         return VXGE_HW_OK;
 137                 mdelay(1);
 138         } while (++i <= max_millis);
 139
 140         return VXGE_HW_FAIL;
 141 }
 142
 143 static inline enum vxge_hw_status
 144 __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
 145                           u64 mask, u32 max_millis)
 146 {
 147         __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
 148         wmb();
 149         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
 150         wmb();
 151
 152         return __vxge_hw_device_register_poll(addr, mask, max_millis);
 153 }
 154
 155 static enum vxge_hw_status
 156 vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
 157                      u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
 158                      u64 *steer_ctrl)
 159 {
 160         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
 161         enum vxge_hw_status status;
 162         u64 val64;
 163         u32 retry = 0, max_retry = 3;
 164
 165         spin_lock(&vpath->lock);
 166         if (!vpath->vp_open) {
 167                 spin_unlock(&vpath->lock);
 168                 max_retry = 100;
 169         }
 170
 171         writeq(*data0, &vp_reg->rts_access_steer_data0);
 172         writeq(*data1, &vp_reg->rts_access_steer_data1);
 173         wmb();
 174
 175         val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
 176                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
 177                 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
 178                 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
 179                 *steer_ctrl;
 180
 181         status = __vxge_hw_pio_mem_write64(val64,
 182                                            &vp_reg->rts_access_steer_ctrl,
 183                                            VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
 184                                            VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 185
 186         /* The __vxge_hw_device_register_poll can udelay for a significant
 187          * amount of time, blocking other process from the CPU.  If it delays
 188          * for ~5secs, a NMI error can occur.  A way around this is to give up
 189          * the processor via msleep, but this is not allowed is under lock.
 190          * So, only allow it to sleep for ~4secs if open.  Otherwise, delay for
 191          * 1sec and sleep for 10ms until the firmware operation has completed
 192          * or timed-out.
 193          */
 194         while ((status != VXGE_HW_OK) && retry++ < max_retry) {
 195                 if (!vpath->vp_open)
 196                         msleep(20);
 197                 status = __vxge_hw_device_register_poll(
 198                                         &vp_reg->rts_access_steer_ctrl,
 199                                         VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
 200                                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 201         }
 202
 203         if (status != VXGE_HW_OK)
 204                 goto out;
 205
 206         val64 = readq(&vp_reg->rts_access_steer_ctrl);
 207         if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
 208                 *data0 = readq(&vp_reg->rts_access_steer_data0);
 209                 *data1 = readq(&vp_reg->rts_access_steer_data1);
 210                 *steer_ctrl = val64;
 211         } else
 212                 status = VXGE_HW_FAIL;
 213
 214 out:
 215         if (vpath->vp_open)
 216                 spin_unlock(&vpath->lock);
 217         return status;
 218 }
 219
 220 enum vxge_hw_status
 221 vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
 222                              u32 *minor, u32 *build)
 223 {
 224         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 225         struct __vxge_hw_virtualpath *vpath;
 226         enum vxge_hw_status status;
 227
 228         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 229
 230         status = vxge_hw_vpath_fw_api(vpath,
 231                                       VXGE_HW_FW_UPGRADE_ACTION,
 232                                       VXGE_HW_FW_UPGRADE_MEMO,
 233                                       VXGE_HW_FW_UPGRADE_OFFSET_READ,
 234                                       &data0, &data1, &steer_ctrl);
 235         if (status != VXGE_HW_OK)
 236                 return status;
 237
 238         *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
 239         *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
 240         *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
 241
 242         return status;
 243 }
 244
 245 enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
 246 {
 247         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 248         struct __vxge_hw_virtualpath *vpath;
 249         enum vxge_hw_status status;
 250         u32 ret;
 251
 252         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 253
 254         status = vxge_hw_vpath_fw_api(vpath,
 255                                       VXGE_HW_FW_UPGRADE_ACTION,
 256                                       VXGE_HW_FW_UPGRADE_MEMO,
 257                                       VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
 258                                       &data0, &data1, &steer_ctrl);
 259         if (status != VXGE_HW_OK) {
 260                 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
 261                 goto exit;
 262         }
 263
 264         ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
 265         if (ret != 1) {
 266                 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
 267                                 __func__, ret);
 268                 status = VXGE_HW_FAIL;
 269         }
 270
 271 exit:
 272         return status;
 273 }
 274
 275 enum vxge_hw_status
 276 vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
 277 {
 278         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 279         struct __vxge_hw_virtualpath *vpath;
 280         enum vxge_hw_status status;
 281         int ret_code, sec_code;
 282
 283         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 284
 285         /* send upgrade start command */
 286         status = vxge_hw_vpath_fw_api(vpath,
 287                                       VXGE_HW_FW_UPGRADE_ACTION,
 288                                       VXGE_HW_FW_UPGRADE_MEMO,
 289                                       VXGE_HW_FW_UPGRADE_OFFSET_START,
 290                                       &data0, &data1, &steer_ctrl);
 291         if (status != VXGE_HW_OK) {
 292                 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
 293                                 __func__);
 294                 return status;
 295         }
 296
 297         /* Transfer fw image to adapter 16 bytes at a time */
 298         for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
 299                 steer_ctrl = 0;
 300
 301                 /* The next 128bits of fwdata to be loaded onto the adapter */
 302                 data0 = *((u64 *)fwdata);
 303                 data1 = *((u64 *)fwdata + 1);
 304
 305                 status = vxge_hw_vpath_fw_api(vpath,
 306                                               VXGE_HW_FW_UPGRADE_ACTION,
 307                                               VXGE_HW_FW_UPGRADE_MEMO,
 308                                               VXGE_HW_FW_UPGRADE_OFFSET_SEND,
 309                                               &data0, &data1, &steer_ctrl);
 310                 if (status != VXGE_HW_OK) {
 311                         vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
 312                                         __func__);
 313                         goto out;
 314                 }
 315
 316                 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
 317                 switch (ret_code) {
 318                 case VXGE_HW_FW_UPGRADE_OK:
 319                         /* All OK, send next 16 bytes. */
 320                         break;
 321                 case VXGE_FW_UPGRADE_BYTES2SKIP:
 322                         /* skip bytes in the stream */
 323                         fwdata += (data0 >> 8) & 0xFFFFFFFF;
 324                         break;
 325                 case VXGE_HW_FW_UPGRADE_DONE:
 326                         goto out;
 327                 case VXGE_HW_FW_UPGRADE_ERR:
 328                         sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
 329                         switch (sec_code) {
 330                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
 331                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
 332                                 printk(KERN_ERR
 333                                        "corrupted data from .ncf file\n");
 334                                 break;
 335                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
 336                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
 337                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
 338                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
 339                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
 340                                 printk(KERN_ERR "invalid .ncf file\n");
 341                                 break;
 342                         case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
 343                                 printk(KERN_ERR "buffer overflow\n");
 344                                 break;
 345                         case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
 346                                 printk(KERN_ERR "failed to flash the image\n");
 347                                 break;
 348                         case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
 349                                 printk(KERN_ERR
 350                                        "generic error. Unknown error type\n");
 351                                 break;
 352                         default:
 353                                 printk(KERN_ERR "Unknown error of type %d\n",
 354                                        sec_code);
 355                                 break;
 356                         }
 357                         status = VXGE_HW_FAIL;
 358                         goto out;
 359                 default:
 360                         printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
 361                         status = VXGE_HW_FAIL;
 362                         goto out;
 363                 }
 364                 /* point to next 16 bytes */
 365                 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
 366         }
 367 out:
 368         return status;
 369 }
 370
 371 enum vxge_hw_status
 372 vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
 373                                 struct eprom_image *img)
 374 {
 375         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 376         struct __vxge_hw_virtualpath *vpath;
 377         enum vxge_hw_status status;
 378         int i;
 379
 380         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 381
 382         for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
 383                 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
 384                 data1 = steer_ctrl = 0;
 385
 386                 status = vxge_hw_vpath_fw_api(vpath,
 387                         VXGE_HW_FW_API_GET_EPROM_REV,
 388                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 389                         0, &data0, &data1, &steer_ctrl);
 390                 if (status != VXGE_HW_OK)
 391                         break;
 392
 393                 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
 394                 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
 395                 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
 396                 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
 397         }
 398
 399         return status;
 400 }
 401
 402 /*
 403  * __vxge_hw_channel_free - Free memory allocated for channel
 404  * This function deallocates memory from the channel and various arrays
 405  * in the channel
 406  */
 407 static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
 408 {
 409         kfree(channel->work_arr);
 410         kfree(channel->free_arr);
 411         kfree(channel->reserve_arr);
 412         kfree(channel->orig_arr);
 413         kfree(channel);
 414 }
 415
 416 /*
 417  * __vxge_hw_channel_initialize - Initialize a channel
 418  * This function initializes a channel by properly setting the
 419  * various references
 420  */
 421 static enum vxge_hw_status
 422 __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
 423 {
 424         u32 i;
 425         struct __vxge_hw_virtualpath *vpath;
 426
 427         vpath = channel->vph->vpath;
 428
 429         if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
 430                 for (i = 0; i < channel->length; i++)
 431                         channel->orig_arr[i] = channel->reserve_arr[i];
 432         }
 433
 434         switch (channel->type) {
 435         case VXGE_HW_CHANNEL_TYPE_FIFO:
 436                 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
 437                 channel->stats = &((struct __vxge_hw_fifo *)
 438                                 channel)->stats->common_stats;
 439                 break;
 440         case VXGE_HW_CHANNEL_TYPE_RING:
 441                 vpath->ringh = (struct __vxge_hw_ring *)channel;
 442                 channel->stats = &((struct __vxge_hw_ring *)
 443                                 channel)->stats->common_stats;
 444                 break;
 445         default:
 446                 break;
 447         }
 448
 449         return VXGE_HW_OK;
 450 }
 451
 452 /*
 453  * __vxge_hw_channel_reset - Resets a channel
 454  * This function resets a channel by properly setting the various references
 455  */
 456 static enum vxge_hw_status
 457 __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
 458 {
 459         u32 i;
 460
 461         for (i = 0; i < channel->length; i++) {
 462                 if (channel->reserve_arr != NULL)
 463                         channel->reserve_arr[i] = channel->orig_arr[i];
 464                 if (channel->free_arr != NULL)
 465                         channel->free_arr[i] = NULL;
 466                 if (channel->work_arr != NULL)
 467                         channel->work_arr[i] = NULL;
 468         }
 469         channel->free_ptr = channel->length;
 470         channel->reserve_ptr = channel->length;
 471         channel->reserve_top = 0;
 472         channel->post_index = 0;
 473         channel->compl_index = 0;
 474
 475         return VXGE_HW_OK;
 476 }
 477
 478 /*
 479  * __vxge_hw_device_pci_e_init
 480  * Initialize certain PCI/PCI-X configuration registers
 481  * with recommended values. Save config space for future hw resets.
 482  */
 483 static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
 484 {
 485         u16 cmd = 0;
 486
 487         /* Set the PErr Repconse bit and SERR in PCI command register. */
 488         pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
 489         cmd |= 0x140;
 490         pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
 491
 492         pci_save_state(hldev->pdev);
 493 }
 494
 495 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
 496  * in progress
 497  * This routine checks the vpath reset in progress register is turned zero
 498  */
 499 static enum vxge_hw_status
 500 __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
 501 {
 502         enum vxge_hw_status status;
 503         status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
 504                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
 505                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 506         return status;
 507 }
 508
 509 /*
 510  * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
 511  * Set the swapper bits appropriately for the lagacy section.
 512  */
 513 static enum vxge_hw_status
 514 __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
 515 {
 516         u64 val64;
 517         enum vxge_hw_status status = VXGE_HW_OK;
 518
 519         val64 = readq(&legacy_reg->toc_swapper_fb);
 520
 521         wmb();
 522
 523         switch (val64) {
 524         case VXGE_HW_SWAPPER_INITIAL_VALUE:
 525                 return status;
 526
 527         case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
 528                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
 529                         &legacy_reg->pifm_rd_swap_en);
 530                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
 531                         &legacy_reg->pifm_rd_flip_en);
 532                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
 533                         &legacy_reg->pifm_wr_swap_en);
 534                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
 535                         &legacy_reg->pifm_wr_flip_en);
 536                 break;
 537
 538         case VXGE_HW_SWAPPER_BYTE_SWAPPED:
 539                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
 540                         &legacy_reg->pifm_rd_swap_en);
 541                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
 542                         &legacy_reg->pifm_wr_swap_en);
 543                 break;
 544
 545         case VXGE_HW_SWAPPER_BIT_FLIPPED:
 546                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
 547                         &legacy_reg->pifm_rd_flip_en);
 548                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
 549                         &legacy_reg->pifm_wr_flip_en);
 550                 break;
 551         }
 552
 553         wmb();
 554
 555         val64 = readq(&legacy_reg->toc_swapper_fb);
 556
 557         if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
 558                 status = VXGE_HW_ERR_SWAPPER_CTRL;
 559
 560         return status;
 561 }
 562
 563 /*
 564  * __vxge_hw_device_toc_get
 565  * This routine sets the swapper and reads the toc pointer and returns the
 566  * memory mapped address of the toc
 567  */
 568 static struct vxge_hw_toc_reg __iomem *
 569 __vxge_hw_device_toc_get(void __iomem *bar0)
 570 {
 571         u64 val64;
 572         struct vxge_hw_toc_reg __iomem *toc = NULL;
 573         enum vxge_hw_status status;
 574
 575         struct vxge_hw_legacy_reg __iomem *legacy_reg =
 576                 (struct vxge_hw_legacy_reg __iomem *)bar0;
 577
 578         status = __vxge_hw_legacy_swapper_set(legacy_reg);
 579         if (status != VXGE_HW_OK)
 580                 goto exit;
 581
 582         val64 = readq(&legacy_reg->toc_first_pointer);
 583         toc = bar0 + val64;
 584 exit:
 585         return toc;
 586 }
 587
 588 /*
 589  * __vxge_hw_device_reg_addr_get
 590  * This routine sets the swapper and reads the toc pointer and initializes the
 591  * register location pointers in the device object. It waits until the ric is
 592  * completed initializing registers.
 593  */
 594 static enum vxge_hw_status
 595 __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
 596 {
 597         u64 val64;
 598         u32 i;
 599         enum vxge_hw_status status = VXGE_HW_OK;
 600
 601         hldev->legacy_reg = hldev->bar0;
 602
 603         hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
 604         if (hldev->toc_reg  == NULL) {
 605                 status = VXGE_HW_FAIL;
 606                 goto exit;
 607         }
 608
 609         val64 = readq(&hldev->toc_reg->toc_common_pointer);
 610         hldev->common_reg = hldev->bar0 + val64;
 611
 612         val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
 613         hldev->mrpcim_reg = hldev->bar0 + val64;
 614
 615         for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
 616                 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
 617                 hldev->srpcim_reg[i] = hldev->bar0 + val64;
 618         }
 619
 620         for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
 621                 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
 622                 hldev->vpmgmt_reg[i] = hldev->bar0 + val64;
 623         }
 624
 625         for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
 626                 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
 627                 hldev->vpath_reg[i] = hldev->bar0 + val64;
 628         }
 629
 630         val64 = readq(&hldev->toc_reg->toc_kdfc);
 631
 632         switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
 633         case 0:
 634                 hldev->kdfc = hldev->bar0 + VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64) ;
 635                 break;
 636         default:
 637                 break;
 638         }
 639
 640         status = __vxge_hw_device_vpath_reset_in_prog_check(
 641                         (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
 642 exit:
 643         return status;
 644 }
 645
 646 /*
 647  * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
 648  * This routine returns the Access Rights of the driver
 649  */
 650 static u32
 651 __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
 652 {
 653         u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
 654
 655         switch (host_type) {
 656         case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
 657                 if (func_id == 0) {
 658                         access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 659                                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 660                 }
 661                 break;
 662         case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
 663                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 664                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 665                 break;
 666         case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
 667                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 668                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 669                 break;
 670         case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
 671         case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
 672         case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
 673                 break;
 674         case VXGE_HW_SR_VH_FUNCTION0:
 675         case VXGE_HW_VH_NORMAL_FUNCTION:
 676                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 677                 break;
 678         }
 679
 680         return access_rights;
 681 }
 682 /*
 683  * __vxge_hw_device_is_privilaged
 684  * This routine checks if the device function is privilaged or not
 685  */
 686
 687 enum vxge_hw_status
 688 __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
 689 {
 690         if (__vxge_hw_device_access_rights_get(host_type,
 691                 func_id) &
 692                 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
 693                 return VXGE_HW_OK;
 694         else
 695                 return VXGE_HW_ERR_PRIVILEGED_OPERATION;
 696 }
 697
 698 /*
 699  * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
 700  * Returns the function number of the vpath.
 701  */
 702 static u32
 703 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
 704 {
 705         u64 val64;
 706
 707         val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
 708
 709         return
 710          (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
 711 }
 712
 713 /*
 714  * __vxge_hw_device_host_info_get
 715  * This routine returns the host type assignments
 716  */
 717 static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
 718 {
 719         u64 val64;
 720         u32 i;
 721
 722         val64 = readq(&hldev->common_reg->host_type_assignments);
 723
 724         hldev->host_type =
 725            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
 726
 727         hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
 728
 729         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 730                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
 731                         continue;
 732
 733                 hldev->func_id =
 734                         __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
 735
 736                 hldev->access_rights = __vxge_hw_device_access_rights_get(
 737                         hldev->host_type, hldev->func_id);
 738
 739                 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
 740                 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
 741
 742                 hldev->first_vp_id = i;
 743                 break;
 744         }
 745 }
 746
 747 /*
 748  * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
 749  * link width and signalling rate.
 750  */
 751 static enum vxge_hw_status
 752 __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
 753 {
 754         struct pci_dev *dev = hldev->pdev;
 755         u16 lnk;
 756
 757         /* Get the negotiated link width and speed from PCI config space */
 758         pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
 759
 760         if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
 761                 return VXGE_HW_ERR_INVALID_PCI_INFO;
 762
 763         switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
 764         case PCIE_LNK_WIDTH_RESRV:
 765         case PCIE_LNK_X1:
 766         case PCIE_LNK_X2:
 767         case PCIE_LNK_X4:
 768         case PCIE_LNK_X8:
 769                 break;
 770         default:
 771                 return VXGE_HW_ERR_INVALID_PCI_INFO;
 772         }
 773
 774         return VXGE_HW_OK;
 775 }
 776
 777 /*
 778  * __vxge_hw_device_initialize
 779  * Initialize Titan-V hardware.
 780  */
 781 static enum vxge_hw_status
 782 __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
 783 {
 784         enum vxge_hw_status status = VXGE_HW_OK;
 785
 786         if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
 787                                 hldev->func_id)) {
 788                 /* Validate the pci-e link width and speed */
 789                 status = __vxge_hw_verify_pci_e_info(hldev);
 790                 if (status != VXGE_HW_OK)
 791                         goto exit;
 792         }
 793
 794 exit:
 795         return status;
 796 }
 797
 798 /*
 799  * __vxge_hw_vpath_fw_ver_get - Get the fw version
 800  * Returns FW Version
 801  */
 802 static enum vxge_hw_status
 803 __vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
 804                            struct vxge_hw_device_hw_info *hw_info)
 805 {
 806         struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
 807         struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
 808         struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
 809         struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
 810         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 811         enum vxge_hw_status status;
 812
 813         status = vxge_hw_vpath_fw_api(vpath,
 814                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
 815                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 816                         0, &data0, &data1, &steer_ctrl);
 817         if (status != VXGE_HW_OK)
 818                 goto exit;
 819
 820         fw_date->day =
 821             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
 822         fw_date->month =
 823             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
 824         fw_date->year =
 825             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
 826
 827         snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
 828                  fw_date->month, fw_date->day, fw_date->year);
 829
 830         fw_version->major =
 831             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
 832         fw_version->minor =
 833             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
 834         fw_version->build =
 835             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
 836
 837         snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
 838                  fw_version->major, fw_version->minor, fw_version->build);
 839
 840         flash_date->day =
 841             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
 842         flash_date->month =
 843             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
 844         flash_date->year =
 845             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
 846
 847         snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
 848                  flash_date->month, flash_date->day, flash_date->year);
 849
 850         flash_version->major =
 851             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
 852         flash_version->minor =
 853             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
 854         flash_version->build =
 855             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
 856
 857         snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
 858                  flash_version->major, flash_version->minor,
 859                  flash_version->build);
 860
 861 exit:
 862         return status;
 863 }
 864
 865 /*
 866  * __vxge_hw_vpath_card_info_get - Get the serial numbers,
 867  * part number and product description.
 868  */
 869 static enum vxge_hw_status
 870 __vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
 871                               struct vxge_hw_device_hw_info *hw_info)
 872 {
 873         enum vxge_hw_status status;
 874         u64 data0, data1 = 0, steer_ctrl = 0;
 875         u8 *serial_number = hw_info->serial_number;
 876         u8 *part_number = hw_info->part_number;
 877         u8 *product_desc = hw_info->product_desc;
 878         u32 i, j = 0;
 879
 880         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
 881
 882         status = vxge_hw_vpath_fw_api(vpath,
 883                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 884                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 885                         0, &data0, &data1, &steer_ctrl);
 886         if (status != VXGE_HW_OK)
 887                 return status;
 888
 889         ((u64 *)serial_number)[0] = be64_to_cpu(data0);
 890         ((u64 *)serial_number)[1] = be64_to_cpu(data1);
 891
 892         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
 893         data1 = steer_ctrl = 0;
 894
 895         status = vxge_hw_vpath_fw_api(vpath,
 896                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 897                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 898                         0, &data0, &data1, &steer_ctrl);
 899         if (status != VXGE_HW_OK)
 900                 return status;
 901
 902         ((u64 *)part_number)[0] = be64_to_cpu(data0);
 903         ((u64 *)part_number)[1] = be64_to_cpu(data1);
 904
 905         for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
 906              i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
 907                 data0 = i;
 908                 data1 = steer_ctrl = 0;
 909
 910                 status = vxge_hw_vpath_fw_api(vpath,
 911                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 912                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 913                         0, &data0, &data1, &steer_ctrl);
 914                 if (status != VXGE_HW_OK)
 915                         return status;
 916
 917                 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
 918                 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
 919         }
 920
 921         return status;
 922 }
 923
 924 /*
 925  * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
 926  * Returns pci function mode
 927  */
 928 static enum vxge_hw_status
 929 __vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
 930                                   struct vxge_hw_device_hw_info *hw_info)
 931 {
 932         u64 data0, data1 = 0, steer_ctrl = 0;
 933         enum vxge_hw_status status;
 934
 935         data0 = 0;
 936
 937         status = vxge_hw_vpath_fw_api(vpath,
 938                         VXGE_HW_FW_API_GET_FUNC_MODE,
 939                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 940                         0, &data0, &data1, &steer_ctrl);
 941         if (status != VXGE_HW_OK)
 942                 return status;
 943
 944         hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
 945         return status;
 946 }
 947
 948 /*
 949  * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
 950  *               from MAC address table.
 951  */
 952 static enum vxge_hw_status
 953 __vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
 954                          u8 *macaddr, u8 *macaddr_mask)
 955 {
 956         u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
 957             data0 = 0, data1 = 0, steer_ctrl = 0;
 958         enum vxge_hw_status status;
 959         int i;
 960
 961         do {
 962                 status = vxge_hw_vpath_fw_api(vpath, action,
 963                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
 964                         0, &data0, &data1, &steer_ctrl);
 965                 if (status != VXGE_HW_OK)
 966                         goto exit;
 967
 968                 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
 969                 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
 970                                                                         data1);
 971
 972                 for (i = ETH_ALEN; i > 0; i--) {
 973                         macaddr[i - 1] = (u8) (data0 & 0xFF);
 974                         data0 >>= 8;
 975
 976                         macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
 977                         data1 >>= 8;
 978                 }
 979
 980                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
 981                 data0 = 0, data1 = 0, steer_ctrl = 0;
 982
 983         } while (!is_valid_ether_addr(macaddr));
 984 exit:
 985         return status;
 986 }
 987
 988 /**
 989  * vxge_hw_device_hw_info_get - Get the hw information
 990  * Returns the vpath mask that has the bits set for each vpath allocated
 991  * for the driver, FW version information, and the first mac address for
 992  * each vpath
 993  */
 994 enum vxge_hw_status
 995 vxge_hw_device_hw_info_get(void __iomem *bar0,
 996                            struct vxge_hw_device_hw_info *hw_info)
 997 {
 998         u32 i;
 999         u64 val64;
1000         struct vxge_hw_toc_reg __iomem *toc;
1001         struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1002         struct vxge_hw_common_reg __iomem *common_reg;
1003         struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1004         enum vxge_hw_status status;
1005         struct __vxge_hw_virtualpath vpath;
1006
1007         memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1008
1009         toc = __vxge_hw_device_toc_get(bar0);
1010         if (toc == NULL) {
1011                 status = VXGE_HW_ERR_CRITICAL;
1012                 goto exit;
1013         }
1014
1015         val64 = readq(&toc->toc_common_pointer);
1016         common_reg = bar0 + val64;
1017
1018         status = __vxge_hw_device_vpath_reset_in_prog_check(
1019                 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1020         if (status != VXGE_HW_OK)
1021                 goto exit;
1022
1023         hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1024
1025         val64 = readq(&common_reg->host_type_assignments);
1026
1027         hw_info->host_type =
1028            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1029
1030         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1031                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1032                         continue;
1033
1034                 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1035
1036                 vpmgmt_reg = bar0 + val64;
1037
1038                 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
1039                 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1040                         hw_info->func_id) &
1041                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1042
1043                         val64 = readq(&toc->toc_mrpcim_pointer);
1044
1045                         mrpcim_reg = bar0 + val64;
1046
1047                         writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1048                         wmb();
1049                 }
1050
1051                 val64 = readq(&toc->toc_vpath_pointer[i]);
1052
1053                 spin_lock_init(&vpath.lock);
1054                 vpath.vp_reg = bar0 + val64;
1055                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1056
1057                 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1058                 if (status != VXGE_HW_OK)
1059                         goto exit;
1060
1061                 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
1062                 if (status != VXGE_HW_OK)
1063                         goto exit;
1064
1065                 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
1066                 if (status != VXGE_HW_OK)
1067                         goto exit;
1068
1069                 break;
1070         }
1071
1072         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1073                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1074                         continue;
1075
1076                 val64 = readq(&toc->toc_vpath_pointer[i]);
1077                 vpath.vp_reg = bar0 + val64;
1078                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1079
1080                 status =  __vxge_hw_vpath_addr_get(&vpath,
1081                                 hw_info->mac_addrs[i],
1082                                 hw_info->mac_addr_masks[i]);
1083                 if (status != VXGE_HW_OK)
1084                         goto exit;
1085         }
1086 exit:
1087         return status;
1088 }
1089
1090 /*
1091  * __vxge_hw_blockpool_destroy - Deallocates the block pool
1092  */
1093 static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
1094 {
1095         struct __vxge_hw_device *hldev;
1096         struct list_head *p, *n;
1097
1098         if (!blockpool)
1099                 return;
1100
1101         hldev = blockpool->hldev;
1102
1103         list_for_each_safe(p, n, &blockpool->free_block_list) {
1104                 pci_unmap_single(hldev->pdev,
1105                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
1106                         ((struct __vxge_hw_blockpool_entry *)p)->length,
1107                         PCI_DMA_BIDIRECTIONAL);
1108
1109                 vxge_os_dma_free(hldev->pdev,
1110                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
1111                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
1112
1113                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1114                 kfree(p);
1115                 blockpool->pool_size--;
1116         }
1117
1118         list_for_each_safe(p, n, &blockpool->free_entry_list) {
1119                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1120                 kfree((void *)p);
1121         }
1122
1123         return;
1124 }
1125
1126 /*
1127  * __vxge_hw_blockpool_create - Create block pool
1128  */
1129 static enum vxge_hw_status
1130 __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1131                            struct __vxge_hw_blockpool *blockpool,
1132                            u32 pool_size,
1133                            u32 pool_max)
1134 {
1135         u32 i;
1136         struct __vxge_hw_blockpool_entry *entry = NULL;
1137         void *memblock;
1138         dma_addr_t dma_addr;
1139         struct pci_dev *dma_handle;
1140         struct pci_dev *acc_handle;
1141         enum vxge_hw_status status = VXGE_HW_OK;
1142
1143         if (blockpool == NULL) {
1144                 status = VXGE_HW_FAIL;
1145                 goto blockpool_create_exit;
1146         }
1147
1148         blockpool->hldev = hldev;
1149         blockpool->block_size = VXGE_HW_BLOCK_SIZE;
1150         blockpool->pool_size = 0;
1151         blockpool->pool_max = pool_max;
1152         blockpool->req_out = 0;
1153
1154         INIT_LIST_HEAD(&blockpool->free_block_list);
1155         INIT_LIST_HEAD(&blockpool->free_entry_list);
1156
1157         for (i = 0; i < pool_size + pool_max; i++) {
1158                 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1159                                 GFP_KERNEL);
1160                 if (entry == NULL) {
1161                         __vxge_hw_blockpool_destroy(blockpool);
1162                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1163                         goto blockpool_create_exit;
1164                 }
1165                 list_add(&entry->item, &blockpool->free_entry_list);
1166         }
1167
1168         for (i = 0; i < pool_size; i++) {
1169                 memblock = vxge_os_dma_malloc(
1170                                 hldev->pdev,
1171                                 VXGE_HW_BLOCK_SIZE,
1172                                 &dma_handle,
1173                                 &acc_handle);
1174                 if (memblock == NULL) {
1175                         __vxge_hw_blockpool_destroy(blockpool);
1176                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1177                         goto blockpool_create_exit;
1178                 }
1179
1180                 dma_addr = pci_map_single(hldev->pdev, memblock,
1181                                 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
1182                 if (unlikely(pci_dma_mapping_error(hldev->pdev,
1183                                 dma_addr))) {
1184                         vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
1185                         __vxge_hw_blockpool_destroy(blockpool);
1186                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1187                         goto blockpool_create_exit;
1188                 }
1189
1190                 if (!list_empty(&blockpool->free_entry_list))
1191                         entry = (struct __vxge_hw_blockpool_entry *)
1192                                 list_first_entry(&blockpool->free_entry_list,
1193                                         struct __vxge_hw_blockpool_entry,
1194                                         item);
1195
1196                 if (entry == NULL)
1197                         entry =
1198                             kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1199                                         GFP_KERNEL);
1200                 if (entry != NULL) {
1201                         list_del(&entry->item);
1202                         entry->length = VXGE_HW_BLOCK_SIZE;
1203                         entry->memblock = memblock;
1204                         entry->dma_addr = dma_addr;
1205                         entry->acc_handle = acc_handle;
1206                         entry->dma_handle = dma_handle;
1207                         list_add(&entry->item,
1208                                           &blockpool->free_block_list);
1209                         blockpool->pool_size++;
1210                 } else {
1211                         __vxge_hw_blockpool_destroy(blockpool);
1212                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1213                         goto blockpool_create_exit;
1214                 }
1215         }
1216
1217 blockpool_create_exit:
1218         return status;
1219 }
1220
1221 /*
1222  * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1223  * Check the fifo configuration
1224  */
1225 static enum vxge_hw_status
1226 __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1227 {
1228         if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1229             (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1230                 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1231
1232         return VXGE_HW_OK;
1233 }
1234
1235 /*
1236  * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1237  * Check the vpath configuration
1238  */
1239 static enum vxge_hw_status
1240 __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1241 {
1242         enum vxge_hw_status status;
1243
1244         if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1245             (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
1246                 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1247
1248         status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1249         if (status != VXGE_HW_OK)
1250                 return status;
1251
1252         if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1253                 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1254                 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1255                 return VXGE_HW_BADCFG_VPATH_MTU;
1256
1257         if ((vp_config->rpa_strip_vlan_tag !=
1258                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1259                 (vp_config->rpa_strip_vlan_tag !=
1260                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1261                 (vp_config->rpa_strip_vlan_tag !=
1262                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1263                 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1264
1265         return VXGE_HW_OK;
1266 }
1267
1268 /*
1269  * __vxge_hw_device_config_check - Check device configuration.
1270  * Check the device configuration
1271  */
1272 static enum vxge_hw_status
1273 __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1274 {
1275         u32 i;
1276         enum vxge_hw_status status;
1277
1278         if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1279             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1280             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1281             (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1282                 return VXGE_HW_BADCFG_INTR_MODE;
1283
1284         if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1285             (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1286                 return VXGE_HW_BADCFG_RTS_MAC_EN;
1287
1288         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1289                 status = __vxge_hw_device_vpath_config_check(
1290                                 &new_config->vp_config[i]);
1291                 if (status != VXGE_HW_OK)
1292                         return status;
1293         }
1294
1295         return VXGE_HW_OK;
1296 }
1297
1298 /*
1299  * vxge_hw_device_initialize - Initialize Titan device.
1300  * Initialize Titan device. Note that all the arguments of this public API
1301  * are 'IN', including @hldev. Driver cooperates with
1302  * OS to find new Titan device, locate its PCI and memory spaces.
1303  *
1304  * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1305  * to enable the latter to perform Titan hardware initialization.
1306  */
1307 enum vxge_hw_status
1308 vxge_hw_device_initialize(
1309         struct __vxge_hw_device **devh,
1310         struct vxge_hw_device_attr *attr,
1311         struct vxge_hw_device_config *device_config)
1312 {
1313         u32 i;
1314         u32 nblocks = 0;
1315         struct __vxge_hw_device *hldev = NULL;
1316         enum vxge_hw_status status = VXGE_HW_OK;
1317
1318         status = __vxge_hw_device_config_check(device_config);
1319         if (status != VXGE_HW_OK)
1320                 goto exit;
1321
1322         hldev = vzalloc(sizeof(struct __vxge_hw_device));
1323         if (hldev == NULL) {
1324                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1325                 goto exit;
1326         }
1327
1328         hldev->magic = VXGE_HW_DEVICE_MAGIC;
1329
1330         vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1331
1332         /* apply config */
1333         memcpy(&hldev->config, device_config,
1334                 sizeof(struct vxge_hw_device_config));
1335
1336         hldev->bar0 = attr->bar0;
1337         hldev->pdev = attr->pdev;
1338
1339         hldev->uld_callbacks = attr->uld_callbacks;
1340
1341         __vxge_hw_device_pci_e_init(hldev);
1342
1343         status = __vxge_hw_device_reg_addr_get(hldev);
1344         if (status != VXGE_HW_OK) {
1345                 vfree(hldev);
1346                 goto exit;
1347         }
1348
1349         __vxge_hw_device_host_info_get(hldev);
1350
1351         /* Incrementing for stats blocks */
1352         nblocks++;
1353
1354         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1355                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1356                         continue;
1357
1358                 if (device_config->vp_config[i].ring.enable ==
1359                         VXGE_HW_RING_ENABLE)
1360                         nblocks += device_config->vp_config[i].ring.ring_blocks;
1361
1362                 if (device_config->vp_config[i].fifo.enable ==
1363                         VXGE_HW_FIFO_ENABLE)
1364                         nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1365                 nblocks++;
1366         }
1367
1368         if (__vxge_hw_blockpool_create(hldev,
1369                 &hldev->block_pool,
1370                 device_config->dma_blockpool_initial + nblocks,
1371                 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1372
1373                 vxge_hw_device_terminate(hldev);
1374                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1375                 goto exit;
1376         }
1377
1378         status = __vxge_hw_device_initialize(hldev);
1379         if (status != VXGE_HW_OK) {
1380                 vxge_hw_device_terminate(hldev);
1381                 goto exit;
1382         }
1383
1384         *devh = hldev;
1385 exit:
1386         return status;
1387 }
1388
1389 /*
1390  * vxge_hw_device_terminate - Terminate Titan device.
1391  * Terminate HW device.
1392  */
1393 void
1394 vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1395 {
1396         vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1397
1398         hldev->magic = VXGE_HW_DEVICE_DEAD;
1399         __vxge_hw_blockpool_destroy(&hldev->block_pool);
1400         vfree(hldev);
1401 }
1402
1403 /*
1404  * __vxge_hw_vpath_stats_access - Get the statistics from the given location
1405  *                           and offset and perform an operation
1406  */
1407 static enum vxge_hw_status
1408 __vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
1409                              u32 operation, u32 offset, u64 *stat)
1410 {
1411         u64 val64;
1412         enum vxge_hw_status status = VXGE_HW_OK;
1413         struct vxge_hw_vpath_reg __iomem *vp_reg;
1414
1415         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1416                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1417                 goto vpath_stats_access_exit;
1418         }
1419
1420         vp_reg = vpath->vp_reg;
1421
1422         val64 =  VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
1423                  VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
1424                  VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
1425
1426         status = __vxge_hw_pio_mem_write64(val64,
1427                                 &vp_reg->xmac_stats_access_cmd,
1428                                 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
1429                                 vpath->hldev->config.device_poll_millis);
1430         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1431                 *stat = readq(&vp_reg->xmac_stats_access_data);
1432         else
1433                 *stat = 0;
1434
1435 vpath_stats_access_exit:
1436         return status;
1437 }
1438
1439 /*
1440  * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
1441  */
1442 static enum vxge_hw_status
1443 __vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
1444                         struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
1445 {
1446         u64 *val64;
1447         int i;
1448         u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
1449         enum vxge_hw_status status = VXGE_HW_OK;
1450
1451         val64 = (u64 *)vpath_tx_stats;
1452
1453         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1454                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1455                 goto exit;
1456         }
1457
1458         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
1459                 status = __vxge_hw_vpath_stats_access(vpath,
1460                                         VXGE_HW_STATS_OP_READ,
1461                                         offset, val64);
1462                 if (status != VXGE_HW_OK)
1463                         goto exit;
1464                 offset++;
1465                 val64++;
1466         }
1467 exit:
1468         return status;
1469 }
1470
1471 /*
1472  * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
1473  */
1474 static enum vxge_hw_status
1475 __vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
1476                         struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
1477 {
1478         u64 *val64;
1479         enum vxge_hw_status status = VXGE_HW_OK;
1480         int i;
1481         u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
1482         val64 = (u64 *) vpath_rx_stats;
1483
1484         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1485                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1486                 goto exit;
1487         }
1488         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
1489                 status = __vxge_hw_vpath_stats_access(vpath,
1490                                         VXGE_HW_STATS_OP_READ,
1491                                         offset >> 3, val64);
1492                 if (status != VXGE_HW_OK)
1493                         goto exit;
1494
1495                 offset += 8;
1496                 val64++;
1497         }
1498 exit:
1499         return status;
1500 }
1501
1502 /*
1503  * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
1504  */
1505 static enum vxge_hw_status
1506 __vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
1507                           struct vxge_hw_vpath_stats_hw_info *hw_stats)
1508 {
1509         u64 val64;
1510         enum vxge_hw_status status = VXGE_HW_OK;
1511         struct vxge_hw_vpath_reg __iomem *vp_reg;
1512
1513         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1514                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1515                 goto exit;
1516         }
1517         vp_reg = vpath->vp_reg;
1518
1519         val64 = readq(&vp_reg->vpath_debug_stats0);
1520         hw_stats->ini_num_mwr_sent =
1521                 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
1522
1523         val64 = readq(&vp_reg->vpath_debug_stats1);
1524         hw_stats->ini_num_mrd_sent =
1525                 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
1526
1527         val64 = readq(&vp_reg->vpath_debug_stats2);
1528         hw_stats->ini_num_cpl_rcvd =
1529                 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
1530
1531         val64 = readq(&vp_reg->vpath_debug_stats3);
1532         hw_stats->ini_num_mwr_byte_sent =
1533                 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
1534
1535         val64 = readq(&vp_reg->vpath_debug_stats4);
1536         hw_stats->ini_num_cpl_byte_rcvd =
1537                 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
1538
1539         val64 = readq(&vp_reg->vpath_debug_stats5);
1540         hw_stats->wrcrdtarb_xoff =
1541                 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
1542
1543         val64 = readq(&vp_reg->vpath_debug_stats6);
1544         hw_stats->rdcrdtarb_xoff =
1545                 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
1546
1547         val64 = readq(&vp_reg->vpath_genstats_count01);
1548         hw_stats->vpath_genstats_count0 =
1549         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
1550                 val64);
1551
1552         val64 = readq(&vp_reg->vpath_genstats_count01);
1553         hw_stats->vpath_genstats_count1 =
1554         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
1555                 val64);
1556
1557         val64 = readq(&vp_reg->vpath_genstats_count23);
1558         hw_stats->vpath_genstats_count2 =
1559         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
1560                 val64);
1561
1562         val64 = readq(&vp_reg->vpath_genstats_count01);
1563         hw_stats->vpath_genstats_count3 =
1564         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
1565                 val64);
1566
1567         val64 = readq(&vp_reg->vpath_genstats_count4);
1568         hw_stats->vpath_genstats_count4 =
1569         (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
1570                 val64);
1571
1572         val64 = readq(&vp_reg->vpath_genstats_count5);
1573         hw_stats->vpath_genstats_count5 =
1574         (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
1575                 val64);
1576
1577         status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
1578         if (status != VXGE_HW_OK)
1579                 goto exit;
1580
1581         status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
1582         if (status != VXGE_HW_OK)
1583                 goto exit;
1584
1585         VXGE_HW_VPATH_STATS_PIO_READ(
1586                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
1587
1588         hw_stats->prog_event_vnum0 =
1589                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
1590
1591         hw_stats->prog_event_vnum1 =
1592                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
1593
1594         VXGE_HW_VPATH_STATS_PIO_READ(
1595                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
1596
1597         hw_stats->prog_event_vnum2 =
1598                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
1599
1600         hw_stats->prog_event_vnum3 =
1601                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
1602
1603         val64 = readq(&vp_reg->rx_multi_cast_stats);
1604         hw_stats->rx_multi_cast_frame_discard =
1605                 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
1606
1607         val64 = readq(&vp_reg->rx_frm_transferred);
1608         hw_stats->rx_frm_transferred =
1609                 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
1610
1611         val64 = readq(&vp_reg->rxd_returned);
1612         hw_stats->rxd_returned =
1613                 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
1614
1615         val64 = readq(&vp_reg->dbg_stats_rx_mpa);
1616         hw_stats->rx_mpa_len_fail_frms =
1617                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
1618         hw_stats->rx_mpa_mrk_fail_frms =
1619                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
1620         hw_stats->rx_mpa_crc_fail_frms =
1621                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
1622
1623         val64 = readq(&vp_reg->dbg_stats_rx_fau);
1624         hw_stats->rx_permitted_frms =
1625                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
1626         hw_stats->rx_vp_reset_discarded_frms =
1627         (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
1628         hw_stats->rx_wol_frms =
1629                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
1630
1631         val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
1632         hw_stats->tx_vp_reset_discarded_frms =
1633         (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
1634                 val64);
1635 exit:
1636         return status;
1637 }
1638
1639 /*
1640  * vxge_hw_device_stats_get - Get the device hw statistics.
1641  * Returns the vpath h/w stats for the device.
1642  */
1643 enum vxge_hw_status
1644 vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1645                         struct vxge_hw_device_stats_hw_info *hw_stats)
1646 {
1647         u32 i;
1648         enum vxge_hw_status status = VXGE_HW_OK;
1649
1650         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1651                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1652                         (hldev->virtual_paths[i].vp_open ==
1653                                 VXGE_HW_VP_NOT_OPEN))
1654                         continue;
1655
1656                 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1657                                 hldev->virtual_paths[i].hw_stats,
1658                                 sizeof(struct vxge_hw_vpath_stats_hw_info));
1659
1660                 status = __vxge_hw_vpath_stats_get(
1661                         &hldev->virtual_paths[i],
1662                         hldev->virtual_paths[i].hw_stats);
1663         }
1664
1665         memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1666                         sizeof(struct vxge_hw_device_stats_hw_info));
1667
1668         return status;
1669 }
1670
1671 /*
1672  * vxge_hw_driver_stats_get - Get the device sw statistics.
1673  * Returns the vpath s/w stats for the device.
1674  */
1675 enum vxge_hw_status vxge_hw_driver_stats_get(
1676                         struct __vxge_hw_device *hldev,
1677                         struct vxge_hw_device_stats_sw_info *sw_stats)
1678 {
1679         memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1680                 sizeof(struct vxge_hw_device_stats_sw_info));
1681
1682         return VXGE_HW_OK;
1683 }
1684
1685 /*
1686  * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1687  *                           and offset and perform an operation
1688  * Get the statistics from the given location and offset.
1689  */
1690 enum vxge_hw_status
1691 vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1692                             u32 operation, u32 location, u32 offset, u64 *stat)
1693 {
1694         u64 val64;
1695         enum vxge_hw_status status = VXGE_HW_OK;
1696
1697         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1698                         hldev->func_id);
1699         if (status != VXGE_HW_OK)
1700                 goto exit;
1701
1702         val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1703                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1704                 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1705                 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1706
1707         status = __vxge_hw_pio_mem_write64(val64,
1708                                 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1709                                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1710                                 hldev->config.device_poll_millis);
1711
1712         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1713                 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1714         else
1715                 *stat = 0;
1716 exit:
1717         return status;
1718 }
1719
1720 /*
1721  * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1722  * Get the Statistics on aggregate port
1723  */
1724 static enum vxge_hw_status
1725 vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1726                                    struct vxge_hw_xmac_aggr_stats *aggr_stats)
1727 {
1728         u64 *val64;
1729         int i;
1730         u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1731         enum vxge_hw_status status = VXGE_HW_OK;
1732
1733         val64 = (u64 *)aggr_stats;
1734
1735         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1736                         hldev->func_id);
1737         if (status != VXGE_HW_OK)
1738                 goto exit;
1739
1740         for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1741                 status = vxge_hw_mrpcim_stats_access(hldev,
1742                                         VXGE_HW_STATS_OP_READ,
1743                                         VXGE_HW_STATS_LOC_AGGR,
1744                                         ((offset + (104 * port)) >> 3), val64);
1745                 if (status != VXGE_HW_OK)
1746                         goto exit;
1747
1748                 offset += 8;
1749                 val64++;
1750         }
1751 exit:
1752         return status;
1753 }
1754
1755 /*
1756  * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1757  * Get the Statistics on port
1758  */
1759 static enum vxge_hw_status
1760 vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1761                                    struct vxge_hw_xmac_port_stats *port_stats)
1762 {
1763         u64 *val64;
1764         enum vxge_hw_status status = VXGE_HW_OK;
1765         int i;
1766         u32 offset = 0x0;
1767         val64 = (u64 *) port_stats;
1768
1769         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1770                         hldev->func_id);
1771         if (status != VXGE_HW_OK)
1772                 goto exit;
1773
1774         for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1775                 status = vxge_hw_mrpcim_stats_access(hldev,
1776                                         VXGE_HW_STATS_OP_READ,
1777                                         VXGE_HW_STATS_LOC_AGGR,
1778                                         ((offset + (608 * port)) >> 3), val64);
1779                 if (status != VXGE_HW_OK)
1780                         goto exit;
1781
1782                 offset += 8;
1783                 val64++;
1784         }
1785
1786 exit:
1787         return status;
1788 }
1789
1790 /*
1791  * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1792  * Get the XMAC Statistics
1793  */
1794 enum vxge_hw_status
1795 vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1796                               struct vxge_hw_xmac_stats *xmac_stats)
1797 {
1798         enum vxge_hw_status status = VXGE_HW_OK;
1799         u32 i;
1800
1801         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1802                                         0, &xmac_stats->aggr_stats[0]);
1803         if (status != VXGE_HW_OK)
1804                 goto exit;
1805
1806         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1807                                 1, &xmac_stats->aggr_stats[1]);
1808         if (status != VXGE_HW_OK)
1809                 goto exit;
1810
1811         for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1812
1813                 status = vxge_hw_device_xmac_port_stats_get(hldev,
1814                                         i, &xmac_stats->port_stats[i]);
1815                 if (status != VXGE_HW_OK)
1816                         goto exit;
1817         }
1818
1819         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1820
1821                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1822                         continue;
1823
1824                 status = __vxge_hw_vpath_xmac_tx_stats_get(
1825                                         &hldev->virtual_paths[i],
1826                                         &xmac_stats->vpath_tx_stats[i]);
1827                 if (status != VXGE_HW_OK)
1828                         goto exit;
1829
1830                 status = __vxge_hw_vpath_xmac_rx_stats_get(
1831                                         &hldev->virtual_paths[i],
1832                                         &xmac_stats->vpath_rx_stats[i]);
1833                 if (status != VXGE_HW_OK)
1834                         goto exit;
1835         }
1836 exit:
1837         return status;
1838 }
1839
1840 /*
1841  * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1842  * This routine is used to dynamically change the debug output
1843  */
1844 void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1845                               enum vxge_debug_level level, u32 mask)
1846 {
1847         if (hldev == NULL)
1848                 return;
1849
1850 #if defined(VXGE_DEBUG_TRACE_MASK) || \
1851         defined(VXGE_DEBUG_ERR_MASK)
1852         hldev->debug_module_mask = mask;
1853         hldev->debug_level = level;
1854 #endif
1855
1856 #if defined(VXGE_DEBUG_ERR_MASK)
1857         hldev->level_err = level & VXGE_ERR;
1858 #endif
1859
1860 #if defined(VXGE_DEBUG_TRACE_MASK)
1861         hldev->level_trace = level & VXGE_TRACE;
1862 #endif
1863 }
1864
1865 /*
1866  * vxge_hw_device_error_level_get - Get the error level
1867  * This routine returns the current error level set
1868  */
1869 u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1870 {
1871 #if defined(VXGE_DEBUG_ERR_MASK)
1872         if (hldev == NULL)
1873                 return VXGE_ERR;
1874         else
1875                 return hldev->level_err;
1876 #else
1877         return 0;
1878 #endif
1879 }
1880
1881 /*
1882  * vxge_hw_device_trace_level_get - Get the trace level
1883  * This routine returns the current trace level set
1884  */
1885 u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1886 {
1887 #if defined(VXGE_DEBUG_TRACE_MASK)
1888         if (hldev == NULL)
1889                 return VXGE_TRACE;
1890         else
1891                 return hldev->level_trace;
1892 #else
1893         return 0;
1894 #endif
1895 }
1896
1897 /*
1898  * vxge_hw_getpause_data -Pause frame frame generation and reception.
1899  * Returns the Pause frame generation and reception capability of the NIC.
1900  */
1901 enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1902                                                  u32 port, u32 *tx, u32 *rx)
1903 {
1904         u64 val64;
1905         enum vxge_hw_status status = VXGE_HW_OK;
1906
1907         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1908                 status = VXGE_HW_ERR_INVALID_DEVICE;
1909                 goto exit;
1910         }
1911
1912         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1913                 status = VXGE_HW_ERR_INVALID_PORT;
1914                 goto exit;
1915         }
1916
1917         if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1918                 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
1919                 goto exit;
1920         }
1921
1922         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1923         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1924                 *tx = 1;
1925         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1926                 *rx = 1;
1927 exit:
1928         return status;
1929 }
1930
1931 /*
1932  * vxge_hw_device_setpause_data -  set/reset pause frame generation.
1933  * It can be used to set or reset Pause frame generation or reception
1934  * support of the NIC.
1935  */
1936 enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1937                                                  u32 port, u32 tx, u32 rx)
1938 {
1939         u64 val64;
1940         enum vxge_hw_status status = VXGE_HW_OK;
1941
1942         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1943                 status = VXGE_HW_ERR_INVALID_DEVICE;
1944                 goto exit;
1945         }
1946
1947         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1948                 status = VXGE_HW_ERR_INVALID_PORT;
1949                 goto exit;
1950         }
1951
1952         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1953                         hldev->func_id);
1954         if (status != VXGE_HW_OK)
1955                 goto exit;
1956
1957         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1958         if (tx)
1959                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1960         else
1961                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1962         if (rx)
1963                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1964         else
1965                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1966
1967         writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1968 exit:
1969         return status;
1970 }
1971
1972 u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1973 {
1974         struct pci_dev *dev = hldev->pdev;
1975         u16 lnk;
1976
1977         pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
1978         return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1979 }
1980
1981 /*
1982  * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1983  * This function returns the index of memory block
1984  */
1985 static inline u32
1986 __vxge_hw_ring_block_memblock_idx(u8 *block)
1987 {
1988         return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1989 }
1990
1991 /*
1992  * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1993  * This function sets index to a memory block
1994  */
1995 static inline void
1996 __vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
1997 {
1998         *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
1999 }
2000
2001 /*
2002  * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
2003  * in RxD block
2004  * Sets the next block pointer in RxD block
2005  */
2006 static inline void
2007 __vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
2008 {
2009         *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
2010 }
2011
2012 /*
2013  * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
2014  *             first block
2015  * Returns the dma address of the first RxD block
2016  */
2017 static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
2018 {
2019         struct vxge_hw_mempool_dma *dma_object;
2020
2021         dma_object = ring->mempool->memblocks_dma_arr;
2022         vxge_assert(dma_object != NULL);
2023
2024         return dma_object->addr;
2025 }
2026
2027 /*
2028  * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
2029  * This function returns the dma address of a given item
2030  */
2031 static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
2032                                                void *item)
2033 {
2034         u32 memblock_idx;
2035         void *memblock;
2036         struct vxge_hw_mempool_dma *memblock_dma_object;
2037         ptrdiff_t dma_item_offset;
2038
2039         /* get owner memblock index */
2040         memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
2041
2042         /* get owner memblock by memblock index */
2043         memblock = mempoolh->memblocks_arr[memblock_idx];
2044
2045         /* get memblock DMA object by memblock index */
2046         memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
2047
2048         /* calculate offset in the memblock of this item */
2049         dma_item_offset = (u8 *)item - (u8 *)memblock;
2050
2051         return memblock_dma_object->addr + dma_item_offset;
2052 }
2053
2054 /*
2055  * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
2056  * This function returns the dma address of a given item
2057  */
2058 static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
2059                                          struct __vxge_hw_ring *ring, u32 from,
2060                                          u32 to)
2061 {
2062         u8 *to_item , *from_item;
2063         dma_addr_t to_dma;
2064
2065         /* get "from" RxD block */
2066         from_item = mempoolh->items_arr[from];
2067         vxge_assert(from_item);
2068
2069         /* get "to" RxD block */
2070         to_item = mempoolh->items_arr[to];
2071         vxge_assert(to_item);
2072
2073         /* return address of the beginning of previous RxD block */
2074         to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
2075
2076         /* set next pointer for this RxD block to point on
2077          * previous item's DMA start address */
2078         __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
2079 }
2080
2081 /*
2082  * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
2083  * block callback
2084  * This function is callback passed to __vxge_hw_mempool_create to create memory
2085  * pool for RxD block
2086  */
2087 static void
2088 __vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
2089                                   u32 memblock_index,
2090                                   struct vxge_hw_mempool_dma *dma_object,
2091                                   u32 index, u32 is_last)
2092 {
2093         u32 i;
2094         void *item = mempoolh->items_arr[index];
2095         struct __vxge_hw_ring *ring =
2096                 (struct __vxge_hw_ring *)mempoolh->userdata;
2097
2098         /* format rxds array */
2099         for (i = 0; i < ring->rxds_per_block; i++) {
2100                 void *rxdblock_priv;
2101                 void *uld_priv;
2102                 struct vxge_hw_ring_rxd_1 *rxdp;
2103
2104                 u32 reserve_index = ring->channel.reserve_ptr -
2105                                 (index * ring->rxds_per_block + i + 1);
2106                 u32 memblock_item_idx;
2107
2108                 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
2109                                                 i * ring->rxd_size;
2110
2111                 /* Note: memblock_item_idx is index of the item within
2112                  *       the memblock. For instance, in case of three RxD-blocks
2113                  *       per memblock this value can be 0, 1 or 2. */
2114                 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
2115                                         memblock_index, item,
2116                                         &memblock_item_idx);
2117
2118                 rxdp = ring->channel.reserve_arr[reserve_index];
2119
2120                 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
2121
2122                 /* pre-format Host_Control */
2123                 rxdp->host_control = (u64)(size_t)uld_priv;
2124         }
2125
2126         __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
2127
2128         if (is_last) {
2129                 /* link last one with first one */
2130                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
2131         }
2132
2133         if (index > 0) {
2134                 /* link this RxD block with previous one */
2135                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
2136         }
2137 }
2138
2139 /*
2140  * __vxge_hw_ring_replenish - Initial replenish of RxDs
2141  * This function replenishes the RxDs from reserve array to work array
2142  */
2143 static enum vxge_hw_status
2144 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
2145 {
2146         void *rxd;
2147         struct __vxge_hw_channel *channel;
2148         enum vxge_hw_status status = VXGE_HW_OK;
2149
2150         channel = &ring->channel;
2151
2152         while (vxge_hw_channel_dtr_count(channel) > 0) {
2153
2154                 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
2155
2156                 vxge_assert(status == VXGE_HW_OK);
2157
2158                 if (ring->rxd_init) {
2159                         status = ring->rxd_init(rxd, channel->userdata);
2160                         if (status != VXGE_HW_OK) {
2161                                 vxge_hw_ring_rxd_free(ring, rxd);
2162                                 goto exit;
2163                         }
2164                 }
2165
2166                 vxge_hw_ring_rxd_post(ring, rxd);
2167         }
2168         status = VXGE_HW_OK;
2169 exit:
2170         return status;
2171 }
2172
2173 /*
2174  * __vxge_hw_channel_allocate - Allocate memory for channel
2175  * This function allocates required memory for the channel and various arrays
2176  * in the channel
2177  */
2178 static struct __vxge_hw_channel *
2179 __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2180                            enum __vxge_hw_channel_type type,
2181                            u32 length, u32 per_dtr_space,
2182                            void *userdata)
2183 {
2184         struct __vxge_hw_channel *channel;
2185         struct __vxge_hw_device *hldev;
2186         int size = 0;
2187         u32 vp_id;
2188
2189         hldev = vph->vpath->hldev;
2190         vp_id = vph->vpath->vp_id;
2191
2192         switch (type) {
2193         case VXGE_HW_CHANNEL_TYPE_FIFO:
2194                 size = sizeof(struct __vxge_hw_fifo);
2195                 break;
2196         case VXGE_HW_CHANNEL_TYPE_RING:
2197                 size = sizeof(struct __vxge_hw_ring);
2198                 break;
2199         default:
2200                 break;
2201         }
2202
2203         channel = kzalloc(size, GFP_KERNEL);
2204         if (channel == NULL)
2205                 goto exit0;
2206         INIT_LIST_HEAD(&channel->item);
2207
2208         channel->common_reg = hldev->common_reg;
2209         channel->first_vp_id = hldev->first_vp_id;
2210         channel->type = type;
2211         channel->devh = hldev;
2212         channel->vph = vph;
2213         channel->userdata = userdata;
2214         channel->per_dtr_space = per_dtr_space;
2215         channel->length = length;
2216         channel->vp_id = vp_id;
2217
2218         channel->work_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2219         if (channel->work_arr == NULL)
2220                 goto exit1;
2221
2222         channel->free_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2223         if (channel->free_arr == NULL)
2224                 goto exit1;
2225         channel->free_ptr = length;
2226
2227         channel->reserve_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2228         if (channel->reserve_arr == NULL)
2229                 goto exit1;
2230         channel->reserve_ptr = length;
2231         channel->reserve_top = 0;
2232
2233         channel->orig_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2234         if (channel->orig_arr == NULL)
2235                 goto exit1;
2236
2237         return channel;
2238 exit1:
2239         __vxge_hw_channel_free(channel);
2240
2241 exit0:
2242         return NULL;
2243 }
2244
2245 /*
2246  * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
2247  * Adds a block to block pool
2248  */
2249 static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
2250                                         void *block_addr,
2251                                         u32 length,
2252                                         struct pci_dev *dma_h,
2253                                         struct pci_dev *acc_handle)
2254 {
2255         struct __vxge_hw_blockpool *blockpool;
2256         struct __vxge_hw_blockpool_entry *entry = NULL;
2257         dma_addr_t dma_addr;
2258
2259         blockpool = &devh->block_pool;
2260
2261         if (block_addr == NULL) {
2262                 blockpool->req_out--;
2263                 goto exit;
2264         }
2265
2266         dma_addr = pci_map_single(devh->pdev, block_addr, length,
2267                                 PCI_DMA_BIDIRECTIONAL);
2268
2269         if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
2270                 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
2271                 blockpool->req_out--;
2272                 goto exit;
2273         }
2274
2275         if (!list_empty(&blockpool->free_entry_list))
2276                 entry = (struct __vxge_hw_blockpool_entry *)
2277                         list_first_entry(&blockpool->free_entry_list,
2278                                 struct __vxge_hw_blockpool_entry,
2279                                 item);
2280
2281         if (entry == NULL)
2282                 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
2283         else
2284                 list_del(&entry->item);
2285
2286         if (entry) {
2287                 entry->length = length;
2288                 entry->memblock = block_addr;
2289                 entry->dma_addr = dma_addr;
2290                 entry->acc_handle = acc_handle;
2291                 entry->dma_handle = dma_h;
2292                 list_add(&entry->item, &blockpool->free_block_list);
2293                 blockpool->pool_size++;
2294         }
2295
2296         blockpool->req_out--;
2297
2298 exit:
2299         return;
2300 }
2301
2302 static inline void
2303 vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
2304 {
2305         gfp_t flags;
2306         void *vaddr;
2307
2308         if (in_interrupt())
2309                 flags = GFP_ATOMIC | GFP_DMA;
2310         else
2311                 flags = GFP_KERNEL | GFP_DMA;
2312
2313         vaddr = kmalloc((size), flags);
2314
2315         vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
2316 }
2317
2318 /*
2319  * __vxge_hw_blockpool_blocks_add - Request additional blocks
2320  */
2321 static
2322 void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
2323 {
2324         u32 nreq = 0, i;
2325
2326         if ((blockpool->pool_size  +  blockpool->req_out) <
2327                 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
2328                 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
2329                 blockpool->req_out += nreq;
2330         }
2331
2332         for (i = 0; i < nreq; i++)
2333                 vxge_os_dma_malloc_async(
2334                         (blockpool->hldev)->pdev,
2335                         blockpool->hldev, VXGE_HW_BLOCK_SIZE);
2336 }
2337
2338 /*
2339  * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
2340  * Allocates a block of memory of given size, either from block pool
2341  * or by calling vxge_os_dma_malloc()
2342  */
2343 static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
2344                                         struct vxge_hw_mempool_dma *dma_object)
2345 {
2346         struct __vxge_hw_blockpool_entry *entry = NULL;
2347         struct __vxge_hw_blockpool  *blockpool;
2348         void *memblock = NULL;
2349
2350         blockpool = &devh->block_pool;
2351
2352         if (size != blockpool->block_size) {
2353
2354                 memblock = vxge_os_dma_malloc(devh->pdev, size,
2355                                                 &dma_object->handle,
2356                                                 &dma_object->acc_handle);
2357
2358                 if (!memblock)
2359                         goto exit;
2360
2361                 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
2362                                         PCI_DMA_BIDIRECTIONAL);
2363
2364                 if (unlikely(pci_dma_mapping_error(devh->pdev,
2365                                 dma_object->addr))) {
2366                         vxge_os_dma_free(devh->pdev, memblock,
2367                                 &dma_object->acc_handle);
2368                         memblock = NULL;
2369                         goto exit;
2370                 }
2371
2372         } else {
2373
2374                 if (!list_empty(&blockpool->free_block_list))
2375                         entry = (struct __vxge_hw_blockpool_entry *)
2376                                 list_first_entry(&blockpool->free_block_list,
2377                                         struct __vxge_hw_blockpool_entry,
2378                                         item);
2379
2380                 if (entry != NULL) {
2381                         list_del(&entry->item);
2382                         dma_object->addr = entry->dma_addr;
2383                         dma_object->handle = entry->dma_handle;
2384                         dma_object->acc_handle = entry->acc_handle;
2385                         memblock = entry->memblock;
2386
2387                         list_add(&entry->item,
2388                                 &blockpool->free_entry_list);
2389                         blockpool->pool_size--;
2390                 }
2391
2392                 if (memblock != NULL)
2393                         __vxge_hw_blockpool_blocks_add(blockpool);
2394         }
2395 exit:
2396         return memblock;
2397 }
2398
2399 /*
2400  * __vxge_hw_blockpool_blocks_remove - Free additional blocks
2401  */
2402 static void
2403 __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
2404 {
2405         struct list_head *p, *n;
2406
2407         list_for_each_safe(p, n, &blockpool->free_block_list) {
2408
2409                 if (blockpool->pool_size < blockpool->pool_max)
2410                         break;
2411
2412                 pci_unmap_single(
2413                         (blockpool->hldev)->pdev,
2414                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
2415                         ((struct __vxge_hw_blockpool_entry *)p)->length,
2416                         PCI_DMA_BIDIRECTIONAL);
2417
2418                 vxge_os_dma_free(
2419                         (blockpool->hldev)->pdev,
2420                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
2421                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
2422
2423                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
2424
2425                 list_add(p, &blockpool->free_entry_list);
2426
2427                 blockpool->pool_size--;
2428
2429         }
2430 }
2431
2432 /*
2433  * __vxge_hw_blockpool_free - Frees the memory allcoated with
2434  *                              __vxge_hw_blockpool_malloc
2435  */
2436 static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
2437                                      void *memblock, u32 size,
2438                                      struct vxge_hw_mempool_dma *dma_object)
2439 {
2440         struct __vxge_hw_blockpool_entry *entry = NULL;
2441         struct __vxge_hw_blockpool  *blockpool;
2442         enum vxge_hw_status status = VXGE_HW_OK;
2443
2444         blockpool = &devh->block_pool;
2445
2446         if (size != blockpool->block_size) {
2447                 pci_unmap_single(devh->pdev, dma_object->addr, size,
2448                         PCI_DMA_BIDIRECTIONAL);
2449                 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
2450         } else {
2451
2452                 if (!list_empty(&blockpool->free_entry_list))
2453                         entry = (struct __vxge_hw_blockpool_entry *)
2454                                 list_first_entry(&blockpool->free_entry_list,
2455                                         struct __vxge_hw_blockpool_entry,
2456                                         item);
2457
2458                 if (entry == NULL)
2459                         entry = vmalloc(sizeof(
2460                                         struct __vxge_hw_blockpool_entry));
2461                 else
2462                         list_del(&entry->item);
2463
2464                 if (entry != NULL) {
2465                         entry->length = size;
2466                         entry->memblock = memblock;
2467                         entry->dma_addr = dma_object->addr;
2468                         entry->acc_handle = dma_object->acc_handle;
2469                         entry->dma_handle = dma_object->handle;
2470                         list_add(&entry->item,
2471                                         &blockpool->free_block_list);
2472                         blockpool->pool_size++;
2473                         status = VXGE_HW_OK;
2474                 } else
2475                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2476
2477                 if (status == VXGE_HW_OK)
2478                         __vxge_hw_blockpool_blocks_remove(blockpool);
2479         }
2480 }
2481
2482 /*
2483  * vxge_hw_mempool_destroy
2484  */
2485 static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
2486 {
2487         u32 i, j;
2488         struct __vxge_hw_device *devh = mempool->devh;
2489
2490         for (i = 0; i < mempool->memblocks_allocated; i++) {
2491                 struct vxge_hw_mempool_dma *dma_object;
2492
2493                 vxge_assert(mempool->memblocks_arr[i]);
2494                 vxge_assert(mempool->memblocks_dma_arr + i);
2495
2496                 dma_object = mempool->memblocks_dma_arr + i;
2497
2498                 for (j = 0; j < mempool->items_per_memblock; j++) {
2499                         u32 index = i * mempool->items_per_memblock + j;
2500
2501                         /* to skip last partially filled(if any) memblock */
2502                         if (index >= mempool->items_current)
2503                                 break;
2504                 }
2505
2506                 vfree(mempool->memblocks_priv_arr[i]);
2507
2508                 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2509                                 mempool->memblock_size, dma_object);
2510         }
2511
2512         vfree(mempool->items_arr);
2513         vfree(mempool->memblocks_dma_arr);
2514         vfree(mempool->memblocks_priv_arr);
2515         vfree(mempool->memblocks_arr);
2516         vfree(mempool);
2517 }
2518
2519 /*
2520  * __vxge_hw_mempool_grow
2521  * Will resize mempool up to %num_allocate value.
2522  */
2523 static enum vxge_hw_status
2524 __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2525                        u32 *num_allocated)
2526 {
2527         u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2528         u32 n_items = mempool->items_per_memblock;
2529         u32 start_block_idx = mempool->memblocks_allocated;
2530         u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2531         enum vxge_hw_status status = VXGE_HW_OK;
2532
2533         *num_allocated = 0;
2534
2535         if (end_block_idx > mempool->memblocks_max) {
2536                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2537                 goto exit;
2538         }
2539
2540         for (i = start_block_idx; i < end_block_idx; i++) {
2541                 u32 j;
2542                 u32 is_last = ((end_block_idx - 1) == i);
2543                 struct vxge_hw_mempool_dma *dma_object =
2544                         mempool->memblocks_dma_arr + i;
2545                 void *the_memblock;
2546
2547                 /* allocate memblock's private part. Each DMA memblock
2548                  * has a space allocated for item's private usage upon
2549                  * mempool's user request. Each time mempool grows, it will
2550                  * allocate new memblock and its private part at once.
2551                  * This helps to minimize memory usage a lot. */
2552                 mempool->memblocks_priv_arr[i] =
2553                         vzalloc(array_size(mempool->items_priv_size, n_items));
2554                 if (mempool->memblocks_priv_arr[i] == NULL) {
2555                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2556                         goto exit;
2557                 }
2558
2559                 /* allocate DMA-capable memblock */
2560                 mempool->memblocks_arr[i] =
2561                         __vxge_hw_blockpool_malloc(mempool->devh,
2562                                 mempool->memblock_size, dma_object);
2563                 if (mempool->memblocks_arr[i] == NULL) {
2564                         vfree(mempool->memblocks_priv_arr[i]);
2565                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2566                         goto exit;
2567                 }
2568
2569                 (*num_allocated)++;
2570                 mempool->memblocks_allocated++;
2571
2572                 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2573
2574                 the_memblock = mempool->memblocks_arr[i];
2575
2576                 /* fill the items hash array */
2577                 for (j = 0; j < n_items; j++) {
2578                         u32 index = i * n_items + j;
2579
2580                         if (first_time && index >= mempool->items_initial)
2581                                 break;
2582
2583                         mempool->items_arr[index] =
2584                                 ((char *)the_memblock + j*mempool->item_size);
2585
2586                         /* let caller to do more job on each item */
2587                         if (mempool->item_func_alloc != NULL)
2588                                 mempool->item_func_alloc(mempool, i,
2589                                         dma_object, index, is_last);
2590
2591                         mempool->items_current = index + 1;
2592                 }
2593
2594                 if (first_time && mempool->items_current ==
2595                                         mempool->items_initial)
2596                         break;
2597         }
2598 exit:
2599         return status;
2600 }
2601
2602 /*
2603  * vxge_hw_mempool_create
2604  * This function will create memory pool object. Pool may grow but will
2605  * never shrink. Pool consists of number of dynamically allocated blocks
2606  * with size enough to hold %items_initial number of items. Memory is
2607  * DMA-able but client must map/unmap before interoperating with the device.
2608  */
2609 static struct vxge_hw_mempool *
2610 __vxge_hw_mempool_create(struct __vxge_hw_device *devh,
2611                          u32 memblock_size,
2612                          u32 item_size,
2613                          u32 items_priv_size,
2614                          u32 items_initial,
2615                          u32 items_max,
2616                          const struct vxge_hw_mempool_cbs *mp_callback,
2617                          void *userdata)
2618 {
2619         enum vxge_hw_status status = VXGE_HW_OK;
2620         u32 memblocks_to_allocate;
2621         struct vxge_hw_mempool *mempool = NULL;
2622         u32 allocated;
2623
2624         if (memblock_size < item_size) {
2625                 status = VXGE_HW_FAIL;
2626                 goto exit;
2627         }
2628
2629         mempool = vzalloc(sizeof(struct vxge_hw_mempool));
2630         if (mempool == NULL) {
2631                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2632                 goto exit;
2633         }
2634
2635         mempool->devh                   = devh;
2636         mempool->memblock_size          = memblock_size;
2637         mempool->items_max              = items_max;
2638         mempool->items_initial          = items_initial;
2639         mempool->item_size              = item_size;
2640         mempool->items_priv_size        = items_priv_size;
2641         mempool->item_func_alloc        = mp_callback->item_func_alloc;
2642         mempool->userdata               = userdata;
2643
2644         mempool->memblocks_allocated = 0;
2645
2646         mempool->items_per_memblock = memblock_size / item_size;
2647
2648         mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2649                                         mempool->items_per_memblock;
2650
2651         /* allocate array of memblocks */
2652         mempool->memblocks_arr =
2653                 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2654         if (mempool->memblocks_arr == NULL) {
2655                 __vxge_hw_mempool_destroy(mempool);
2656                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2657                 mempool = NULL;
2658                 goto exit;
2659         }
2660
2661         /* allocate array of private parts of items per memblocks */
2662         mempool->memblocks_priv_arr =
2663                 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2664         if (mempool->memblocks_priv_arr == NULL) {
2665                 __vxge_hw_mempool_destroy(mempool);
2666                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2667                 mempool = NULL;
2668                 goto exit;
2669         }
2670
2671         /* allocate array of memblocks DMA objects */
2672         mempool->memblocks_dma_arr =
2673                 vzalloc(array_size(sizeof(struct vxge_hw_mempool_dma),
2674                                    mempool->memblocks_max));
2675         if (mempool->memblocks_dma_arr == NULL) {
2676                 __vxge_hw_mempool_destroy(mempool);
2677                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2678                 mempool = NULL;
2679                 goto exit;
2680         }
2681
2682         /* allocate hash array of items */
2683         mempool->items_arr = vzalloc(array_size(sizeof(void *),
2684                                                 mempool->items_max));
2685         if (mempool->items_arr == NULL) {
2686                 __vxge_hw_mempool_destroy(mempool);
2687                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2688                 mempool = NULL;
2689                 goto exit;
2690         }
2691
2692         /* calculate initial number of memblocks */
2693         memblocks_to_allocate = (mempool->items_initial +
2694                                  mempool->items_per_memblock - 1) /
2695                                                 mempool->items_per_memblock;
2696
2697         /* pre-allocate the mempool */
2698         status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2699                                         &allocated);
2700         if (status != VXGE_HW_OK) {
2701                 __vxge_hw_mempool_destroy(mempool);
2702                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2703                 mempool = NULL;
2704                 goto exit;
2705         }
2706
2707 exit:
2708         return mempool;
2709 }
2710
2711 /*
2712  * __vxge_hw_ring_abort - Returns the RxD
2713  * This function terminates the RxDs of ring
2714  */
2715 static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
2716 {
2717         void *rxdh;
2718         struct __vxge_hw_channel *channel;
2719
2720         channel = &ring->channel;
2721
2722         for (;;) {
2723                 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
2724
2725                 if (rxdh == NULL)
2726                         break;
2727
2728                 vxge_hw_channel_dtr_complete(channel);
2729
2730                 if (ring->rxd_term)
2731                         ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
2732                                 channel->userdata);
2733
2734                 vxge_hw_channel_dtr_free(channel, rxdh);
2735         }
2736
2737         return VXGE_HW_OK;
2738 }
2739
2740 /*
2741  * __vxge_hw_ring_reset - Resets the ring
2742  * This function resets the ring during vpath reset operation
2743  */
2744 static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
2745 {
2746         enum vxge_hw_status status = VXGE_HW_OK;
2747         struct __vxge_hw_channel *channel;
2748
2749         channel = &ring->channel;
2750
2751         __vxge_hw_ring_abort(ring);
2752
2753         status = __vxge_hw_channel_reset(channel);
2754
2755         if (status != VXGE_HW_OK)
2756                 goto exit;
2757
2758         if (ring->rxd_init) {
2759                 status = vxge_hw_ring_replenish(ring);
2760                 if (status != VXGE_HW_OK)
2761                         goto exit;
2762         }
2763 exit:
2764         return status;
2765 }
2766
2767 /*
2768  * __vxge_hw_ring_delete - Removes the ring
2769  * This function freeup the memory pool and removes the ring
2770  */
2771 static enum vxge_hw_status
2772 __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
2773 {
2774         struct __vxge_hw_ring *ring = vp->vpath->ringh;
2775
2776         __vxge_hw_ring_abort(ring);
2777
2778         if (ring->mempool)
2779                 __vxge_hw_mempool_destroy(ring->mempool);
2780
2781         vp->vpath->ringh = NULL;
2782         __vxge_hw_channel_free(&ring->channel);
2783
2784         return VXGE_HW_OK;
2785 }
2786
2787 /*
2788  * __vxge_hw_ring_create - Create a Ring
2789  * This function creates Ring and initializes it.
2790  */
2791 static enum vxge_hw_status
2792 __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
2793                       struct vxge_hw_ring_attr *attr)
2794 {
2795         enum vxge_hw_status status = VXGE_HW_OK;
2796         struct __vxge_hw_ring *ring;
2797         u32 ring_length;
2798         struct vxge_hw_ring_config *config;
2799         struct __vxge_hw_device *hldev;
2800         u32 vp_id;
2801         static const struct vxge_hw_mempool_cbs ring_mp_callback = {
2802                 .item_func_alloc = __vxge_hw_ring_mempool_item_alloc,
2803         };
2804
2805         if ((vp == NULL) || (attr == NULL)) {
2806                 status = VXGE_HW_FAIL;
2807                 goto exit;
2808         }
2809
2810         hldev = vp->vpath->hldev;
2811         vp_id = vp->vpath->vp_id;
2812
2813         config = &hldev->config.vp_config[vp_id].ring;
2814
2815         ring_length = config->ring_blocks *
2816                         vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2817
2818         ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
2819                                                 VXGE_HW_CHANNEL_TYPE_RING,
2820                                                 ring_length,
2821                                                 attr->per_rxd_space,
2822                                                 attr->userdata);
2823         if (ring == NULL) {
2824                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2825                 goto exit;
2826         }
2827
2828         vp->vpath->ringh = ring;
2829         ring->vp_id = vp_id;
2830         ring->vp_reg = vp->vpath->vp_reg;
2831         ring->common_reg = hldev->common_reg;
2832         ring->stats = &vp->vpath->sw_stats->ring_stats;
2833         ring->config = config;
2834         ring->callback = attr->callback;
2835         ring->rxd_init = attr->rxd_init;
2836         ring->rxd_term = attr->rxd_term;
2837         ring->buffer_mode = config->buffer_mode;
2838         ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
2839         ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
2840         ring->rxds_limit = config->rxds_limit;
2841
2842         ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
2843         ring->rxd_priv_size =
2844                 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
2845         ring->per_rxd_space = attr->per_rxd_space;
2846
2847         ring->rxd_priv_size =
2848                 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2849                 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2850
2851         /* how many RxDs can fit into one block. Depends on configured
2852          * buffer_mode. */
2853         ring->rxds_per_block =
2854                 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2855
2856         /* calculate actual RxD block private size */
2857         ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
2858         ring->mempool = __vxge_hw_mempool_create(hldev,
2859                                 VXGE_HW_BLOCK_SIZE,
2860                                 VXGE_HW_BLOCK_SIZE,
2861                                 ring->rxdblock_priv_size,
2862                                 ring->config->ring_blocks,
2863                                 ring->config->ring_blocks,
2864                                 &ring_mp_callback,
2865                                 ring);
2866         if (ring->mempool == NULL) {
2867                 __vxge_hw_ring_delete(vp);
2868                 return VXGE_HW_ERR_OUT_OF_MEMORY;
2869         }
2870
2871         status = __vxge_hw_channel_initialize(&ring->channel);
2872         if (status != VXGE_HW_OK) {
2873                 __vxge_hw_ring_delete(vp);
2874                 goto exit;
2875         }
2876
2877         /* Note:
2878          * Specifying rxd_init callback means two things:
2879          * 1) rxds need to be initialized by driver at channel-open time;
2880          * 2) rxds need to be posted at channel-open time
2881          *    (that's what the initial_replenish() below does)
2882          * Currently we don't have a case when the 1) is done without the 2).
2883          */
2884         if (ring->rxd_init) {
2885                 status = vxge_hw_ring_replenish(ring);
2886                 if (status != VXGE_HW_OK) {
2887                         __vxge_hw_ring_delete(vp);
2888                         goto exit;
2889                 }
2890         }
2891
2892         /* initial replenish will increment the counter in its post() routine,
2893          * we have to reset it */
2894         ring->stats->common_stats.usage_cnt = 0;
2895 exit:
2896         return status;
2897 }
2898
2899 /*
2900  * vxge_hw_device_config_default_get - Initialize device config with defaults.
2901  * Initialize Titan device config with default values.
2902  */
2903 enum vxge_hw_status
2904 vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2905 {
2906         u32 i;
2907
2908         device_config->dma_blockpool_initial =
2909                                         VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2910         device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2911         device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2912         device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2913         device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2914         device_config->device_poll_millis =  VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2915         device_config->rts_mac_en =  VXGE_HW_RTS_MAC_DEFAULT;
2916
2917         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2918                 device_config->vp_config[i].vp_id = i;
2919
2920                 device_config->vp_config[i].min_bandwidth =
2921                                 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2922
2923                 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2924
2925                 device_config->vp_config[i].ring.ring_blocks =
2926                                 VXGE_HW_DEF_RING_BLOCKS;
2927
2928                 device_config->vp_config[i].ring.buffer_mode =
2929                                 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2930
2931                 device_config->vp_config[i].ring.scatter_mode =
2932                                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2933
2934                 device_config->vp_config[i].ring.rxds_limit =
2935                                 VXGE_HW_DEF_RING_RXDS_LIMIT;
2936
2937                 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2938
2939                 device_config->vp_config[i].fifo.fifo_blocks =
2940                                 VXGE_HW_MIN_FIFO_BLOCKS;
2941
2942                 device_config->vp_config[i].fifo.max_frags =
2943                                 VXGE_HW_MAX_FIFO_FRAGS;
2944
2945                 device_config->vp_config[i].fifo.memblock_size =
2946                                 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2947
2948                 device_config->vp_config[i].fifo.alignment_size =
2949                                 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2950
2951                 device_config->vp_config[i].fifo.intr =
2952                                 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2953
2954                 device_config->vp_config[i].fifo.no_snoop_bits =
2955                                 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2956                 device_config->vp_config[i].tti.intr_enable =
2957                                 VXGE_HW_TIM_INTR_DEFAULT;
2958
2959                 device_config->vp_config[i].tti.btimer_val =
2960                                 VXGE_HW_USE_FLASH_DEFAULT;
2961
2962                 device_config->vp_config[i].tti.timer_ac_en =
2963                                 VXGE_HW_USE_FLASH_DEFAULT;
2964
2965                 device_config->vp_config[i].tti.timer_ci_en =
2966                                 VXGE_HW_USE_FLASH_DEFAULT;
2967
2968                 device_config->vp_config[i].tti.timer_ri_en =
2969                                 VXGE_HW_USE_FLASH_DEFAULT;
2970
2971                 device_config->vp_config[i].tti.rtimer_val =
2972                                 VXGE_HW_USE_FLASH_DEFAULT;
2973
2974                 device_config->vp_config[i].tti.util_sel =
2975                                 VXGE_HW_USE_FLASH_DEFAULT;
2976
2977                 device_config->vp_config[i].tti.ltimer_val =
2978                                 VXGE_HW_USE_FLASH_DEFAULT;
2979
2980                 device_config->vp_config[i].tti.urange_a =
2981                                 VXGE_HW_USE_FLASH_DEFAULT;
2982
2983                 device_config->vp_config[i].tti.uec_a =
2984                                 VXGE_HW_USE_FLASH_DEFAULT;
2985
2986                 device_config->vp_config[i].tti.urange_b =
2987                                 VXGE_HW_USE_FLASH_DEFAULT;
2988
2989                 device_config->vp_config[i].tti.uec_b =
2990                                 VXGE_HW_USE_FLASH_DEFAULT;
2991
2992                 device_config->vp_config[i].tti.urange_c =
2993                                 VXGE_HW_USE_FLASH_DEFAULT;
2994
2995                 device_config->vp_config[i].tti.uec_c =
2996                                 VXGE_HW_USE_FLASH_DEFAULT;
2997
2998                 device_config->vp_config[i].tti.uec_d =
2999                                 VXGE_HW_USE_FLASH_DEFAULT;
3000
3001                 device_config->vp_config[i].rti.intr_enable =
3002                                 VXGE_HW_TIM_INTR_DEFAULT;
3003
3004                 device_config->vp_config[i].rti.btimer_val =
3005                                 VXGE_HW_USE_FLASH_DEFAULT;
3006
3007                 device_config->vp_config[i].rti.timer_ac_en =
3008                                 VXGE_HW_USE_FLASH_DEFAULT;
3009
3010                 device_config->vp_config[i].rti.timer_ci_en =
3011                                 VXGE_HW_USE_FLASH_DEFAULT;
3012
3013                 device_config->vp_config[i].rti.timer_ri_en =
3014                                 VXGE_HW_USE_FLASH_DEFAULT;
3015
3016                 device_config->vp_config[i].rti.rtimer_val =
3017                                 VXGE_HW_USE_FLASH_DEFAULT;
3018
3019                 device_config->vp_config[i].rti.util_sel =
3020                                 VXGE_HW_USE_FLASH_DEFAULT;
3021
3022                 device_config->vp_config[i].rti.ltimer_val =
3023                                 VXGE_HW_USE_FLASH_DEFAULT;
3024
3025                 device_config->vp_config[i].rti.urange_a =
3026                                 VXGE_HW_USE_FLASH_DEFAULT;
3027
3028                 device_config->vp_config[i].rti.uec_a =
3029                                 VXGE_HW_USE_FLASH_DEFAULT;
3030
3031                 device_config->vp_config[i].rti.urange_b =
3032                                 VXGE_HW_USE_FLASH_DEFAULT;
3033
3034                 device_config->vp_config[i].rti.uec_b =
3035                                 VXGE_HW_USE_FLASH_DEFAULT;
3036
3037                 device_config->vp_config[i].rti.urange_c =
3038                                 VXGE_HW_USE_FLASH_DEFAULT;
3039
3040                 device_config->vp_config[i].rti.uec_c =
3041                                 VXGE_HW_USE_FLASH_DEFAULT;
3042
3043                 device_config->vp_config[i].rti.uec_d =
3044                                 VXGE_HW_USE_FLASH_DEFAULT;
3045
3046                 device_config->vp_config[i].mtu =
3047                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
3048
3049                 device_config->vp_config[i].rpa_strip_vlan_tag =
3050                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
3051         }
3052
3053         return VXGE_HW_OK;
3054 }
3055
3056 /*
3057  * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
3058  * Set the swapper bits appropriately for the vpath.
3059  */
3060 static enum vxge_hw_status
3061 __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
3062 {
3063 #ifndef __BIG_ENDIAN
3064         u64 val64;
3065
3066         val64 = readq(&vpath_reg->vpath_general_cfg1);
3067         wmb();
3068         val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
3069         writeq(val64, &vpath_reg->vpath_general_cfg1);
3070         wmb();
3071 #endif
3072         return VXGE_HW_OK;
3073 }
3074
3075 /*
3076  * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
3077  * Set the swapper bits appropriately for the vpath.
3078  */
3079 static enum vxge_hw_status
3080 __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
3081                            struct vxge_hw_vpath_reg __iomem *vpath_reg)
3082 {
3083         u64 val64;
3084
3085         val64 = readq(&legacy_reg->pifm_wr_swap_en);
3086
3087         if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
3088                 val64 = readq(&vpath_reg->kdfcctl_cfg0);
3089                 wmb();
3090
3091                 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
3092                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1  |
3093                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
3094
3095                 writeq(val64, &vpath_reg->kdfcctl_cfg0);
3096                 wmb();
3097         }
3098
3099         return VXGE_HW_OK;
3100 }
3101
3102 /*
3103  * vxge_hw_mgmt_reg_read - Read Titan register.
3104  */
3105 enum vxge_hw_status
3106 vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
3107                       enum vxge_hw_mgmt_reg_type type,
3108                       u32 index, u32 offset, u64 *value)
3109 {
3110         enum vxge_hw_status status = VXGE_HW_OK;
3111
3112         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3113                 status = VXGE_HW_ERR_INVALID_DEVICE;
3114                 goto exit;
3115         }
3116
3117         switch (type) {
3118         case vxge_hw_mgmt_reg_type_legacy:
3119                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3120                         status = VXGE_HW_ERR_INVALID_OFFSET;
3121                         break;
3122                 }
3123                 *value = readq((void __iomem *)hldev->legacy_reg + offset);
3124                 break;
3125         case vxge_hw_mgmt_reg_type_toc:
3126                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3127                         status = VXGE_HW_ERR_INVALID_OFFSET;
3128                         break;
3129                 }
3130                 *value = readq((void __iomem *)hldev->toc_reg + offset);
3131                 break;
3132         case vxge_hw_mgmt_reg_type_common:
3133                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3134                         status = VXGE_HW_ERR_INVALID_OFFSET;
3135                         break;
3136                 }
3137                 *value = readq((void __iomem *)hldev->common_reg + offset);
3138                 break;
3139         case vxge_hw_mgmt_reg_type_mrpcim:
3140                 if (!(hldev->access_rights &
3141                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3142                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3143                         break;
3144                 }
3145                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3146                         status = VXGE_HW_ERR_INVALID_OFFSET;
3147                         break;
3148                 }
3149                 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
3150                 break;
3151         case vxge_hw_mgmt_reg_type_srpcim:
3152                 if (!(hldev->access_rights &
3153                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3154                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3155                         break;
3156                 }
3157                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3158                         status = VXGE_HW_ERR_INVALID_INDEX;
3159                         break;
3160                 }
3161                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3162                         status = VXGE_HW_ERR_INVALID_OFFSET;
3163                         break;
3164                 }
3165                 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
3166                                 offset);
3167                 break;
3168         case vxge_hw_mgmt_reg_type_vpmgmt:
3169                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3170                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3171                         status = VXGE_HW_ERR_INVALID_INDEX;
3172                         break;
3173                 }
3174                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3175                         status = VXGE_HW_ERR_INVALID_OFFSET;
3176                         break;
3177                 }
3178                 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
3179                                 offset);
3180                 break;
3181         case vxge_hw_mgmt_reg_type_vpath:
3182                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
3183                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3184                         status = VXGE_HW_ERR_INVALID_INDEX;
3185                         break;
3186                 }
3187                 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
3188                         status = VXGE_HW_ERR_INVALID_INDEX;
3189                         break;
3190                 }
3191                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3192                         status = VXGE_HW_ERR_INVALID_OFFSET;
3193                         break;
3194                 }
3195                 *value = readq((void __iomem *)hldev->vpath_reg[index] +
3196                                 offset);
3197                 break;
3198         default:
3199                 status = VXGE_HW_ERR_INVALID_TYPE;
3200                 break;
3201         }
3202
3203 exit:
3204         return status;
3205 }
3206
3207 /*
3208  * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
3209  */
3210 enum vxge_hw_status
3211 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
3212 {
3213         struct vxge_hw_vpmgmt_reg       __iomem *vpmgmt_reg;
3214         int i = 0, j = 0;
3215
3216         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3217                 if (!((vpath_mask) & vxge_mBIT(i)))
3218                         continue;
3219                 vpmgmt_reg = hldev->vpmgmt_reg[i];
3220                 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
3221                         if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
3222                         & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
3223                                 return VXGE_HW_FAIL;
3224                 }
3225         }
3226         return VXGE_HW_OK;
3227 }
3228 /*
3229  * vxge_hw_mgmt_reg_Write - Write Titan register.
3230  */
3231 enum vxge_hw_status
3232 vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
3233                       enum vxge_hw_mgmt_reg_type type,
3234                       u32 index, u32 offset, u64 value)
3235 {
3236         enum vxge_hw_status status = VXGE_HW_OK;
3237
3238         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3239                 status = VXGE_HW_ERR_INVALID_DEVICE;
3240                 goto exit;
3241         }
3242
3243         switch (type) {
3244         case vxge_hw_mgmt_reg_type_legacy:
3245                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3246                         status = VXGE_HW_ERR_INVALID_OFFSET;
3247                         break;
3248                 }
3249                 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
3250                 break;
3251         case vxge_hw_mgmt_reg_type_toc:
3252                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3253                         status = VXGE_HW_ERR_INVALID_OFFSET;
3254                         break;
3255                 }
3256                 writeq(value, (void __iomem *)hldev->toc_reg + offset);
3257                 break;
3258         case vxge_hw_mgmt_reg_type_common:
3259                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3260                         status = VXGE_HW_ERR_INVALID_OFFSET;
3261                         break;
3262                 }
3263                 writeq(value, (void __iomem *)hldev->common_reg + offset);
3264                 break;
3265         case vxge_hw_mgmt_reg_type_mrpcim:
3266                 if (!(hldev->access_rights &
3267                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3268                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3269                         break;
3270                 }
3271                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3272                         status = VXGE_HW_ERR_INVALID_OFFSET;
3273                         break;
3274                 }
3275                 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
3276                 break;
3277         case vxge_hw_mgmt_reg_type_srpcim:
3278                 if (!(hldev->access_rights &
3279                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3280                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3281                         break;
3282                 }
3283                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3284                         status = VXGE_HW_ERR_INVALID_INDEX;
3285                         break;
3286                 }
3287                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3288                         status = VXGE_HW_ERR_INVALID_OFFSET;
3289                         break;
3290                 }
3291                 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
3292                         offset);
3293
3294                 break;
3295         case vxge_hw_mgmt_reg_type_vpmgmt:
3296                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3297                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3298                         status = VXGE_HW_ERR_INVALID_INDEX;
3299                         break;
3300                 }
3301                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3302                         status = VXGE_HW_ERR_INVALID_OFFSET;
3303                         break;
3304                 }
3305                 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
3306                         offset);
3307                 break;
3308         case vxge_hw_mgmt_reg_type_vpath:
3309                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
3310                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3311                         status = VXGE_HW_ERR_INVALID_INDEX;
3312                         break;
3313                 }
3314                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3315                         status = VXGE_HW_ERR_INVALID_OFFSET;
3316                         break;
3317                 }
3318                 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
3319                         offset);
3320                 break;
3321         default:
3322                 status = VXGE_HW_ERR_INVALID_TYPE;
3323                 break;
3324         }
3325 exit:
3326         return status;
3327 }
3328
3329 /*
3330  * __vxge_hw_fifo_abort - Returns the TxD
3331  * This function terminates the TxDs of fifo
3332  */
3333 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3334 {
3335         void *txdlh;
3336
3337         for (;;) {
3338                 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3339
3340                 if (txdlh == NULL)
3341                         break;
3342
3343                 vxge_hw_channel_dtr_complete(&fifo->channel);
3344
3345                 if (fifo->txdl_term) {
3346                         fifo->txdl_term(txdlh,
3347                         VXGE_HW_TXDL_STATE_POSTED,
3348                         fifo->channel.userdata);
3349                 }
3350
3351                 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3352         }
3353
3354         return VXGE_HW_OK;
3355 }
3356
3357 /*
3358  * __vxge_hw_fifo_reset - Resets the fifo
3359  * This function resets the fifo during vpath reset operation
3360  */
3361 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3362 {
3363         enum vxge_hw_status status = VXGE_HW_OK;
3364
3365         __vxge_hw_fifo_abort(fifo);
3366         status = __vxge_hw_channel_reset(&fifo->channel);
3367
3368         return status;
3369 }
3370
3371 /*
3372  * __vxge_hw_fifo_delete - Removes the FIFO
3373  * This function freeup the memory pool and removes the FIFO
3374  */
3375 static enum vxge_hw_status
3376 __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
3377 {
3378         struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3379
3380         __vxge_hw_fifo_abort(fifo);
3381
3382         if (fifo->mempool)
3383                 __vxge_hw_mempool_destroy(fifo->mempool);
3384
3385         vp->vpath->fifoh = NULL;
3386
3387         __vxge_hw_channel_free(&fifo->channel);
3388
3389         return VXGE_HW_OK;
3390 }
3391
3392 /*
3393  * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
3394  * list callback
3395  * This function is callback passed to __vxge_hw_mempool_create to create memory
3396  * pool for TxD list
3397  */
3398 static void
3399 __vxge_hw_fifo_mempool_item_alloc(
3400         struct vxge_hw_mempool *mempoolh,
3401         u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
3402         u32 index, u32 is_last)
3403 {
3404         u32 memblock_item_idx;
3405         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
3406         struct vxge_hw_fifo_txd *txdp =
3407                 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
3408         struct __vxge_hw_fifo *fifo =
3409                         (struct __vxge_hw_fifo *)mempoolh->userdata;
3410         void *memblock = mempoolh->memblocks_arr[memblock_index];
3411
3412         vxge_assert(txdp);
3413
3414         txdp->host_control = (u64) (size_t)
3415         __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
3416                                         &memblock_item_idx);
3417
3418         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3419
3420         vxge_assert(txdl_priv);
3421
3422         fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3423
3424         /* pre-format HW's TxDL's private */
3425         txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
3426         txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
3427         txdl_priv->dma_handle = dma_object->handle;
3428         txdl_priv->memblock   = memblock;
3429         txdl_priv->first_txdp = txdp;
3430         txdl_priv->next_txdl_priv = NULL;
3431         txdl_priv->alloc_frags = 0;
3432 }
3433
3434 /*
3435  * __vxge_hw_fifo_create - Create a FIFO
3436  * This function creates FIFO and initializes it.
3437  */
3438 static enum vxge_hw_status
3439 __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
3440                       struct vxge_hw_fifo_attr *attr)
3441 {
3442         enum vxge_hw_status status = VXGE_HW_OK;
3443         struct __vxge_hw_fifo *fifo;
3444         struct vxge_hw_fifo_config *config;
3445         u32 txdl_size, txdl_per_memblock;
3446         struct vxge_hw_mempool_cbs fifo_mp_callback;
3447         struct __vxge_hw_virtualpath *vpath;
3448
3449         if ((vp == NULL) || (attr == NULL)) {
3450                 status = VXGE_HW_ERR_INVALID_HANDLE;
3451                 goto exit;
3452         }
3453         vpath = vp->vpath;
3454         config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3455
3456         txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
3457
3458         txdl_per_memblock = config->memblock_size / txdl_size;
3459
3460         fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3461                                         VXGE_HW_CHANNEL_TYPE_FIFO,
3462                                         config->fifo_blocks * txdl_per_memblock,
3463                                         attr->per_txdl_space, attr->userdata);
3464
3465         if (fifo == NULL) {
3466                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3467                 goto exit;
3468         }
3469
3470         vpath->fifoh = fifo;
3471         fifo->nofl_db = vpath->nofl_db;
3472
3473         fifo->vp_id = vpath->vp_id;
3474         fifo->vp_reg = vpath->vp_reg;
3475         fifo->stats = &vpath->sw_stats->fifo_stats;
3476
3477         fifo->config = config;
3478
3479         /* apply "interrupts per txdl" attribute */
3480         fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3481         fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3482         fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3483
3484         if (fifo->config->intr)
3485                 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3486
3487         fifo->no_snoop_bits = config->no_snoop_bits;
3488
3489         /*
3490          * FIFO memory management strategy:
3491          *
3492          * TxDL split into three independent parts:
3493          *      - set of TxD's
3494          *      - TxD HW private part
3495          *      - driver private part
3496          *
3497          * Adaptative memory allocation used. i.e. Memory allocated on
3498          * demand with the size which will fit into one memory block.
3499          * One memory block may contain more than one TxDL.
3500          *
3501          * During "reserve" operations more memory can be allocated on demand
3502          * for example due to FIFO full condition.
3503          *
3504          * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
3505          * routine which will essentially stop the channel and free resources.
3506          */
3507
3508         /* TxDL common private size == TxDL private  +  driver private */
3509         fifo->priv_size =
3510                 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
3511         fifo->priv_size = ((fifo->priv_size  +  VXGE_CACHE_LINE_SIZE - 1) /
3512                         VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
3513
3514         fifo->per_txdl_space = attr->per_txdl_space;
3515
3516         /* recompute txdl size to be cacheline aligned */
3517         fifo->txdl_size = txdl_size;
3518         fifo->txdl_per_memblock = txdl_per_memblock;
3519
3520         fifo->txdl_term = attr->txdl_term;
3521         fifo->callback = attr->callback;
3522
3523         if (fifo->txdl_per_memblock == 0) {
3524                 __vxge_hw_fifo_delete(vp);
3525                 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
3526                 goto exit;
3527         }
3528
3529         fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
3530
3531         fifo->mempool =
3532                 __vxge_hw_mempool_create(vpath->hldev,
3533                         fifo->config->memblock_size,
3534                         fifo->txdl_size,
3535                         fifo->priv_size,
3536                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3537                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3538                         &fifo_mp_callback,
3539                         fifo);
3540
3541         if (fifo->mempool == NULL) {
3542                 __vxge_hw_fifo_delete(vp);
3543                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3544                 goto exit;
3545         }
3546
3547         status = __vxge_hw_channel_initialize(&fifo->channel);
3548         if (status != VXGE_HW_OK) {
3549                 __vxge_hw_fifo_delete(vp);
3550                 goto exit;
3551         }
3552
3553         vxge_assert(fifo->channel.reserve_ptr);
3554 exit:
3555         return status;
3556 }
3557
3558 /*
3559  * __vxge_hw_vpath_pci_read - Read the content of given address
3560  *                          in pci config space.
3561  * Read from the vpath pci config space.
3562  */
3563 static enum vxge_hw_status
3564 __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3565                          u32 phy_func_0, u32 offset, u32 *val)
3566 {
3567         u64 val64;
3568         enum vxge_hw_status status = VXGE_HW_OK;
3569         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3570
3571         val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3572
3573         if (phy_func_0)
3574                 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3575
3576         writeq(val64, &vp_reg->pci_config_access_cfg1);
3577         wmb();
3578         writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3579                         &vp_reg->pci_config_access_cfg2);
3580         wmb();
3581
3582         status = __vxge_hw_device_register_poll(
3583                         &vp_reg->pci_config_access_cfg2,
3584                         VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3585
3586         if (status != VXGE_HW_OK)
3587                 goto exit;
3588
3589         val64 = readq(&vp_reg->pci_config_access_status);
3590
3591         if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3592                 status = VXGE_HW_FAIL;
3593                 *val = 0;
3594         } else
3595                 *val = (u32)vxge_bVALn(val64, 32, 32);
3596 exit:
3597         return status;
3598 }
3599
3600 /**
3601  * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3602  * @hldev: HW device.
3603  * @on_off: TRUE if flickering to be on, FALSE to be off
3604  *
3605  * Flicker the link LED.
3606  */
3607 enum vxge_hw_status
3608 vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
3609 {
3610         struct __vxge_hw_virtualpath *vpath;
3611         u64 data0, data1 = 0, steer_ctrl = 0;
3612         enum vxge_hw_status status;
3613
3614         if (hldev == NULL) {
3615                 status = VXGE_HW_ERR_INVALID_DEVICE;
3616                 goto exit;
3617         }
3618
3619         vpath = &hldev->virtual_paths[hldev->first_vp_id];
3620
3621         data0 = on_off;
3622         status = vxge_hw_vpath_fw_api(vpath,
3623                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3624                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3625                         0, &data0, &data1, &steer_ctrl);
3626 exit:
3627         return status;
3628 }
3629
3630 /*
3631  * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3632  */
3633 enum vxge_hw_status
3634 __vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3635                               u32 action, u32 rts_table, u32 offset,
3636                               u64 *data0, u64 *data1)
3637 {
3638         enum vxge_hw_status status;
3639         u64 steer_ctrl = 0;
3640
3641         if (vp == NULL) {
3642                 status = VXGE_HW_ERR_INVALID_HANDLE;
3643                 goto exit;
3644         }
3645
3646         if ((rts_table ==
3647              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
3648             (rts_table ==
3649              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
3650             (rts_table ==
3651              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
3652             (rts_table ==
3653              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3654                 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
3655         }
3656
3657         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3658                                       data0, data1, &steer_ctrl);
3659         if (status != VXGE_HW_OK)
3660                 goto exit;
3661
3662         if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) &&
3663             (rts_table !=
3664              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3665                 *data1 = 0;
3666 exit:
3667         return status;
3668 }
3669
3670 /*
3671  * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3672  */
3673 enum vxge_hw_status
3674 __vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3675                               u32 rts_table, u32 offset, u64 steer_data0,
3676                               u64 steer_data1)
3677 {
3678         u64 data0, data1 = 0, steer_ctrl = 0;
3679         enum vxge_hw_status status;
3680
3681         if (vp == NULL) {
3682                 status = VXGE_HW_ERR_INVALID_HANDLE;
3683                 goto exit;
3684         }
3685
3686         data0 = steer_data0;
3687
3688         if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3689             (rts_table ==
3690              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3691                 data1 = steer_data1;
3692
3693         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3694                                       &data0, &data1, &steer_ctrl);
3695 exit:
3696         return status;
3697 }
3698
3699 /*
3700  * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3701  */
3702 enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3703                         struct __vxge_hw_vpath_handle *vp,
3704                         enum vxge_hw_rth_algoritms algorithm,
3705                         struct vxge_hw_rth_hash_types *hash_type,
3706                         u16 bucket_size)
3707 {
3708         u64 data0, data1;
3709         enum vxge_hw_status status = VXGE_HW_OK;
3710
3711         if (vp == NULL) {
3712                 status = VXGE_HW_ERR_INVALID_HANDLE;
3713                 goto exit;
3714         }
3715
3716         status = __vxge_hw_vpath_rts_table_get(vp,
3717                      VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3718                      VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3719                         0, &data0, &data1);
3720         if (status != VXGE_HW_OK)
3721                 goto exit;
3722
3723         data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3724                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3725
3726         data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3727         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3728         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3729
3730         if (hash_type->hash_type_tcpipv4_en)
3731                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3732
3733         if (hash_type->hash_type_ipv4_en)
3734                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3735
3736         if (hash_type->hash_type_tcpipv6_en)
3737                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3738
3739         if (hash_type->hash_type_ipv6_en)
3740                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3741
3742         if (hash_type->hash_type_tcpipv6ex_en)
3743                 data0 |=
3744                 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3745
3746         if (hash_type->hash_type_ipv6ex_en)
3747                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3748
3749         if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3750                 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3751         else
3752                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3753
3754         status = __vxge_hw_vpath_rts_table_set(vp,
3755                 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3756                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3757                 0, data0, 0);
3758 exit:
3759         return status;
3760 }
3761
3762 static void
3763 vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3764                                 u16 flag, u8 *itable)
3765 {
3766         switch (flag) {
3767         case 1:
3768                 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3769                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3770                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3771                         itable[j]);
3772                 /* fall through */
3773         case 2:
3774                 *data0 |=
3775                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3776                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3777                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3778                         itable[j]);
3779                 /* fall through */
3780         case 3:
3781                 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3782                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3783                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3784                         itable[j]);
3785                 /* fall through */
3786         case 4:
3787                 *data1 |=
3788                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3789                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3790                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3791                         itable[j]);
3792         default:
3793                 return;
3794         }
3795 }
3796 /*
3797  * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3798  */
3799 enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3800                         struct __vxge_hw_vpath_handle **vpath_handles,
3801                         u32 vpath_count,
3802                         u8 *mtable,
3803                         u8 *itable,
3804                         u32 itable_size)
3805 {
3806         u32 i, j, action, rts_table;
3807         u64 data0;
3808         u64 data1;
3809         u32 max_entries;
3810         enum vxge_hw_status status = VXGE_HW_OK;
3811         struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3812
3813         if (vp == NULL) {
3814                 status = VXGE_HW_ERR_INVALID_HANDLE;
3815                 goto exit;
3816         }
3817
3818         max_entries = (((u32)1) << itable_size);
3819
3820         if (vp->vpath->hldev->config.rth_it_type
3821                                 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3822                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3823                 rts_table =
3824                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3825
3826                 for (j = 0; j < max_entries; j++) {
3827
3828                         data1 = 0;
3829
3830                         data0 =
3831                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3832                                 itable[j]);
3833
3834                         status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3835                                 action, rts_table, j, data0, data1);
3836
3837                         if (status != VXGE_HW_OK)
3838                                 goto exit;
3839                 }
3840
3841                 for (j = 0; j < max_entries; j++) {
3842
3843                         data1 = 0;
3844
3845                         data0 =
3846                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3847                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3848                                 itable[j]);
3849
3850                         status = __vxge_hw_vpath_rts_table_set(
3851                                 vpath_handles[mtable[itable[j]]], action,
3852                                 rts_table, j, data0, data1);
3853
3854                         if (status != VXGE_HW_OK)
3855                                 goto exit;
3856                 }
3857         } else {
3858                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3859                 rts_table =
3860                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3861                 for (i = 0; i < vpath_count; i++) {
3862
3863                         for (j = 0; j < max_entries;) {
3864
3865                                 data0 = 0;
3866                                 data1 = 0;
3867
3868                                 while (j < max_entries) {
3869                                         if (mtable[itable[j]] != i) {
3870                                                 j++;
3871                                                 continue;
3872                                         }
3873                                         vxge_hw_rts_rth_data0_data1_get(j,
3874                                                 &data0, &data1, 1, itable);
3875                                         j++;
3876                                         break;
3877                                 }
3878
3879                                 while (j < max_entries) {
3880                                         if (mtable[itable[j]] != i) {
3881                                                 j++;
3882                                                 continue;
3883                                         }
3884                                         vxge_hw_rts_rth_data0_data1_get(j,
3885                                                 &data0, &data1, 2, itable);
3886                                         j++;
3887                                         break;
3888                                 }
3889
3890                                 while (j < max_entries) {
3891                                         if (mtable[itable[j]] != i) {
3892                                                 j++;
3893                                                 continue;
3894                                         }
3895                                         vxge_hw_rts_rth_data0_data1_get(j,
3896                                                 &data0, &data1, 3, itable);
3897                                         j++;
3898                                         break;
3899                                 }
3900
3901                                 while (j < max_entries) {
3902                                         if (mtable[itable[j]] != i) {
3903                                                 j++;
3904                                                 continue;
3905                                         }
3906                                         vxge_hw_rts_rth_data0_data1_get(j,
3907                                                 &data0, &data1, 4, itable);
3908                                         j++;
3909                                         break;
3910                                 }
3911
3912                                 if (data0 != 0) {
3913                                         status = __vxge_hw_vpath_rts_table_set(
3914                                                         vpath_handles[i],
3915                                                         action, rts_table,
3916                                                         0, data0, data1);
3917
3918                                         if (status != VXGE_HW_OK)
3919                                                 goto exit;
3920                                 }
3921                         }
3922                 }
3923         }
3924 exit:
3925         return status;
3926 }
3927
3928 /**
3929  * vxge_hw_vpath_check_leak - Check for memory leak
3930  * @ringh: Handle to the ring object used for receive
3931  *
3932  * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3933  * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3934  * Returns: VXGE_HW_FAIL, if leak has occurred.
3935  *
3936  */
3937 enum vxge_hw_status
3938 vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3939 {
3940         enum vxge_hw_status status = VXGE_HW_OK;
3941         u64 rxd_new_count, rxd_spat;
3942
3943         if (ring == NULL)
3944                 return status;
3945
3946         rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3947         rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3948         rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3949
3950         if (rxd_new_count >= rxd_spat)
3951                 status = VXGE_HW_FAIL;
3952
3953         return status;
3954 }
3955
3956 /*
3957  * __vxge_hw_vpath_mgmt_read
3958  * This routine reads the vpath_mgmt registers
3959  */
3960 static enum vxge_hw_status
3961 __vxge_hw_vpath_mgmt_read(
3962         struct __vxge_hw_device *hldev,
3963         struct __vxge_hw_virtualpath *vpath)
3964 {
3965         u32 i, mtu = 0, max_pyld = 0;
3966         u64 val64;
3967
3968         for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3969
3970                 val64 = readq(&vpath->vpmgmt_reg->
3971                                 rxmac_cfg0_port_vpmgmt_clone[i]);
3972                 max_pyld =
3973                         (u32)
3974                         VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3975                         (val64);
3976                 if (mtu < max_pyld)
3977                         mtu = max_pyld;
3978         }
3979
3980         vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3981
3982         val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3983
3984         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3985                 if (val64 & vxge_mBIT(i))
3986                         vpath->vsport_number = i;
3987         }
3988
3989         val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3990
3991         if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3992                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3993         else
3994                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3995
3996         return VXGE_HW_OK;
3997 }
3998
3999 /*
4000  * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
4001  * This routine checks the vpath_rst_in_prog register to see if
4002  * adapter completed the reset process for the vpath
4003  */
4004 static enum vxge_hw_status
4005 __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
4006 {
4007         enum vxge_hw_status status;
4008
4009         status = __vxge_hw_device_register_poll(
4010                         &vpath->hldev->common_reg->vpath_rst_in_prog,
4011                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
4012                                 1 << (16 - vpath->vp_id)),
4013                         vpath->hldev->config.device_poll_millis);
4014
4015         return status;
4016 }
4017
4018 /*
4019  * __vxge_hw_vpath_reset
4020  * This routine resets the vpath on the device
4021  */
4022 static enum vxge_hw_status
4023 __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4024 {
4025         u64 val64;
4026
4027         val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
4028
4029         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4030                                 &hldev->common_reg->cmn_rsthdlr_cfg0);
4031
4032         return VXGE_HW_OK;
4033 }
4034
4035 /*
4036  * __vxge_hw_vpath_sw_reset
4037  * This routine resets the vpath structures
4038  */
4039 static enum vxge_hw_status
4040 __vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4041 {
4042         enum vxge_hw_status status = VXGE_HW_OK;
4043         struct __vxge_hw_virtualpath *vpath;
4044
4045         vpath = &hldev->virtual_paths[vp_id];
4046
4047         if (vpath->ringh) {
4048                 status = __vxge_hw_ring_reset(vpath->ringh);
4049                 if (status != VXGE_HW_OK)
4050                         goto exit;
4051         }
4052
4053         if (vpath->fifoh)
4054                 status = __vxge_hw_fifo_reset(vpath->fifoh);
4055 exit:
4056         return status;
4057 }
4058
4059 /*
4060  * __vxge_hw_vpath_prc_configure
4061  * This routine configures the prc registers of virtual path using the config
4062  * passed
4063  */
4064 static void
4065 __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4066 {
4067         u64 val64;
4068         struct __vxge_hw_virtualpath *vpath;
4069         struct vxge_hw_vp_config *vp_config;
4070         struct vxge_hw_vpath_reg __iomem *vp_reg;
4071
4072         vpath = &hldev->virtual_paths[vp_id];
4073         vp_reg = vpath->vp_reg;
4074         vp_config = vpath->vp_config;
4075
4076         if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
4077                 return;
4078
4079         val64 = readq(&vp_reg->prc_cfg1);
4080         val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
4081         writeq(val64, &vp_reg->prc_cfg1);
4082
4083         val64 = readq(&vpath->vp_reg->prc_cfg6);
4084         val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
4085         writeq(val64, &vpath->vp_reg->prc_cfg6);
4086
4087         val64 = readq(&vp_reg->prc_cfg7);
4088
4089         if (vpath->vp_config->ring.scatter_mode !=
4090                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
4091
4092                 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
4093
4094                 switch (vpath->vp_config->ring.scatter_mode) {
4095                 case VXGE_HW_RING_SCATTER_MODE_A:
4096                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4097                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
4098                         break;
4099                 case VXGE_HW_RING_SCATTER_MODE_B:
4100                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4101                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
4102                         break;
4103                 case VXGE_HW_RING_SCATTER_MODE_C:
4104                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4105                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
4106                         break;
4107                 }
4108         }
4109
4110         writeq(val64, &vp_reg->prc_cfg7);
4111
4112         writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
4113                                 __vxge_hw_ring_first_block_address_get(
4114                                         vpath->ringh) >> 3), &vp_reg->prc_cfg5);
4115
4116         val64 = readq(&vp_reg->prc_cfg4);
4117         val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
4118         val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
4119
4120         val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
4121                         VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
4122
4123         if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
4124                 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
4125         else
4126                 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
4127
4128         writeq(val64, &vp_reg->prc_cfg4);
4129 }
4130
4131 /*
4132  * __vxge_hw_vpath_kdfc_configure
4133  * This routine configures the kdfc registers of virtual path using the
4134  * config passed
4135  */
4136 static enum vxge_hw_status
4137 __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4138 {
4139         u64 val64;
4140         u64 vpath_stride;
4141         enum vxge_hw_status status = VXGE_HW_OK;
4142         struct __vxge_hw_virtualpath *vpath;
4143         struct vxge_hw_vpath_reg __iomem *vp_reg;
4144
4145         vpath = &hldev->virtual_paths[vp_id];
4146         vp_reg = vpath->vp_reg;
4147         status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
4148
4149         if (status != VXGE_HW_OK)
4150                 goto exit;
4151
4152         val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
4153
4154         vpath->max_kdfc_db =
4155                 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
4156                         val64+1)/2;
4157
4158         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4159
4160                 vpath->max_nofl_db = vpath->max_kdfc_db;
4161
4162                 if (vpath->max_nofl_db <
4163                         ((vpath->vp_config->fifo.memblock_size /
4164                         (vpath->vp_config->fifo.max_frags *
4165                         sizeof(struct vxge_hw_fifo_txd))) *
4166                         vpath->vp_config->fifo.fifo_blocks)) {
4167
4168                         return VXGE_HW_BADCFG_FIFO_BLOCKS;
4169                 }
4170                 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
4171                                 (vpath->max_nofl_db*2)-1);
4172         }
4173
4174         writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
4175
4176         writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
4177                 &vp_reg->kdfc_fifo_trpl_ctrl);
4178
4179         val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
4180
4181         val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
4182                    VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
4183
4184         val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
4185                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
4186 #ifndef __BIG_ENDIAN
4187                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
4188 #endif
4189                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
4190
4191         writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
4192         writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
4193         wmb();
4194         vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
4195
4196         vpath->nofl_db =
4197                 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
4198                 (hldev->kdfc + (vp_id *
4199                 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
4200                                         vpath_stride)));
4201 exit:
4202         return status;
4203 }
4204
4205 /*
4206  * __vxge_hw_vpath_mac_configure
4207  * This routine configures the mac of virtual path using the config passed
4208  */
4209 static enum vxge_hw_status
4210 __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4211 {
4212         u64 val64;
4213         struct __vxge_hw_virtualpath *vpath;
4214         struct vxge_hw_vp_config *vp_config;
4215         struct vxge_hw_vpath_reg __iomem *vp_reg;
4216
4217         vpath = &hldev->virtual_paths[vp_id];
4218         vp_reg = vpath->vp_reg;
4219         vp_config = vpath->vp_config;
4220
4221         writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
4222                         vpath->vsport_number), &vp_reg->xmac_vsport_choice);
4223
4224         if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4225
4226                 val64 = readq(&vp_reg->xmac_rpa_vcfg);
4227
4228                 if (vp_config->rpa_strip_vlan_tag !=
4229                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
4230                         if (vp_config->rpa_strip_vlan_tag)
4231                                 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4232                         else
4233                                 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4234                 }
4235
4236                 writeq(val64, &vp_reg->xmac_rpa_vcfg);
4237                 val64 = readq(&vp_reg->rxmac_vcfg0);
4238
4239                 if (vp_config->mtu !=
4240                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
4241                         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4242                         if ((vp_config->mtu  +
4243                                 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
4244                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4245                                         vp_config->mtu  +
4246                                         VXGE_HW_MAC_HEADER_MAX_SIZE);
4247                         else
4248                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4249                                         vpath->max_mtu);
4250                 }
4251
4252                 writeq(val64, &vp_reg->rxmac_vcfg0);
4253
4254                 val64 = readq(&vp_reg->rxmac_vcfg1);
4255
4256                 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
4257                         VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
4258
4259                 if (hldev->config.rth_it_type ==
4260                                 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
4261                         val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
4262                                 0x2) |
4263                                 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
4264                 }
4265
4266                 writeq(val64, &vp_reg->rxmac_vcfg1);
4267         }
4268         return VXGE_HW_OK;
4269 }
4270
4271 /*
4272  * __vxge_hw_vpath_tim_configure
4273  * This routine configures the tim registers of virtual path using the config
4274  * passed
4275  */
4276 static enum vxge_hw_status
4277 __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4278 {
4279         u64 val64;
4280         struct __vxge_hw_virtualpath *vpath;
4281         struct vxge_hw_vpath_reg __iomem *vp_reg;
4282         struct vxge_hw_vp_config *config;
4283
4284         vpath = &hldev->virtual_paths[vp_id];
4285         vp_reg = vpath->vp_reg;
4286         config = vpath->vp_config;
4287
4288         writeq(0, &vp_reg->tim_dest_addr);
4289         writeq(0, &vp_reg->tim_vpath_map);
4290         writeq(0, &vp_reg->tim_bitmap);
4291         writeq(0, &vp_reg->tim_remap);
4292
4293         if (config->ring.enable == VXGE_HW_RING_ENABLE)
4294                 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
4295                         (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4296                         VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
4297
4298         val64 = readq(&vp_reg->tim_pci_cfg);
4299         val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
4300         writeq(val64, &vp_reg->tim_pci_cfg);
4301
4302         if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4303
4304                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4305
4306                 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4307                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4308                                 0x3ffffff);
4309                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4310                                         config->tti.btimer_val);
4311                 }
4312
4313                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4314
4315                 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4316                         if (config->tti.timer_ac_en)
4317                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4318                         else
4319                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4320                 }
4321
4322                 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4323                         if (config->tti.timer_ci_en)
4324                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4325                         else
4326                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4327                 }
4328
4329                 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4330                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4331                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4332                                         config->tti.urange_a);
4333                 }
4334
4335                 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4336                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4337                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4338                                         config->tti.urange_b);
4339                 }
4340
4341                 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4342                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4343                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4344                                         config->tti.urange_c);
4345                 }
4346
4347                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4348                 vpath->tim_tti_cfg1_saved = val64;
4349
4350                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4351
4352                 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4353                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4354                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4355                                                 config->tti.uec_a);
4356                 }
4357
4358                 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4359                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4360                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4361                                                 config->tti.uec_b);
4362                 }
4363
4364                 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4365                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4366                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4367                                                 config->tti.uec_c);
4368                 }
4369
4370                 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4371                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4372                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4373                                                 config->tti.uec_d);
4374                 }
4375
4376                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4377                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4378
4379                 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4380                         if (config->tti.timer_ri_en)
4381                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4382                         else
4383                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4384                 }
4385
4386                 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4387                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4388                                         0x3ffffff);
4389                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4390                                         config->tti.rtimer_val);
4391                 }
4392
4393                 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4394                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4395                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4396                 }
4397
4398                 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4399                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4400                                         0x3ffffff);
4401                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4402                                         config->tti.ltimer_val);
4403                 }
4404
4405                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4406                 vpath->tim_tti_cfg3_saved = val64;
4407         }
4408
4409         if (config->ring.enable == VXGE_HW_RING_ENABLE) {
4410
4411                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4412
4413                 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4414                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4415                                         0x3ffffff);
4416                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4417                                         config->rti.btimer_val);
4418                 }
4419
4420                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4421
4422                 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4423                         if (config->rti.timer_ac_en)
4424                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4425                         else
4426                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4427                 }
4428
4429                 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4430                         if (config->rti.timer_ci_en)
4431                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4432                         else
4433                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4434                 }
4435
4436                 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4437                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4438                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4439                                         config->rti.urange_a);
4440                 }
4441
4442                 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4443                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4444                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4445                                         config->rti.urange_b);
4446                 }
4447
4448                 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4449                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4450                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4451                                         config->rti.urange_c);
4452                 }
4453
4454                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4455                 vpath->tim_rti_cfg1_saved = val64;
4456
4457                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4458
4459                 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4460                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4461                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4462                                                 config->rti.uec_a);
4463                 }
4464
4465                 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4466                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4467                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4468                                                 config->rti.uec_b);
4469                 }
4470
4471                 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4472                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4473                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4474                                                 config->rti.uec_c);
4475                 }
4476
4477                 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4478                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4479                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4480                                                 config->rti.uec_d);
4481                 }
4482
4483                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4484                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4485
4486                 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4487                         if (config->rti.timer_ri_en)
4488                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4489                         else
4490                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4491                 }
4492
4493                 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4494                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4495                                         0x3ffffff);
4496                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4497                                         config->rti.rtimer_val);
4498                 }
4499
4500                 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4501                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4502                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4503                 }
4504
4505                 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4506                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4507                                         0x3ffffff);
4508                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4509                                         config->rti.ltimer_val);
4510                 }
4511
4512                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4513                 vpath->tim_rti_cfg3_saved = val64;
4514         }
4515
4516         val64 = 0;
4517         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4518         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4519         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4520         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4521         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4522         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4523
4524         val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
4525         val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
4526         val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
4527         writeq(val64, &vp_reg->tim_wrkld_clc);
4528
4529         return VXGE_HW_OK;
4530 }
4531
4532 /*
4533  * __vxge_hw_vpath_initialize
4534  * This routine is the final phase of init which initializes the
4535  * registers of the vpath using the configuration passed.
4536  */
4537 static enum vxge_hw_status
4538 __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4539 {
4540         u64 val64;
4541         u32 val32;
4542         enum vxge_hw_status status = VXGE_HW_OK;
4543         struct __vxge_hw_virtualpath *vpath;
4544         struct vxge_hw_vpath_reg __iomem *vp_reg;
4545
4546         vpath = &hldev->virtual_paths[vp_id];
4547
4548         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4549                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4550                 goto exit;
4551         }
4552         vp_reg = vpath->vp_reg;
4553
4554         status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4555         if (status != VXGE_HW_OK)
4556                 goto exit;
4557
4558         status =  __vxge_hw_vpath_mac_configure(hldev, vp_id);
4559         if (status != VXGE_HW_OK)
4560                 goto exit;
4561
4562         status =  __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4563         if (status != VXGE_HW_OK)
4564                 goto exit;
4565
4566         status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4567         if (status != VXGE_HW_OK)
4568                 goto exit;
4569
4570         val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4571
4572         /* Get MRRS value from device control */
4573         status  = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4574         if (status == VXGE_HW_OK) {
4575                 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4576                 val64 &=
4577                     ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4578                 val64 |=
4579                     VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4580
4581                 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4582         }
4583
4584         val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4585         val64 |=
4586             VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4587                     VXGE_HW_MAX_PAYLOAD_SIZE_512);
4588
4589         val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4590         writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4591
4592 exit:
4593         return status;
4594 }
4595
4596 /*
4597  * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4598  * This routine closes all channels it opened and freeup memory
4599  */
4600 static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4601 {
4602         struct __vxge_hw_virtualpath *vpath;
4603
4604         vpath = &hldev->virtual_paths[vp_id];
4605
4606         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4607                 goto exit;
4608
4609         VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4610                 vpath->hldev->tim_int_mask1, vpath->vp_id);
4611         hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4612
4613         /* If the whole struct __vxge_hw_virtualpath is zeroed, nothing will
4614          * work after the interface is brought down.
4615          */
4616         spin_lock(&vpath->lock);
4617         vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4618         spin_unlock(&vpath->lock);
4619
4620         vpath->vpmgmt_reg = NULL;
4621         vpath->nofl_db = NULL;
4622         vpath->max_mtu = 0;
4623         vpath->vsport_number = 0;
4624         vpath->max_kdfc_db = 0;
4625         vpath->max_nofl_db = 0;
4626         vpath->ringh = NULL;
4627         vpath->fifoh = NULL;
4628         memset(&vpath->vpath_handles, 0, sizeof(struct list_head));
4629         vpath->stats_block = NULL;
4630         vpath->hw_stats = NULL;
4631         vpath->hw_stats_sav = NULL;
4632         vpath->sw_stats = NULL;
4633
4634 exit:
4635         return;
4636 }
4637
4638 /*
4639  * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4640  * This routine is the initial phase of init which resets the vpath and
4641  * initializes the software support structures.
4642  */
4643 static enum vxge_hw_status
4644 __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4645                         struct vxge_hw_vp_config *config)
4646 {
4647         struct __vxge_hw_virtualpath *vpath;
4648         enum vxge_hw_status status = VXGE_HW_OK;
4649
4650         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4651                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4652                 goto exit;
4653         }
4654
4655         vpath = &hldev->virtual_paths[vp_id];
4656
4657         spin_lock_init(&vpath->lock);
4658         vpath->vp_id = vp_id;
4659         vpath->vp_open = VXGE_HW_VP_OPEN;
4660         vpath->hldev = hldev;
4661         vpath->vp_config = config;
4662         vpath->vp_reg = hldev->vpath_reg[vp_id];
4663         vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4664
4665         __vxge_hw_vpath_reset(hldev, vp_id);
4666
4667         status = __vxge_hw_vpath_reset_check(vpath);
4668         if (status != VXGE_HW_OK) {
4669                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4670                 goto exit;
4671         }
4672
4673         status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4674         if (status != VXGE_HW_OK) {
4675                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4676                 goto exit;
4677         }
4678
4679         INIT_LIST_HEAD(&vpath->vpath_handles);
4680
4681         vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4682
4683         VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4684                 hldev->tim_int_mask1, vp_id);
4685
4686         status = __vxge_hw_vpath_initialize(hldev, vp_id);
4687         if (status != VXGE_HW_OK)
4688                 __vxge_hw_vp_terminate(hldev, vp_id);
4689 exit:
4690         return status;
4691 }
4692
4693 /*
4694  * vxge_hw_vpath_mtu_set - Set MTU.
4695  * Set new MTU value. Example, to use jumbo frames:
4696  * vxge_hw_vpath_mtu_set(my_device, 9600);
4697  */
4698 enum vxge_hw_status
4699 vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4700 {
4701         u64 val64;
4702         enum vxge_hw_status status = VXGE_HW_OK;
4703         struct __vxge_hw_virtualpath *vpath;
4704
4705         if (vp == NULL) {
4706                 status = VXGE_HW_ERR_INVALID_HANDLE;
4707                 goto exit;
4708         }
4709         vpath = vp->vpath;
4710
4711         new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4712
4713         if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4714                 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4715
4716         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4717
4718         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4719         val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4720
4721         writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4722
4723         vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4724
4725 exit:
4726         return status;
4727 }
4728
4729 /*
4730  * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4731  * Enable the DMA vpath statistics. The function is to be called to re-enable
4732  * the adapter to update stats into the host memory
4733  */
4734 static enum vxge_hw_status
4735 vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4736 {
4737         enum vxge_hw_status status = VXGE_HW_OK;
4738         struct __vxge_hw_virtualpath *vpath;
4739
4740         vpath = vp->vpath;
4741
4742         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4743                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4744                 goto exit;
4745         }
4746
4747         memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4748                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4749
4750         status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4751 exit:
4752         return status;
4753 }
4754
4755 /*
4756  * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
4757  * This function allocates a block from block pool or from the system
4758  */
4759 static struct __vxge_hw_blockpool_entry *
4760 __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
4761 {
4762         struct __vxge_hw_blockpool_entry *entry = NULL;
4763         struct __vxge_hw_blockpool  *blockpool;
4764
4765         blockpool = &devh->block_pool;
4766
4767         if (size == blockpool->block_size) {
4768
4769                 if (!list_empty(&blockpool->free_block_list))
4770                         entry = (struct __vxge_hw_blockpool_entry *)
4771                                 list_first_entry(&blockpool->free_block_list,
4772                                         struct __vxge_hw_blockpool_entry,
4773                                         item);
4774
4775                 if (entry != NULL) {
4776                         list_del(&entry->item);
4777                         blockpool->pool_size--;
4778                 }
4779         }
4780
4781         if (entry != NULL)
4782                 __vxge_hw_blockpool_blocks_add(blockpool);
4783
4784         return entry;
4785 }
4786
4787 /*
4788  * vxge_hw_vpath_open - Open a virtual path on a given adapter
4789  * This function is used to open access to virtual path of an
4790  * adapter for offload, GRO operations. This function returns
4791  * synchronously.
4792  */
4793 enum vxge_hw_status
4794 vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4795                    struct vxge_hw_vpath_attr *attr,
4796                    struct __vxge_hw_vpath_handle **vpath_handle)
4797 {
4798         struct __vxge_hw_virtualpath *vpath;
4799         struct __vxge_hw_vpath_handle *vp;
4800         enum vxge_hw_status status;
4801
4802         vpath = &hldev->virtual_paths[attr->vp_id];
4803
4804         if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4805                 status = VXGE_HW_ERR_INVALID_STATE;
4806                 goto vpath_open_exit1;
4807         }
4808
4809         status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4810                         &hldev->config.vp_config[attr->vp_id]);
4811         if (status != VXGE_HW_OK)
4812                 goto vpath_open_exit1;
4813
4814         vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
4815         if (vp == NULL) {
4816                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4817                 goto vpath_open_exit2;
4818         }
4819
4820         vp->vpath = vpath;
4821
4822         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4823                 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4824                 if (status != VXGE_HW_OK)
4825                         goto vpath_open_exit6;
4826         }
4827
4828         if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4829                 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4830                 if (status != VXGE_HW_OK)
4831                         goto vpath_open_exit7;
4832
4833                 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4834         }
4835
4836         vpath->fifoh->tx_intr_num =
4837                 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP)  +
4838                         VXGE_HW_VPATH_INTR_TX;
4839
4840         vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4841                                 VXGE_HW_BLOCK_SIZE);
4842         if (vpath->stats_block == NULL) {
4843                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4844                 goto vpath_open_exit8;
4845         }
4846
4847         vpath->hw_stats = vpath->stats_block->memblock;
4848         memset(vpath->hw_stats, 0,
4849                 sizeof(struct vxge_hw_vpath_stats_hw_info));
4850
4851         hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4852                                                 vpath->hw_stats;
4853
4854         vpath->hw_stats_sav =
4855                 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4856         memset(vpath->hw_stats_sav, 0,
4857                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4858
4859         writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4860
4861         status = vxge_hw_vpath_stats_enable(vp);
4862         if (status != VXGE_HW_OK)
4863                 goto vpath_open_exit8;
4864
4865         list_add(&vp->item, &vpath->vpath_handles);
4866
4867         hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4868
4869         *vpath_handle = vp;
4870
4871         attr->fifo_attr.userdata = vpath->fifoh;
4872         attr->ring_attr.userdata = vpath->ringh;
4873
4874         return VXGE_HW_OK;
4875
4876 vpath_open_exit8:
4877         if (vpath->ringh != NULL)
4878                 __vxge_hw_ring_delete(vp);
4879 vpath_open_exit7:
4880         if (vpath->fifoh != NULL)
4881                 __vxge_hw_fifo_delete(vp);
4882 vpath_open_exit6:
4883         vfree(vp);
4884 vpath_open_exit2:
4885         __vxge_hw_vp_terminate(hldev, attr->vp_id);
4886 vpath_open_exit1:
4887
4888         return status;
4889 }
4890
4891 /**
4892  * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4893  * (vpath) open
4894  * @vp: Handle got from previous vpath open
4895  *
4896  * This function is used to close access to virtual path opened
4897  * earlier.
4898  */
4899 void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4900 {
4901         struct __vxge_hw_virtualpath *vpath = vp->vpath;
4902         struct __vxge_hw_ring *ring = vpath->ringh;
4903         struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
4904         u64 new_count, val64, val164;
4905
4906         if (vdev->titan1) {
4907                 new_count = readq(&vpath->vp_reg->rxdmem_size);
4908                 new_count &= 0x1fff;
4909         } else
4910                 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
4911
4912         val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
4913
4914         writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4915                 &vpath->vp_reg->prc_rxd_doorbell);
4916         readl(&vpath->vp_reg->prc_rxd_doorbell);
4917
4918         val164 /= 2;
4919         val64 = readq(&vpath->vp_reg->prc_cfg6);
4920         val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4921         val64 &= 0x1ff;
4922
4923         /*
4924          * Each RxD is of 4 qwords
4925          */
4926         new_count -= (val64 + 1);
4927         val64 = min(val164, new_count) / 4;
4928
4929         ring->rxds_limit = min(ring->rxds_limit, val64);
4930         if (ring->rxds_limit < 4)
4931                 ring->rxds_limit = 4;
4932 }
4933
4934 /*
4935  * __vxge_hw_blockpool_block_free - Frees a block from block pool
4936  * @devh: Hal device
4937  * @entry: Entry of block to be freed
4938  *
4939  * This function frees a block from block pool
4940  */
4941 static void
4942 __vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
4943                                struct __vxge_hw_blockpool_entry *entry)
4944 {
4945         struct __vxge_hw_blockpool  *blockpool;
4946
4947         blockpool = &devh->block_pool;
4948
4949         if (entry->length == blockpool->block_size) {
4950                 list_add(&entry->item, &blockpool->free_block_list);
4951                 blockpool->pool_size++;
4952         }
4953
4954         __vxge_hw_blockpool_blocks_remove(blockpool);
4955 }
4956
4957 /*
4958  * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4959  * This function is used to close access to virtual path opened
4960  * earlier.
4961  */
4962 enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4963 {
4964         struct __vxge_hw_virtualpath *vpath = NULL;
4965         struct __vxge_hw_device *devh = NULL;
4966         u32 vp_id = vp->vpath->vp_id;
4967         u32 is_empty = TRUE;
4968         enum vxge_hw_status status = VXGE_HW_OK;
4969
4970         vpath = vp->vpath;
4971         devh = vpath->hldev;
4972
4973         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4974                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4975                 goto vpath_close_exit;
4976         }
4977
4978         list_del(&vp->item);
4979
4980         if (!list_empty(&vpath->vpath_handles)) {
4981                 list_add(&vp->item, &vpath->vpath_handles);
4982                 is_empty = FALSE;
4983         }
4984
4985         if (!is_empty) {
4986                 status = VXGE_HW_FAIL;
4987                 goto vpath_close_exit;
4988         }
4989
4990         devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4991
4992         if (vpath->ringh != NULL)
4993                 __vxge_hw_ring_delete(vp);
4994
4995         if (vpath->fifoh != NULL)
4996                 __vxge_hw_fifo_delete(vp);
4997
4998         if (vpath->stats_block != NULL)
4999                 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
5000
5001         vfree(vp);
5002
5003         __vxge_hw_vp_terminate(devh, vp_id);
5004
5005 vpath_close_exit:
5006         return status;
5007 }
5008
5009 /*
5010  * vxge_hw_vpath_reset - Resets vpath
5011  * This function is used to request a reset of vpath
5012  */
5013 enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
5014 {
5015         enum vxge_hw_status status;
5016         u32 vp_id;
5017         struct __vxge_hw_virtualpath *vpath = vp->vpath;
5018
5019         vp_id = vpath->vp_id;
5020
5021         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5022                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5023                 goto exit;
5024         }
5025
5026         status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
5027         if (status == VXGE_HW_OK)
5028                 vpath->sw_stats->soft_reset_cnt++;
5029 exit:
5030         return status;
5031 }
5032
5033 /*
5034  * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
5035  * This function poll's for the vpath reset completion and re initializes
5036  * the vpath.
5037  */
5038 enum vxge_hw_status
5039 vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
5040 {
5041         struct __vxge_hw_virtualpath *vpath = NULL;
5042         enum vxge_hw_status status;
5043         struct __vxge_hw_device *hldev;
5044         u32 vp_id;
5045
5046         vp_id = vp->vpath->vp_id;
5047         vpath = vp->vpath;
5048         hldev = vpath->hldev;
5049
5050         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5051                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5052                 goto exit;
5053         }
5054
5055         status = __vxge_hw_vpath_reset_check(vpath);
5056         if (status != VXGE_HW_OK)
5057                 goto exit;
5058
5059         status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
5060         if (status != VXGE_HW_OK)
5061                 goto exit;
5062
5063         status = __vxge_hw_vpath_initialize(hldev, vp_id);
5064         if (status != VXGE_HW_OK)
5065                 goto exit;
5066
5067         if (vpath->ringh != NULL)
5068                 __vxge_hw_vpath_prc_configure(hldev, vp_id);
5069
5070         memset(vpath->hw_stats, 0,
5071                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5072
5073         memset(vpath->hw_stats_sav, 0,
5074                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5075
5076         writeq(vpath->stats_block->dma_addr,
5077                 &vpath->vp_reg->stats_cfg);
5078
5079         status = vxge_hw_vpath_stats_enable(vp);
5080
5081 exit:
5082         return status;
5083 }
5084
5085 /*
5086  * vxge_hw_vpath_enable - Enable vpath.
5087  * This routine clears the vpath reset thereby enabling a vpath
5088  * to start forwarding frames and generating interrupts.
5089  */
5090 void
5091 vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
5092 {
5093         struct __vxge_hw_device *hldev;
5094         u64 val64;
5095
5096         hldev = vp->vpath->hldev;
5097
5098         val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
5099                 1 << (16 - vp->vpath->vp_id));
5100
5101         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
5102                 &hldev->common_reg->cmn_rsthdlr_cfg1);
5103 }