drivers/net/ethernet/neterion/vxge/vxge-traffic.c

   1 /******************************************************************************
   2  * This software may be used and distributed according to the terms of
   3  * the GNU General Public License (GPL), incorporated herein by reference.
   4  * Drivers based on or derived from this code fall under the GPL and must
   5  * retain the authorship, copyright and license notice.  This file is not
   6  * a complete program and may only be used when the entire operating
   7  * system is licensed under the GPL.
   8  * See the file COPYING in this distribution for more information.
   9  *
  10  * vxge-traffic.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
  11  *                 Virtualized Server Adapter.
  12  * Copyright(c) 2002-2010 Exar Corp.
  13  ******************************************************************************/
  14 #include <linux/etherdevice.h>
  15 #include <linux/prefetch.h>
  16
  17 #include "vxge-traffic.h"
  18 #include "vxge-config.h"
  19 #include "vxge-main.h"
  20
  21 /*
  22  * vxge_hw_vpath_intr_enable - Enable vpath interrupts.
  23  * @vp: Virtual Path handle.
  24  *
  25  * Enable vpath interrupts. The function is to be executed the last in
  26  * vpath initialization sequence.
  27  *
  28  * See also: vxge_hw_vpath_intr_disable()
  29  */
  30 enum vxge_hw_status vxge_hw_vpath_intr_enable(struct __vxge_hw_vpath_handle *vp)
  31 {
  32         struct __vxge_hw_virtualpath *vpath;
  33         struct vxge_hw_vpath_reg __iomem *vp_reg;
  34         enum vxge_hw_status status = VXGE_HW_OK;
  35         if (vp == NULL) {
  36                 status = VXGE_HW_ERR_INVALID_HANDLE;
  37                 goto exit;
  38         }
  39
  40         vpath = vp->vpath;
  41
  42         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
  43                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
  44                 goto exit;
  45         }
  46
  47         vp_reg = vpath->vp_reg;
  48
  49         writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg);
  50
  51         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  52                         &vp_reg->general_errors_reg);
  53
  54         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  55                         &vp_reg->pci_config_errors_reg);
  56
  57         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  58                         &vp_reg->mrpcim_to_vpath_alarm_reg);
  59
  60         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  61                         &vp_reg->srpcim_to_vpath_alarm_reg);
  62
  63         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  64                         &vp_reg->vpath_ppif_int_status);
  65
  66         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  67                         &vp_reg->srpcim_msg_to_vpath_reg);
  68
  69         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  70                         &vp_reg->vpath_pcipif_int_status);
  71
  72         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  73                         &vp_reg->prc_alarm_reg);
  74
  75         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  76                         &vp_reg->wrdma_alarm_status);
  77
  78         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  79                         &vp_reg->asic_ntwk_vp_err_reg);
  80
  81         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  82                         &vp_reg->xgmac_vp_int_status);
  83
  84         readq(&vp_reg->vpath_general_int_status);
  85
  86         /* Mask unwanted interrupts */
  87
  88         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  89                         &vp_reg->vpath_pcipif_int_mask);
  90
  91         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  92                         &vp_reg->srpcim_msg_to_vpath_mask);
  93
  94         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  95                         &vp_reg->srpcim_to_vpath_alarm_mask);
  96
  97         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  98                         &vp_reg->mrpcim_to_vpath_alarm_mask);
  99
 100         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 101                         &vp_reg->pci_config_errors_mask);
 102
 103         /* Unmask the individual interrupts */
 104
 105         writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW|
 106                 VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW|
 107                 VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ|
 108                 VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32),
 109                 &vp_reg->general_errors_mask);
 110
 111         __vxge_hw_pio_mem_write32_upper(
 112                 (u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR|
 113                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR|
 114                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON|
 115                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON|
 116                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR|
 117                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR), 0, 32),
 118                 &vp_reg->kdfcctl_errors_mask);
 119
 120         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask);
 121
 122         __vxge_hw_pio_mem_write32_upper(
 123                 (u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32),
 124                 &vp_reg->prc_alarm_mask);
 125
 126         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask);
 127         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask);
 128
 129         if (vpath->hldev->first_vp_id != vpath->vp_id)
 130                 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 131                         &vp_reg->asic_ntwk_vp_err_mask);
 132         else
 133                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn((
 134                 VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT |
 135                 VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK), 0, 32),
 136                 &vp_reg->asic_ntwk_vp_err_mask);
 137
 138         __vxge_hw_pio_mem_write32_upper(0,
 139                 &vp_reg->vpath_general_int_mask);
 140 exit:
 141         return status;
 142
 143 }
 144
 145 /*
 146  * vxge_hw_vpath_intr_disable - Disable vpath interrupts.
 147  * @vp: Virtual Path handle.
 148  *
 149  * Disable vpath interrupts. The function is to be executed the last in
 150  * vpath initialization sequence.
 151  *
 152  * See also: vxge_hw_vpath_intr_enable()
 153  */
 154 enum vxge_hw_status vxge_hw_vpath_intr_disable(
 155                         struct __vxge_hw_vpath_handle *vp)
 156 {
 157         struct __vxge_hw_virtualpath *vpath;
 158         enum vxge_hw_status status = VXGE_HW_OK;
 159         struct vxge_hw_vpath_reg __iomem *vp_reg;
 160         if (vp == NULL) {
 161                 status = VXGE_HW_ERR_INVALID_HANDLE;
 162                 goto exit;
 163         }
 164
 165         vpath = vp->vpath;
 166
 167         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
 168                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
 169                 goto exit;
 170         }
 171         vp_reg = vpath->vp_reg;
 172
 173         __vxge_hw_pio_mem_write32_upper(
 174                 (u32)VXGE_HW_INTR_MASK_ALL,
 175                 &vp_reg->vpath_general_int_mask);
 176
 177         writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask);
 178
 179         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 180                         &vp_reg->general_errors_mask);
 181
 182         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 183                         &vp_reg->pci_config_errors_mask);
 184
 185         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 186                         &vp_reg->mrpcim_to_vpath_alarm_mask);
 187
 188         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 189                         &vp_reg->srpcim_to_vpath_alarm_mask);
 190
 191         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 192                         &vp_reg->vpath_ppif_int_mask);
 193
 194         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 195                         &vp_reg->srpcim_msg_to_vpath_mask);
 196
 197         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 198                         &vp_reg->vpath_pcipif_int_mask);
 199
 200         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 201                         &vp_reg->wrdma_alarm_mask);
 202
 203         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 204                         &vp_reg->prc_alarm_mask);
 205
 206         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 207                         &vp_reg->xgmac_vp_int_mask);
 208
 209         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 210                         &vp_reg->asic_ntwk_vp_err_mask);
 211
 212 exit:
 213         return status;
 214 }
 215
 216 void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo)
 217 {
 218         struct vxge_hw_vpath_reg __iomem *vp_reg;
 219         struct vxge_hw_vp_config *config;
 220         u64 val64;
 221
 222         if (fifo->config->enable != VXGE_HW_FIFO_ENABLE)
 223                 return;
 224
 225         vp_reg = fifo->vp_reg;
 226         config = container_of(fifo->config, struct vxge_hw_vp_config, fifo);
 227
 228         if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
 229                 config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
 230                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
 231                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
 232                 fifo->tim_tti_cfg1_saved = val64;
 233                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
 234         }
 235 }
 236
 237 void vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring)
 238 {
 239         u64 val64 = ring->tim_rti_cfg1_saved;
 240
 241         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
 242         ring->tim_rti_cfg1_saved = val64;
 243         writeq(val64, &ring->vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
 244 }
 245
 246 void vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo)
 247 {
 248         u64 val64 = fifo->tim_tti_cfg3_saved;
 249         u64 timer = (fifo->rtimer * 1000) / 272;
 250
 251         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
 252         if (timer)
 253                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
 254                         VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5);
 255
 256         writeq(val64, &fifo->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
 257         /* tti_cfg3_saved is not updated again because it is
 258          * initialized at one place only - init time.
 259          */
 260 }
 261
 262 void vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring)
 263 {
 264         u64 val64 = ring->tim_rti_cfg3_saved;
 265         u64 timer = (ring->rtimer * 1000) / 272;
 266
 267         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
 268         if (timer)
 269                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
 270                         VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4);
 271
 272         writeq(val64, &ring->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
 273         /* rti_cfg3_saved is not updated again because it is
 274          * initialized at one place only - init time.
 275          */
 276 }
 277
 278 /**
 279  * vxge_hw_channel_msix_mask - Mask MSIX Vector.
 280  * @channeh: Channel for rx or tx handle
 281  * @msix_id:  MSIX ID
 282  *
 283  * The function masks the msix interrupt for the given msix_id
 284  *
 285  * Returns: 0
 286  */
 287 void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id)
 288 {
 289
 290         __vxge_hw_pio_mem_write32_upper(
 291                 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
 292                 &channel->common_reg->set_msix_mask_vect[msix_id%4]);
 293 }
 294
 295 /**
 296  * vxge_hw_channel_msix_unmask - Unmask the MSIX Vector.
 297  * @channeh: Channel for rx or tx handle
 298  * @msix_id:  MSI ID
 299  *
 300  * The function unmasks the msix interrupt for the given msix_id
 301  *
 302  * Returns: 0
 303  */
 304 void
 305 vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
 306 {
 307
 308         __vxge_hw_pio_mem_write32_upper(
 309                 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
 310                 &channel->common_reg->clear_msix_mask_vect[msix_id%4]);
 311 }
 312
 313 /**
 314  * vxge_hw_channel_msix_clear - Unmask the MSIX Vector.
 315  * @channel: Channel for rx or tx handle
 316  * @msix_id:  MSI ID
 317  *
 318  * The function unmasks the msix interrupt for the given msix_id
 319  * if configured in MSIX oneshot mode
 320  *
 321  * Returns: 0
 322  */
 323 void vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channel, int msix_id)
 324 {
 325         __vxge_hw_pio_mem_write32_upper(
 326                 (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
 327                 &channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
 328 }
 329
 330 /**
 331  * vxge_hw_device_set_intr_type - Updates the configuration
 332  *              with new interrupt type.
 333  * @hldev: HW device handle.
 334  * @intr_mode: New interrupt type
 335  */
 336 u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *hldev, u32 intr_mode)
 337 {
 338
 339         if ((intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
 340            (intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
 341            (intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
 342            (intr_mode != VXGE_HW_INTR_MODE_DEF))
 343                 intr_mode = VXGE_HW_INTR_MODE_IRQLINE;
 344
 345         hldev->config.intr_mode = intr_mode;
 346         return intr_mode;
 347 }
 348
 349 /**
 350  * vxge_hw_device_intr_enable - Enable interrupts.
 351  * @hldev: HW device handle.
 352  * @op: One of the enum vxge_hw_device_intr enumerated values specifying
 353  *      the type(s) of interrupts to enable.
 354  *
 355  * Enable Titan interrupts. The function is to be executed the last in
 356  * Titan initialization sequence.
 357  *
 358  * See also: vxge_hw_device_intr_disable()
 359  */
 360 void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev)
 361 {
 362         u32 i;
 363         u64 val64;
 364         u32 val32;
 365
 366         vxge_hw_device_mask_all(hldev);
 367
 368         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 369
 370                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 371                         continue;
 372
 373                 vxge_hw_vpath_intr_enable(
 374                         VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
 375         }
 376
 377         if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE) {
 378                 val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
 379                         hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
 380
 381                 if (val64 != 0) {
 382                         writeq(val64, &hldev->common_reg->tim_int_status0);
 383
 384                         writeq(~val64, &hldev->common_reg->tim_int_mask0);
 385                 }
 386
 387                 val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
 388                         hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX];
 389
 390                 if (val32 != 0) {
 391                         __vxge_hw_pio_mem_write32_upper(val32,
 392                                         &hldev->common_reg->tim_int_status1);
 393
 394                         __vxge_hw_pio_mem_write32_upper(~val32,
 395                                         &hldev->common_reg->tim_int_mask1);
 396                 }
 397         }
 398
 399         val64 = readq(&hldev->common_reg->titan_general_int_status);
 400
 401         vxge_hw_device_unmask_all(hldev);
 402 }
 403
 404 /**
 405  * vxge_hw_device_intr_disable - Disable Titan interrupts.
 406  * @hldev: HW device handle.
 407  * @op: One of the enum vxge_hw_device_intr enumerated values specifying
 408  *      the type(s) of interrupts to disable.
 409  *
 410  * Disable Titan interrupts.
 411  *
 412  * See also: vxge_hw_device_intr_enable()
 413  */
 414 void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev)
 415 {
 416         u32 i;
 417
 418         vxge_hw_device_mask_all(hldev);
 419
 420         /* mask all the tim interrupts */
 421         writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
 422         __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32,
 423                 &hldev->common_reg->tim_int_mask1);
 424
 425         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 426
 427                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 428                         continue;
 429
 430                 vxge_hw_vpath_intr_disable(
 431                         VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
 432         }
 433 }
 434
 435 /**
 436  * vxge_hw_device_mask_all - Mask all device interrupts.
 437  * @hldev: HW device handle.
 438  *
 439  * Mask all device interrupts.
 440  *
 441  * See also: vxge_hw_device_unmask_all()
 442  */
 443 void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
 444 {
 445         u64 val64;
 446
 447         val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM |
 448                 VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
 449
 450         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
 451                                 &hldev->common_reg->titan_mask_all_int);
 452 }
 453
 454 /**
 455  * vxge_hw_device_unmask_all - Unmask all device interrupts.
 456  * @hldev: HW device handle.
 457  *
 458  * Unmask all device interrupts.
 459  *
 460  * See also: vxge_hw_device_mask_all()
 461  */
 462 void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev)
 463 {
 464         u64 val64 = 0;
 465
 466         if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE)
 467                 val64 =  VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
 468
 469         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
 470                         &hldev->common_reg->titan_mask_all_int);
 471 }
 472
 473 /**
 474  * vxge_hw_device_flush_io - Flush io writes.
 475  * @hldev: HW device handle.
 476  *
 477  * The function performs a read operation to flush io writes.
 478  *
 479  * Returns: void
 480  */
 481 void vxge_hw_device_flush_io(struct __vxge_hw_device *hldev)
 482 {
 483         readl(&hldev->common_reg->titan_general_int_status);
 484 }
 485
 486 /**
 487  * __vxge_hw_device_handle_error - Handle error
 488  * @hldev: HW device
 489  * @vp_id: Vpath Id
 490  * @type: Error type. Please see enum vxge_hw_event{}
 491  *
 492  * Handle error.
 493  */
 494 static enum vxge_hw_status
 495 __vxge_hw_device_handle_error(struct __vxge_hw_device *hldev, u32 vp_id,
 496                               enum vxge_hw_event type)
 497 {
 498         switch (type) {
 499         case VXGE_HW_EVENT_UNKNOWN:
 500                 break;
 501         case VXGE_HW_EVENT_RESET_START:
 502         case VXGE_HW_EVENT_RESET_COMPLETE:
 503         case VXGE_HW_EVENT_LINK_DOWN:
 504         case VXGE_HW_EVENT_LINK_UP:
 505                 goto out;
 506         case VXGE_HW_EVENT_ALARM_CLEARED:
 507                 goto out;
 508         case VXGE_HW_EVENT_ECCERR:
 509         case VXGE_HW_EVENT_MRPCIM_ECCERR:
 510                 goto out;
 511         case VXGE_HW_EVENT_FIFO_ERR:
 512         case VXGE_HW_EVENT_VPATH_ERR:
 513         case VXGE_HW_EVENT_CRITICAL_ERR:
 514         case VXGE_HW_EVENT_SERR:
 515                 break;
 516         case VXGE_HW_EVENT_SRPCIM_SERR:
 517         case VXGE_HW_EVENT_MRPCIM_SERR:
 518                 goto out;
 519         case VXGE_HW_EVENT_SLOT_FREEZE:
 520                 break;
 521         default:
 522                 vxge_assert(0);
 523                 goto out;
 524         }
 525
 526         /* notify driver */
 527         if (hldev->uld_callbacks->crit_err)
 528                 hldev->uld_callbacks->crit_err(hldev,
 529                         type, vp_id);
 530 out:
 531
 532         return VXGE_HW_OK;
 533 }
 534
 535 /*
 536  * __vxge_hw_device_handle_link_down_ind
 537  * @hldev: HW device handle.
 538  *
 539  * Link down indication handler. The function is invoked by HW when
 540  * Titan indicates that the link is down.
 541  */
 542 static enum vxge_hw_status
 543 __vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev)
 544 {
 545         /*
 546          * If the previous link state is not down, return.
 547          */
 548         if (hldev->link_state == VXGE_HW_LINK_DOWN)
 549                 goto exit;
 550
 551         hldev->link_state = VXGE_HW_LINK_DOWN;
 552
 553         /* notify driver */
 554         if (hldev->uld_callbacks->link_down)
 555                 hldev->uld_callbacks->link_down(hldev);
 556 exit:
 557         return VXGE_HW_OK;
 558 }
 559
 560 /*
 561  * __vxge_hw_device_handle_link_up_ind
 562  * @hldev: HW device handle.
 563  *
 564  * Link up indication handler. The function is invoked by HW when
 565  * Titan indicates that the link is up for programmable amount of time.
 566  */
 567 static enum vxge_hw_status
 568 __vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev)
 569 {
 570         /*
 571          * If the previous link state is not down, return.
 572          */
 573         if (hldev->link_state == VXGE_HW_LINK_UP)
 574                 goto exit;
 575
 576         hldev->link_state = VXGE_HW_LINK_UP;
 577
 578         /* notify driver */
 579         if (hldev->uld_callbacks->link_up)
 580                 hldev->uld_callbacks->link_up(hldev);
 581 exit:
 582         return VXGE_HW_OK;
 583 }
 584
 585 /*
 586  * __vxge_hw_vpath_alarm_process - Process Alarms.
 587  * @vpath: Virtual Path.
 588  * @skip_alarms: Do not clear the alarms
 589  *
 590  * Process vpath alarms.
 591  *
 592  */
 593 static enum vxge_hw_status
 594 __vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath,
 595                               u32 skip_alarms)
 596 {
 597         u64 val64;
 598         u64 alarm_status;
 599         u64 pic_status;
 600         struct __vxge_hw_device *hldev = NULL;
 601         enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN;
 602         u64 mask64;
 603         struct vxge_hw_vpath_stats_sw_info *sw_stats;
 604         struct vxge_hw_vpath_reg __iomem *vp_reg;
 605
 606         if (vpath == NULL) {
 607                 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
 608                         alarm_event);
 609                 goto out2;
 610         }
 611
 612         hldev = vpath->hldev;
 613         vp_reg = vpath->vp_reg;
 614         alarm_status = readq(&vp_reg->vpath_general_int_status);
 615
 616         if (alarm_status == VXGE_HW_ALL_FOXES) {
 617                 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_SLOT_FREEZE,
 618                         alarm_event);
 619                 goto out;
 620         }
 621
 622         sw_stats = vpath->sw_stats;
 623
 624         if (alarm_status & ~(
 625                 VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
 626                 VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
 627                 VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
 628                 VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
 629                 sw_stats->error_stats.unknown_alarms++;
 630
 631                 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
 632                         alarm_event);
 633                 goto out;
 634         }
 635
 636         if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
 637
 638                 val64 = readq(&vp_reg->xgmac_vp_int_status);
 639
 640                 if (val64 &
 641                 VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
 642
 643                         val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
 644
 645                         if (((val64 &
 646                               VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
 647                              (!(val64 &
 648                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
 649                             ((val64 &
 650                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) &&
 651                              (!(val64 &
 652                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
 653                                      ))) {
 654                                 sw_stats->error_stats.network_sustained_fault++;
 655
 656                                 writeq(
 657                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
 658                                         &vp_reg->asic_ntwk_vp_err_mask);
 659
 660                                 __vxge_hw_device_handle_link_down_ind(hldev);
 661                                 alarm_event = VXGE_HW_SET_LEVEL(
 662                                         VXGE_HW_EVENT_LINK_DOWN, alarm_event);
 663                         }
 664
 665                         if (((val64 &
 666                               VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
 667                              (!(val64 &
 668                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
 669                             ((val64 &
 670                               VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) &&
 671                              (!(val64 &
 672                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
 673                                      ))) {
 674
 675                                 sw_stats->error_stats.network_sustained_ok++;
 676
 677                                 writeq(
 678                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
 679                                         &vp_reg->asic_ntwk_vp_err_mask);
 680
 681                                 __vxge_hw_device_handle_link_up_ind(hldev);
 682                                 alarm_event = VXGE_HW_SET_LEVEL(
 683                                         VXGE_HW_EVENT_LINK_UP, alarm_event);
 684                         }
 685
 686                         writeq(VXGE_HW_INTR_MASK_ALL,
 687                                 &vp_reg->asic_ntwk_vp_err_reg);
 688
 689                         alarm_event = VXGE_HW_SET_LEVEL(
 690                                 VXGE_HW_EVENT_ALARM_CLEARED, alarm_event);
 691
 692                         if (skip_alarms)
 693                                 return VXGE_HW_OK;
 694                 }
 695         }
 696
 697         if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) {
 698
 699                 pic_status = readq(&vp_reg->vpath_ppif_int_status);
 700
 701                 if (pic_status &
 702                     VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) {
 703
 704                         val64 = readq(&vp_reg->general_errors_reg);
 705                         mask64 = readq(&vp_reg->general_errors_mask);
 706
 707                         if ((val64 &
 708                                 VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) &
 709                                 ~mask64) {
 710                                 sw_stats->error_stats.ini_serr_det++;
 711
 712                                 alarm_event = VXGE_HW_SET_LEVEL(
 713                                         VXGE_HW_EVENT_SERR, alarm_event);
 714                         }
 715
 716                         if ((val64 &
 717                             VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) &
 718                                 ~mask64) {
 719                                 sw_stats->error_stats.dblgen_fifo0_overflow++;
 720
 721                                 alarm_event = VXGE_HW_SET_LEVEL(
 722                                         VXGE_HW_EVENT_FIFO_ERR, alarm_event);
 723                         }
 724
 725                         if ((val64 &
 726                             VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) &
 727                                 ~mask64)
 728                                 sw_stats->error_stats.statsb_pif_chain_error++;
 729
 730                         if ((val64 &
 731                            VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) &
 732                                 ~mask64)
 733                                 sw_stats->error_stats.statsb_drop_timeout++;
 734
 735                         if ((val64 &
 736                                 VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) &
 737                                 ~mask64)
 738                                 sw_stats->error_stats.target_illegal_access++;
 739
 740                         if (!skip_alarms) {
 741                                 writeq(VXGE_HW_INTR_MASK_ALL,
 742                                         &vp_reg->general_errors_reg);
 743                                 alarm_event = VXGE_HW_SET_LEVEL(
 744                                         VXGE_HW_EVENT_ALARM_CLEARED,
 745                                         alarm_event);
 746                         }
 747                 }
 748
 749                 if (pic_status &
 750                     VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) {
 751
 752                         val64 = readq(&vp_reg->kdfcctl_errors_reg);
 753                         mask64 = readq(&vp_reg->kdfcctl_errors_mask);
 754
 755                         if ((val64 &
 756                             VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) &
 757                                 ~mask64) {
 758                                 sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
 759
 760                                 alarm_event = VXGE_HW_SET_LEVEL(
 761                                         VXGE_HW_EVENT_FIFO_ERR,
 762                                         alarm_event);
 763                         }
 764
 765                         if ((val64 &
 766                             VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) &
 767                                 ~mask64) {
 768                                 sw_stats->error_stats.kdfcctl_fifo0_poison++;
 769
 770                                 alarm_event = VXGE_HW_SET_LEVEL(
 771                                         VXGE_HW_EVENT_FIFO_ERR,
 772                                         alarm_event);
 773                         }
 774
 775                         if ((val64 &
 776                             VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) &
 777                                 ~mask64) {
 778                                 sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
 779
 780                                 alarm_event = VXGE_HW_SET_LEVEL(
 781                                         VXGE_HW_EVENT_FIFO_ERR,
 782                                         alarm_event);
 783                         }
 784
 785                         if (!skip_alarms) {
 786                                 writeq(VXGE_HW_INTR_MASK_ALL,
 787                                         &vp_reg->kdfcctl_errors_reg);
 788                                 alarm_event = VXGE_HW_SET_LEVEL(
 789                                         VXGE_HW_EVENT_ALARM_CLEARED,
 790                                         alarm_event);
 791                         }
 792                 }
 793
 794         }
 795
 796         if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
 797
 798                 val64 = readq(&vp_reg->wrdma_alarm_status);
 799
 800                 if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
 801
 802                         val64 = readq(&vp_reg->prc_alarm_reg);
 803                         mask64 = readq(&vp_reg->prc_alarm_mask);
 804
 805                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)&
 806                                 ~mask64)
 807                                 sw_stats->error_stats.prc_ring_bumps++;
 808
 809                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) &
 810                                 ~mask64) {
 811                                 sw_stats->error_stats.prc_rxdcm_sc_err++;
 812
 813                                 alarm_event = VXGE_HW_SET_LEVEL(
 814                                         VXGE_HW_EVENT_VPATH_ERR,
 815                                         alarm_event);
 816                         }
 817
 818                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT)
 819                                 & ~mask64) {
 820                                 sw_stats->error_stats.prc_rxdcm_sc_abort++;
 821
 822                                 alarm_event = VXGE_HW_SET_LEVEL(
 823                                                 VXGE_HW_EVENT_VPATH_ERR,
 824                                                 alarm_event);
 825                         }
 826
 827                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR)
 828                                  & ~mask64) {
 829                                 sw_stats->error_stats.prc_quanta_size_err++;
 830
 831                                 alarm_event = VXGE_HW_SET_LEVEL(
 832                                         VXGE_HW_EVENT_VPATH_ERR,
 833                                         alarm_event);
 834                         }
 835
 836                         if (!skip_alarms) {
 837                                 writeq(VXGE_HW_INTR_MASK_ALL,
 838                                         &vp_reg->prc_alarm_reg);
 839                                 alarm_event = VXGE_HW_SET_LEVEL(
 840                                                 VXGE_HW_EVENT_ALARM_CLEARED,
 841                                                 alarm_event);
 842                         }
 843                 }
 844         }
 845 out:
 846         hldev->stats.sw_dev_err_stats.vpath_alarms++;
 847 out2:
 848         if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) ||
 849                 (alarm_event == VXGE_HW_EVENT_UNKNOWN))
 850                 return VXGE_HW_OK;
 851
 852         __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event);
 853
 854         if (alarm_event == VXGE_HW_EVENT_SERR)
 855                 return VXGE_HW_ERR_CRITICAL;
 856
 857         return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ?
 858                 VXGE_HW_ERR_SLOT_FREEZE :
 859                 (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO :
 860                 VXGE_HW_ERR_VPATH;
 861 }
 862
 863 /**
 864  * vxge_hw_device_begin_irq - Begin IRQ processing.
 865  * @hldev: HW device handle.
 866  * @skip_alarms: Do not clear the alarms
 867  * @reason: "Reason" for the interrupt, the value of Titan's
 868  *      general_int_status register.
 869  *
 870  * The function performs two actions, It first checks whether (shared IRQ) the
 871  * interrupt was raised by the device. Next, it masks the device interrupts.
 872  *
 873  * Note:
 874  * vxge_hw_device_begin_irq() does not flush MMIO writes through the
 875  * bridge. Therefore, two back-to-back interrupts are potentially possible.
 876  *
 877  * Returns: 0, if the interrupt is not "ours" (note that in this case the
 878  * device remain enabled).
 879  * Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter
 880  * status.
 881  */
 882 enum vxge_hw_status vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev,
 883                                              u32 skip_alarms, u64 *reason)
 884 {
 885         u32 i;
 886         u64 val64;
 887         u64 adapter_status;
 888         u64 vpath_mask;
 889         enum vxge_hw_status ret = VXGE_HW_OK;
 890
 891         val64 = readq(&hldev->common_reg->titan_general_int_status);
 892
 893         if (unlikely(!val64)) {
 894                 /* not Titan interrupt  */
 895                 *reason = 0;
 896                 ret = VXGE_HW_ERR_WRONG_IRQ;
 897                 goto exit;
 898         }
 899
 900         if (unlikely(val64 == VXGE_HW_ALL_FOXES)) {
 901
 902                 adapter_status = readq(&hldev->common_reg->adapter_status);
 903
 904                 if (adapter_status == VXGE_HW_ALL_FOXES) {
 905
 906                         __vxge_hw_device_handle_error(hldev,
 907                                 NULL_VPID, VXGE_HW_EVENT_SLOT_FREEZE);
 908                         *reason = 0;
 909                         ret = VXGE_HW_ERR_SLOT_FREEZE;
 910                         goto exit;
 911                 }
 912         }
 913
 914         hldev->stats.sw_dev_info_stats.total_intr_cnt++;
 915
 916         *reason = val64;
 917
 918         vpath_mask = hldev->vpaths_deployed >>
 919                                 (64 - VXGE_HW_MAX_VIRTUAL_PATHS);
 920
 921         if (val64 &
 922             VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(vpath_mask)) {
 923                 hldev->stats.sw_dev_info_stats.traffic_intr_cnt++;
 924
 925                 return VXGE_HW_OK;
 926         }
 927
 928         hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++;
 929
 930         if (unlikely(val64 &
 931                         VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) {
 932
 933                 enum vxge_hw_status error_level = VXGE_HW_OK;
 934
 935                 hldev->stats.sw_dev_err_stats.vpath_alarms++;
 936
 937                 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 938
 939                         if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 940                                 continue;
 941
 942                         ret = __vxge_hw_vpath_alarm_process(
 943                                 &hldev->virtual_paths[i], skip_alarms);
 944
 945                         error_level = VXGE_HW_SET_LEVEL(ret, error_level);
 946
 947                         if (unlikely((ret == VXGE_HW_ERR_CRITICAL) ||
 948                                 (ret == VXGE_HW_ERR_SLOT_FREEZE)))
 949                                 break;
 950                 }
 951
 952                 ret = error_level;
 953         }
 954 exit:
 955         return ret;
 956 }
 957
 958 /**
 959  * vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the
 960  * condition that has caused the Tx and RX interrupt.
 961  * @hldev: HW device.
 962  *
 963  * Acknowledge (that is, clear) the condition that has caused
 964  * the Tx and Rx interrupt.
 965  * See also: vxge_hw_device_begin_irq(),
 966  * vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx().
 967  */
 968 void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev)
 969 {
 970
 971         if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
 972            (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
 973                 writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
 974                                  hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]),
 975                                 &hldev->common_reg->tim_int_status0);
 976         }
 977
 978         if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
 979            (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
 980                 __vxge_hw_pio_mem_write32_upper(
 981                                 (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
 982                                  hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]),
 983                                 &hldev->common_reg->tim_int_status1);
 984         }
 985 }
 986
 987 /*
 988  * vxge_hw_channel_dtr_alloc - Allocate a dtr from the channel
 989  * @channel: Channel
 990  * @dtrh: Buffer to return the DTR pointer
 991  *
 992  * Allocates a dtr from the reserve array. If the reserve array is empty,
 993  * it swaps the reserve and free arrays.
 994  *
 995  */
 996 static enum vxge_hw_status
 997 vxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh)
 998 {
 999         if (channel->reserve_ptr - channel->reserve_top > 0) {
1000 _alloc_after_swap:
1001                 *dtrh = channel->reserve_arr[--channel->reserve_ptr];
1002
1003                 return VXGE_HW_OK;
1004         }
1005
1006         /* switch between empty and full arrays */
1007
1008         /* the idea behind such a design is that by having free and reserved
1009          * arrays separated we basically separated irq and non-irq parts.
1010          * i.e. no additional lock need to be done when we free a resource */
1011
1012         if (channel->length - channel->free_ptr > 0) {
1013                 swap(channel->reserve_arr, channel->free_arr);
1014                 channel->reserve_ptr = channel->length;
1015                 channel->reserve_top = channel->free_ptr;
1016                 channel->free_ptr = channel->length;
1017
1018                 channel->stats->reserve_free_swaps_cnt++;
1019
1020                 goto _alloc_after_swap;
1021         }
1022
1023         channel->stats->full_cnt++;
1024
1025         *dtrh = NULL;
1026         return VXGE_HW_INF_OUT_OF_DESCRIPTORS;
1027 }
1028
1029 /*
1030  * vxge_hw_channel_dtr_post - Post a dtr to the channel
1031  * @channelh: Channel
1032  * @dtrh: DTR pointer
1033  *
1034  * Posts a dtr to work array.
1035  *
1036  */
1037 static void
1038 vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh)
1039 {
1040         vxge_assert(channel->work_arr[channel->post_index] == NULL);
1041
1042         channel->work_arr[channel->post_index++] = dtrh;
1043
1044         /* wrap-around */
1045         if (channel->post_index == channel->length)
1046                 channel->post_index = 0;
1047 }
1048
1049 /*
1050  * vxge_hw_channel_dtr_try_complete - Returns next completed dtr
1051  * @channel: Channel
1052  * @dtr: Buffer to return the next completed DTR pointer
1053  *
1054  * Returns the next completed dtr with out removing it from work array
1055  *
1056  */
1057 void
1058 vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel, void **dtrh)
1059 {
1060         vxge_assert(channel->compl_index < channel->length);
1061
1062         *dtrh = channel->work_arr[channel->compl_index];
1063         prefetch(*dtrh);
1064 }
1065
1066 /*
1067  * vxge_hw_channel_dtr_complete - Removes next completed dtr from the work array
1068  * @channel: Channel handle
1069  *
1070  * Removes the next completed dtr from work array
1071  *
1072  */
1073 void vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel)
1074 {
1075         channel->work_arr[channel->compl_index] = NULL;
1076
1077         /* wrap-around */
1078         if (++channel->compl_index == channel->length)
1079                 channel->compl_index = 0;
1080
1081         channel->stats->total_compl_cnt++;
1082 }
1083
1084 /*
1085  * vxge_hw_channel_dtr_free - Frees a dtr
1086  * @channel: Channel handle
1087  * @dtr:  DTR pointer
1088  *
1089  * Returns the dtr to free array
1090  *
1091  */
1092 void vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh)
1093 {
1094         channel->free_arr[--channel->free_ptr] = dtrh;
1095 }
1096
1097 /*
1098  * vxge_hw_channel_dtr_count
1099  * @channel: Channel handle. Obtained via vxge_hw_channel_open().
1100  *
1101  * Retrieve number of DTRs available. This function can not be called
1102  * from data path. ring_initial_replenishi() is the only user.
1103  */
1104 int vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel)
1105 {
1106         return (channel->reserve_ptr - channel->reserve_top) +
1107                 (channel->length - channel->free_ptr);
1108 }
1109
1110 /**
1111  * vxge_hw_ring_rxd_reserve     - Reserve ring descriptor.
1112  * @ring: Handle to the ring object used for receive
1113  * @rxdh: Reserved descriptor. On success HW fills this "out" parameter
1114  * with a valid handle.
1115  *
1116  * Reserve Rx descriptor for the subsequent filling-in driver
1117  * and posting on the corresponding channel (@channelh)
1118  * via vxge_hw_ring_rxd_post().
1119  *
1120  * Returns: VXGE_HW_OK - success.
1121  * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available.
1122  *
1123  */
1124 enum vxge_hw_status vxge_hw_ring_rxd_reserve(struct __vxge_hw_ring *ring,
1125         void **rxdh)
1126 {
1127         enum vxge_hw_status status;
1128         struct __vxge_hw_channel *channel;
1129
1130         channel = &ring->channel;
1131
1132         status = vxge_hw_channel_dtr_alloc(channel, rxdh);
1133
1134         if (status == VXGE_HW_OK) {
1135                 struct vxge_hw_ring_rxd_1 *rxdp =
1136                         (struct vxge_hw_ring_rxd_1 *)*rxdh;
1137
1138                 rxdp->control_0 = rxdp->control_1 = 0;
1139         }
1140
1141         return status;
1142 }
1143
1144 /**
1145  * vxge_hw_ring_rxd_free - Free descriptor.
1146  * @ring: Handle to the ring object used for receive
1147  * @rxdh: Descriptor handle.
1148  *
1149  * Free the reserved descriptor. This operation is "symmetrical" to
1150  * vxge_hw_ring_rxd_reserve. The "free-ing" completes the descriptor's
1151  * lifecycle.
1152  *
1153  * After free-ing (see vxge_hw_ring_rxd_free()) the descriptor again can
1154  * be:
1155  *
1156  * - reserved (vxge_hw_ring_rxd_reserve);
1157  *
1158  * - posted     (vxge_hw_ring_rxd_post);
1159  *
1160  * - completed (vxge_hw_ring_rxd_next_completed);
1161  *
1162  * - and recycled again (vxge_hw_ring_rxd_free).
1163  *
1164  * For alternative state transitions and more details please refer to
1165  * the design doc.
1166  *
1167  */
1168 void vxge_hw_ring_rxd_free(struct __vxge_hw_ring *ring, void *rxdh)
1169 {
1170         struct __vxge_hw_channel *channel;
1171
1172         channel = &ring->channel;
1173
1174         vxge_hw_channel_dtr_free(channel, rxdh);
1175
1176 }
1177
1178 /**
1179  * vxge_hw_ring_rxd_pre_post - Prepare rxd and post
1180  * @ring: Handle to the ring object used for receive
1181  * @rxdh: Descriptor handle.
1182  *
1183  * This routine prepares a rxd and posts
1184  */
1185 void vxge_hw_ring_rxd_pre_post(struct __vxge_hw_ring *ring, void *rxdh)
1186 {
1187         struct __vxge_hw_channel *channel;
1188
1189         channel = &ring->channel;
1190
1191         vxge_hw_channel_dtr_post(channel, rxdh);
1192 }
1193
1194 /**
1195  * vxge_hw_ring_rxd_post_post - Process rxd after post.
1196  * @ring: Handle to the ring object used for receive
1197  * @rxdh: Descriptor handle.
1198  *
1199  * Processes rxd after post
1200  */
1201 void vxge_hw_ring_rxd_post_post(struct __vxge_hw_ring *ring, void *rxdh)
1202 {
1203         struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1204
1205         rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1206
1207         if (ring->stats->common_stats.usage_cnt > 0)
1208                 ring->stats->common_stats.usage_cnt--;
1209 }
1210
1211 /**
1212  * vxge_hw_ring_rxd_post - Post descriptor on the ring.
1213  * @ring: Handle to the ring object used for receive
1214  * @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve().
1215  *
1216  * Post descriptor on the ring.
1217  * Prior to posting the descriptor should be filled in accordance with
1218  * Host/Titan interface specification for a given service (LL, etc.).
1219  *
1220  */
1221 void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring, void *rxdh)
1222 {
1223         struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1224         struct __vxge_hw_channel *channel;
1225
1226         channel = &ring->channel;
1227
1228         wmb();
1229         rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1230
1231         vxge_hw_channel_dtr_post(channel, rxdh);
1232
1233         if (ring->stats->common_stats.usage_cnt > 0)
1234                 ring->stats->common_stats.usage_cnt--;
1235 }
1236
1237 /**
1238  * vxge_hw_ring_rxd_post_post_wmb - Process rxd after post with memory barrier.
1239  * @ring: Handle to the ring object used for receive
1240  * @rxdh: Descriptor handle.
1241  *
1242  * Processes rxd after post with memory barrier.
1243  */
1244 void vxge_hw_ring_rxd_post_post_wmb(struct __vxge_hw_ring *ring, void *rxdh)
1245 {
1246         wmb();
1247         vxge_hw_ring_rxd_post_post(ring, rxdh);
1248 }
1249
1250 /**
1251  * vxge_hw_ring_rxd_next_completed - Get the _next_ completed descriptor.
1252  * @ring: Handle to the ring object used for receive
1253  * @rxdh: Descriptor handle. Returned by HW.
1254  * @t_code:     Transfer code, as per Titan User Guide,
1255  *       Receive Descriptor Format. Returned by HW.
1256  *
1257  * Retrieve the _next_ completed descriptor.
1258  * HW uses ring callback (*vxge_hw_ring_callback_f) to notifiy
1259  * driver of new completed descriptors. After that
1260  * the driver can use vxge_hw_ring_rxd_next_completed to retrieve the rest
1261  * completions (the very first completion is passed by HW via
1262  * vxge_hw_ring_callback_f).
1263  *
1264  * Implementation-wise, the driver is free to call
1265  * vxge_hw_ring_rxd_next_completed either immediately from inside the
1266  * ring callback, or in a deferred fashion and separate (from HW)
1267  * context.
1268  *
1269  * Non-zero @t_code means failure to fill-in receive buffer(s)
1270  * of the descriptor.
1271  * For instance, parity error detected during the data transfer.
1272  * In this case Titan will complete the descriptor and indicate
1273  * for the host that the received data is not to be used.
1274  * For details please refer to Titan User Guide.
1275  *
1276  * Returns: VXGE_HW_OK - success.
1277  * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
1278  * are currently available for processing.
1279  *
1280  * See also: vxge_hw_ring_callback_f{},
1281  * vxge_hw_fifo_rxd_next_completed(), enum vxge_hw_status{}.
1282  */
1283 enum vxge_hw_status vxge_hw_ring_rxd_next_completed(
1284         struct __vxge_hw_ring *ring, void **rxdh, u8 *t_code)
1285 {
1286         struct __vxge_hw_channel *channel;
1287         struct vxge_hw_ring_rxd_1 *rxdp;
1288         enum vxge_hw_status status = VXGE_HW_OK;
1289         u64 control_0, own;
1290
1291         channel = &ring->channel;
1292
1293         vxge_hw_channel_dtr_try_complete(channel, rxdh);
1294
1295         rxdp = *rxdh;
1296         if (rxdp == NULL) {
1297                 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1298                 goto exit;
1299         }
1300
1301         control_0 = rxdp->control_0;
1302         own = control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1303         *t_code = (u8)VXGE_HW_RING_RXD_T_CODE_GET(control_0);
1304
1305         /* check whether it is not the end */
1306         if (!own || *t_code == VXGE_HW_RING_T_CODE_FRM_DROP) {
1307
1308                 vxge_assert((rxdp)->host_control !=
1309                                 0);
1310
1311                 ++ring->cmpl_cnt;
1312                 vxge_hw_channel_dtr_complete(channel);
1313
1314                 vxge_assert(*t_code != VXGE_HW_RING_RXD_T_CODE_UNUSED);
1315
1316                 ring->stats->common_stats.usage_cnt++;
1317                 if (ring->stats->common_stats.usage_max <
1318                                 ring->stats->common_stats.usage_cnt)
1319                         ring->stats->common_stats.usage_max =
1320                                 ring->stats->common_stats.usage_cnt;
1321
1322                 status = VXGE_HW_OK;
1323                 goto exit;
1324         }
1325
1326         /* reset it. since we don't want to return
1327          * garbage to the driver */
1328         *rxdh = NULL;
1329         status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1330 exit:
1331         return status;
1332 }
1333
1334 /**
1335  * vxge_hw_ring_handle_tcode - Handle transfer code.
1336  * @ring: Handle to the ring object used for receive
1337  * @rxdh: Descriptor handle.
1338  * @t_code: One of the enumerated (and documented in the Titan user guide)
1339  * "transfer codes".
1340  *
1341  * Handle descriptor's transfer code. The latter comes with each completed
1342  * descriptor.
1343  *
1344  * Returns: one of the enum vxge_hw_status{} enumerated types.
1345  * VXGE_HW_OK                   - for success.
1346  * VXGE_HW_ERR_CRITICAL         - when encounters critical error.
1347  */
1348 enum vxge_hw_status vxge_hw_ring_handle_tcode(
1349         struct __vxge_hw_ring *ring, void *rxdh, u8 t_code)
1350 {
1351         enum vxge_hw_status status = VXGE_HW_OK;
1352
1353         /* If the t_code is not supported and if the
1354          * t_code is other than 0x5 (unparseable packet
1355          * such as unknown UPV6 header), Drop it !!!
1356          */
1357
1358         if (t_code ==  VXGE_HW_RING_T_CODE_OK ||
1359                 t_code == VXGE_HW_RING_T_CODE_L3_PKT_ERR) {
1360                 status = VXGE_HW_OK;
1361                 goto exit;
1362         }
1363
1364         if (t_code > VXGE_HW_RING_T_CODE_MULTI_ERR) {
1365                 status = VXGE_HW_ERR_INVALID_TCODE;
1366                 goto exit;
1367         }
1368
1369         ring->stats->rxd_t_code_err_cnt[t_code]++;
1370 exit:
1371         return status;
1372 }
1373
1374 /**
1375  * __vxge_hw_non_offload_db_post - Post non offload doorbell
1376  *
1377  * @fifo: fifohandle
1378  * @txdl_ptr: The starting location of the TxDL in host memory
1379  * @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)
1380  * @no_snoop: No snoop flags
1381  *
1382  * This function posts a non-offload doorbell to doorbell FIFO
1383  *
1384  */
1385 static void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo,
1386         u64 txdl_ptr, u32 num_txds, u32 no_snoop)
1387 {
1388         writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) |
1389                 VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds) |
1390                 VXGE_HW_NODBW_GET_NO_SNOOP(no_snoop),
1391                 &fifo->nofl_db->control_0);
1392
1393         mmiowb();
1394
1395         writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr);
1396
1397         mmiowb();
1398 }
1399
1400 /**
1401  * vxge_hw_fifo_free_txdl_count_get - returns the number of txdls available in
1402  * the fifo
1403  * @fifoh: Handle to the fifo object used for non offload send
1404  */
1405 u32 vxge_hw_fifo_free_txdl_count_get(struct __vxge_hw_fifo *fifoh)
1406 {
1407         return vxge_hw_channel_dtr_count(&fifoh->channel);
1408 }
1409
1410 /**
1411  * vxge_hw_fifo_txdl_reserve - Reserve fifo descriptor.
1412  * @fifoh: Handle to the fifo object used for non offload send
1413  * @txdlh: Reserved descriptor. On success HW fills this "out" parameter
1414  *        with a valid handle.
1415  * @txdl_priv: Buffer to return the pointer to per txdl space
1416  *
1417  * Reserve a single TxDL (that is, fifo descriptor)
1418  * for the subsequent filling-in by driver)
1419  * and posting on the corresponding channel (@channelh)
1420  * via vxge_hw_fifo_txdl_post().
1421  *
1422  * Note: it is the responsibility of driver to reserve multiple descriptors
1423  * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor
1424  * carries up to configured number (fifo.max_frags) of contiguous buffers.
1425  *
1426  * Returns: VXGE_HW_OK - success;
1427  * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
1428  *
1429  */
1430 enum vxge_hw_status vxge_hw_fifo_txdl_reserve(
1431         struct __vxge_hw_fifo *fifo,
1432         void **txdlh, void **txdl_priv)
1433 {
1434         struct __vxge_hw_channel *channel;
1435         enum vxge_hw_status status;
1436         int i;
1437
1438         channel = &fifo->channel;
1439
1440         status = vxge_hw_channel_dtr_alloc(channel, txdlh);
1441
1442         if (status == VXGE_HW_OK) {
1443                 struct vxge_hw_fifo_txd *txdp =
1444                         (struct vxge_hw_fifo_txd *)*txdlh;
1445                 struct __vxge_hw_fifo_txdl_priv *priv;
1446
1447                 priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
1448
1449                 /* reset the TxDL's private */
1450                 priv->align_dma_offset = 0;
1451                 priv->align_vaddr_start = priv->align_vaddr;
1452                 priv->align_used_frags = 0;
1453                 priv->frags = 0;
1454                 priv->alloc_frags = fifo->config->max_frags;
1455                 priv->next_txdl_priv = NULL;
1456
1457                 *txdl_priv = (void *)(size_t)txdp->host_control;
1458
1459                 for (i = 0; i < fifo->config->max_frags; i++) {
1460                         txdp = ((struct vxge_hw_fifo_txd *)*txdlh) + i;
1461                         txdp->control_0 = txdp->control_1 = 0;
1462                 }
1463         }
1464
1465         return status;
1466 }
1467
1468 /**
1469  * vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the
1470  * descriptor.
1471  * @fifo: Handle to the fifo object used for non offload send
1472  * @txdlh: Descriptor handle.
1473  * @frag_idx: Index of the data buffer in the caller's scatter-gather list
1474  *            (of buffers).
1475  * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
1476  * @size: Size of the data buffer (in bytes).
1477  *
1478  * This API is part of the preparation of the transmit descriptor for posting
1479  * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
1480  * vxge_hw_fifo_txdl_mss_set() and vxge_hw_fifo_txdl_cksum_set_bits().
1481  * All three APIs fill in the fields of the fifo descriptor,
1482  * in accordance with the Titan specification.
1483  *
1484  */
1485 void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo,
1486                                   void *txdlh, u32 frag_idx,
1487                                   dma_addr_t dma_pointer, u32 size)
1488 {
1489         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
1490         struct vxge_hw_fifo_txd *txdp, *txdp_last;
1491
1492         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
1493         txdp = (struct vxge_hw_fifo_txd *)txdlh  +  txdl_priv->frags;
1494
1495         if (frag_idx != 0)
1496                 txdp->control_0 = txdp->control_1 = 0;
1497         else {
1498                 txdp->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
1499                         VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST);
1500                 txdp->control_1 |= fifo->interrupt_type;
1501                 txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_NUMBER(
1502                         fifo->tx_intr_num);
1503                 if (txdl_priv->frags) {
1504                         txdp_last = (struct vxge_hw_fifo_txd *)txdlh  +
1505                         (txdl_priv->frags - 1);
1506                         txdp_last->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
1507                                 VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
1508                 }
1509         }
1510
1511         vxge_assert(frag_idx < txdl_priv->alloc_frags);
1512
1513         txdp->buffer_pointer = (u64)dma_pointer;
1514         txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(size);
1515         fifo->stats->total_buffers++;
1516         txdl_priv->frags++;
1517 }
1518
1519 /**
1520  * vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
1521  * @fifo: Handle to the fifo object used for non offload send
1522  * @txdlh: Descriptor obtained via vxge_hw_fifo_txdl_reserve()
1523  * @frags: Number of contiguous buffers that are part of a single
1524  *         transmit operation.
1525  *
1526  * Post descriptor on the 'fifo' type channel for transmission.
1527  * Prior to posting the descriptor should be filled in accordance with
1528  * Host/Titan interface specification for a given service (LL, etc.).
1529  *
1530  */
1531 void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo, void *txdlh)
1532 {
1533         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
1534         struct vxge_hw_fifo_txd *txdp_last;
1535         struct vxge_hw_fifo_txd *txdp_first;
1536
1537         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
1538         txdp_first = txdlh;
1539
1540         txdp_last = (struct vxge_hw_fifo_txd *)txdlh  +  (txdl_priv->frags - 1);
1541         txdp_last->control_0 |=
1542               VXGE_HW_FIFO_TXD_GATHER_CODE(VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
1543         txdp_first->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER;
1544
1545         vxge_hw_channel_dtr_post(&fifo->channel, txdlh);
1546
1547         __vxge_hw_non_offload_db_post(fifo,
1548                 (u64)txdl_priv->dma_addr,
1549                 txdl_priv->frags - 1,
1550                 fifo->no_snoop_bits);
1551
1552         fifo->stats->total_posts++;
1553         fifo->stats->common_stats.usage_cnt++;
1554         if (fifo->stats->common_stats.usage_max <
1555                 fifo->stats->common_stats.usage_cnt)
1556                 fifo->stats->common_stats.usage_max =
1557                         fifo->stats->common_stats.usage_cnt;
1558 }
1559
1560 /**
1561  * vxge_hw_fifo_txdl_next_completed - Retrieve next completed descriptor.
1562  * @fifo: Handle to the fifo object used for non offload send
1563  * @txdlh: Descriptor handle. Returned by HW.
1564  * @t_code: Transfer code, as per Titan User Guide,
1565  *          Transmit Descriptor Format.
1566  *          Returned by HW.
1567  *
1568  * Retrieve the _next_ completed descriptor.
1569  * HW uses channel callback (*vxge_hw_channel_callback_f) to notifiy
1570  * driver of new completed descriptors. After that
1571  * the driver can use vxge_hw_fifo_txdl_next_completed to retrieve the rest
1572  * completions (the very first completion is passed by HW via
1573  * vxge_hw_channel_callback_f).
1574  *
1575  * Implementation-wise, the driver is free to call
1576  * vxge_hw_fifo_txdl_next_completed either immediately from inside the
1577  * channel callback, or in a deferred fashion and separate (from HW)
1578  * context.
1579  *
1580  * Non-zero @t_code means failure to process the descriptor.
1581  * The failure could happen, for instance, when the link is
1582  * down, in which case Titan completes the descriptor because it
1583  * is not able to send the data out.
1584  *
1585  * For details please refer to Titan User Guide.
1586  *
1587  * Returns: VXGE_HW_OK - success.
1588  * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
1589  * are currently available for processing.
1590  *
1591  */
1592 enum vxge_hw_status vxge_hw_fifo_txdl_next_completed(
1593         struct __vxge_hw_fifo *fifo, void **txdlh,
1594         enum vxge_hw_fifo_tcode *t_code)
1595 {
1596         struct __vxge_hw_channel *channel;
1597         struct vxge_hw_fifo_txd *txdp;
1598         enum vxge_hw_status status = VXGE_HW_OK;
1599
1600         channel = &fifo->channel;
1601
1602         vxge_hw_channel_dtr_try_complete(channel, txdlh);
1603
1604         txdp = *txdlh;
1605         if (txdp == NULL) {
1606                 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1607                 goto exit;
1608         }
1609
1610         /* check whether host owns it */
1611         if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)) {
1612
1613                 vxge_assert(txdp->host_control != 0);
1614
1615                 vxge_hw_channel_dtr_complete(channel);
1616
1617                 *t_code = (u8)VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0);
1618
1619                 if (fifo->stats->common_stats.usage_cnt > 0)
1620                         fifo->stats->common_stats.usage_cnt--;
1621
1622                 status = VXGE_HW_OK;
1623                 goto exit;
1624         }
1625
1626         /* no more completions */
1627         *txdlh = NULL;
1628         status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1629 exit:
1630         return status;
1631 }
1632
1633 /**
1634  * vxge_hw_fifo_handle_tcode - Handle transfer code.
1635  * @fifo: Handle to the fifo object used for non offload send
1636  * @txdlh: Descriptor handle.
1637  * @t_code: One of the enumerated (and documented in the Titan user guide)
1638  *          "transfer codes".
1639  *
1640  * Handle descriptor's transfer code. The latter comes with each completed
1641  * descriptor.
1642  *
1643  * Returns: one of the enum vxge_hw_status{} enumerated types.
1644  * VXGE_HW_OK - for success.
1645  * VXGE_HW_ERR_CRITICAL - when encounters critical error.
1646  */
1647 enum vxge_hw_status vxge_hw_fifo_handle_tcode(struct __vxge_hw_fifo *fifo,
1648                                               void *txdlh,
1649                                               enum vxge_hw_fifo_tcode t_code)
1650 {
1651         enum vxge_hw_status status = VXGE_HW_OK;
1652
1653         if (((t_code & 0x7) < 0) || ((t_code & 0x7) > 0x4)) {
1654                 status = VXGE_HW_ERR_INVALID_TCODE;
1655                 goto exit;
1656         }
1657
1658         fifo->stats->txd_t_code_err_cnt[t_code]++;
1659 exit:
1660         return status;
1661 }
1662
1663 /**
1664  * vxge_hw_fifo_txdl_free - Free descriptor.
1665  * @fifo: Handle to the fifo object used for non offload send
1666  * @txdlh: Descriptor handle.
1667  *
1668  * Free the reserved descriptor. This operation is "symmetrical" to
1669  * vxge_hw_fifo_txdl_reserve. The "free-ing" completes the descriptor's
1670  * lifecycle.
1671  *
1672  * After free-ing (see vxge_hw_fifo_txdl_free()) the descriptor again can
1673  * be:
1674  *
1675  * - reserved (vxge_hw_fifo_txdl_reserve);
1676  *
1677  * - posted (vxge_hw_fifo_txdl_post);
1678  *
1679  * - completed (vxge_hw_fifo_txdl_next_completed);
1680  *
1681  * - and recycled again (vxge_hw_fifo_txdl_free).
1682  *
1683  * For alternative state transitions and more details please refer to
1684  * the design doc.
1685  *
1686  */
1687 void vxge_hw_fifo_txdl_free(struct __vxge_hw_fifo *fifo, void *txdlh)
1688 {
1689         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
1690         u32 max_frags;
1691         struct __vxge_hw_channel *channel;
1692
1693         channel = &fifo->channel;
1694
1695         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo,
1696                         (struct vxge_hw_fifo_txd *)txdlh);
1697
1698         max_frags = fifo->config->max_frags;
1699
1700         vxge_hw_channel_dtr_free(channel, txdlh);
1701 }
1702
1703 /**
1704  * vxge_hw_vpath_mac_addr_add - Add the mac address entry for this vpath
1705  *               to MAC address table.
1706  * @vp: Vpath handle.
1707  * @macaddr: MAC address to be added for this vpath into the list
1708  * @macaddr_mask: MAC address mask for macaddr
1709  * @duplicate_mode: Duplicate MAC address add mode. Please see
1710  *             enum vxge_hw_vpath_mac_addr_add_mode{}
1711  *
1712  * Adds the given mac address and mac address mask into the list for this
1713  * vpath.
1714  * see also: vxge_hw_vpath_mac_addr_delete, vxge_hw_vpath_mac_addr_get and
1715  * vxge_hw_vpath_mac_addr_get_next
1716  *
1717  */
1718 enum vxge_hw_status
1719 vxge_hw_vpath_mac_addr_add(
1720         struct __vxge_hw_vpath_handle *vp,
1721         u8 *macaddr,
1722         u8 *macaddr_mask,
1723         enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode)
1724 {
1725         u32 i;
1726         u64 data1 = 0ULL;
1727         u64 data2 = 0ULL;
1728         enum vxge_hw_status status = VXGE_HW_OK;
1729
1730         if (vp == NULL) {
1731                 status = VXGE_HW_ERR_INVALID_HANDLE;
1732                 goto exit;
1733         }
1734
1735         for (i = 0; i < ETH_ALEN; i++) {
1736                 data1 <<= 8;
1737                 data1 |= (u8)macaddr[i];
1738
1739                 data2 <<= 8;
1740                 data2 |= (u8)macaddr_mask[i];
1741         }
1742
1743         switch (duplicate_mode) {
1744         case VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE:
1745                 i = 0;
1746                 break;
1747         case VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE:
1748                 i = 1;
1749                 break;
1750         case VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE:
1751                 i = 2;
1752                 break;
1753         default:
1754                 i = 0;
1755                 break;
1756         }
1757
1758         status = __vxge_hw_vpath_rts_table_set(vp,
1759                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
1760                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1761                         0,
1762                         VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1763                         VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2)|
1764                         VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i));
1765 exit:
1766         return status;
1767 }
1768
1769 /**
1770  * vxge_hw_vpath_mac_addr_get - Get the first mac address entry for this vpath
1771  *               from MAC address table.
1772  * @vp: Vpath handle.
1773  * @macaddr: First MAC address entry for this vpath in the list
1774  * @macaddr_mask: MAC address mask for macaddr
1775  *
1776  * Returns the first mac address and mac address mask in the list for this
1777  * vpath.
1778  * see also: vxge_hw_vpath_mac_addr_get_next
1779  *
1780  */
1781 enum vxge_hw_status
1782 vxge_hw_vpath_mac_addr_get(
1783         struct __vxge_hw_vpath_handle *vp,
1784         u8 *macaddr,
1785         u8 *macaddr_mask)
1786 {
1787         u32 i;
1788         u64 data1 = 0ULL;
1789         u64 data2 = 0ULL;
1790         enum vxge_hw_status status = VXGE_HW_OK;
1791
1792         if (vp == NULL) {
1793                 status = VXGE_HW_ERR_INVALID_HANDLE;
1794                 goto exit;
1795         }
1796
1797         status = __vxge_hw_vpath_rts_table_get(vp,
1798                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
1799                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1800                         0, &data1, &data2);
1801
1802         if (status != VXGE_HW_OK)
1803                 goto exit;
1804
1805         data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1806
1807         data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1808
1809         for (i = ETH_ALEN; i > 0; i--) {
1810                 macaddr[i-1] = (u8)(data1 & 0xFF);
1811                 data1 >>= 8;
1812
1813                 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
1814                 data2 >>= 8;
1815         }
1816 exit:
1817         return status;
1818 }
1819
1820 /**
1821  * vxge_hw_vpath_mac_addr_get_next - Get the next mac address entry for this
1822  * vpath
1823  *               from MAC address table.
1824  * @vp: Vpath handle.
1825  * @macaddr: Next MAC address entry for this vpath in the list
1826  * @macaddr_mask: MAC address mask for macaddr
1827  *
1828  * Returns the next mac address and mac address mask in the list for this
1829  * vpath.
1830  * see also: vxge_hw_vpath_mac_addr_get
1831  *
1832  */
1833 enum vxge_hw_status
1834 vxge_hw_vpath_mac_addr_get_next(
1835         struct __vxge_hw_vpath_handle *vp,
1836         u8 *macaddr,
1837         u8 *macaddr_mask)
1838 {
1839         u32 i;
1840         u64 data1 = 0ULL;
1841         u64 data2 = 0ULL;
1842         enum vxge_hw_status status = VXGE_HW_OK;
1843
1844         if (vp == NULL) {
1845                 status = VXGE_HW_ERR_INVALID_HANDLE;
1846                 goto exit;
1847         }
1848
1849         status = __vxge_hw_vpath_rts_table_get(vp,
1850                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
1851                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1852                         0, &data1, &data2);
1853
1854         if (status != VXGE_HW_OK)
1855                 goto exit;
1856
1857         data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1858
1859         data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1860
1861         for (i = ETH_ALEN; i > 0; i--) {
1862                 macaddr[i-1] = (u8)(data1 & 0xFF);
1863                 data1 >>= 8;
1864
1865                 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
1866                 data2 >>= 8;
1867         }
1868
1869 exit:
1870         return status;
1871 }
1872
1873 /**
1874  * vxge_hw_vpath_mac_addr_delete - Delete the mac address entry for this vpath
1875  *               to MAC address table.
1876  * @vp: Vpath handle.
1877  * @macaddr: MAC address to be added for this vpath into the list
1878  * @macaddr_mask: MAC address mask for macaddr
1879  *
1880  * Delete the given mac address and mac address mask into the list for this
1881  * vpath.
1882  * see also: vxge_hw_vpath_mac_addr_add, vxge_hw_vpath_mac_addr_get and
1883  * vxge_hw_vpath_mac_addr_get_next
1884  *
1885  */
1886 enum vxge_hw_status
1887 vxge_hw_vpath_mac_addr_delete(
1888         struct __vxge_hw_vpath_handle *vp,
1889         u8 *macaddr,
1890         u8 *macaddr_mask)
1891 {
1892         u32 i;
1893         u64 data1 = 0ULL;
1894         u64 data2 = 0ULL;
1895         enum vxge_hw_status status = VXGE_HW_OK;
1896
1897         if (vp == NULL) {
1898                 status = VXGE_HW_ERR_INVALID_HANDLE;
1899                 goto exit;
1900         }
1901
1902         for (i = 0; i < ETH_ALEN; i++) {
1903                 data1 <<= 8;
1904                 data1 |= (u8)macaddr[i];
1905
1906                 data2 <<= 8;
1907                 data2 |= (u8)macaddr_mask[i];
1908         }
1909
1910         status = __vxge_hw_vpath_rts_table_set(vp,
1911                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
1912                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1913                         0,
1914                         VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1915                         VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2));
1916 exit:
1917         return status;
1918 }
1919
1920 /**
1921  * vxge_hw_vpath_vid_add - Add the vlan id entry for this vpath
1922  *               to vlan id table.
1923  * @vp: Vpath handle.
1924  * @vid: vlan id to be added for this vpath into the list
1925  *
1926  * Adds the given vlan id into the list for this  vpath.
1927  * see also: vxge_hw_vpath_vid_delete
1928  *
1929  */
1930 enum vxge_hw_status
1931 vxge_hw_vpath_vid_add(struct __vxge_hw_vpath_handle *vp, u64 vid)
1932 {
1933         enum vxge_hw_status status = VXGE_HW_OK;
1934
1935         if (vp == NULL) {
1936                 status = VXGE_HW_ERR_INVALID_HANDLE;
1937                 goto exit;
1938         }
1939
1940         status = __vxge_hw_vpath_rts_table_set(vp,
1941                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
1942                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
1943                         0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
1944 exit:
1945         return status;
1946 }
1947
1948 /**
1949  * vxge_hw_vpath_vid_delete - Delete the vlan id entry for this vpath
1950  *               to vlan id table.
1951  * @vp: Vpath handle.
1952  * @vid: vlan id to be added for this vpath into the list
1953  *
1954  * Adds the given vlan id into the list for this  vpath.
1955  * see also: vxge_hw_vpath_vid_add
1956  *
1957  */
1958 enum vxge_hw_status
1959 vxge_hw_vpath_vid_delete(struct __vxge_hw_vpath_handle *vp, u64 vid)
1960 {
1961         enum vxge_hw_status status = VXGE_HW_OK;
1962
1963         if (vp == NULL) {
1964                 status = VXGE_HW_ERR_INVALID_HANDLE;
1965                 goto exit;
1966         }
1967
1968         status = __vxge_hw_vpath_rts_table_set(vp,
1969                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
1970                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
1971                         0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
1972 exit:
1973         return status;
1974 }
1975
1976 /**
1977  * vxge_hw_vpath_promisc_enable - Enable promiscuous mode.
1978  * @vp: Vpath handle.
1979  *
1980  * Enable promiscuous mode of Titan-e operation.
1981  *
1982  * See also: vxge_hw_vpath_promisc_disable().
1983  */
1984 enum vxge_hw_status vxge_hw_vpath_promisc_enable(
1985                         struct __vxge_hw_vpath_handle *vp)
1986 {
1987         u64 val64;
1988         struct __vxge_hw_virtualpath *vpath;
1989         enum vxge_hw_status status = VXGE_HW_OK;
1990
1991         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
1992                 status = VXGE_HW_ERR_INVALID_HANDLE;
1993                 goto exit;
1994         }
1995
1996         vpath = vp->vpath;
1997
1998         /* Enable promiscuous mode for function 0 only */
1999         if (!(vpath->hldev->access_rights &
2000                 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM))
2001                 return VXGE_HW_OK;
2002
2003         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2004
2005         if (!(val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN)) {
2006
2007                 val64 |= VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
2008                          VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
2009                          VXGE_HW_RXMAC_VCFG0_BCAST_EN |
2010                          VXGE_HW_RXMAC_VCFG0_ALL_VID_EN;
2011
2012                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2013         }
2014 exit:
2015         return status;
2016 }
2017
2018 /**
2019  * vxge_hw_vpath_promisc_disable - Disable promiscuous mode.
2020  * @vp: Vpath handle.
2021  *
2022  * Disable promiscuous mode of Titan-e operation.
2023  *
2024  * See also: vxge_hw_vpath_promisc_enable().
2025  */
2026 enum vxge_hw_status vxge_hw_vpath_promisc_disable(
2027                         struct __vxge_hw_vpath_handle *vp)
2028 {
2029         u64 val64;
2030         struct __vxge_hw_virtualpath *vpath;
2031         enum vxge_hw_status status = VXGE_HW_OK;
2032
2033         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2034                 status = VXGE_HW_ERR_INVALID_HANDLE;
2035                 goto exit;
2036         }
2037
2038         vpath = vp->vpath;
2039
2040         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2041
2042         if (val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) {
2043
2044                 val64 &= ~(VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
2045                            VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
2046                            VXGE_HW_RXMAC_VCFG0_ALL_VID_EN);
2047
2048                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2049         }
2050 exit:
2051         return status;
2052 }
2053
2054 /*
2055  * vxge_hw_vpath_bcast_enable - Enable broadcast
2056  * @vp: Vpath handle.
2057  *
2058  * Enable receiving broadcasts.
2059  */
2060 enum vxge_hw_status vxge_hw_vpath_bcast_enable(
2061                         struct __vxge_hw_vpath_handle *vp)
2062 {
2063         u64 val64;
2064         struct __vxge_hw_virtualpath *vpath;
2065         enum vxge_hw_status status = VXGE_HW_OK;
2066
2067         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2068                 status = VXGE_HW_ERR_INVALID_HANDLE;
2069                 goto exit;
2070         }
2071
2072         vpath = vp->vpath;
2073
2074         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2075
2076         if (!(val64 & VXGE_HW_RXMAC_VCFG0_BCAST_EN)) {
2077                 val64 |= VXGE_HW_RXMAC_VCFG0_BCAST_EN;
2078                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2079         }
2080 exit:
2081         return status;
2082 }
2083
2084 /**
2085  * vxge_hw_vpath_mcast_enable - Enable multicast addresses.
2086  * @vp: Vpath handle.
2087  *
2088  * Enable Titan-e multicast addresses.
2089  * Returns: VXGE_HW_OK on success.
2090  *
2091  */
2092 enum vxge_hw_status vxge_hw_vpath_mcast_enable(
2093                         struct __vxge_hw_vpath_handle *vp)
2094 {
2095         u64 val64;
2096         struct __vxge_hw_virtualpath *vpath;
2097         enum vxge_hw_status status = VXGE_HW_OK;
2098
2099         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2100                 status = VXGE_HW_ERR_INVALID_HANDLE;
2101                 goto exit;
2102         }
2103
2104         vpath = vp->vpath;
2105
2106         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2107
2108         if (!(val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN)) {
2109                 val64 |= VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
2110                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2111         }
2112 exit:
2113         return status;
2114 }
2115
2116 /**
2117  * vxge_hw_vpath_mcast_disable - Disable  multicast addresses.
2118  * @vp: Vpath handle.
2119  *
2120  * Disable Titan-e multicast addresses.
2121  * Returns: VXGE_HW_OK - success.
2122  * VXGE_HW_ERR_INVALID_HANDLE - Invalid handle
2123  *
2124  */
2125 enum vxge_hw_status
2126 vxge_hw_vpath_mcast_disable(struct __vxge_hw_vpath_handle *vp)
2127 {
2128         u64 val64;
2129         struct __vxge_hw_virtualpath *vpath;
2130         enum vxge_hw_status status = VXGE_HW_OK;
2131
2132         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2133                 status = VXGE_HW_ERR_INVALID_HANDLE;
2134                 goto exit;
2135         }
2136
2137         vpath = vp->vpath;
2138
2139         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2140
2141         if (val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) {
2142                 val64 &= ~VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
2143                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2144         }
2145 exit:
2146         return status;
2147 }
2148
2149 /*
2150  * vxge_hw_vpath_alarm_process - Process Alarms.
2151  * @vpath: Virtual Path.
2152  * @skip_alarms: Do not clear the alarms
2153  *
2154  * Process vpath alarms.
2155  *
2156  */
2157 enum vxge_hw_status vxge_hw_vpath_alarm_process(
2158                         struct __vxge_hw_vpath_handle *vp,
2159                         u32 skip_alarms)
2160 {
2161         enum vxge_hw_status status = VXGE_HW_OK;
2162
2163         if (vp == NULL) {
2164                 status = VXGE_HW_ERR_INVALID_HANDLE;
2165                 goto exit;
2166         }
2167
2168         status = __vxge_hw_vpath_alarm_process(vp->vpath, skip_alarms);
2169 exit:
2170         return status;
2171 }
2172
2173 /**
2174  * vxge_hw_vpath_msix_set - Associate MSIX vectors with TIM interrupts and
2175  *                            alrms
2176  * @vp: Virtual Path handle.
2177  * @tim_msix_id: MSIX vectors associated with VXGE_HW_MAX_INTR_PER_VP number of
2178  *             interrupts(Can be repeated). If fifo or ring are not enabled
2179  *             the MSIX vector for that should be set to 0
2180  * @alarm_msix_id: MSIX vector for alarm.
2181  *
2182  * This API will associate a given MSIX vector numbers with the four TIM
2183  * interrupts and alarm interrupt.
2184  */
2185 void
2186 vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
2187                        int alarm_msix_id)
2188 {
2189         u64 val64;
2190         struct __vxge_hw_virtualpath *vpath = vp->vpath;
2191         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
2192         u32 vp_id = vp->vpath->vp_id;
2193
2194         val64 =  VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
2195                   (vp_id * 4) + tim_msix_id[0]) |
2196                  VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
2197                   (vp_id * 4) + tim_msix_id[1]);
2198
2199         writeq(val64, &vp_reg->interrupt_cfg0);
2200
2201         writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
2202                         (vpath->hldev->first_vp_id * 4) + alarm_msix_id),
2203                         &vp_reg->interrupt_cfg2);
2204
2205         if (vpath->hldev->config.intr_mode ==
2206                                         VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
2207                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2208                                 VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN,
2209                                 0, 32), &vp_reg->one_shot_vect0_en);
2210                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2211                                 VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN,
2212                                 0, 32), &vp_reg->one_shot_vect1_en);
2213                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2214                                 VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN,
2215                                 0, 32), &vp_reg->one_shot_vect2_en);
2216         }
2217 }
2218
2219 /**
2220  * vxge_hw_vpath_msix_mask - Mask MSIX Vector.
2221  * @vp: Virtual Path handle.
2222  * @msix_id:  MSIX ID
2223  *
2224  * The function masks the msix interrupt for the given msix_id
2225  *
2226  * Returns: 0,
2227  * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2228  * status.
2229  * See also:
2230  */
2231 void
2232 vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2233 {
2234         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2235         __vxge_hw_pio_mem_write32_upper(
2236                 (u32) vxge_bVALn(vxge_mBIT(msix_id  >> 2), 0, 32),
2237                 &hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
2238 }
2239
2240 /**
2241  * vxge_hw_vpath_msix_clear - Clear MSIX Vector.
2242  * @vp: Virtual Path handle.
2243  * @msix_id:  MSI ID
2244  *
2245  * The function clears the msix interrupt for the given msix_id
2246  *
2247  * Returns: 0,
2248  * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2249  * status.
2250  * See also:
2251  */
2252 void vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
2253 {
2254         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2255
2256         if ((hldev->config.intr_mode == VXGE_HW_INTR_MODE_MSIX_ONE_SHOT))
2257                 __vxge_hw_pio_mem_write32_upper(
2258                         (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2259                         &hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
2260         else
2261                 __vxge_hw_pio_mem_write32_upper(
2262                         (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2263                         &hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);
2264 }
2265
2266 /**
2267  * vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector.
2268  * @vp: Virtual Path handle.
2269  * @msix_id:  MSI ID
2270  *
2271  * The function unmasks the msix interrupt for the given msix_id
2272  *
2273  * Returns: 0,
2274  * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2275  * status.
2276  * See also:
2277  */
2278 void
2279 vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2280 {
2281         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2282         __vxge_hw_pio_mem_write32_upper(
2283                         (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
2284                         &hldev->common_reg->clear_msix_mask_vect[msix_id%4]);
2285 }
2286
2287 /**
2288  * vxge_hw_vpath_inta_mask_tx_rx - Mask Tx and Rx interrupts.
2289  * @vp: Virtual Path handle.
2290  *
2291  * Mask Tx and Rx vpath interrupts.
2292  *
2293  * See also: vxge_hw_vpath_inta_mask_tx_rx()
2294  */
2295 void vxge_hw_vpath_inta_mask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2296 {
2297         u64     tim_int_mask0[4] = {[0 ...3] = 0};
2298         u32     tim_int_mask1[4] = {[0 ...3] = 0};
2299         u64     val64;
2300         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2301
2302         VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2303                 tim_int_mask1, vp->vpath->vp_id);
2304
2305         val64 = readq(&hldev->common_reg->tim_int_mask0);
2306
2307         if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2308                 (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2309                 writeq((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2310                         tim_int_mask0[VXGE_HW_VPATH_INTR_RX] | val64),
2311                         &hldev->common_reg->tim_int_mask0);
2312         }
2313
2314         val64 = readl(&hldev->common_reg->tim_int_mask1);
2315
2316         if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
2317                 (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
2318                 __vxge_hw_pio_mem_write32_upper(
2319                         (tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
2320                         tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64),
2321                         &hldev->common_reg->tim_int_mask1);
2322         }
2323 }
2324
2325 /**
2326  * vxge_hw_vpath_inta_unmask_tx_rx - Unmask Tx and Rx interrupts.
2327  * @vp: Virtual Path handle.
2328  *
2329  * Unmask Tx and Rx vpath interrupts.
2330  *
2331  * See also: vxge_hw_vpath_inta_mask_tx_rx()
2332  */
2333 void vxge_hw_vpath_inta_unmask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2334 {
2335         u64     tim_int_mask0[4] = {[0 ...3] = 0};
2336         u32     tim_int_mask1[4] = {[0 ...3] = 0};
2337         u64     val64;
2338         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2339
2340         VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2341                 tim_int_mask1, vp->vpath->vp_id);
2342
2343         val64 = readq(&hldev->common_reg->tim_int_mask0);
2344
2345         if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2346            (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2347                 writeq((~(tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2348                         tim_int_mask0[VXGE_HW_VPATH_INTR_RX])) & val64,
2349                         &hldev->common_reg->tim_int_mask0);
2350         }
2351
2352         if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
2353            (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
2354                 __vxge_hw_pio_mem_write32_upper(
2355                         (~(tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
2356                           tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64,
2357                         &hldev->common_reg->tim_int_mask1);
2358         }
2359 }
2360
2361 /**
2362  * vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed
2363  * descriptors and process the same.
2364  * @ring: Handle to the ring object used for receive
2365  *
2366  * The function polls the Rx for the completed  descriptors and calls
2367  * the driver via supplied completion   callback.
2368  *
2369  * Returns: VXGE_HW_OK, if the polling is completed successful.
2370  * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
2371  * descriptors available which are yet to be processed.
2372  *
2373  * See also: vxge_hw_vpath_poll_rx()
2374  */
2375 enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ring)
2376 {
2377         u8 t_code;
2378         enum vxge_hw_status status = VXGE_HW_OK;
2379         void *first_rxdh;
2380         int new_count = 0;
2381
2382         ring->cmpl_cnt = 0;
2383
2384         status = vxge_hw_ring_rxd_next_completed(ring, &first_rxdh, &t_code);
2385         if (status == VXGE_HW_OK)
2386                 ring->callback(ring, first_rxdh,
2387                         t_code, ring->channel.userdata);
2388
2389         if (ring->cmpl_cnt != 0) {
2390                 ring->doorbell_cnt += ring->cmpl_cnt;
2391                 if (ring->doorbell_cnt >= ring->rxds_limit) {
2392                         /*
2393                          * Each RxD is of 4 qwords, update the number of
2394                          * qwords replenished
2395                          */
2396                         new_count = (ring->doorbell_cnt * 4);
2397
2398                         /* For each block add 4 more qwords */
2399                         ring->total_db_cnt += ring->doorbell_cnt;
2400                         if (ring->total_db_cnt >= ring->rxds_per_block) {
2401                                 new_count += 4;
2402                                 /* Reset total count */
2403                                 ring->total_db_cnt %= ring->rxds_per_block;
2404                         }
2405                         writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(new_count),
2406                                 &ring->vp_reg->prc_rxd_doorbell);
2407                         readl(&ring->common_reg->titan_general_int_status);
2408                         ring->doorbell_cnt = 0;
2409                 }
2410         }
2411
2412         return status;
2413 }
2414
2415 /**
2416  * vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process
2417  * the same.
2418  * @fifo: Handle to the fifo object used for non offload send
2419  *
2420  * The function polls the Tx for the completed descriptors and calls
2421  * the driver via supplied completion callback.
2422  *
2423  * Returns: VXGE_HW_OK, if the polling is completed successful.
2424  * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
2425  * descriptors available which are yet to be processed.
2426  */
2427 enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo,
2428                                         struct sk_buff ***skb_ptr, int nr_skb,
2429                                         int *more)
2430 {
2431         enum vxge_hw_fifo_tcode t_code;
2432         void *first_txdlh;
2433         enum vxge_hw_status status = VXGE_HW_OK;
2434         struct __vxge_hw_channel *channel;
2435
2436         channel = &fifo->channel;
2437
2438         status = vxge_hw_fifo_txdl_next_completed(fifo,
2439                                 &first_txdlh, &t_code);
2440         if (status == VXGE_HW_OK)
2441                 if (fifo->callback(fifo, first_txdlh, t_code,
2442                         channel->userdata, skb_ptr, nr_skb, more) != VXGE_HW_OK)
2443                         status = VXGE_HW_COMPLETIONS_REMAIN;
2444
2445         return status;
2446 }