drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/string.h>
  41 #include <linux/etherdevice.h>
  42 #include "qed.h"
  43 #include "qed_cxt.h"
  44 #include "qed_dcbx.h"
  45 #include "qed_hsi.h"
  46 #include "qed_hw.h"
  47 #include "qed_mcp.h"
  48 #include "qed_reg_addr.h"
  49 #include "qed_sriov.h"
  50
  51 #define QED_MCP_RESP_ITER_US    10
  52
  53 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  54 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  55
  56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  57         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  58                _val)
  59
  60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  61         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  62
  63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  64         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  65                      offsetof(struct public_drv_mb, _field), _val)
  66
  67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  68         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  69                      offsetof(struct public_drv_mb, _field))
  70
  71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  72                   DRV_ID_PDA_COMP_VER_SHIFT)
  73
  74 #define MCP_BYTES_PER_MBIT_SHIFT 17
  75
  76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  77 {
  78         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  79                 return false;
  80         return true;
  81 }
  82
  83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  84 {
  85         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  86                                         PUBLIC_PORT);
  87         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  88
  89         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  90                                                    MFW_PORT(p_hwfn));
  91         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  92                    "port_addr = 0x%x, port_id 0x%02x\n",
  93                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  94 }
  95
  96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  97 {
  98         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  99         u32 tmp, i;
 100
 101         if (!p_hwfn->mcp_info->public_base)
 102                 return;
 103
 104         for (i = 0; i < length; i++) {
 105                 tmp = qed_rd(p_hwfn, p_ptt,
 106                              p_hwfn->mcp_info->mfw_mb_addr +
 107                              (i << 2) + sizeof(u32));
 108
 109                 /* The MB data is actually BE; Need to force it to cpu */
 110                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
 111                         be32_to_cpu((__force __be32)tmp);
 112         }
 113 }
 114
 115 struct qed_mcp_cmd_elem {
 116         struct list_head list;
 117         struct qed_mcp_mb_params *p_mb_params;
 118         u16 expected_seq_num;
 119         bool b_is_completed;
 120 };
 121
 122 /* Must be called while cmd_lock is acquired */
 123 static struct qed_mcp_cmd_elem *
 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
 125                      struct qed_mcp_mb_params *p_mb_params,
 126                      u16 expected_seq_num)
 127 {
 128         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 129
 130         p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
 131         if (!p_cmd_elem)
 132                 goto out;
 133
 134         p_cmd_elem->p_mb_params = p_mb_params;
 135         p_cmd_elem->expected_seq_num = expected_seq_num;
 136         list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 137 out:
 138         return p_cmd_elem;
 139 }
 140
 141 /* Must be called while cmd_lock is acquired */
 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
 143                                  struct qed_mcp_cmd_elem *p_cmd_elem)
 144 {
 145         list_del(&p_cmd_elem->list);
 146         kfree(p_cmd_elem);
 147 }
 148
 149 /* Must be called while cmd_lock is acquired */
 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
 151                                                      u16 seq_num)
 152 {
 153         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 154
 155         list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
 156                 if (p_cmd_elem->expected_seq_num == seq_num)
 157                         return p_cmd_elem;
 158         }
 159
 160         return NULL;
 161 }
 162
 163 int qed_mcp_free(struct qed_hwfn *p_hwfn)
 164 {
 165         if (p_hwfn->mcp_info) {
 166                 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
 167
 168                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
 169                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
 170
 171                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 172                 list_for_each_entry_safe(p_cmd_elem,
 173                                          p_tmp,
 174                                          &p_hwfn->mcp_info->cmd_list, list) {
 175                         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 176                 }
 177                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 178         }
 179
 180         kfree(p_hwfn->mcp_info);
 181         p_hwfn->mcp_info = NULL;
 182
 183         return 0;
 184 }
 185
 186 /* Maximum of 1 sec to wait for the SHMEM ready indication */
 187 #define QED_MCP_SHMEM_RDY_MAX_RETRIES   20
 188 #define QED_MCP_SHMEM_RDY_ITER_MS       50
 189
 190 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 191 {
 192         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 193         u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES;
 194         u8 msec = QED_MCP_SHMEM_RDY_ITER_MS;
 195         u32 drv_mb_offsize, mfw_mb_offsize;
 196         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 197
 198         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 199         if (!p_info->public_base) {
 200                 DP_NOTICE(p_hwfn,
 201                           "The address of the MCP scratch-pad is not configured\n");
 202                 return -EINVAL;
 203         }
 204
 205         p_info->public_base |= GRCBASE_MCP;
 206
 207         /* Get the MFW MB address and number of supported messages */
 208         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 209                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 210                                                      PUBLIC_MFW_MB));
 211         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 212         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt,
 213                                             p_info->mfw_mb_addr +
 214                                             offsetof(struct public_mfw_mb,
 215                                                      sup_msgs));
 216
 217         /* The driver can notify that there was an MCP reset, and might read the
 218          * SHMEM values before the MFW has completed initializing them.
 219          * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a
 220          * data ready indication.
 221          */
 222         while (!p_info->mfw_mb_length && --cnt) {
 223                 msleep(msec);
 224                 p_info->mfw_mb_length =
 225                         (u16)qed_rd(p_hwfn, p_ptt,
 226                                     p_info->mfw_mb_addr +
 227                                     offsetof(struct public_mfw_mb, sup_msgs));
 228         }
 229
 230         if (!cnt) {
 231                 DP_NOTICE(p_hwfn,
 232                           "Failed to get the SHMEM ready notification after %d msec\n",
 233                           QED_MCP_SHMEM_RDY_MAX_RETRIES * msec);
 234                 return -EBUSY;
 235         }
 236
 237         /* Calculate the driver and MFW mailbox address */
 238         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 239                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 240                                                      PUBLIC_DRV_MB));
 241         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 242         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 243                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 244                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 245
 246         /* Get the current driver mailbox sequence before sending
 247          * the first command
 248          */
 249         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 250                              DRV_MSG_SEQ_NUMBER_MASK;
 251
 252         /* Get current FW pulse sequence */
 253         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 254                                 DRV_PULSE_SEQ_MASK;
 255
 256         p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 257
 258         return 0;
 259 }
 260
 261 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 262 {
 263         struct qed_mcp_info *p_info;
 264         u32 size;
 265
 266         /* Allocate mcp_info structure */
 267         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 268         if (!p_hwfn->mcp_info)
 269                 goto err;
 270         p_info = p_hwfn->mcp_info;
 271
 272         /* Initialize the MFW spinlock */
 273         spin_lock_init(&p_info->cmd_lock);
 274         spin_lock_init(&p_info->link_lock);
 275
 276         INIT_LIST_HEAD(&p_info->cmd_list);
 277
 278         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 279                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 280                 /* Do not free mcp_info here, since public_base indicate that
 281                  * the MCP is not initialized
 282                  */
 283                 return 0;
 284         }
 285
 286         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 287         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 288         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 289         if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
 290                 goto err;
 291
 292         return 0;
 293
 294 err:
 295         qed_mcp_free(p_hwfn);
 296         return -ENOMEM;
 297 }
 298
 299 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
 300                                    struct qed_ptt *p_ptt)
 301 {
 302         u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 303
 304         /* Use MCP history register to check if MCP reset occurred between init
 305          * time and now.
 306          */
 307         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 308                 DP_VERBOSE(p_hwfn,
 309                            QED_MSG_SP,
 310                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 311                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 312
 313                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 314                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 315         }
 316 }
 317
 318 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 319 {
 320         u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0;
 321         int rc = 0;
 322
 323         if (p_hwfn->mcp_info->b_block_cmd) {
 324                 DP_NOTICE(p_hwfn,
 325                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 326                 return -EBUSY;
 327         }
 328
 329         /* Ensure that only a single thread is accessing the mailbox */
 330         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 331
 332         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 333
 334         /* Set drv command along with the updated sequence */
 335         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 336         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 337         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 338
 339         do {
 340                 /* Wait for MFW response */
 341                 udelay(delay);
 342                 /* Give the FW up to 500 second (50*1000*10usec) */
 343         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 344                                               MISCS_REG_GENERIC_POR_0)) &&
 345                  (cnt++ < QED_MCP_RESET_RETRIES));
 346
 347         if (org_mcp_reset_seq !=
 348             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 349                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 350                            "MCP was reset after %d usec\n", cnt * delay);
 351         } else {
 352                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 353                 rc = -EAGAIN;
 354         }
 355
 356         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 357
 358         return rc;
 359 }
 360
 361 /* Must be called while cmd_lock is acquired */
 362 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
 363 {
 364         struct qed_mcp_cmd_elem *p_cmd_elem;
 365
 366         /* There is at most one pending command at a certain time, and if it
 367          * exists - it is placed at the HEAD of the list.
 368          */
 369         if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
 370                 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
 371                                               struct qed_mcp_cmd_elem, list);
 372                 return !p_cmd_elem->b_is_completed;
 373         }
 374
 375         return false;
 376 }
 377
 378 /* Must be called while cmd_lock is acquired */
 379 static int
 380 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 381 {
 382         struct qed_mcp_mb_params *p_mb_params;
 383         struct qed_mcp_cmd_elem *p_cmd_elem;
 384         u32 mcp_resp;
 385         u16 seq_num;
 386
 387         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 388         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 389
 390         /* Return if no new non-handled response has been received */
 391         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 392                 return -EAGAIN;
 393
 394         p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
 395         if (!p_cmd_elem) {
 396                 DP_ERR(p_hwfn,
 397                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 398                        seq_num);
 399                 return -EINVAL;
 400         }
 401
 402         p_mb_params = p_cmd_elem->p_mb_params;
 403
 404         /* Get the MFW response along with the sequence number */
 405         p_mb_params->mcp_resp = mcp_resp;
 406
 407         /* Get the MFW param */
 408         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 409
 410         /* Get the union data */
 411         if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
 412                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 413                                       offsetof(struct public_drv_mb,
 414                                                union_data);
 415                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 416                                 union_data_addr, p_mb_params->data_dst_size);
 417         }
 418
 419         p_cmd_elem->b_is_completed = true;
 420
 421         return 0;
 422 }
 423
 424 /* Must be called while cmd_lock is acquired */
 425 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 426                                     struct qed_ptt *p_ptt,
 427                                     struct qed_mcp_mb_params *p_mb_params,
 428                                     u16 seq_num)
 429 {
 430         union drv_union_data union_data;
 431         u32 union_data_addr;
 432
 433         /* Set the union data */
 434         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 435                           offsetof(struct public_drv_mb, union_data);
 436         memset(&union_data, 0, sizeof(union_data));
 437         if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
 438                 memcpy(&union_data, p_mb_params->p_data_src,
 439                        p_mb_params->data_src_size);
 440         qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 441                       sizeof(union_data));
 442
 443         /* Set the drv param */
 444         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 445
 446         /* Set the drv command along with the sequence number */
 447         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 448
 449         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 450                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 451                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 452 }
 453
 454 static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd)
 455 {
 456         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 457
 458         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 459                 block_cmd ? "Block" : "Unblock");
 460 }
 461
 462 static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn,
 463                                    struct qed_ptt *p_ptt)
 464 {
 465         u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2;
 466         u32 delay = QED_MCP_RESP_ITER_US;
 467
 468         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
 469         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
 470         cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 471         udelay(delay);
 472         cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 473         udelay(delay);
 474         cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 475
 476         DP_NOTICE(p_hwfn,
 477                   "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n",
 478                   cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2);
 479 }
 480
 481 static int
 482 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 483                        struct qed_ptt *p_ptt,
 484                        struct qed_mcp_mb_params *p_mb_params,
 485                        u32 max_retries, u32 usecs)
 486 {
 487         u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000);
 488         struct qed_mcp_cmd_elem *p_cmd_elem;
 489         u16 seq_num;
 490         int rc = 0;
 491
 492         /* Wait until the mailbox is non-occupied */
 493         do {
 494                 /* Exit the loop if there is no pending command, or if the
 495                  * pending command is completed during this iteration.
 496                  * The spinlock stays locked until the command is sent.
 497                  */
 498
 499                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 500
 501                 if (!qed_mcp_has_pending_cmd(p_hwfn)) {
 502                         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 503                         break;
 504                 }
 505
 506                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 507                 if (!rc) {
 508                         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 509                         break;
 510                 } else if (rc != -EAGAIN) {
 511                         goto err;
 512                 }
 513
 514                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 515
 516                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 517                         msleep(msecs);
 518                 else
 519                         udelay(usecs);
 520         } while (++cnt < max_retries);
 521
 522         if (cnt >= max_retries) {
 523                 DP_NOTICE(p_hwfn,
 524                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 525                           p_mb_params->cmd, p_mb_params->param);
 526                 return -EAGAIN;
 527         }
 528
 529         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 530
 531         /* Send the mailbox command */
 532         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 533         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 534         p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 535         if (!p_cmd_elem) {
 536                 rc = -ENOMEM;
 537                 goto err;
 538         }
 539
 540         __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 541         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 542
 543         /* Wait for the MFW response */
 544         do {
 545                 /* Exit the loop if the command is already completed, or if the
 546                  * command is completed during this iteration.
 547                  * The spinlock stays locked until the list element is removed.
 548                  */
 549
 550                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 551                         msleep(msecs);
 552                 else
 553                         udelay(usecs);
 554
 555                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 556
 557                 if (p_cmd_elem->b_is_completed) {
 558                         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 559                         break;
 560                 }
 561
 562                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 563                 if (!rc) {
 564                         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 565                         break;
 566                 } else if (rc != -EAGAIN) {
 567                         goto err;
 568                 }
 569
 570                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 571         } while (++cnt < max_retries);
 572
 573         if (cnt >= max_retries) {
 574                 DP_NOTICE(p_hwfn,
 575                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 576                           p_mb_params->cmd, p_mb_params->param);
 577                 qed_mcp_print_cpu_info(p_hwfn, p_ptt);
 578
 579                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 580                 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 581                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 582
 583                 if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK))
 584                         qed_mcp_cmd_set_blocking(p_hwfn, true);
 585
 586                 return -EAGAIN;
 587         }
 588
 589         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 590         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 591         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 592
 593         DP_VERBOSE(p_hwfn,
 594                    QED_MSG_SP,
 595                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 596                    p_mb_params->mcp_resp,
 597                    p_mb_params->mcp_param,
 598                    (cnt * usecs) / 1000, (cnt * usecs) % 1000);
 599
 600         /* Clear the sequence number from the MFW response */
 601         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 602
 603         return 0;
 604
 605 err:
 606         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 607         return rc;
 608 }
 609
 610 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 611                                  struct qed_ptt *p_ptt,
 612                                  struct qed_mcp_mb_params *p_mb_params)
 613 {
 614         size_t union_data_size = sizeof(union drv_union_data);
 615         u32 max_retries = QED_DRV_MB_MAX_RETRIES;
 616         u32 usecs = QED_MCP_RESP_ITER_US;
 617
 618         /* MCP not initialized */
 619         if (!qed_mcp_is_init(p_hwfn)) {
 620                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 621                 return -EBUSY;
 622         }
 623
 624         if (p_hwfn->mcp_info->b_block_cmd) {
 625                 DP_NOTICE(p_hwfn,
 626                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 627                           p_mb_params->cmd, p_mb_params->param);
 628                 return -EBUSY;
 629         }
 630
 631         if (p_mb_params->data_src_size > union_data_size ||
 632             p_mb_params->data_dst_size > union_data_size) {
 633                 DP_ERR(p_hwfn,
 634                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 635                        p_mb_params->data_src_size,
 636                        p_mb_params->data_dst_size, union_data_size);
 637                 return -EINVAL;
 638         }
 639
 640         if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) {
 641                 max_retries = DIV_ROUND_UP(max_retries, 1000);
 642                 usecs *= 1000;
 643         }
 644
 645         return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 646                                       usecs);
 647 }
 648
 649 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 650                 struct qed_ptt *p_ptt,
 651                 u32 cmd,
 652                 u32 param,
 653                 u32 *o_mcp_resp,
 654                 u32 *o_mcp_param)
 655 {
 656         struct qed_mcp_mb_params mb_params;
 657         int rc;
 658
 659         memset(&mb_params, 0, sizeof(mb_params));
 660         mb_params.cmd = cmd;
 661         mb_params.param = param;
 662
 663         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 664         if (rc)
 665                 return rc;
 666
 667         *o_mcp_resp = mb_params.mcp_resp;
 668         *o_mcp_param = mb_params.mcp_param;
 669
 670         return 0;
 671 }
 672
 673 static int
 674 qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
 675                    struct qed_ptt *p_ptt,
 676                    u32 cmd,
 677                    u32 param,
 678                    u32 *o_mcp_resp,
 679                    u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
 680 {
 681         struct qed_mcp_mb_params mb_params;
 682         int rc;
 683
 684         memset(&mb_params, 0, sizeof(mb_params));
 685         mb_params.cmd = cmd;
 686         mb_params.param = param;
 687         mb_params.p_data_src = i_buf;
 688         mb_params.data_src_size = (u8)i_txn_size;
 689         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 690         if (rc)
 691                 return rc;
 692
 693         *o_mcp_resp = mb_params.mcp_resp;
 694         *o_mcp_param = mb_params.mcp_param;
 695
 696         /* nvm_info needs to be updated */
 697         p_hwfn->nvm_info.valid = false;
 698
 699         return 0;
 700 }
 701
 702 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 703                        struct qed_ptt *p_ptt,
 704                        u32 cmd,
 705                        u32 param,
 706                        u32 *o_mcp_resp,
 707                        u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
 708 {
 709         struct qed_mcp_mb_params mb_params;
 710         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 711         int rc;
 712
 713         memset(&mb_params, 0, sizeof(mb_params));
 714         mb_params.cmd = cmd;
 715         mb_params.param = param;
 716         mb_params.p_data_dst = raw_data;
 717
 718         /* Use the maximal value since the actual one is part of the response */
 719         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 720
 721         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 722         if (rc)
 723                 return rc;
 724
 725         *o_mcp_resp = mb_params.mcp_resp;
 726         *o_mcp_param = mb_params.mcp_param;
 727
 728         *o_txn_size = *o_mcp_param;
 729         memcpy(o_buf, raw_data, *o_txn_size);
 730
 731         return 0;
 732 }
 733
 734 static bool
 735 qed_mcp_can_force_load(u8 drv_role,
 736                        u8 exist_drv_role,
 737                        enum qed_override_force_load override_force_load)
 738 {
 739         bool can_force_load = false;
 740
 741         switch (override_force_load) {
 742         case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
 743                 can_force_load = true;
 744                 break;
 745         case QED_OVERRIDE_FORCE_LOAD_NEVER:
 746                 can_force_load = false;
 747                 break;
 748         default:
 749                 can_force_load = (drv_role == DRV_ROLE_OS &&
 750                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 751                                  (drv_role == DRV_ROLE_KDUMP &&
 752                                   exist_drv_role == DRV_ROLE_OS);
 753                 break;
 754         }
 755
 756         return can_force_load;
 757 }
 758
 759 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
 760                                    struct qed_ptt *p_ptt)
 761 {
 762         u32 resp = 0, param = 0;
 763         int rc;
 764
 765         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 766                          &resp, &param);
 767         if (rc)
 768                 DP_NOTICE(p_hwfn,
 769                           "Failed to send cancel load request, rc = %d\n", rc);
 770
 771         return rc;
 772 }
 773
 774 #define CONFIG_QEDE_BITMAP_IDX          BIT(0)
 775 #define CONFIG_QED_SRIOV_BITMAP_IDX     BIT(1)
 776 #define CONFIG_QEDR_BITMAP_IDX          BIT(2)
 777 #define CONFIG_QEDF_BITMAP_IDX          BIT(4)
 778 #define CONFIG_QEDI_BITMAP_IDX          BIT(5)
 779 #define CONFIG_QED_LL2_BITMAP_IDX       BIT(6)
 780
 781 static u32 qed_get_config_bitmap(void)
 782 {
 783         u32 config_bitmap = 0x0;
 784
 785         if (IS_ENABLED(CONFIG_QEDE))
 786                 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
 787
 788         if (IS_ENABLED(CONFIG_QED_SRIOV))
 789                 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
 790
 791         if (IS_ENABLED(CONFIG_QED_RDMA))
 792                 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
 793
 794         if (IS_ENABLED(CONFIG_QED_FCOE))
 795                 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
 796
 797         if (IS_ENABLED(CONFIG_QED_ISCSI))
 798                 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
 799
 800         if (IS_ENABLED(CONFIG_QED_LL2))
 801                 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
 802
 803         return config_bitmap;
 804 }
 805
 806 struct qed_load_req_in_params {
 807         u8 hsi_ver;
 808 #define QED_LOAD_REQ_HSI_VER_DEFAULT    0
 809 #define QED_LOAD_REQ_HSI_VER_1          1
 810         u32 drv_ver_0;
 811         u32 drv_ver_1;
 812         u32 fw_ver;
 813         u8 drv_role;
 814         u8 timeout_val;
 815         u8 force_cmd;
 816         bool avoid_eng_reset;
 817 };
 818
 819 struct qed_load_req_out_params {
 820         u32 load_code;
 821         u32 exist_drv_ver_0;
 822         u32 exist_drv_ver_1;
 823         u32 exist_fw_ver;
 824         u8 exist_drv_role;
 825         u8 mfw_hsi_ver;
 826         bool drv_exists;
 827 };
 828
 829 static int
 830 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 831                    struct qed_ptt *p_ptt,
 832                    struct qed_load_req_in_params *p_in_params,
 833                    struct qed_load_req_out_params *p_out_params)
 834 {
 835         struct qed_mcp_mb_params mb_params;
 836         struct load_req_stc load_req;
 837         struct load_rsp_stc load_rsp;
 838         u32 hsi_ver;
 839         int rc;
 840
 841         memset(&load_req, 0, sizeof(load_req));
 842         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 843         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 844         load_req.fw_ver = p_in_params->fw_ver;
 845         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 846         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 847                           p_in_params->timeout_val);
 848         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 849                           p_in_params->force_cmd);
 850         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 851                           p_in_params->avoid_eng_reset);
 852
 853         hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
 854                   DRV_ID_MCP_HSI_VER_CURRENT :
 855                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 856
 857         memset(&mb_params, 0, sizeof(mb_params));
 858         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 859         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
 860         mb_params.p_data_src = &load_req;
 861         mb_params.data_src_size = sizeof(load_req);
 862         mb_params.p_data_dst = &load_rsp;
 863         mb_params.data_dst_size = sizeof(load_rsp);
 864         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
 865
 866         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 867                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 868                    mb_params.param,
 869                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 870                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 871                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 872                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 873
 874         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
 875                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 876                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 877                            load_req.drv_ver_0,
 878                            load_req.drv_ver_1,
 879                            load_req.fw_ver,
 880                            load_req.misc0,
 881                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 882                            QED_MFW_GET_FIELD(load_req.misc0,
 883                                              LOAD_REQ_LOCK_TO),
 884                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 885                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 886         }
 887
 888         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 889         if (rc) {
 890                 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
 891                 return rc;
 892         }
 893
 894         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 895                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 896         p_out_params->load_code = mb_params.mcp_resp;
 897
 898         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 899             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 900                 DP_VERBOSE(p_hwfn,
 901                            QED_MSG_SP,
 902                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 903                            load_rsp.drv_ver_0,
 904                            load_rsp.drv_ver_1,
 905                            load_rsp.fw_ver,
 906                            load_rsp.misc0,
 907                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 908                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 909                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 910
 911                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 912                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 913                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 914                 p_out_params->exist_drv_role =
 915                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 916                 p_out_params->mfw_hsi_ver =
 917                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 918                 p_out_params->drv_exists =
 919                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 920                     LOAD_RSP_FLAGS0_DRV_EXISTS;
 921         }
 922
 923         return 0;
 924 }
 925
 926 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
 927                                   enum qed_drv_role drv_role,
 928                                   u8 *p_mfw_drv_role)
 929 {
 930         switch (drv_role) {
 931         case QED_DRV_ROLE_OS:
 932                 *p_mfw_drv_role = DRV_ROLE_OS;
 933                 break;
 934         case QED_DRV_ROLE_KDUMP:
 935                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 936                 break;
 937         default:
 938                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 939                 return -EINVAL;
 940         }
 941
 942         return 0;
 943 }
 944
 945 enum qed_load_req_force {
 946         QED_LOAD_REQ_FORCE_NONE,
 947         QED_LOAD_REQ_FORCE_PF,
 948         QED_LOAD_REQ_FORCE_ALL,
 949 };
 950
 951 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
 952
 953                                   enum qed_load_req_force force_cmd,
 954                                   u8 *p_mfw_force_cmd)
 955 {
 956         switch (force_cmd) {
 957         case QED_LOAD_REQ_FORCE_NONE:
 958                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 959                 break;
 960         case QED_LOAD_REQ_FORCE_PF:
 961                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 962                 break;
 963         case QED_LOAD_REQ_FORCE_ALL:
 964                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 965                 break;
 966         }
 967 }
 968
 969 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 970                      struct qed_ptt *p_ptt,
 971                      struct qed_load_req_params *p_params)
 972 {
 973         struct qed_load_req_out_params out_params;
 974         struct qed_load_req_in_params in_params;
 975         u8 mfw_drv_role, mfw_force_cmd;
 976         int rc;
 977
 978         memset(&in_params, 0, sizeof(in_params));
 979         in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
 980         in_params.drv_ver_0 = QED_VERSION;
 981         in_params.drv_ver_1 = qed_get_config_bitmap();
 982         in_params.fw_ver = STORM_FW_VERSION;
 983         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 984         if (rc)
 985                 return rc;
 986
 987         in_params.drv_role = mfw_drv_role;
 988         in_params.timeout_val = p_params->timeout_val;
 989         qed_get_mfw_force_cmd(p_hwfn,
 990                               QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 991
 992         in_params.force_cmd = mfw_force_cmd;
 993         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 994
 995         memset(&out_params, 0, sizeof(out_params));
 996         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 997         if (rc)
 998                 return rc;
 999
1000         /* First handle cases where another load request should/might be sent:
1001          * - MFW expects the old interface [HSI version = 1]
1002          * - MFW responds that a force load request is required
1003          */
1004         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
1005                 DP_INFO(p_hwfn,
1006                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
1007
1008                 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
1009                 memset(&out_params, 0, sizeof(out_params));
1010                 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
1011                 if (rc)
1012                         return rc;
1013         } else if (out_params.load_code ==
1014                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
1015                 if (qed_mcp_can_force_load(in_params.drv_role,
1016                                            out_params.exist_drv_role,
1017                                            p_params->override_force_load)) {
1018                         DP_INFO(p_hwfn,
1019                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
1020                                 in_params.drv_role, in_params.fw_ver,
1021                                 in_params.drv_ver_0, in_params.drv_ver_1,
1022                                 out_params.exist_drv_role,
1023                                 out_params.exist_fw_ver,
1024                                 out_params.exist_drv_ver_0,
1025                                 out_params.exist_drv_ver_1);
1026
1027                         qed_get_mfw_force_cmd(p_hwfn,
1028                                               QED_LOAD_REQ_FORCE_ALL,
1029                                               &mfw_force_cmd);
1030
1031                         in_params.force_cmd = mfw_force_cmd;
1032                         memset(&out_params, 0, sizeof(out_params));
1033                         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
1034                                                 &out_params);
1035                         if (rc)
1036                                 return rc;
1037                 } else {
1038                         DP_NOTICE(p_hwfn,
1039                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1040                                   in_params.drv_role, in_params.fw_ver,
1041                                   in_params.drv_ver_0, in_params.drv_ver_1,
1042                                   out_params.exist_drv_role,
1043                                   out_params.exist_fw_ver,
1044                                   out_params.exist_drv_ver_0,
1045                                   out_params.exist_drv_ver_1);
1046                         DP_NOTICE(p_hwfn,
1047                                   "Avoid sending a force load request to prevent disruption of active PFs\n");
1048
1049                         qed_mcp_cancel_load_req(p_hwfn, p_ptt);
1050                         return -EBUSY;
1051                 }
1052         }
1053
1054         /* Now handle the other types of responses.
1055          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1056          * expected here after the additional revised load requests were sent.
1057          */
1058         switch (out_params.load_code) {
1059         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1060         case FW_MSG_CODE_DRV_LOAD_PORT:
1061         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1062                 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
1063                     out_params.drv_exists) {
1064                         /* The role and fw/driver version match, but the PF is
1065                          * already loaded and has not been unloaded gracefully.
1066                          */
1067                         DP_NOTICE(p_hwfn,
1068                                   "PF is already loaded\n");
1069                         return -EINVAL;
1070                 }
1071                 break;
1072         default:
1073                 DP_NOTICE(p_hwfn,
1074                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1075                           out_params.load_code);
1076                 return -EBUSY;
1077         }
1078
1079         p_params->load_code = out_params.load_code;
1080
1081         return 0;
1082 }
1083
1084 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1085 {
1086         struct qed_mcp_mb_params mb_params;
1087         u32 wol_param;
1088
1089         switch (p_hwfn->cdev->wol_config) {
1090         case QED_OV_WOL_DISABLED:
1091                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
1092                 break;
1093         case QED_OV_WOL_ENABLED:
1094                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
1095                 break;
1096         default:
1097                 DP_NOTICE(p_hwfn,
1098                           "Unknown WoL configuration %02x\n",
1099                           p_hwfn->cdev->wol_config);
1100                 /* Fallthrough */
1101         case QED_OV_WOL_DEFAULT:
1102                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1103         }
1104
1105         memset(&mb_params, 0, sizeof(mb_params));
1106         mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ;
1107         mb_params.param = wol_param;
1108         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
1109
1110         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1111 }
1112
1113 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1114 {
1115         struct qed_mcp_mb_params mb_params;
1116         struct mcp_mac wol_mac;
1117
1118         memset(&mb_params, 0, sizeof(mb_params));
1119         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1120
1121         /* Set the primary MAC if WoL is enabled */
1122         if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
1123                 u8 *p_mac = p_hwfn->cdev->wol_mac;
1124
1125                 memset(&wol_mac, 0, sizeof(wol_mac));
1126                 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
1127                 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
1128                                     p_mac[4] << 8 | p_mac[5];
1129
1130                 DP_VERBOSE(p_hwfn,
1131                            (QED_MSG_SP | NETIF_MSG_IFDOWN),
1132                            "Setting WoL MAC: %pM --> [%08x,%08x]\n",
1133                            p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
1134
1135                 mb_params.p_data_src = &wol_mac;
1136                 mb_params.data_src_size = sizeof(wol_mac);
1137         }
1138
1139         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1140 }
1141
1142 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1143                                   struct qed_ptt *p_ptt)
1144 {
1145         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1146                                         PUBLIC_PATH);
1147         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1148         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1149                                      QED_PATH_ID(p_hwfn));
1150         u32 disabled_vfs[VF_MAX_STATIC / 32];
1151         int i;
1152
1153         DP_VERBOSE(p_hwfn,
1154                    QED_MSG_SP,
1155                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1156                    mfw_path_offsize, path_addr);
1157
1158         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1159                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1160                                          path_addr +
1161                                          offsetof(struct public_path,
1162                                                   mcp_vf_disabled) +
1163                                          sizeof(u32) * i);
1164                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1165                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1166                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1167         }
1168
1169         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1170                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1171 }
1172
1173 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1174                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1175 {
1176         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1177                                         PUBLIC_FUNC);
1178         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1179         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1180                                      MCP_PF_ID(p_hwfn));
1181         struct qed_mcp_mb_params mb_params;
1182         int rc;
1183         int i;
1184
1185         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1186                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1187                            "Acking VFs [%08x,...,%08x] - %08x\n",
1188                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1189
1190         memset(&mb_params, 0, sizeof(mb_params));
1191         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1192         mb_params.p_data_src = vfs_to_ack;
1193         mb_params.data_src_size = VF_MAX_STATIC / 8;
1194         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1195         if (rc) {
1196                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1197                 return -EBUSY;
1198         }
1199
1200         /* Clear the ACK bits */
1201         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1202                 qed_wr(p_hwfn, p_ptt,
1203                        func_addr +
1204                        offsetof(struct public_func, drv_ack_vf_disabled) +
1205                        i * sizeof(u32), 0);
1206
1207         return rc;
1208 }
1209
1210 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1211                                               struct qed_ptt *p_ptt)
1212 {
1213         u32 transceiver_state;
1214
1215         transceiver_state = qed_rd(p_hwfn, p_ptt,
1216                                    p_hwfn->mcp_info->port_addr +
1217                                    offsetof(struct public_port,
1218                                             transceiver_data));
1219
1220         DP_VERBOSE(p_hwfn,
1221                    (NETIF_MSG_HW | QED_MSG_SP),
1222                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1223                    transceiver_state,
1224                    (u32)(p_hwfn->mcp_info->port_addr +
1225                           offsetof(struct public_port, transceiver_data)));
1226
1227         transceiver_state = GET_FIELD(transceiver_state,
1228                                       ETH_TRANSCEIVER_STATE);
1229
1230         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1231                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1232         else
1233                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1234 }
1235
1236 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1237                                     struct qed_ptt *p_ptt,
1238                                     struct qed_mcp_link_state *p_link)
1239 {
1240         u32 eee_status, val;
1241
1242         p_link->eee_adv_caps = 0;
1243         p_link->eee_lp_adv_caps = 0;
1244         eee_status = qed_rd(p_hwfn,
1245                             p_ptt,
1246                             p_hwfn->mcp_info->port_addr +
1247                             offsetof(struct public_port, eee_status));
1248         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1249         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1250         if (val & EEE_1G_ADV)
1251                 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1252         if (val & EEE_10G_ADV)
1253                 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1254         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1255         if (val & EEE_1G_ADV)
1256                 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1257         if (val & EEE_10G_ADV)
1258                 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1259 }
1260
1261 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1262                                        struct qed_ptt *p_ptt, bool b_reset)
1263 {
1264         struct qed_mcp_link_state *p_link;
1265         u8 max_bw, min_bw;
1266         u32 status = 0;
1267
1268         /* Prevent SW/attentions from doing this at the same time */
1269         spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1270
1271         p_link = &p_hwfn->mcp_info->link_output;
1272         memset(p_link, 0, sizeof(*p_link));
1273         if (!b_reset) {
1274                 status = qed_rd(p_hwfn, p_ptt,
1275                                 p_hwfn->mcp_info->port_addr +
1276                                 offsetof(struct public_port, link_status));
1277                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1278                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1279                            status,
1280                            (u32)(p_hwfn->mcp_info->port_addr +
1281                                  offsetof(struct public_port, link_status)));
1282         } else {
1283                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1284                            "Resetting link indications\n");
1285                 goto out;
1286         }
1287
1288         if (p_hwfn->b_drv_link_init)
1289                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1290         else
1291                 p_link->link_up = false;
1292
1293         p_link->full_duplex = true;
1294         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1295         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1296                 p_link->speed = 100000;
1297                 break;
1298         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1299                 p_link->speed = 50000;
1300                 break;
1301         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1302                 p_link->speed = 40000;
1303                 break;
1304         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1305                 p_link->speed = 25000;
1306                 break;
1307         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1308                 p_link->speed = 20000;
1309                 break;
1310         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1311                 p_link->speed = 10000;
1312                 break;
1313         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1314                 p_link->full_duplex = false;
1315         /* Fall-through */
1316         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1317                 p_link->speed = 1000;
1318                 break;
1319         default:
1320                 p_link->speed = 0;
1321                 p_link->link_up = 0;
1322         }
1323
1324         if (p_link->link_up && p_link->speed)
1325                 p_link->line_speed = p_link->speed;
1326         else
1327                 p_link->line_speed = 0;
1328
1329         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1330         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1331
1332         /* Max bandwidth configuration */
1333         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1334
1335         /* Min bandwidth configuration */
1336         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1337         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1338                                             p_link->min_pf_rate);
1339
1340         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1341         p_link->an_complete = !!(status &
1342                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1343         p_link->parallel_detection = !!(status &
1344                                         LINK_STATUS_PARALLEL_DETECTION_USED);
1345         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1346
1347         p_link->partner_adv_speed |=
1348                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1349                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1350         p_link->partner_adv_speed |=
1351                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1352                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1353         p_link->partner_adv_speed |=
1354                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1355                 QED_LINK_PARTNER_SPEED_10G : 0;
1356         p_link->partner_adv_speed |=
1357                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1358                 QED_LINK_PARTNER_SPEED_20G : 0;
1359         p_link->partner_adv_speed |=
1360                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1361                 QED_LINK_PARTNER_SPEED_25G : 0;
1362         p_link->partner_adv_speed |=
1363                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1364                 QED_LINK_PARTNER_SPEED_40G : 0;
1365         p_link->partner_adv_speed |=
1366                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1367                 QED_LINK_PARTNER_SPEED_50G : 0;
1368         p_link->partner_adv_speed |=
1369                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1370                 QED_LINK_PARTNER_SPEED_100G : 0;
1371
1372         p_link->partner_tx_flow_ctrl_en =
1373                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1374         p_link->partner_rx_flow_ctrl_en =
1375                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1376
1377         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1378         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1379                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1380                 break;
1381         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1382                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1383                 break;
1384         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1385                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1386                 break;
1387         default:
1388                 p_link->partner_adv_pause = 0;
1389         }
1390
1391         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1392
1393         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1394                 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1395
1396         qed_link_update(p_hwfn, p_ptt);
1397 out:
1398         spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1399 }
1400
1401 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1402 {
1403         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1404         struct qed_mcp_mb_params mb_params;
1405         struct eth_phy_cfg phy_cfg;
1406         int rc = 0;
1407         u32 cmd;
1408
1409         /* Set the shmem configuration according to params */
1410         memset(&phy_cfg, 0, sizeof(phy_cfg));
1411         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1412         if (!params->speed.autoneg)
1413                 phy_cfg.speed = params->speed.forced_speed;
1414         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1415         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1416         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1417         phy_cfg.adv_speed = params->speed.advertised_speeds;
1418         phy_cfg.loopback_mode = params->loopback_mode;
1419
1420         /* There are MFWs that share this capability regardless of whether
1421          * this is feasible or not. And given that at the very least adv_caps
1422          * would be set internally by qed, we want to make sure LFA would
1423          * still work.
1424          */
1425         if ((p_hwfn->mcp_info->capabilities &
1426              FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) {
1427                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1428                 if (params->eee.tx_lpi_enable)
1429                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1430                 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1431                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1432                 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1433                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1434                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1435                                     EEE_TX_TIMER_USEC_OFFSET) &
1436                                    EEE_TX_TIMER_USEC_MASK;
1437         }
1438
1439         p_hwfn->b_drv_link_init = b_up;
1440
1441         if (b_up) {
1442                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1443                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1444                            phy_cfg.speed,
1445                            phy_cfg.pause,
1446                            phy_cfg.adv_speed,
1447                            phy_cfg.loopback_mode,
1448                            phy_cfg.feature_config_flags);
1449         } else {
1450                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1451                            "Resetting link\n");
1452         }
1453
1454         memset(&mb_params, 0, sizeof(mb_params));
1455         mb_params.cmd = cmd;
1456         mb_params.p_data_src = &phy_cfg;
1457         mb_params.data_src_size = sizeof(phy_cfg);
1458         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1459
1460         /* if mcp fails to respond we must abort */
1461         if (rc) {
1462                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1463                 return rc;
1464         }
1465
1466         /* Mimic link-change attention, done for several reasons:
1467          *  - On reset, there's no guarantee MFW would trigger
1468          *    an attention.
1469          *  - On initialization, older MFWs might not indicate link change
1470          *    during LFA, so we'll never get an UP indication.
1471          */
1472         qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1473
1474         return 0;
1475 }
1476
1477 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1478                                         struct qed_ptt *p_ptt,
1479                                         enum MFW_DRV_MSG_TYPE type)
1480 {
1481         enum qed_mcp_protocol_type stats_type;
1482         union qed_mcp_protocol_stats stats;
1483         struct qed_mcp_mb_params mb_params;
1484         u32 hsi_param;
1485
1486         switch (type) {
1487         case MFW_DRV_MSG_GET_LAN_STATS:
1488                 stats_type = QED_MCP_LAN_STATS;
1489                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1490                 break;
1491         case MFW_DRV_MSG_GET_FCOE_STATS:
1492                 stats_type = QED_MCP_FCOE_STATS;
1493                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1494                 break;
1495         case MFW_DRV_MSG_GET_ISCSI_STATS:
1496                 stats_type = QED_MCP_ISCSI_STATS;
1497                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1498                 break;
1499         case MFW_DRV_MSG_GET_RDMA_STATS:
1500                 stats_type = QED_MCP_RDMA_STATS;
1501                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1502                 break;
1503         default:
1504                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1505                 return;
1506         }
1507
1508         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1509
1510         memset(&mb_params, 0, sizeof(mb_params));
1511         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1512         mb_params.param = hsi_param;
1513         mb_params.p_data_src = &stats;
1514         mb_params.data_src_size = sizeof(stats);
1515         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1516 }
1517
1518 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1519                                   struct public_func *p_shmem_info)
1520 {
1521         struct qed_mcp_function_info *p_info;
1522
1523         p_info = &p_hwfn->mcp_info->func_info;
1524
1525         p_info->bandwidth_min = (p_shmem_info->config &
1526                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1527                                         FUNC_MF_CFG_MIN_BW_SHIFT;
1528         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1529                 DP_INFO(p_hwfn,
1530                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1531                         p_info->bandwidth_min);
1532                 p_info->bandwidth_min = 1;
1533         }
1534
1535         p_info->bandwidth_max = (p_shmem_info->config &
1536                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1537                                         FUNC_MF_CFG_MAX_BW_SHIFT;
1538         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1539                 DP_INFO(p_hwfn,
1540                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1541                         p_info->bandwidth_max);
1542                 p_info->bandwidth_max = 100;
1543         }
1544 }
1545
1546 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1547                                   struct qed_ptt *p_ptt,
1548                                   struct public_func *p_data, int pfid)
1549 {
1550         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1551                                         PUBLIC_FUNC);
1552         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1553         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1554         u32 i, size;
1555
1556         memset(p_data, 0, sizeof(*p_data));
1557
1558         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1559         for (i = 0; i < size / sizeof(u32); i++)
1560                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1561                                             func_addr + (i << 2));
1562         return size;
1563 }
1564
1565 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1566 {
1567         struct qed_mcp_function_info *p_info;
1568         struct public_func shmem_info;
1569         u32 resp = 0, param = 0;
1570
1571         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1572
1573         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1574
1575         p_info = &p_hwfn->mcp_info->func_info;
1576
1577         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1578         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1579
1580         /* Acknowledge the MFW */
1581         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1582                     &param);
1583 }
1584
1585 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1586 {
1587         struct public_func shmem_info;
1588         u32 resp = 0, param = 0;
1589
1590         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1591
1592         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1593                                                  FUNC_MF_CFG_OV_STAG_MASK;
1594         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1595         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) {
1596                 if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) {
1597                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
1598                                p_hwfn->hw_info.ovlan);
1599                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1);
1600
1601                         /* Configure DB to add external vlan to EDPM packets */
1602                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
1603                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,
1604                                p_hwfn->hw_info.ovlan);
1605                 } else {
1606                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);
1607                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0);
1608                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);
1609                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);
1610                 }
1611
1612                 qed_sp_pf_update_stag(p_hwfn);
1613         }
1614
1615         DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan  = %d hw_mode = 0x%x\n",
1616                    p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode);
1617
1618         /* Acknowledge the MFW */
1619         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1620                     &resp, &param);
1621 }
1622
1623 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1624 {
1625         struct public_func shmem_info;
1626         u32 port_cfg, val;
1627
1628         if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
1629                 return;
1630
1631         memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1632         port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1633                           offsetof(struct public_port, oem_cfg_port));
1634         val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >>
1635                 OEM_CFG_CHANNEL_TYPE_OFFSET;
1636         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1637                 DP_NOTICE(p_hwfn, "Incorrect UFP Channel type  %d\n", val);
1638
1639         val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET;
1640         if (val == OEM_CFG_SCHED_TYPE_ETS) {
1641                 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS;
1642         } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) {
1643                 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW;
1644         } else {
1645                 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN;
1646                 DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val);
1647         }
1648
1649         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1650         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >>
1651                 OEM_CFG_FUNC_TC_OFFSET;
1652         p_hwfn->ufp_info.tc = (u8)val;
1653         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >>
1654                 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET;
1655         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) {
1656                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC;
1657         } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) {
1658                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS;
1659         } else {
1660                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN;
1661                 DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val);
1662         }
1663
1664         DP_NOTICE(p_hwfn,
1665                   "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1666                   p_hwfn->ufp_info.mode,
1667                   p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type);
1668 }
1669
1670 static int
1671 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1672 {
1673         qed_mcp_read_ufp_config(p_hwfn, p_ptt);
1674
1675         if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) {
1676                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1677                 qed_hw_info_set_offload_tc(&p_hwfn->hw_info,
1678                                            p_hwfn->ufp_info.tc);
1679
1680                 qed_qm_reconf(p_hwfn, p_ptt);
1681         } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) {
1682                 /* Merge UFP TC with the dcbx TC data */
1683                 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1684                                           QED_DCBX_OPERATIONAL_MIB);
1685         } else {
1686                 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n");
1687                 return -EINVAL;
1688         }
1689
1690         /* update storm FW with negotiation results */
1691         qed_sp_pf_update_ufp(p_hwfn);
1692
1693         /* update stag pcp value */
1694         qed_sp_pf_update_stag(p_hwfn);
1695
1696         return 0;
1697 }
1698
1699 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1700                           struct qed_ptt *p_ptt)
1701 {
1702         struct qed_mcp_info *info = p_hwfn->mcp_info;
1703         int rc = 0;
1704         bool found = false;
1705         u16 i;
1706
1707         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1708
1709         /* Read Messages from MFW */
1710         qed_mcp_read_mb(p_hwfn, p_ptt);
1711
1712         /* Compare current messages to old ones */
1713         for (i = 0; i < info->mfw_mb_length; i++) {
1714                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1715                         continue;
1716
1717                 found = true;
1718
1719                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1720                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1721                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1722
1723                 switch (i) {
1724                 case MFW_DRV_MSG_LINK_CHANGE:
1725                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1726                         break;
1727                 case MFW_DRV_MSG_VF_DISABLED:
1728                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1729                         break;
1730                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1731                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1732                                                   QED_DCBX_REMOTE_LLDP_MIB);
1733                         break;
1734                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1735                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1736                                                   QED_DCBX_REMOTE_MIB);
1737                         break;
1738                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1739                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1740                                                   QED_DCBX_OPERATIONAL_MIB);
1741                         break;
1742                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1743                         qed_mcp_handle_ufp_event(p_hwfn, p_ptt);
1744                         break;
1745                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1746                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1747                         break;
1748                 case MFW_DRV_MSG_GET_LAN_STATS:
1749                 case MFW_DRV_MSG_GET_FCOE_STATS:
1750                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1751                 case MFW_DRV_MSG_GET_RDMA_STATS:
1752                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1753                         break;
1754                 case MFW_DRV_MSG_BW_UPDATE:
1755                         qed_mcp_update_bw(p_hwfn, p_ptt);
1756                         break;
1757                 case MFW_DRV_MSG_S_TAG_UPDATE:
1758                         qed_mcp_update_stag(p_hwfn, p_ptt);
1759                         break;
1760                 case MFW_DRV_MSG_GET_TLV_REQ:
1761                         qed_mfw_tlv_req(p_hwfn);
1762                         break;
1763                 default:
1764                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1765                         rc = -EINVAL;
1766                 }
1767         }
1768
1769         /* ACK everything */
1770         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1771                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1772
1773                 /* MFW expect answer in BE, so we force write in that format */
1774                 qed_wr(p_hwfn, p_ptt,
1775                        info->mfw_mb_addr + sizeof(u32) +
1776                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1777                        sizeof(u32) + i * sizeof(u32),
1778                        (__force u32)val);
1779         }
1780
1781         if (!found) {
1782                 DP_NOTICE(p_hwfn,
1783                           "Received an MFW message indication but no new message!\n");
1784                 rc = -EINVAL;
1785         }
1786
1787         /* Copy the new mfw messages into the shadow */
1788         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1789
1790         return rc;
1791 }
1792
1793 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
1794                         struct qed_ptt *p_ptt,
1795                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
1796 {
1797         u32 global_offsize;
1798
1799         if (IS_VF(p_hwfn->cdev)) {
1800                 if (p_hwfn->vf_iov_info) {
1801                         struct pfvf_acquire_resp_tlv *p_resp;
1802
1803                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1804                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1805                         return 0;
1806                 } else {
1807                         DP_VERBOSE(p_hwfn,
1808                                    QED_MSG_IOV,
1809                                    "VF requested MFW version prior to ACQUIRE\n");
1810                         return -EINVAL;
1811                 }
1812         }
1813
1814         global_offsize = qed_rd(p_hwfn, p_ptt,
1815                                 SECTION_OFFSIZE_ADDR(p_hwfn->
1816                                                      mcp_info->public_base,
1817                                                      PUBLIC_GLOBAL));
1818         *p_mfw_ver =
1819             qed_rd(p_hwfn, p_ptt,
1820                    SECTION_ADDR(global_offsize,
1821                                 0) + offsetof(struct public_global, mfw_ver));
1822
1823         if (p_running_bundle_id != NULL) {
1824                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1825                                               SECTION_ADDR(global_offsize, 0) +
1826                                               offsetof(struct public_global,
1827                                                        running_bundle_id));
1828         }
1829
1830         return 0;
1831 }
1832
1833 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
1834                         struct qed_ptt *p_ptt, u32 *p_mbi_ver)
1835 {
1836         u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
1837
1838         if (IS_VF(p_hwfn->cdev))
1839                 return -EINVAL;
1840
1841         /* Read the address of the nvm_cfg */
1842         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1843         if (!nvm_cfg_addr) {
1844                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1845                 return -EINVAL;
1846         }
1847
1848         /* Read the offset of nvm_cfg1 */
1849         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1850
1851         mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1852                        offsetof(struct nvm_cfg1, glob) +
1853                        offsetof(struct nvm_cfg1_glob, mbi_version);
1854         *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
1855                             mbi_ver_addr) &
1856                      (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
1857                       NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
1858                       NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
1859
1860         return 0;
1861 }
1862
1863 int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn,
1864                            struct qed_ptt *p_ptt, u32 *p_media_type)
1865 {
1866         if (IS_VF(p_hwfn->cdev))
1867                 return -EINVAL;
1868
1869         if (!qed_mcp_is_init(p_hwfn)) {
1870                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1871                 return -EBUSY;
1872         }
1873
1874         if (!p_ptt) {
1875                 *p_media_type = MEDIA_UNSPECIFIED;
1876                 return -EINVAL;
1877         }
1878
1879         *p_media_type = qed_rd(p_hwfn, p_ptt,
1880                                p_hwfn->mcp_info->port_addr +
1881                                offsetof(struct public_port,
1882                                         media_type));
1883
1884         return 0;
1885 }
1886
1887 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1888 static void
1889 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1890                                enum qed_pci_personality *p_proto)
1891 {
1892         /* There wasn't ever a legacy MFW that published iwarp.
1893          * So at this point, this is either plain l2 or RoCE.
1894          */
1895         if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1896                 *p_proto = QED_PCI_ETH_ROCE;
1897         else
1898                 *p_proto = QED_PCI_ETH;
1899
1900         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1901                    "According to Legacy capabilities, L2 personality is %08x\n",
1902                    (u32) *p_proto);
1903 }
1904
1905 static int
1906 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1907                             struct qed_ptt *p_ptt,
1908                             enum qed_pci_personality *p_proto)
1909 {
1910         u32 resp = 0, param = 0;
1911         int rc;
1912
1913         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1914                          DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
1915         if (rc)
1916                 return rc;
1917         if (resp != FW_MSG_CODE_OK) {
1918                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1919                            "MFW lacks support for command; Returns %08x\n",
1920                            resp);
1921                 return -EINVAL;
1922         }
1923
1924         switch (param) {
1925         case FW_MB_PARAM_GET_PF_RDMA_NONE:
1926                 *p_proto = QED_PCI_ETH;
1927                 break;
1928         case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1929                 *p_proto = QED_PCI_ETH_ROCE;
1930                 break;
1931         case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1932                 *p_proto = QED_PCI_ETH_IWARP;
1933                 break;
1934         case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1935                 *p_proto = QED_PCI_ETH_RDMA;
1936                 break;
1937         default:
1938                 DP_NOTICE(p_hwfn,
1939                           "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1940                           param);
1941                 return -EINVAL;
1942         }
1943
1944         DP_VERBOSE(p_hwfn,
1945                    NETIF_MSG_IFUP,
1946                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1947                    (u32) *p_proto, resp, param);
1948         return 0;
1949 }
1950
1951 static int
1952 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1953                         struct public_func *p_info,
1954                         struct qed_ptt *p_ptt,
1955                         enum qed_pci_personality *p_proto)
1956 {
1957         int rc = 0;
1958
1959         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1960         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1961                 if (!IS_ENABLED(CONFIG_QED_RDMA))
1962                         *p_proto = QED_PCI_ETH;
1963                 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1964                         qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1965                 break;
1966         case FUNC_MF_CFG_PROTOCOL_ISCSI:
1967                 *p_proto = QED_PCI_ISCSI;
1968                 break;
1969         case FUNC_MF_CFG_PROTOCOL_FCOE:
1970                 *p_proto = QED_PCI_FCOE;
1971                 break;
1972         case FUNC_MF_CFG_PROTOCOL_ROCE:
1973                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1974         /* Fallthrough */
1975         default:
1976                 rc = -EINVAL;
1977         }
1978
1979         return rc;
1980 }
1981
1982 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1983                                  struct qed_ptt *p_ptt)
1984 {
1985         struct qed_mcp_function_info *info;
1986         struct public_func shmem_info;
1987
1988         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1989         info = &p_hwfn->mcp_info->func_info;
1990
1991         info->pause_on_host = (shmem_info.config &
1992                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1993
1994         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1995                                     &info->protocol)) {
1996                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1997                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1998                 return -EINVAL;
1999         }
2000
2001         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
2002
2003         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2004                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2005                 info->mac[1] = (u8)(shmem_info.mac_upper);
2006                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2007                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2008                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2009                 info->mac[5] = (u8)(shmem_info.mac_lower);
2010
2011                 /* Store primary MAC for later possible WoL */
2012                 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
2013         } else {
2014                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
2015         }
2016
2017         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
2018                          (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
2019         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
2020                          (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
2021
2022         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2023
2024         info->mtu = (u16)shmem_info.mtu_size;
2025
2026         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
2027         p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
2028         if (qed_mcp_is_init(p_hwfn)) {
2029                 u32 resp = 0, param = 0;
2030                 int rc;
2031
2032                 rc = qed_mcp_cmd(p_hwfn, p_ptt,
2033                                  DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
2034                 if (rc)
2035                         return rc;
2036                 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
2037                         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
2038         }
2039
2040         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
2041                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
2042                 info->pause_on_host, info->protocol,
2043                 info->bandwidth_min, info->bandwidth_max,
2044                 info->mac[0], info->mac[1], info->mac[2],
2045                 info->mac[3], info->mac[4], info->mac[5],
2046                 info->wwn_port, info->wwn_node,
2047                 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
2048
2049         return 0;
2050 }
2051
2052 struct qed_mcp_link_params
2053 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
2054 {
2055         if (!p_hwfn || !p_hwfn->mcp_info)
2056                 return NULL;
2057         return &p_hwfn->mcp_info->link_input;
2058 }
2059
2060 struct qed_mcp_link_state
2061 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
2062 {
2063         if (!p_hwfn || !p_hwfn->mcp_info)
2064                 return NULL;
2065         return &p_hwfn->mcp_info->link_output;
2066 }
2067
2068 struct qed_mcp_link_capabilities
2069 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
2070 {
2071         if (!p_hwfn || !p_hwfn->mcp_info)
2072                 return NULL;
2073         return &p_hwfn->mcp_info->link_capabilities;
2074 }
2075
2076 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2077 {
2078         u32 resp = 0, param = 0;
2079         int rc;
2080
2081         rc = qed_mcp_cmd(p_hwfn, p_ptt,
2082                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2083
2084         /* Wait for the drain to complete before returning */
2085         msleep(1020);
2086
2087         return rc;
2088 }
2089
2090 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
2091                            struct qed_ptt *p_ptt, u32 *p_flash_size)
2092 {
2093         u32 flash_size;
2094
2095         if (IS_VF(p_hwfn->cdev))
2096                 return -EINVAL;
2097
2098         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2099         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2100                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2101         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2102
2103         *p_flash_size = flash_size;
2104
2105         return 0;
2106 }
2107
2108 static int
2109 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
2110                           struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2111 {
2112         u32 resp = 0, param = 0, rc_param = 0;
2113         int rc;
2114
2115         /* Only Leader can configure MSIX, and need to take CMT into account */
2116         if (!IS_LEAD_HWFN(p_hwfn))
2117                 return 0;
2118         num *= p_hwfn->cdev->num_hwfns;
2119
2120         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2121                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2122         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2123                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2124
2125         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2126                          &resp, &rc_param);
2127
2128         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2129                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
2130                 rc = -EINVAL;
2131         } else {
2132                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2133                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2134                            num, vf_id);
2135         }
2136
2137         return rc;
2138 }
2139
2140 static int
2141 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
2142                           struct qed_ptt *p_ptt, u8 num)
2143 {
2144         u32 resp = 0, param = num, rc_param = 0;
2145         int rc;
2146
2147         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2148                          param, &resp, &rc_param);
2149
2150         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2151                 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
2152                 rc = -EINVAL;
2153         } else {
2154                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2155                            "Requested 0x%02x MSI-x interrupts for VFs\n", num);
2156         }
2157
2158         return rc;
2159 }
2160
2161 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
2162                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2163 {
2164         if (QED_IS_BB(p_hwfn->cdev))
2165                 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2166         else
2167                 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2168 }
2169
2170 int
2171 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
2172                          struct qed_ptt *p_ptt,
2173                          struct qed_mcp_drv_version *p_ver)
2174 {
2175         struct qed_mcp_mb_params mb_params;
2176         struct drv_version_stc drv_version;
2177         __be32 val;
2178         u32 i;
2179         int rc;
2180
2181         memset(&drv_version, 0, sizeof(drv_version));
2182         drv_version.version = p_ver->version;
2183         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
2184                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
2185                 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
2186         }
2187
2188         memset(&mb_params, 0, sizeof(mb_params));
2189         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2190         mb_params.p_data_src = &drv_version;
2191         mb_params.data_src_size = sizeof(drv_version);
2192         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2193         if (rc)
2194                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2195
2196         return rc;
2197 }
2198
2199 /* A maximal 100 msec waiting time for the MCP to halt */
2200 #define QED_MCP_HALT_SLEEP_MS           10
2201 #define QED_MCP_HALT_MAX_RETRIES        10
2202
2203 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2204 {
2205         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2206         int rc;
2207
2208         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2209                          &param);
2210         if (rc) {
2211                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2212                 return rc;
2213         }
2214
2215         do {
2216                 msleep(QED_MCP_HALT_SLEEP_MS);
2217                 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2218                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2219                         break;
2220         } while (++cnt < QED_MCP_HALT_MAX_RETRIES);
2221
2222         if (cnt == QED_MCP_HALT_MAX_RETRIES) {
2223                 DP_NOTICE(p_hwfn,
2224                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2225                           qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2226                 return -EBUSY;
2227         }
2228
2229         qed_mcp_cmd_set_blocking(p_hwfn, true);
2230
2231         return 0;
2232 }
2233
2234 #define QED_MCP_RESUME_SLEEP_MS 10
2235
2236 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2237 {
2238         u32 cpu_mode, cpu_state;
2239
2240         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2241
2242         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2243         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2244         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2245         msleep(QED_MCP_RESUME_SLEEP_MS);
2246         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2247
2248         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2249                 DP_NOTICE(p_hwfn,
2250                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2251                           cpu_mode, cpu_state);
2252                 return -EBUSY;
2253         }
2254
2255         qed_mcp_cmd_set_blocking(p_hwfn, false);
2256
2257         return 0;
2258 }
2259
2260 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
2261                                      struct qed_ptt *p_ptt,
2262                                      enum qed_ov_client client)
2263 {
2264         u32 resp = 0, param = 0;
2265         u32 drv_mb_param;
2266         int rc;
2267
2268         switch (client) {
2269         case QED_OV_CLIENT_DRV:
2270                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2271                 break;
2272         case QED_OV_CLIENT_USER:
2273                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2274                 break;
2275         case QED_OV_CLIENT_VENDOR_SPEC:
2276                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2277                 break;
2278         default:
2279                 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2280                 return -EINVAL;
2281         }
2282
2283         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2284                          drv_mb_param, &resp, &param);
2285         if (rc)
2286                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2287
2288         return rc;
2289 }
2290
2291 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2292                                    struct qed_ptt *p_ptt,
2293                                    enum qed_ov_driver_state drv_state)
2294 {
2295         u32 resp = 0, param = 0;
2296         u32 drv_mb_param;
2297         int rc;
2298
2299         switch (drv_state) {
2300         case QED_OV_DRIVER_STATE_NOT_LOADED:
2301                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2302                 break;
2303         case QED_OV_DRIVER_STATE_DISABLED:
2304                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2305                 break;
2306         case QED_OV_DRIVER_STATE_ACTIVE:
2307                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2308                 break;
2309         default:
2310                 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2311                 return -EINVAL;
2312         }
2313
2314         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2315                          drv_mb_param, &resp, &param);
2316         if (rc)
2317                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2318
2319         return rc;
2320 }
2321
2322 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2323                           struct qed_ptt *p_ptt, u16 mtu)
2324 {
2325         u32 resp = 0, param = 0;
2326         u32 drv_mb_param;
2327         int rc;
2328
2329         drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2330         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2331                          drv_mb_param, &resp, &param);
2332         if (rc)
2333                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2334
2335         return rc;
2336 }
2337
2338 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2339                           struct qed_ptt *p_ptt, u8 *mac)
2340 {
2341         struct qed_mcp_mb_params mb_params;
2342         u32 mfw_mac[2];
2343         int rc;
2344
2345         memset(&mb_params, 0, sizeof(mb_params));
2346         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2347         mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2348                           DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2349         mb_params.param |= MCP_PF_ID(p_hwfn);
2350
2351         /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
2352          * in 32-bit granularity.
2353          * So the MAC has to be set in native order [and not byte order],
2354          * otherwise it would be read incorrectly by MFW after swap.
2355          */
2356         mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2357         mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2358
2359         mb_params.p_data_src = (u8 *)mfw_mac;
2360         mb_params.data_src_size = 8;
2361         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2362         if (rc)
2363                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2364
2365         /* Store primary MAC for later possible WoL */
2366         memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2367
2368         return rc;
2369 }
2370
2371 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2372                           struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2373 {
2374         u32 resp = 0, param = 0;
2375         u32 drv_mb_param;
2376         int rc;
2377
2378         if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2379                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2380                            "Can't change WoL configuration when WoL isn't supported\n");
2381                 return -EINVAL;
2382         }
2383
2384         switch (wol) {
2385         case QED_OV_WOL_DEFAULT:
2386                 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2387                 break;
2388         case QED_OV_WOL_DISABLED:
2389                 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2390                 break;
2391         case QED_OV_WOL_ENABLED:
2392                 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2393                 break;
2394         default:
2395                 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2396                 return -EINVAL;
2397         }
2398
2399         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2400                          drv_mb_param, &resp, &param);
2401         if (rc)
2402                 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2403
2404         /* Store the WoL update for a future unload */
2405         p_hwfn->cdev->wol_config = (u8)wol;
2406
2407         return rc;
2408 }
2409
2410 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2411                               struct qed_ptt *p_ptt,
2412                               enum qed_ov_eswitch eswitch)
2413 {
2414         u32 resp = 0, param = 0;
2415         u32 drv_mb_param;
2416         int rc;
2417
2418         switch (eswitch) {
2419         case QED_OV_ESWITCH_NONE:
2420                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2421                 break;
2422         case QED_OV_ESWITCH_VEB:
2423                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2424                 break;
2425         case QED_OV_ESWITCH_VEPA:
2426                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2427                 break;
2428         default:
2429                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2430                 return -EINVAL;
2431         }
2432
2433         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2434                          drv_mb_param, &resp, &param);
2435         if (rc)
2436                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2437
2438         return rc;
2439 }
2440
2441 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2442                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
2443 {
2444         u32 resp = 0, param = 0, drv_mb_param;
2445         int rc;
2446
2447         switch (mode) {
2448         case QED_LED_MODE_ON:
2449                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2450                 break;
2451         case QED_LED_MODE_OFF:
2452                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2453                 break;
2454         case QED_LED_MODE_RESTORE:
2455                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2456                 break;
2457         default:
2458                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2459                 return -EINVAL;
2460         }
2461
2462         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2463                          drv_mb_param, &resp, &param);
2464
2465         return rc;
2466 }
2467
2468 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2469                           struct qed_ptt *p_ptt, u32 mask_parities)
2470 {
2471         u32 resp = 0, param = 0;
2472         int rc;
2473
2474         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2475                          mask_parities, &resp, &param);
2476
2477         if (rc) {
2478                 DP_ERR(p_hwfn,
2479                        "MCP response failure for mask parities, aborting\n");
2480         } else if (resp != FW_MSG_CODE_OK) {
2481                 DP_ERR(p_hwfn,
2482                        "MCP did not acknowledge mask parity request. Old MFW?\n");
2483                 rc = -EINVAL;
2484         }
2485
2486         return rc;
2487 }
2488
2489 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2490 {
2491         u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2492         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2493         u32 resp = 0, resp_param = 0;
2494         struct qed_ptt *p_ptt;
2495         int rc = 0;
2496
2497         p_ptt = qed_ptt_acquire(p_hwfn);
2498         if (!p_ptt)
2499                 return -EBUSY;
2500
2501         while (bytes_left > 0) {
2502                 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2503
2504                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2505                                         DRV_MSG_CODE_NVM_READ_NVRAM,
2506                                         addr + offset +
2507                                         (bytes_to_copy <<
2508                                          DRV_MB_PARAM_NVM_LEN_OFFSET),
2509                                         &resp, &resp_param,
2510                                         &read_len,
2511                                         (u32 *)(p_buf + offset));
2512
2513                 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2514                         DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2515                         break;
2516                 }
2517
2518                 /* This can be a lengthy process, and it's possible scheduler
2519                  * isn't preemptable. Sleep a bit to prevent CPU hogging.
2520                  */
2521                 if (bytes_left % 0x1000 <
2522                     (bytes_left - read_len) % 0x1000)
2523                         usleep_range(1000, 2000);
2524
2525                 offset += read_len;
2526                 bytes_left -= read_len;
2527         }
2528
2529         cdev->mcp_nvm_resp = resp;
2530         qed_ptt_release(p_hwfn, p_ptt);
2531
2532         return rc;
2533 }
2534
2535 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
2536 {
2537         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2538         struct qed_ptt *p_ptt;
2539
2540         p_ptt = qed_ptt_acquire(p_hwfn);
2541         if (!p_ptt)
2542                 return -EBUSY;
2543
2544         memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
2545         qed_ptt_release(p_hwfn, p_ptt);
2546
2547         return 0;
2548 }
2549
2550 int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr)
2551 {
2552         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2553         struct qed_ptt *p_ptt;
2554         u32 resp, param;
2555         int rc;
2556
2557         p_ptt = qed_ptt_acquire(p_hwfn);
2558         if (!p_ptt)
2559                 return -EBUSY;
2560         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2561                          &resp, &param);
2562         cdev->mcp_nvm_resp = resp;
2563         qed_ptt_release(p_hwfn, p_ptt);
2564
2565         return rc;
2566 }
2567
2568 int qed_mcp_nvm_write(struct qed_dev *cdev,
2569                       u32 cmd, u32 addr, u8 *p_buf, u32 len)
2570 {
2571         u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
2572         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2573         struct qed_ptt *p_ptt;
2574         int rc = -EINVAL;
2575
2576         p_ptt = qed_ptt_acquire(p_hwfn);
2577         if (!p_ptt)
2578                 return -EBUSY;
2579
2580         switch (cmd) {
2581         case QED_PUT_FILE_DATA:
2582                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2583                 break;
2584         case QED_NVM_WRITE_NVRAM:
2585                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2586                 break;
2587         default:
2588                 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
2589                 rc = -EINVAL;
2590                 goto out;
2591         }
2592
2593         while (buf_idx < len) {
2594                 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
2595                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2596                               addr) + buf_idx;
2597                 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2598                                         &resp, &param, buf_size,
2599                                         (u32 *)&p_buf[buf_idx]);
2600                 if (rc) {
2601                         DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
2602                         resp = FW_MSG_CODE_ERROR;
2603                         break;
2604                 }
2605
2606                 if (resp != FW_MSG_CODE_OK &&
2607                     resp != FW_MSG_CODE_NVM_OK &&
2608                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2609                         DP_NOTICE(cdev,
2610                                   "nvm write failed, resp = 0x%08x\n", resp);
2611                         rc = -EINVAL;
2612                         break;
2613                 }
2614
2615                 /* This can be a lengthy process, and it's possible scheduler
2616                  * isn't pre-emptable. Sleep a bit to prevent CPU hogging.
2617                  */
2618                 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
2619                         usleep_range(1000, 2000);
2620
2621                 buf_idx += buf_size;
2622         }
2623
2624         cdev->mcp_nvm_resp = resp;
2625 out:
2626         qed_ptt_release(p_hwfn, p_ptt);
2627
2628         return rc;
2629 }
2630
2631 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2632                          u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf)
2633 {
2634         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0;
2635         u32 resp, param;
2636         int rc;
2637
2638         nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) &
2639                        DRV_MB_PARAM_TRANSCEIVER_PORT_MASK;
2640         nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) &
2641                        DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK;
2642
2643         addr = offset;
2644         offset = 0;
2645         bytes_left = len;
2646         while (bytes_left > 0) {
2647                 bytes_to_copy = min_t(u32, bytes_left,
2648                                       MAX_I2C_TRANSACTION_SIZE);
2649                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2650                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2651                 nvm_offset |= ((addr + offset) <<
2652                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) &
2653                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK;
2654                 nvm_offset |= (bytes_to_copy <<
2655                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) &
2656                                DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK;
2657                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2658                                         DRV_MSG_CODE_TRANSCEIVER_READ,
2659                                         nvm_offset, &resp, &param, &buf_size,
2660                                         (u32 *)(p_buf + offset));
2661                 if (rc) {
2662                         DP_NOTICE(p_hwfn,
2663                                   "Failed to send a transceiver read command to the MFW. rc = %d.\n",
2664                                   rc);
2665                         return rc;
2666                 }
2667
2668                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
2669                         return -ENODEV;
2670                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2671                         return -EINVAL;
2672
2673                 offset += buf_size;
2674                 bytes_left -= buf_size;
2675         }
2676
2677         return 0;
2678 }
2679
2680 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2681 {
2682         u32 drv_mb_param = 0, rsp, param;
2683         int rc = 0;
2684
2685         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2686                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2687
2688         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2689                          drv_mb_param, &rsp, &param);
2690
2691         if (rc)
2692                 return rc;
2693
2694         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2695             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2696                 rc = -EAGAIN;
2697
2698         return rc;
2699 }
2700
2701 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2702 {
2703         u32 drv_mb_param, rsp, param;
2704         int rc = 0;
2705
2706         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2707                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2708
2709         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2710                          drv_mb_param, &rsp, &param);
2711
2712         if (rc)
2713                 return rc;
2714
2715         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2716             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2717                 rc = -EAGAIN;
2718
2719         return rc;
2720 }
2721
2722 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
2723                                     struct qed_ptt *p_ptt,
2724                                     u32 *num_images)
2725 {
2726         u32 drv_mb_param = 0, rsp;
2727         int rc = 0;
2728
2729         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2730                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2731
2732         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2733                          drv_mb_param, &rsp, num_images);
2734         if (rc)
2735                 return rc;
2736
2737         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2738                 rc = -EINVAL;
2739
2740         return rc;
2741 }
2742
2743 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
2744                                    struct qed_ptt *p_ptt,
2745                                    struct bist_nvm_image_att *p_image_att,
2746                                    u32 image_index)
2747 {
2748         u32 buf_size = 0, param, resp = 0, resp_param = 0;
2749         int rc;
2750
2751         param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2752                 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
2753         param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
2754
2755         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2756                                 DRV_MSG_CODE_BIST_TEST, param,
2757                                 &resp, &resp_param,
2758                                 &buf_size,
2759                                 (u32 *)p_image_att);
2760         if (rc)
2761                 return rc;
2762
2763         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2764             (p_image_att->return_code != 1))
2765                 rc = -EINVAL;
2766
2767         return rc;
2768 }
2769
2770 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
2771 {
2772         struct qed_nvm_image_info nvm_info;
2773         struct qed_ptt *p_ptt;
2774         int rc;
2775         u32 i;
2776
2777         if (p_hwfn->nvm_info.valid)
2778                 return 0;
2779
2780         p_ptt = qed_ptt_acquire(p_hwfn);
2781         if (!p_ptt) {
2782                 DP_ERR(p_hwfn, "failed to acquire ptt\n");
2783                 return -EBUSY;
2784         }
2785
2786         /* Acquire from MFW the amount of available images */
2787         nvm_info.num_images = 0;
2788         rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
2789                                              p_ptt, &nvm_info.num_images);
2790         if (rc == -EOPNOTSUPP) {
2791                 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
2792                 goto out;
2793         } else if (rc || !nvm_info.num_images) {
2794                 DP_ERR(p_hwfn, "Failed getting number of images\n");
2795                 goto err0;
2796         }
2797
2798         nvm_info.image_att = kmalloc_array(nvm_info.num_images,
2799                                            sizeof(struct bist_nvm_image_att),
2800                                            GFP_KERNEL);
2801         if (!nvm_info.image_att) {
2802                 rc = -ENOMEM;
2803                 goto err0;
2804         }
2805
2806         /* Iterate over images and get their attributes */
2807         for (i = 0; i < nvm_info.num_images; i++) {
2808                 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
2809                                                     &nvm_info.image_att[i], i);
2810                 if (rc) {
2811                         DP_ERR(p_hwfn,
2812                                "Failed getting image index %d attributes\n", i);
2813                         goto err1;
2814                 }
2815
2816                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
2817                            nvm_info.image_att[i].len);
2818         }
2819 out:
2820         /* Update hwfn's nvm_info */
2821         if (nvm_info.num_images) {
2822                 p_hwfn->nvm_info.num_images = nvm_info.num_images;
2823                 kfree(p_hwfn->nvm_info.image_att);
2824                 p_hwfn->nvm_info.image_att = nvm_info.image_att;
2825                 p_hwfn->nvm_info.valid = true;
2826         }
2827
2828         qed_ptt_release(p_hwfn, p_ptt);
2829         return 0;
2830
2831 err1:
2832         kfree(nvm_info.image_att);
2833 err0:
2834         qed_ptt_release(p_hwfn, p_ptt);
2835         return rc;
2836 }
2837
2838 int
2839 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
2840                           enum qed_nvm_images image_id,
2841                           struct qed_nvm_image_att *p_image_att)
2842 {
2843         enum nvm_image_type type;
2844         int rc;
2845         u32 i;
2846
2847         /* Translate image_id into MFW definitions */
2848         switch (image_id) {
2849         case QED_NVM_IMAGE_ISCSI_CFG:
2850                 type = NVM_TYPE_ISCSI_CFG;
2851                 break;
2852         case QED_NVM_IMAGE_FCOE_CFG:
2853                 type = NVM_TYPE_FCOE_CFG;
2854                 break;
2855         case QED_NVM_IMAGE_NVM_CFG1:
2856                 type = NVM_TYPE_NVM_CFG1;
2857                 break;
2858         case QED_NVM_IMAGE_DEFAULT_CFG:
2859                 type = NVM_TYPE_DEFAULT_CFG;
2860                 break;
2861         case QED_NVM_IMAGE_NVM_META:
2862                 type = NVM_TYPE_META;
2863                 break;
2864         default:
2865                 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
2866                           image_id);
2867                 return -EINVAL;
2868         }
2869
2870         rc = qed_mcp_nvm_info_populate(p_hwfn);
2871         if (rc)
2872                 return rc;
2873
2874         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2875                 if (type == p_hwfn->nvm_info.image_att[i].image_type)
2876                         break;
2877         if (i == p_hwfn->nvm_info.num_images) {
2878                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2879                            "Failed to find nvram image of type %08x\n",
2880                            image_id);
2881                 return -ENOENT;
2882         }
2883
2884         p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2885         p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
2886
2887         return 0;
2888 }
2889
2890 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
2891                           enum qed_nvm_images image_id,
2892                           u8 *p_buffer, u32 buffer_len)
2893 {
2894         struct qed_nvm_image_att image_att;
2895         int rc;
2896
2897         memset(p_buffer, 0, buffer_len);
2898
2899         rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
2900         if (rc)
2901                 return rc;
2902
2903         /* Validate sizes - both the image's and the supplied buffer's */
2904         if (image_att.length <= 4) {
2905                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2906                            "Image [%d] is too small - only %d bytes\n",
2907                            image_id, image_att.length);
2908                 return -EINVAL;
2909         }
2910
2911         if (image_att.length > buffer_len) {
2912                 DP_VERBOSE(p_hwfn,
2913                            QED_MSG_STORAGE,
2914                            "Image [%d] is too big - %08x bytes where only %08x are available\n",
2915                            image_id, image_att.length, buffer_len);
2916                 return -ENOMEM;
2917         }
2918
2919         return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
2920                                 p_buffer, image_att.length);
2921 }
2922
2923 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
2924 {
2925         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2926
2927         switch (res_id) {
2928         case QED_SB:
2929                 mfw_res_id = RESOURCE_NUM_SB_E;
2930                 break;
2931         case QED_L2_QUEUE:
2932                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2933                 break;
2934         case QED_VPORT:
2935                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2936                 break;
2937         case QED_RSS_ENG:
2938                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2939                 break;
2940         case QED_PQ:
2941                 mfw_res_id = RESOURCE_NUM_PQ_E;
2942                 break;
2943         case QED_RL:
2944                 mfw_res_id = RESOURCE_NUM_RL_E;
2945                 break;
2946         case QED_MAC:
2947         case QED_VLAN:
2948                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2949                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2950                 break;
2951         case QED_ILT:
2952                 mfw_res_id = RESOURCE_ILT_E;
2953                 break;
2954         case QED_LL2_QUEUE:
2955                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2956                 break;
2957         case QED_RDMA_CNQ_RAM:
2958         case QED_CMDQS_CQS:
2959                 /* CNQ/CMDQS are the same resource */
2960                 mfw_res_id = RESOURCE_CQS_E;
2961                 break;
2962         case QED_RDMA_STATS_QUEUE:
2963                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2964                 break;
2965         case QED_BDQ:
2966                 mfw_res_id = RESOURCE_BDQ_E;
2967                 break;
2968         default:
2969                 break;
2970         }
2971
2972         return mfw_res_id;
2973 }
2974
2975 #define QED_RESC_ALLOC_VERSION_MAJOR    2
2976 #define QED_RESC_ALLOC_VERSION_MINOR    0
2977 #define QED_RESC_ALLOC_VERSION                               \
2978         ((QED_RESC_ALLOC_VERSION_MAJOR <<                    \
2979           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2980          (QED_RESC_ALLOC_VERSION_MINOR <<                    \
2981           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2982
2983 struct qed_resc_alloc_in_params {
2984         u32 cmd;
2985         enum qed_resources res_id;
2986         u32 resc_max_val;
2987 };
2988
2989 struct qed_resc_alloc_out_params {
2990         u32 mcp_resp;
2991         u32 mcp_param;
2992         u32 resc_num;
2993         u32 resc_start;
2994         u32 vf_resc_num;
2995         u32 vf_resc_start;
2996         u32 flags;
2997 };
2998
2999 static int
3000 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
3001                             struct qed_ptt *p_ptt,
3002                             struct qed_resc_alloc_in_params *p_in_params,
3003                             struct qed_resc_alloc_out_params *p_out_params)
3004 {
3005         struct qed_mcp_mb_params mb_params;
3006         struct resource_info mfw_resc_info;
3007         int rc;
3008
3009         memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
3010
3011         mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
3012         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3013                 DP_ERR(p_hwfn,
3014                        "Failed to match resource %d [%s] with the MFW resources\n",
3015                        p_in_params->res_id,
3016                        qed_hw_get_resc_name(p_in_params->res_id));
3017                 return -EINVAL;
3018         }
3019
3020         switch (p_in_params->cmd) {
3021         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3022                 mfw_resc_info.size = p_in_params->resc_max_val;
3023                 /* Fallthrough */
3024         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3025                 break;
3026         default:
3027                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3028                        p_in_params->cmd);
3029                 return -EINVAL;
3030         }
3031
3032         memset(&mb_params, 0, sizeof(mb_params));
3033         mb_params.cmd = p_in_params->cmd;
3034         mb_params.param = QED_RESC_ALLOC_VERSION;
3035         mb_params.p_data_src = &mfw_resc_info;
3036         mb_params.data_src_size = sizeof(mfw_resc_info);
3037         mb_params.p_data_dst = mb_params.p_data_src;
3038         mb_params.data_dst_size = mb_params.data_src_size;
3039
3040         DP_VERBOSE(p_hwfn,
3041                    QED_MSG_SP,
3042                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3043                    p_in_params->cmd,
3044                    p_in_params->res_id,
3045                    qed_hw_get_resc_name(p_in_params->res_id),
3046                    QED_MFW_GET_FIELD(mb_params.param,
3047                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3048                    QED_MFW_GET_FIELD(mb_params.param,
3049                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3050                    p_in_params->resc_max_val);
3051
3052         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3053         if (rc)
3054                 return rc;
3055
3056         p_out_params->mcp_resp = mb_params.mcp_resp;
3057         p_out_params->mcp_param = mb_params.mcp_param;
3058         p_out_params->resc_num = mfw_resc_info.size;
3059         p_out_params->resc_start = mfw_resc_info.offset;
3060         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3061         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3062         p_out_params->flags = mfw_resc_info.flags;
3063
3064         DP_VERBOSE(p_hwfn,
3065                    QED_MSG_SP,
3066                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3067                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3068                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3069                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3070                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3071                    p_out_params->resc_num,
3072                    p_out_params->resc_start,
3073                    p_out_params->vf_resc_num,
3074                    p_out_params->vf_resc_start, p_out_params->flags);
3075
3076         return 0;
3077 }
3078
3079 int
3080 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
3081                          struct qed_ptt *p_ptt,
3082                          enum qed_resources res_id,
3083                          u32 resc_max_val, u32 *p_mcp_resp)
3084 {
3085         struct qed_resc_alloc_out_params out_params;
3086         struct qed_resc_alloc_in_params in_params;
3087         int rc;
3088
3089         memset(&in_params, 0, sizeof(in_params));
3090         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3091         in_params.res_id = res_id;
3092         in_params.resc_max_val = resc_max_val;
3093         memset(&out_params, 0, sizeof(out_params));
3094         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3095                                          &out_params);
3096         if (rc)
3097                 return rc;
3098
3099         *p_mcp_resp = out_params.mcp_resp;
3100
3101         return 0;
3102 }
3103
3104 int
3105 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
3106                       struct qed_ptt *p_ptt,
3107                       enum qed_resources res_id,
3108                       u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
3109 {
3110         struct qed_resc_alloc_out_params out_params;
3111         struct qed_resc_alloc_in_params in_params;
3112         int rc;
3113
3114         memset(&in_params, 0, sizeof(in_params));
3115         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3116         in_params.res_id = res_id;
3117         memset(&out_params, 0, sizeof(out_params));
3118         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3119                                          &out_params);
3120         if (rc)
3121                 return rc;
3122
3123         *p_mcp_resp = out_params.mcp_resp;
3124
3125         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3126                 *p_resc_num = out_params.resc_num;
3127                 *p_resc_start = out_params.resc_start;
3128         }
3129
3130         return 0;
3131 }
3132
3133 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3134 {
3135         u32 mcp_resp, mcp_param;
3136
3137         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3138                            &mcp_resp, &mcp_param);
3139 }
3140
3141 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
3142                                 struct qed_ptt *p_ptt,
3143                                 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
3144 {
3145         int rc;
3146
3147         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3148                          p_mcp_resp, p_mcp_param);
3149         if (rc)
3150                 return rc;
3151
3152         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3153                 DP_INFO(p_hwfn,
3154                         "The resource command is unsupported by the MFW\n");
3155                 return -EINVAL;
3156         }
3157
3158         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3159                 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3160
3161                 DP_NOTICE(p_hwfn,
3162                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3163                           param, opcode);
3164                 return -EINVAL;
3165         }
3166
3167         return rc;
3168 }
3169
3170 static int
3171 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3172                     struct qed_ptt *p_ptt,
3173                     struct qed_resc_lock_params *p_params)
3174 {
3175         u32 param = 0, mcp_resp, mcp_param;
3176         u8 opcode;
3177         int rc;
3178
3179         switch (p_params->timeout) {
3180         case QED_MCP_RESC_LOCK_TO_DEFAULT:
3181                 opcode = RESOURCE_OPCODE_REQ;
3182                 p_params->timeout = 0;
3183                 break;
3184         case QED_MCP_RESC_LOCK_TO_NONE:
3185                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3186                 p_params->timeout = 0;
3187                 break;
3188         default:
3189                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3190                 break;
3191         }
3192
3193         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3194         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3195         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3196
3197         DP_VERBOSE(p_hwfn,
3198                    QED_MSG_SP,
3199                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3200                    param, p_params->timeout, opcode, p_params->resource);
3201
3202         /* Attempt to acquire the resource */
3203         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3204         if (rc)
3205                 return rc;
3206
3207         /* Analyze the response */
3208         p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3209         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3210
3211         DP_VERBOSE(p_hwfn,
3212                    QED_MSG_SP,
3213                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3214                    mcp_param, opcode, p_params->owner);
3215
3216         switch (opcode) {
3217         case RESOURCE_OPCODE_GNT:
3218                 p_params->b_granted = true;
3219                 break;
3220         case RESOURCE_OPCODE_BUSY:
3221                 p_params->b_granted = false;
3222                 break;
3223         default:
3224                 DP_NOTICE(p_hwfn,
3225                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3226                           mcp_param, opcode);
3227                 return -EINVAL;
3228         }
3229
3230         return 0;
3231 }
3232
3233 int
3234 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3235                   struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
3236 {
3237         u32 retry_cnt = 0;
3238         int rc;
3239
3240         do {
3241                 /* No need for an interval before the first iteration */
3242                 if (retry_cnt) {
3243                         if (p_params->sleep_b4_retry) {
3244                                 u16 retry_interval_in_ms =
3245                                     DIV_ROUND_UP(p_params->retry_interval,
3246                                                  1000);
3247
3248                                 msleep(retry_interval_in_ms);
3249                         } else {
3250                                 udelay(p_params->retry_interval);
3251                         }
3252                 }
3253
3254                 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3255                 if (rc)
3256                         return rc;
3257
3258                 if (p_params->b_granted)
3259                         break;
3260         } while (retry_cnt++ < p_params->retry_num);
3261
3262         return 0;
3263 }
3264
3265 int
3266 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
3267                     struct qed_ptt *p_ptt,
3268                     struct qed_resc_unlock_params *p_params)
3269 {
3270         u32 param = 0, mcp_resp, mcp_param;
3271         u8 opcode;
3272         int rc;
3273
3274         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3275                                    : RESOURCE_OPCODE_RELEASE;
3276         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3277         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3278
3279         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3280                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3281                    param, opcode, p_params->resource);
3282
3283         /* Attempt to release the resource */
3284         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3285         if (rc)
3286                 return rc;
3287
3288         /* Analyze the response */
3289         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3290
3291         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3292                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3293                    mcp_param, opcode);
3294
3295         switch (opcode) {
3296         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3297                 DP_INFO(p_hwfn,
3298                         "Resource unlock request for an already released resource [%d]\n",
3299                         p_params->resource);
3300                 /* Fallthrough */
3301         case RESOURCE_OPCODE_RELEASED:
3302                 p_params->b_released = true;
3303                 break;
3304         case RESOURCE_OPCODE_WRONG_OWNER:
3305                 p_params->b_released = false;
3306                 break;
3307         default:
3308                 DP_NOTICE(p_hwfn,
3309                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3310                           mcp_param, opcode);
3311                 return -EINVAL;
3312         }
3313
3314         return 0;
3315 }
3316
3317 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
3318                                     struct qed_resc_unlock_params *p_unlock,
3319                                     enum qed_resc_lock
3320                                     resource, bool b_is_permanent)
3321 {
3322         if (p_lock) {
3323                 memset(p_lock, 0, sizeof(*p_lock));
3324
3325                 /* Permanent resources don't require aging, and there's no
3326                  * point in trying to acquire them more than once since it's
3327                  * unexpected another entity would release them.
3328                  */
3329                 if (b_is_permanent) {
3330                         p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
3331                 } else {
3332                         p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3333                         p_lock->retry_interval =
3334                             QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3335                         p_lock->sleep_b4_retry = true;
3336                 }
3337
3338                 p_lock->resource = resource;
3339         }
3340
3341         if (p_unlock) {
3342                 memset(p_unlock, 0, sizeof(*p_unlock));
3343                 p_unlock->resource = resource;
3344         }
3345 }
3346
3347 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3348 {
3349         u32 mcp_resp;
3350         int rc;
3351
3352         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3353                          0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3354         if (!rc)
3355                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
3356                            "MFW supported features: %08x\n",
3357                            p_hwfn->mcp_info->capabilities);
3358
3359         return rc;
3360 }
3361
3362 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3363 {
3364         u32 mcp_resp, mcp_param, features;
3365
3366         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3367
3368         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3369                            features, &mcp_resp, &mcp_param);
3370 }