drivers/net/ethernet/qlogic/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/bitops.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/skbuff.h>
  38 #include <linux/delay.h>
  39 #include <linux/mm.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/prefetch.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61 /*  NETIF_MSG_TX_QUEUED | */
  62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = -1;  /* defaults above */
  67 module_param(debug, int, 0664);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int qlge_irq_type = MSIX_IRQ;
  74 module_param(qlge_irq_type, int, 0664);
  75 MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static int qlge_mpi_coredump;
  78 module_param(qlge_mpi_coredump, int, 0);
  79 MODULE_PARM_DESC(qlge_mpi_coredump,
  80                 "Option to enable MPI firmware dump. "
  81                 "Default is OFF - Do Not allocate memory. ");
  82
  83 static int qlge_force_coredump;
  84 module_param(qlge_force_coredump, int, 0);
  85 MODULE_PARM_DESC(qlge_force_coredump,
  86                 "Option to allow force of firmware core dump. "
  87                 "Default is OFF - Do not allow.");
  88
  89 static const struct pci_device_id qlge_pci_tbl[] = {
  90         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
  91         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
  92         /* required last entry */
  93         {0,}
  94 };
  95
  96 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  97
  98 static int ql_wol(struct ql_adapter *);
  99 static void qlge_set_multicast_list(struct net_device *);
 100 static int ql_adapter_down(struct ql_adapter *);
 101 static int ql_adapter_up(struct ql_adapter *);
 102
 103 /* This hardware semaphore causes exclusive access to
 104  * resources shared between the NIC driver, MPI firmware,
 105  * FCOE firmware and the FC driver.
 106  */
 107 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
 108 {
 109         u32 sem_bits = 0;
 110
 111         switch (sem_mask) {
 112         case SEM_XGMAC0_MASK:
 113                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
 114                 break;
 115         case SEM_XGMAC1_MASK:
 116                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 117                 break;
 118         case SEM_ICB_MASK:
 119                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 120                 break;
 121         case SEM_MAC_ADDR_MASK:
 122                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 123                 break;
 124         case SEM_FLASH_MASK:
 125                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 126                 break;
 127         case SEM_PROBE_MASK:
 128                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 129                 break;
 130         case SEM_RT_IDX_MASK:
 131                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 132                 break;
 133         case SEM_PROC_REG_MASK:
 134                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 135                 break;
 136         default:
 137                 netif_alert(qdev, probe, qdev->ndev, "bad Semaphore mask!.\n");
 138                 return -EINVAL;
 139         }
 140
 141         ql_write32(qdev, SEM, sem_bits | sem_mask);
 142         return !(ql_read32(qdev, SEM) & sem_bits);
 143 }
 144
 145 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 146 {
 147         unsigned int wait_count = 30;
 148         do {
 149                 if (!ql_sem_trylock(qdev, sem_mask))
 150                         return 0;
 151                 udelay(100);
 152         } while (--wait_count);
 153         return -ETIMEDOUT;
 154 }
 155
 156 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 157 {
 158         ql_write32(qdev, SEM, sem_mask);
 159         ql_read32(qdev, SEM);   /* flush */
 160 }
 161
 162 /* This function waits for a specific bit to come ready
 163  * in a given register.  It is used mostly by the initialize
 164  * process, but is also used in kernel thread API such as
 165  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 166  */
 167 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 168 {
 169         u32 temp;
 170         int count = UDELAY_COUNT;
 171
 172         while (count) {
 173                 temp = ql_read32(qdev, reg);
 174
 175                 /* check for errors */
 176                 if (temp & err_bit) {
 177                         netif_alert(qdev, probe, qdev->ndev,
 178                                     "register 0x%.08x access error, value = 0x%.08x!.\n",
 179                                     reg, temp);
 180                         return -EIO;
 181                 } else if (temp & bit)
 182                         return 0;
 183                 udelay(UDELAY_DELAY);
 184                 count--;
 185         }
 186         netif_alert(qdev, probe, qdev->ndev,
 187                     "Timed out waiting for reg %x to come ready.\n", reg);
 188         return -ETIMEDOUT;
 189 }
 190
 191 /* The CFG register is used to download TX and RX control blocks
 192  * to the chip. This function waits for an operation to complete.
 193  */
 194 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 195 {
 196         int count = UDELAY_COUNT;
 197         u32 temp;
 198
 199         while (count) {
 200                 temp = ql_read32(qdev, CFG);
 201                 if (temp & CFG_LE)
 202                         return -EIO;
 203                 if (!(temp & bit))
 204                         return 0;
 205                 udelay(UDELAY_DELAY);
 206                 count--;
 207         }
 208         return -ETIMEDOUT;
 209 }
 210
 211
 212 /* Used to issue init control blocks to hw. Maps control block,
 213  * sets address, triggers download, waits for completion.
 214  */
 215 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 216                  u16 q_id)
 217 {
 218         u64 map;
 219         int status = 0;
 220         int direction;
 221         u32 mask;
 222         u32 value;
 223
 224         direction =
 225             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 226             PCI_DMA_FROMDEVICE;
 227
 228         map = pci_map_single(qdev->pdev, ptr, size, direction);
 229         if (pci_dma_mapping_error(qdev->pdev, map)) {
 230                 netif_err(qdev, ifup, qdev->ndev, "Couldn't map DMA area.\n");
 231                 return -ENOMEM;
 232         }
 233
 234         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 235         if (status)
 236                 return status;
 237
 238         status = ql_wait_cfg(qdev, bit);
 239         if (status) {
 240                 netif_err(qdev, ifup, qdev->ndev,
 241                           "Timed out waiting for CFG to come ready.\n");
 242                 goto exit;
 243         }
 244
 245         ql_write32(qdev, ICB_L, (u32) map);
 246         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 247
 248         mask = CFG_Q_MASK | (bit << 16);
 249         value = bit | (q_id << CFG_Q_SHIFT);
 250         ql_write32(qdev, CFG, (mask | value));
 251
 252         /*
 253          * Wait for the bit to clear after signaling hw.
 254          */
 255         status = ql_wait_cfg(qdev, bit);
 256 exit:
 257         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 258         pci_unmap_single(qdev->pdev, map, size, direction);
 259         return status;
 260 }
 261
 262 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 263 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 264                         u32 *value)
 265 {
 266         u32 offset = 0;
 267         int status;
 268
 269         switch (type) {
 270         case MAC_ADDR_TYPE_MULTI_MAC:
 271         case MAC_ADDR_TYPE_CAM_MAC:
 272                 {
 273                         status =
 274                             ql_wait_reg_rdy(qdev,
 275                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 276                         if (status)
 277                                 goto exit;
 278                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 279                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 280                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 281                         status =
 282                             ql_wait_reg_rdy(qdev,
 283                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 284                         if (status)
 285                                 goto exit;
 286                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 287                         status =
 288                             ql_wait_reg_rdy(qdev,
 289                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 290                         if (status)
 291                                 goto exit;
 292                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 293                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 294                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 295                         status =
 296                             ql_wait_reg_rdy(qdev,
 297                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 298                         if (status)
 299                                 goto exit;
 300                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 301                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 302                                 status =
 303                                     ql_wait_reg_rdy(qdev,
 304                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 305                                 if (status)
 306                                         goto exit;
 307                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 308                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 309                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 310                                 status =
 311                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 312                                                     MAC_ADDR_MR, 0);
 313                                 if (status)
 314                                         goto exit;
 315                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 316                         }
 317                         break;
 318                 }
 319         case MAC_ADDR_TYPE_VLAN:
 320         case MAC_ADDR_TYPE_MULTI_FLTR:
 321         default:
 322                 netif_crit(qdev, ifup, qdev->ndev,
 323                            "Address type %d not yet supported.\n", type);
 324                 status = -EPERM;
 325         }
 326 exit:
 327         return status;
 328 }
 329
 330 /* Set up a MAC, multicast or VLAN address for the
 331  * inbound frame matching.
 332  */
 333 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 334                                u16 index)
 335 {
 336         u32 offset = 0;
 337         int status = 0;
 338
 339         switch (type) {
 340         case MAC_ADDR_TYPE_MULTI_MAC:
 341                 {
 342                         u32 upper = (addr[0] << 8) | addr[1];
 343                         u32 lower = (addr[2] << 24) | (addr[3] << 16) |
 344                                         (addr[4] << 8) | (addr[5]);
 345
 346                         status =
 347                                 ql_wait_reg_rdy(qdev,
 348                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 349                         if (status)
 350                                 goto exit;
 351                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
 352                                 (index << MAC_ADDR_IDX_SHIFT) |
 353                                 type | MAC_ADDR_E);
 354                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 355                         status =
 356                                 ql_wait_reg_rdy(qdev,
 357                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 358                         if (status)
 359                                 goto exit;
 360                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
 361                                 (index << MAC_ADDR_IDX_SHIFT) |
 362                                 type | MAC_ADDR_E);
 363
 364                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 365                         status =
 366                                 ql_wait_reg_rdy(qdev,
 367                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 368                         if (status)
 369                                 goto exit;
 370                         break;
 371                 }
 372         case MAC_ADDR_TYPE_CAM_MAC:
 373                 {
 374                         u32 cam_output;
 375                         u32 upper = (addr[0] << 8) | addr[1];
 376                         u32 lower =
 377                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 378                             (addr[5]);
 379                         status =
 380                             ql_wait_reg_rdy(qdev,
 381                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 382                         if (status)
 383                                 goto exit;
 384                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 385                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 386                                    type);       /* type */
 387                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 388                         status =
 389                             ql_wait_reg_rdy(qdev,
 390                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 391                         if (status)
 392                                 goto exit;
 393                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 394                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 395                                    type);       /* type */
 396                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 397                         status =
 398                             ql_wait_reg_rdy(qdev,
 399                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 400                         if (status)
 401                                 goto exit;
 402                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 403                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 404                                    type);       /* type */
 405                         /* This field should also include the queue id
 406                            and possibly the function id.  Right now we hardcode
 407                            the route field to NIC core.
 408                          */
 409                         cam_output = (CAM_OUT_ROUTE_NIC |
 410                                       (qdev->
 411                                        func << CAM_OUT_FUNC_SHIFT) |
 412                                         (0 << CAM_OUT_CQ_ID_SHIFT));
 413                         if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 414                                 cam_output |= CAM_OUT_RV;
 415                         /* route to NIC core */
 416                         ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 417                         break;
 418                 }
 419         case MAC_ADDR_TYPE_VLAN:
 420                 {
 421                         u32 enable_bit = *((u32 *) &addr[0]);
 422                         /* For VLAN, the addr actually holds a bit that
 423                          * either enables or disables the vlan id we are
 424                          * addressing. It's either MAC_ADDR_E on or off.
 425                          * That's bit-27 we're talking about.
 426                          */
 427                         status =
 428                             ql_wait_reg_rdy(qdev,
 429                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 430                         if (status)
 431                                 goto exit;
 432                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 433                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 434                                    type |       /* type */
 435                                    enable_bit); /* enable/disable */
 436                         break;
 437                 }
 438         case MAC_ADDR_TYPE_MULTI_FLTR:
 439         default:
 440                 netif_crit(qdev, ifup, qdev->ndev,
 441                            "Address type %d not yet supported.\n", type);
 442                 status = -EPERM;
 443         }
 444 exit:
 445         return status;
 446 }
 447
 448 /* Set or clear MAC address in hardware. We sometimes
 449  * have to clear it to prevent wrong frame routing
 450  * especially in a bonding environment.
 451  */
 452 static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
 453 {
 454         int status;
 455         char zero_mac_addr[ETH_ALEN];
 456         char *addr;
 457
 458         if (set) {
 459                 addr = &qdev->current_mac_addr[0];
 460                 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
 461                              "Set Mac addr %pM\n", addr);
 462         } else {
 463                 eth_zero_addr(zero_mac_addr);
 464                 addr = &zero_mac_addr[0];
 465                 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
 466                              "Clearing MAC address\n");
 467         }
 468         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 469         if (status)
 470                 return status;
 471         status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
 472                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
 473         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 474         if (status)
 475                 netif_err(qdev, ifup, qdev->ndev,
 476                           "Failed to init mac address.\n");
 477         return status;
 478 }
 479
 480 void ql_link_on(struct ql_adapter *qdev)
 481 {
 482         netif_err(qdev, link, qdev->ndev, "Link is up.\n");
 483         netif_carrier_on(qdev->ndev);
 484         ql_set_mac_addr(qdev, 1);
 485 }
 486
 487 void ql_link_off(struct ql_adapter *qdev)
 488 {
 489         netif_err(qdev, link, qdev->ndev, "Link is down.\n");
 490         netif_carrier_off(qdev->ndev);
 491         ql_set_mac_addr(qdev, 0);
 492 }
 493
 494 /* Get a specific frame routing value from the CAM.
 495  * Used for debug and reg dump.
 496  */
 497 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 498 {
 499         int status = 0;
 500
 501         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 502         if (status)
 503                 goto exit;
 504
 505         ql_write32(qdev, RT_IDX,
 506                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 507         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 508         if (status)
 509                 goto exit;
 510         *value = ql_read32(qdev, RT_DATA);
 511 exit:
 512         return status;
 513 }
 514
 515 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 516  * to route different frame types to various inbound queues.  We send broadcast/
 517  * multicast/error frames to the default queue for slow handling,
 518  * and CAM hit/RSS frames to the fast handling queues.
 519  */
 520 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 521                               int enable)
 522 {
 523         int status = -EINVAL; /* Return error if no mask match. */
 524         u32 value = 0;
 525
 526         switch (mask) {
 527         case RT_IDX_CAM_HIT:
 528                 {
 529                         value = RT_IDX_DST_CAM_Q |      /* dest */
 530                             RT_IDX_TYPE_NICQ |  /* type */
 531                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 532                         break;
 533                 }
 534         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 535                 {
 536                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 537                             RT_IDX_TYPE_NICQ |  /* type */
 538                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 539                         break;
 540                 }
 541         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 542                 {
 543                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 544                             RT_IDX_TYPE_NICQ |  /* type */
 545                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 546                         break;
 547                 }
 548         case RT_IDX_IP_CSUM_ERR: /* Pass up IP CSUM error frames. */
 549                 {
 550                         value = RT_IDX_DST_DFLT_Q | /* dest */
 551                                 RT_IDX_TYPE_NICQ | /* type */
 552                                 (RT_IDX_IP_CSUM_ERR_SLOT <<
 553                                 RT_IDX_IDX_SHIFT); /* index */
 554                         break;
 555                 }
 556         case RT_IDX_TU_CSUM_ERR: /* Pass up TCP/UDP CSUM error frames. */
 557                 {
 558                         value = RT_IDX_DST_DFLT_Q | /* dest */
 559                                 RT_IDX_TYPE_NICQ | /* type */
 560                                 (RT_IDX_TCP_UDP_CSUM_ERR_SLOT <<
 561                                 RT_IDX_IDX_SHIFT); /* index */
 562                         break;
 563                 }
 564         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 565                 {
 566                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 567                             RT_IDX_TYPE_NICQ |  /* type */
 568                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 569                         break;
 570                 }
 571         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 572                 {
 573                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 574                             RT_IDX_TYPE_NICQ |  /* type */
 575                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 576                         break;
 577                 }
 578         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 579                 {
 580                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 581                             RT_IDX_TYPE_NICQ |  /* type */
 582                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 583                         break;
 584                 }
 585         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 586                 {
 587                         value = RT_IDX_DST_RSS |        /* dest */
 588                             RT_IDX_TYPE_NICQ |  /* type */
 589                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 590                         break;
 591                 }
 592         case 0:         /* Clear the E-bit on an entry. */
 593                 {
 594                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 595                             RT_IDX_TYPE_NICQ |  /* type */
 596                             (index << RT_IDX_IDX_SHIFT);/* index */
 597                         break;
 598                 }
 599         default:
 600                 netif_err(qdev, ifup, qdev->ndev,
 601                           "Mask type %d not yet supported.\n", mask);
 602                 status = -EPERM;
 603                 goto exit;
 604         }
 605
 606         if (value) {
 607                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 608                 if (status)
 609                         goto exit;
 610                 value |= (enable ? RT_IDX_E : 0);
 611                 ql_write32(qdev, RT_IDX, value);
 612                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 613         }
 614 exit:
 615         return status;
 616 }
 617
 618 static void ql_enable_interrupts(struct ql_adapter *qdev)
 619 {
 620         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 621 }
 622
 623 static void ql_disable_interrupts(struct ql_adapter *qdev)
 624 {
 625         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 626 }
 627
 628 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 629  * Otherwise, we may have multiple outstanding workers and don't want to
 630  * enable until the last one finishes. In this case, the irq_cnt gets
 631  * incremented every time we queue a worker and decremented every time
 632  * a worker finishes.  Once it hits zero we enable the interrupt.
 633  */
 634 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 635 {
 636         u32 var = 0;
 637         unsigned long hw_flags = 0;
 638         struct intr_context *ctx = qdev->intr_context + intr;
 639
 640         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 641                 /* Always enable if we're MSIX multi interrupts and
 642                  * it's not the default (zeroeth) interrupt.
 643                  */
 644                 ql_write32(qdev, INTR_EN,
 645                            ctx->intr_en_mask);
 646                 var = ql_read32(qdev, STS);
 647                 return var;
 648         }
 649
 650         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 651         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 652                 ql_write32(qdev, INTR_EN,
 653                            ctx->intr_en_mask);
 654                 var = ql_read32(qdev, STS);
 655         }
 656         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 657         return var;
 658 }
 659
 660 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 661 {
 662         u32 var = 0;
 663         struct intr_context *ctx;
 664
 665         /* HW disables for us if we're MSIX multi interrupts and
 666          * it's not the default (zeroeth) interrupt.
 667          */
 668         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 669                 return 0;
 670
 671         ctx = qdev->intr_context + intr;
 672         spin_lock(&qdev->hw_lock);
 673         if (!atomic_read(&ctx->irq_cnt)) {
 674                 ql_write32(qdev, INTR_EN,
 675                 ctx->intr_dis_mask);
 676                 var = ql_read32(qdev, STS);
 677         }
 678         atomic_inc(&ctx->irq_cnt);
 679         spin_unlock(&qdev->hw_lock);
 680         return var;
 681 }
 682
 683 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 684 {
 685         int i;
 686         for (i = 0; i < qdev->intr_count; i++) {
 687                 /* The enable call does a atomic_dec_and_test
 688                  * and enables only if the result is zero.
 689                  * So we precharge it here.
 690                  */
 691                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 692                         i == 0))
 693                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 694                 ql_enable_completion_interrupt(qdev, i);
 695         }
 696
 697 }
 698
 699 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
 700 {
 701         int status, i;
 702         u16 csum = 0;
 703         __le16 *flash = (__le16 *)&qdev->flash;
 704
 705         status = strncmp((char *)&qdev->flash, str, 4);
 706         if (status) {
 707                 netif_err(qdev, ifup, qdev->ndev, "Invalid flash signature.\n");
 708                 return  status;
 709         }
 710
 711         for (i = 0; i < size; i++)
 712                 csum += le16_to_cpu(*flash++);
 713
 714         if (csum)
 715                 netif_err(qdev, ifup, qdev->ndev,
 716                           "Invalid flash checksum, csum = 0x%.04x.\n", csum);
 717
 718         return csum;
 719 }
 720
 721 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 722 {
 723         int status = 0;
 724         /* wait for reg to come ready */
 725         status = ql_wait_reg_rdy(qdev,
 726                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 727         if (status)
 728                 goto exit;
 729         /* set up for reg read */
 730         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 731         /* wait for reg to come ready */
 732         status = ql_wait_reg_rdy(qdev,
 733                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 734         if (status)
 735                 goto exit;
 736          /* This data is stored on flash as an array of
 737          * __le32.  Since ql_read32() returns cpu endian
 738          * we need to swap it back.
 739          */
 740         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 741 exit:
 742         return status;
 743 }
 744
 745 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
 746 {
 747         u32 i, size;
 748         int status;
 749         __le32 *p = (__le32 *)&qdev->flash;
 750         u32 offset;
 751         u8 mac_addr[6];
 752
 753         /* Get flash offset for function and adjust
 754          * for dword access.
 755          */
 756         if (!qdev->port)
 757                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
 758         else
 759                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
 760
 761         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 762                 return -ETIMEDOUT;
 763
 764         size = sizeof(struct flash_params_8000) / sizeof(u32);
 765         for (i = 0; i < size; i++, p++) {
 766                 status = ql_read_flash_word(qdev, i+offset, p);
 767                 if (status) {
 768                         netif_err(qdev, ifup, qdev->ndev,
 769                                   "Error reading flash.\n");
 770                         goto exit;
 771                 }
 772         }
 773
 774         status = ql_validate_flash(qdev,
 775                         sizeof(struct flash_params_8000) / sizeof(u16),
 776                         "8000");
 777         if (status) {
 778                 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
 779                 status = -EINVAL;
 780                 goto exit;
 781         }
 782
 783         /* Extract either manufacturer or BOFM modified
 784          * MAC address.
 785          */
 786         if (qdev->flash.flash_params_8000.data_type1 == 2)
 787                 memcpy(mac_addr,
 788                         qdev->flash.flash_params_8000.mac_addr1,
 789                         qdev->ndev->addr_len);
 790         else
 791                 memcpy(mac_addr,
 792                         qdev->flash.flash_params_8000.mac_addr,
 793                         qdev->ndev->addr_len);
 794
 795         if (!is_valid_ether_addr(mac_addr)) {
 796                 netif_err(qdev, ifup, qdev->ndev, "Invalid MAC address.\n");
 797                 status = -EINVAL;
 798                 goto exit;
 799         }
 800
 801         memcpy(qdev->ndev->dev_addr,
 802                 mac_addr,
 803                 qdev->ndev->addr_len);
 804
 805 exit:
 806         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 807         return status;
 808 }
 809
 810 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
 811 {
 812         int i;
 813         int status;
 814         __le32 *p = (__le32 *)&qdev->flash;
 815         u32 offset = 0;
 816         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
 817
 818         /* Second function's parameters follow the first
 819          * function's.
 820          */
 821         if (qdev->port)
 822                 offset = size;
 823
 824         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 825                 return -ETIMEDOUT;
 826
 827         for (i = 0; i < size; i++, p++) {
 828                 status = ql_read_flash_word(qdev, i+offset, p);
 829                 if (status) {
 830                         netif_err(qdev, ifup, qdev->ndev,
 831                                   "Error reading flash.\n");
 832                         goto exit;
 833                 }
 834
 835         }
 836
 837         status = ql_validate_flash(qdev,
 838                         sizeof(struct flash_params_8012) / sizeof(u16),
 839                         "8012");
 840         if (status) {
 841                 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
 842                 status = -EINVAL;
 843                 goto exit;
 844         }
 845
 846         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
 847                 status = -EINVAL;
 848                 goto exit;
 849         }
 850
 851         memcpy(qdev->ndev->dev_addr,
 852                 qdev->flash.flash_params_8012.mac_addr,
 853                 qdev->ndev->addr_len);
 854
 855 exit:
 856         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 857         return status;
 858 }
 859
 860 /* xgmac register are located behind the xgmac_addr and xgmac_data
 861  * register pair.  Each read/write requires us to wait for the ready
 862  * bit before reading/writing the data.
 863  */
 864 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 865 {
 866         int status;
 867         /* wait for reg to come ready */
 868         status = ql_wait_reg_rdy(qdev,
 869                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 870         if (status)
 871                 return status;
 872         /* write the data to the data reg */
 873         ql_write32(qdev, XGMAC_DATA, data);
 874         /* trigger the write */
 875         ql_write32(qdev, XGMAC_ADDR, reg);
 876         return status;
 877 }
 878
 879 /* xgmac register are located behind the xgmac_addr and xgmac_data
 880  * register pair.  Each read/write requires us to wait for the ready
 881  * bit before reading/writing the data.
 882  */
 883 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 884 {
 885         int status = 0;
 886         /* wait for reg to come ready */
 887         status = ql_wait_reg_rdy(qdev,
 888                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 889         if (status)
 890                 goto exit;
 891         /* set up for reg read */
 892         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 893         /* wait for reg to come ready */
 894         status = ql_wait_reg_rdy(qdev,
 895                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 896         if (status)
 897                 goto exit;
 898         /* get the data */
 899         *data = ql_read32(qdev, XGMAC_DATA);
 900 exit:
 901         return status;
 902 }
 903
 904 /* This is used for reading the 64-bit statistics regs. */
 905 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 906 {
 907         int status = 0;
 908         u32 hi = 0;
 909         u32 lo = 0;
 910
 911         status = ql_read_xgmac_reg(qdev, reg, &lo);
 912         if (status)
 913                 goto exit;
 914
 915         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 916         if (status)
 917                 goto exit;
 918
 919         *data = (u64) lo | ((u64) hi << 32);
 920
 921 exit:
 922         return status;
 923 }
 924
 925 static int ql_8000_port_initialize(struct ql_adapter *qdev)
 926 {
 927         int status;
 928         /*
 929          * Get MPI firmware version for driver banner
 930          * and ethool info.
 931          */
 932         status = ql_mb_about_fw(qdev);
 933         if (status)
 934                 goto exit;
 935         status = ql_mb_get_fw_state(qdev);
 936         if (status)
 937                 goto exit;
 938         /* Wake up a worker to get/set the TX/RX frame sizes. */
 939         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
 940 exit:
 941         return status;
 942 }
 943
 944 /* Take the MAC Core out of reset.
 945  * Enable statistics counting.
 946  * Take the transmitter/receiver out of reset.
 947  * This functionality may be done in the MPI firmware at a
 948  * later date.
 949  */
 950 static int ql_8012_port_initialize(struct ql_adapter *qdev)
 951 {
 952         int status = 0;
 953         u32 data;
 954
 955         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 956                 /* Another function has the semaphore, so
 957                  * wait for the port init bit to come ready.
 958                  */
 959                 netif_info(qdev, link, qdev->ndev,
 960                            "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 961                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 962                 if (status) {
 963                         netif_crit(qdev, link, qdev->ndev,
 964                                    "Port initialize timed out.\n");
 965                 }
 966                 return status;
 967         }
 968
 969         netif_info(qdev, link, qdev->ndev, "Got xgmac semaphore!.\n");
 970         /* Set the core reset. */
 971         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 972         if (status)
 973                 goto end;
 974         data |= GLOBAL_CFG_RESET;
 975         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 976         if (status)
 977                 goto end;
 978
 979         /* Clear the core reset and turn on jumbo for receiver. */
 980         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 981         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 982         data |= GLOBAL_CFG_TX_STAT_EN;
 983         data |= GLOBAL_CFG_RX_STAT_EN;
 984         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 985         if (status)
 986                 goto end;
 987
 988         /* Enable transmitter, and clear it's reset. */
 989         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 990         if (status)
 991                 goto end;
 992         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 993         data |= TX_CFG_EN;      /* Enable the transmitter. */
 994         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 995         if (status)
 996                 goto end;
 997
 998         /* Enable receiver and clear it's reset. */
 999         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
1000         if (status)
1001                 goto end;
1002         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
1003         data |= RX_CFG_EN;      /* Enable the receiver. */
1004         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
1005         if (status)
1006                 goto end;
1007
1008         /* Turn on jumbo. */
1009         status =
1010             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
1011         if (status)
1012                 goto end;
1013         status =
1014             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
1015         if (status)
1016                 goto end;
1017
1018         /* Signal to the world that the port is enabled.        */
1019         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
1020 end:
1021         ql_sem_unlock(qdev, qdev->xg_sem_mask);
1022         return status;
1023 }
1024
1025 static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev)
1026 {
1027         return PAGE_SIZE << qdev->lbq_buf_order;
1028 }
1029
1030 /* Get the next large buffer. */
1031 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
1032 {
1033         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
1034         rx_ring->lbq_curr_idx++;
1035         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
1036                 rx_ring->lbq_curr_idx = 0;
1037         rx_ring->lbq_free_cnt++;
1038         return lbq_desc;
1039 }
1040
1041 static struct bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev,
1042                 struct rx_ring *rx_ring)
1043 {
1044         struct bq_desc *lbq_desc = ql_get_curr_lbuf(rx_ring);
1045
1046         pci_dma_sync_single_for_cpu(qdev->pdev,
1047                                         dma_unmap_addr(lbq_desc, mapaddr),
1048                                     rx_ring->lbq_buf_size,
1049                                         PCI_DMA_FROMDEVICE);
1050
1051         /* If it's the last chunk of our master page then
1052          * we unmap it.
1053          */
1054         if ((lbq_desc->p.pg_chunk.offset + rx_ring->lbq_buf_size)
1055                                         == ql_lbq_block_size(qdev))
1056                 pci_unmap_page(qdev->pdev,
1057                                 lbq_desc->p.pg_chunk.map,
1058                                 ql_lbq_block_size(qdev),
1059                                 PCI_DMA_FROMDEVICE);
1060         return lbq_desc;
1061 }
1062
1063 /* Get the next small buffer. */
1064 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
1065 {
1066         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
1067         rx_ring->sbq_curr_idx++;
1068         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
1069                 rx_ring->sbq_curr_idx = 0;
1070         rx_ring->sbq_free_cnt++;
1071         return sbq_desc;
1072 }
1073
1074 /* Update an rx ring index. */
1075 static void ql_update_cq(struct rx_ring *rx_ring)
1076 {
1077         rx_ring->cnsmr_idx++;
1078         rx_ring->curr_entry++;
1079         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
1080                 rx_ring->cnsmr_idx = 0;
1081                 rx_ring->curr_entry = rx_ring->cq_base;
1082         }
1083 }
1084
1085 static void ql_write_cq_idx(struct rx_ring *rx_ring)
1086 {
1087         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
1088 }
1089
1090 static int ql_get_next_chunk(struct ql_adapter *qdev, struct rx_ring *rx_ring,
1091                                                 struct bq_desc *lbq_desc)
1092 {
1093         if (!rx_ring->pg_chunk.page) {
1094                 u64 map;
1095                 rx_ring->pg_chunk.page = alloc_pages(__GFP_COLD | __GFP_COMP |
1096                                                 GFP_ATOMIC,
1097                                                 qdev->lbq_buf_order);
1098                 if (unlikely(!rx_ring->pg_chunk.page)) {
1099                         netif_err(qdev, drv, qdev->ndev,
1100                                   "page allocation failed.\n");
1101                         return -ENOMEM;
1102                 }
1103                 rx_ring->pg_chunk.offset = 0;
1104                 map = pci_map_page(qdev->pdev, rx_ring->pg_chunk.page,
1105                                         0, ql_lbq_block_size(qdev),
1106                                         PCI_DMA_FROMDEVICE);
1107                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1108                         __free_pages(rx_ring->pg_chunk.page,
1109                                         qdev->lbq_buf_order);
1110                         rx_ring->pg_chunk.page = NULL;
1111                         netif_err(qdev, drv, qdev->ndev,
1112                                   "PCI mapping failed.\n");
1113                         return -ENOMEM;
1114                 }
1115                 rx_ring->pg_chunk.map = map;
1116                 rx_ring->pg_chunk.va = page_address(rx_ring->pg_chunk.page);
1117         }
1118
1119         /* Copy the current master pg_chunk info
1120          * to the current descriptor.
1121          */
1122         lbq_desc->p.pg_chunk = rx_ring->pg_chunk;
1123
1124         /* Adjust the master page chunk for next
1125          * buffer get.
1126          */
1127         rx_ring->pg_chunk.offset += rx_ring->lbq_buf_size;
1128         if (rx_ring->pg_chunk.offset == ql_lbq_block_size(qdev)) {
1129                 rx_ring->pg_chunk.page = NULL;
1130                 lbq_desc->p.pg_chunk.last_flag = 1;
1131         } else {
1132                 rx_ring->pg_chunk.va += rx_ring->lbq_buf_size;
1133                 get_page(rx_ring->pg_chunk.page);
1134                 lbq_desc->p.pg_chunk.last_flag = 0;
1135         }
1136         return 0;
1137 }
1138 /* Process (refill) a large buffer queue. */
1139 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1140 {
1141         u32 clean_idx = rx_ring->lbq_clean_idx;
1142         u32 start_idx = clean_idx;
1143         struct bq_desc *lbq_desc;
1144         u64 map;
1145         int i;
1146
1147         while (rx_ring->lbq_free_cnt > 32) {
1148                 for (i = (rx_ring->lbq_clean_idx % 16); i < 16; i++) {
1149                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1150                                      "lbq: try cleaning clean_idx = %d.\n",
1151                                      clean_idx);
1152                         lbq_desc = &rx_ring->lbq[clean_idx];
1153                         if (ql_get_next_chunk(qdev, rx_ring, lbq_desc)) {
1154                                 rx_ring->lbq_clean_idx = clean_idx;
1155                                 netif_err(qdev, ifup, qdev->ndev,
1156                                                 "Could not get a page chunk, i=%d, clean_idx =%d .\n",
1157                                                 i, clean_idx);
1158                                 return;
1159                         }
1160
1161                         map = lbq_desc->p.pg_chunk.map +
1162                                 lbq_desc->p.pg_chunk.offset;
1163                                 dma_unmap_addr_set(lbq_desc, mapaddr, map);
1164                         dma_unmap_len_set(lbq_desc, maplen,
1165                                         rx_ring->lbq_buf_size);
1166                                 *lbq_desc->addr = cpu_to_le64(map);
1167
1168                         pci_dma_sync_single_for_device(qdev->pdev, map,
1169                                                 rx_ring->lbq_buf_size,
1170                                                 PCI_DMA_FROMDEVICE);
1171                         clean_idx++;
1172                         if (clean_idx == rx_ring->lbq_len)
1173                                 clean_idx = 0;
1174                 }
1175
1176                 rx_ring->lbq_clean_idx = clean_idx;
1177                 rx_ring->lbq_prod_idx += 16;
1178                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1179                         rx_ring->lbq_prod_idx = 0;
1180                 rx_ring->lbq_free_cnt -= 16;
1181         }
1182
1183         if (start_idx != clean_idx) {
1184                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1185                              "lbq: updating prod idx = %d.\n",
1186                              rx_ring->lbq_prod_idx);
1187                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1188                                 rx_ring->lbq_prod_idx_db_reg);
1189         }
1190 }
1191
1192 /* Process (refill) a small buffer queue. */
1193 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1194 {
1195         u32 clean_idx = rx_ring->sbq_clean_idx;
1196         u32 start_idx = clean_idx;
1197         struct bq_desc *sbq_desc;
1198         u64 map;
1199         int i;
1200
1201         while (rx_ring->sbq_free_cnt > 16) {
1202                 for (i = (rx_ring->sbq_clean_idx % 16); i < 16; i++) {
1203                         sbq_desc = &rx_ring->sbq[clean_idx];
1204                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1205                                      "sbq: try cleaning clean_idx = %d.\n",
1206                                      clean_idx);
1207                         if (sbq_desc->p.skb == NULL) {
1208                                 netif_printk(qdev, rx_status, KERN_DEBUG,
1209                                              qdev->ndev,
1210                                              "sbq: getting new skb for index %d.\n",
1211                                              sbq_desc->index);
1212                                 sbq_desc->p.skb =
1213                                     netdev_alloc_skb(qdev->ndev,
1214                                                      SMALL_BUFFER_SIZE);
1215                                 if (sbq_desc->p.skb == NULL) {
1216                                         rx_ring->sbq_clean_idx = clean_idx;
1217                                         return;
1218                                 }
1219                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1220                                 map = pci_map_single(qdev->pdev,
1221                                                      sbq_desc->p.skb->data,
1222                                                      rx_ring->sbq_buf_size,
1223                                                      PCI_DMA_FROMDEVICE);
1224                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1225                                         netif_err(qdev, ifup, qdev->ndev,
1226                                                   "PCI mapping failed.\n");
1227                                         rx_ring->sbq_clean_idx = clean_idx;
1228                                         dev_kfree_skb_any(sbq_desc->p.skb);
1229                                         sbq_desc->p.skb = NULL;
1230                                         return;
1231                                 }
1232                                 dma_unmap_addr_set(sbq_desc, mapaddr, map);
1233                                 dma_unmap_len_set(sbq_desc, maplen,
1234                                                   rx_ring->sbq_buf_size);
1235                                 *sbq_desc->addr = cpu_to_le64(map);
1236                         }
1237
1238                         clean_idx++;
1239                         if (clean_idx == rx_ring->sbq_len)
1240                                 clean_idx = 0;
1241                 }
1242                 rx_ring->sbq_clean_idx = clean_idx;
1243                 rx_ring->sbq_prod_idx += 16;
1244                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1245                         rx_ring->sbq_prod_idx = 0;
1246                 rx_ring->sbq_free_cnt -= 16;
1247         }
1248
1249         if (start_idx != clean_idx) {
1250                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1251                              "sbq: updating prod idx = %d.\n",
1252                              rx_ring->sbq_prod_idx);
1253                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1254                                 rx_ring->sbq_prod_idx_db_reg);
1255         }
1256 }
1257
1258 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1259                                     struct rx_ring *rx_ring)
1260 {
1261         ql_update_sbq(qdev, rx_ring);
1262         ql_update_lbq(qdev, rx_ring);
1263 }
1264
1265 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1266  * fails at some stage, or from the interrupt when a tx completes.
1267  */
1268 static void ql_unmap_send(struct ql_adapter *qdev,
1269                           struct tx_ring_desc *tx_ring_desc, int mapped)
1270 {
1271         int i;
1272         for (i = 0; i < mapped; i++) {
1273                 if (i == 0 || (i == 7 && mapped > 7)) {
1274                         /*
1275                          * Unmap the skb->data area, or the
1276                          * external sglist (AKA the Outbound
1277                          * Address List (OAL)).
1278                          * If its the zeroeth element, then it's
1279                          * the skb->data area.  If it's the 7th
1280                          * element and there is more than 6 frags,
1281                          * then its an OAL.
1282                          */
1283                         if (i == 7) {
1284                                 netif_printk(qdev, tx_done, KERN_DEBUG,
1285                                              qdev->ndev,
1286                                              "unmapping OAL area.\n");
1287                         }
1288                         pci_unmap_single(qdev->pdev,
1289                                          dma_unmap_addr(&tx_ring_desc->map[i],
1290                                                         mapaddr),
1291                                          dma_unmap_len(&tx_ring_desc->map[i],
1292                                                        maplen),
1293                                          PCI_DMA_TODEVICE);
1294                 } else {
1295                         netif_printk(qdev, tx_done, KERN_DEBUG, qdev->ndev,
1296                                      "unmapping frag %d.\n", i);
1297                         pci_unmap_page(qdev->pdev,
1298                                        dma_unmap_addr(&tx_ring_desc->map[i],
1299                                                       mapaddr),
1300                                        dma_unmap_len(&tx_ring_desc->map[i],
1301                                                      maplen), PCI_DMA_TODEVICE);
1302                 }
1303         }
1304
1305 }
1306
1307 /* Map the buffers for this transmit.  This will return
1308  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1309  */
1310 static int ql_map_send(struct ql_adapter *qdev,
1311                        struct ob_mac_iocb_req *mac_iocb_ptr,
1312                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1313 {
1314         int len = skb_headlen(skb);
1315         dma_addr_t map;
1316         int frag_idx, err, map_idx = 0;
1317         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1318         int frag_cnt = skb_shinfo(skb)->nr_frags;
1319
1320         if (frag_cnt) {
1321                 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
1322                              "frag_cnt = %d.\n", frag_cnt);
1323         }
1324         /*
1325          * Map the skb buffer first.
1326          */
1327         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1328
1329         err = pci_dma_mapping_error(qdev->pdev, map);
1330         if (err) {
1331                 netif_err(qdev, tx_queued, qdev->ndev,
1332                           "PCI mapping failed with error: %d\n", err);
1333
1334                 return NETDEV_TX_BUSY;
1335         }
1336
1337         tbd->len = cpu_to_le32(len);
1338         tbd->addr = cpu_to_le64(map);
1339         dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1340         dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1341         map_idx++;
1342
1343         /*
1344          * This loop fills the remainder of the 8 address descriptors
1345          * in the IOCB.  If there are more than 7 fragments, then the
1346          * eighth address desc will point to an external list (OAL).
1347          * When this happens, the remainder of the frags will be stored
1348          * in this list.
1349          */
1350         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1351                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1352                 tbd++;
1353                 if (frag_idx == 6 && frag_cnt > 7) {
1354                         /* Let's tack on an sglist.
1355                          * Our control block will now
1356                          * look like this:
1357                          * iocb->seg[0] = skb->data
1358                          * iocb->seg[1] = frag[0]
1359                          * iocb->seg[2] = frag[1]
1360                          * iocb->seg[3] = frag[2]
1361                          * iocb->seg[4] = frag[3]
1362                          * iocb->seg[5] = frag[4]
1363                          * iocb->seg[6] = frag[5]
1364                          * iocb->seg[7] = ptr to OAL (external sglist)
1365                          * oal->seg[0] = frag[6]
1366                          * oal->seg[1] = frag[7]
1367                          * oal->seg[2] = frag[8]
1368                          * oal->seg[3] = frag[9]
1369                          * oal->seg[4] = frag[10]
1370                          *      etc...
1371                          */
1372                         /* Tack on the OAL in the eighth segment of IOCB. */
1373                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1374                                              sizeof(struct oal),
1375                                              PCI_DMA_TODEVICE);
1376                         err = pci_dma_mapping_error(qdev->pdev, map);
1377                         if (err) {
1378                                 netif_err(qdev, tx_queued, qdev->ndev,
1379                                           "PCI mapping outbound address list with error: %d\n",
1380                                           err);
1381                                 goto map_error;
1382                         }
1383
1384                         tbd->addr = cpu_to_le64(map);
1385                         /*
1386                          * The length is the number of fragments
1387                          * that remain to be mapped times the length
1388                          * of our sglist (OAL).
1389                          */
1390                         tbd->len =
1391                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1392                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1393                         dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1394                                            map);
1395                         dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1396                                           sizeof(struct oal));
1397                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1398                         map_idx++;
1399                 }
1400
1401                 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
1402                                        DMA_TO_DEVICE);
1403
1404                 err = dma_mapping_error(&qdev->pdev->dev, map);
1405                 if (err) {
1406                         netif_err(qdev, tx_queued, qdev->ndev,
1407                                   "PCI mapping frags failed with error: %d.\n",
1408                                   err);
1409                         goto map_error;
1410                 }
1411
1412                 tbd->addr = cpu_to_le64(map);
1413                 tbd->len = cpu_to_le32(skb_frag_size(frag));
1414                 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1415                 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1416                                   skb_frag_size(frag));
1417
1418         }
1419         /* Save the number of segments we've mapped. */
1420         tx_ring_desc->map_cnt = map_idx;
1421         /* Terminate the last segment. */
1422         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1423         return NETDEV_TX_OK;
1424
1425 map_error:
1426         /*
1427          * If the first frag mapping failed, then i will be zero.
1428          * This causes the unmap of the skb->data area.  Otherwise
1429          * we pass in the number of frags that mapped successfully
1430          * so they can be umapped.
1431          */
1432         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1433         return NETDEV_TX_BUSY;
1434 }
1435
1436 /* Categorizing receive firmware frame errors */
1437 static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err,
1438                                  struct rx_ring *rx_ring)
1439 {
1440         struct nic_stats *stats = &qdev->nic_stats;
1441
1442         stats->rx_err_count++;
1443         rx_ring->rx_errors++;
1444
1445         switch (rx_err & IB_MAC_IOCB_RSP_ERR_MASK) {
1446         case IB_MAC_IOCB_RSP_ERR_CODE_ERR:
1447                 stats->rx_code_err++;
1448                 break;
1449         case IB_MAC_IOCB_RSP_ERR_OVERSIZE:
1450                 stats->rx_oversize_err++;
1451                 break;
1452         case IB_MAC_IOCB_RSP_ERR_UNDERSIZE:
1453                 stats->rx_undersize_err++;
1454                 break;
1455         case IB_MAC_IOCB_RSP_ERR_PREAMBLE:
1456                 stats->rx_preamble_err++;
1457                 break;
1458         case IB_MAC_IOCB_RSP_ERR_FRAME_LEN:
1459                 stats->rx_frame_len_err++;
1460                 break;
1461         case IB_MAC_IOCB_RSP_ERR_CRC:
1462                 stats->rx_crc_err++;
1463         default:
1464                 break;
1465         }
1466 }
1467
1468 /**
1469  * ql_update_mac_hdr_len - helper routine to update the mac header length
1470  * based on vlan tags if present
1471  */
1472 static void ql_update_mac_hdr_len(struct ql_adapter *qdev,
1473                                   struct ib_mac_iocb_rsp *ib_mac_rsp,
1474                                   void *page, size_t *len)
1475 {
1476         u16 *tags;
1477
1478         if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
1479                 return;
1480         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) {
1481                 tags = (u16 *)page;
1482                 /* Look for stacked vlan tags in ethertype field */
1483                 if (tags[6] == ETH_P_8021Q &&
1484                     tags[8] == ETH_P_8021Q)
1485                         *len += 2 * VLAN_HLEN;
1486                 else
1487                         *len += VLAN_HLEN;
1488         }
1489 }
1490
1491 /* Process an inbound completion from an rx ring. */
1492 static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev,
1493                                         struct rx_ring *rx_ring,
1494                                         struct ib_mac_iocb_rsp *ib_mac_rsp,
1495                                         u32 length,
1496                                         u16 vlan_id)
1497 {
1498         struct sk_buff *skb;
1499         struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1500         struct napi_struct *napi = &rx_ring->napi;
1501
1502         /* Frame error, so drop the packet. */
1503         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1504                 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1505                 put_page(lbq_desc->p.pg_chunk.page);
1506                 return;
1507         }
1508         napi->dev = qdev->ndev;
1509
1510         skb = napi_get_frags(napi);
1511         if (!skb) {
1512                 netif_err(qdev, drv, qdev->ndev,
1513                           "Couldn't get an skb, exiting.\n");
1514                 rx_ring->rx_dropped++;
1515                 put_page(lbq_desc->p.pg_chunk.page);
1516                 return;
1517         }
1518         prefetch(lbq_desc->p.pg_chunk.va);
1519         __skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1520                              lbq_desc->p.pg_chunk.page,
1521                              lbq_desc->p.pg_chunk.offset,
1522                              length);
1523
1524         skb->len += length;
1525         skb->data_len += length;
1526         skb->truesize += length;
1527         skb_shinfo(skb)->nr_frags++;
1528
1529         rx_ring->rx_packets++;
1530         rx_ring->rx_bytes += length;
1531         skb->ip_summed = CHECKSUM_UNNECESSARY;
1532         skb_record_rx_queue(skb, rx_ring->cq_id);
1533         if (vlan_id != 0xffff)
1534                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1535         napi_gro_frags(napi);
1536 }
1537
1538 /* Process an inbound completion from an rx ring. */
1539 static void ql_process_mac_rx_page(struct ql_adapter *qdev,
1540                                         struct rx_ring *rx_ring,
1541                                         struct ib_mac_iocb_rsp *ib_mac_rsp,
1542                                         u32 length,
1543                                         u16 vlan_id)
1544 {
1545         struct net_device *ndev = qdev->ndev;
1546         struct sk_buff *skb = NULL;
1547         void *addr;
1548         struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1549         struct napi_struct *napi = &rx_ring->napi;
1550         size_t hlen = ETH_HLEN;
1551
1552         skb = netdev_alloc_skb(ndev, length);
1553         if (!skb) {
1554                 rx_ring->rx_dropped++;
1555                 put_page(lbq_desc->p.pg_chunk.page);
1556                 return;
1557         }
1558
1559         addr = lbq_desc->p.pg_chunk.va;
1560         prefetch(addr);
1561
1562         /* Frame error, so drop the packet. */
1563         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1564                 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1565                 goto err_out;
1566         }
1567
1568         /* Update the MAC header length*/
1569         ql_update_mac_hdr_len(qdev, ib_mac_rsp, addr, &hlen);
1570
1571         /* The max framesize filter on this chip is set higher than
1572          * MTU since FCoE uses 2k frames.
1573          */
1574         if (skb->len > ndev->mtu + hlen) {
1575                 netif_err(qdev, drv, qdev->ndev,
1576                           "Segment too small, dropping.\n");
1577                 rx_ring->rx_dropped++;
1578                 goto err_out;
1579         }
1580         memcpy(skb_put(skb, hlen), addr, hlen);
1581         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1582                      "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1583                      length);
1584         skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1585                                 lbq_desc->p.pg_chunk.offset + hlen,
1586                                 length - hlen);
1587         skb->len += length - hlen;
1588         skb->data_len += length - hlen;
1589         skb->truesize += length - hlen;
1590
1591         rx_ring->rx_packets++;
1592         rx_ring->rx_bytes += skb->len;
1593         skb->protocol = eth_type_trans(skb, ndev);
1594         skb_checksum_none_assert(skb);
1595
1596         if ((ndev->features & NETIF_F_RXCSUM) &&
1597                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1598                 /* TCP frame. */
1599                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1600                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1601                                      "TCP checksum done!\n");
1602                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1603                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1604                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1605                         /* Unfragmented ipv4 UDP frame. */
1606                         struct iphdr *iph =
1607                                 (struct iphdr *)((u8 *)addr + hlen);
1608                         if (!(iph->frag_off &
1609                                 htons(IP_MF|IP_OFFSET))) {
1610                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1611                                 netif_printk(qdev, rx_status, KERN_DEBUG,
1612                                              qdev->ndev,
1613                                              "UDP checksum done!\n");
1614                         }
1615                 }
1616         }
1617
1618         skb_record_rx_queue(skb, rx_ring->cq_id);
1619         if (vlan_id != 0xffff)
1620                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1621         if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1622                 napi_gro_receive(napi, skb);
1623         else
1624                 netif_receive_skb(skb);
1625         return;
1626 err_out:
1627         dev_kfree_skb_any(skb);
1628         put_page(lbq_desc->p.pg_chunk.page);
1629 }
1630
1631 /* Process an inbound completion from an rx ring. */
1632 static void ql_process_mac_rx_skb(struct ql_adapter *qdev,
1633                                         struct rx_ring *rx_ring,
1634                                         struct ib_mac_iocb_rsp *ib_mac_rsp,
1635                                         u32 length,
1636                                         u16 vlan_id)
1637 {
1638         struct net_device *ndev = qdev->ndev;
1639         struct sk_buff *skb = NULL;
1640         struct sk_buff *new_skb = NULL;
1641         struct bq_desc *sbq_desc = ql_get_curr_sbuf(rx_ring);
1642
1643         skb = sbq_desc->p.skb;
1644         /* Allocate new_skb and copy */
1645         new_skb = netdev_alloc_skb(qdev->ndev, length + NET_IP_ALIGN);
1646         if (new_skb == NULL) {
1647                 rx_ring->rx_dropped++;
1648                 return;
1649         }
1650         skb_reserve(new_skb, NET_IP_ALIGN);
1651
1652         pci_dma_sync_single_for_cpu(qdev->pdev,
1653                                     dma_unmap_addr(sbq_desc, mapaddr),
1654                                     dma_unmap_len(sbq_desc, maplen),
1655                                     PCI_DMA_FROMDEVICE);
1656
1657         memcpy(skb_put(new_skb, length), skb->data, length);
1658
1659         pci_dma_sync_single_for_device(qdev->pdev,
1660                                        dma_unmap_addr(sbq_desc, mapaddr),
1661                                        dma_unmap_len(sbq_desc, maplen),
1662                                        PCI_DMA_FROMDEVICE);
1663         skb = new_skb;
1664
1665         /* Frame error, so drop the packet. */
1666         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1667                 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1668                 dev_kfree_skb_any(skb);
1669                 return;
1670         }
1671
1672         /* loopback self test for ethtool */
1673         if (test_bit(QL_SELFTEST, &qdev->flags)) {
1674                 ql_check_lb_frame(qdev, skb);
1675                 dev_kfree_skb_any(skb);
1676                 return;
1677         }
1678
1679         /* The max framesize filter on this chip is set higher than
1680          * MTU since FCoE uses 2k frames.
1681          */
1682         if (skb->len > ndev->mtu + ETH_HLEN) {
1683                 dev_kfree_skb_any(skb);
1684                 rx_ring->rx_dropped++;
1685                 return;
1686         }
1687
1688         prefetch(skb->data);
1689         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1690                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1691                              "%s Multicast.\n",
1692                              (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1693                              IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
1694                              (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1695                              IB_MAC_IOCB_RSP_M_REG ? "Registered" :
1696                              (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1697                              IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1698         }
1699         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P)
1700                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1701                              "Promiscuous Packet.\n");
1702
1703         rx_ring->rx_packets++;
1704         rx_ring->rx_bytes += skb->len;
1705         skb->protocol = eth_type_trans(skb, ndev);
1706         skb_checksum_none_assert(skb);
1707
1708         /* If rx checksum is on, and there are no
1709          * csum or frame errors.
1710          */
1711         if ((ndev->features & NETIF_F_RXCSUM) &&
1712                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1713                 /* TCP frame. */
1714                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1715                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1716                                      "TCP checksum done!\n");
1717                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1718                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1719                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1720                         /* Unfragmented ipv4 UDP frame. */
1721                         struct iphdr *iph = (struct iphdr *) skb->data;
1722                         if (!(iph->frag_off &
1723                                 htons(IP_MF|IP_OFFSET))) {
1724                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1725                                 netif_printk(qdev, rx_status, KERN_DEBUG,
1726                                              qdev->ndev,
1727                                              "UDP checksum done!\n");
1728                         }
1729                 }
1730         }
1731
1732         skb_record_rx_queue(skb, rx_ring->cq_id);
1733         if (vlan_id != 0xffff)
1734                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1735         if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1736                 napi_gro_receive(&rx_ring->napi, skb);
1737         else
1738                 netif_receive_skb(skb);
1739 }
1740
1741 static void ql_realign_skb(struct sk_buff *skb, int len)
1742 {
1743         void *temp_addr = skb->data;
1744
1745         /* Undo the skb_reserve(skb,32) we did before
1746          * giving to hardware, and realign data on
1747          * a 2-byte boundary.
1748          */
1749         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1750         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1751         skb_copy_to_linear_data(skb, temp_addr,
1752                 (unsigned int)len);
1753 }
1754
1755 /*
1756  * This function builds an skb for the given inbound
1757  * completion.  It will be rewritten for readability in the near
1758  * future, but for not it works well.
1759  */
1760 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1761                                        struct rx_ring *rx_ring,
1762                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1763 {
1764         struct bq_desc *lbq_desc;
1765         struct bq_desc *sbq_desc;
1766         struct sk_buff *skb = NULL;
1767         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1768         u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1769         size_t hlen = ETH_HLEN;
1770
1771         /*
1772          * Handle the header buffer if present.
1773          */
1774         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1775             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1776                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1777                              "Header of %d bytes in small buffer.\n", hdr_len);
1778                 /*
1779                  * Headers fit nicely into a small buffer.
1780                  */
1781                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1782                 pci_unmap_single(qdev->pdev,
1783                                 dma_unmap_addr(sbq_desc, mapaddr),
1784                                 dma_unmap_len(sbq_desc, maplen),
1785                                 PCI_DMA_FROMDEVICE);
1786                 skb = sbq_desc->p.skb;
1787                 ql_realign_skb(skb, hdr_len);
1788                 skb_put(skb, hdr_len);
1789                 sbq_desc->p.skb = NULL;
1790         }
1791
1792         /*
1793          * Handle the data buffer(s).
1794          */
1795         if (unlikely(!length)) {        /* Is there data too? */
1796                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1797                              "No Data buffer in this packet.\n");
1798                 return skb;
1799         }
1800
1801         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1802                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1803                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1804                                      "Headers in small, data of %d bytes in small, combine them.\n",
1805                                      length);
1806                         /*
1807                          * Data is less than small buffer size so it's
1808                          * stuffed in a small buffer.
1809                          * For this case we append the data
1810                          * from the "data" small buffer to the "header" small
1811                          * buffer.
1812                          */
1813                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1814                         pci_dma_sync_single_for_cpu(qdev->pdev,
1815                                                     dma_unmap_addr
1816                                                     (sbq_desc, mapaddr),
1817                                                     dma_unmap_len
1818                                                     (sbq_desc, maplen),
1819                                                     PCI_DMA_FROMDEVICE);
1820                         memcpy(skb_put(skb, length),
1821                                sbq_desc->p.skb->data, length);
1822                         pci_dma_sync_single_for_device(qdev->pdev,
1823                                                        dma_unmap_addr
1824                                                        (sbq_desc,
1825                                                         mapaddr),
1826                                                        dma_unmap_len
1827                                                        (sbq_desc,
1828                                                         maplen),
1829                                                        PCI_DMA_FROMDEVICE);
1830                 } else {
1831                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1832                                      "%d bytes in a single small buffer.\n",
1833                                      length);
1834                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1835                         skb = sbq_desc->p.skb;
1836                         ql_realign_skb(skb, length);
1837                         skb_put(skb, length);
1838                         pci_unmap_single(qdev->pdev,
1839                                          dma_unmap_addr(sbq_desc,
1840                                                         mapaddr),
1841                                          dma_unmap_len(sbq_desc,
1842                                                        maplen),
1843                                          PCI_DMA_FROMDEVICE);
1844                         sbq_desc->p.skb = NULL;
1845                 }
1846         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1847                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1848                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1849                                      "Header in small, %d bytes in large. Chain large to small!\n",
1850                                      length);
1851                         /*
1852                          * The data is in a single large buffer.  We
1853                          * chain it to the header buffer's skb and let
1854                          * it rip.
1855                          */
1856                         lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1857                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1858                                      "Chaining page at offset = %d, for %d bytes  to skb.\n",
1859                                      lbq_desc->p.pg_chunk.offset, length);
1860                         skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1861                                                 lbq_desc->p.pg_chunk.offset,
1862                                                 length);
1863                         skb->len += length;
1864                         skb->data_len += length;
1865                         skb->truesize += length;
1866                 } else {
1867                         /*
1868                          * The headers and data are in a single large buffer. We
1869                          * copy it to a new skb and let it go. This can happen with
1870                          * jumbo mtu on a non-TCP/UDP frame.
1871                          */
1872                         lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1873                         skb = netdev_alloc_skb(qdev->ndev, length);
1874                         if (skb == NULL) {
1875                                 netif_printk(qdev, probe, KERN_DEBUG, qdev->ndev,
1876                                              "No skb available, drop the packet.\n");
1877                                 return NULL;
1878                         }
1879                         pci_unmap_page(qdev->pdev,
1880                                        dma_unmap_addr(lbq_desc,
1881                                                       mapaddr),
1882                                        dma_unmap_len(lbq_desc, maplen),
1883                                        PCI_DMA_FROMDEVICE);
1884                         skb_reserve(skb, NET_IP_ALIGN);
1885                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1886                                      "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1887                                      length);
1888                         skb_fill_page_desc(skb, 0,
1889                                                 lbq_desc->p.pg_chunk.page,
1890                                                 lbq_desc->p.pg_chunk.offset,
1891                                                 length);
1892                         skb->len += length;
1893                         skb->data_len += length;
1894                         skb->truesize += length;
1895                         length -= length;
1896                         ql_update_mac_hdr_len(qdev, ib_mac_rsp,
1897                                               lbq_desc->p.pg_chunk.va,
1898                                               &hlen);
1899                         __pskb_pull_tail(skb, hlen);
1900                 }
1901         } else {
1902                 /*
1903                  * The data is in a chain of large buffers
1904                  * pointed to by a small buffer.  We loop
1905                  * thru and chain them to the our small header
1906                  * buffer's skb.
1907                  * frags:  There are 18 max frags and our small
1908                  *         buffer will hold 32 of them. The thing is,
1909                  *         we'll use 3 max for our 9000 byte jumbo
1910                  *         frames.  If the MTU goes up we could
1911                  *          eventually be in trouble.
1912                  */
1913                 int size, i = 0;
1914                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1915                 pci_unmap_single(qdev->pdev,
1916                                  dma_unmap_addr(sbq_desc, mapaddr),
1917                                  dma_unmap_len(sbq_desc, maplen),
1918                                  PCI_DMA_FROMDEVICE);
1919                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1920                         /*
1921                          * This is an non TCP/UDP IP frame, so
1922                          * the headers aren't split into a small
1923                          * buffer.  We have to use the small buffer
1924                          * that contains our sg list as our skb to
1925                          * send upstairs. Copy the sg list here to
1926                          * a local buffer and use it to find the
1927                          * pages to chain.
1928                          */
1929                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1930                                      "%d bytes of headers & data in chain of large.\n",
1931                                      length);
1932                         skb = sbq_desc->p.skb;
1933                         sbq_desc->p.skb = NULL;
1934                         skb_reserve(skb, NET_IP_ALIGN);
1935                 }
1936                 do {
1937                         lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1938                         size = (length < rx_ring->lbq_buf_size) ? length :
1939                                 rx_ring->lbq_buf_size;
1940
1941                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1942                                      "Adding page %d to skb for %d bytes.\n",
1943                                      i, size);
1944                         skb_fill_page_desc(skb, i,
1945                                                 lbq_desc->p.pg_chunk.page,
1946                                                 lbq_desc->p.pg_chunk.offset,
1947                                                 size);
1948                         skb->len += size;
1949                         skb->data_len += size;
1950                         skb->truesize += size;
1951                         length -= size;
1952                         i++;
1953                 } while (length > 0);
1954                 ql_update_mac_hdr_len(qdev, ib_mac_rsp, lbq_desc->p.pg_chunk.va,
1955                                       &hlen);
1956                 __pskb_pull_tail(skb, hlen);
1957         }
1958         return skb;
1959 }
1960
1961 /* Process an inbound completion from an rx ring. */
1962 static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev,
1963                                    struct rx_ring *rx_ring,
1964                                    struct ib_mac_iocb_rsp *ib_mac_rsp,
1965                                    u16 vlan_id)
1966 {
1967         struct net_device *ndev = qdev->ndev;
1968         struct sk_buff *skb = NULL;
1969
1970         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1971
1972         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1973         if (unlikely(!skb)) {
1974                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1975                              "No skb available, drop packet.\n");
1976                 rx_ring->rx_dropped++;
1977                 return;
1978         }
1979
1980         /* Frame error, so drop the packet. */
1981         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1982                 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1983                 dev_kfree_skb_any(skb);
1984                 return;
1985         }
1986
1987         /* The max framesize filter on this chip is set higher than
1988          * MTU since FCoE uses 2k frames.
1989          */
1990         if (skb->len > ndev->mtu + ETH_HLEN) {
1991                 dev_kfree_skb_any(skb);
1992                 rx_ring->rx_dropped++;
1993                 return;
1994         }
1995
1996         /* loopback self test for ethtool */
1997         if (test_bit(QL_SELFTEST, &qdev->flags)) {
1998                 ql_check_lb_frame(qdev, skb);
1999                 dev_kfree_skb_any(skb);
2000                 return;
2001         }
2002
2003         prefetch(skb->data);
2004         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
2005                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "%s Multicast.\n",
2006                              (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2007                              IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
2008                              (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2009                              IB_MAC_IOCB_RSP_M_REG ? "Registered" :
2010                              (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2011                              IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
2012                 rx_ring->rx_multicast++;
2013         }
2014         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
2015                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2016                              "Promiscuous Packet.\n");
2017         }
2018
2019         skb->protocol = eth_type_trans(skb, ndev);
2020         skb_checksum_none_assert(skb);
2021
2022         /* If rx checksum is on, and there are no
2023          * csum or frame errors.
2024          */
2025         if ((ndev->features & NETIF_F_RXCSUM) &&
2026                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
2027                 /* TCP frame. */
2028                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
2029                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2030                                      "TCP checksum done!\n");
2031                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2032                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
2033                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
2034                 /* Unfragmented ipv4 UDP frame. */
2035                         struct iphdr *iph = (struct iphdr *) skb->data;
2036                         if (!(iph->frag_off &
2037                                 htons(IP_MF|IP_OFFSET))) {
2038                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2039                                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2040                                              "TCP checksum done!\n");
2041                         }
2042                 }
2043         }
2044
2045         rx_ring->rx_packets++;
2046         rx_ring->rx_bytes += skb->len;
2047         skb_record_rx_queue(skb, rx_ring->cq_id);
2048         if (vlan_id != 0xffff)
2049                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
2050         if (skb->ip_summed == CHECKSUM_UNNECESSARY)
2051                 napi_gro_receive(&rx_ring->napi, skb);
2052         else
2053                 netif_receive_skb(skb);
2054 }
2055
2056 /* Process an inbound completion from an rx ring. */
2057 static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev,
2058                                         struct rx_ring *rx_ring,
2059                                         struct ib_mac_iocb_rsp *ib_mac_rsp)
2060 {
2061         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
2062         u16 vlan_id = ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
2063                         (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)) ?
2064                         ((le16_to_cpu(ib_mac_rsp->vlan_id) &
2065                         IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff;
2066
2067         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
2068
2069         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
2070                 /* The data and headers are split into
2071                  * separate buffers.
2072                  */
2073                 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2074                                                 vlan_id);
2075         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
2076                 /* The data fit in a single small buffer.
2077                  * Allocate a new skb, copy the data and
2078                  * return the buffer to the free pool.
2079                  */
2080                 ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp,
2081                                                 length, vlan_id);
2082         } else if ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) &&
2083                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) &&
2084                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) {
2085                 /* TCP packet in a page chunk that's been checksummed.
2086                  * Tack it on to our GRO skb and let it go.
2087                  */
2088                 ql_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp,
2089                                                 length, vlan_id);
2090         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
2091                 /* Non-TCP packet in a page chunk. Allocate an
2092                  * skb, tack it on frags, and send it up.
2093                  */
2094                 ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp,
2095                                                 length, vlan_id);
2096         } else {
2097                 /* Non-TCP/UDP large frames that span multiple buffers
2098                  * can be processed corrrectly by the split frame logic.
2099                  */
2100                 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2101                                                 vlan_id);
2102         }
2103
2104         return (unsigned long)length;
2105 }
2106
2107 /* Process an outbound completion from an rx ring. */
2108 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
2109                                    struct ob_mac_iocb_rsp *mac_rsp)
2110 {
2111         struct tx_ring *tx_ring;
2112         struct tx_ring_desc *tx_ring_desc;
2113
2114         QL_DUMP_OB_MAC_RSP(mac_rsp);
2115         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
2116         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
2117         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
2118         tx_ring->tx_bytes += (tx_ring_desc->skb)->len;
2119         tx_ring->tx_packets++;
2120         dev_kfree_skb(tx_ring_desc->skb);
2121         tx_ring_desc->skb = NULL;
2122
2123         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
2124                                         OB_MAC_IOCB_RSP_S |
2125                                         OB_MAC_IOCB_RSP_L |
2126                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
2127                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
2128                         netif_warn(qdev, tx_done, qdev->ndev,
2129                                    "Total descriptor length did not match transfer length.\n");
2130                 }
2131                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
2132                         netif_warn(qdev, tx_done, qdev->ndev,
2133                                    "Frame too short to be valid, not sent.\n");
2134                 }
2135                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
2136                         netif_warn(qdev, tx_done, qdev->ndev,
2137                                    "Frame too long, but sent anyway.\n");
2138                 }
2139                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
2140                         netif_warn(qdev, tx_done, qdev->ndev,
2141                                    "PCI backplane error. Frame not sent.\n");
2142                 }
2143         }
2144         atomic_inc(&tx_ring->tx_count);
2145 }
2146
2147 /* Fire up a handler to reset the MPI processor. */
2148 void ql_queue_fw_error(struct ql_adapter *qdev)
2149 {
2150         ql_link_off(qdev);
2151         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
2152 }
2153
2154 void ql_queue_asic_error(struct ql_adapter *qdev)
2155 {
2156         ql_link_off(qdev);
2157         ql_disable_interrupts(qdev);
2158         /* Clear adapter up bit to signal the recovery
2159          * process that it shouldn't kill the reset worker
2160          * thread
2161          */
2162         clear_bit(QL_ADAPTER_UP, &qdev->flags);
2163         /* Set asic recovery bit to indicate reset process that we are
2164          * in fatal error recovery process rather than normal close
2165          */
2166         set_bit(QL_ASIC_RECOVERY, &qdev->flags);
2167         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
2168 }
2169
2170 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
2171                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
2172 {
2173         switch (ib_ae_rsp->event) {
2174         case MGMT_ERR_EVENT:
2175                 netif_err(qdev, rx_err, qdev->ndev,
2176                           "Management Processor Fatal Error.\n");
2177                 ql_queue_fw_error(qdev);
2178                 return;
2179
2180         case CAM_LOOKUP_ERR_EVENT:
2181                 netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n");
2182                 netdev_err(qdev->ndev, "This event shouldn't occur.\n");
2183                 ql_queue_asic_error(qdev);
2184                 return;
2185
2186         case SOFT_ECC_ERROR_EVENT:
2187                 netdev_err(qdev->ndev, "Soft ECC error detected.\n");
2188                 ql_queue_asic_error(qdev);
2189                 break;
2190
2191         case PCI_ERR_ANON_BUF_RD:
2192                 netdev_err(qdev->ndev, "PCI error occurred when reading "
2193                                         "anonymous buffers from rx_ring %d.\n",
2194                                         ib_ae_rsp->q_id);
2195                 ql_queue_asic_error(qdev);
2196                 break;
2197
2198         default:
2199                 netif_err(qdev, drv, qdev->ndev, "Unexpected event %d.\n",
2200                           ib_ae_rsp->event);
2201                 ql_queue_asic_error(qdev);
2202                 break;
2203         }
2204 }
2205
2206 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
2207 {
2208         struct ql_adapter *qdev = rx_ring->qdev;
2209         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2210         struct ob_mac_iocb_rsp *net_rsp = NULL;
2211         int count = 0;
2212
2213         struct tx_ring *tx_ring;
2214         /* While there are entries in the completion queue. */
2215         while (prod != rx_ring->cnsmr_idx) {
2216
2217                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2218                              "cq_id = %d, prod = %d, cnsmr = %d.\n.",
2219                              rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2220
2221                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
2222                 rmb();
2223                 switch (net_rsp->opcode) {
2224
2225                 case OPCODE_OB_MAC_TSO_IOCB:
2226                 case OPCODE_OB_MAC_IOCB:
2227                         ql_process_mac_tx_intr(qdev, net_rsp);
2228                         break;
2229                 default:
2230                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2231                                      "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2232                                      net_rsp->opcode);
2233                 }
2234                 count++;
2235                 ql_update_cq(rx_ring);
2236                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2237         }
2238         if (!net_rsp)
2239                 return 0;
2240         ql_write_cq_idx(rx_ring);
2241         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
2242         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id)) {
2243                 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2244                         /*
2245                          * The queue got stopped because the tx_ring was full.
2246                          * Wake it up, because it's now at least 25% empty.
2247                          */
2248                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2249         }
2250
2251         return count;
2252 }
2253
2254 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
2255 {
2256         struct ql_adapter *qdev = rx_ring->qdev;
2257         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2258         struct ql_net_rsp_iocb *net_rsp;
2259         int count = 0;
2260
2261         /* While there are entries in the completion queue. */
2262         while (prod != rx_ring->cnsmr_idx) {
2263
2264                 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2265                              "cq_id = %d, prod = %d, cnsmr = %d.\n.",
2266                              rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2267
2268                 net_rsp = rx_ring->curr_entry;
2269                 rmb();
2270                 switch (net_rsp->opcode) {
2271                 case OPCODE_IB_MAC_IOCB:
2272                         ql_process_mac_rx_intr(qdev, rx_ring,
2273                                                (struct ib_mac_iocb_rsp *)
2274                                                net_rsp);
2275                         break;
2276
2277                 case OPCODE_IB_AE_IOCB:
2278                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
2279                                                 net_rsp);
2280                         break;
2281                 default:
2282                         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2283                                      "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2284                                      net_rsp->opcode);
2285                         break;
2286                 }
2287                 count++;
2288                 ql_update_cq(rx_ring);
2289                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2290                 if (count == budget)
2291                         break;
2292         }
2293         ql_update_buffer_queues(qdev, rx_ring);
2294         ql_write_cq_idx(rx_ring);
2295         return count;
2296 }
2297
2298 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
2299 {
2300         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
2301         struct ql_adapter *qdev = rx_ring->qdev;
2302         struct rx_ring *trx_ring;
2303         int i, work_done = 0;
2304         struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id];
2305
2306         netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2307                      "Enter, NAPI POLL cq_id = %d.\n", rx_ring->cq_id);
2308
2309         /* Service the TX rings first.  They start
2310          * right after the RSS rings. */
2311         for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) {
2312                 trx_ring = &qdev->rx_ring[i];
2313                 /* If this TX completion ring belongs to this vector and
2314                  * it's not empty then service it.
2315                  */
2316                 if ((ctx->irq_mask & (1 << trx_ring->cq_id)) &&
2317                         (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) !=
2318                                         trx_ring->cnsmr_idx)) {
2319                         netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2320                                      "%s: Servicing TX completion ring %d.\n",
2321                                      __func__, trx_ring->cq_id);
2322                         ql_clean_outbound_rx_ring(trx_ring);
2323                 }
2324         }
2325
2326         /*
2327          * Now service the RSS ring if it's active.
2328          */
2329         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
2330                                         rx_ring->cnsmr_idx) {
2331                 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2332                              "%s: Servicing RX completion ring %d.\n",
2333                              __func__, rx_ring->cq_id);
2334                 work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
2335         }
2336
2337         if (work_done < budget) {
2338                 napi_complete(napi);
2339                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
2340         }
2341         return work_done;
2342 }
2343
2344 static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features)
2345 {
2346         struct ql_adapter *qdev = netdev_priv(ndev);
2347
2348         if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2349                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
2350                                  NIC_RCV_CFG_VLAN_MATCH_AND_NON);
2351         } else {
2352                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
2353         }
2354 }
2355
2356 /**
2357  * qlge_update_hw_vlan_features - helper routine to reinitialize the adapter
2358  * based on the features to enable/disable hardware vlan accel
2359  */
2360 static int qlge_update_hw_vlan_features(struct net_device *ndev,
2361                                         netdev_features_t features)
2362 {
2363         struct ql_adapter *qdev = netdev_priv(ndev);
2364         int status = 0;
2365         bool need_restart = netif_running(ndev);
2366
2367         if (need_restart) {
2368                 status = ql_adapter_down(qdev);
2369                 if (status) {
2370                         netif_err(qdev, link, qdev->ndev,
2371                                   "Failed to bring down the adapter\n");
2372                         return status;
2373                 }
2374         }
2375
2376         /* update the features with resent change */
2377         ndev->features = features;
2378
2379         if (need_restart) {
2380                 status = ql_adapter_up(qdev);
2381                 if (status) {
2382                         netif_err(qdev, link, qdev->ndev,
2383                                   "Failed to bring up the adapter\n");
2384                         return status;
2385                 }
2386         }
2387
2388         return status;
2389 }
2390
2391 static int qlge_set_features(struct net_device *ndev,
2392         netdev_features_t features)
2393 {
2394         netdev_features_t changed = ndev->features ^ features;
2395         int err;
2396
2397         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2398                 /* Update the behavior of vlan accel in the adapter */
2399                 err = qlge_update_hw_vlan_features(ndev, features);
2400                 if (err)
2401                         return err;
2402
2403                 qlge_vlan_mode(ndev, features);
2404         }
2405
2406         return 0;
2407 }
2408
2409 static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid)
2410 {
2411         u32 enable_bit = MAC_ADDR_E;
2412         int err;
2413
2414         err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2415                                   MAC_ADDR_TYPE_VLAN, vid);
2416         if (err)
2417                 netif_err(qdev, ifup, qdev->ndev,
2418                           "Failed to init vlan address.\n");
2419         return err;
2420 }
2421
2422 static int qlge_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
2423 {
2424         struct ql_adapter *qdev = netdev_priv(ndev);
2425         int status;
2426         int err;
2427
2428         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2429         if (status)
2430                 return status;
2431
2432         err = __qlge_vlan_rx_add_vid(qdev, vid);
2433         set_bit(vid, qdev->active_vlans);
2434
2435         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2436
2437         return err;
2438 }
2439
2440 static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid)
2441 {
2442         u32 enable_bit = 0;
2443         int err;
2444
2445         err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2446                                   MAC_ADDR_TYPE_VLAN, vid);
2447         if (err)
2448                 netif_err(qdev, ifup, qdev->ndev,
2449                           "Failed to clear vlan address.\n");
2450         return err;
2451 }
2452
2453 static int qlge_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
2454 {
2455         struct ql_adapter *qdev = netdev_priv(ndev);
2456         int status;
2457         int err;
2458
2459         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2460         if (status)
2461                 return status;
2462
2463         err = __qlge_vlan_rx_kill_vid(qdev, vid);
2464         clear_bit(vid, qdev->active_vlans);
2465
2466         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2467
2468         return err;
2469 }
2470
2471 static void qlge_restore_vlan(struct ql_adapter *qdev)
2472 {
2473         int status;
2474         u16 vid;
2475
2476         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2477         if (status)
2478                 return;
2479
2480         for_each_set_bit(vid, qdev->active_vlans, VLAN_N_VID)
2481                 __qlge_vlan_rx_add_vid(qdev, vid);
2482
2483         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2484 }
2485
2486 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
2487 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
2488 {
2489         struct rx_ring *rx_ring = dev_id;
2490         napi_schedule(&rx_ring->napi);
2491         return IRQ_HANDLED;
2492 }
2493
2494 /* This handles a fatal error, MPI activity, and the default
2495  * rx_ring in an MSI-X multiple vector environment.
2496  * In MSI/Legacy environment it also process the rest of
2497  * the rx_rings.
2498  */
2499 static irqreturn_t qlge_isr(int irq, void *dev_id)
2500 {
2501         struct rx_ring *rx_ring = dev_id;
2502         struct ql_adapter *qdev = rx_ring->qdev;
2503         struct intr_context *intr_context = &qdev->intr_context[0];
2504         u32 var;
2505         int work_done = 0;
2506
2507         spin_lock(&qdev->hw_lock);
2508         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
2509                 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2510                              "Shared Interrupt, Not ours!\n");
2511                 spin_unlock(&qdev->hw_lock);
2512                 return IRQ_NONE;
2513         }
2514         spin_unlock(&qdev->hw_lock);
2515
2516         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
2517
2518         /*
2519          * Check for fatal error.
2520          */
2521         if (var & STS_FE) {
2522                 ql_queue_asic_error(qdev);
2523                 netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var);
2524                 var = ql_read32(qdev, ERR_STS);
2525                 netdev_err(qdev->ndev, "Resetting chip. "
2526                                         "Error Status Register = 0x%x\n", var);
2527                 return IRQ_HANDLED;
2528         }
2529
2530         /*
2531          * Check MPI processor activity.
2532          */
2533         if ((var & STS_PI) &&
2534                 (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) {
2535                 /*
2536                  * We've got an async event or mailbox completion.
2537                  * Handle it and clear the source of the interrupt.
2538                  */
2539                 netif_err(qdev, intr, qdev->ndev,
2540                           "Got MPI processor interrupt.\n");
2541                 ql_disable_completion_interrupt(qdev, intr_context->intr);
2542                 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
2543                 queue_delayed_work_on(smp_processor_id(),
2544                                 qdev->workqueue, &qdev->mpi_work, 0);
2545                 work_done++;
2546         }
2547
2548         /*
2549          * Get the bit-mask that shows the active queues for this
2550          * pass.  Compare it to the queues that this irq services
2551          * and call napi if there's a match.
2552          */
2553         var = ql_read32(qdev, ISR1);
2554         if (var & intr_context->irq_mask) {
2555                 netif_info(qdev, intr, qdev->ndev,
2556                            "Waking handler for rx_ring[0].\n");
2557                 ql_disable_completion_interrupt(qdev, intr_context->intr);
2558                 napi_schedule(&rx_ring->napi);
2559                 work_done++;
2560         }
2561         ql_enable_completion_interrupt(qdev, intr_context->intr);
2562         return work_done ? IRQ_HANDLED : IRQ_NONE;
2563 }
2564
2565 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2566 {
2567
2568         if (skb_is_gso(skb)) {
2569                 int err;
2570                 __be16 l3_proto = vlan_get_protocol(skb);
2571
2572                 err = skb_cow_head(skb, 0);
2573                 if (err < 0)
2574                         return err;
2575
2576                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2577                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2578                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2579                 mac_iocb_ptr->total_hdrs_len =
2580                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2581                 mac_iocb_ptr->net_trans_offset =
2582                     cpu_to_le16(skb_network_offset(skb) |
2583                                 skb_transport_offset(skb)
2584                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
2585                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2586                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2587                 if (likely(l3_proto == htons(ETH_P_IP))) {
2588                         struct iphdr *iph = ip_hdr(skb);
2589                         iph->check = 0;
2590                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2591                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2592                                                                  iph->daddr, 0,
2593                                                                  IPPROTO_TCP,
2594                                                                  0);
2595                 } else if (l3_proto == htons(ETH_P_IPV6)) {
2596                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2597                         tcp_hdr(skb)->check =
2598                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2599                                              &ipv6_hdr(skb)->daddr,
2600                                              0, IPPROTO_TCP, 0);
2601                 }
2602                 return 1;
2603         }
2604         return 0;
2605 }
2606
2607 static void ql_hw_csum_setup(struct sk_buff *skb,
2608                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2609 {
2610         int len;
2611         struct iphdr *iph = ip_hdr(skb);
2612         __sum16 *check;
2613         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2614         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2615         mac_iocb_ptr->net_trans_offset =
2616                 cpu_to_le16(skb_network_offset(skb) |
2617                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2618
2619         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2620         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2621         if (likely(iph->protocol == IPPROTO_TCP)) {
2622                 check = &(tcp_hdr(skb)->check);
2623                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2624                 mac_iocb_ptr->total_hdrs_len =
2625                     cpu_to_le16(skb_transport_offset(skb) +
2626                                 (tcp_hdr(skb)->doff << 2));
2627         } else {
2628                 check = &(udp_hdr(skb)->check);
2629                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2630                 mac_iocb_ptr->total_hdrs_len =
2631                     cpu_to_le16(skb_transport_offset(skb) +
2632                                 sizeof(struct udphdr));
2633         }
2634         *check = ~csum_tcpudp_magic(iph->saddr,
2635                                     iph->daddr, len, iph->protocol, 0);
2636 }
2637
2638 static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
2639 {
2640         struct tx_ring_desc *tx_ring_desc;
2641         struct ob_mac_iocb_req *mac_iocb_ptr;
2642         struct ql_adapter *qdev = netdev_priv(ndev);
2643         int tso;
2644         struct tx_ring *tx_ring;
2645         u32 tx_ring_idx = (u32) skb->queue_mapping;
2646
2647         tx_ring = &qdev->tx_ring[tx_ring_idx];
2648
2649         if (skb_padto(skb, ETH_ZLEN))
2650                 return NETDEV_TX_OK;
2651
2652         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2653                 netif_info(qdev, tx_queued, qdev->ndev,
2654                            "%s: BUG! shutting down tx queue %d due to lack of resources.\n",
2655                            __func__, tx_ring_idx);
2656                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2657                 tx_ring->tx_errors++;
2658                 return NETDEV_TX_BUSY;
2659         }
2660         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2661         mac_iocb_ptr = tx_ring_desc->queue_entry;
2662         memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
2663
2664         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2665         mac_iocb_ptr->tid = tx_ring_desc->index;
2666         /* We use the upper 32-bits to store the tx queue for this IO.
2667          * When we get the completion we can use it to establish the context.
2668          */
2669         mac_iocb_ptr->txq_idx = tx_ring_idx;
2670         tx_ring_desc->skb = skb;
2671
2672         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2673
2674         if (skb_vlan_tag_present(skb)) {
2675                 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2676                              "Adding a vlan tag %d.\n", skb_vlan_tag_get(skb));
2677                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2678                 mac_iocb_ptr->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
2679         }
2680         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2681         if (tso < 0) {
2682                 dev_kfree_skb_any(skb);
2683                 return NETDEV_TX_OK;
2684         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2685                 ql_hw_csum_setup(skb,
2686                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2687         }
2688         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2689                         NETDEV_TX_OK) {
2690                 netif_err(qdev, tx_queued, qdev->ndev,
2691                           "Could not map the segments.\n");
2692                 tx_ring->tx_errors++;
2693                 return NETDEV_TX_BUSY;
2694         }
2695         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2696         tx_ring->prod_idx++;
2697         if (tx_ring->prod_idx == tx_ring->wq_len)
2698                 tx_ring->prod_idx = 0;
2699         wmb();
2700
2701         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2702         netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2703                      "tx queued, slot %d, len %d\n",
2704                      tx_ring->prod_idx, skb->len);
2705
2706         atomic_dec(&tx_ring->tx_count);
2707
2708         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2709                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2710                 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2711                         /*
2712                          * The queue got stopped because the tx_ring was full.
2713                          * Wake it up, because it's now at least 25% empty.
2714                          */
2715                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2716         }
2717         return NETDEV_TX_OK;
2718 }
2719
2720
2721 static void ql_free_shadow_space(struct ql_adapter *qdev)
2722 {
2723         if (qdev->rx_ring_shadow_reg_area) {
2724                 pci_free_consistent(qdev->pdev,
2725                                     PAGE_SIZE,
2726                                     qdev->rx_ring_shadow_reg_area,
2727                                     qdev->rx_ring_shadow_reg_dma);
2728                 qdev->rx_ring_shadow_reg_area = NULL;
2729         }
2730         if (qdev->tx_ring_shadow_reg_area) {
2731                 pci_free_consistent(qdev->pdev,
2732                                     PAGE_SIZE,
2733                                     qdev->tx_ring_shadow_reg_area,
2734                                     qdev->tx_ring_shadow_reg_dma);
2735                 qdev->tx_ring_shadow_reg_area = NULL;
2736         }
2737 }
2738
2739 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2740 {
2741         qdev->rx_ring_shadow_reg_area =
2742                 pci_zalloc_consistent(qdev->pdev, PAGE_SIZE,
2743                                       &qdev->rx_ring_shadow_reg_dma);
2744         if (qdev->rx_ring_shadow_reg_area == NULL) {
2745                 netif_err(qdev, ifup, qdev->ndev,
2746                           "Allocation of RX shadow space failed.\n");
2747                 return -ENOMEM;
2748         }
2749
2750         qdev->tx_ring_shadow_reg_area =
2751                 pci_zalloc_consistent(qdev->pdev, PAGE_SIZE,
2752                                       &qdev->tx_ring_shadow_reg_dma);
2753         if (qdev->tx_ring_shadow_reg_area == NULL) {
2754                 netif_err(qdev, ifup, qdev->ndev,
2755                           "Allocation of TX shadow space failed.\n");
2756                 goto err_wqp_sh_area;
2757         }
2758         return 0;
2759
2760 err_wqp_sh_area:
2761         pci_free_consistent(qdev->pdev,
2762                             PAGE_SIZE,
2763                             qdev->rx_ring_shadow_reg_area,
2764                             qdev->rx_ring_shadow_reg_dma);
2765         return -ENOMEM;
2766 }
2767
2768 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2769 {
2770         struct tx_ring_desc *tx_ring_desc;
2771         int i;
2772         struct ob_mac_iocb_req *mac_iocb_ptr;
2773
2774         mac_iocb_ptr = tx_ring->wq_base;
2775         tx_ring_desc = tx_ring->q;
2776         for (i = 0; i < tx_ring->wq_len; i++) {
2777                 tx_ring_desc->index = i;
2778                 tx_ring_desc->skb = NULL;
2779                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2780                 mac_iocb_ptr++;
2781                 tx_ring_desc++;
2782         }
2783         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2784 }
2785
2786 static void ql_free_tx_resources(struct ql_adapter *qdev,
2787                                  struct tx_ring *tx_ring)
2788 {
2789         if (tx_ring->wq_base) {
2790                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2791                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2792                 tx_ring->wq_base = NULL;
2793         }
2794         kfree(tx_ring->q);
2795         tx_ring->q = NULL;
2796 }
2797
2798 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2799                                  struct tx_ring *tx_ring)
2800 {
2801         tx_ring->wq_base =
2802             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2803                                  &tx_ring->wq_base_dma);
2804
2805         if ((tx_ring->wq_base == NULL) ||
2806             tx_ring->wq_base_dma & WQ_ADDR_ALIGN)
2807                 goto pci_alloc_err;
2808
2809         tx_ring->q =
2810             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2811         if (tx_ring->q == NULL)
2812                 goto err;
2813
2814         return 0;
2815 err:
2816         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2817                             tx_ring->wq_base, tx_ring->wq_base_dma);
2818         tx_ring->wq_base = NULL;
2819 pci_alloc_err:
2820         netif_err(qdev, ifup, qdev->ndev, "tx_ring alloc failed.\n");
2821         return -ENOMEM;
2822 }
2823
2824 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2825 {
2826         struct bq_desc *lbq_desc;
2827
2828         uint32_t  curr_idx, clean_idx;
2829
2830         curr_idx = rx_ring->lbq_curr_idx;
2831         clean_idx = rx_ring->lbq_clean_idx;
2832         while (curr_idx != clean_idx) {
2833                 lbq_desc = &rx_ring->lbq[curr_idx];
2834
2835                 if (lbq_desc->p.pg_chunk.last_flag) {
2836                         pci_unmap_page(qdev->pdev,
2837                                 lbq_desc->p.pg_chunk.map,
2838                                 ql_lbq_block_size(qdev),
2839                                        PCI_DMA_FROMDEVICE);
2840                         lbq_desc->p.pg_chunk.last_flag = 0;
2841                 }
2842
2843                 put_page(lbq_desc->p.pg_chunk.page);
2844                 lbq_desc->p.pg_chunk.page = NULL;
2845
2846                 if (++curr_idx == rx_ring->lbq_len)
2847                         curr_idx = 0;
2848
2849         }
2850         if (rx_ring->pg_chunk.page) {
2851                 pci_unmap_page(qdev->pdev, rx_ring->pg_chunk.map,
2852                         ql_lbq_block_size(qdev), PCI_DMA_FROMDEVICE);
2853                 put_page(rx_ring->pg_chunk.page);
2854                 rx_ring->pg_chunk.page = NULL;
2855         }
2856 }
2857
2858 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2859 {
2860         int i;
2861         struct bq_desc *sbq_desc;
2862
2863         for (i = 0; i < rx_ring->sbq_len; i++) {
2864                 sbq_desc = &rx_ring->sbq[i];
2865                 if (sbq_desc == NULL) {
2866                         netif_err(qdev, ifup, qdev->ndev,
2867                                   "sbq_desc %d is NULL.\n", i);
2868                         return;
2869                 }
2870                 if (sbq_desc->p.skb) {
2871                         pci_unmap_single(qdev->pdev,
2872                                          dma_unmap_addr(sbq_desc, mapaddr),
2873                                          dma_unmap_len(sbq_desc, maplen),
2874                                          PCI_DMA_FROMDEVICE);
2875                         dev_kfree_skb(sbq_desc->p.skb);
2876                         sbq_desc->p.skb = NULL;
2877                 }
2878         }
2879 }
2880
2881 /* Free all large and small rx buffers associated
2882  * with the completion queues for this device.
2883  */
2884 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2885 {
2886         int i;
2887         struct rx_ring *rx_ring;
2888
2889         for (i = 0; i < qdev->rx_ring_count; i++) {
2890                 rx_ring = &qdev->rx_ring[i];
2891                 if (rx_ring->lbq)
2892                         ql_free_lbq_buffers(qdev, rx_ring);
2893                 if (rx_ring->sbq)
2894                         ql_free_sbq_buffers(qdev, rx_ring);
2895         }
2896 }
2897
2898 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2899 {
2900         struct rx_ring *rx_ring;
2901         int i;
2902
2903         for (i = 0; i < qdev->rx_ring_count; i++) {
2904                 rx_ring = &qdev->rx_ring[i];
2905                 if (rx_ring->type != TX_Q)
2906                         ql_update_buffer_queues(qdev, rx_ring);
2907         }
2908 }
2909
2910 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2911                                 struct rx_ring *rx_ring)
2912 {
2913         int i;
2914         struct bq_desc *lbq_desc;
2915         __le64 *bq = rx_ring->lbq_base;
2916
2917         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2918         for (i = 0; i < rx_ring->lbq_len; i++) {
2919                 lbq_desc = &rx_ring->lbq[i];
2920                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2921                 lbq_desc->index = i;
2922                 lbq_desc->addr = bq;
2923                 bq++;
2924         }
2925 }
2926
2927 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2928                                 struct rx_ring *rx_ring)
2929 {
2930         int i;
2931         struct bq_desc *sbq_desc;
2932         __le64 *bq = rx_ring->sbq_base;
2933
2934         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2935         for (i = 0; i < rx_ring->sbq_len; i++) {
2936                 sbq_desc = &rx_ring->sbq[i];
2937                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2938                 sbq_desc->index = i;
2939                 sbq_desc->addr = bq;
2940                 bq++;
2941         }
2942 }
2943
2944 static void ql_free_rx_resources(struct ql_adapter *qdev,
2945                                  struct rx_ring *rx_ring)
2946 {
2947         /* Free the small buffer queue. */
2948         if (rx_ring->sbq_base) {
2949                 pci_free_consistent(qdev->pdev,
2950                                     rx_ring->sbq_size,
2951                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2952                 rx_ring->sbq_base = NULL;
2953         }
2954
2955         /* Free the small buffer queue control blocks. */
2956         kfree(rx_ring->sbq);
2957         rx_ring->sbq = NULL;
2958
2959         /* Free the large buffer queue. */
2960         if (rx_ring->lbq_base) {
2961                 pci_free_consistent(qdev->pdev,
2962                                     rx_ring->lbq_size,
2963                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2964                 rx_ring->lbq_base = NULL;
2965         }
2966
2967         /* Free the large buffer queue control blocks. */
2968         kfree(rx_ring->lbq);
2969         rx_ring->lbq = NULL;
2970
2971         /* Free the rx queue. */
2972         if (rx_ring->cq_base) {
2973                 pci_free_consistent(qdev->pdev,
2974                                     rx_ring->cq_size,
2975                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2976                 rx_ring->cq_base = NULL;
2977         }
2978 }
2979
2980 /* Allocate queues and buffers for this completions queue based
2981  * on the values in the parameter structure. */
2982 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2983                                  struct rx_ring *rx_ring)
2984 {
2985
2986         /*
2987          * Allocate the completion queue for this rx_ring.
2988          */
2989         rx_ring->cq_base =
2990             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2991                                  &rx_ring->cq_base_dma);
2992
2993         if (rx_ring->cq_base == NULL) {
2994                 netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n");
2995                 return -ENOMEM;
2996         }
2997
2998         if (rx_ring->sbq_len) {
2999                 /*
3000                  * Allocate small buffer queue.
3001                  */
3002                 rx_ring->sbq_base =
3003                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
3004                                          &rx_ring->sbq_base_dma);
3005
3006                 if (rx_ring->sbq_base == NULL) {
3007                         netif_err(qdev, ifup, qdev->ndev,
3008                                   "Small buffer queue allocation failed.\n");
3009                         goto err_mem;
3010                 }
3011
3012                 /*
3013                  * Allocate small buffer queue control blocks.
3014                  */
3015                 rx_ring->sbq = kmalloc_array(rx_ring->sbq_len,
3016                                              sizeof(struct bq_desc),
3017                                              GFP_KERNEL);
3018                 if (rx_ring->sbq == NULL)
3019                         goto err_mem;
3020
3021                 ql_init_sbq_ring(qdev, rx_ring);
3022         }
3023
3024         if (rx_ring->lbq_len) {
3025                 /*
3026                  * Allocate large buffer queue.
3027                  */
3028                 rx_ring->lbq_base =
3029                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
3030                                          &rx_ring->lbq_base_dma);
3031
3032                 if (rx_ring->lbq_base == NULL) {
3033                         netif_err(qdev, ifup, qdev->ndev,
3034                                   "Large buffer queue allocation failed.\n");
3035                         goto err_mem;
3036                 }
3037                 /*
3038                  * Allocate large buffer queue control blocks.
3039                  */
3040                 rx_ring->lbq = kmalloc_array(rx_ring->lbq_len,
3041                                              sizeof(struct bq_desc),
3042                                              GFP_KERNEL);
3043                 if (rx_ring->lbq == NULL)
3044                         goto err_mem;
3045
3046                 ql_init_lbq_ring(qdev, rx_ring);
3047         }
3048
3049         return 0;
3050
3051 err_mem:
3052         ql_free_rx_resources(qdev, rx_ring);
3053         return -ENOMEM;
3054 }
3055
3056 static void ql_tx_ring_clean(struct ql_adapter *qdev)
3057 {
3058         struct tx_ring *tx_ring;
3059         struct tx_ring_desc *tx_ring_desc;
3060         int i, j;
3061
3062         /*
3063          * Loop through all queues and free
3064          * any resources.
3065          */
3066         for (j = 0; j < qdev->tx_ring_count; j++) {
3067                 tx_ring = &qdev->tx_ring[j];
3068                 for (i = 0; i < tx_ring->wq_len; i++) {
3069                         tx_ring_desc = &tx_ring->q[i];
3070                         if (tx_ring_desc && tx_ring_desc->skb) {
3071                                 netif_err(qdev, ifdown, qdev->ndev,
3072                                           "Freeing lost SKB %p, from queue %d, index %d.\n",
3073                                           tx_ring_desc->skb, j,
3074                                           tx_ring_desc->index);
3075                                 ql_unmap_send(qdev, tx_ring_desc,
3076                                               tx_ring_desc->map_cnt);
3077                                 dev_kfree_skb(tx_ring_desc->skb);
3078                                 tx_ring_desc->skb = NULL;
3079                         }
3080                 }
3081         }
3082 }
3083
3084 static void ql_free_mem_resources(struct ql_adapter *qdev)
3085 {
3086         int i;
3087
3088         for (i = 0; i < qdev->tx_ring_count; i++)
3089                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
3090         for (i = 0; i < qdev->rx_ring_count; i++)
3091                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
3092         ql_free_shadow_space(qdev);
3093 }
3094
3095 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
3096 {
3097         int i;
3098
3099         /* Allocate space for our shadow registers and such. */
3100         if (ql_alloc_shadow_space(qdev))
3101                 return -ENOMEM;
3102
3103         for (i = 0; i < qdev->rx_ring_count; i++) {
3104                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
3105                         netif_err(qdev, ifup, qdev->ndev,
3106                                   "RX resource allocation failed.\n");
3107                         goto err_mem;
3108                 }
3109         }
3110         /* Allocate tx queue resources */
3111         for (i = 0; i < qdev->tx_ring_count; i++) {
3112                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
3113                         netif_err(qdev, ifup, qdev->ndev,
3114                                   "TX resource allocation failed.\n");
3115                         goto err_mem;
3116                 }
3117         }
3118         return 0;
3119
3120 err_mem:
3121         ql_free_mem_resources(qdev);
3122         return -ENOMEM;
3123 }
3124
3125 /* Set up the rx ring control block and pass it to the chip.
3126  * The control block is defined as
3127  * "Completion Queue Initialization Control Block", or cqicb.
3128  */
3129 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
3130 {
3131         struct cqicb *cqicb = &rx_ring->cqicb;
3132         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
3133                 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3134         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
3135                 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3136         void __iomem *doorbell_area =
3137             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
3138         int err = 0;
3139         u16 bq_len;
3140         u64 tmp;
3141         __le64 *base_indirect_ptr;
3142         int page_entries;
3143
3144         /* Set up the shadow registers for this ring. */
3145         rx_ring->prod_idx_sh_reg = shadow_reg;
3146         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
3147         *rx_ring->prod_idx_sh_reg = 0;
3148         shadow_reg += sizeof(u64);
3149         shadow_reg_dma += sizeof(u64);
3150         rx_ring->lbq_base_indirect = shadow_reg;
3151         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
3152         shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3153         shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3154         rx_ring->sbq_base_indirect = shadow_reg;
3155         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
3156
3157         /* PCI doorbell mem area + 0x00 for consumer index register */
3158         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
3159         rx_ring->cnsmr_idx = 0;
3160         rx_ring->curr_entry = rx_ring->cq_base;
3161
3162         /* PCI doorbell mem area + 0x04 for valid register */
3163         rx_ring->valid_db_reg = doorbell_area + 0x04;
3164
3165         /* PCI doorbell mem area + 0x18 for large buffer consumer */
3166         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
3167
3168         /* PCI doorbell mem area + 0x1c */
3169         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
3170
3171         memset((void *)cqicb, 0, sizeof(struct cqicb));
3172         cqicb->msix_vect = rx_ring->irq;
3173
3174         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
3175         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
3176
3177         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
3178
3179         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
3180
3181         /*
3182          * Set up the control block load flags.
3183          */
3184         cqicb->flags = FLAGS_LC |       /* Load queue base address */
3185             FLAGS_LV |          /* Load MSI-X vector */
3186             FLAGS_LI;           /* Load irq delay values */
3187         if (rx_ring->lbq_len) {
3188                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
3189                 tmp = (u64)rx_ring->lbq_base_dma;
3190                 base_indirect_ptr = rx_ring->lbq_base_indirect;
3191                 page_entries = 0;
3192                 do {
3193                         *base_indirect_ptr = cpu_to_le64(tmp);
3194                         tmp += DB_PAGE_SIZE;
3195                         base_indirect_ptr++;
3196                         page_entries++;
3197                 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3198                 cqicb->lbq_addr =
3199                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
3200                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
3201                         (u16) rx_ring->lbq_buf_size;
3202                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
3203                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
3204                         (u16) rx_ring->lbq_len;
3205                 cqicb->lbq_len = cpu_to_le16(bq_len);
3206                 rx_ring->lbq_prod_idx = 0;
3207                 rx_ring->lbq_curr_idx = 0;
3208                 rx_ring->lbq_clean_idx = 0;
3209                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
3210         }
3211         if (rx_ring->sbq_len) {
3212                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
3213                 tmp = (u64)rx_ring->sbq_base_dma;
3214                 base_indirect_ptr = rx_ring->sbq_base_indirect;
3215                 page_entries = 0;
3216                 do {
3217                         *base_indirect_ptr = cpu_to_le64(tmp);
3218                         tmp += DB_PAGE_SIZE;
3219                         base_indirect_ptr++;
3220                         page_entries++;
3221                 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
3222                 cqicb->sbq_addr =
3223                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
3224                 cqicb->sbq_buf_size =
3225                     cpu_to_le16((u16)(rx_ring->sbq_buf_size));
3226                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
3227                         (u16) rx_ring->sbq_len;
3228                 cqicb->sbq_len = cpu_to_le16(bq_len);
3229                 rx_ring->sbq_prod_idx = 0;
3230                 rx_ring->sbq_curr_idx = 0;
3231                 rx_ring->sbq_clean_idx = 0;
3232                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
3233         }
3234         switch (rx_ring->type) {
3235         case TX_Q:
3236                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
3237                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
3238                 break;
3239         case RX_Q:
3240                 /* Inbound completion handling rx_rings run in
3241                  * separate NAPI contexts.
3242                  */
3243                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
3244                                64);
3245                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
3246                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
3247                 break;
3248         default:
3249                 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3250                              "Invalid rx_ring->type = %d.\n", rx_ring->type);
3251         }
3252         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
3253                            CFG_LCQ, rx_ring->cq_id);
3254         if (err) {
3255                 netif_err(qdev, ifup, qdev->ndev, "Failed to load CQICB.\n");
3256                 return err;
3257         }
3258         return err;
3259 }
3260
3261 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
3262 {
3263         struct wqicb *wqicb = (struct wqicb *)tx_ring;
3264         void __iomem *doorbell_area =
3265             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
3266         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
3267             (tx_ring->wq_id * sizeof(u64));
3268         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
3269             (tx_ring->wq_id * sizeof(u64));
3270         int err = 0;
3271
3272         /*
3273          * Assign doorbell registers for this tx_ring.
3274          */
3275         /* TX PCI doorbell mem area for tx producer index */
3276         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
3277         tx_ring->prod_idx = 0;
3278         /* TX PCI doorbell mem area + 0x04 */
3279         tx_ring->valid_db_reg = doorbell_area + 0x04;
3280
3281         /*
3282          * Assign shadow registers for this tx_ring.
3283          */
3284         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
3285         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
3286
3287         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
3288         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
3289                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
3290         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
3291         wqicb->rid = 0;
3292         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
3293
3294         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
3295
3296         ql_init_tx_ring(qdev, tx_ring);
3297
3298         err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
3299                            (u16) tx_ring->wq_id);
3300         if (err) {
3301                 netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n");
3302                 return err;
3303         }
3304         return err;
3305 }
3306
3307 static void ql_disable_msix(struct ql_adapter *qdev)
3308 {
3309         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3310                 pci_disable_msix(qdev->pdev);
3311                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
3312                 kfree(qdev->msi_x_entry);
3313                 qdev->msi_x_entry = NULL;
3314         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3315                 pci_disable_msi(qdev->pdev);
3316                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3317         }
3318 }
3319
3320 /* We start by trying to get the number of vectors
3321  * stored in qdev->intr_count. If we don't get that
3322  * many then we reduce the count and try again.
3323  */
3324 static void ql_enable_msix(struct ql_adapter *qdev)
3325 {
3326         int i, err;
3327
3328         /* Get the MSIX vectors. */
3329         if (qlge_irq_type == MSIX_IRQ) {
3330                 /* Try to alloc space for the msix struct,
3331                  * if it fails then go to MSI/legacy.
3332                  */
3333                 qdev->msi_x_entry = kcalloc(qdev->intr_count,
3334                                             sizeof(struct msix_entry),
3335                                             GFP_KERNEL);
3336                 if (!qdev->msi_x_entry) {
3337                         qlge_irq_type = MSI_IRQ;
3338                         goto msi;
3339                 }
3340
3341                 for (i = 0; i < qdev->intr_count; i++)
3342                         qdev->msi_x_entry[i].entry = i;
3343
3344                 err = pci_enable_msix_range(qdev->pdev, qdev->msi_x_entry,
3345                                             1, qdev->intr_count);
3346                 if (err < 0) {
3347                         kfree(qdev->msi_x_entry);
3348                         qdev->msi_x_entry = NULL;
3349                         netif_warn(qdev, ifup, qdev->ndev,
3350                                    "MSI-X Enable failed, trying MSI.\n");
3351                         qlge_irq_type = MSI_IRQ;
3352                 } else {
3353                         qdev->intr_count = err;
3354                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
3355                         netif_info(qdev, ifup, qdev->ndev,
3356                                    "MSI-X Enabled, got %d vectors.\n",
3357                                    qdev->intr_count);
3358                         return;
3359                 }
3360         }
3361 msi:
3362         qdev->intr_count = 1;
3363         if (qlge_irq_type == MSI_IRQ) {
3364                 if (!pci_enable_msi(qdev->pdev)) {
3365                         set_bit(QL_MSI_ENABLED, &qdev->flags);
3366                         netif_info(qdev, ifup, qdev->ndev,
3367                                    "Running with MSI interrupts.\n");
3368                         return;
3369                 }
3370         }
3371         qlge_irq_type = LEG_IRQ;
3372         netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3373                      "Running with legacy interrupts.\n");
3374 }
3375
3376 /* Each vector services 1 RSS ring and and 1 or more
3377  * TX completion rings.  This function loops through
3378  * the TX completion rings and assigns the vector that
3379  * will service it.  An example would be if there are
3380  * 2 vectors (so 2 RSS rings) and 8 TX completion rings.
3381  * This would mean that vector 0 would service RSS ring 0
3382  * and TX completion rings 0,1,2 and 3.  Vector 1 would
3383  * service RSS ring 1 and TX completion rings 4,5,6 and 7.
3384  */
3385 static void ql_set_tx_vect(struct ql_adapter *qdev)
3386 {
3387         int i, j, vect;
3388         u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3389
3390         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3391                 /* Assign irq vectors to TX rx_rings.*/
3392                 for (vect = 0, j = 0, i = qdev->rss_ring_count;
3393                                          i < qdev->rx_ring_count; i++) {
3394                         if (j == tx_rings_per_vector) {
3395                                 vect++;
3396                                 j = 0;
3397                         }
3398                         qdev->rx_ring[i].irq = vect;
3399                         j++;
3400                 }
3401         } else {
3402                 /* For single vector all rings have an irq
3403                  * of zero.
3404                  */
3405                 for (i = 0; i < qdev->rx_ring_count; i++)
3406                         qdev->rx_ring[i].irq = 0;
3407         }
3408 }
3409
3410 /* Set the interrupt mask for this vector.  Each vector
3411  * will service 1 RSS ring and 1 or more TX completion
3412  * rings.  This function sets up a bit mask per vector
3413  * that indicates which rings it services.
3414  */
3415 static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx)
3416 {
3417         int j, vect = ctx->intr;
3418         u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3419
3420         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3421                 /* Add the RSS ring serviced by this vector
3422                  * to the mask.
3423                  */
3424                 ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id);
3425                 /* Add the TX ring(s) serviced by this vector
3426                  * to the mask. */
3427                 for (j = 0; j < tx_rings_per_vector; j++) {
3428                         ctx->irq_mask |=
3429                         (1 << qdev->rx_ring[qdev->rss_ring_count +
3430                         (vect * tx_rings_per_vector) + j].cq_id);
3431                 }
3432         } else {
3433                 /* For single vector we just shift each queue's
3434                  * ID into the mask.
3435                  */
3436                 for (j = 0; j < qdev->rx_ring_count; j++)
3437                         ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id);
3438         }
3439 }
3440
3441 /*
3442  * Here we build the intr_context structures based on
3443  * our rx_ring count and intr vector count.
3444  * The intr_context structure is used to hook each vector
3445  * to possibly different handlers.
3446  */
3447 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
3448 {
3449         int i = 0;
3450         struct intr_context *intr_context = &qdev->intr_context[0];
3451
3452         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3453                 /* Each rx_ring has it's
3454                  * own intr_context since we have separate
3455                  * vectors for each queue.
3456                  */
3457                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3458                         qdev->rx_ring[i].irq = i;
3459                         intr_context->intr = i;
3460                         intr_context->qdev = qdev;
3461                         /* Set up this vector's bit-mask that indicates
3462                          * which queues it services.
3463                          */
3464                         ql_set_irq_mask(qdev, intr_context);
3465                         /*
3466                          * We set up each vectors enable/disable/read bits so
3467                          * there's no bit/mask calculations in the critical path.
3468                          */
3469                         intr_context->intr_en_mask =
3470                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3471                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
3472                             | i;
3473                         intr_context->intr_dis_mask =
3474                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3475                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
3476                             INTR_EN_IHD | i;
3477                         intr_context->intr_read_mask =
3478                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3479                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
3480                             i;
3481                         if (i == 0) {
3482                                 /* The first vector/queue handles
3483                                  * broadcast/multicast, fatal errors,
3484                                  * and firmware events.  This in addition
3485                                  * to normal inbound NAPI processing.
3486                                  */
3487                                 intr_context->handler = qlge_isr;
3488                                 sprintf(intr_context->name, "%s-rx-%d",
3489                                         qdev->ndev->name, i);
3490                         } else {
3491                                 /*
3492                                  * Inbound queues handle unicast frames only.
3493                                  */
3494                                 intr_context->handler = qlge_msix_rx_isr;
3495                                 sprintf(intr_context->name, "%s-rx-%d",
3496                                         qdev->ndev->name, i);
3497                         }
3498                 }
3499         } else {
3500                 /*
3501                  * All rx_rings use the same intr_context since
3502                  * there is only one vector.
3503                  */
3504                 intr_context->intr = 0;
3505                 intr_context->qdev = qdev;
3506                 /*
3507                  * We set up each vectors enable/disable/read bits so
3508                  * there's no bit/mask calculations in the critical path.
3509                  */
3510                 intr_context->intr_en_mask =
3511                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
3512                 intr_context->intr_dis_mask =
3513                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3514                     INTR_EN_TYPE_DISABLE;
3515                 intr_context->intr_read_mask =
3516                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
3517                 /*
3518                  * Single interrupt means one handler for all rings.
3519                  */
3520                 intr_context->handler = qlge_isr;
3521                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
3522                 /* Set up this vector's bit-mask that indicates
3523                  * which queues it services. In this case there is
3524                  * a single vector so it will service all RSS and
3525                  * TX completion rings.
3526                  */
3527                 ql_set_irq_mask(qdev, intr_context);
3528         }
3529         /* Tell the TX completion rings which MSIx vector
3530          * they will be using.
3531          */
3532         ql_set_tx_vect(qdev);
3533 }
3534
3535 static void ql_free_irq(struct ql_adapter *qdev)
3536 {
3537         int i;
3538         struct intr_context *intr_context = &qdev->intr_context[0];
3539
3540         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3541                 if (intr_context->hooked) {
3542                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3543                                 free_irq(qdev->msi_x_entry[i].vector,
3544                                          &qdev->rx_ring[i]);
3545                         } else {
3546                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
3547                         }
3548                 }
3549         }
3550         ql_disable_msix(qdev);
3551 }
3552
3553 static int ql_request_irq(struct ql_adapter *qdev)
3554 {
3555         int i;
3556         int status = 0;
3557         struct pci_dev *pdev = qdev->pdev;
3558         struct intr_context *intr_context = &qdev->intr_context[0];
3559
3560         ql_resolve_queues_to_irqs(qdev);
3561
3562         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3563                 atomic_set(&intr_context->irq_cnt, 0);
3564                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3565                         status = request_irq(qdev->msi_x_entry[i].vector,
3566                                              intr_context->handler,
3567                                              0,
3568                                              intr_context->name,
3569                                              &qdev->rx_ring[i]);
3570                         if (status) {
3571                                 netif_err(qdev, ifup, qdev->ndev,
3572                                           "Failed request for MSIX interrupt %d.\n",
3573                                           i);
3574                                 goto err_irq;
3575                         }
3576                 } else {
3577                         netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3578                                      "trying msi or legacy interrupts.\n");
3579                         netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3580                                      "%s: irq = %d.\n", __func__, pdev->irq);
3581                         netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3582                                      "%s: context->name = %s.\n", __func__,
3583                                      intr_context->name);
3584                         netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3585                                      "%s: dev_id = 0x%p.\n", __func__,
3586                                      &qdev->rx_ring[0]);
3587                         status =
3588                             request_irq(pdev->irq, qlge_isr,
3589                                         test_bit(QL_MSI_ENABLED,
3590                                                  &qdev->
3591                                                  flags) ? 0 : IRQF_SHARED,
3592                                         intr_context->name, &qdev->rx_ring[0]);
3593                         if (status)
3594                                 goto err_irq;
3595
3596                         netif_err(qdev, ifup, qdev->ndev,
3597                                   "Hooked intr %d, queue type %s, with name %s.\n",
3598                                   i,
3599                                   qdev->rx_ring[0].type == DEFAULT_Q ?
3600                                   "DEFAULT_Q" :
3601                                   qdev->rx_ring[0].type == TX_Q ? "TX_Q" :
3602                                   qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
3603                                   intr_context->name);
3604                 }
3605                 intr_context->hooked = 1;
3606         }
3607         return status;
3608 err_irq:
3609         netif_err(qdev, ifup, qdev->ndev, "Failed to get the interrupts!!!\n");
3610         ql_free_irq(qdev);
3611         return status;
3612 }
3613
3614 static int ql_start_rss(struct ql_adapter *qdev)
3615 {
3616         static const u8 init_hash_seed[] = {
3617                 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
3618                 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
3619                 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
3620                 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
3621                 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa
3622         };
3623         struct ricb *ricb = &qdev->ricb;
3624         int status = 0;
3625         int i;
3626         u8 *hash_id = (u8 *) ricb->hash_cq_id;
3627
3628         memset((void *)ricb, 0, sizeof(*ricb));
3629
3630         ricb->base_cq = RSS_L4K;
3631         ricb->flags =
3632                 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);
3633         ricb->mask = cpu_to_le16((u16)(0x3ff));
3634
3635         /*
3636          * Fill out the Indirection Table.
3637          */
3638         for (i = 0; i < 1024; i++)
3639                 hash_id[i] = (i & (qdev->rss_ring_count - 1));
3640
3641         memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);
3642         memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);
3643
3644         status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
3645         if (status) {
3646                 netif_err(qdev, ifup, qdev->ndev, "Failed to load RICB.\n");
3647                 return status;
3648         }
3649         return status;
3650 }
3651
3652 static int ql_clear_routing_entries(struct ql_adapter *qdev)
3653 {
3654         int i, status = 0;
3655
3656         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3657         if (status)
3658                 return status;
3659         /* Clear all the entries in the routing table. */
3660         for (i = 0; i < 16; i++) {
3661                 status = ql_set_routing_reg(qdev, i, 0, 0);
3662                 if (status) {
3663                         netif_err(qdev, ifup, qdev->ndev,
3664                                   "Failed to init routing register for CAM packets.\n");
3665                         break;
3666                 }
3667         }
3668         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3669         return status;
3670 }
3671
3672 /* Initialize the frame-to-queue routing. */
3673 static int ql_route_initialize(struct ql_adapter *qdev)
3674 {
3675         int status = 0;
3676
3677         /* Clear all the entries in the routing table. */
3678         status = ql_clear_routing_entries(qdev);
3679         if (status)
3680                 return status;
3681
3682         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3683         if (status)
3684                 return status;
3685
3686         status = ql_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT,
3687                                                 RT_IDX_IP_CSUM_ERR, 1);
3688         if (status) {
3689                 netif_err(qdev, ifup, qdev->ndev,
3690                         "Failed to init routing register "
3691                         "for IP CSUM error packets.\n");
3692                 goto exit;
3693         }
3694         status = ql_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT,
3695                                                 RT_IDX_TU_CSUM_ERR, 1);
3696         if (status) {
3697                 netif_err(qdev, ifup, qdev->ndev,
3698                         "Failed to init routing register "
3699                         "for TCP/UDP CSUM error packets.\n");
3700                 goto exit;
3701         }
3702         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3703         if (status) {
3704                 netif_err(qdev, ifup, qdev->ndev,
3705                           "Failed to init routing register for broadcast packets.\n");
3706                 goto exit;
3707         }
3708         /* If we have more than one inbound queue, then turn on RSS in the
3709          * routing block.
3710          */
3711         if (qdev->rss_ring_count > 1) {
3712                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3713                                         RT_IDX_RSS_MATCH, 1);
3714                 if (status) {
3715                         netif_err(qdev, ifup, qdev->ndev,
3716                                   "Failed to init routing register for MATCH RSS packets.\n");
3717                         goto exit;
3718                 }
3719         }
3720
3721         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3722                                     RT_IDX_CAM_HIT, 1);
3723         if (status)
3724                 netif_err(qdev, ifup, qdev->ndev,
3725                           "Failed to init routing register for CAM packets.\n");
3726 exit:
3727         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3728         return status;
3729 }
3730
3731 int ql_cam_route_initialize(struct ql_adapter *qdev)
3732 {
3733         int status, set;
3734
3735         /* If check if the link is up and use to
3736          * determine if we are setting or clearing
3737          * the MAC address in the CAM.
3738          */
3739         set = ql_read32(qdev, STS);
3740         set &= qdev->port_link_up;
3741         status = ql_set_mac_addr(qdev, set);
3742         if (status) {
3743                 netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n");
3744                 return status;
3745         }
3746
3747         status = ql_route_initialize(qdev);
3748         if (status)
3749                 netif_err(qdev, ifup, qdev->ndev, "Failed to init routing table.\n");
3750
3751         return status;
3752 }
3753
3754 static int ql_adapter_initialize(struct ql_adapter *qdev)
3755 {
3756         u32 value, mask;
3757         int i;
3758         int status = 0;
3759
3760         /*
3761          * Set up the System register to halt on errors.
3762          */
3763         value = SYS_EFE | SYS_FAE;
3764         mask = value << 16;
3765         ql_write32(qdev, SYS, mask | value);
3766
3767         /* Set the default queue, and VLAN behavior. */
3768         value = NIC_RCV_CFG_DFQ;
3769         mask = NIC_RCV_CFG_DFQ_MASK;
3770         if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3771                 value |= NIC_RCV_CFG_RV;
3772                 mask |= (NIC_RCV_CFG_RV << 16);
3773         }
3774         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3775
3776         /* Set the MPI interrupt to enabled. */
3777         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3778
3779         /* Enable the function, set pagesize, enable error checking. */
3780         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3781             FSC_EC | FSC_VM_PAGE_4K;
3782         value |= SPLT_SETTING;
3783
3784         /* Set/clear header splitting. */
3785         mask = FSC_VM_PAGESIZE_MASK |
3786             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3787         ql_write32(qdev, FSC, mask | value);
3788
3789         ql_write32(qdev, SPLT_HDR, SPLT_LEN);
3790
3791         /* Set RX packet routing to use port/pci function on which the
3792          * packet arrived on in addition to usual frame routing.
3793          * This is helpful on bonding where both interfaces can have
3794          * the same MAC address.
3795          */
3796         ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);
3797         /* Reroute all packets to our Interface.
3798          * They may have been routed to MPI firmware
3799          * due to WOL.
3800          */
3801         value = ql_read32(qdev, MGMT_RCV_CFG);
3802         value &= ~MGMT_RCV_CFG_RM;
3803         mask = 0xffff0000;
3804
3805         /* Sticky reg needs clearing due to WOL. */
3806         ql_write32(qdev, MGMT_RCV_CFG, mask);
3807         ql_write32(qdev, MGMT_RCV_CFG, mask | value);
3808
3809         /* Default WOL is enable on Mezz cards */
3810         if (qdev->pdev->subsystem_device == 0x0068 ||
3811                         qdev->pdev->subsystem_device == 0x0180)
3812                 qdev->wol = WAKE_MAGIC;
3813
3814         /* Start up the rx queues. */
3815         for (i = 0; i < qdev->rx_ring_count; i++) {
3816                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3817                 if (status) {
3818                         netif_err(qdev, ifup, qdev->ndev,
3819                                   "Failed to start rx ring[%d].\n", i);
3820                         return status;
3821                 }
3822         }
3823
3824         /* If there is more than one inbound completion queue
3825          * then download a RICB to configure RSS.
3826          */
3827         if (qdev->rss_ring_count > 1) {
3828                 status = ql_start_rss(qdev);
3829                 if (status) {
3830                         netif_err(qdev, ifup, qdev->ndev, "Failed to start RSS.\n");
3831                         return status;
3832                 }
3833         }
3834
3835         /* Start up the tx queues. */
3836         for (i = 0; i < qdev->tx_ring_count; i++) {
3837                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3838                 if (status) {
3839                         netif_err(qdev, ifup, qdev->ndev,
3840                                   "Failed to start tx ring[%d].\n", i);
3841                         return status;
3842                 }
3843         }
3844
3845         /* Initialize the port and set the max framesize. */
3846         status = qdev->nic_ops->port_initialize(qdev);
3847         if (status)
3848                 netif_err(qdev, ifup, qdev->ndev, "Failed to start port.\n");
3849
3850         /* Set up the MAC address and frame routing filter. */
3851         status = ql_cam_route_initialize(qdev);
3852         if (status) {
3853                 netif_err(qdev, ifup, qdev->ndev,
3854                           "Failed to init CAM/Routing tables.\n");
3855                 return status;
3856         }
3857
3858         /* Start NAPI for the RSS queues. */
3859         for (i = 0; i < qdev->rss_ring_count; i++)
3860                 napi_enable(&qdev->rx_ring[i].napi);
3861
3862         return status;
3863 }
3864
3865 /* Issue soft reset to chip. */
3866 static int ql_adapter_reset(struct ql_adapter *qdev)
3867 {
3868         u32 value;
3869         int status = 0;
3870         unsigned long end_jiffies;
3871
3872         /* Clear all the entries in the routing table. */
3873         status = ql_clear_routing_entries(qdev);
3874         if (status) {
3875                 netif_err(qdev, ifup, qdev->ndev, "Failed to clear routing bits.\n");
3876                 return status;
3877         }
3878
3879         /* Check if bit is set then skip the mailbox command and
3880          * clear the bit, else we are in normal reset process.
3881          */
3882         if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) {
3883                 /* Stop management traffic. */
3884                 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
3885
3886                 /* Wait for the NIC and MGMNT FIFOs to empty. */
3887                 ql_wait_fifo_empty(qdev);
3888         } else
3889                 clear_bit(QL_ASIC_RECOVERY, &qdev->flags);
3890
3891         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3892
3893         end_jiffies = jiffies + usecs_to_jiffies(30);
3894         do {
3895                 value = ql_read32(qdev, RST_FO);
3896                 if ((value & RST_FO_FR) == 0)
3897                         break;
3898                 cpu_relax();
3899         } while (time_before(jiffies, end_jiffies));
3900
3901         if (value & RST_FO_FR) {
3902                 netif_err(qdev, ifdown, qdev->ndev,
3903                           "ETIMEDOUT!!! errored out of resetting the chip!\n");
3904                 status = -ETIMEDOUT;
3905         }
3906
3907         /* Resume management traffic. */
3908         ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME);
3909         return status;
3910 }
3911
3912 static void ql_display_dev_info(struct net_device *ndev)
3913 {
3914         struct ql_adapter *qdev = netdev_priv(ndev);
3915
3916         netif_info(qdev, probe, qdev->ndev,
3917                    "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
3918                    "XG Roll = %d, XG Rev = %d.\n",
3919                    qdev->func,
3920                    qdev->port,
3921                    qdev->chip_rev_id & 0x0000000f,
3922                    qdev->chip_rev_id >> 4 & 0x0000000f,
3923                    qdev->chip_rev_id >> 8 & 0x0000000f,
3924                    qdev->chip_rev_id >> 12 & 0x0000000f);
3925         netif_info(qdev, probe, qdev->ndev,
3926                    "MAC address %pM\n", ndev->dev_addr);
3927 }
3928
3929 static int ql_wol(struct ql_adapter *qdev)
3930 {
3931         int status = 0;
3932         u32 wol = MB_WOL_DISABLE;
3933
3934         /* The CAM is still intact after a reset, but if we
3935          * are doing WOL, then we may need to program the
3936          * routing regs. We would also need to issue the mailbox
3937          * commands to instruct the MPI what to do per the ethtool
3938          * settings.
3939          */
3940
3941         if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST |
3942                         WAKE_MCAST | WAKE_BCAST)) {
3943                 netif_err(qdev, ifdown, qdev->ndev,
3944                           "Unsupported WOL parameter. qdev->wol = 0x%x.\n",
3945                           qdev->wol);
3946                 return -EINVAL;
3947         }
3948
3949         if (qdev->wol & WAKE_MAGIC) {
3950                 status = ql_mb_wol_set_magic(qdev, 1);
3951                 if (status) {
3952                         netif_err(qdev, ifdown, qdev->ndev,
3953                                   "Failed to set magic packet on %s.\n",
3954                                   qdev->ndev->name);
3955                         return status;
3956                 } else
3957                         netif_info(qdev, drv, qdev->ndev,
3958                                    "Enabled magic packet successfully on %s.\n",
3959                                    qdev->ndev->name);
3960
3961                 wol |= MB_WOL_MAGIC_PKT;
3962         }
3963
3964         if (qdev->wol) {
3965                 wol |= MB_WOL_MODE_ON;
3966                 status = ql_mb_wol_mode(qdev, wol);
3967                 netif_err(qdev, drv, qdev->ndev,
3968                           "WOL %s (wol code 0x%x) on %s\n",
3969                           (status == 0) ? "Successfully set" : "Failed",
3970                           wol, qdev->ndev->name);
3971         }
3972
3973         return status;
3974 }
3975
3976 static void ql_cancel_all_work_sync(struct ql_adapter *qdev)
3977 {
3978
3979         /* Don't kill the reset worker thread if we
3980          * are in the process of recovery.
3981          */
3982         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3983                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3984         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3985         cancel_delayed_work_sync(&qdev->mpi_work);
3986         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3987         cancel_delayed_work_sync(&qdev->mpi_core_to_log);
3988         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3989 }
3990
3991 static int ql_adapter_down(struct ql_adapter *qdev)
3992 {
3993         int i, status = 0;
3994
3995         ql_link_off(qdev);
3996
3997         ql_cancel_all_work_sync(qdev);
3998
3999         for (i = 0; i < qdev->rss_ring_count; i++)
4000                 napi_disable(&qdev->rx_ring[i].napi);
4001
4002         clear_bit(QL_ADAPTER_UP, &qdev->flags);
4003
4004         ql_disable_interrupts(qdev);
4005
4006         ql_tx_ring_clean(qdev);
4007
4008         /* Call netif_napi_del() from common point.
4009          */
4010         for (i = 0; i < qdev->rss_ring_count; i++)
4011                 netif_napi_del(&qdev->rx_ring[i].napi);
4012
4013         status = ql_adapter_reset(qdev);
4014         if (status)
4015                 netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n",
4016                           qdev->func);
4017         ql_free_rx_buffers(qdev);
4018
4019         return status;
4020 }
4021
4022 static int ql_adapter_up(struct ql_adapter *qdev)
4023 {
4024         int err = 0;
4025
4026         err = ql_adapter_initialize(qdev);
4027         if (err) {
4028                 netif_info(qdev, ifup, qdev->ndev, "Unable to initialize adapter.\n");
4029                 goto err_init;
4030         }
4031         set_bit(QL_ADAPTER_UP, &qdev->flags);
4032         ql_alloc_rx_buffers(qdev);
4033         /* If the port is initialized and the
4034          * link is up the turn on the carrier.
4035          */
4036         if ((ql_read32(qdev, STS) & qdev->port_init) &&
4037                         (ql_read32(qdev, STS) & qdev->port_link_up))
4038                 ql_link_on(qdev);
4039         /* Restore rx mode. */
4040         clear_bit(QL_ALLMULTI, &qdev->flags);
4041         clear_bit(QL_PROMISCUOUS, &qdev->flags);
4042         qlge_set_multicast_list(qdev->ndev);
4043
4044         /* Restore vlan setting. */
4045         qlge_restore_vlan(qdev);
4046
4047         ql_enable_interrupts(qdev);
4048         ql_enable_all_completion_interrupts(qdev);
4049         netif_tx_start_all_queues(qdev->ndev);
4050
4051         return 0;
4052 err_init:
4053         ql_adapter_reset(qdev);
4054         return err;
4055 }
4056
4057 static void ql_release_adapter_resources(struct ql_adapter *qdev)
4058 {
4059         ql_free_mem_resources(qdev);
4060         ql_free_irq(qdev);
4061 }
4062
4063 static int ql_get_adapter_resources(struct ql_adapter *qdev)
4064 {
4065         int status = 0;
4066
4067         if (ql_alloc_mem_resources(qdev)) {
4068                 netif_err(qdev, ifup, qdev->ndev, "Unable to  allocate memory.\n");
4069                 return -ENOMEM;
4070         }
4071         status = ql_request_irq(qdev);
4072         return status;
4073 }
4074
4075 static int qlge_close(struct net_device *ndev)
4076 {
4077         struct ql_adapter *qdev = netdev_priv(ndev);
4078
4079         /* If we hit pci_channel_io_perm_failure
4080          * failure condition, then we already
4081          * brought the adapter down.
4082          */
4083         if (test_bit(QL_EEH_FATAL, &qdev->flags)) {
4084                 netif_err(qdev, drv, qdev->ndev, "EEH fatal did unload.\n");
4085                 clear_bit(QL_EEH_FATAL, &qdev->flags);
4086                 return 0;
4087         }
4088
4089         /*
4090          * Wait for device to recover from a reset.
4091          * (Rarely happens, but possible.)
4092          */
4093         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
4094                 msleep(1);
4095         ql_adapter_down(qdev);
4096         ql_release_adapter_resources(qdev);
4097         return 0;
4098 }
4099
4100 static int ql_configure_rings(struct ql_adapter *qdev)
4101 {
4102         int i;
4103         struct rx_ring *rx_ring;
4104         struct tx_ring *tx_ring;
4105         int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus());
4106         unsigned int lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4107                 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4108
4109         qdev->lbq_buf_order = get_order(lbq_buf_len);
4110
4111         /* In a perfect world we have one RSS ring for each CPU
4112          * and each has it's own vector.  To do that we ask for
4113          * cpu_cnt vectors.  ql_enable_msix() will adjust the
4114          * vector count to what we actually get.  We then
4115          * allocate an RSS ring for each.
4116          * Essentially, we are doing min(cpu_count, msix_vector_count).
4117          */
4118         qdev->intr_count = cpu_cnt;
4119         ql_enable_msix(qdev);
4120         /* Adjust the RSS ring count to the actual vector count. */
4121         qdev->rss_ring_count = qdev->intr_count;
4122         qdev->tx_ring_count = cpu_cnt;
4123         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
4124
4125         for (i = 0; i < qdev->tx_ring_count; i++) {
4126                 tx_ring = &qdev->tx_ring[i];
4127                 memset((void *)tx_ring, 0, sizeof(*tx_ring));
4128                 tx_ring->qdev = qdev;
4129                 tx_ring->wq_id = i;
4130                 tx_ring->wq_len = qdev->tx_ring_size;
4131                 tx_ring->wq_size =
4132                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
4133
4134                 /*
4135                  * The completion queue ID for the tx rings start
4136                  * immediately after the rss rings.
4137                  */
4138                 tx_ring->cq_id = qdev->rss_ring_count + i;
4139         }
4140
4141         for (i = 0; i < qdev->rx_ring_count; i++) {
4142                 rx_ring = &qdev->rx_ring[i];
4143                 memset((void *)rx_ring, 0, sizeof(*rx_ring));
4144                 rx_ring->qdev = qdev;
4145                 rx_ring->cq_id = i;
4146                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
4147                 if (i < qdev->rss_ring_count) {
4148                         /*
4149                          * Inbound (RSS) queues.
4150                          */
4151                         rx_ring->cq_len = qdev->rx_ring_size;
4152                         rx_ring->cq_size =
4153                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4154                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
4155                         rx_ring->lbq_size =
4156                             rx_ring->lbq_len * sizeof(__le64);
4157                         rx_ring->lbq_buf_size = (u16)lbq_buf_len;
4158                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
4159                         rx_ring->sbq_size =
4160                             rx_ring->sbq_len * sizeof(__le64);
4161                         rx_ring->sbq_buf_size = SMALL_BUF_MAP_SIZE;
4162                         rx_ring->type = RX_Q;
4163                 } else {
4164                         /*
4165                          * Outbound queue handles outbound completions only.
4166                          */
4167                         /* outbound cq is same size as tx_ring it services. */
4168                         rx_ring->cq_len = qdev->tx_ring_size;
4169                         rx_ring->cq_size =
4170                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4171                         rx_ring->lbq_len = 0;
4172                         rx_ring->lbq_size = 0;
4173                         rx_ring->lbq_buf_size = 0;
4174                         rx_ring->sbq_len = 0;
4175                         rx_ring->sbq_size = 0;
4176                         rx_ring->sbq_buf_size = 0;
4177                         rx_ring->type = TX_Q;
4178                 }
4179         }
4180         return 0;
4181 }
4182
4183 static int qlge_open(struct net_device *ndev)
4184 {
4185         int err = 0;
4186         struct ql_adapter *qdev = netdev_priv(ndev);
4187
4188         err = ql_adapter_reset(qdev);
4189         if (err)
4190                 return err;
4191
4192         err = ql_configure_rings(qdev);
4193         if (err)
4194                 return err;
4195
4196         err = ql_get_adapter_resources(qdev);
4197         if (err)
4198                 goto error_up;
4199
4200         err = ql_adapter_up(qdev);
4201         if (err)
4202                 goto error_up;
4203
4204         return err;
4205
4206 error_up:
4207         ql_release_adapter_resources(qdev);
4208         return err;
4209 }
4210
4211 static int ql_change_rx_buffers(struct ql_adapter *qdev)
4212 {
4213         struct rx_ring *rx_ring;
4214         int i, status;
4215         u32 lbq_buf_len;
4216
4217         /* Wait for an outstanding reset to complete. */
4218         if (!test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4219                 int i = 4;
4220
4221                 while (--i && !test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4222                         netif_err(qdev, ifup, qdev->ndev,
4223                                   "Waiting for adapter UP...\n");
4224                         ssleep(1);
4225                 }
4226
4227                 if (!i) {
4228                         netif_err(qdev, ifup, qdev->ndev,
4229                                   "Timed out waiting for adapter UP\n");
4230                         return -ETIMEDOUT;
4231                 }
4232         }
4233
4234         status = ql_adapter_down(qdev);
4235         if (status)
4236                 goto error;
4237
4238         /* Get the new rx buffer size. */
4239         lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4240                 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4241         qdev->lbq_buf_order = get_order(lbq_buf_len);
4242
4243         for (i = 0; i < qdev->rss_ring_count; i++) {
4244                 rx_ring = &qdev->rx_ring[i];
4245                 /* Set the new size. */
4246                 rx_ring->lbq_buf_size = lbq_buf_len;
4247         }
4248
4249         status = ql_adapter_up(qdev);
4250         if (status)
4251                 goto error;
4252
4253         return status;
4254 error:
4255         netif_alert(qdev, ifup, qdev->ndev,
4256                     "Driver up/down cycle failed, closing device.\n");
4257         set_bit(QL_ADAPTER_UP, &qdev->flags);
4258         dev_close(qdev->ndev);
4259         return status;
4260 }
4261
4262 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
4263 {
4264         struct ql_adapter *qdev = netdev_priv(ndev);
4265         int status;
4266
4267         if (ndev->mtu == 1500 && new_mtu == 9000) {
4268                 netif_err(qdev, ifup, qdev->ndev, "Changing to jumbo MTU.\n");
4269         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
4270                 netif_err(qdev, ifup, qdev->ndev, "Changing to normal MTU.\n");
4271         } else
4272                 return -EINVAL;
4273
4274         queue_delayed_work(qdev->workqueue,
4275                         &qdev->mpi_port_cfg_work, 3*HZ);
4276
4277         ndev->mtu = new_mtu;
4278
4279         if (!netif_running(qdev->ndev)) {
4280                 return 0;
4281         }
4282
4283         status = ql_change_rx_buffers(qdev);
4284         if (status) {
4285                 netif_err(qdev, ifup, qdev->ndev,
4286                           "Changing MTU failed.\n");
4287         }
4288
4289         return status;
4290 }
4291
4292 static struct net_device_stats *qlge_get_stats(struct net_device
4293                                                *ndev)
4294 {
4295         struct ql_adapter *qdev = netdev_priv(ndev);
4296         struct rx_ring *rx_ring = &qdev->rx_ring[0];
4297         struct tx_ring *tx_ring = &qdev->tx_ring[0];
4298         unsigned long pkts, mcast, dropped, errors, bytes;
4299         int i;
4300
4301         /* Get RX stats. */
4302         pkts = mcast = dropped = errors = bytes = 0;
4303         for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) {
4304                         pkts += rx_ring->rx_packets;
4305                         bytes += rx_ring->rx_bytes;
4306                         dropped += rx_ring->rx_dropped;
4307                         errors += rx_ring->rx_errors;
4308                         mcast += rx_ring->rx_multicast;
4309         }
4310         ndev->stats.rx_packets = pkts;
4311         ndev->stats.rx_bytes = bytes;
4312         ndev->stats.rx_dropped = dropped;
4313         ndev->stats.rx_errors = errors;
4314         ndev->stats.multicast = mcast;
4315
4316         /* Get TX stats. */
4317         pkts = errors = bytes = 0;
4318         for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) {
4319                         pkts += tx_ring->tx_packets;
4320                         bytes += tx_ring->tx_bytes;
4321                         errors += tx_ring->tx_errors;
4322         }
4323         ndev->stats.tx_packets = pkts;
4324         ndev->stats.tx_bytes = bytes;
4325         ndev->stats.tx_errors = errors;
4326         return &ndev->stats;
4327 }
4328
4329 static void qlge_set_multicast_list(struct net_device *ndev)
4330 {
4331         struct ql_adapter *qdev = netdev_priv(ndev);
4332         struct netdev_hw_addr *ha;
4333         int i, status;
4334
4335         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
4336         if (status)
4337                 return;
4338         /*
4339          * Set or clear promiscuous mode if a
4340          * transition is taking place.
4341          */
4342         if (ndev->flags & IFF_PROMISC) {
4343                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4344                         if (ql_set_routing_reg
4345                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
4346                                 netif_err(qdev, hw, qdev->ndev,
4347                                           "Failed to set promiscuous mode.\n");
4348                         } else {
4349                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
4350                         }
4351                 }
4352         } else {
4353                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4354                         if (ql_set_routing_reg
4355                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
4356                                 netif_err(qdev, hw, qdev->ndev,
4357                                           "Failed to clear promiscuous mode.\n");
4358                         } else {
4359                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4360                         }
4361                 }
4362         }
4363
4364         /*
4365          * Set or clear all multicast mode if a
4366          * transition is taking place.
4367          */
4368         if ((ndev->flags & IFF_ALLMULTI) ||
4369             (netdev_mc_count(ndev) > MAX_MULTICAST_ENTRIES)) {
4370                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
4371                         if (ql_set_routing_reg
4372                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
4373                                 netif_err(qdev, hw, qdev->ndev,
4374                                           "Failed to set all-multi mode.\n");
4375                         } else {
4376                                 set_bit(QL_ALLMULTI, &qdev->flags);
4377                         }
4378                 }
4379         } else {
4380                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
4381                         if (ql_set_routing_reg
4382                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
4383                                 netif_err(qdev, hw, qdev->ndev,
4384                                           "Failed to clear all-multi mode.\n");
4385                         } else {
4386                                 clear_bit(QL_ALLMULTI, &qdev->flags);
4387                         }
4388                 }
4389         }
4390
4391         if (!netdev_mc_empty(ndev)) {
4392                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4393                 if (status)
4394                         goto exit;
4395                 i = 0;
4396                 netdev_for_each_mc_addr(ha, ndev) {
4397                         if (ql_set_mac_addr_reg(qdev, (u8 *) ha->addr,
4398                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
4399                                 netif_err(qdev, hw, qdev->ndev,
4400                                           "Failed to loadmulticast address.\n");
4401                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4402                                 goto exit;
4403                         }
4404                         i++;
4405                 }
4406                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4407                 if (ql_set_routing_reg
4408                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
4409                         netif_err(qdev, hw, qdev->ndev,
4410                                   "Failed to set multicast match mode.\n");
4411                 } else {
4412                         set_bit(QL_ALLMULTI, &qdev->flags);
4413                 }
4414         }
4415 exit:
4416         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
4417 }
4418
4419 static int qlge_set_mac_address(struct net_device *ndev, void *p)
4420 {
4421         struct ql_adapter *qdev = netdev_priv(ndev);
4422         struct sockaddr *addr = p;
4423         int status;
4424
4425         if (!is_valid_ether_addr(addr->sa_data))
4426                 return -EADDRNOTAVAIL;
4427         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
4428         /* Update local copy of current mac address. */
4429         memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4430
4431         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4432         if (status)
4433                 return status;
4434         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
4435                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
4436         if (status)
4437                 netif_err(qdev, hw, qdev->ndev, "Failed to load MAC address.\n");
4438         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4439         return status;
4440 }
4441
4442 static void qlge_tx_timeout(struct net_device *ndev)
4443 {
4444         struct ql_adapter *qdev = netdev_priv(ndev);
4445         ql_queue_asic_error(qdev);
4446 }
4447
4448 static void ql_asic_reset_work(struct work_struct *work)
4449 {
4450         struct ql_adapter *qdev =
4451             container_of(work, struct ql_adapter, asic_reset_work.work);
4452         int status;
4453         rtnl_lock();
4454         status = ql_adapter_down(qdev);
4455         if (status)
4456                 goto error;
4457
4458         status = ql_adapter_up(qdev);
4459         if (status)
4460                 goto error;
4461
4462         /* Restore rx mode. */
4463         clear_bit(QL_ALLMULTI, &qdev->flags);
4464         clear_bit(QL_PROMISCUOUS, &qdev->flags);
4465         qlge_set_multicast_list(qdev->ndev);
4466
4467         rtnl_unlock();
4468         return;
4469 error:
4470         netif_alert(qdev, ifup, qdev->ndev,
4471                     "Driver up/down cycle failed, closing device\n");
4472
4473         set_bit(QL_ADAPTER_UP, &qdev->flags);
4474         dev_close(qdev->ndev);
4475         rtnl_unlock();
4476 }
4477
4478 static const struct nic_operations qla8012_nic_ops = {
4479         .get_flash              = ql_get_8012_flash_params,
4480         .port_initialize        = ql_8012_port_initialize,
4481 };
4482
4483 static const struct nic_operations qla8000_nic_ops = {
4484         .get_flash              = ql_get_8000_flash_params,
4485         .port_initialize        = ql_8000_port_initialize,
4486 };
4487
4488 /* Find the pcie function number for the other NIC
4489  * on this chip.  Since both NIC functions share a
4490  * common firmware we have the lowest enabled function
4491  * do any common work.  Examples would be resetting
4492  * after a fatal firmware error, or doing a firmware
4493  * coredump.
4494  */
4495 static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
4496 {
4497         int status = 0;
4498         u32 temp;
4499         u32 nic_func1, nic_func2;
4500
4501         status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
4502                         &temp);
4503         if (status)
4504                 return status;
4505
4506         nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
4507                         MPI_TEST_NIC_FUNC_MASK);
4508         nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
4509                         MPI_TEST_NIC_FUNC_MASK);
4510
4511         if (qdev->func == nic_func1)
4512                 qdev->alt_func = nic_func2;
4513         else if (qdev->func == nic_func2)
4514                 qdev->alt_func = nic_func1;
4515         else
4516                 status = -EIO;
4517
4518         return status;
4519 }
4520
4521 static int ql_get_board_info(struct ql_adapter *qdev)
4522 {
4523         int status;
4524         qdev->func =
4525             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
4526         if (qdev->func > 3)
4527                 return -EIO;
4528
4529         status = ql_get_alt_pcie_func(qdev);
4530         if (status)
4531                 return status;
4532
4533         qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
4534         if (qdev->port) {
4535                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
4536                 qdev->port_link_up = STS_PL1;
4537                 qdev->port_init = STS_PI1;
4538                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
4539                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
4540         } else {
4541                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
4542                 qdev->port_link_up = STS_PL0;
4543                 qdev->port_init = STS_PI0;
4544                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
4545                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
4546         }
4547         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
4548         qdev->device_id = qdev->pdev->device;
4549         if (qdev->device_id == QLGE_DEVICE_ID_8012)
4550                 qdev->nic_ops = &qla8012_nic_ops;
4551         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
4552                 qdev->nic_ops = &qla8000_nic_ops;
4553         return status;
4554 }
4555
4556 static void ql_release_all(struct pci_dev *pdev)
4557 {
4558         struct net_device *ndev = pci_get_drvdata(pdev);
4559         struct ql_adapter *qdev = netdev_priv(ndev);
4560
4561         if (qdev->workqueue) {
4562                 destroy_workqueue(qdev->workqueue);
4563                 qdev->workqueue = NULL;
4564         }
4565
4566         if (qdev->reg_base)
4567                 iounmap(qdev->reg_base);
4568         if (qdev->doorbell_area)
4569                 iounmap(qdev->doorbell_area);
4570         vfree(qdev->mpi_coredump);
4571         pci_release_regions(pdev);
4572 }
4573
4574 static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev,
4575                           int cards_found)
4576 {
4577         struct ql_adapter *qdev = netdev_priv(ndev);
4578         int err = 0;
4579
4580         memset((void *)qdev, 0, sizeof(*qdev));
4581         err = pci_enable_device(pdev);
4582         if (err) {
4583                 dev_err(&pdev->dev, "PCI device enable failed.\n");
4584                 return err;
4585         }
4586
4587         qdev->ndev = ndev;
4588         qdev->pdev = pdev;
4589         pci_set_drvdata(pdev, ndev);
4590
4591         /* Set PCIe read request size */
4592         err = pcie_set_readrq(pdev, 4096);
4593         if (err) {
4594                 dev_err(&pdev->dev, "Set readrq failed.\n");
4595                 goto err_out1;
4596         }
4597
4598         err = pci_request_regions(pdev, DRV_NAME);
4599         if (err) {
4600                 dev_err(&pdev->dev, "PCI region request failed.\n");
4601                 return err;
4602         }
4603
4604         pci_set_master(pdev);
4605         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4606                 set_bit(QL_DMA64, &qdev->flags);
4607                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4608         } else {
4609                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4610                 if (!err)
4611                        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4612         }
4613
4614         if (err) {
4615                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
4616                 goto err_out2;
4617         }
4618
4619         /* Set PCIe reset type for EEH to fundamental. */
4620         pdev->needs_freset = 1;
4621         pci_save_state(pdev);
4622         qdev->reg_base =
4623             ioremap_nocache(pci_resource_start(pdev, 1),
4624                             pci_resource_len(pdev, 1));
4625         if (!qdev->reg_base) {
4626                 dev_err(&pdev->dev, "Register mapping failed.\n");
4627                 err = -ENOMEM;
4628                 goto err_out2;
4629         }
4630
4631         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
4632         qdev->doorbell_area =
4633             ioremap_nocache(pci_resource_start(pdev, 3),
4634                             pci_resource_len(pdev, 3));
4635         if (!qdev->doorbell_area) {
4636                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
4637                 err = -ENOMEM;
4638                 goto err_out2;
4639         }
4640
4641         err = ql_get_board_info(qdev);
4642         if (err) {
4643                 dev_err(&pdev->dev, "Register access failed.\n");
4644                 err = -EIO;
4645                 goto err_out2;
4646         }
4647         qdev->msg_enable = netif_msg_init(debug, default_msg);
4648         spin_lock_init(&qdev->hw_lock);
4649         spin_lock_init(&qdev->stats_lock);
4650
4651         if (qlge_mpi_coredump) {
4652                 qdev->mpi_coredump =
4653                         vmalloc(sizeof(struct ql_mpi_coredump));
4654                 if (qdev->mpi_coredump == NULL) {
4655                         err = -ENOMEM;
4656                         goto err_out2;
4657                 }
4658                 if (qlge_force_coredump)
4659                         set_bit(QL_FRC_COREDUMP, &qdev->flags);
4660         }
4661         /* make sure the EEPROM is good */
4662         err = qdev->nic_ops->get_flash(qdev);
4663         if (err) {
4664                 dev_err(&pdev->dev, "Invalid FLASH.\n");
4665                 goto err_out2;
4666         }
4667
4668         /* Keep local copy of current mac address. */
4669         memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4670
4671         /* Set up the default ring sizes. */
4672         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
4673         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
4674
4675         /* Set up the coalescing parameters. */
4676         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
4677         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
4678         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4679         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4680
4681         /*
4682          * Set up the operating parameters.
4683          */
4684         qdev->workqueue = create_singlethread_workqueue(ndev->name);
4685         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
4686         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
4687         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
4688         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
4689         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
4690         INIT_DELAYED_WORK(&qdev->mpi_core_to_log, ql_mpi_core_to_log);
4691         init_completion(&qdev->ide_completion);
4692         mutex_init(&qdev->mpi_mutex);
4693
4694         if (!cards_found) {
4695                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
4696                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
4697                          DRV_NAME, DRV_VERSION);
4698         }
4699         return 0;
4700 err_out2:
4701         ql_release_all(pdev);
4702 err_out1:
4703         pci_disable_device(pdev);
4704         return err;
4705 }
4706
4707 static const struct net_device_ops qlge_netdev_ops = {
4708         .ndo_open               = qlge_open,
4709         .ndo_stop               = qlge_close,
4710         .ndo_start_xmit         = qlge_send,
4711         .ndo_change_mtu         = qlge_change_mtu,
4712         .ndo_get_stats          = qlge_get_stats,
4713         .ndo_set_rx_mode        = qlge_set_multicast_list,
4714         .ndo_set_mac_address    = qlge_set_mac_address,
4715         .ndo_validate_addr      = eth_validate_addr,
4716         .ndo_tx_timeout         = qlge_tx_timeout,
4717         .ndo_set_features       = qlge_set_features,
4718         .ndo_vlan_rx_add_vid    = qlge_vlan_rx_add_vid,
4719         .ndo_vlan_rx_kill_vid   = qlge_vlan_rx_kill_vid,
4720 };
4721
4722 static void ql_timer(unsigned long data)
4723 {
4724         struct ql_adapter *qdev = (struct ql_adapter *)data;
4725         u32 var = 0;
4726
4727         var = ql_read32(qdev, STS);
4728         if (pci_channel_offline(qdev->pdev)) {
4729                 netif_err(qdev, ifup, qdev->ndev, "EEH STS = 0x%.08x.\n", var);
4730                 return;
4731         }
4732
4733         mod_timer(&qdev->timer, jiffies + (5*HZ));
4734 }
4735
4736 static int qlge_probe(struct pci_dev *pdev,
4737                       const struct pci_device_id *pci_entry)
4738 {
4739         struct net_device *ndev = NULL;
4740         struct ql_adapter *qdev = NULL;
4741         static int cards_found = 0;
4742         int err = 0;
4743
4744         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
4745                         min(MAX_CPUS, netif_get_num_default_rss_queues()));
4746         if (!ndev)
4747                 return -ENOMEM;
4748
4749         err = ql_init_device(pdev, ndev, cards_found);
4750         if (err < 0) {
4751                 free_netdev(ndev);
4752                 return err;
4753         }
4754
4755         qdev = netdev_priv(ndev);
4756         SET_NETDEV_DEV(ndev, &pdev->dev);
4757         ndev->hw_features = NETIF_F_SG |
4758                             NETIF_F_IP_CSUM |
4759                             NETIF_F_TSO |
4760                             NETIF_F_TSO_ECN |
4761                             NETIF_F_HW_VLAN_CTAG_TX |
4762                             NETIF_F_HW_VLAN_CTAG_RX |
4763                             NETIF_F_HW_VLAN_CTAG_FILTER |
4764                             NETIF_F_RXCSUM;
4765         ndev->features = ndev->hw_features;
4766         ndev->vlan_features = ndev->hw_features;
4767         /* vlan gets same features (except vlan filter) */
4768         ndev->vlan_features &= ~(NETIF_F_HW_VLAN_CTAG_FILTER |
4769                                  NETIF_F_HW_VLAN_CTAG_TX |
4770                                  NETIF_F_HW_VLAN_CTAG_RX);
4771
4772         if (test_bit(QL_DMA64, &qdev->flags))
4773                 ndev->features |= NETIF_F_HIGHDMA;
4774
4775         /*
4776          * Set up net_device structure.
4777          */
4778         ndev->tx_queue_len = qdev->tx_ring_size;
4779         ndev->irq = pdev->irq;
4780
4781         ndev->netdev_ops = &qlge_netdev_ops;
4782         ndev->ethtool_ops = &qlge_ethtool_ops;
4783         ndev->watchdog_timeo = 10 * HZ;
4784
4785         err = register_netdev(ndev);
4786         if (err) {
4787                 dev_err(&pdev->dev, "net device registration failed.\n");
4788                 ql_release_all(pdev);
4789                 pci_disable_device(pdev);
4790                 free_netdev(ndev);
4791                 return err;
4792         }
4793         /* Start up the timer to trigger EEH if
4794          * the bus goes dead
4795          */
4796         init_timer_deferrable(&qdev->timer);
4797         qdev->timer.data = (unsigned long)qdev;
4798         qdev->timer.function = ql_timer;
4799         qdev->timer.expires = jiffies + (5*HZ);
4800         add_timer(&qdev->timer);
4801         ql_link_off(qdev);
4802         ql_display_dev_info(ndev);
4803         atomic_set(&qdev->lb_count, 0);
4804         cards_found++;
4805         return 0;
4806 }
4807
4808 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev)
4809 {
4810         return qlge_send(skb, ndev);
4811 }
4812
4813 int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget)
4814 {
4815         return ql_clean_inbound_rx_ring(rx_ring, budget);
4816 }
4817
4818 static void qlge_remove(struct pci_dev *pdev)
4819 {
4820         struct net_device *ndev = pci_get_drvdata(pdev);
4821         struct ql_adapter *qdev = netdev_priv(ndev);
4822         del_timer_sync(&qdev->timer);
4823         ql_cancel_all_work_sync(qdev);
4824         unregister_netdev(ndev);
4825         ql_release_all(pdev);
4826         pci_disable_device(pdev);
4827         free_netdev(ndev);
4828 }
4829
4830 /* Clean up resources without touching hardware. */
4831 static void ql_eeh_close(struct net_device *ndev)
4832 {
4833         int i;
4834         struct ql_adapter *qdev = netdev_priv(ndev);
4835
4836         if (netif_carrier_ok(ndev)) {
4837                 netif_carrier_off(ndev);
4838                 netif_stop_queue(ndev);
4839         }
4840
4841         /* Disabling the timer */
4842         del_timer_sync(&qdev->timer);
4843         ql_cancel_all_work_sync(qdev);
4844
4845         for (i = 0; i < qdev->rss_ring_count; i++)
4846                 netif_napi_del(&qdev->rx_ring[i].napi);
4847
4848         clear_bit(QL_ADAPTER_UP, &qdev->flags);
4849         ql_tx_ring_clean(qdev);
4850         ql_free_rx_buffers(qdev);
4851         ql_release_adapter_resources(qdev);
4852 }
4853
4854 /*
4855  * This callback is called by the PCI subsystem whenever
4856  * a PCI bus error is detected.
4857  */
4858 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
4859                                                enum pci_channel_state state)
4860 {
4861         struct net_device *ndev = pci_get_drvdata(pdev);
4862         struct ql_adapter *qdev = netdev_priv(ndev);
4863
4864         switch (state) {
4865         case pci_channel_io_normal:
4866                 return PCI_ERS_RESULT_CAN_RECOVER;
4867         case pci_channel_io_frozen:
4868                 netif_device_detach(ndev);
4869                 if (netif_running(ndev))
4870                         ql_eeh_close(ndev);
4871                 pci_disable_device(pdev);
4872                 return PCI_ERS_RESULT_NEED_RESET;
4873         case pci_channel_io_perm_failure:
4874                 dev_err(&pdev->dev,
4875                         "%s: pci_channel_io_perm_failure.\n", __func__);
4876                 ql_eeh_close(ndev);
4877                 set_bit(QL_EEH_FATAL, &qdev->flags);
4878                 return PCI_ERS_RESULT_DISCONNECT;
4879         }
4880
4881         /* Request a slot reset. */
4882         return PCI_ERS_RESULT_NEED_RESET;
4883 }
4884
4885 /*
4886  * This callback is called after the PCI buss has been reset.
4887  * Basically, this tries to restart the card from scratch.
4888  * This is a shortened version of the device probe/discovery code,
4889  * it resembles the first-half of the () routine.
4890  */
4891 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4892 {
4893         struct net_device *ndev = pci_get_drvdata(pdev);
4894         struct ql_adapter *qdev = netdev_priv(ndev);
4895
4896         pdev->error_state = pci_channel_io_normal;
4897
4898         pci_restore_state(pdev);
4899         if (pci_enable_device(pdev)) {
4900                 netif_err(qdev, ifup, qdev->ndev,
4901                           "Cannot re-enable PCI device after reset.\n");
4902                 return PCI_ERS_RESULT_DISCONNECT;
4903         }
4904         pci_set_master(pdev);
4905
4906         if (ql_adapter_reset(qdev)) {
4907                 netif_err(qdev, drv, qdev->ndev, "reset FAILED!\n");
4908                 set_bit(QL_EEH_FATAL, &qdev->flags);
4909                 return PCI_ERS_RESULT_DISCONNECT;
4910         }
4911
4912         return PCI_ERS_RESULT_RECOVERED;
4913 }
4914
4915 static void qlge_io_resume(struct pci_dev *pdev)
4916 {
4917         struct net_device *ndev = pci_get_drvdata(pdev);
4918         struct ql_adapter *qdev = netdev_priv(ndev);
4919         int err = 0;
4920
4921         if (netif_running(ndev)) {
4922                 err = qlge_open(ndev);
4923                 if (err) {
4924                         netif_err(qdev, ifup, qdev->ndev,
4925                                   "Device initialization failed after reset.\n");
4926                         return;
4927                 }
4928         } else {
4929                 netif_err(qdev, ifup, qdev->ndev,
4930                           "Device was not running prior to EEH.\n");
4931         }
4932         mod_timer(&qdev->timer, jiffies + (5*HZ));
4933         netif_device_attach(ndev);
4934 }
4935
4936 static const struct pci_error_handlers qlge_err_handler = {
4937         .error_detected = qlge_io_error_detected,
4938         .slot_reset = qlge_io_slot_reset,
4939         .resume = qlge_io_resume,
4940 };
4941
4942 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4943 {
4944         struct net_device *ndev = pci_get_drvdata(pdev);
4945         struct ql_adapter *qdev = netdev_priv(ndev);
4946         int err;
4947
4948         netif_device_detach(ndev);
4949         del_timer_sync(&qdev->timer);
4950
4951         if (netif_running(ndev)) {
4952                 err = ql_adapter_down(qdev);
4953                 if (!err)
4954                         return err;
4955         }
4956
4957         ql_wol(qdev);
4958         err = pci_save_state(pdev);
4959         if (err)
4960                 return err;
4961
4962         pci_disable_device(pdev);
4963
4964         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4965
4966         return 0;
4967 }
4968
4969 #ifdef CONFIG_PM
4970 static int qlge_resume(struct pci_dev *pdev)
4971 {
4972         struct net_device *ndev = pci_get_drvdata(pdev);
4973         struct ql_adapter *qdev = netdev_priv(ndev);
4974         int err;
4975
4976         pci_set_power_state(pdev, PCI_D0);
4977         pci_restore_state(pdev);
4978         err = pci_enable_device(pdev);
4979         if (err) {
4980                 netif_err(qdev, ifup, qdev->ndev, "Cannot enable PCI device from suspend\n");
4981                 return err;
4982         }
4983         pci_set_master(pdev);
4984
4985         pci_enable_wake(pdev, PCI_D3hot, 0);
4986         pci_enable_wake(pdev, PCI_D3cold, 0);
4987
4988         if (netif_running(ndev)) {
4989                 err = ql_adapter_up(qdev);
4990                 if (err)
4991                         return err;
4992         }
4993
4994         mod_timer(&qdev->timer, jiffies + (5*HZ));
4995         netif_device_attach(ndev);
4996
4997         return 0;
4998 }
4999 #endif /* CONFIG_PM */
5000
5001 static void qlge_shutdown(struct pci_dev *pdev)
5002 {
5003         qlge_suspend(pdev, PMSG_SUSPEND);
5004 }
5005
5006 static struct pci_driver qlge_driver = {
5007         .name = DRV_NAME,
5008         .id_table = qlge_pci_tbl,
5009         .probe = qlge_probe,
5010         .remove = qlge_remove,
5011 #ifdef CONFIG_PM
5012         .suspend = qlge_suspend,
5013         .resume = qlge_resume,
5014 #endif
5015         .shutdown = qlge_shutdown,
5016         .err_handler = &qlge_err_handler
5017 };
5018
5019 module_pci_driver(qlge_driver);