drivers/net/ethernet/qualcomm/emac/emac-sgmii.c

   1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
  14  */
  15
  16 #include <linux/iopoll.h>
  17 #include <linux/acpi.h>
  18 #include <linux/of_device.h>
  19 #include "emac.h"
  20 #include "emac-mac.h"
  21 #include "emac-sgmii.h"
  22
  23 /* EMAC_QSERDES register offsets */
  24 #define EMAC_QSERDES_COM_SYS_CLK_CTRL           0x000000
  25 #define EMAC_QSERDES_COM_PLL_CNTRL              0x000014
  26 #define EMAC_QSERDES_COM_PLL_IP_SETI            0x000018
  27 #define EMAC_QSERDES_COM_PLL_CP_SETI            0x000024
  28 #define EMAC_QSERDES_COM_PLL_IP_SETP            0x000028
  29 #define EMAC_QSERDES_COM_PLL_CP_SETP            0x00002c
  30 #define EMAC_QSERDES_COM_SYSCLK_EN_SEL          0x000038
  31 #define EMAC_QSERDES_COM_RESETSM_CNTRL          0x000040
  32 #define EMAC_QSERDES_COM_PLLLOCK_CMP1           0x000044
  33 #define EMAC_QSERDES_COM_PLLLOCK_CMP2           0x000048
  34 #define EMAC_QSERDES_COM_PLLLOCK_CMP3           0x00004c
  35 #define EMAC_QSERDES_COM_PLLLOCK_CMP_EN         0x000050
  36 #define EMAC_QSERDES_COM_DEC_START1             0x000064
  37 #define EMAC_QSERDES_COM_DIV_FRAC_START1        0x000098
  38 #define EMAC_QSERDES_COM_DIV_FRAC_START2        0x00009c
  39 #define EMAC_QSERDES_COM_DIV_FRAC_START3        0x0000a0
  40 #define EMAC_QSERDES_COM_DEC_START2             0x0000a4
  41 #define EMAC_QSERDES_COM_PLL_CRCTRL             0x0000ac
  42 #define EMAC_QSERDES_COM_RESET_SM               0x0000bc
  43 #define EMAC_QSERDES_TX_BIST_MODE_LANENO        0x000100
  44 #define EMAC_QSERDES_TX_TX_EMP_POST1_LVL        0x000108
  45 #define EMAC_QSERDES_TX_TX_DRV_LVL              0x00010c
  46 #define EMAC_QSERDES_TX_LANE_MODE               0x000150
  47 #define EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN        0x000170
  48 #define EMAC_QSERDES_RX_CDR_CONTROL             0x000200
  49 #define EMAC_QSERDES_RX_CDR_CONTROL2            0x000210
  50 #define EMAC_QSERDES_RX_RX_EQ_GAIN12            0x000230
  51
  52 /* EMAC_SGMII register offsets */
  53 #define EMAC_SGMII_PHY_SERDES_START             0x000000
  54 #define EMAC_SGMII_PHY_CMN_PWR_CTRL             0x000004
  55 #define EMAC_SGMII_PHY_RX_PWR_CTRL              0x000008
  56 #define EMAC_SGMII_PHY_TX_PWR_CTRL              0x00000C
  57 #define EMAC_SGMII_PHY_LANE_CTRL1               0x000018
  58 #define EMAC_SGMII_PHY_AUTONEG_CFG2             0x000048
  59 #define EMAC_SGMII_PHY_CDR_CTRL0                0x000058
  60 #define EMAC_SGMII_PHY_SPEED_CFG1               0x000074
  61 #define EMAC_SGMII_PHY_POW_DWN_CTRL0            0x000080
  62 #define EMAC_SGMII_PHY_RESET_CTRL               0x0000a8
  63 #define EMAC_SGMII_PHY_IRQ_CMD                  0x0000ac
  64 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR          0x0000b0
  65 #define EMAC_SGMII_PHY_INTERRUPT_MASK           0x0000b4
  66 #define EMAC_SGMII_PHY_INTERRUPT_STATUS         0x0000b8
  67 #define EMAC_SGMII_PHY_RX_CHK_STATUS            0x0000d4
  68 #define EMAC_SGMII_PHY_AUTONEG0_STATUS          0x0000e0
  69 #define EMAC_SGMII_PHY_AUTONEG1_STATUS          0x0000e4
  70
  71 /* EMAC_QSERDES_COM_PLL_IP_SETI */
  72 #define PLL_IPSETI(x)                           ((x) & 0x3f)
  73
  74 /* EMAC_QSERDES_COM_PLL_CP_SETI */
  75 #define PLL_CPSETI(x)                           ((x) & 0xff)
  76
  77 /* EMAC_QSERDES_COM_PLL_IP_SETP */
  78 #define PLL_IPSETP(x)                           ((x) & 0x3f)
  79
  80 /* EMAC_QSERDES_COM_PLL_CP_SETP */
  81 #define PLL_CPSETP(x)                           ((x) & 0x1f)
  82
  83 /* EMAC_QSERDES_COM_PLL_CRCTRL */
  84 #define PLL_RCTRL(x)                            (((x) & 0xf) << 4)
  85 #define PLL_CCTRL(x)                            ((x) & 0xf)
  86
  87 /* SGMII v2 PHY registers per lane */
  88 #define EMAC_SGMII_PHY_LN_OFFSET                0x0400
  89
  90 /* SGMII v2 digital lane registers */
  91 #define EMAC_SGMII_LN_DRVR_CTRL0                0x00C
  92 #define EMAC_SGMII_LN_DRVR_TAP_EN               0x018
  93 #define EMAC_SGMII_LN_TX_MARGINING              0x01C
  94 #define EMAC_SGMII_LN_TX_PRE                    0x020
  95 #define EMAC_SGMII_LN_TX_POST                   0x024
  96 #define EMAC_SGMII_LN_TX_BAND_MODE              0x060
  97 #define EMAC_SGMII_LN_LANE_MODE                 0x064
  98 #define EMAC_SGMII_LN_PARALLEL_RATE             0x078
  99 #define EMAC_SGMII_LN_CML_CTRL_MODE0            0x0B8
 100 #define EMAC_SGMII_LN_MIXER_CTRL_MODE0          0x0D0
 101 #define EMAC_SGMII_LN_VGA_INITVAL               0x134
 102 #define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0        0x17C
 103 #define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0        0x188
 104 #define EMAC_SGMII_LN_UCDR_SO_CONFIG            0x194
 105 #define EMAC_SGMII_LN_RX_BAND                   0x19C
 106 #define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0       0x1B8
 107 #define EMAC_SGMII_LN_RSM_CONFIG                0x1F0
 108 #define EMAC_SGMII_LN_SIGDET_ENABLES            0x224
 109 #define EMAC_SGMII_LN_SIGDET_CNTRL              0x228
 110 #define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL     0x22C
 111 #define EMAC_SGMII_LN_RX_EN_SIGNAL              0x2A0
 112 #define EMAC_SGMII_LN_RX_MISC_CNTRL0            0x2AC
 113 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV         0x2BC
 114
 115 /* SGMII v2 digital lane register values */
 116 #define UCDR_STEP_BY_TWO_MODE0                  BIT(7)
 117 #define UCDR_xO_GAIN_MODE(x)                    ((x) & 0x7f)
 118 #define UCDR_ENABLE                             BIT(6)
 119 #define UCDR_SO_SATURATION(x)                   ((x) & 0x3f)
 120 #define SIGDET_LP_BYP_PS4                       BIT(7)
 121 #define SIGDET_EN_PS0_TO_PS2                    BIT(6)
 122 #define EN_ACCOUPLEVCM_SW_MUX                   BIT(5)
 123 #define EN_ACCOUPLEVCM_SW                       BIT(4)
 124 #define RX_SYNC_EN                              BIT(3)
 125 #define RXTERM_HIGHZ_PS5                        BIT(2)
 126 #define SIGDET_EN_PS3                           BIT(1)
 127 #define EN_ACCOUPLE_VCM_PS3                     BIT(0)
 128 #define UFS_MODE                                BIT(5)
 129 #define TXVAL_VALID_INIT                        BIT(4)
 130 #define TXVAL_VALID_MUX                         BIT(3)
 131 #define TXVAL_VALID                             BIT(2)
 132 #define USB3P1_MODE                             BIT(1)
 133 #define KR_PCIGEN3_MODE                         BIT(0)
 134 #define PRE_EN                                  BIT(3)
 135 #define POST_EN                                 BIT(2)
 136 #define MAIN_EN_MUX                             BIT(1)
 137 #define MAIN_EN                                 BIT(0)
 138 #define TX_MARGINING_MUX                        BIT(6)
 139 #define TX_MARGINING(x)                         ((x) & 0x3f)
 140 #define TX_PRE_MUX                              BIT(6)
 141 #define TX_PRE(x)                               ((x) & 0x3f)
 142 #define TX_POST_MUX                             BIT(6)
 143 #define TX_POST(x)                              ((x) & 0x3f)
 144 #define CML_GEAR_MODE(x)                        (((x) & 7) << 3)
 145 #define CML2CMOS_IBOOST_MODE(x)                 ((x) & 7)
 146 #define MIXER_LOADB_MODE(x)                     (((x) & 0xf) << 2)
 147 #define MIXER_DATARATE_MODE(x)                  ((x) & 3)
 148 #define VGA_THRESH_DFE(x)                       ((x) & 0x3f)
 149 #define SIGDET_LP_BYP_PS0_TO_PS2                BIT(5)
 150 #define SIGDET_LP_BYP_MUX                       BIT(4)
 151 #define SIGDET_LP_BYP                           BIT(3)
 152 #define SIGDET_EN_MUX                           BIT(2)
 153 #define SIGDET_EN                               BIT(1)
 154 #define SIGDET_FLT_BYP                          BIT(0)
 155 #define SIGDET_LVL(x)                           (((x) & 0xf) << 4)
 156 #define SIGDET_BW_CTRL(x)                       ((x) & 0xf)
 157 #define SIGDET_DEGLITCH_CTRL(x)                 (((x) & 0xf) << 1)
 158 #define SIGDET_DEGLITCH_BYP                     BIT(0)
 159 #define INVERT_PCS_RX_CLK                       BIT(7)
 160 #define PWM_EN                                  BIT(6)
 161 #define RXBIAS_SEL(x)                           (((x) & 0x3) << 4)
 162 #define EBDAC_SIGN                              BIT(3)
 163 #define EDAC_SIGN                               BIT(2)
 164 #define EN_AUXTAP1SIGN_INVERT                   BIT(1)
 165 #define EN_DAC_CHOPPING                         BIT(0)
 166 #define DRVR_LOGIC_CLK_EN                       BIT(4)
 167 #define DRVR_LOGIC_CLK_DIV(x)                   ((x) & 0xf)
 168 #define PARALLEL_RATE_MODE2(x)                  (((x) & 0x3) << 4)
 169 #define PARALLEL_RATE_MODE1(x)                  (((x) & 0x3) << 2)
 170 #define PARALLEL_RATE_MODE0(x)                  ((x) & 0x3)
 171 #define BAND_MODE2(x)                           (((x) & 0x3) << 4)
 172 #define BAND_MODE1(x)                           (((x) & 0x3) << 2)
 173 #define BAND_MODE0(x)                           ((x) & 0x3)
 174 #define LANE_SYNC_MODE                          BIT(5)
 175 #define LANE_MODE(x)                            ((x) & 0x1f)
 176 #define CDR_PD_SEL_MODE0(x)                     (((x) & 0x3) << 5)
 177 #define EN_DLL_MODE0                            BIT(4)
 178 #define EN_IQ_DCC_MODE0                         BIT(3)
 179 #define EN_IQCAL_MODE0                          BIT(2)
 180 #define EN_QPATH_MODE0                          BIT(1)
 181 #define EN_EPATH_MODE0                          BIT(0)
 182 #define FORCE_TSYNC_ACK                         BIT(7)
 183 #define FORCE_CMN_ACK                           BIT(6)
 184 #define FORCE_CMN_READY                         BIT(5)
 185 #define EN_RCLK_DEGLITCH                        BIT(4)
 186 #define BYPASS_RSM_CDR_RESET                    BIT(3)
 187 #define BYPASS_RSM_TSYNC                        BIT(2)
 188 #define BYPASS_RSM_SAMP_CAL                     BIT(1)
 189 #define BYPASS_RSM_DLL_CAL                      BIT(0)
 190
 191 /* EMAC_QSERDES_COM_SYS_CLK_CTRL */
 192 #define SYSCLK_CM                               BIT(4)
 193 #define SYSCLK_AC_COUPLE                        BIT(3)
 194
 195 /* EMAC_QSERDES_COM_PLL_CNTRL */
 196 #define OCP_EN                                  BIT(5)
 197 #define PLL_DIV_FFEN                            BIT(2)
 198 #define PLL_DIV_ORD                             BIT(1)
 199
 200 /* EMAC_QSERDES_COM_SYSCLK_EN_SEL */
 201 #define SYSCLK_SEL_CMOS                         BIT(3)
 202
 203 /* EMAC_QSERDES_COM_RESETSM_CNTRL */
 204 #define FRQ_TUNE_MODE                           BIT(4)
 205
 206 /* EMAC_QSERDES_COM_PLLLOCK_CMP_EN */
 207 #define PLLLOCK_CMP_EN                          BIT(0)
 208
 209 /* EMAC_QSERDES_COM_DEC_START1 */
 210 #define DEC_START1_MUX                          BIT(7)
 211 #define DEC_START1(x)                           ((x) & 0x7f)
 212
 213 /* EMAC_QSERDES_COM_DIV_FRAC_START1 * EMAC_QSERDES_COM_DIV_FRAC_START2 */
 214 #define DIV_FRAC_START_MUX                      BIT(7)
 215 #define DIV_FRAC_START(x)                       ((x) & 0x7f)
 216
 217 /* EMAC_QSERDES_COM_DIV_FRAC_START3 */
 218 #define DIV_FRAC_START3_MUX                     BIT(4)
 219 #define DIV_FRAC_START3(x)                      ((x) & 0xf)
 220
 221 /* EMAC_QSERDES_COM_DEC_START2 */
 222 #define DEC_START2_MUX                          BIT(1)
 223 #define DEC_START2                              BIT(0)
 224
 225 /* EMAC_QSERDES_COM_RESET_SM */
 226 #define READY                                   BIT(5)
 227
 228 /* EMAC_QSERDES_TX_TX_EMP_POST1_LVL */
 229 #define TX_EMP_POST1_LVL_MUX                    BIT(5)
 230 #define TX_EMP_POST1_LVL(x)                     ((x) & 0x1f)
 231 #define TX_EMP_POST1_LVL_BMSK                   0x1f
 232 #define TX_EMP_POST1_LVL_SHFT                   0
 233
 234 /* EMAC_QSERDES_TX_TX_DRV_LVL */
 235 #define TX_DRV_LVL_MUX                          BIT(4)
 236 #define TX_DRV_LVL(x)                           ((x) & 0xf)
 237
 238 /* EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN */
 239 #define EMP_EN_MUX                              BIT(1)
 240 #define EMP_EN                                  BIT(0)
 241
 242 /* EMAC_QSERDES_RX_CDR_CONTROL & EMAC_QSERDES_RX_CDR_CONTROL2 */
 243 #define HBW_PD_EN                               BIT(7)
 244 #define SECONDORDERENABLE                       BIT(6)
 245 #define FIRSTORDER_THRESH(x)                    (((x) & 0x7) << 3)
 246 #define SECONDORDERGAIN(x)                      ((x) & 0x7)
 247
 248 /* EMAC_QSERDES_RX_RX_EQ_GAIN12 */
 249 #define RX_EQ_GAIN2(x)                          (((x) & 0xf) << 4)
 250 #define RX_EQ_GAIN1(x)                          ((x) & 0xf)
 251
 252 /* EMAC_SGMII_PHY_SERDES_START */
 253 #define SERDES_START                            BIT(0)
 254
 255 /* EMAC_SGMII_PHY_CMN_PWR_CTRL */
 256 #define BIAS_EN                                 BIT(6)
 257 #define PLL_EN                                  BIT(5)
 258 #define SYSCLK_EN                               BIT(4)
 259 #define CLKBUF_L_EN                             BIT(3)
 260 #define PLL_TXCLK_EN                            BIT(1)
 261 #define PLL_RXCLK_EN                            BIT(0)
 262
 263 /* EMAC_SGMII_PHY_RX_PWR_CTRL */
 264 #define L0_RX_SIGDET_EN                         BIT(7)
 265 #define L0_RX_TERM_MODE(x)                      (((x) & 3) << 4)
 266 #define L0_RX_I_EN                              BIT(1)
 267
 268 /* EMAC_SGMII_PHY_TX_PWR_CTRL */
 269 #define L0_TX_EN                                BIT(5)
 270 #define L0_CLKBUF_EN                            BIT(4)
 271 #define L0_TRAN_BIAS_EN                         BIT(1)
 272
 273 /* EMAC_SGMII_PHY_LANE_CTRL1 */
 274 #define L0_RX_EQUALIZE_ENABLE                   BIT(6)
 275 #define L0_RESET_TSYNC_EN                       BIT(4)
 276 #define L0_DRV_LVL(x)                           ((x) & 0xf)
 277
 278 /* EMAC_SGMII_PHY_AUTONEG_CFG2 */
 279 #define FORCE_AN_TX_CFG                         BIT(5)
 280 #define FORCE_AN_RX_CFG                         BIT(4)
 281 #define AN_ENABLE                               BIT(0)
 282
 283 /* EMAC_SGMII_PHY_SPEED_CFG1 */
 284 #define DUPLEX_MODE                             BIT(4)
 285 #define SPDMODE_1000                            BIT(1)
 286 #define SPDMODE_100                             BIT(0)
 287 #define SPDMODE_10                              0
 288 #define SPDMODE_BMSK                            3
 289 #define SPDMODE_SHFT                            0
 290
 291 /* EMAC_SGMII_PHY_POW_DWN_CTRL0 */
 292 #define PWRDN_B                                 BIT(0)
 293 #define CDR_MAX_CNT(x)                          ((x) & 0xff)
 294
 295 /* EMAC_QSERDES_TX_BIST_MODE_LANENO */
 296 #define BIST_LANE_NUMBER(x)                     (((x) & 3) << 5)
 297 #define BISTMODE(x)                             ((x) & 0x1f)
 298
 299 /* EMAC_QSERDES_COM_PLLLOCK_CMPx */
 300 #define PLLLOCK_CMP(x)                          ((x) & 0xff)
 301
 302 /* EMAC_SGMII_PHY_RESET_CTRL */
 303 #define PHY_SW_RESET                            BIT(0)
 304
 305 /* EMAC_SGMII_PHY_IRQ_CMD */
 306 #define IRQ_GLOBAL_CLEAR                        BIT(0)
 307
 308 /* EMAC_SGMII_PHY_INTERRUPT_MASK */
 309 #define DECODE_CODE_ERR                         BIT(7)
 310 #define DECODE_DISP_ERR                         BIT(6)
 311 #define PLL_UNLOCK                              BIT(5)
 312 #define AN_ILLEGAL_TERM                         BIT(4)
 313 #define SYNC_FAIL                               BIT(3)
 314 #define AN_START                                BIT(2)
 315 #define AN_END                                  BIT(1)
 316 #define AN_REQUEST                              BIT(0)
 317
 318 #define SGMII_PHY_IRQ_CLR_WAIT_TIME             10
 319
 320 #define SGMII_PHY_INTERRUPT_ERR (\
 321         DECODE_CODE_ERR         |\
 322         DECODE_DISP_ERR)
 323
 324 #define SGMII_ISR_AN_MASK       (\
 325         AN_REQUEST              |\
 326         AN_START                |\
 327         AN_END                  |\
 328         AN_ILLEGAL_TERM         |\
 329         PLL_UNLOCK              |\
 330         SYNC_FAIL)
 331
 332 #define SGMII_ISR_MASK          (\
 333         SGMII_PHY_INTERRUPT_ERR |\
 334         SGMII_ISR_AN_MASK)
 335
 336 /* SGMII TX_CONFIG */
 337 #define TXCFG_LINK                              0x8000
 338 #define TXCFG_MODE_BMSK                         0x1c00
 339 #define TXCFG_1000_FULL                         0x1800
 340 #define TXCFG_100_FULL                          0x1400
 341 #define TXCFG_100_HALF                          0x0400
 342 #define TXCFG_10_FULL                           0x1000
 343 #define TXCFG_10_HALF                           0x0000
 344
 345 #define SERDES_START_WAIT_TIMES                 100
 346
 347 struct emac_reg_write {
 348         unsigned int offset;
 349         u32 val;
 350 };
 351
 352 static void emac_reg_write_all(void __iomem *base,
 353                                const struct emac_reg_write *itr, size_t size)
 354 {
 355         size_t i;
 356
 357         for (i = 0; i < size; ++itr, ++i)
 358                 writel(itr->val, base + itr->offset);
 359 }
 360
 361 static const struct emac_reg_write physical_coding_sublayer_programming_v1[] = {
 362         {EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
 363         {EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
 364         {EMAC_SGMII_PHY_CMN_PWR_CTRL,
 365                 BIAS_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
 366         {EMAC_SGMII_PHY_TX_PWR_CTRL, L0_TX_EN | L0_CLKBUF_EN | L0_TRAN_BIAS_EN},
 367         {EMAC_SGMII_PHY_RX_PWR_CTRL,
 368                 L0_RX_SIGDET_EN | L0_RX_TERM_MODE(1) | L0_RX_I_EN},
 369         {EMAC_SGMII_PHY_CMN_PWR_CTRL,
 370                 BIAS_EN | PLL_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN |
 371                 PLL_RXCLK_EN},
 372         {EMAC_SGMII_PHY_LANE_CTRL1,
 373                 L0_RX_EQUALIZE_ENABLE | L0_RESET_TSYNC_EN | L0_DRV_LVL(15)},
 374 };
 375
 376 static const struct emac_reg_write sysclk_refclk_setting[] = {
 377         {EMAC_QSERDES_COM_SYSCLK_EN_SEL, SYSCLK_SEL_CMOS},
 378         {EMAC_QSERDES_COM_SYS_CLK_CTRL, SYSCLK_CM | SYSCLK_AC_COUPLE},
 379 };
 380
 381 static const struct emac_reg_write pll_setting[] = {
 382         {EMAC_QSERDES_COM_PLL_IP_SETI, PLL_IPSETI(1)},
 383         {EMAC_QSERDES_COM_PLL_CP_SETI, PLL_CPSETI(59)},
 384         {EMAC_QSERDES_COM_PLL_IP_SETP, PLL_IPSETP(10)},
 385         {EMAC_QSERDES_COM_PLL_CP_SETP, PLL_CPSETP(9)},
 386         {EMAC_QSERDES_COM_PLL_CRCTRL, PLL_RCTRL(15) | PLL_CCTRL(11)},
 387         {EMAC_QSERDES_COM_PLL_CNTRL, OCP_EN | PLL_DIV_FFEN | PLL_DIV_ORD},
 388         {EMAC_QSERDES_COM_DEC_START1, DEC_START1_MUX | DEC_START1(2)},
 389         {EMAC_QSERDES_COM_DEC_START2, DEC_START2_MUX | DEC_START2},
 390         {EMAC_QSERDES_COM_DIV_FRAC_START1,
 391                 DIV_FRAC_START_MUX | DIV_FRAC_START(85)},
 392         {EMAC_QSERDES_COM_DIV_FRAC_START2,
 393                 DIV_FRAC_START_MUX | DIV_FRAC_START(42)},
 394         {EMAC_QSERDES_COM_DIV_FRAC_START3,
 395                 DIV_FRAC_START3_MUX | DIV_FRAC_START3(3)},
 396         {EMAC_QSERDES_COM_PLLLOCK_CMP1, PLLLOCK_CMP(43)},
 397         {EMAC_QSERDES_COM_PLLLOCK_CMP2, PLLLOCK_CMP(104)},
 398         {EMAC_QSERDES_COM_PLLLOCK_CMP3, PLLLOCK_CMP(0)},
 399         {EMAC_QSERDES_COM_PLLLOCK_CMP_EN, PLLLOCK_CMP_EN},
 400         {EMAC_QSERDES_COM_RESETSM_CNTRL, FRQ_TUNE_MODE},
 401 };
 402
 403 static const struct emac_reg_write cdr_setting[] = {
 404         {EMAC_QSERDES_RX_CDR_CONTROL,
 405                 SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(2)},
 406         {EMAC_QSERDES_RX_CDR_CONTROL2,
 407                 SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(4)},
 408 };
 409
 410 static const struct emac_reg_write tx_rx_setting[] = {
 411         {EMAC_QSERDES_TX_BIST_MODE_LANENO, 0},
 412         {EMAC_QSERDES_TX_TX_DRV_LVL, TX_DRV_LVL_MUX | TX_DRV_LVL(15)},
 413         {EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN, EMP_EN_MUX | EMP_EN},
 414         {EMAC_QSERDES_TX_TX_EMP_POST1_LVL,
 415                 TX_EMP_POST1_LVL_MUX | TX_EMP_POST1_LVL(1)},
 416         {EMAC_QSERDES_RX_RX_EQ_GAIN12, RX_EQ_GAIN2(15) | RX_EQ_GAIN1(15)},
 417         {EMAC_QSERDES_TX_LANE_MODE, LANE_MODE(8)},
 418 };
 419
 420 static const struct emac_reg_write sgmii_v2_laned[] = {
 421         /* CDR Settings */
 422         {EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0,
 423                 UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)},
 424         {EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
 425         {EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)},
 426
 427         /* TX/RX Settings */
 428         {EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2},
 429
 430         {EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE},
 431         {EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN},
 432         {EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)},
 433         {EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX},
 434         {EMAC_SGMII_LN_TX_POST, TX_POST_MUX},
 435
 436         {EMAC_SGMII_LN_CML_CTRL_MODE0,
 437                 CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)},
 438         {EMAC_SGMII_LN_MIXER_CTRL_MODE0,
 439                 MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)},
 440         {EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)},
 441         {EMAC_SGMII_LN_SIGDET_ENABLES,
 442                 SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP},
 443         {EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)},
 444
 445         {EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)},
 446         {EMAC_SGMII_LN_RX_MISC_CNTRL0, 0},
 447         {EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV,
 448                 DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)},
 449
 450         {EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
 451         {EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(2)},
 452         {EMAC_SGMII_LN_RX_BAND, BAND_MODE0(3)},
 453         {EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
 454         {EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(3)},
 455         {EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL},
 456 };
 457
 458 static const struct emac_reg_write physical_coding_sublayer_programming_v2[] = {
 459         {EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
 460         {EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
 461         {EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
 462         {EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE},
 463 };
 464
 465 static int emac_sgmii_link_init(struct emac_adapter *adpt)
 466 {
 467         struct phy_device *phydev = adpt->phydev;
 468         struct emac_phy *phy = &adpt->phy;
 469         u32 val;
 470
 471         val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
 472
 473         if (phydev->autoneg == AUTONEG_ENABLE) {
 474                 val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
 475                 val |= AN_ENABLE;
 476                 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
 477         } else {
 478                 u32 speed_cfg;
 479
 480                 switch (phydev->speed) {
 481                 case SPEED_10:
 482                         speed_cfg = SPDMODE_10;
 483                         break;
 484                 case SPEED_100:
 485                         speed_cfg = SPDMODE_100;
 486                         break;
 487                 case SPEED_1000:
 488                         speed_cfg = SPDMODE_1000;
 489                         break;
 490                 default:
 491                         return -EINVAL;
 492                 }
 493
 494                 if (phydev->duplex == DUPLEX_FULL)
 495                         speed_cfg |= DUPLEX_MODE;
 496
 497                 val &= ~AN_ENABLE;
 498                 writel(speed_cfg, phy->base + EMAC_SGMII_PHY_SPEED_CFG1);
 499                 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
 500         }
 501
 502         return 0;
 503 }
 504
 505 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u32 irq_bits)
 506 {
 507         struct emac_phy *phy = &adpt->phy;
 508         u32 status;
 509
 510         writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
 511         writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
 512         /* Ensure interrupt clear command is written to HW */
 513         wmb();
 514
 515         /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
 516          * be confirmed before clearing the bits in other registers.
 517          * It takes a few cycles for hw to clear the interrupt status.
 518          */
 519         if (readl_poll_timeout_atomic(phy->base +
 520                                       EMAC_SGMII_PHY_INTERRUPT_STATUS,
 521                                       status, !(status & irq_bits), 1,
 522                                       SGMII_PHY_IRQ_CLR_WAIT_TIME)) {
 523                 netdev_err(adpt->netdev,
 524                            "error: failed clear SGMII irq: status:0x%x bits:0x%x\n",
 525                            status, irq_bits);
 526                 return -EIO;
 527         }
 528
 529         /* Finalize clearing procedure */
 530         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
 531         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
 532
 533         /* Ensure that clearing procedure finalization is written to HW */
 534         wmb();
 535
 536         return 0;
 537 }
 538
 539 int emac_sgmii_init_v1(struct emac_adapter *adpt)
 540 {
 541         struct emac_phy *phy = &adpt->phy;
 542         unsigned int i;
 543         int ret;
 544
 545         ret = emac_sgmii_link_init(adpt);
 546         if (ret)
 547                 return ret;
 548
 549         emac_reg_write_all(phy->base, physical_coding_sublayer_programming_v1,
 550                            ARRAY_SIZE(physical_coding_sublayer_programming_v1));
 551         emac_reg_write_all(phy->base, sysclk_refclk_setting,
 552                            ARRAY_SIZE(sysclk_refclk_setting));
 553         emac_reg_write_all(phy->base, pll_setting, ARRAY_SIZE(pll_setting));
 554         emac_reg_write_all(phy->base, cdr_setting, ARRAY_SIZE(cdr_setting));
 555         emac_reg_write_all(phy->base, tx_rx_setting,
 556                            ARRAY_SIZE(tx_rx_setting));
 557
 558         /* Power up the Ser/Des engine */
 559         writel(SERDES_START, phy->base + EMAC_SGMII_PHY_SERDES_START);
 560
 561         for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
 562                 if (readl(phy->base + EMAC_QSERDES_COM_RESET_SM) & READY)
 563                         break;
 564                 usleep_range(100, 200);
 565         }
 566
 567         if (i == SERDES_START_WAIT_TIMES) {
 568                 netdev_err(adpt->netdev, "error: ser/des failed to start\n");
 569                 return -EIO;
 570         }
 571         /* Mask out all the SGMII Interrupt */
 572         writel(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
 573
 574         emac_sgmii_irq_clear(adpt, SGMII_PHY_INTERRUPT_ERR);
 575
 576         return 0;
 577 }
 578
 579 int emac_sgmii_init_v2(struct emac_adapter *adpt)
 580 {
 581         struct emac_phy *phy = &adpt->phy;
 582         void __iomem *phy_regs = phy->base;
 583         void __iomem *laned = phy->digital;
 584         unsigned int i;
 585         u32 lnstatus;
 586         int ret;
 587
 588         ret = emac_sgmii_link_init(adpt);
 589         if (ret)
 590                 return ret;
 591
 592         /* PCS lane-x init */
 593         emac_reg_write_all(phy->base, physical_coding_sublayer_programming_v2,
 594                            ARRAY_SIZE(physical_coding_sublayer_programming_v2));
 595
 596         /* SGMII lane-x init */
 597         emac_reg_write_all(phy->digital,
 598                            sgmii_v2_laned, ARRAY_SIZE(sgmii_v2_laned));
 599
 600         /* Power up PCS and start reset lane state machine */
 601
 602         writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
 603         writel(1, laned + SGMII_LN_RSM_START);
 604
 605         /* Wait for c_ready assertion */
 606         for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
 607                 lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS);
 608                 if (lnstatus & BIT(1))
 609                         break;
 610                 usleep_range(100, 200);
 611         }
 612
 613         if (i == SERDES_START_WAIT_TIMES) {
 614                 netdev_err(adpt->netdev, "SGMII failed to start\n");
 615                 return -EIO;
 616         }
 617
 618         /* Disable digital and SERDES loopback */
 619         writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
 620         writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
 621         writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
 622
 623         /* Mask out all the SGMII Interrupt */
 624         writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
 625
 626         emac_sgmii_irq_clear(adpt, SGMII_PHY_INTERRUPT_ERR);
 627
 628         return 0;
 629 }
 630
 631 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
 632 {
 633         struct emac_phy *phy = &adpt->phy;
 634         u32 val;
 635
 636         /* Reset PHY */
 637         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 638         writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
 639                EMAC_EMAC_WRAPPER_CSR2);
 640         /* Ensure phy-reset command is written to HW before the release cmd */
 641         msleep(50);
 642         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 643         writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
 644         /* Ensure phy-reset release command is written to HW before initializing
 645          * SGMII
 646          */
 647         msleep(50);
 648 }
 649
 650 void emac_sgmii_reset(struct emac_adapter *adpt)
 651 {
 652         int ret;
 653
 654         clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000);
 655         emac_sgmii_reset_prepare(adpt);
 656
 657         ret = adpt->phy.initialize(adpt);
 658         if (ret)
 659                 netdev_err(adpt->netdev,
 660                            "could not reinitialize internal PHY (error=%i)\n",
 661                            ret);
 662
 663         clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000);
 664 }
 665
 666 static int emac_sgmii_acpi_match(struct device *dev, void *data)
 667 {
 668         static const struct acpi_device_id match_table[] = {
 669                 {
 670                         .id = "QCOM8071",
 671                         .driver_data = (kernel_ulong_t)emac_sgmii_init_v2,
 672                 },
 673                 {}
 674         };
 675         const struct acpi_device_id *id = acpi_match_device(match_table, dev);
 676         emac_sgmii_initialize *initialize = data;
 677
 678         if (id)
 679                 *initialize = (emac_sgmii_initialize)id->driver_data;
 680
 681         return !!id;
 682 }
 683
 684 static const struct of_device_id emac_sgmii_dt_match[] = {
 685         {
 686                 .compatible = "qcom,fsm9900-emac-sgmii",
 687                 .data = emac_sgmii_init_v1,
 688         },
 689         {
 690                 .compatible = "qcom,qdf2432-emac-sgmii",
 691                 .data = emac_sgmii_init_v2,
 692         },
 693         {}
 694 };
 695
 696 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
 697 {
 698         struct platform_device *sgmii_pdev = NULL;
 699         struct emac_phy *phy = &adpt->phy;
 700         struct resource *res;
 701         int ret;
 702
 703         if (has_acpi_companion(&pdev->dev)) {
 704                 struct device *dev;
 705
 706                 dev = device_find_child(&pdev->dev, &phy->initialize,
 707                                         emac_sgmii_acpi_match);
 708
 709                 if (!dev) {
 710                         dev_err(&pdev->dev, "cannot find internal phy node\n");
 711                         return -ENODEV;
 712                 }
 713
 714                 sgmii_pdev = to_platform_device(dev);
 715         } else {
 716                 const struct of_device_id *match;
 717                 struct device_node *np;
 718
 719                 np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
 720                 if (!np) {
 721                         dev_err(&pdev->dev, "missing internal-phy property\n");
 722                         return -ENODEV;
 723                 }
 724
 725                 sgmii_pdev = of_find_device_by_node(np);
 726                 if (!sgmii_pdev) {
 727                         dev_err(&pdev->dev, "invalid internal-phy property\n");
 728                         return -ENODEV;
 729                 }
 730
 731                 match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
 732                 if (!match) {
 733                         dev_err(&pdev->dev, "unrecognized internal phy node\n");
 734                         ret = -ENODEV;
 735                         goto error_put_device;
 736                 }
 737
 738                 phy->initialize = (emac_sgmii_initialize)match->data;
 739         }
 740
 741         /* Base address is the first address */
 742         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
 743         if (!res) {
 744                 ret = -EINVAL;
 745                 goto error_put_device;
 746         }
 747
 748         phy->base = ioremap(res->start, resource_size(res));
 749         if (!phy->base) {
 750                 ret = -ENOMEM;
 751                 goto error_put_device;
 752         }
 753
 754         /* v2 SGMII has a per-lane digital digital, so parse it if it exists */
 755         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1);
 756         if (res) {
 757                 phy->digital = ioremap(res->start, resource_size(res));
 758                 if (!phy->digital) {
 759                         ret = -ENOMEM;
 760                         goto error_unmap_base;
 761                 }
 762         }
 763
 764         ret = phy->initialize(adpt);
 765         if (ret)
 766                 goto error;
 767
 768         /* We've remapped the addresses, so we don't need the device any
 769          * more.  of_find_device_by_node() says we should release it.
 770          */
 771         put_device(&sgmii_pdev->dev);
 772
 773         return 0;
 774
 775 error:
 776         if (phy->digital)
 777                 iounmap(phy->digital);
 778 error_unmap_base:
 779         iounmap(phy->base);
 780 error_put_device:
 781         put_device(&sgmii_pdev->dev);
 782
 783         return ret;
 784 }