1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
16 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/acpi.h>
19 #include <linux/of_device.h>
22 #include "emac-sgmii.h"
24 /* EMAC_SGMII register offsets */
25 #define EMAC_SGMII_PHY_AUTONEG_CFG2 0x0048
26 #define EMAC_SGMII_PHY_SPEED_CFG1 0x0074
27 #define EMAC_SGMII_PHY_IRQ_CMD 0x00ac
28 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR 0x00b0
29 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
30 #define EMAC_SGMII_PHY_INTERRUPT_STATUS 0x00b8
31 #define EMAC_SGMII_PHY_RX_CHK_STATUS 0x00d4
33 #define FORCE_AN_TX_CFG BIT(5)
34 #define FORCE_AN_RX_CFG BIT(4)
35 #define AN_ENABLE BIT(0)
37 #define DUPLEX_MODE BIT(4)
38 #define SPDMODE_1000 BIT(1)
39 #define SPDMODE_100 BIT(0)
42 #define CDR_ALIGN_DET BIT(6)
44 #define IRQ_GLOBAL_CLEAR BIT(0)
46 #define DECODE_CODE_ERR BIT(7)
47 #define DECODE_DISP_ERR BIT(6)
49 #define SGMII_PHY_IRQ_CLR_WAIT_TIME 10
51 #define SGMII_PHY_INTERRUPT_ERR (DECODE_CODE_ERR | DECODE_DISP_ERR)
52 #define SGMII_ISR_MASK (SGMII_PHY_INTERRUPT_ERR)
54 #define SERDES_START_WAIT_TIMES 100
56 int emac_sgmii_init(struct emac_adapter *adpt)
58 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->init))
61 return adpt->phy.sgmii_ops->init(adpt);
64 int emac_sgmii_open(struct emac_adapter *adpt)
66 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->open))
69 return adpt->phy.sgmii_ops->open(adpt);
72 void emac_sgmii_close(struct emac_adapter *adpt)
74 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->close))
77 adpt->phy.sgmii_ops->close(adpt);
80 int emac_sgmii_link_change(struct emac_adapter *adpt, bool link_state)
82 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->link_change))
85 return adpt->phy.sgmii_ops->link_change(adpt, link_state);
88 void emac_sgmii_reset(struct emac_adapter *adpt)
90 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->reset))
93 adpt->phy.sgmii_ops->reset(adpt);
96 /* Initialize the SGMII link between the internal and external PHYs. */
97 static void emac_sgmii_link_init(struct emac_adapter *adpt)
99 struct emac_sgmii *phy = &adpt->phy;
102 /* Always use autonegotiation. It works no matter how the external
105 val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
106 val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
108 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
111 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u8 irq_bits)
113 struct emac_sgmii *phy = &adpt->phy;
116 writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
117 writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
118 /* Ensure interrupt clear command is written to HW */
121 /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
122 * be confirmed before clearing the bits in other registers.
123 * It takes a few cycles for hw to clear the interrupt status.
125 if (readl_poll_timeout_atomic(phy->base +
126 EMAC_SGMII_PHY_INTERRUPT_STATUS,
127 status, !(status & irq_bits), 1,
128 SGMII_PHY_IRQ_CLR_WAIT_TIME)) {
129 net_err_ratelimited("%s: failed to clear SGMII irq: status:0x%x bits:0x%x\n",
130 adpt->netdev->name, status, irq_bits);
134 /* Finalize clearing procedure */
135 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
136 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
138 /* Ensure that clearing procedure finalization is written to HW */
144 /* The number of decode errors that triggers a reset */
145 #define DECODE_ERROR_LIMIT 2
147 static irqreturn_t emac_sgmii_interrupt(int irq, void *data)
149 struct emac_adapter *adpt = data;
150 struct emac_sgmii *phy = &adpt->phy;
153 status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS);
154 status &= SGMII_ISR_MASK;
158 /* If we get a decoding error and CDR is not locked, then try
159 * resetting the internal PHY. The internal PHY uses an embedded
160 * clock with Clock and Data Recovery (CDR) to recover the
163 if (status & SGMII_PHY_INTERRUPT_ERR) {
166 /* The SGMII is capable of recovering from some decode
167 * errors automatically. However, if we get multiple
168 * decode errors in a row, then assume that something
169 * is wrong and reset the interface.
171 count = atomic_inc_return(&phy->decode_error_count);
172 if (count == DECODE_ERROR_LIMIT) {
173 schedule_work(&adpt->work_thread);
174 atomic_set(&phy->decode_error_count, 0);
177 /* We only care about consecutive decode errors. */
178 atomic_set(&phy->decode_error_count, 0);
181 if (emac_sgmii_irq_clear(adpt, status))
182 schedule_work(&adpt->work_thread);
187 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
189 struct emac_sgmii *phy = &adpt->phy;
193 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
194 writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
195 EMAC_EMAC_WRAPPER_CSR2);
196 /* Ensure phy-reset command is written to HW before the release cmd */
198 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
199 writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
200 /* Ensure phy-reset release command is written to HW before initializing
206 static void emac_sgmii_common_reset(struct emac_adapter *adpt)
210 emac_sgmii_reset_prepare(adpt);
211 emac_sgmii_link_init(adpt);
213 ret = emac_sgmii_init(adpt);
215 netdev_err(adpt->netdev,
216 "could not reinitialize internal PHY (error=%i)\n",
220 static int emac_sgmii_common_open(struct emac_adapter *adpt)
222 struct emac_sgmii *sgmii = &adpt->phy;
226 /* Make sure interrupts are cleared and disabled first */
227 ret = emac_sgmii_irq_clear(adpt, 0xff);
230 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
232 ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0,
235 netdev_err(adpt->netdev,
236 "could not register handler for internal PHY\n");
244 static void emac_sgmii_common_close(struct emac_adapter *adpt)
246 struct emac_sgmii *sgmii = &adpt->phy;
248 /* Make sure interrupts are disabled */
249 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
250 free_irq(sgmii->irq, adpt);
253 /* The error interrupts are only valid after the link is up */
254 static int emac_sgmii_common_link_change(struct emac_adapter *adpt, bool linkup)
256 struct emac_sgmii *sgmii = &adpt->phy;
260 /* Clear and enable interrupts */
261 ret = emac_sgmii_irq_clear(adpt, 0xff);
265 writel(SGMII_ISR_MASK,
266 sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
268 /* Disable interrupts */
269 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
270 synchronize_irq(sgmii->irq);
276 static struct sgmii_ops fsm9900_ops = {
277 .init = emac_sgmii_init_fsm9900,
278 .open = emac_sgmii_common_open,
279 .close = emac_sgmii_common_close,
280 .link_change = emac_sgmii_common_link_change,
281 .reset = emac_sgmii_common_reset,
284 static struct sgmii_ops qdf2432_ops = {
285 .init = emac_sgmii_init_qdf2432,
286 .open = emac_sgmii_common_open,
287 .close = emac_sgmii_common_close,
288 .link_change = emac_sgmii_common_link_change,
289 .reset = emac_sgmii_common_reset,
293 static struct sgmii_ops qdf2400_ops = {
294 .init = emac_sgmii_init_qdf2400,
295 .open = emac_sgmii_common_open,
296 .close = emac_sgmii_common_close,
297 .link_change = emac_sgmii_common_link_change,
298 .reset = emac_sgmii_common_reset,
302 static int emac_sgmii_acpi_match(struct device *dev, void *data)
305 static const struct acpi_device_id match_table[] = {
311 const struct acpi_device_id *id = acpi_match_device(match_table, dev);
312 struct sgmii_ops **ops = data;
315 acpi_handle handle = ACPI_HANDLE(dev);
316 unsigned long long hrv;
319 status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
321 if (status == AE_NOT_FOUND)
322 /* Older versions of the QDF2432 ACPI tables do
323 * not have an _HRV property.
327 /* Something is wrong with the tables */
345 static const struct of_device_id emac_sgmii_dt_match[] = {
347 .compatible = "qcom,fsm9900-emac-sgmii",
348 .data = &fsm9900_ops,
351 .compatible = "qcom,qdf2432-emac-sgmii",
352 .data = &qdf2432_ops,
357 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
359 struct platform_device *sgmii_pdev = NULL;
360 struct emac_sgmii *phy = &adpt->phy;
361 struct resource *res;
364 if (has_acpi_companion(&pdev->dev)) {
367 dev = device_find_child(&pdev->dev, &phy->sgmii_ops,
368 emac_sgmii_acpi_match);
371 dev_warn(&pdev->dev, "cannot find internal phy node\n");
375 sgmii_pdev = to_platform_device(dev);
377 const struct of_device_id *match;
378 struct device_node *np;
380 np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
382 dev_err(&pdev->dev, "missing internal-phy property\n");
386 sgmii_pdev = of_find_device_by_node(np);
389 dev_err(&pdev->dev, "invalid internal-phy property\n");
393 match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
395 dev_err(&pdev->dev, "unrecognized internal phy node\n");
397 goto error_put_device;
400 phy->sgmii_ops = (struct sgmii_ops *)match->data;
403 /* Base address is the first address */
404 res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
407 goto error_put_device;
410 phy->base = ioremap(res->start, resource_size(res));
413 goto error_put_device;
416 /* v2 SGMII has a per-lane digital digital, so parse it if it exists */
417 res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1);
419 phy->digital = ioremap(res->start, resource_size(res));
422 goto error_unmap_base;
426 ret = emac_sgmii_init(adpt);
430 emac_sgmii_link_init(adpt);
432 ret = platform_get_irq(sgmii_pdev, 0);
436 /* We've remapped the addresses, so we don't need the device any
437 * more. of_find_device_by_node() says we should release it.
439 put_device(&sgmii_pdev->dev);
445 iounmap(phy->digital);
449 put_device(&sgmii_pdev->dev);