drivers/net/ethernet/qualcomm/emac/emac.h

   1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #ifndef _EMAC_H_
  14 #define _EMAC_H_
  15
  16 #include <linux/irqreturn.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/clk.h>
  19 #include <linux/platform_device.h>
  20 #include "emac-mac.h"
  21 #include "emac-phy.h"
  22
  23 /* EMAC base register offsets */
  24 #define EMAC_DMA_MAS_CTRL                                     0x001400
  25 #define EMAC_IRQ_MOD_TIM_INIT                                 0x001408
  26 #define EMAC_BLK_IDLE_STS                                     0x00140c
  27 #define EMAC_PHY_LINK_DELAY                                   0x00141c
  28 #define EMAC_SYS_ALIV_CTRL                                    0x001434
  29 #define EMAC_MAC_IPGIFG_CTRL                                  0x001484
  30 #define EMAC_MAC_STA_ADDR0                                    0x001488
  31 #define EMAC_MAC_STA_ADDR1                                    0x00148c
  32 #define EMAC_HASH_TAB_REG0                                    0x001490
  33 #define EMAC_HASH_TAB_REG1                                    0x001494
  34 #define EMAC_MAC_HALF_DPLX_CTRL                               0x001498
  35 #define EMAC_MAX_FRAM_LEN_CTRL                                0x00149c
  36 #define EMAC_INT_STATUS                                       0x001600
  37 #define EMAC_INT_MASK                                         0x001604
  38 #define EMAC_RXMAC_STATC_REG0                                 0x001700
  39 #define EMAC_RXMAC_STATC_REG22                                0x001758
  40 #define EMAC_TXMAC_STATC_REG0                                 0x001760
  41 #define EMAC_TXMAC_STATC_REG24                                0x0017c0
  42 #define EMAC_CORE_HW_VERSION                                  0x001974
  43 #define EMAC_IDT_TABLE0                                       0x001b00
  44 #define EMAC_RXMAC_STATC_REG23                                0x001bc8
  45 #define EMAC_RXMAC_STATC_REG24                                0x001bcc
  46 #define EMAC_TXMAC_STATC_REG25                                0x001bd0
  47 #define EMAC_INT1_MASK                                        0x001bf0
  48 #define EMAC_INT1_STATUS                                      0x001bf4
  49 #define EMAC_INT2_MASK                                        0x001bf8
  50 #define EMAC_INT2_STATUS                                      0x001bfc
  51 #define EMAC_INT3_MASK                                        0x001c00
  52 #define EMAC_INT3_STATUS                                      0x001c04
  53
  54 /* EMAC_DMA_MAS_CTRL */
  55 #define DEV_ID_NUM_BMSK                                     0x7f000000
  56 #define DEV_ID_NUM_SHFT                                             24
  57 #define DEV_REV_NUM_BMSK                                      0xff0000
  58 #define DEV_REV_NUM_SHFT                                            16
  59 #define INT_RD_CLR_EN                                           0x4000
  60 #define IRQ_MODERATOR2_EN                                        0x800
  61 #define IRQ_MODERATOR_EN                                         0x400
  62 #define LPW_CLK_SEL                                               0x80
  63 #define LPW_STATE                                                 0x20
  64 #define LPW_MODE                                                  0x10
  65 #define SOFT_RST                                                   0x1
  66
  67 /* EMAC_IRQ_MOD_TIM_INIT */
  68 #define IRQ_MODERATOR2_INIT_BMSK                            0xffff0000
  69 #define IRQ_MODERATOR2_INIT_SHFT                                    16
  70 #define IRQ_MODERATOR_INIT_BMSK                                 0xffff
  71 #define IRQ_MODERATOR_INIT_SHFT                                      0
  72
  73 /* EMAC_INT_STATUS */
  74 #define DIS_INT                                                BIT(31)
  75 #define PTP_INT                                                BIT(30)
  76 #define RFD4_UR_INT                                            BIT(29)
  77 #define TX_PKT_INT3                                            BIT(26)
  78 #define TX_PKT_INT2                                            BIT(25)
  79 #define TX_PKT_INT1                                            BIT(24)
  80 #define RX_PKT_INT3                                            BIT(19)
  81 #define RX_PKT_INT2                                            BIT(18)
  82 #define RX_PKT_INT1                                            BIT(17)
  83 #define RX_PKT_INT0                                            BIT(16)
  84 #define TX_PKT_INT                                             BIT(15)
  85 #define TXQ_TO_INT                                             BIT(14)
  86 #define GPHY_WAKEUP_INT                                        BIT(13)
  87 #define GPHY_LINK_DOWN_INT                                     BIT(12)
  88 #define GPHY_LINK_UP_INT                                       BIT(11)
  89 #define DMAW_TO_INT                                            BIT(10)
  90 #define DMAR_TO_INT                                             BIT(9)
  91 #define TXF_UR_INT                                              BIT(8)
  92 #define RFD3_UR_INT                                             BIT(7)
  93 #define RFD2_UR_INT                                             BIT(6)
  94 #define RFD1_UR_INT                                             BIT(5)
  95 #define RFD0_UR_INT                                             BIT(4)
  96 #define RXF_OF_INT                                              BIT(3)
  97 #define SW_MAN_INT                                              BIT(2)
  98
  99 /* EMAC_MAILBOX_6 */
 100 #define RFD2_PROC_IDX_BMSK                                   0xfff0000
 101 #define RFD2_PROC_IDX_SHFT                                          16
 102 #define RFD2_PROD_IDX_BMSK                                       0xfff
 103 #define RFD2_PROD_IDX_SHFT                                           0
 104
 105 /* EMAC_CORE_HW_VERSION */
 106 #define MAJOR_BMSK                                          0xf0000000
 107 #define MAJOR_SHFT                                                  28
 108 #define MINOR_BMSK                                           0xfff0000
 109 #define MINOR_SHFT                                                  16
 110 #define STEP_BMSK                                               0xffff
 111 #define STEP_SHFT                                                    0
 112
 113 /* EMAC_EMAC_WRAPPER_CSR1 */
 114 #define TX_INDX_FIFO_SYNC_RST                                  BIT(23)
 115 #define TX_TS_FIFO_SYNC_RST                                    BIT(22)
 116 #define RX_TS_FIFO2_SYNC_RST                                   BIT(21)
 117 #define RX_TS_FIFO1_SYNC_RST                                   BIT(20)
 118 #define TX_TS_ENABLE                                           BIT(16)
 119 #define DIS_1588_CLKS                                          BIT(11)
 120 #define FREQ_MODE                                               BIT(9)
 121 #define ENABLE_RRD_TIMESTAMP                                    BIT(3)
 122
 123 /* EMAC_EMAC_WRAPPER_CSR2 */
 124 #define HDRIVE_BMSK                                             0x3000
 125 #define HDRIVE_SHFT                                                 12
 126 #define SLB_EN                                                  BIT(9)
 127 #define PLB_EN                                                  BIT(8)
 128 #define WOL_EN                                                  BIT(3)
 129 #define PHY_RESET                                               BIT(0)
 130
 131 #define EMAC_DEV_ID                                             0x0040
 132
 133 /* SGMII v2 per lane registers */
 134 #define SGMII_LN_RSM_START             0x029C
 135
 136 /* SGMII v2 PHY common registers */
 137 #define SGMII_PHY_CMN_CTRL            0x0408
 138 #define SGMII_PHY_CMN_RESET_CTRL      0x0410
 139
 140 /* SGMII v2 PHY registers per lane */
 141 #define SGMII_PHY_LN_OFFSET          0x0400
 142 #define SGMII_PHY_LN_LANE_STATUS     0x00DC
 143 #define SGMII_PHY_LN_BIST_GEN0       0x008C
 144 #define SGMII_PHY_LN_BIST_GEN1       0x0090
 145 #define SGMII_PHY_LN_BIST_GEN2       0x0094
 146 #define SGMII_PHY_LN_BIST_GEN3       0x0098
 147 #define SGMII_PHY_LN_CDR_CTRL1       0x005C
 148
 149 enum emac_clk_id {
 150         EMAC_CLK_AXI,
 151         EMAC_CLK_CFG_AHB,
 152         EMAC_CLK_HIGH_SPEED,
 153         EMAC_CLK_MDIO,
 154         EMAC_CLK_TX,
 155         EMAC_CLK_RX,
 156         EMAC_CLK_SYS,
 157         EMAC_CLK_CNT
 158 };
 159
 160 #define EMAC_LINK_SPEED_UNKNOWN                                    0x0
 161 #define EMAC_LINK_SPEED_10_HALF                                 BIT(0)
 162 #define EMAC_LINK_SPEED_10_FULL                                 BIT(1)
 163 #define EMAC_LINK_SPEED_100_HALF                                BIT(2)
 164 #define EMAC_LINK_SPEED_100_FULL                                BIT(3)
 165 #define EMAC_LINK_SPEED_1GB_FULL                                BIT(5)
 166
 167 #define EMAC_MAX_SETUP_LNK_CYCLE                                   100
 168
 169 /* Wake On Lan */
 170 #define EMAC_WOL_PHY                     0x00000001 /* PHY Status Change */
 171 #define EMAC_WOL_MAGIC                   0x00000002 /* Magic Packet */
 172
 173 struct emac_stats {
 174         /* rx */
 175         u64 rx_ok;              /* good packets */
 176         u64 rx_bcast;           /* good broadcast packets */
 177         u64 rx_mcast;           /* good multicast packets */
 178         u64 rx_pause;           /* pause packet */
 179         u64 rx_ctrl;            /* control packets other than pause frame. */
 180         u64 rx_fcs_err;         /* packets with bad FCS. */
 181         u64 rx_len_err;         /* packets with length mismatch */
 182         u64 rx_byte_cnt;        /* good bytes count (without FCS) */
 183         u64 rx_runt;            /* runt packets */
 184         u64 rx_frag;            /* fragment count */
 185         u64 rx_sz_64;           /* packets that are 64 bytes */
 186         u64 rx_sz_65_127;       /* packets that are 65-127 bytes */
 187         u64 rx_sz_128_255;      /* packets that are 128-255 bytes */
 188         u64 rx_sz_256_511;      /* packets that are 256-511 bytes */
 189         u64 rx_sz_512_1023;     /* packets that are 512-1023 bytes */
 190         u64 rx_sz_1024_1518;    /* packets that are 1024-1518 bytes */
 191         u64 rx_sz_1519_max;     /* packets that are 1519-MTU bytes*/
 192         u64 rx_sz_ov;           /* packets that are >MTU bytes (truncated) */
 193         u64 rx_rxf_ov;          /* packets dropped due to RX FIFO overflow */
 194         u64 rx_align_err;       /* alignment errors */
 195         u64 rx_bcast_byte_cnt;  /* broadcast packets byte count (without FCS) */
 196         u64 rx_mcast_byte_cnt;  /* multicast packets byte count (without FCS) */
 197         u64 rx_err_addr;        /* packets dropped due to address filtering */
 198         u64 rx_crc_align;       /* CRC align errors */
 199         u64 rx_jabbers;         /* jabbers */
 200
 201         /* tx */
 202         u64 tx_ok;              /* good packets */
 203         u64 tx_bcast;           /* good broadcast packets */
 204         u64 tx_mcast;           /* good multicast packets */
 205         u64 tx_pause;           /* pause packets */
 206         u64 tx_exc_defer;       /* packets with excessive deferral */
 207         u64 tx_ctrl;            /* control packets other than pause frame */
 208         u64 tx_defer;           /* packets that are deferred. */
 209         u64 tx_byte_cnt;        /* good bytes count (without FCS) */
 210         u64 tx_sz_64;           /* packets that are 64 bytes */
 211         u64 tx_sz_65_127;       /* packets that are 65-127 bytes */
 212         u64 tx_sz_128_255;      /* packets that are 128-255 bytes */
 213         u64 tx_sz_256_511;      /* packets that are 256-511 bytes */
 214         u64 tx_sz_512_1023;     /* packets that are 512-1023 bytes */
 215         u64 tx_sz_1024_1518;    /* packets that are 1024-1518 bytes */
 216         u64 tx_sz_1519_max;     /* packets that are 1519-MTU bytes */
 217         u64 tx_1_col;           /* packets single prior collision */
 218         u64 tx_2_col;           /* packets with multiple prior collisions */
 219         u64 tx_late_col;        /* packets with late collisions */
 220         u64 tx_abort_col;       /* packets aborted due to excess collisions */
 221         u64 tx_underrun;        /* packets aborted due to FIFO underrun */
 222         u64 tx_rd_eop;          /* count of reads beyond EOP */
 223         u64 tx_len_err;         /* packets with length mismatch */
 224         u64 tx_trunc;           /* packets truncated due to size >MTU */
 225         u64 tx_bcast_byte;      /* broadcast packets byte count (without FCS) */
 226         u64 tx_mcast_byte;      /* multicast packets byte count (without FCS) */
 227         u64 tx_col;             /* collisions */
 228
 229         spinlock_t lock;        /* prevent multiple simultaneous readers */
 230 };
 231
 232 /* RSS hstype Definitions */
 233 #define EMAC_RSS_HSTYP_IPV4_EN                              0x00000001
 234 #define EMAC_RSS_HSTYP_TCP4_EN                              0x00000002
 235 #define EMAC_RSS_HSTYP_IPV6_EN                              0x00000004
 236 #define EMAC_RSS_HSTYP_TCP6_EN                              0x00000008
 237 #define EMAC_RSS_HSTYP_ALL_EN (\
 238                 EMAC_RSS_HSTYP_IPV4_EN   |\
 239                 EMAC_RSS_HSTYP_TCP4_EN   |\
 240                 EMAC_RSS_HSTYP_IPV6_EN   |\
 241                 EMAC_RSS_HSTYP_TCP6_EN)
 242
 243 #define EMAC_VLAN_TO_TAG(_vlan, _tag) \
 244                 (_tag =  ((((_vlan) >> 8) & 0xFF) | (((_vlan) & 0xFF) << 8)))
 245
 246 #define EMAC_TAG_TO_VLAN(_tag, _vlan) \
 247                 (_vlan = ((((_tag) >> 8) & 0xFF) | (((_tag) & 0xFF) << 8)))
 248
 249 #define EMAC_DEF_RX_BUF_SIZE                                      1536
 250 #define EMAC_MAX_JUMBO_PKT_SIZE                             (9 * 1024)
 251 #define EMAC_MAX_TX_OFFLOAD_THRESH                          (9 * 1024)
 252
 253 #define EMAC_MAX_ETH_FRAME_SIZE                EMAC_MAX_JUMBO_PKT_SIZE
 254 #define EMAC_MIN_ETH_FRAME_SIZE                                     68
 255
 256 #define EMAC_DEF_TX_QUEUES                                           1
 257 #define EMAC_DEF_RX_QUEUES                                           1
 258
 259 #define EMAC_MIN_TX_DESCS                                          128
 260 #define EMAC_MIN_RX_DESCS                                          128
 261
 262 #define EMAC_MAX_TX_DESCS                                        16383
 263 #define EMAC_MAX_RX_DESCS                                         2047
 264
 265 #define EMAC_DEF_TX_DESCS                                          512
 266 #define EMAC_DEF_RX_DESCS                                          256
 267
 268 #define EMAC_DEF_RX_IRQ_MOD                                        250
 269 #define EMAC_DEF_TX_IRQ_MOD                                        250
 270
 271 #define EMAC_WATCHDOG_TIME                                    (5 * HZ)
 272
 273 /* by default check link every 4 seconds */
 274 #define EMAC_TRY_LINK_TIMEOUT                                 (4 * HZ)
 275
 276 /* emac_irq per-device (per-adapter) irq properties.
 277  * @irq:        irq number.
 278  * @mask        mask to use over status register.
 279  */
 280 struct emac_irq {
 281         unsigned int    irq;
 282         u32             mask;
 283 };
 284
 285 /* The device's main data structure */
 286 struct emac_adapter {
 287         struct net_device               *netdev;
 288         struct mii_bus                  *mii_bus;
 289         struct phy_device               *phydev;
 290
 291         void __iomem                    *base;
 292         void __iomem                    *csr;
 293
 294         struct emac_phy                 phy;
 295         struct emac_stats               stats;
 296
 297         struct emac_irq                 irq;
 298         struct clk                      *clk[EMAC_CLK_CNT];
 299
 300         /* All Descriptor memory */
 301         struct emac_ring_header         ring_header;
 302         struct emac_tx_queue            tx_q;
 303         struct emac_rx_queue            rx_q;
 304         unsigned int                    tx_desc_cnt;
 305         unsigned int                    rx_desc_cnt;
 306         unsigned int                    rrd_size; /* in quad words */
 307         unsigned int                    rfd_size; /* in quad words */
 308         unsigned int                    tpd_size; /* in quad words */
 309
 310         unsigned int                    rxbuf_size;
 311
 312         /* Ring parameter */
 313         u8                              tpd_burst;
 314         u8                              rfd_burst;
 315         unsigned int                    dmaw_dly_cnt;
 316         unsigned int                    dmar_dly_cnt;
 317         enum emac_dma_req_block         dmar_block;
 318         enum emac_dma_req_block         dmaw_block;
 319         enum emac_dma_order             dma_order;
 320
 321         u32                             irq_mod;
 322         u32                             preamble;
 323
 324         struct work_struct              work_thread;
 325
 326         u16                             msg_enable;
 327
 328         struct mutex                    reset_lock;
 329 };
 330
 331 int emac_reinit_locked(struct emac_adapter *adpt);
 332 void emac_reg_update32(void __iomem *addr, u32 mask, u32 val);
 333 irqreturn_t emac_isr(int irq, void *data);
 334
 335 #endif /* _EMAC_H_ */